diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
| commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
| tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /zephyr/boards | |
| parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
| download | chrome-ec-stabilize-14695.107.B-ish.tar.gz | |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'zephyr/boards')
45 files changed, 0 insertions, 3022 deletions
diff --git a/zephyr/boards/arm/brya/Kconfig.board b/zephyr/boards/arm/brya/Kconfig.board deleted file mode 100644 index 8add483941..0000000000 --- a/zephyr/boards/arm/brya/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# "BOARD" below refers to a Zephyr board, which does not have a 1:1 -# mapping with the Chrome OS concept of a board. By Zephyr's -# conventions, we'll still call it "BOARD_*" to make this more -# applicable to be upstreamed, even though this code is shared by all -# projects using Brya baseboard. -config BOARD_BRYA - bool "Google Brya Baseboard" - depends on SOC_NPCX9M3F - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/brya/Kconfig.defconfig b/zephyr/boards/arm/brya/Kconfig.defconfig deleted file mode 100644 index e4de179311..0000000000 --- a/zephyr/boards/arm/brya/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_BRYA - -config BOARD - default "brya" - -endif # BOARD_BRYA diff --git a/zephyr/boards/arm/brya/board.cmake b/zephyr/boards/arm/brya/board.cmake deleted file mode 100644 index 67ade59f57..0000000000 --- a/zephyr/boards/arm/brya/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) - diff --git a/zephyr/boards/arm/brya/brya.dts b/zephyr/boards/arm/brya/brya.dts deleted file mode 100644 index 4ba8704cd2..0000000000 --- a/zephyr/boards/arm/brya/brya.dts +++ /dev/null @@ -1,188 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx9.dtsi> -#include <dt-bindings/gpio_defines.h> -#include <nuvoton/npcx9m3f.dtsi> - -/ { - model = "Google Brya Baseboard"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - i2c_sensor: sensor { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - tcpc0_2 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_USB_C0_C2_TCPC"; - label = "TCPC0,2"; - }; - tcpc1 { - i2c-port = <&i2c4_1>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - label = "TCPC1"; - }; - ppc0_2 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_USB_C0_C2_PPC"; - label = "PPC0,2"; - }; - ppc1 { - i2c-port = <&i2c6_1>; - enum-name = "I2C_PORT_USB_C1_PPC"; - label = "PPC1"; - }; - retimer0_2 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_C0_C2_MUX"; - label = "RETIMER0,2"; - }; - battery { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - eeprom { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - charger { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_CHARGER"; - label = "EEPROM"; - }; - }; - - named-pwms { - compatible = "named-pwms"; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c4_1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl4 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c6_1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl6 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - >; -}; diff --git a/zephyr/boards/arm/brya/brya_defconfig b/zephyr/boards/arm/brya/brya_defconfig deleted file mode 100644 index e8c412a592..0000000000 --- a/zephyr/boards/arm/brya/brya_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX9=y - -# Platform Configuration -CONFIG_SOC_NPCX9M3F=y -CONFIG_BOARD_BRYA=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/herobrine_npcx9/Kconfig.board b/zephyr/boards/arm/herobrine_npcx9/Kconfig.board deleted file mode 100644 index d9e7faf3af..0000000000 --- a/zephyr/boards/arm/herobrine_npcx9/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# "BOARD" below refers to a Zephyr board, which does not have a 1:1 -# mapping with the Chrome OS concept of a board. By Zephyr's -# conventions, we'll still call it "BOARD_*" to make this more -# applicable to be upstreamed, even though this code is shared by all -# projects using Herobrine-NPCX9 baseboard. -config BOARD_HEROBRINE_NPCX9 - bool "Google Herobrine-NPCX9 Baseboard" - depends on SOC_NPCX9M3F - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig b/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig deleted file mode 100644 index 65f3225d91..0000000000 --- a/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_HEROBRINE_NPCX9 - -config BOARD - default "herobrine_npcx9" - -endif # BOARD_HEROBRINE_NPCX9 diff --git a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts deleted file mode 100644 index 34884a8275..0000000000 --- a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx9.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/gpio_defines.h> -#include <dt-bindings/wake_mask_event_defines.h> -#include <nuvoton/npcx9m3f.dtsi> - -/ { - model = "Google Herobrine-NPCX9 Baseboard"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - cros,rtc = &pcf85063a; - }; - - ec-console { - compatible = "ec-console"; - - disabled = "hostcmd"; - }; - - ec-mkbp-host-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <(HOST_EVENT_LID_OPEN | \ - HOST_EVENT_POWER_BUTTON | \ - HOST_EVENT_AC_CONNECTED | \ - HOST_EVENT_AC_DISCONNECTED | \ - HOST_EVENT_HANG_DETECT | \ - HOST_EVENT_RTC | \ - HOST_EVENT_MODE_CHANGE | \ - HOST_EVENT_DEVICE)>; - }; - - ec-mkbp-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \ - MKBP_EVENT_HOST_EVENT | \ - MKBP_EVENT_SENSOR_FIFO)>; - }; - - named-pwms { - compatible = "named-pwms"; - - kblight { - pwms = <&pwm3 0 0>; - label = "KBLIGHT"; - frequency = <10000>; - }; - displight { - pwms = <&pwm5 0 0>; - label = "DISPLIGHT"; - frequency = <4800>; - }; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - vbus { - label = "ADC_VBUS"; - enum-name = "ADC_VBUS"; - channel = <1>; - /* Measure VBUS through a 1/10 voltage divider */ - mul = <10>; - }; - amon_bmon { - label = "ADC_AMON_BMON"; - enum-name = "ADC_AMON_BMON"; - channel = <2>; - /* - * Adapter current output or battery charging/ - * discharging current (uV) 18x amplification on - * charger side. - */ - mul = <1000>; - div = <18>; - }; - psys { - label = "ADC_PSYS"; - enum-name = "ADC_PSYS"; - channel = <3>; - /* - * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, - * to read 0.8V @ 99 W, i.e. 124000 uW/mV. - */ - mul = <124000>; - }; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; -}; - -/* Keyboard backlight */ -&pwm3 { - status = "okay"; -}; - -/* Display backlight */ -&pwm5 { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - >; -}; diff --git a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig deleted file mode 100644 index 907ae9ed34..0000000000 --- a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_SOC_NPCX9M3F=y - -# Platform Configuration -CONFIG_BOARD_HEROBRINE_NPCX9=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/kohaku/Kconfig.board b/zephyr/boards/arm/kohaku/Kconfig.board deleted file mode 100644 index c1a1718847..0000000000 --- a/zephyr/boards/arm/kohaku/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -config BOARD_KOHAKU - bool "Google Kohaku EC" - depends on SOC_NPCX7M6FC - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/kohaku/Kconfig.defconfig b/zephyr/boards/arm/kohaku/Kconfig.defconfig deleted file mode 100644 index 83b97d8ef7..0000000000 --- a/zephyr/boards/arm/kohaku/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_KOHAKU - -config BOARD - default "kohaku" - -endif # BOARD_KOHAKU diff --git a/zephyr/boards/arm/kohaku/board.cmake b/zephyr/boards/arm/kohaku/board.cmake deleted file mode 100644 index a204305534..0000000000 --- a/zephyr/boards/arm/kohaku/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) diff --git a/zephyr/boards/arm/kohaku/kohaku.dts b/zephyr/boards/arm/kohaku/kohaku.dts deleted file mode 100644 index 00e340faea..0000000000 --- a/zephyr/boards/arm/kohaku/kohaku.dts +++ /dev/null @@ -1,418 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx7.dtsi> -#include <dt-bindings/gpio_defines.h> -#include <nuvoton/npcx7m6fc.dtsi> - -/ { - model = "Google Kohaku EC"; - - aliases { - i2c-0 = &i2c0_0; - i2c-1 = &i2c1_0; - i2c-2 = &i2c2_0; - i2c-3 = &i2c3_0; - i2c-5 = &i2c5_0; - i2c-7 = &i2c7_0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - }; - - named-gpios { - compatible = "named-gpios"; - - lid_open { - gpios = <&gpiod 2 GPIO_INPUT>; - enum-name = "GPIO_LID_OPEN"; - label = "LID_OPEN"; - }; - wp_l { - gpios = <&gpioa 1 GPIO_INPUT>; - enum-name = "GPIO_WP_L"; - label = "WP_L"; - }; - power_button_l { - gpios = <&gpio0 1 GPIO_INPUT>; - enum-name = "GPIO_POWER_BUTTON_L"; - label = "POWER_BUTTON_L"; - }; - acok_od { - gpios = <&gpio0 0 GPIO_INPUT>; - enum-name = "GPIO_AC_PRESENT"; - label = "ACOK_OD"; - }; - slp_s0_l { - gpios = <&gpiod 5 GPIO_INPUT>; - enum-name = "GPIO_PCH_SLP_S0_L"; - label = "SLP_S0_L"; - }; - slp_s3_l { - gpios = <&gpioa 5 GPIO_INPUT>; - enum-name = "GPIO_PCH_SLP_S3_L"; - label = "SLP_S3_L"; - }; - slp_s4_l { - gpios = <&gpiod 4 GPIO_INPUT>; - enum-name = "GPIO_PCH_SLP_S4_L"; - label = "SLP_S4_L"; - }; - pg_ec_rsmrst_l { - gpios = <&gpioe 2 GPIO_INPUT>; - enum-name = "GPIO_RSMRST_L_PGOOD"; - label = "PG_EC_RSMRST_L"; - }; - pg_ec_all_sys_pwrgd { - gpios = <&gpiof 4 GPIO_INPUT>; - enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD"; - label = "PG_EC_ALL_SYS_PWRGD"; - }; - pp5000_a_pg_od { - gpios = <&gpiod 7 GPIO_INPUT>; - enum-name = "GPIO_PP5000_A_PG_OD"; - label = "PP5000_A_PG_OD"; - }; - base_sixaxis_int_l { - gpios = <&gpio5 6 GPIO_INPUT>; - label = "BASE_SIXAXIS_INT_L"; - }; - wfcam_vsync { - gpios = <&gpiob 7 GPIO_INPUT>; - label = "WFCAM_VSYNC"; - }; - tcs3400_int_odl { - gpios = <&gpio7 2 GPIO_INPUT>; - label = "TCS3400_INT_ODL"; - }; - usb_c0_ppc_int_odl { - gpios = <&gpioe 0 GPIO_INPUT>; - label = "USB_C0_PPC_INT_ODL"; - }; - usb_c1_ppc_int_odl { - gpios = <&gpioa 2 GPIO_INPUT>; - label = "USB_C1_PPC_INT_ODL"; - }; - usb_c0_tcpc_int_odl { - gpios = <&gpio6 2 GPIO_INPUT>; - label = "USB_C0_TCPC_INT_ODL"; - }; - usb_c1_tcpc_int_odl { - gpios = <&gpiof 5 GPIO_INPUT>; - label = "USB_C1_TCPC_INT_ODL"; - }; - usb_c0_bc12_int_odl { - gpios = <&gpio9 5 GPIO_INPUT>; - label = "USB_C0_BC12_INT_ODL"; - }; - usb_c1_bc12_int_odl { - gpios = <&gpioe 4 GPIO_INPUT>; - label = "USB_C1_BC12_INT_ODL"; - }; - ec_voldn_btn_odl { - gpios = <&gpio9 3 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "EC_VOLDN_BTN_ODL"; - }; - ec_volup_btn_odl { - gpios = <&gpio7 5 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "EC_VOLUP_BTN_ODL"; - }; - sys_reset_l { - gpios = <&gpioc 5 GPIO_ODR_HIGH>; - enum-name = "GPIO_SYS_RESET_L"; - label = "SYS_RESET_L"; - }; - entering_rw { - gpios = <&gpioe 3 GPIO_OUT_LOW>; - enum-name = "GPIO_ENTERING_RW"; - label = "ENTERING_RW"; - }; - pch_wake_l { - gpios = <&gpio7 4 GPIO_ODR_HIGH>; - enum-name = "GPIO_EC_PCH_WAKE_ODL"; - label = "PCH_WAKE_L"; - }; - pch_pwrbtn_l { - gpios = <&gpioc 1 GPIO_ODR_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - label = "PCH_PWRBTN_L"; - }; - en_pp5000_a { - gpios = <&gpioa 4 GPIO_OUT_LOW>; - enum-name = "GPIO_EN_PP5000_A"; - label = "EN_PP5000_A"; - }; - en_pp5000 { - gpios = <&gpioa 4 GPIO_OUT_LOW>; - enum-name = "GPIO_EN_PP5000"; - label = "EN_PP5000"; - }; - gpio_edp_bklten_od { - gpios = <&gpiod 3 GPIO_ODR_HIGH>; - enum-name = "GPIO_ENABLE_BACKLIGHT"; - label = "EDP_BKLTEN_OD"; - }; - en_a_rails { - gpios = <&gpioa 3 GPIO_OUT_LOW>; - enum-name = "GPIO_EN_A_RAILS"; - label = "EN_A_RAILS"; - }; - ec_pch_rsmrst_l { - gpios = <&gpioa 6 GPIO_OUT_LOW>; - enum-name = "GPIO_PCH_RSMRST_L"; - label = "EC_PCH_RSMRST_L"; - }; - ec_prochot_odl { - gpios = <&gpio6 3 GPIO_ODR_HIGH>; - enum-name = "GPIO_CPU_PROCHOT"; - label = "EC_PROCHOT_ODL"; - }; - ec_prochot_in_od { - gpios = <&gpio3 4 GPIO_INPUT>; - label = "EC_PROCHOT_IN_OD"; - }; - ec_pch_sys_pwrok { - gpios = <&gpio3 7 GPIO_OUT_LOW>; - enum-name = "GPIO_PCH_SYS_PWROK"; - label = "EC_PCH_SYS_PWROK"; - }; - cpu_c10_gate_l { - gpios = <&gpio6 7 GPIO_INPUT>; - label = "CPU_C10_GATE_L"; - }; - ec_int_l { - gpios = <&gpio7 0 GPIO_ODR_HIGH>; - label = "EC_INT_L"; - }; - ec_rst_odl { - gpios = <&gpio0 2 GPIO_INPUT>; - label = "EC_RST_ODL"; - }; - usb_c_oc_odl { - gpios = <&gpiob 1 GPIO_ODR_HIGH>; - label = "USB_C_OC_ODL"; - }; - usb_c0_tcpc_rst_odl { - gpios = <&gpio9 7 GPIO_ODR_HIGH>; - label = "USB_C0_TCPC_RST_ODL"; - }; - usb_c1_tcpc_rst_odl { - gpios = <&gpio3 2 GPIO_ODR_HIGH>; - label = "USB_C1_TCPC_RST_ODL"; - }; - usb_c0_bc12_chg_det_l { - gpios = <&gpio6 0 GPIO_INPUT>; - label = "USB_C0_BC12_CHG_DET_L"; - }; - usb_c1_bc12_chg_det_l { - gpios = <&gpio9 6 GPIO_INPUT>; - label = "USB_C1_BC12_CHG_DET_L"; - }; - usb_c0_bc12_vbus_on { - gpios = <&gpio9 4 GPIO_OUT_LOW>; - label = "USB_C0_BC12_VBUS_ON"; - }; - usb_c1_bc12_vbus_on { - gpios = <&gpioc 6 GPIO_OUT_LOW>; - label = "USB_C1_BC12_VBUS_ON"; - }; - ec_batt_pres_odl { - gpios = <&gpioe 1 GPIO_INPUT>; - label = "EC_BATT_PRES_ODL"; - }; - led_1_l { - gpios = <&gpioc 4 GPIO_OUT_HIGH>; - label = "LED_1_L"; - }; - led_2_l { - gpios = <&gpioc 3 GPIO_OUT_HIGH>; - label = "LED_2_L"; - }; - led_3_l { - gpios = <&gpioc 2 GPIO_OUT_HIGH>; - label = "LED_3_L"; - }; - ec_kb_bl_en { - gpios = <&gpio8 6 GPIO_OUT_LOW>; - label = "EC_KB_BL_EN"; - }; - edp_bklten_od { - gpios = <&gpiod 3 GPIO_ODR_HIGH>; - label = "EDP_BKLTEN_OD"; - }; - lid_accel_int_l { - gpios = <&gpio5 0 GPIO_INPUT>; - label = "LID_ACCEL_INT_L"; - }; - m2_sd_pln { - gpios = <&gpioa 0 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "M2_SD_PLN"; - }; - imvp8_pe { - gpios = <&gpioa 7 GPIO_INPUT>; - label = "IMVP8_PE"; - }; - i2c0_scl { - gpios = <&gpiob 5 GPIO_INPUT>; - label = "I2C0_SCL"; - }; - i2c0_sda { - gpios = <&gpiob 4 GPIO_INPUT>; - label = "I2C0_SDA"; - }; - i2c1_scl { - gpios = <&gpio9 0 GPIO_INPUT>; - label = "I2C1_SCL"; - }; - i2c1_sda { - gpios = <&gpio8 7 GPIO_INPUT>; - label = "I2C1_SDA"; - }; - i2c2_scl { - gpios = <&gpio9 2 GPIO_INPUT>; - label = "I2C2_SCL"; - }; - i2c2_sda { - gpios = <&gpio9 1 GPIO_INPUT>; - label = "I2C2_SDA"; - }; - i2c3_scl { - gpios = <&gpiod 1 GPIO_INPUT>; - label = "I2C3_SCL"; - }; - i2c3_sda { - gpios = <&gpiod 0 GPIO_INPUT>; - label = "I2C3_SDA"; - }; - i2c5_scl { - gpios = <&gpio3 3 GPIO_INPUT>; - label = "I2C5_SCL"; - }; - i2c5_sda { - gpios = <&gpio3 6 GPIO_INPUT>; - label = "I2C5_SDA"; - }; - i2c7_scl { - gpios = <&gpiob 3 GPIO_INPUT>; - label = "I2C7_SCL"; - }; - i2c7_sda { - gpios = <&gpiob 2 GPIO_INPUT>; - label = "I2C7_SDA"; - }; - tp58 { - gpios = <&gpio0 4 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP58"; - }; - tp73 { - gpios = <&gpio8 2 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP73"; - }; - tp18 { - gpios = <&gpioc 0 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP18"; - }; - tp54 { - gpios = <&gpio4 0 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP54"; - }; - tp56 { - gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP56"; - }; - tp57 { - gpios = <&gpio8 1 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP57"; - }; - tp55 { - gpios = <&gpio7 3 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP55"; - }; - tp59 { - gpios = <&gpiob 0 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP59"; - }; - kbd_kso2 { - gpios = <&gpio1 7 GPIO_OUT_LOW>; - label = "KBD_KSO2"; - }; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - lvol-io-pads = <&lvol_iob4 &lvol_iob5 /* I2C_SDA0 & SCL0 */ - &lvol_io50>; /* GPIO50 */ - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */ -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; diff --git a/zephyr/boards/arm/kohaku/kohaku.yaml b/zephyr/boards/arm/kohaku/kohaku.yaml deleted file mode 100644 index 48cc85e7df..0000000000 --- a/zephyr/boards/arm/kohaku/kohaku.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2020 Google LLC. -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: kohaku -name: "Google Kohaku (Samsung Galaxy Chromebook) Embedded Controller" -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -ram: 64 -flash: 512 -testing: - ignore_tags: - - net - - bluetooth diff --git a/zephyr/boards/arm/kohaku/kohaku_defconfig b/zephyr/boards/arm/kohaku/kohaku_defconfig deleted file mode 100644 index eccf6da6ab..0000000000 --- a/zephyr/boards/arm/kohaku/kohaku_defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX7=y -CONFIG_SOC_NPCX7M6FC=y - -# Platform Configuration -CONFIG_BOARD_KOHAKU=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx9/Kconfig.board b/zephyr/boards/arm/npcx9/Kconfig.board deleted file mode 100644 index e4b184d83e..0000000000 --- a/zephyr/boards/arm/npcx9/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -config BOARD_NPCX9 - bool "NPCX9 Zephyr Board" - depends on SOC_NPCX9M3F - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/npcx9/Kconfig.defconfig b/zephyr/boards/arm/npcx9/Kconfig.defconfig deleted file mode 100644 index 9b83915f04..0000000000 --- a/zephyr/boards/arm/npcx9/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_NPCX9 - -config BOARD - default "npcx9" - -endif # BOARD_TROGDOR diff --git a/zephyr/boards/arm/npcx9/board.cmake b/zephyr/boards/arm/npcx9/board.cmake deleted file mode 100644 index a204305534..0000000000 --- a/zephyr/boards/arm/npcx9/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) diff --git a/zephyr/boards/arm/npcx9/npcx9.dts b/zephyr/boards/arm/npcx9/npcx9.dts deleted file mode 100644 index ab44d8119e..0000000000 --- a/zephyr/boards/arm/npcx9/npcx9.dts +++ /dev/null @@ -1,199 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx9.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/gpio_defines.h> -#include <dt-bindings/wake_mask_event_defines.h> -#include <nuvoton/npcx9m3f.dtsi> - -/ { - model = "NPCX9"; - - aliases { - i2c-0 = &i2c0_0; - i2c-1 = &i2c1_0; - i2c-2 = &i2c2_0; - i2c-3 = &i2c3_0; - i2c-5 = &i2c5_0; - i2c-7 = &i2c7_0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - i2c_sensor: sensor { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - tcpc0_2 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_USB_C0_C2_TCPC"; - label = "TCPC0,2"; - }; - tcpc1 { - i2c-port = <&i2c4_1>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - label = "TCPC1"; - }; - ppc0_2 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_USB_C0_C2_PPC"; - label = "PPC0,2"; - }; - ppc1 { - i2c-port = <&i2c6_1>; - enum-name = "I2C_PORT_USB_C1_PPC"; - label = "PPC1"; - }; - retimer0_2 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_C0_C2_MUX"; - label = "RETIMER0,2"; - }; - battery { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - eeprom { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - charger { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_CHARGER"; - label = "EEPROM"; - }; - }; - - named-pwms { - compatible = "named-pwms"; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c4_1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl4 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c6_1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl6 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - >; -}; diff --git a/zephyr/boards/arm/npcx9/npcx9_defconfig b/zephyr/boards/arm/npcx9/npcx9_defconfig deleted file mode 100644 index d20fd87f3a..0000000000 --- a/zephyr/boards/arm/npcx9/npcx9_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_SOC_NPCX9M3F=y - -# Platform Configuration -CONFIG_BOARD_NPCX9=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.board b/zephyr/boards/arm/npcx_evb/Kconfig.board deleted file mode 100644 index 0ac4a80833..0000000000 --- a/zephyr/boards/arm/npcx_evb/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Note: this Zephyr board more closely represents the Chrome OS -# concept of a baseboard. Zephyr boards and Chrome OS boards do not -# have a 1:1 mapping. -config BOARD_NPCX7_EVB - bool "NPCX7 Evaluation Board" - depends on SOC_NPCX7M6FB || SOC_NPCX7M6FC || SOC_NPCX7M7FC - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT - -config BOARD_NPCX9_EVB - bool "NPCX9 Evaluation Board" - depends on SOC_NPCX9M3F || SOC_NPCX9M6F - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig deleted file mode 100644 index c0c874ad26..0000000000 --- a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -config BOARD - default "npcx7_evb" if BOARD_NPCX7_EVB - default "npcx9_evb" if BOARD_NPCX9_EVB diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts deleted file mode 100644 index c20589d637..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx7.dtsi> - -/* - * #include <nuvoton/npcx7m6fb.dtsi> - * #include <nuvoton/npcx7m6fc.dtsi> - * #include <nuvoton/npcx7m7fc.dtsi> - */ -#include <nuvoton/npcx7m6fc.dtsi> -#include "npcx_evb.dtsi" - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */ -}; diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig deleted file mode 100644 index b2fc879cbc..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX7=y -# NPCX7 soc list -# CONFIG_SOC_NPCX7M6FB -# CONFIG_SOC_NPCX7M6FC -# CONFIG_SOC_NPCX7M7FC -CONFIG_SOC_NPCX7M6FC=y - -# Platform Configuration -CONFIG_BOARD_NPCX7_EVB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# I2C -CONFIG_I2C=y - -# ADC -CONFIG_ADC=y -CONFIG_ADC_SHELL=n - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts deleted file mode 100644 index 4ab68cdde1..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx9.dtsi> - -/* - * #include <nuvoton/npcx9m3f.dtsi> - * #include <nuvoton/npcx9m6f.dtsi> - */ -#include <nuvoton/npcx9m6f.dtsi> -#include "npcx_evb.dtsi" - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; -}; diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig deleted file mode 100644 index 9a946584ef..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX9=y -# NPCX9 soc list -# CONFIG_SOC_NPCX9M3F -# CONFIG_SOC_NPCX9M6F -CONFIG_SOC_NPCX9M6F=y - -# Platform Configuration -CONFIG_BOARD_NPCX9_EVB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# I2C -CONFIG_I2C=y - -# ADC -CONFIG_ADC=y -CONFIG_ADC_SHELL=n - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi deleted file mode 100644 index 61a1e79783..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <dt-bindings/gpio_defines.h> - -/ { - model = "Nuvoton NPCX Evaluation Board"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - cros,rtc = &mtc; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_evb_0_0 { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_EVB_0"; - label = "I2C0_0"; - }; - i2c_evb_1_0 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_EVB_1"; - label = "I2C1_0"; - }; - i2c_evb_2_0 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_EVB_2"; - label = "I2C2_0"; - }; - i2c_evb_3_0 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_EVB_3"; - label = "I2C3_0"; - }; - i2c_evb_7_0 { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EVB_7"; - label = "I2C7_0"; - }; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_ch_0 { - label = "ADC0"; - enum-name = "ADC_EVB_CH_0"; - channel = <0>; - }; - adc_ch_1 { - label = "ADC1"; - enum-name = "ADC_EVB_CH_1"; - channel = <1>; - }; - adc_ch_2 { - label = "ADC2"; - enum-name = "ADC_EVB_CH_2"; - channel = <2>; - }; - adc_ch_3 { - label = "ADC3"; - enum-name = "ADC_EVB_CH_3"; - channel = <3>; - }; - adc_ch_4 { - label = "ADC4"; - enum-name = "ADC_EVB_CH_4"; - channel = <4>; - }; - }; - - vsby-psl-in-list { - /* Use PSL_IN1/2/3 as detection pins from hibernate mode */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in3>; - }; -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -/* Power switch logic input pads */ -&psl_in1 { - flag = <NPCX_PSL_FALLING_EDGE>; -}; -&psl_in2 { - flag = <NPCX_PSL_FALLING_EDGE>; -}; -&psl_in3 { - flag = <NPCX_PSL_RISING_EDGE>; -}; - -&cros_kb_raw { - status = "okay"; - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso02_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - >; -}; diff --git a/zephyr/boards/arm/trogdor/Kconfig.board b/zephyr/boards/arm/trogdor/Kconfig.board deleted file mode 100644 index 4bfa4e50ac..0000000000 --- a/zephyr/boards/arm/trogdor/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# "BOARD" below refers to a Zephyr board, which does not have a 1:1 -# mapping with the Chrome OS concept of a board. By Zephyr's -# conventions, we'll still call it "BOARD_*" to make this more -# applicable to be upstreamed, even though this code is shared by all -# projects using Trogdor baseboard. -config BOARD_TROGDOR - bool "Google Trogdor Baseboard" - depends on SOC_NPCX7M7FC - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/trogdor/Kconfig.defconfig b/zephyr/boards/arm/trogdor/Kconfig.defconfig deleted file mode 100644 index bfd2e43bbf..0000000000 --- a/zephyr/boards/arm/trogdor/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_TROGDOR - -config BOARD - default "trogdor" - -endif # BOARD_TROGDOR diff --git a/zephyr/boards/arm/trogdor/board.cmake b/zephyr/boards/arm/trogdor/board.cmake deleted file mode 100644 index a204305534..0000000000 --- a/zephyr/boards/arm/trogdor/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) diff --git a/zephyr/boards/arm/trogdor/trogdor.dts b/zephyr/boards/arm/trogdor/trogdor.dts deleted file mode 100644 index 4bc7f7efc1..0000000000 --- a/zephyr/boards/arm/trogdor/trogdor.dts +++ /dev/null @@ -1,272 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx7.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/gpio_defines.h> -#include <dt-bindings/wake_mask_event_defines.h> -#include <nuvoton/npcx7m7fc.dtsi> - -/ { - model = "Google Trogdor Baseboard"; - - aliases { - i2c-0 = &i2c0_0; - i2c-1 = &i2c1_0; - i2c-2 = &i2c2_0; - i2c-3 = &i2c3_0; - i2c-5 = &i2c5_0; - i2c-7 = &i2c7_0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - cros,rtc = &mtc; - }; - - ec-console { - compatible = "ec-console"; - - disabled = "hostcmd"; - }; - - ec-mkbp-host-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <( - HOST_EVENT_MASK(HOST_EVENT_LID_OPEN) | - HOST_EVENT_MASK(HOST_EVENT_POWER_BUTTON) | - HOST_EVENT_MASK(HOST_EVENT_AC_CONNECTED) | - HOST_EVENT_MASK(HOST_EVENT_AC_DISCONNECTED) | - HOST_EVENT_MASK(HOST_EVENT_HANG_DETECT) | - HOST_EVENT_MASK(HOST_EVENT_RTC) | - HOST_EVENT_MASK(HOST_EVENT_MODE_CHANGE) | - HOST_EVENT_MASK(HOST_EVENT_DEVICE))>; - }; - - ec-mkbp-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | - MKBP_EVENT_HOST_EVENT | - MKBP_EVENT_SENSOR_FIFO)>; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - power { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_POWER"; - label = "POWER"; - }; - battery { - i2c-port = <&i2c0_0>; - remote-port = <0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - virtual { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_VIRTUAL"; - label = "VIRTUAL"; - }; - charger { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_CHARGER"; - label = "CHARGER"; - }; - tcpc0 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_TCPC0"; - label = "TCPC0"; - }; - tcpc1 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_TCPC1"; - label = "TCPC1"; - }; - eeprom { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - i2c_sensor: sensor { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - accel { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_ACCEL"; - label = "ACCEL"; - }; - }; - - named-pwms { - compatible = "named-pwms"; - - kblight { - pwms = <&pwm3 0 0>; - label = "KBLIGHT"; - frequency = <10000>; - }; - displight { - pwms = <&pwm5 0 0>; - label = "DISPLIGHT"; - frequency = <4800>; - }; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - vbus { - label = "ADC_VBUS"; - enum-name = "ADC_VBUS"; - channel = <1>; - /* Measure VBUS through a 1/10 voltage divider */ - mul = <10>; - }; - amon_bmon { - label = "ADC_AMON_BMON"; - enum-name = "ADC_AMON_BMON"; - channel = <2>; - /* - * Adapter current output or battery charging/ - * discharging current (uV) 18x amplification on - * charger side. - */ - mul = <1000>; - div = <18>; - }; - psys { - label = "ADC_PSYS"; - enum-name = "ADC_PSYS"; - channel = <3>; - /* - * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, - * to read 0.8V @ 99 W, i.e. 124000 uW/mV. - */ - mul = <124000>; - }; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - - /* I2C_SDA0 & SCL0 */ - lvol-io-pads = <&lvol_iob4 &lvol_iob5>; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */ -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; - - isl9238: isl9238@9 { - compatible = "intersil,isl9238"; - reg = <0x09>; - label = "ISL9238_CHARGER"; - }; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - /* Not used as no WLC connected */ - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -/* Keyboard backlight */ -&pwm3 { - status = "okay"; -}; - -/* Display backlight */ -&pwm5 { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - >; -}; diff --git a/zephyr/boards/arm/trogdor/trogdor_defconfig b/zephyr/boards/arm/trogdor/trogdor_defconfig deleted file mode 100644 index 2a61f3dd5c..0000000000 --- a/zephyr/boards/arm/trogdor/trogdor_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX7=y -CONFIG_SOC_NPCX7M7FC=y - -# Platform Configuration -CONFIG_BOARD_TROGDOR=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/volteer/Kconfig.board b/zephyr/boards/arm/volteer/Kconfig.board deleted file mode 100644 index 5a0390e16f..0000000000 --- a/zephyr/boards/arm/volteer/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Note: this Zephyr board more closely represents the Chrome OS -# concept of a baseboard. Zephyr boards and Chrome OS boards do not -# have a 1:1 mapping. -config BOARD_VOLTEER - bool "Google Volteer Baseboard" - depends on SOC_NPCX7M6FC || SOC_NPCX7M7FC - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/volteer/Kconfig.defconfig b/zephyr/boards/arm/volteer/Kconfig.defconfig deleted file mode 100644 index 05361962d9..0000000000 --- a/zephyr/boards/arm/volteer/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Google Volteer EC - -# Copyright 2020 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_VOLTEER - -config BOARD - default "volteer" - -endif # BOARD_VOLTEER diff --git a/zephyr/boards/arm/volteer/board.cmake b/zephyr/boards/arm/volteer/board.cmake deleted file mode 100644 index e29e12278d..0000000000 --- a/zephyr/boards/arm/volteer/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) diff --git a/zephyr/boards/arm/volteer/volteer.dts b/zephyr/boards/arm/volteer/volteer.dts deleted file mode 100644 index d837f8ab55..0000000000 --- a/zephyr/boards/arm/volteer/volteer.dts +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2020 The Chromium OS Authors - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx7.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/charger/intersil_isl9241.h> -#include <dt-bindings/gpio_defines.h> -#include <nuvoton/npcx7m7fc.dtsi> -#include <cros/thermistor/thermistor.dtsi> - -/ { - model = "Google Volteer EC"; - - aliases { - i2c-0 = &i2c0_0; - i2c-1 = &i2c1_0; - i2c-2 = &i2c2_0; - i2c-3 = &i2c3_0; - i2c-5 = &i2c5_0; - i2c-7 = &i2c7_0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - cros,rtc = &mtc; - }; - - ec-console { - compatible = "ec-console"; - - disabled = "hostcmd"; - }; - - named-batteries { - compatible = "named-batteries"; - - lgc011 { - enum-name = "lgc011"; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_sensor: sensor { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - i2c-accel { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_ACCEL"; - label = "ACCEL"; - }; - usb-c0 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_USB_C0"; - label = "USB_C0"; - }; - usb-c1 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_USB_C1"; - label = "USB_C1"; - }; - usb1-mix { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_1_MIX"; - label = "USB_1_MIX"; - }; - power { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_POWER"; - label = "POWER"; - }; - battery { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - eeprom { - i2c-port = <&i2c7_0>; - remote-port = <7>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - charger { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_CHARGER"; - label = "CHARGER"; - }; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_charger: charger { - label = "ADC_TEMP_SENSOR_CHARGER"; - enum-name = "ADC_TEMP_SENSOR_CHARGER"; - channel = <0>; - }; - adc_pp3300_regulator: pp3300_regulator { - label = "ADC_TEMP_SENSOR_PP3300_REGULATOR"; - enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR"; - channel = <1>; - }; - adc_ddr_soc: ddr_soc { - label = "ADC_TEMP_SENSOR_DDR_SOC"; - enum-name = "ADC_TEMP_SENSOR_DDR_SOC"; - channel = <8>; - }; - adc_fan: fan { - label = "ADC_TEMP_SENSOR_FAN"; - enum-name = "ADC_TEMP_SENSOR_FAN"; - channel = <3>; - }; - }; - - named-temp-sensors { - charger { - compatible = "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "TEMP_SENSOR_CHARGER"; - enum-name = "TEMP_SENSOR_CHARGER"; - temp_fan_off = <40>; - temp_fan_max = <55>; - temp_host_high = <75>; - temp_host_halt = <80>; - temp_host_release_high = <65>; - adc = <&adc_charger>; - }; - pp3300_regulator { - compatible = "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "TEMP_SENSOR_PP3300_REGULATOR"; - enum-name = "TEMP_SENSOR_PP3300_REGULATOR"; - temp_fan_off = <40>; - temp_fan_max = <55>; - temp_host_high = <75>; - temp_host_halt = <80>; - temp_host_release_high = <65>; - adc = <&adc_pp3300_regulator>; - }; - ddr_soc { - compatible = "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "TEMP_SENSOR_DDR_SOC"; - enum-name = "TEMP_SENSOR_DDR_SOC"; - temp_fan_off = <35>; - temp_fan_max = <50>; - temp_host_high = <70>; - temp_host_halt = <80>; - temp_host_release_high = <65>; - adc = <&adc_ddr_soc>; - }; - fan { - compatible = "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "TEMP_SENSOR_FAN"; - enum-name = "TEMP_SENSOR_FAN"; - temp_fan_off = <35>; - temp_fan_max = <50>; - temp_host_high = <70>; - temp_host_halt = <80>; - temp_host_release_high = <65>; - adc = <&adc_fan>; - }; - }; - - vsby-psl-in-list { - /* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>; - }; - - /* - * The CBI Second Source Factory Cache (SSFC) layout definition. - * Specific fields values are defined per board. - */ - cbi-ssfc { - compatible = "named-cbi-ssfc"; - - cbi_ssfc_base_sensor: base_sensor { - enum-name = "BASE_SENSOR"; - size = <3>; - }; - cbi_ssfc_lid_sensor: lid_sensor { - enum-name = "LID_SENSOR"; - size = <3>; - }; - cbi_ssfc_lightbar: lightbar { - enum-name = "LIGHTBAR"; - size = <2>; - }; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */ -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; - - isl9241: isl9241@9 { - compatible = "intersil,isl9241"; - reg = <0x09>; - label = "ISL9241_CHARGER"; - switching-frequency = <SWITCHING_FREQ_724KHZ>; - }; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - >; -}; - -&adc0 { - status = "okay"; -}; - -/* Power switch logic input pads */ -&psl_in1 { - flag = <NPCX_PSL_RISING_EDGE>; -}; - -&psl_in2 { - flag = <NPCX_PSL_RISING_EDGE>; -}; - -&psl_in3 { - flag = <NPCX_PSL_FALLING_EDGE>; -}; - -&psl_in4 { - flag = <NPCX_PSL_RISING_EDGE>; -}; - -&thermistor_3V3_30K9_47K_4050B { - status = "okay"; -}; diff --git a/zephyr/boards/arm/volteer/volteer_defconfig b/zephyr/boards/arm/volteer/volteer_defconfig deleted file mode 100644 index a3f184dff8..0000000000 --- a/zephyr/boards/arm/volteer/volteer_defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX7=y -CONFIG_SOC_NPCX7M7FC=y - -# Platform Configuration -CONFIG_BOARD_VOLTEER=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# ADC -# The resolution and oversamplig values are fixed by the NPCX ADC driver -CONFIG_ADC=y -CONFIG_ADC_SHELL=n - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/riscv/asurada/Kconfig.board b/zephyr/boards/riscv/asurada/Kconfig.board deleted file mode 100644 index f17a00d2fd..0000000000 --- a/zephyr/boards/riscv/asurada/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# "BOARD" below refers to a Zephyr board, which does not have a 1:1 -# mapping with the Chrome OS concept of a board. By Zephyr's -# conventions, we'll still call it "BOARD_*" to make this more -# applicable to be upstreamed, even though this code is shared by all -# projects using Trogdor baseboard. -config BOARD_ASURADA - bool "Google Asurada Baseboard" - depends on SOC_IT8XXX2 - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/riscv/asurada/Kconfig.defconfig b/zephyr/boards/riscv/asurada/Kconfig.defconfig deleted file mode 100644 index cc3e4b000c..0000000000 --- a/zephyr/boards/riscv/asurada/Kconfig.defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_ASURADA - -config BOARD - default "asurada" - -# Zephyr internal stack sizes - -config IDLE_STACK_SIZE - default 256 - -config ISR_STACK_SIZE - default 800 - -config SHELL_STACK_SIZE - default 1048 - -config SYSTEM_WORKQUEUE_STACK_SIZE - default 1024 - - -# Chromium EC stack sizes - -config TASK_CHARGER_STACK_SIZE - default 960 - -config TASK_CHIPSET_STACK_SIZE - default 820 - -config TASK_HOOKS_STACK_SIZE - default 672 - -config TASK_HOSTCMD_STACK_SIZE - default 1024 - -config TASK_KEYSCAN_STACK_SIZE - default 920 - -config TASK_MOTIONSENSE_STACK_SIZE - default 920 - -config TASK_PD_STACK_SIZE - default 1024 - -config TASK_USB_CHG_STACK_SIZE - default 800 - - -choice PLATFORM_EC_HOSTCMD_DEBUG_MODE - default HCDEBUG_OFF -endchoice # PLATFORM_EC_HOSTCMD_DEBUG_MODE - -endif # BOARD_ASURADA diff --git a/zephyr/boards/riscv/asurada/asurada.dts b/zephyr/boards/riscv/asurada/asurada.dts deleted file mode 100644 index 7b4519c0e1..0000000000 --- a/zephyr/boards/riscv/asurada/asurada.dts +++ /dev/null @@ -1,200 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/ite/it8xxx2.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/gpio_defines.h> -#include <it8xxx2.dtsi> -#include <dt-bindings/wake_mask_event_defines.h> - -/ { - model = "Google Asurada Baseboard"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - zephyr,flash-controller = &flashctrl; - }; - - ec-mkbp-host-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <( - HOST_EVENT_MASK(HOST_EVENT_AC_CONNECTED) | - HOST_EVENT_MASK(HOST_EVENT_AC_DISCONNECTED) | - HOST_EVENT_MASK(HOST_EVENT_LID_OPEN) | - HOST_EVENT_MASK(HOST_EVENT_POWER_BUTTON) | - HOST_EVENT_MASK(HOST_EVENT_HANG_DETECT) | - HOST_EVENT_MASK(HOST_EVENT_MODE_CHANGE))>; - }; - - ec-mkbp-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | - MKBP_EVENT_HOST_EVENT)>; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_vbus_c0 { - label = "ADC_VBUS_C0"; - enum-name = "ADC_VBUS_C0"; - channel = <0>; - mul = <10>; - }; - adc_board_id0 { - label = "ADC_BOARD_ID_0"; - enum-name = "ADC_BOARD_ID_0"; - channel = <1>; - }; - adc_board_id1 { - label = "ADC_BOARD_ID_1"; - enum-name = "ADC_BOARD_ID_1"; - channel = <2>; - }; - adc_charger_amon_r { - label = "ADC_AMON_BMON"; - enum-name = "ADC_AMON_BMON"; - channel = <3>; - mul = <1000>; - div = <18>; - }; - adc_vbus_c1 { - label = "ADC_VBUS_C1"; - enum-name = "ADC_VBUS_C1"; - channel = <5>; - mul = <10>; - }; - adc_charger_pmon { - label = "ADC_PMON"; - enum-name = "ADC_PMON"; - channel = <6>; - }; - adc-psys { - label = "ADC_PSYS"; - enum-name = "ADC_PSYS"; - channel = <6>; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - power { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_POWER"; - label = "POWER"; - }; - battery { - i2c-port = <&i2c0>; - remote-port = <0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - eeprom { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - charger { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_CHARGER"; - label = "CHARGER"; - }; - i2c_sensor: sensor { - i2c-port = <&i2c1>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - i2c-accel { - i2c-port = <&i2c1>; - enum-name = "I2C_PORT_ACCEL"; - label = "ACCEL"; - }; - ppc0 { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_PPC0"; - label = "PPC0"; - }; - ppc1 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_PPC1"; - label = "PPC1"; - }; - usb-c0 { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_USB_C0"; - label = "USB_C0"; - }; - usb-c1 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_USB_C1"; - label = "USB_C1"; - }; - usb-mux0 { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_USB_MUX0"; - label = "USB_MUX0"; - }; - usb-mux1 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_USB_MUX1"; - label = "USB_MUX1"; - }; - }; - - soc { - cros_kb_raw: cros-kb-raw@f01d00 { - compatible = "ite,it8xxx2-cros-kb-raw"; - reg = <0x00f01d00 0x29>; - label = "CROS_KB_RAW_0"; - interrupt-parent = <&intc>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <1804800>; -}; - -&adc0 { - status = "okay"; -}; - -&i2c0 { - /* EC_I2C_PWR_CBI */ - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c1 { - /* EC_I2C_SENSOR */ - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c2 { - /* EC_I2C_USB_C0 */ - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c4{ - /* EC_I2C_USB_C1 */ - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&cros_kb_raw { - status = "okay"; -}; diff --git a/zephyr/boards/riscv/asurada/asurada_defconfig b/zephyr/boards/riscv/asurada/asurada_defconfig deleted file mode 100644 index be85cd0f07..0000000000 --- a/zephyr/boards/riscv/asurada/asurada_defconfig +++ /dev/null @@ -1,99 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y - -# Platform Configuration -CONFIG_SOC_IT8XXX2=y -CONFIG_BOARD_ASURADA=y - -# SoC configuration -CONFIG_AP=y -CONFIG_AP_ARM_MTK_MT8192=y -CONFIG_HAS_TASK_CHIPSET=y - -# Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_NS16550=y -CONFIG_SHELL_TAB=y -CONFIG_SHELL_TAB_AUTOCOMPLETION=y -CONFIG_SHELL_HISTORY=y - -# GPIO Controller -CONFIG_GPIO=y -CONFIG_GPIO_ITE_IT8XXX2=y - -# ADC Driver -CONFIG_ADC_ITE_IT8XXX2=y -CONFIG_PLATFORM_EC_ADC=y -CONFIG_PLATFORM_EC_ADC_RESOLUTION=10 - -# Clock configuration -CONFIG_CLOCK_CONTROL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768 - -# Flash -CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y -CONFIG_PLATFORM_EC_FLASH_CROS=y -CONFIG_SOC_FLASH_ITE_IT8XXX2=y - -# I2C -CONFIG_I2C_ITE_IT8XXX2=y -CONFIG_PLATFORM_EC_I2C=y - -# Keyboard -CONFIG_PLATFORM_EC_KEYBOARD=y -CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y - -# Lid Switch -CONFIG_PLATFORM_EC_LID_SWITCH=y - -# MKBP -CONFIG_PLATFORM_EC_MKBP_EVENT=y -CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y -CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y -CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y - -# Pinmux Driver -CONFIG_PINMUX=y -CONFIG_PINMUX_ITE_IT8XXX2=y - -# Power Button -CONFIG_PLATFORM_EC_POWER_BUTTON=y - -# Power Sequencing -CONFIG_PLATFORM_EC_POWERSEQ=y -CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y -CONFIG_PLATFORM_EC_POWERSEQ_IT8XXX2=y -CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n -CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y -CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n -CONFIG_PLATFORM_EC_PWM=y -CONFIG_PWM_ITE_IT8XXX2=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Serial Host Interface (SHI) device. -CONFIG_CROS_SHI_IT8XXX2=y - -# Timer configuration -CONFIG_ITE_IT8XXX2_TIMER=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y -CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS=2500 -CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500 - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_IT8XXX2=y diff --git a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.board b/zephyr/boards/riscv/it8xxx2_evb/Kconfig.board deleted file mode 100644 index f0691edb39..0000000000 --- a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -config BOARD_IT8XXX2_EVB - bool "IT8XXX2 EV-board" - depends on SOC_IT8XXX2 - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig b/zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig deleted file mode 100644 index de08d278de..0000000000 --- a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_IT8XXX2_EVB - -config BOARD - default "it8xxx2_evb" - -endif # BOARD_IT8XXX2_EVB diff --git a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts b/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts deleted file mode 100644 index a1b61d02ec..0000000000 --- a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/ite/it8xxx2.dtsi> -#include <dt-bindings/gpio_defines.h> -#include <it8xxx2.dtsi> - -/ { - model = "IT8XXX2 EV-Board"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - zephyr,flash-controller = &flashctrl; - }; - - named-gpios { - compatible = "named-gpios"; - - power_button_l: power_button_l { - gpios = <&gpioe 4 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_POWER_BUTTON_L"; - label = "POWER_BUTTON_L"; - }; - lid_open: lid_open { - gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_LID_OPEN"; - label = "LID_OPEN"; - }; - wp_l { - gpios = <&gpioi 4 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_WP_L"; - label = "WP_L"; - }; - pch_pltrst_l { - gpios = <&gpioe 3 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_PCH_RSMRST_L"; - label = "PCH_PLTRST_L"; - }; - uart1_rx { - gpios = <&gpiob 0 GPIO_INPUT_PULL_UP>; - #enum-name = "GPIO_UART1_RX"; - label = "UART1_RX"; - }; - pch_smi_l { - gpios = <&gpiod 3 GPIO_OUT_HIGH>; - #enum-name = "GPIO_PCH_SMI_L"; - label = "PCH_SMI_L"; - }; - pch_sci_l { - gpios = <&gpiod 4 GPIO_OUT_HIGH>; - #enum-name = "GPIO_PCH_SCI_L"; - label = "PCH_SCI_L"; - }; - gate_a20_h { - gpios = <&gpiob 5 GPIO_OUT_HIGH>; - #enum-name = "GPIO_GATE_A20_H"; - label = "GATE_A20_H"; - }; - sys_reset_l { - gpios = <&gpiob 6 GPIO_OUT_HIGH>; - enum-name = "GPIO_SYS_RESET_L"; - label = "SYS_RESET_L"; - }; - lpc_clkrun_l { - gpios = <&gpioh 0 GPIO_OUT_LOW>; - #enum-name = "GPIO_LPC_CLKRUN_L"; - label = "LPC_CLKRUN_L"; - }; - pch_wake_l { - gpios = <&gpiob 7 GPIO_OUT_HIGH>; - enum-name = "GPIO_EC_PCH_WAKE_ODL"; - label = "PCH_WAKE_L"; - }; - i2c_a_scl { - gpios = <&gpiob 3 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C0_SENSOR_SCL"; - label = "I2C_A_SCL"; - }; - i2c_a_sda { - gpios = <&gpiob 4 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C0_SENSOR_SDA"; - label = "I2C_A_SDA"; - }; - i2c_b_scl { - gpios = <&gpioc 1 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C1_USB_C0_SCL"; - label = "I2C_B_SCL"; - }; - i2c_b_sda { - gpios = <&gpioc 2 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C1_USB_C0_SDA"; - label = "I2C_B_SDA"; - }; - i2c_c_scl { - gpios = <&gpiof 6 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C2_USB_C1_SCL"; - label = "I2C_C_SCL"; - }; - i2c_c_sda { - gpios = <&gpiof 7 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C2_USB_C1_SDA"; - label = "I2C_C_SDA"; - }; - i2c_e_scl { - gpios = <&gpioe 0 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C5_BATTERY_SCL"; - label = "I2C_E_SCL"; - }; - i2c_e_sda { - gpios = <&gpioe 7 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C5_BATTERY_SDA"; - label = "I2C_E_SDA"; - }; - - spi0_cs { - gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; - enum-name = "GPIO_SPI0_CS"; - label = "SPI0_CS"; - }; - }; - - hibernate-wake-pins { - compatible = "cros-ec,hibernate-wake-pins"; - wakeup-pins = <&power_button_l - &lid_open>; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_vbussa: vbussa { - label = "ADC_VBUSSA"; - enum-name = "ADC_VBUS"; - channel = <0>; - }; - adc_vbussb: vbussb { - label = "ADC_VBUSSB"; - enum-name = "ADC_PSYS"; - channel = <1>; - }; - adc_evb_ch_13: evb_ch_13 { - label = "ADC_EVB_CH_13"; - enum-name = "ADC_AMON_BMON"; - channel = <2>; - }; - adc_evb_ch_14: evb_ch_14 { - label = "ADC_EVB_CH_14"; - enum-name = "ADC_TEMP_SENSOR_FAN"; - channel = <3>; - }; - adc_evb_ch_15: evb_ch_15 { - label = "ADC_EVB_CH_15"; - enum-name = "ADC_TEMP_SENSOR_DDR_SOC"; - channel = <4>; - }; - adc_evb_ch_16: evb_ch_16 { - label = "ADC_EVB_CH_16"; - enum-name = "ADC_TEMP_SENSOR_CHARGER"; - channel = <5>; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - battery { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - evb-1 { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_EVB_1"; - label = "EVB_1"; - }; - evb-2 { - i2c-port = <&i2c1>; - enum-name = "I2C_PORT_EVB_2"; - label = "EVB_2"; - }; - opt-4 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_OPT_4"; - label = "OPT_4"; - }; - }; - - named-pwms { - compatible = "named-pwms"; - /* NOTE: &pwm number needs same with channel number */ - test0 { - pwms = <&pwm7 PWM_CHANNEL_7 PWM_POLARITY_INVERTED>; - label = "TEST0"; - /* - * If we need pwm output in ITE chip power saving - * mode, then we should set frequency <=324Hz. - */ - frequency = <324>; - }; - test1 { - pwms = <&pwm0 PWM_CHANNEL_0 PWM_POLARITY_NORMAL>; - label = "TEST1"; - frequency = <30000>; - }; - }; -}; - -&adc0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <1804800>; -}; - -/* TEST1 */ -&pwm0 { - status = "okay"; - prescaler-cx = <PWM_PRESCALER_C6>; -}; - -/* TEST0 */ -&pwm7 { - status = "okay"; - prescaler-cx = <PWM_PRESCALER_C4>; -}; diff --git a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig b/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig deleted file mode 100644 index d667fac5a1..0000000000 --- a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y - -# Platform Configuration -CONFIG_SOC_IT8XXX2=y -CONFIG_BOARD_IT8XXX2_EVB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_NS16550=y -CONFIG_SHELL_TAB=y -CONFIG_SHELL_TAB_AUTOCOMPLETION=y -CONFIG_SHELL_HISTORY=y - -# Pinmux Driver -CONFIG_PINMUX=y -CONFIG_PINMUX_ITE_IT8XXX2=y - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n -CONFIG_PLATFORM_EC_PWM=y -CONFIG_PWM_ITE_IT8XXX2=y - -# GPIO Controller -CONFIG_GPIO=y -CONFIG_GPIO_ITE_IT8XXX2=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y -CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500 - -# I2C Controller -CONFIG_I2C_ITE_IT8XXX2=y - -CONFIG_ITE_IT8XXX2_TIMER=y - -# ADC -CONFIG_ADC=y -CONFIG_ADC_ITE_IT8XXX2=y -CONFIG_PLATFORM_EC_ADC_RESOLUTION=10 - -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768 - -# Flash -CONFIG_SOC_FLASH_ITE_IT8XXX2=y - -# Code RAM base for IT8XXX2 -CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x80000000 -CONFIG_CROS_EC_RAM_BASE=0x80100000 -CONFIG_CROS_EC_DATA_RAM_SIZE=0x00100000 -CONFIG_CROS_EC_RAM_SIZE=0x0000f000 - - -CONFIG_CROS_EC_RO_MEM_OFF=0x0 -CONFIG_CROS_EC_RO_SIZE=0x80000 -CONFIG_CROS_EC_RW_MEM_OFF=0x0 -CONFIG_CROS_EC_RW_SIZE=0x80000 - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_IT8XXX2=y |