ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 246 deletions

diff --git a/zephyr/drivers/cros_system/cros_system_it8xxx2.c b/zephyr/drivers/cros_system/cros_system_it8xxx2.c
deleted file mode 100644
index 5731dcf984..0000000000
--- a/zephyr/drivers/cros_system/cros_system_it8xxx2.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT ite_it8xxx2_gctrl
-
-#include <device.h>
-#include <drivers/cros_system.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <soc/ite_it8xxx2/reg_def_cros.h>
-
-#include "gpio.h"
-#include "system.h"
-#include "util.h"
-
-LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
-
-#define GCTRL_IT8XXX2_REG_BASE \
-	((struct gctrl_it8xxx2_regs *)DT_INST_REG_ADDR(0))
-
-#define WDT_IT8XXX2_REG_BASE \
-	((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
-
-static const char *cros_system_it8xxx2_get_chip_vendor(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	return "ite";
-}
-
-static uint32_t system_get_chip_id(void)
-{
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-
-	return (gctrl_base->GCTRL_ECHIPID1 << 16) |
-		(gctrl_base->GCTRL_ECHIPID2 << 8) |
-		gctrl_base->GCTRL_ECHIPID3;
-}
-
-static uint8_t system_get_chip_version(void)
-{
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-
-	/* bit[3-0], chip version */
-	return gctrl_base->GCTRL_ECHIPVER & 0x0F;
-}
-
-static const char *cros_system_it8xxx2_get_chip_name(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	static char buf[8] = {'i', 't'};
-	uint32_t chip_id = system_get_chip_id();
-	int num = 4;
-
-	for (int n = 2; num >= 0; n++, num--)
-		snprintf(buf+n, (sizeof(buf)-n), "%x",
-			 chip_id >> (num * 4) & 0xF);
-
-	return buf;
-}
-
-static const char *cros_system_it8xxx2_get_chip_revision(const struct device
-							 *dev)
-{
-	ARG_UNUSED(dev);
-
-	static char buf[3];
-	uint8_t rev = system_get_chip_version();
-
-	snprintf(buf, sizeof(buf), "%1xx", rev+0xa);
-
-	return buf;
-}
-
-static int cros_system_it8xxx2_get_reset_cause(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-	/* system reset flag */
-	uint32_t system_flags = chip_read_reset_flags();
-	int chip_reset_cause = 0;
-	uint8_t raw_reset_cause = gctrl_base->GCTRL_RSTS & IT8XXX2_GCTRL_LRS;
-	uint8_t raw_reset_cause2 = gctrl_base->GCTRL_SPCTRL4 &
-		(IT8XXX2_GCTRL_LRSIWR | IT8XXX2_GCTRL_LRSIPWRSWTR |
-		IT8XXX2_GCTRL_LRSIPGWR);
-
-	/* Clear reset cause. */
-	gctrl_base->GCTRL_RSTS |= IT8XXX2_GCTRL_LRS;
-	gctrl_base->GCTRL_SPCTRL4 |= (IT8XXX2_GCTRL_LRSIWR |
-		IT8XXX2_GCTRL_LRSIPWRSWTR | IT8XXX2_GCTRL_LRSIPGWR);
-
-	/* Determine if watchdog reset or power on reset. */
-	if (raw_reset_cause & IT8XXX2_GCTRL_IWDTR) {
-		system_flags |= EC_RESET_FLAG_WATCHDOG;
-		chip_reset_cause = WATCHDOG_RST;
-	} else if (raw_reset_cause < 2) {
-		system_flags |= EC_RESET_FLAG_POWER_ON;
-		chip_reset_cause = POWERUP;
-	}
-	/* Determine reset-pin reset. */
-	if (raw_reset_cause2 & IT8XXX2_GCTRL_LRSIWR) {
-		system_flags |= EC_RESET_FLAG_RESET_PIN;
-		chip_reset_cause = VCC1_RST_PIN;
-	}
-
-	/* watchdog module triggers these reset */
-	if (system_flags & (EC_RESET_FLAG_HARD | EC_RESET_FLAG_SOFT))
-		system_flags &= ~EC_RESET_FLAG_WATCHDOG;
-
-	/* Set the system reset flags. */
-	system_set_reset_flags(system_flags);
-
-	return chip_reset_cause;
-}
-
-static int cros_system_it8xxx2_init(const struct device *dev)
-{
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-
-	/* System triggers a soft reset by default (command: reboot). */
-	gctrl_base->GCTRL_ETWDUARTCR &= ~IT8XXX2_GCTRL_ETWD_HW_RST_EN;
-
-	return 0;
-}
-
-static int cros_system_it8xxx2_soc_reset(const struct device *dev)
-{
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-	struct wdt_it8xxx2_regs *const wdt_base = WDT_IT8XXX2_REG_BASE;
-	uint32_t chip_reset_flags = chip_read_reset_flags();
-
-	/* Disable interrupts to avoid task swaps during reboot. */
-	interrupt_disable_all();
-
-	if (chip_reset_flags & (EC_RESET_FLAG_HARD | EC_RESET_FLAG_HIBERNATE))
-		gctrl_base->GCTRL_ETWDUARTCR |= IT8XXX2_GCTRL_ETWD_HW_RST_EN;
-
-	/*
-	 * Writing invalid key to watchdog module triggers a soft or hardware
-	 * reset. It depends on the setting of bit0 at ETWDUARTCR register.
-	 */
-	wdt_base->ETWCFG |= IT8XXX2_WDT_EWDKEYEN;
-	wdt_base->EWDKEYR = 0x00;
-
-	/* Spin and wait for reboot */
-	while (1)
-		;
-
-	/* Should never return */
-	return 0;
-}
-
-static int cros_system_it8xxx2_hibernate(const struct device *dev,
-					 uint32_t seconds,
-					 uint32_t microseconds)
-{
-	struct wdt_it8xxx2_regs *const wdt_base = WDT_IT8XXX2_REG_BASE;
-
-	/* Disable all interrupts. */
-	interrupt_disable_all();
-
-	/* Save and disable interrupts */
-	if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC))
-		ite_intc_save_and_disable_interrupts();
-
-	/* bit5: watchdog is disabled. */
-	wdt_base->ETWCTRL |= IT8XXX2_WDT_EWDSCEN;
-
-	/*
-	 * Setup GPIOs for hibernate. On some boards, it's possible that this
-	 * may not return at all. On those boards, power to the EC is likely
-	 * being turn off entirely.
-	 */
-	if (board_hibernate_late) {
-		/*
-		 * Set reset flag in case board_hibernate_late() doesn't
-		 * return.
-		 */
-		chip_save_reset_flags(EC_RESET_FLAG_HIBERNATE);
-		board_hibernate_late();
-	}
-
-	if (seconds || microseconds) {
-		/*
-		 * Convert milliseconds(or at least 1 ms) to 32 Hz
-		 * free run timer count for hibernate.
-		 */
-		uint32_t c = (seconds * 1000 + microseconds / 1000 + 1) *
-				32 / 1000;
-
-		/* Enable a 32-bit timer and clock source is 32 Hz */
-		/* Disable external timer x */
-		IT8XXX2_EXT_CTRLX(FREE_RUN_TIMER) &= ~IT8XXX2_EXT_ETXEN;
-		irq_disable(FREE_RUN_TIMER_IRQ);
-		IT8XXX2_EXT_PSRX(FREE_RUN_TIMER) = EXT_PSR_32;
-		IT8XXX2_EXT_CNTX(FREE_RUN_TIMER) = c & FREE_RUN_TIMER_MAX_CNT;
-		/* Enable and re-start external timer x */
-		IT8XXX2_EXT_CTRLX(FREE_RUN_TIMER) |=
-			(IT8XXX2_EXT_ETXEN | IT8XXX2_EXT_ETXRST);
-		irq_enable(FREE_RUN_TIMER_IRQ);
-	}
-
-	static const int wakeup_pin_list[] = {
-#if DT_NODE_EXISTS(SYSTEM_DT_NODE_HIBERNATE_CONFIG)
-		UTIL_LISTIFY(SYSTEM_DT_NODE_WAKEUP_PIN_LEN,
-			     SYSTEM_DT_WAKEUP_GPIO_ENUM_BY_IDX, _)
-#endif
-	};
-
-	/* Reconfigure wake-up GPIOs */
-	for (int i = 0; i < ARRAY_SIZE(wakeup_pin_list); i++)
-		/* Re-enable interrupt for wake-up inputs */
-		gpio_enable_interrupt(wakeup_pin_list[i]);
-
-	/* EC sleep mode */
-	chip_pll_ctrl(CHIP_PLL_SLEEP);
-
-	/* Chip sleep and wait timer wake it up */
-	__asm__ volatile ("wfi");
-
-	/* Reset EC when wake up from sleep mode (system hibernate) */
-	system_reset(SYSTEM_RESET_HIBERNATE);
-
-	return 0;
-}
-
-static const struct cros_system_driver_api cros_system_driver_it8xxx2_api = {
-	.get_reset_cause = cros_system_it8xxx2_get_reset_cause,
-	.soc_reset = cros_system_it8xxx2_soc_reset,
-	.hibernate = cros_system_it8xxx2_hibernate,
-	.chip_vendor = cros_system_it8xxx2_get_chip_vendor,
-	.chip_name = cros_system_it8xxx2_get_chip_name,
-	.chip_revision = cros_system_it8xxx2_get_chip_revision,
-};
-
-#if CONFIG_CROS_SYSTEM_IT8XXX2_INIT_PRIORITY >= \
-	CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY
-#error "CROS_SYSTEM must initialize before the SYSTEM_PRE initialization"
-#endif
-DEVICE_DEFINE(cros_system_it8xxx2_0, "CROS_SYSTEM", cros_system_it8xxx2_init,
-	      NULL, NULL, NULL, PRE_KERNEL_1,
-	      CONFIG_CROS_SYSTEM_IT8XXX2_INIT_PRIORITY,
-	      &cros_system_driver_it8xxx2_api);