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authorJack Rosenthal <jrosenth@chromium.org>2021-11-04 12:11:58 -0600
committerCommit Bot <commit-bot@chromium.org>2021-11-05 04:22:34 +0000
commit252457d4b21f46889eebad61d4c0a65331919cec (patch)
tree01856c4d31d710b20e85a74c8d7b5836e35c3b98 /zephyr/shim/chip/npcx/include/flash_chip.h
parent08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff)
downloadchrome-ec-stabilize-14469.58.B-ish.tar.gz
In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'zephyr/shim/chip/npcx/include/flash_chip.h')
-rw-r--r--zephyr/shim/chip/npcx/include/flash_chip.h31
1 files changed, 0 insertions, 31 deletions
diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h
deleted file mode 100644
index 622633c570..0000000000
--- a/zephyr/shim/chip/npcx/include/flash_chip.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FLASH_CHIP_H
-#define __CROS_EC_FLASH_CHIP_H
-
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-#ifdef CONFIG_FLASH_SIZE
-#define CONFIG_FLASH_SIZE_BYTES (CONFIG_FLASH_SIZE * 1024)
-#else
-#define CONFIG_FLASH_SIZE_BYTES 0x0
-#endif
-
-/* TODO(b:176490413): use DT_PROP(DT_INST(inst, DT_DRV_COMPAT), size) ? */
-#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
-#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
-#define CONFIG_FLASH_ERASE_SIZE 0x10000
-#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE
-
-/* RO image resides at start of protected region, right after header */
-#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
-
-#define CONFIG_RW_STORAGE_OFF 0
-
-/* Use 4k sector erase for NPCX monitor flash erase operations. */
-#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000
-
-#endif /* __CROS_EC_FLASH_CHIP_H */