diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
| commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
| tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /zephyr/shim/chip | |
| parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
| download | chrome-ec-firmware-cherry-14454.B-ish.tar.gz | |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'zephyr/shim/chip')
29 files changed, 0 insertions, 2108 deletions
diff --git a/zephyr/shim/chip/CMakeLists.txt b/zephyr/shim/chip/CMakeLists.txt deleted file mode 100644 index 5c76a4163a..0000000000 --- a/zephyr/shim/chip/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if (DEFINED CONFIG_SOC_FAMILY_NPCX) - add_subdirectory(npcx) -elseif (DEFINED CONFIG_SOC_FAMILY_RISCV_ITE) - add_subdirectory(it8xxx2) -elseif (DEFINED CONFIG_SOC_POSIX) - add_subdirectory(posix) -endif() - diff --git a/zephyr/shim/chip/it8xxx2/CMakeLists.txt b/zephyr/shim/chip/it8xxx2/CMakeLists.txt deleted file mode 100644 index 7a92a3cfb6..0000000000 --- a/zephyr/shim/chip/it8xxx2/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -zephyr_library_include_directories(include) - -zephyr_library_sources(clock.c) -zephyr_library_sources_ifdef(CONFIG_CROS_EC system.c) -zephyr_library_sources_ifdef(CONFIG_CROS_EC pinmux.c) -zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_ITE keyboard_raw.c) diff --git a/zephyr/shim/chip/it8xxx2/clock.c b/zephyr/shim/chip/it8xxx2/clock.c deleted file mode 100644 index 2bcf9e2899..0000000000 --- a/zephyr/shim/chip/it8xxx2/clock.c +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <device.h> -#include <drivers/clock_control.h> -#include <kernel.h> -#include <logging/log.h> -#include <soc.h> -#include <zephyr.h> -#include <soc/ite_it8xxx2/reg_def_cros.h> -#include <sys/util.h> - -#include "module_id.h" - -LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); - -#define ECPM_NODE DT_INST(0, ite_it8xxx2_ecpm) -#define HAL_ECPM_REG_BASE_ADDR \ - ((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0)) -#define PLLFREQ_MASK 0xf - -static const int pll_reg_to_freq[8] = { - MHZ(8), - MHZ(16), - MHZ(24), - MHZ(32), - MHZ(48), - MHZ(64), - MHZ(72), - MHZ(96) -}; - -int clock_get_freq(void) -{ - struct ecpm_reg *const ecpm_base = HAL_ECPM_REG_BASE_ADDR; - int reg_val = ecpm_base->ECPM_PLLFREQ & PLLFREQ_MASK; - - return pll_reg_to_freq[reg_val]; -} diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h deleted file mode 100644 index e45a08296f..0000000000 --- a/zephyr/shim/chip/it8xxx2/include/flash_chip.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_FLASH_CHIP_H -#define __CROS_EC_FLASH_CHIP_H - -/* - * Flash size of IT81202 is 1MB. - * We use only half space of flash to save time of erasing RW image from flash. - */ -#define CONFIG_FLASH_SIZE_BYTES (DT_REG_SIZE(DT_NODELABEL(flash0)) / 2) -/* Program is run directly from storage */ -#define CONFIG_MAPPED_STORAGE_BASE DT_REG_ADDR(DT_NODELABEL(flash0)) -/* - * One page program instruction allows maximum 256 bytes (a page) of data - * to be programmed. - */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 -/* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE DT_PROP(DT_INST(0, soc_nv_flash), \ - write_block_size) -/* Erase bank size */ -#define CONFIG_FLASH_ERASE_SIZE DT_PROP(DT_INST(0, soc_nv_flash), \ - erase_block_size) -/* Protect bank size */ -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE - -#define CONFIG_RO_STORAGE_OFF 0x0 -#define CONFIG_RW_STORAGE_OFF 0x0 - -/* - * The EC uses the one bank of flash to emulate a SPI-like write protect - * register with persistent state. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_FLASH_SIZE_BYTES / 2 - \ - CONFIG_FW_PSTATE_SIZE) - -#endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/chip/it8xxx2/keyboard_raw.c b/zephyr/shim/chip/it8xxx2/keyboard_raw.c deleted file mode 100644 index 0096798915..0000000000 --- a/zephyr/shim/chip/it8xxx2/keyboard_raw.c +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Functions needed by keyboard scanner module for Chrome EC */ - -#include <device.h> -#include <logging/log.h> -#include <soc.h> -#include <zephyr.h> - -#include "drivers/cros_kb_raw.h" -#include "keyboard_raw.h" - -/** - * Return true if the current value of the given input GPIO port is zero - */ -int keyboard_raw_is_input_low(int port, int id) -{ - /* - * TODO: implement for factory testing KSI and KSO pin as GPIO - * function. - */ - return 0; -} diff --git a/zephyr/shim/chip/it8xxx2/pinmux.c b/zephyr/shim/chip/it8xxx2/pinmux.c deleted file mode 100644 index fd8dc7fc8e..0000000000 --- a/zephyr/shim/chip/it8xxx2/pinmux.c +++ /dev/null @@ -1,112 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <init.h> -#include <drivers/pinmux.h> -#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h> -#include <soc.h> - -static int it8xxx2_pinmux_init(const struct device *dev) -{ - ARG_UNUSED(dev); - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxb), okay) && \ - DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) - const struct device *portb = DEVICE_DT_GET(DT_NODELABEL(pinmuxb)); - - /* SIN0 */ - pinmux_pin_set(portb, 0, IT8XXX2_PINMUX_FUNC_3); - /* SOUT0 */ - pinmux_pin_set(portb, 1, IT8XXX2_PINMUX_FUNC_3); -#endif - - return 0; -} -SYS_INIT(it8xxx2_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); - -/* - * Init priority is behind CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY to overwrite - * GPIO_INPUT setting of i2c ports. - */ -static int it8xxx2_pinmux_init_latr(const struct device *dev) -{ - ARG_UNUSED(dev); - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c0), okay) && \ - DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxb), okay) - { - const struct device *portb = - DEVICE_DT_GET(DT_NODELABEL(pinmuxb)); - - /* I2C0 CLK */ - pinmux_pin_set(portb, 3, IT8XXX2_PINMUX_FUNC_1); - /* I2C0 DAT */ - pinmux_pin_set(portb, 4, IT8XXX2_PINMUX_FUNC_1); - } -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay) && \ - DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxc), okay) - { - const struct device *portc = - DEVICE_DT_GET(DT_NODELABEL(pinmuxc)); - - /* I2C1 CLK */ - pinmux_pin_set(portc, 1, IT8XXX2_PINMUX_FUNC_1); - /* I2C1 DAT */ - pinmux_pin_set(portc, 2, IT8XXX2_PINMUX_FUNC_1); - } -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c2), okay) && \ - DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxf), okay) - { - const struct device *portf = - DEVICE_DT_GET(DT_NODELABEL(pinmuxf)); - - /* I2C2 CLK */ - pinmux_pin_set(portf, 6, IT8XXX2_PINMUX_FUNC_1); - /* I2C2 DAT */ - pinmux_pin_set(portf, 7, IT8XXX2_PINMUX_FUNC_1); - } -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c3), okay) && \ - DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxh), okay) - { - const struct device *porth = - DEVICE_DT_GET(DT_NODELABEL(pinmuxh)); - - /* I2C3 CLK */ - pinmux_pin_set(porth, 1, IT8XXX2_PINMUX_FUNC_3); - /* I2C3 DAT */ - pinmux_pin_set(porth, 2, IT8XXX2_PINMUX_FUNC_3); - } -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c4), okay) && \ - DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxe), okay) - { - const struct device *porte = - DEVICE_DT_GET(DT_NODELABEL(pinmuxe)); - - /* I2C4 CLK */ - pinmux_pin_set(porte, 0, IT8XXX2_PINMUX_FUNC_3); - /* I2C4 DAT */ - pinmux_pin_set(porte, 7, IT8XXX2_PINMUX_FUNC_3); - } -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c5), okay) && \ - DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxa), okay) - { - const struct device *porta = - DEVICE_DT_GET(DT_NODELABEL(pinmuxa)); - - /* I2C5 CLK */ - pinmux_pin_set(porta, 4, IT8XXX2_PINMUX_FUNC_3); - /* I2C5 DAT */ - pinmux_pin_set(porta, 5, IT8XXX2_PINMUX_FUNC_3); - } -#endif - - return 0; -} -SYS_INIT(it8xxx2_pinmux_init_latr, POST_KERNEL, 52); diff --git a/zephyr/shim/chip/it8xxx2/system.c b/zephyr/shim/chip/it8xxx2/system.c deleted file mode 100644 index d9dcd7ccfb..0000000000 --- a/zephyr/shim/chip/it8xxx2/system.c +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "system.h" - -uintptr_t system_get_fw_reset_vector(uintptr_t base) -{ - /* - * Because our reset vector is at the beginning of image copy - * (see init.S). So I just need to return 'base' here and EC will jump - * to the reset vector. - */ - return base; -} diff --git a/zephyr/shim/chip/npcx/CMakeLists.txt b/zephyr/shim/chip/npcx/CMakeLists.txt deleted file mode 100644 index d3cd4b48fd..0000000000 --- a/zephyr/shim/chip/npcx/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# When building code coverage, the final Zephyr image isn't actually linked -# and there's no valid image to program. Skip compiling and linking the NPCX -# monitor when coverage is enabled. -if (NOT DEFINED CONFIG_COVERAGE) - add_subdirectory(npcx_monitor) -endif() - -zephyr_library_include_directories(include) - -zephyr_library_sources(clock.c) -zephyr_library_sources(gpio.c) -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ESPI espi.c) -zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_NPCX keyboard_raw.c) -zephyr_library_sources_ifdef(CONFIG_CROS_SHI_NPCX shi.c) -zephyr_library_sources_ifdef(CONFIG_CROS_EC system.c) - -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_EXTERNAL_STORAGE - system_external_storage.c) -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API - system_download_from_flash.c) -zephyr_library_sources_ifdef(CONFIG_PM_POLICY_APP power_policy.c) diff --git a/zephyr/shim/chip/npcx/Kconfig.npcx b/zephyr/shim/chip/npcx/Kconfig.npcx deleted file mode 100644 index b044912ae1..0000000000 --- a/zephyr/shim/chip/npcx/Kconfig.npcx +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if PLATFORM_EC - -config CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY - int "System pre-initialization priority" - default 15 - range 10 19 - depends on SOC_FAMILY_NPCX - help - This sets the priority of the NPCX chip system initialization. The - chip system initialization verifies the integrity of the BBRAM and - must be a lower priority than CONFIG_BBRAM_INIT_PRIORITY and - must be a higher priority than PLATFORM_EC_SYSTEM_PRE_INIT. - -endif # PLATFORM_EC diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c deleted file mode 100644 index 8c8bad5596..0000000000 --- a/zephyr/shim/chip/npcx/clock.c +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <device.h> -#include <drivers/clock_control.h> -#include <dt-bindings/clock/npcx_clock.h> -#include <kernel.h> -#include <logging/log.h> -#include <soc.h> -#include <zephyr.h> - -#include "clock_chip.h" -#include "module_id.h" - -LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); - -#define CDCG_NODE DT_INST(0, nuvoton_npcx_pcc) -#define HAL_CDCG_REG_BASE_ADDR \ - ((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1)) - -int clock_get_freq(void) -{ - const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE); - const struct npcx_clk_cfg clk_cfg = { - .bus = NPCX_CLOCK_BUS_CORE, - }; - uint32_t rate; - - if (clock_control_get_rate(clk_dev, (clock_control_subsys_t *)&clk_cfg, - &rate) != 0) { - LOG_ERR("Get %s clock rate error", clk_dev->name); - return -EIO; - } - - return rate; -} - -void clock_turbo(void) -{ - struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR; - - /* For NPCX7: - * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since - * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1. - */ - cdcg_base->HFCGP = 0x01; - cdcg_base->HFCBCD = BIT(4); -} - -void clock_normal(void) -{ - struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR; - - cdcg_base->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL); - cdcg_base->HFCBCD = (FIUDIV_VAL << 4); -} - -void clock_enable_module(enum module_id module, int enable) -{ - /* Assume we have a single task using MODULE_FAST_CPU */ - if (module == MODULE_FAST_CPU) { - if (enable) - clock_turbo(); - else - clock_normal(); - } -} diff --git a/zephyr/shim/chip/npcx/espi.c b/zephyr/shim/chip/npcx/espi.c deleted file mode 100644 index 2115f388d6..0000000000 --- a/zephyr/shim/chip/npcx/espi.c +++ /dev/null @@ -1,53 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <device.h> -#include <sys/util.h> - -#include "drivers/espi.h" -#include "soc_espi.h" -#include "zephyr_espi_shim.h" - -bool is_acpi_command(uint32_t data) -{ - struct espi_evt_data_acpi *acpi = (struct espi_evt_data_acpi *)&data; - - return acpi->type; -} - -uint32_t get_acpi_value(uint32_t data) -{ - struct espi_evt_data_acpi *acpi = (struct espi_evt_data_acpi *)&data; - - return acpi->data; -} - -bool is_8042_ibf(uint32_t data) -{ - struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data; - - return kbc->evt & HOST_KBC_EVT_IBF; -} - -bool is_8042_obe(uint32_t data) -{ - struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data; - - return kbc->evt & HOST_KBC_EVT_OBE; -} - -uint32_t get_8042_type(uint32_t data) -{ - struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data; - - return kbc->type; -} - -uint32_t get_8042_data(uint32_t data) -{ - struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data; - - return kbc->data; -} diff --git a/zephyr/shim/chip/npcx/gpio.c b/zephyr/shim/chip/npcx/gpio.c deleted file mode 100644 index 148e1a97c9..0000000000 --- a/zephyr/shim/chip/npcx/gpio.c +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <device.h> -#include <kernel.h> - -#include <logging/log.h> - -#include "gpio.h" -#include "gpio/gpio.h" - -LOG_MODULE_REGISTER(shim_cros_gpio, LOG_LEVEL_ERR); - -static const struct unused_pin_config unused_pin_configs[] = { - UNUSED_GPIO_CONFIG_LIST -}; - -int gpio_config_unused_pins(void) -{ - for (size_t i = 0; i < ARRAY_SIZE(unused_pin_configs); ++i) { - int rv; - int flags; - const struct device *dev = - device_get_binding(unused_pin_configs[i].dev_name); - - if (dev == NULL) { - LOG_ERR("Not found (%s)", - unused_pin_configs[i].dev_name); - return -ENOTSUP; - } - - /* - * Set the default setting for the floating IOs. The floating - * IOs cause the leakage current. Set unused pins as input with - * internal PU to prevent extra power consumption. - */ - if (unused_pin_configs[i].flags == 0) - flags = GPIO_INPUT | GPIO_PULL_UP; - else - flags = unused_pin_configs[i].flags; - - rv = gpio_pin_configure(dev, unused_pin_configs[i].pin, flags); - - if (rv < 0) { - LOG_ERR("Config failed %s-%d (%d)", - unused_pin_configs[i].dev_name, - unused_pin_configs[i].pin, rv); - return rv; - } - } - - return 0; -} diff --git a/zephyr/shim/chip/npcx/include/clock_chip.h b/zephyr/shim/chip/npcx/include/clock_chip.h deleted file mode 100644 index 0c39ed8174..0000000000 --- a/zephyr/shim/chip/npcx/include/clock_chip.h +++ /dev/null @@ -1,14 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CLOCK_CHIP_H -#define __CROS_EC_CLOCK_CHIP_H - -/** - * TODO(b:180112248) implement in zephyr's clock_control.h - */ -void clock_turbo(void); - -#endif /* __CROS_EC_CLOCK_CHIP_H */ diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h deleted file mode 100644 index 622633c570..0000000000 --- a/zephyr/shim/chip/npcx/include/flash_chip.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_FLASH_CHIP_H -#define __CROS_EC_FLASH_CHIP_H - -#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ -#ifdef CONFIG_FLASH_SIZE -#define CONFIG_FLASH_SIZE_BYTES (CONFIG_FLASH_SIZE * 1024) -#else -#define CONFIG_FLASH_SIZE_BYTES 0x0 -#endif - -/* TODO(b:176490413): use DT_PROP(DT_INST(inst, DT_DRV_COMPAT), size) ? */ -#define CONFIG_MAPPED_STORAGE_BASE 0x64000000 -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x10000 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE - -/* RO image resides at start of protected region, right after header */ -#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE - -#define CONFIG_RW_STORAGE_OFF 0 - -/* Use 4k sector erase for NPCX monitor flash erase operations. */ -#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 - -#endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/chip/npcx/include/rom_chip.h b/zephyr/shim/chip/npcx/include/rom_chip.h deleted file mode 100644 index aab166e6f1..0000000000 --- a/zephyr/shim/chip/npcx/include/rom_chip.h +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_ROM_CHIP_H -#define __CROS_EC_ROM_CHIP_H - -#include "common.h" - -/* Enumerations of ROM api functions */ -enum API_SIGN_OPTIONS_T { - SIGN_NO_CHECK = 0, - SIGN_CRC_CHECK = 1, -}; - -enum API_RETURN_STATUS_T { - /* Successful download */ - API_RET_STATUS_OK = 0, - /* Address is outside of flash or not 4 bytes aligned. */ - API_RET_STATUS_INVALID_SRC_ADDR = 1, - /* Address is outside of RAM or not 4 bytes aligned. */ - API_RET_STATUS_INVALID_DST_ADDR = 2, - /* Size is 0 or not 4 bytes aligned. */ - API_RET_STATUS_INVALID_SIZE = 3, - /* Flash Address + Size is out of flash. */ - API_RET_STATUS_INVALID_SIZE_OUT_OF_FLASH = 4, - /* RAM Address + Size is out of RAM. */ - API_RET_STATUS_INVALID_SIZE_OUT_OF_RAM = 5, - /* Wrong sign option. */ - API_RET_STATUS_INVALID_SIGN = 6, - /* Error during Code copy. */ - API_RET_STATUS_COPY_FAILED = 7, - /* Execution Address is outside of RAM */ - API_RET_STATUS_INVALID_EXE_ADDR = 8, - /* Bad CRC value */ - API_RET_STATUS_INVALID_SIGNATURE = 9, -}; - -/* Macro functions of ROM api functions */ -#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40) -#define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \ - status) \ - (((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \ - (src_offset, dest_addr, size, sign, exe_addr, status)) - -/* Declarations of ROM api functions */ -typedef void (*download_from_flash_ptr) ( - uint32_t src_offset, /* The offset of the data to be downloaded */ - uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ - uint32_t size, /* Number of bytes to download */ - enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */ - uint32_t exe_addr, /* jump to this address after download if not zero */ - enum API_RETURN_STATUS_T *status /* Status fo download */ -); - -#endif /* __CROS_EC_ROM_CHIP_H */ diff --git a/zephyr/shim/chip/npcx/include/system_chip.h b/zephyr/shim/chip/npcx/include/system_chip.h deleted file mode 100644 index c77c2a8338..0000000000 --- a/zephyr/shim/chip/npcx/include/system_chip.h +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_SYSTEM_CHIP_H_ -#define __CROS_EC_SYSTEM_CHIP_H_ - -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) - -/* TODO(b:179900857) Clean this up too */ -#undef IS_BIT_SET -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) - -/*****************************************************************************/ -/* Memory mapping */ -#define CONFIG_LPRAM_BASE 0x40001400 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ - -/******************************************************************************/ -/* Optional M4 Registers */ -#define CPU_MPU_CTRL REG32(0xE000ED94) -#define CPU_MPU_RNR REG32(0xE000ED98) -#define CPU_MPU_RBAR REG32(0xE000ED9C) -#define CPU_MPU_RASR REG32(0xE000EDA0) - -/* - * Region assignment. 7 as the highest, a higher index has a higher priority. - * For example, using 7 for .iram.text allows us to mark entire RAM XN except - * .iram.text, which is used for hibernation. - * Region assignment is currently wasteful and can be changed if more - * regions are needed in the future. For example, a second region may not - * be necessary for all types, and REGION_CODE_RAM / REGION_STORAGE can be - * made mutually exclusive. - */ -enum mpu_region { - REGION_DATA_RAM = 0, /* For internal data RAM */ - REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ - REGION_CODE_RAM = 2, /* For internal code RAM */ - REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ - REGION_STORAGE = 4, /* For mapped internal storage */ - REGION_STORAGE2 = 5, /* Second region for unaligned size */ - REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ - REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ - /* only for chips with MPU supporting 16 regions */ - REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ - REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ - REGION_ROLLBACK = 10, /* For rollback */ -}; - -/* - * Configure the specific memory addresses in the the MPU - * (Memory Protection Unit) for Nuvoton different chip series. - */ -void system_mpu_config(void); - -/* The utilities and variables depend on npcx chip family */ -#if defined(CONFIG_SOC_SERIES_NPCX5) || \ - defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API) -/* Bypass for GMDA issue of ROM api utilities only on npcx5 series or if - * CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API is defined. - */ -void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr); - -/* Begin address for hibernate utility; defined in linker script */ -extern unsigned int __flash_lpfw_start; - -/* End address for hibernate utility; defined in linker script */ -extern unsigned int __flash_lpfw_end; - -/* Begin address for little FW; defined in linker script */ -extern unsigned int __flash_lplfw_start; - -/* End address for little FW; defined in linker script */ -extern unsigned int __flash_lplfw_end; -#endif - -#endif // __CROS_EC_SYSTEM_CHIP_H_ diff --git a/zephyr/shim/chip/npcx/keyboard_raw.c b/zephyr/shim/chip/npcx/keyboard_raw.c deleted file mode 100644 index aa075d2d56..0000000000 --- a/zephyr/shim/chip/npcx/keyboard_raw.c +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Functions needed by keyboard scanner module for Chrome EC */ - -#include <device.h> -#include <logging/log.h> -#include <soc.h> -#include <soc_gpio.h> -#include <zephyr.h> - -#include "drivers/cros_kb_raw.h" -#include "keyboard_raw.h" - -/** - * Return true if the current value of the given input GPIO port is zero - */ -int keyboard_raw_is_input_low(int port, int id) -{ - const struct device *io_dev = npcx_get_gpio_dev(port); - - return gpio_pin_get_raw(io_dev, id) == 0; -} diff --git a/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt b/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt deleted file mode 100644 index 661eb86e91..0000000000 --- a/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt +++ /dev/null @@ -1,47 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# The NPCX monitor source needs the chip type and flash layout information -# provided by the board configuration. This is provided by -# zephyr/shim/include/config_chip.h, so we need all the include directories -# of the Zephyr application. -zephyr_get_include_directories_for_lang(C zephyr_includes STRIP_PREFIX) - -# Something in the zephyr_get_compile_options_for_lang() output causes the -# "-imacros" option to get dropped during expansion when passed to -# target_compile_options(). Fetch the compile options directly from -# zephyr_interface which works as expected. -get_property( - zephyr_compile_options - TARGET zephyr_interface - PROPERTY INTERFACE_COMPILE_OPTIONS - ) - -add_executable(npcx_monitor npcx_monitor.c) -target_include_directories(npcx_monitor PRIVATE - "${PLATFORM_EC}/zephyr/shim/include" - "${PLATFORM_EC}/zephyr/shim/chip/npcx/include" - ) -target_include_directories(npcx_monitor PRIVATE "${zephyr_includes}") -target_compile_options(npcx_monitor PRIVATE "${zephyr_compile_options}") - -target_link_options(npcx_monitor BEFORE PRIVATE - -nostdlib - -g - -mthumb - -Wl,-T,${CMAKE_CURRENT_SOURCE_DIR}/npcx_monitor.ld - ) - -# Create the NPCX monitor binary, locate it the root of the build -# directory as it needs to be found by the flash_util script -set(npcx_monitor_elf ${CMAKE_CURRENT_BINARY_DIR}/npcx_monitor.elf) -set(npcx_monitor_bin ${CMAKE_BINARY_DIR}/npcx_monitor.bin) - -add_custom_target(generate_npcx_monitor - COMMAND ${CMAKE_OBJCOPY} -O binary ${npcx_monitor_elf} ${npcx_monitor_bin} - BYPRODUCTS ${npcx_monitor_bin} - DEPENDS npcx_monitor - ) - -add_dependencies(zephyr generate_npcx_monitor) diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c deleted file mode 100644 index 2bd9455a91..0000000000 --- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c +++ /dev/null @@ -1,343 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * NPCX SoC spi flash update tool - monitor firmware - */ - -#include <stdint.h> -#include <sys/util.h> -#include "config_chip.h" -#include "npcx_monitor.h" -#include "registers.h" - -/* - * TODO(b/197162681): This was copied from chip/npcx/spiflashfw but this - * needs to be moved to Zephyr upstream - */ - -/*****************************************************************************/ -/* spi flash internal functions */ -void sspi_flash_pinmux(int enable) -{ - if (enable) - CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); - else - SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); - - /* CS0/1 pinmux */ - if (enable) { -#if (FIU_CHIP_SELECT == 1) - SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1); -#elif (FIU_CHIP_SELECT == 2) - SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2); -#endif - } else { - CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1); - CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2); - } -} - -void sspi_flash_tristate(int enable) -{ - if (enable) { - /* Enable FIU pins to tri-state */ - SET_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS); - } else { - /* Disable FIU pins to tri-state */ - CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS); - } -} - -void sspi_flash_execute_cmd(uint8_t code, uint8_t cts) -{ - /* set UMA_CODE */ - NPCX_UMA_CODE = code; - /* execute UMA flash transaction */ - NPCX_UMA_CTS = cts; - while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) - ; -} - -void sspi_flash_cs_level(int level) -{ - /* level is high */ - if (level) { - /* Set chip select to high */ - SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1); - } else { /* level is low */ - /* Set chip select to low */ - CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1); - } -} - -void sspi_flash_wait_ready(void) -{ - uint8_t mask = SPI_FLASH_SR1_BUSY; - - /* Chip Select down. */ - sspi_flash_cs_level(0); - /* Command for Read status register */ - sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY); - do { - /* Read status register */ - NPCX_UMA_CTS = MASK_RD_1BYTE; - while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) - ; - } while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */ - /* Chip Select high. */ - sspi_flash_cs_level(1); -} - -int sspi_flash_write_enable(void) -{ - uint8_t mask = SPI_FLASH_SR1_WEL; - /* Write enable command */ - sspi_flash_execute_cmd(CMD_WRITE_EN, MASK_CMD_ONLY); - /* Wait for flash is not busy */ - sspi_flash_wait_ready(); - - if (NPCX_UMA_DB0 & mask) - return 1; - else - return 0; -} - -void sspi_flash_set_address(uint32_t dest_addr) -{ - uint8_t *addr = (uint8_t *)&dest_addr; - /* Write address */ - NPCX_UMA_AB2 = addr[2]; - NPCX_UMA_AB1 = addr[1]; - NPCX_UMA_AB0 = addr[0]; -} - -void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes, - const char *data) -{ - unsigned int i; - /* Chip Select down. */ - sspi_flash_cs_level(0); - /* Set erase address */ - sspi_flash_set_address(dest_addr); - /* Start write */ - sspi_flash_execute_cmd(CMD_FLASH_PROGRAM, MASK_CMD_WR_ADR); - for (i = 0; i < bytes; i++) { - sspi_flash_execute_cmd(*data, MASK_CMD_WR_ONLY); - data++; - } - /* Chip Select up */ - sspi_flash_cs_level(1); -} - -int sspi_flash_physical_clear_stsreg(void) -{ - /* Disable tri-state */ - sspi_flash_tristate(0); - /* Enable write */ - sspi_flash_write_enable(); - - NPCX_UMA_DB0 = 0x0; - NPCX_UMA_DB1 = 0x0; - - /* Write status register 1/2 */ - sspi_flash_execute_cmd(CMD_WRITE_STATUS_REG, MASK_CMD_WR_2BYTE); - - /* Wait writing completed */ - sspi_flash_wait_ready(); - - /* Read status register 1/2 for checking */ - sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_RD_1BYTE); - if (NPCX_UMA_DB0 != 0x00) - return 0; - sspi_flash_execute_cmd(CMD_READ_STATUS_REG2, MASK_CMD_RD_1BYTE); - if (NPCX_UMA_DB0 != 0x00) - return 0; - /* Enable tri-state */ - sspi_flash_tristate(1); - - return 1; -} - -void sspi_flash_physical_write(int offset, int size, const char *data) -{ - int dest_addr = offset; - const int sz_page = CONFIG_FLASH_WRITE_IDEAL_SIZE; - - /* Disable tri-state */ - sspi_flash_tristate(0); - - /* Write the data per CONFIG_FLASH_WRITE_IDEAL_SIZE bytes */ - for (; size >= sz_page; size -= sz_page) { - /* Enable write */ - sspi_flash_write_enable(); - /* Burst UMA transaction */ - sspi_flash_burst_write(dest_addr, sz_page, data); - /* Wait write completed */ - sspi_flash_wait_ready(); - - data += sz_page; - dest_addr += sz_page; - } - - /* Handle final partial page, if any */ - if (size != 0) { - /* Enable write */ - sspi_flash_write_enable(); - /* Burst UMA transaction */ - sspi_flash_burst_write(dest_addr, size, data); - - /* Wait write completed */ - sspi_flash_wait_ready(); - } - - /* Enable tri-state */ - sspi_flash_tristate(1); -} - -void sspi_flash_physical_erase(int offset, int size) -{ - /* Disable tri-state */ - sspi_flash_tristate(0); - - /* Alignment has been checked in upper layer */ - for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE, - offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { - /* Enable write */ - sspi_flash_write_enable(); - /* Set erase address */ - sspi_flash_set_address(offset); - /* Start erase */ - sspi_flash_execute_cmd(CMD_SECTOR_ERASE, MASK_CMD_ADR); - - /* Wait erase completed */ - sspi_flash_wait_ready(); - } - - /* Enable tri-state */ - sspi_flash_tristate(1); -} - -int sspi_flash_verify(int offset, int size, const char *data) -{ - int i, result; - uint8_t *ptr_flash; - uint8_t *ptr_mram; - uint8_t cmp_data; - - ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset); - ptr_mram = (uint8_t *)data; - result = 1; - - /* Disable tri-state */ - sspi_flash_tristate(0); - - /* Start to verify */ - for (i = 0; i < size; i++) { - cmp_data = ptr_mram ? ptr_mram[i] : 0xFF; - if (ptr_flash[i] != cmp_data) { - result = 0; - break; - } - } - - /* Enable tri-state */ - sspi_flash_tristate(1); - return result; -} - -int sspi_flash_get_image_used(const char *fw_base) -{ - const uint8_t *image; - int size = MAX(CONFIG_RO_SIZE, CONFIG_RW_SIZE); /* max size is 128KB */ - - image = (const uint8_t *)fw_base; - /* - * Scan backwards looking for 0xea byte, which is by definition the - * last byte of the image. See ec.lds.S for how this is inserted at - * the end of the image. - */ - for (size--; size > 0 && image[size] != 0xea; size--) - ; - - return size ? size + 1 : 0; /* 0xea byte IS part of the image */ - -} - -/* Entry function of spi upload function */ -uint32_t __attribute__ ((section(".startup_text"))) -sspi_flash_upload(int spi_offset, int spi_size) -{ - /* - * Flash image has been uploaded to Code RAM - */ - uint32_t sz_image; - uint32_t uut_tag; - const char *image_base; - uint32_t *flag_upload = (uint32_t *)SPI_PROGRAMMING_FLAG; - struct monitor_header_tag *monitor_header = - (struct monitor_header_tag *)NPCX_MONITOR_HEADER_ADDR; - - *flag_upload = 0; - - uut_tag = monitor_header->tag; - /* If it is UUT tag, read required parameters from header */ - if (uut_tag == NPCX_MONITOR_UUT_TAG) { - sz_image = monitor_header->size; - spi_offset = monitor_header->dest_addr; - image_base = (const char *)(monitor_header->src_addr); - } else { - sz_image = spi_size; - image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE; - } - - /* Unlock & stop watchdog */ - NPCX_WDSDM = 0x87; - NPCX_WDSDM = 0x61; - NPCX_WDSDM = 0x63; - - /* UMA Unlock */ - CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK); - - /* - * If UUT is used, assuming the target is the internal flash. - * Don't switch the pinmux and make sure bit 7 of DEVALT0 is set. - */ - if (uut_tag == NPCX_MONITOR_UUT_TAG) - SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); - else - /* Set pinmux first */ - sspi_flash_pinmux(1); - - /* Get size of image automatically */ - if (sz_image == 0) - sz_image = sspi_flash_get_image_used(image_base); - - /* Clear status reg of spi flash for protection */ - if (sspi_flash_physical_clear_stsreg()) { - /* Start to erase */ - sspi_flash_physical_erase(spi_offset, sz_image); - /* Start to write */ - if (image_base != NULL) - sspi_flash_physical_write(spi_offset, sz_image, - image_base); - /* Verify data */ - if (sspi_flash_verify(spi_offset, sz_image, image_base)) - *flag_upload |= 0x02; - } - if (uut_tag != NPCX_MONITOR_UUT_TAG) - /* Disable pinmux */ - sspi_flash_pinmux(0); - - /* Mark we have finished upload work */ - *flag_upload |= 0x01; - - /* Return the status back to ROM code is required for UUT */ - if (uut_tag == NPCX_MONITOR_UUT_TAG) - return *flag_upload; - - /* Infinite loop */ - for (;;) - ; -} - diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h deleted file mode 100644 index c5415d94db..0000000000 --- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_NPCX_MONITOR_H -#define __CROS_EC_NPCX_MONITOR_H - -#include <stdint.h> - -#define NPCX_MONITOR_UUT_TAG 0xA5075001 -#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 - -/* Flag to record the progress of programming SPI flash */ -#define SPI_PROGRAMMING_FLAG 0x200C4000 - -struct monitor_header_tag { - /* offset 0x00: TAG NPCX_MONITOR_TAG */ - uint32_t tag; - /* offset 0x04: Size of the binary being programmed (in bytes) */ - uint32_t size; - /* offset 0x08: The RAM address of the binary to program into the SPI */ - uint32_t src_addr; - /* offset 0x0C: The Flash address to be programmed (Absolute address) */ - uint32_t dest_addr; - /* offset 0x10: Maximum allowable flash clock frequency */ - uint8_t max_clock; - /* offset 0x11: SPI Flash read mode */ - uint8_t read_mode; - /* offset 0x12: Reserved */ - uint16_t reserved; -} __packed; - -#endif /* __CROS_EC_NPCX_MONITOR_H */ diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld deleted file mode 100644 index 03e38b0609..0000000000 --- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * NPCX SoC spi flash update tool - */ - -/* Memory Spaces Definitions */ -MEMORY -{ - CODERAM (rx) : ORIGIN = 0x200C3020, LENGTH = 0xFE0 -} - -/* - * The entry point is informative, for debuggers and simulators, - * since the Cortex-M vector points to it anyway. - */ -ENTRY(sspi_flash_upload) - - -/* Sections Definitions */ - -SECTIONS -{ - .startup_text : - { - . = ALIGN(4); - *(.startup_text ) /* Startup code */ - . = ALIGN(4); - } >CODERAM - - /* - * The program code is stored in the .text section, - * which goes to CODERAM. - */ - .text : - { - . = ALIGN(4); - *(.text .text.*) /* all remaining code */ - *(.rodata .rodata.*) /* read-only data (constants) */ - } >CODERAM - - . = ALIGN(4); - _etext = .; - - /* - * This address is used by the startup code to - * initialise the .data section. - */ - _sidata = _etext; - -} diff --git a/zephyr/shim/chip/npcx/npcx_monitor/registers.h b/zephyr/shim/chip/npcx/npcx_monitor/registers.h deleted file mode 100644 index cc0a6b96fe..0000000000 --- a/zephyr/shim/chip/npcx/npcx_monitor/registers.h +++ /dev/null @@ -1,360 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for NPCX processor - * - * This is meant to be temporary until the NPCX monitor support is moved - * to Zephyr upstream - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -/* - * The monitor code doesn't build cleanly under the Zephyr environment if - * include/common.h is included. Replicate the register access macros until - * this code is moved upstream. - */ - -/* Macros to access registers */ -#define REG64_ADDR(addr) ((volatile uint64_t *)(addr)) -#define REG32_ADDR(addr) ((volatile uint32_t *)(addr)) -#define REG16_ADDR(addr) ((volatile uint16_t *)(addr)) -#define REG8_ADDR(addr) ((volatile uint8_t *)(addr)) - -#define REG64(addr) (*REG64_ADDR(addr)) -#define REG32(addr) (*REG32_ADDR(addr)) -#define REG16(addr) (*REG16_ADDR(addr)) -#define REG8(addr) (*REG8_ADDR(addr)) - -/* Standard macros / definitions */ -#define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y)) -#define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y)) -#ifndef MAX -#define MAX(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MAX(temp_a, temp_b); \ - }) -#endif -#ifndef MIN -#define MIN(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MIN(temp_a, temp_b); \ - }) -#endif -#ifndef NULL -#define NULL ((void *)0) -#endif - -/******************************************************************************/ -/* - * Macro Functions - */ -/* Bit functions */ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) -#define UPDATE_BIT(reg, bit, cond) { if (cond) \ - SET_BIT(reg, bit); \ - else \ - CLEAR_BIT(reg, bit); } -/* Field functions */ -#define GET_POS_FIELD(pos, size) pos -#define GET_SIZE_FIELD(pos, size) size -#define FIELD_POS(field) GET_POS_##field -#define FIELD_SIZE(field) GET_SIZE_##field -/* Read field functions */ -#define GET_FIELD(reg, field) \ - _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field)) -#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1)) -/* Write field functions */ -#define SET_FIELD(reg, field, value) \ - _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value) -#define _SET_FIELD_(reg, f_pos, f_size, value) \ - ((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \ - | ((value) << (f_pos))) - - -/* NPCX7 & NPCX9 */ -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) - -/******************************************************************************/ -/* - * NPCX (Nuvoton M4 EC) Register Definitions - */ - -/* Modules Map */ -#define NPCX_ESPI_BASE_ADDR 0x4000A000 -#define NPCX_MDC_BASE_ADDR 0x4000C000 -#define NPCX_PMC_BASE_ADDR 0x4000D000 -#define NPCX_SIB_BASE_ADDR 0x4000E000 -#define NPCX_SHI_BASE_ADDR 0x4000F000 -#define NPCX_SHM_BASE_ADDR 0x40010000 -#define NPCX_GDMA_BASE_ADDR 0x40011000 -#define NPCX_FIU_BASE_ADDR 0x40020000 -#define NPCX_KBSCAN_REGS_BASE 0x400A3000 -#define NPCX_WOV_BASE_ADDR 0x400A4000 -#define NPCX_APM_BASE_ADDR 0x400A4800 -#define NPCX_GLUE_REGS_BASE 0x400A5000 -#define NPCX_BBRAM_BASE_ADDR 0x400AF000 -#define NPCX_PS2_BASE_ADDR 0x400B1000 -#define NPCX_HFCG_BASE_ADDR 0x400B5000 -#define NPCX_LFCG_BASE_ADDR 0x400B5100 -#define NPCX_FMUL2_BASE_ADDR 0x400B5200 -#define NPCX_MTC_BASE_ADDR 0x400B7000 -#define NPCX_MSWC_BASE_ADDR 0x400C1000 -#define NPCX_SCFG_BASE_ADDR 0x400C3000 -#define NPCX_KBC_BASE_ADDR 0x400C7000 -#define NPCX_ADC_BASE_ADDR 0x400D1000 -#define NPCX_SPI_BASE_ADDR 0x400D2000 -#define NPCX_PECI_BASE_ADDR 0x400D4000 -#define NPCX_TWD_BASE_ADDR 0x400D8000 - -/* Multi-Modules Map */ -#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl) * 0x2000L)) -#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl) * 0x2000L)) -#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl) * 0x2000L)) -#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl) * 0x2000L)) -#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl) * 0x2000L)) -#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl) * 0x2000L)) - - -/******************************************************************************/ -/* System Configuration (SCFG) Registers */ -#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000) -#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001) -#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002) -#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006) -#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021) -#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028) -#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029) -#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F) - -#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037) -#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038) -#define BLKSEL 0 - -/* SCFG register fields */ -#define NPCX_DEVCNT_F_SPI_TRIS 6 -#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) -#define NPCX_DEVCNT_JEN1_HEN 5 -#define NPCX_DEVCNT_JEN0_HEN 4 -#define NPCX_STRPST_TRIST 1 -#define NPCX_STRPST_TEST 2 -#define NPCX_STRPST_JEN1 4 -#define NPCX_STRPST_JEN0 5 -#define NPCX_STRPST_SPI_COMP 7 -#define NPCX_RSTCTL_VCC1_RST_STS 0 -#define NPCX_RSTCTL_DBGRST_STS 1 -#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3 -#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5 -#define NPCX_RSTCTL_HIPRST_MODE 6 -#define NPCX_DEV_CTL4_F_SPI_SLLK 2 -#define NPCX_DEV_CTL4_SPI_SP_SEL 4 -#define NPCX_DEV_CTL4_WP_IF 5 -#define NPCX_DEV_CTL4_VCC1_RST_LK 6 -#define NPCX_DEVPU0_I2C0_0_PUE 0 -#define NPCX_DEVPU0_I2C0_1_PUE 1 -#define NPCX_DEVPU0_I2C1_0_PUE 2 -#define NPCX_DEVPU0_I2C2_0_PUE 4 -#define NPCX_DEVPU0_I2C3_0_PUE 6 -#define NPCX_DEVPU1_F_SPI_PUD_EN 7 - -/* DEVALT */ -/* pin-mux for SPI/FIU */ -#define NPCX_DEVALT0_SPIP_SL 0 -#define NPCX_DEVALT0_GPIO_NO_SPIP 3 -#define NPCX_DEVALT0_F_SPI_CS1_2 4 -#define NPCX_DEVALT0_F_SPI_CS1_1 5 -#define NPCX_DEVALT0_F_SPI_QUAD 6 -#define NPCX_DEVALT0_NO_F_SPI 7 - -/******************************************************************************/ -/* Flash Interface Unit (FIU) Registers */ -#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000) -#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001) -#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002) -#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014) -#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016) -#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017) -#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018) -#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019) -#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A) -#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B) -#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C) -#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D) -#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E) -#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F) -#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020) -#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030) -#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032) -#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033) -#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034) - -/* FIU register fields */ -#define NPCX_RESP_CFG_IAD_EN 0 -#define NPCX_RESP_CFG_DEV_SIZE_EX 2 -#define NPCX_UMA_CTS_A_SIZE 3 -#define NPCX_UMA_CTS_C_SIZE 4 -#define NPCX_UMA_CTS_RD_WR 5 -#define NPCX_UMA_CTS_DEV_NUM 6 -#define NPCX_UMA_CTS_EXEC_DONE 7 -#define NPCX_UMA_ECTS_SW_CS0 0 -#define NPCX_UMA_ECTS_SW_CS1 1 -#define NPCX_UMA_ECTS_SEC_CS 2 -#define NPCX_UMA_ECTS_UMA_LOCK 3 - -/******************************************************************************/ -/* KBC Registers */ -#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000) -#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002) -#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004) -#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006) -#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008) -#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009) -#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A) -#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B) - -/* KBC register field */ -#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */ -#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/ -#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */ -#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */ -#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */ -#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */ -#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */ -#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */ - -#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */ - -/******************************************************************************/ -/* Timer Watch Dog (TWD) Registers */ -#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000) -#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002) -#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004) -#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006) -#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008) -#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A) -#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C) -#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E) -#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010) - -/* TWD register fields */ -#define NPCX_TWCFG_LTWCFG 0 -#define NPCX_TWCFG_LTWCP 1 -#define NPCX_TWCFG_LTWDT0 2 -#define NPCX_TWCFG_LWDCNT 3 -#define NPCX_TWCFG_WDCT0I 4 -#define NPCX_TWCFG_WDSDME 5 -#define NPCX_TWCFG_WDRST_MODE 6 -#define NPCX_TWCFG_WDC2POR 7 -#define NPCX_T0CSR_RST 0 -#define NPCX_T0CSR_TC 1 -#define NPCX_T0CSR_WDLTD 3 -#define NPCX_T0CSR_WDRST_STS 4 -#define NPCX_T0CSR_WD_RUN 5 -#define NPCX_T0CSR_TESDIS 7 - -/******************************************************************************/ -/* SPI Register */ -#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00) -#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02) -#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04) - -/* SPI register fields */ -#define NPCX_SPI_CTL1_SPIEN 0 -#define NPCX_SPI_CTL1_SNM 1 -#define NPCX_SPI_CTL1_MOD 2 -#define NPCX_SPI_CTL1_EIR 5 -#define NPCX_SPI_CTL1_EIW 6 -#define NPCX_SPI_CTL1_SCM 7 -#define NPCX_SPI_CTL1_SCIDL 8 -#define NPCX_SPI_CTL1_SCDV 9 -#define NPCX_SPI_STAT_BSY 0 -#define NPCX_SPI_STAT_RBF 1 - -/******************************************************************************/ -/* Flash Utiltiy definition */ -/* - * Flash commands for the W25Q16CV SPI flash - */ -#define CMD_READ_ID 0x9F -#define CMD_READ_MAN_DEV_ID 0x90 -#define CMD_WRITE_EN 0x06 -#define CMD_WRITE_STATUS 0x50 -#define CMD_READ_STATUS_REG 0x05 -#define CMD_READ_STATUS_REG2 0x35 -#define CMD_WRITE_STATUS_REG 0x01 -#define CMD_FLASH_PROGRAM 0x02 -#define CMD_SECTOR_ERASE 0x20 -#define CMD_BLOCK_32K_ERASE 0x52 -#define CMD_BLOCK_64K_ERASE 0xd8 -#define CMD_PROGRAM_UINT_SIZE 0x08 -#define CMD_PAGE_SIZE 0x00 -#define CMD_READ_ID_TYPE 0x47 -#define CMD_FAST_READ 0x0B - -/* - * Status registers for the W25Q16CV SPI flash - */ -#define SPI_FLASH_SR2_SUS BIT(7) -#define SPI_FLASH_SR2_CMP BIT(6) -#define SPI_FLASH_SR2_LB3 BIT(5) -#define SPI_FLASH_SR2_LB2 BIT(4) -#define SPI_FLASH_SR2_LB1 BIT(3) -#define SPI_FLASH_SR2_QE BIT(1) -#define SPI_FLASH_SR2_SRP1 BIT(0) -#define SPI_FLASH_SR1_SRP0 BIT(7) -#define SPI_FLASH_SR1_SEC BIT(6) -#define SPI_FLASH_SR1_TB BIT(5) -#define SPI_FLASH_SR1_BP2 BIT(4) -#define SPI_FLASH_SR1_BP1 BIT(3) -#define SPI_FLASH_SR1_BP0 BIT(2) -#define SPI_FLASH_SR1_WEL BIT(1) -#define SPI_FLASH_SR1_BUSY BIT(0) - - -/* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */ -#define FIU_CHIP_SELECT 0 -/* Create UMA control mask */ -#define MASK(bit) (0x1 << (bit)) -#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ -#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ -#define RD_WR 0x05 /* 0: Read 1: Write */ -#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ -#define EXEC_DONE 0x07 -#define D_SIZE_1 0x01 -#define D_SIZE_2 0x02 -#define D_SIZE_3 0x03 -#define D_SIZE_4 0x04 -#define FLASH_SEL MASK(DEV_NUM) - -#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) -#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) -#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - |MASK(A_SIZE) | D_SIZE_1) -#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) -#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) -#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) -#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) -#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) -#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) -#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) -#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) -#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) -#define MASK_CMD_WR_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_1) -#define MASK_CMD_WR_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_2) -#define MASK_CMD_WR_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(A_SIZE)) - - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/zephyr/shim/chip/npcx/power_policy.c b/zephyr/shim/chip/npcx/power_policy.c deleted file mode 100644 index 803ac51e9b..0000000000 --- a/zephyr/shim/chip/npcx/power_policy.c +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <zephyr.h> -#include <pm/pm.h> -#include <soc.h> - -#include "console.h" -#include "cros_version.h" -#include "system.h" - -static const struct pm_state_info pm_min_residency[] = - PM_STATE_INFO_DT_ITEMS_LIST(DT_NODELABEL(cpu0)); - -/* CROS PM policy handler */ -struct pm_state_info pm_policy_next_state(int32_t ticks) -{ - /* Deep sleep is allowed and console is not in use. */ - if (DEEP_SLEEP_ALLOWED != 0 && !npcx_power_console_is_in_use()) { - for (int i = ARRAY_SIZE(pm_min_residency) - 1; i >= 0; i--) { - /* Find suitable power state by residency time */ - if (ticks == K_TICKS_FOREVER || - ticks >= k_us_to_ticks_ceil32( - pm_min_residency[i] - .min_residency_us)) { - return pm_min_residency[i]; - } - } - } - - return (struct pm_state_info){ PM_STATE_ACTIVE, 0, 0 }; -} diff --git a/zephyr/shim/chip/npcx/shi.c b/zephyr/shim/chip/npcx/shi.c deleted file mode 100644 index 22b153a806..0000000000 --- a/zephyr/shim/chip/npcx/shi.c +++ /dev/null @@ -1,87 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Functions needed by Serial Host Interface module for Chrome EC */ - -#include <device.h> -#include <dt-bindings/clock/npcx_clock.h> -#include <logging/log.h> -#include <soc.h> -#include <zephyr.h> - -#include "chipset.h" -#include "drivers/cros_shi.h" -#include "hooks.h" -#include "host_command.h" -#include "system.h" - -LOG_MODULE_REGISTER(shim_cros_shi, LOG_LEVEL_DBG); - -#define SHI_NODE DT_NODELABEL(shi) - -static void shi_enable(void) -{ - const struct device *cros_shi_dev = DEVICE_DT_GET(SHI_NODE); - - if (!device_is_ready(cros_shi_dev)) { - LOG_ERR("Error: device %s is not ready", cros_shi_dev->name); - return; - } - - LOG_INF("%s", __func__); - cros_shi_enable(cros_shi_dev); -} -#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK -DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, shi_enable, HOOK_PRIO_DEFAULT); -#else -DECLARE_HOOK(HOOK_CHIPSET_RESUME, shi_enable, HOOK_PRIO_DEFAULT); -#endif - -static void shi_reenable_on_sysjump(void) -{ - if (IS_ENABLED(CONFIG_CROS_SHI_NPCX_DEBUG) || - (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))) { - shi_enable(); - } -} -/* Call hook after chipset sets initial power state */ -DECLARE_HOOK(HOOK_INIT, shi_reenable_on_sysjump, HOOK_PRIO_INIT_CHIPSET + 1); - -static void shi_disable(void) -{ - const struct device *cros_shi_dev = DEVICE_DT_GET(SHI_NODE); - - if (!device_is_ready(cros_shi_dev)) { - LOG_ERR("Error: device %s is not ready", cros_shi_dev->name); - return; - } - - LOG_INF("%s", __func__); - cros_shi_disable(cros_shi_dev); -} -#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND_COMPLETE, shi_disable, HOOK_PRIO_DEFAULT); -#else -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, shi_disable, HOOK_PRIO_DEFAULT); -#endif -DECLARE_HOOK(HOOK_SYSJUMP, shi_disable, HOOK_PRIO_DEFAULT); - -/* Get protocol information */ -static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, '\0', sizeof(*r)); - r->protocol_versions = BIT(3); - r->max_request_packet_size = CONFIG_CROS_SHI_MAX_REQUEST; - r->max_response_packet_size = CONFIG_CROS_SHI_MAX_RESPONSE; - r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED; - - args->response_size = sizeof(*r); - - return EC_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info, - EC_VER_MASK(0)); diff --git a/zephyr/shim/chip/npcx/system.c b/zephyr/shim/chip/npcx/system.c deleted file mode 100644 index 9809e138d5..0000000000 --- a/zephyr/shim/chip/npcx/system.c +++ /dev/null @@ -1,97 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <drivers/bbram.h> -#include <logging/log.h> - -#include "system.h" -#include "system_chip.h" - -LOG_MODULE_REGISTER(shim_npcx_system, LOG_LEVEL_ERR); - -static void chip_bbram_status_check(void) -{ - const struct device *bbram_dev; - int res; - - bbram_dev = DEVICE_DT_GET(DT_NODELABEL(bbram)); - if (!device_is_ready(bbram_dev)) { - LOG_ERR("Error: device %s is not ready", bbram_dev->name); - return; - } - - res = bbram_check_invalid(bbram_dev); - if (res != 0 && res != -ENOTSUP) - LOG_INF("VBAT power drop!"); - - res = bbram_check_standby_power(bbram_dev); - if (res != 0 && res != -ENOTSUP) - LOG_INF("VSBY power drop!"); - - res = bbram_check_power(bbram_dev); - if (res != 0 && res != -ENOTSUP) - LOG_INF("VCC1 power drop!"); -} - -/* - * Configure address 0x40001600 (Low Power RAM) in the the MPU - * (Memory Protection Unit) as a "regular" memory - */ -void system_mpu_config(void) -{ - if (!IS_ENABLED(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API)) - return; - - /* - * npcx9 Rev.1 has the problem for download_from_flash API. - * Workaround it by implementing the system_download_from_flash function - * in the suspend RAM. The functions will do the same, but will provide - * a software solution similar to what's done in the npcx5. - */ - /* Enable MPU */ - CPU_MPU_CTRL = 0x7; - - /* Create a new MPU Region to allow execution from low-power ram */ - CPU_MPU_RNR = REGION_CHIP_RESERVED; - CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */ - CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ - /* - * Set region size & attribute and enable region - * [31:29] - Reserved. - * [28] - XN (Execute Never) = 0 - * [27] - Reserved. - * [26:24] - AP = 011 (Full access) - * [23:22] - Reserved. - * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory) - * [15:8] - SRD = 0 (Subregions enabled) - * [7:6] - Reserved. - * [5:1] - SIZE = 01001 (1K) - * [0] - ENABLE = 1 (enabled) - */ - CPU_MPU_RASR = 0x03080013; -} - -static int chip_system_init(const struct device *unused) -{ - ARG_UNUSED(unused); - - /* - * Check BBRAM power status. - */ - chip_bbram_status_check(); - - system_mpu_config(); - - return 0; -} -/* - * The priority should be lower than CROS_BBRAM_NPCX_INIT_PRIORITY. - */ -#if (CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY <= CONFIG_BBRAM_INIT_PRIORITY) -#error CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY must greater than \ - CONFIG_BBRAM_INIT_PRIORITY -#endif -SYS_INIT(chip_system_init, PRE_KERNEL_1, - CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY); diff --git a/zephyr/shim/chip/npcx/system_download_from_flash.c b/zephyr/shim/chip/npcx/system_download_from_flash.c deleted file mode 100644 index 28ec22962c..0000000000 --- a/zephyr/shim/chip/npcx/system_download_from_flash.c +++ /dev/null @@ -1,159 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include <dt-bindings/clock/npcx_clock.h> -#include <stdnoreturn.h> -#include <sys/__assert.h> - -#include "common.h" -#include "soc.h" -#include "system_chip.h" - -/* Modules Map */ -#define NPCX_PMC_BASE_ADDR 0x4000D000 -#define NPCX_GDMA_BASE_ADDR 0x40011000 - -/******************************************************************************/ -/* GDMA (General DMA) Registers */ -#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) -#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) -#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) -#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) - -/******************************************************************************/ -/* GDMA register fields */ -#define NPCX_GDMA_CTL_GDMAEN 0 -#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) -#define NPCX_GDMA_CTL_DADIR 4 -#define NPCX_GDMA_CTL_SADIR 5 -#define NPCX_GDMA_CTL_SAFIX 7 -#define NPCX_GDMA_CTL_SIEN 8 -#define NPCX_GDMA_CTL_BME 9 -#define NPCX_GDMA_CTL_SBMS 11 -#define NPCX_GDMA_CTL_TWS FIELD(12, 2) -#define NPCX_GDMA_CTL_DM 15 -#define NPCX_GDMA_CTL_SOFTREQ 16 -#define NPCX_GDMA_CTL_TC 18 -#define NPCX_GDMA_CTL_GDMAERR 20 -#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 - -/******************************************************************************/ -/* Low Power RAM definitions */ -#define NPCX_LPRAM_CTRL REG32(0x40001044) - -/******************************************************************************/ -/* Sysjump utilities in low power ram for npcx series. */ -noreturn void __keep __attribute__ ((section(".lowpower_ram2"))) -__start_gdma(uint32_t exeAddr) -{ - /* Enable GDMA now */ - SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN); - - /* Start GDMA */ - SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_SOFTREQ); - - /* Wait for transfer to complete/fail */ - while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) && - !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) - ; - - /* Disable GDMA now */ - CLEAR_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN); - - /* - * Failure occurs during GMDA transaction. Let watchdog issue and - * boot from RO region again. - */ - if (IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) - while (1) - ; - - /* - * Jump to the exeAddr address if needed. Setting bit 0 of address to - * indicate it's a thumb branch for cortex-m series CPU. - */ - ((void (*)(void))(exeAddr | 0x01))(); - - /* Should never get here */ - while (1) - ; -} - -/* Begin address of Suspend RAM for little FW (GDMA utilities). */ -#define LFW_OFFSET 0x160 -uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET; - -void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr) -{ - int i; - uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */ - /* - * GDMA utility in Suspend RAM. Setting bit 0 of address to indicate - * it's a thumb branch for cortex-m series CPU. - */ - void (*__start_gdma_in_lpram)(uint32_t) = - (void(*)(uint32_t))(__lpram_lfw_start | 0x01); - - /* - * Before enabling burst mode for better performance of GDMA, it's - * important to make sure srcAddr, dstAddr and size of transactions - * are 16 bytes aligned in case failure occurs. - */ - __ASSERT_NO_MSG((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 && - (dstAddr % chunkSize) == 0); - - /* Check valid address for jumpiing */ - __ASSERT_NO_MSG(exeAddr != 0x0); - - /* Enable power for the Low Power RAM */ - CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_BASE_ADDR, NPCX_PWDWN_CTL6), 6); - - /* Enable Low Power RAM */ - NPCX_LPRAM_CTRL = 1; - - /* - * Initialize GDMA for flash reading. - * [31:21] - Reserved. - * [20] - GDMAERR = 0 (Indicate GMDA transfer error) - * [19] - Reserved. - * [18] - TC = 0 (Terminal Count. Indicate operation is end.) - * [17] - Reserved. - * [16] - SOFTREQ = 0 (Don't trigger here) - * [15] - DM = 0 (Set normal demand mode) - * [14] - Reserved. - * [13:12] - TWS. = 10 (One double-word for every GDMA transaction) - * [11:10] - Reserved. - * [9] - BME = 1 (4-data ie.16 bytes - Burst mode enable) - * [8] - SIEN = 0 (Stop interrupt disable) - * [7] - SAFIX = 0 (Fixed source address) - * [6] - Reserved. - * [5] - SADIR = 0 (Source address incremented) - * [4] - DADIR = 0 (Destination address incremented) - * [3:2] - GDMAMS = 00 (Software mode) - * [1] - Reserved. - * [0] - ENABLE = 0 (Don't enable yet) - */ - NPCX_GDMA_CTL = 0x00002200; - - /* Set source base address */ - NPCX_GDMA_SRCB = CONFIG_MAPPED_STORAGE_BASE + srcAddr; - - /* Set destination base address */ - NPCX_GDMA_DSTB = dstAddr; - - /* Set number of transfers */ - NPCX_GDMA_TCNT = (size / chunkSize); - - /* Clear Transfer Complete event */ - SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC); - - /* Copy the __start_gdma_in_lpram instructions to LPRAM */ - for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++) - *((uint32_t *)__lpram_lfw_start + i) = - *(&__flash_lplfw_start + i); - - /* Start GDMA in Suspend RAM */ - __start_gdma_in_lpram(exeAddr); -} diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c deleted file mode 100644 index 373a4a48f7..0000000000 --- a/zephyr/shim/chip/npcx/system_external_storage.c +++ /dev/null @@ -1,157 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <devicetree.h> -#include <drivers/syscon.h> - -#include "clock_chip.h" -#include "common.h" -#include "rom_chip.h" -#include "system.h" -#include "system_chip.h" - -/* TODO (b:179900857) Make this implementation not npcx specific. */ - -static const struct device *mdc_dev = DEVICE_DT_GET(DT_NODELABEL(mdc)); - -#ifdef CONFIG_SOC_SERIES_NPCX7 -#define NPCX_FWCTRL 0x007 -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 -#elif defined(CONFIG_SOC_SERIES_NPCX9) -#define NPCX_FWCTRL 0x009 -#define NPCX_FWCTRL_RO_REGION 6 -#define NPCX_FWCTRL_FW_SLOT 7 -#else -#error "Unsupported NPCX SoC series." -#endif - -void system_jump_to_booter(void) -{ - enum API_RETURN_STATUS_T status __attribute__((unused)); - static uint32_t flash_offset; - static uint32_t flash_used; - static uint32_t addr_entry; - - /* - * Get memory offset and size for RO/RW regions. - * Both of them need 16-bytes alignment since GDMA burst mode. - */ - switch (system_get_shrspi_image_copy()) { - case EC_IMAGE_RW: - flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF; - flash_used = CONFIG_RW_SIZE; - break; -#ifdef CONFIG_RW_B - case EC_IMAGE_RW_B: - flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_B_STORAGE_OFF; - flash_used = CONFIG_RW_SIZE; - break; -#endif - case EC_IMAGE_RO: - default: /* Jump to RO by default */ - flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF; - flash_used = CONFIG_RO_SIZE; - break; - } - - /* Make sure the reset vector is inside the destination image */ - addr_entry = *(uintptr_t *)(flash_offset + - CONFIG_MAPPED_STORAGE_BASE + 4); - - /* - * Speed up FW download time by increasing clock freq of EC. It will - * restore to default in clock_init() later. - */ - clock_turbo(); - -/* - * npcx9 Rev.1 has the problem for download_from_flash API. - * Workwaroud it by executing the system_download_from_flash function - * in the suspend RAM like npcx5. - * TODO: Removing npcx9 when Rev.2 is available. - */ - /* Bypass for GMDA issue of ROM api utilities */ -#if defined(CONFIG_SOC_SERIES_NPCX5) || \ - defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API) - system_download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - addr_entry /* jump to this address after download */ - ); -#else - download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - SIGN_NO_CHECK, /* Need CRC check or not */ - addr_entry, /* jump to this address after download */ - &status /* Status fo download */ - ); -#endif -} - -uint32_t system_get_lfw_address() -{ - /* - * In A3 version, we don't use little FW anymore - * We provide the alternative function in ROM - */ - uint32_t jump_addr = (uint32_t)system_jump_to_booter; - return jump_addr; -} - -enum ec_image system_get_shrspi_image_copy(void) -{ - uint32_t fwctrl = 0; - - syscon_read_reg(mdc_dev, NPCX_FWCTRL, &fwctrl); - if (IS_BIT_SET(fwctrl, NPCX_FWCTRL_RO_REGION)) { - /* RO image */ -#ifdef CHIP_HAS_RO_B - if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT)) - return EC_IMAGE_RO_B; -#endif - return EC_IMAGE_RO; - } else { -#ifdef CONFIG_RW_B - /* RW image */ - if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT)) - /* Slot A */ - return EC_IMAGE_RW_B; -#endif - return EC_IMAGE_RW; - } -} - -void system_set_image_copy(enum ec_image copy) -{ - uint32_t fwctrl = 0; - - syscon_read_reg(mdc_dev, NPCX_FWCTRL, &fwctrl); - switch (copy) { - case EC_IMAGE_RW: - CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION); - SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT); - break; -#ifdef CONFIG_RW_B - case EC_IMAGE_RW_B: - CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION); - CLEAR_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT); - break; -#endif - default: - /* Fall through to EC_IMAGE_RO */ - case EC_IMAGE_RO: - SET_BIT(fwctrl, NPCX_FWCTRL_RO_REGION); - SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT); - break; - } - syscon_write_reg(mdc_dev, NPCX_FWCTRL, fwctrl); -} diff --git a/zephyr/shim/chip/posix/CMakeLists.txt b/zephyr/shim/chip/posix/CMakeLists.txt deleted file mode 100644 index 70e8b6269a..0000000000 --- a/zephyr/shim/chip/posix/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ESPI espi.c)
\ No newline at end of file diff --git a/zephyr/shim/chip/posix/espi.c b/zephyr/shim/chip/posix/espi.c deleted file mode 100644 index cf348744d7..0000000000 --- a/zephyr/shim/chip/posix/espi.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <sys/util.h> -#include "zephyr_espi_shim.h" - -#define ACPI_TYPE_POS 0U -#define ACPI_DATA_POS 8U - -/* 8042 event data format */ -#define POSIX_8042_EVT_POS 16U -#define POSIX_8042_DATA_POS 8U -#define POSIX_8042_TYPE_POS 0U - -/* 8042 event type format */ -#define POSIX_8042_EVT_IBF BIT(0) -#define POSIX_8042_EVT_OBE BIT(1) - -bool is_acpi_command(uint32_t data) -{ - return (data >> ACPI_TYPE_POS) & 0x01; -} - -uint32_t get_acpi_value(uint32_t data) -{ - return (data >> ACPI_TYPE_POS) & 0xff; -} - -bool is_POSIX_8042_ibf(uint32_t data) -{ - return (data >> POSIX_8042_EVT_POS) & POSIX_8042_EVT_IBF; -} - -bool is_POSIX_8042_obe(uint32_t data) -{ - return (data >> POSIX_8042_EVT_POS) & POSIX_8042_EVT_OBE; -} - -uint32_t get_POSIX_8042_type(uint32_t data) -{ - return (data >> POSIX_8042_TYPE_POS) & 0xFF; -} - -uint32_t get_POSIX_8042_data(uint32_t data) -{ - return (data >> POSIX_8042_DATA_POS) & 0xFF; -} |