diff options
| author | Andrew McRae <amcrae@google.com> | 2022-03-12 02:11:51 +1100 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-03-14 23:12:57 +0000 |
| commit | 28cff5cfd2e602f91395b273edf80a6a09b280c0 (patch) | |
| tree | 9995360f7d8799c1d943b0a6d3b47a6a818e9ed8 /zephyr/subsys/ap_pwrseq/include | |
| parent | a8a0294eff990eea7304df932496e19376efd821 (diff) | |
| download | chrome-ec-28cff5cfd2e602f91395b273edf80a6a09b280c0.tar.gz | |
ap_pwrseq: Directly access DTS config properties
Directly access DTS config properties so that when
external board level functions are defined, they can can also
access the configuration properties.
BUG=b:223923728
TEST=zmake build nivviks; flash and run
BRANCH=none
Signed-off-by: Andrew McRae <amcrae@google.com>
Change-Id: Id97e03fdc743de1e1a645c19a9a514626986534a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3516768
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Tested-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Diffstat (limited to 'zephyr/subsys/ap_pwrseq/include')
3 files changed, 5 insertions, 33 deletions
diff --git a/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h b/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h index 5762a2b14c..fd84ac49ce 100644 --- a/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h +++ b/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h @@ -66,4 +66,8 @@ struct pwrseq_context { #endif }; + +#define AP_PWRSEQ_DT_VALUE(p) \ + DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(intel_ap_pwrseq), p) + #endif /* __X86_COMMON_PWRSEQ_H__ */ diff --git a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_adlp_pwrseq_sm.h b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_adlp_pwrseq_sm.h deleted file mode 100644 index dda2b2e52b..0000000000 --- a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_adlp_pwrseq_sm.h +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __X86_NON_DSX_ADLP_PWRSEQ_SM_H__ -#define __X86_NON_DSX_ADLP_PWRSEQ_SM_H__ - -#include <x86_common_pwrseq.h> -#include <x86_non_dsx_common_pwrseq_sm_handler.h> - -struct chipset_pwrseq_config { - int pch_pwrok_delay_ms; - int sys_pwrok_delay_ms; - int sys_reset_delay_ms; - int vccst_pwrgd_delay_ms; - int vrrdy_timeout_ms; - int all_sys_pwrgd_timeout; -}; - -#endif /* __X86_NON_DSX_ADLP_PWRSEQ_SM_H__ */ diff --git a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h index 648045cfc0..96d938faf0 100644 --- a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h +++ b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h @@ -17,21 +17,10 @@ #define DT_DRV_COMPAT intel_ap_pwrseq -/* Common device tree configurable attributes */ -struct common_pwrseq_config { - int pch_dsw_pwrok_delay_ms; - int pch_pm_pwrbtn_delay_ms; - int pch_rsmrst_delay_ms; - int wait_signal_timeout_ms; - int s5_timeout_s; -}; - /* The wait time is ~150 msec, allow for safety margin. */ #define IN_PCH_SLP_SUS_WAIT_TIME_MS 250 -enum power_states_ndsx chipset_pwr_sm_run( - enum power_states_ndsx curr_state, - const struct common_pwrseq_config *com_cfg); +enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state); void init_chipset_pwr_seq_state(void); void request_exit_hardoff(bool should_exit); enum power_states_ndsx pwr_sm_get_state(void); |