ap_pwrseq: Trigger power sequence events from chipset

This CL decouples power events generation from power sequence state
action handlers, instead AP power sequence driver will generate power
events using driver API `ap_pwrseq_register_entry_state_callback` and
`ap_pwrseq_register_exit_state_callback`.

BUG=b:217952699
BRANCH=none
TEST=zmake build

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Idadcee50a2ca1dfcb81fe4b550841854ad4258ad
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4079732
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: Peter Marheine <pmarheine@chromium.org>
Commit-Queue: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>

1 files changed, 119 insertions, 0 deletions

diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
index e4da35b095..a8db0bdefe 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
@@ -4,6 +4,7 @@
  */
 
 #ifdef CONFIG_AP_PWRSEQ_DRIVER
+#include <ap_power/ap_power_events.h>
 #include <ap_power/ap_pwrseq_sm.h>
 #endif
 #include <x86_common_pwrseq.h>
@@ -94,6 +95,124 @@ enum power_states_ndsx chipset_pwr_seq_get_state(void)
 	return SYS_POWER_STATE_G3;
 }
 #else
+static void x86_non_dsx_chipset_state_entry_cb(const struct device *dev,
+					       const enum ap_pwrseq_state entry,
+					       const enum ap_pwrseq_state exit)
+{
+	switch (entry) {
+	case AP_POWER_STATE_G3:
+		if (exit >= AP_POWER_STATE_S5) {
+			ap_power_ev_send_callbacks(AP_POWER_HARD_OFF);
+		}
+		ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN);
+		ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN_COMPLETE);
+		break;
+
+	case AP_POWER_STATE_S3:
+		ap_power_ev_send_callbacks(AP_POWER_STARTUP);
+		break;
+
+	case AP_POWER_STATE_S0:
+		/* Notify power event rails are up */
+		ap_power_ev_send_callbacks(AP_POWER_RESUME);
+		break;
+
+#if CONFIG_AP_PWRSEQ_S0IX
+	case AP_POWER_STATE_S0IX:
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_SUSPEND);
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		ap_power_ev_send_callbacks(AP_POWER_SUSPEND_COMPLETE);
+#endif
+		break;
+#endif
+
+	default:
+		break;
+	}
+}
+
+static void x86_non_dsx_chipset_state_exit_cb(const struct device *dev,
+					      const enum ap_pwrseq_state entry,
+					      const enum ap_pwrseq_state exit)
+{
+	switch (exit) {
+	case AP_POWER_STATE_G3:
+		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+		break;
+
+	case AP_POWER_STATE_S3:
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		if (entry == AP_POWER_STATE_S0) {
+			/* Notify power event before resume */
+			ap_power_ev_send_callbacks(AP_POWER_RESUME_INIT);
+		}
+#endif
+		break;
+
+	case AP_POWER_STATE_S0:
+		ap_power_ev_send_callbacks(AP_POWER_SUSPEND);
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		if (entry == AP_POWER_STATE_S3) {
+			/* Notify power event after suspend */
+			ap_power_ev_send_callbacks(AP_POWER_SUSPEND_COMPLETE);
+		}
+#endif
+		break;
+
+#if CONFIG_AP_PWRSEQ_S0IX
+	case AP_POWER_STATE_S0IX:
+#if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
+		ap_power_ev_send_callbacks(AP_POWER_RESUME_INIT);
+#endif
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_RESUME);
+		break;
+#endif
+
+	default:
+		break;
+	}
+}
+
+static int x86_non_dsx_chipset_init_events(const struct device *dev)
+{
+	static struct ap_pwrseq_state_callback ap_pwrseq_entry_cb;
+	static struct ap_pwrseq_state_callback ap_pwrseq_exit_cb;
+	const struct device *ap_pwrseq_dev = ap_pwrseq_get_instance();
+
+	ARG_UNUSED(dev);
+	power_signal_init();
+
+	ap_pwrseq_entry_cb.cb = x86_non_dsx_chipset_state_entry_cb;
+	ap_pwrseq_entry_cb.states_bit_mask =
+		(BIT(AP_POWER_STATE_G3) | BIT(AP_POWER_STATE_S3) |
+		 BIT(AP_POWER_STATE_S0)
+#if CONFIG_AP_PWRSEQ_S0IX
+		 | BIT(AP_POWER_STATE_S0IX)
+#endif
+		);
+
+	ap_pwrseq_register_state_entry_callback(ap_pwrseq_dev,
+						&ap_pwrseq_entry_cb);
+
+	ap_pwrseq_exit_cb.cb = x86_non_dsx_chipset_state_exit_cb;
+	ap_pwrseq_exit_cb.states_bit_mask =
+		(BIT(AP_POWER_STATE_G3) | BIT(AP_POWER_STATE_S3) |
+		 BIT(AP_POWER_STATE_S0)
+#if CONFIG_AP_PWRSEQ_S0IX
+		 | BIT(AP_POWER_STATE_S0IX)
+#endif
+		);
+
+	ap_pwrseq_register_state_exit_callback(ap_pwrseq_dev,
+					       &ap_pwrseq_exit_cb);
+
+	ap_power_ev_send_callbacks(AP_POWER_INITIALIZED);
+
+	return 0;
+}
+SYS_INIT(x86_non_dsx_chipset_init_events, APPLICATION,
+	 CONFIG_APPLICATION_INIT_PRIORITY);
+
 enum ap_pwrseq_state chipset_pwr_seq_get_state(void)
 {
 	power_signal_mask_t sig;