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| author | Grzegorz Bernacki <bernacki@google.com> | 2023-02-02 11:31:14 +0000 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-04-14 10:16:17 +0000 |
| commit | 4ffe5a5da01205ede49e2f001d9c3e1412ea4d64 (patch) | |
| tree | 02219c8c6b1ef77523e2d3d82e432af05f1ef93d /zephyr/subsys | |
| parent | 93389d7454e223043435804ba34b8fc1b39903d0 (diff) | |
| download | chrome-ec-4ffe5a5da01205ede49e2f001d9c3e1412ea4d64.tar.gz | |
ap_pwrseq: Add s0ix counter
This commit adds counter which increments every time EC detects
going into S0ix state.
BUG=b:261869264
TEST=Tested on nissa
BRANCH=none
Change-Id: I2a35411eb085924c95129d98bb7b2be2bdc013a7
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4239442
Reviewed-by: Robert Zieba <robertzieba@google.com>
Diffstat (limited to 'zephyr/subsys')
| -rw-r--r-- | zephyr/subsys/ap_pwrseq/Kconfig | 9 | ||||
| -rw-r--r-- | zephyr/subsys/ap_pwrseq/power_host_sleep.c | 8 |
2 files changed, 16 insertions, 1 deletions
diff --git a/zephyr/subsys/ap_pwrseq/Kconfig b/zephyr/subsys/ap_pwrseq/Kconfig index 9eaa37c017..8bb064aac9 100644 --- a/zephyr/subsys/ap_pwrseq/Kconfig +++ b/zephyr/subsys/ap_pwrseq/Kconfig @@ -169,6 +169,15 @@ config AP_PWRSEQ_S0IX_ERROR_RECOVERY Failure information is reported via the EC_CMD_HOST_SLEEP_EVENT host command. +config AP_PWRSEQ_S0IX_COUNTER + bool "Enable S0ix counter" + depends on AP_PWRSEQ_S0IX + depends on AP_PWRSEQ_HOST_SLEEP + default y + help + Enables counter which increases at every transitions to S0ix state. + Counter can be read via host command. + config AP_PWRSEQ_DEBUG_MODE_COMMAND bool "Console commands to enable/disable AP debug mode" depends on X86_NON_DSX_PWRSEQ diff --git a/zephyr/subsys/ap_pwrseq/power_host_sleep.c b/zephyr/subsys/ap_pwrseq/power_host_sleep.c index 96335b066b..82e84a02fd 100644 --- a/zephyr/subsys/ap_pwrseq/power_host_sleep.c +++ b/zephyr/subsys/ap_pwrseq/power_host_sleep.c @@ -192,6 +192,10 @@ enum ap_power_sleep_type ap_power_sleep_get_notify(void) return sleep_state; } +#ifdef CONFIG_AP_PWRSEQ_S0IX_COUNTER +atomic_t s0ix_counter; +#endif + void ap_power_sleep_notify_transition(enum ap_power_sleep_type check_state) { if (sleep_state != check_state) @@ -204,6 +208,9 @@ void ap_power_sleep_notify_transition(enum ap_power_sleep_type check_state) */ power_s0ix_suspend_clear_masks(); ap_power_ev_send_callbacks(AP_POWER_SUSPEND); +#ifdef CONFIG_AP_PWRSEQ_S0IX_COUNTER + atomic_inc(&s0ix_counter); +#endif } else if (check_state == AP_POWER_SLEEP_RESUME) { ap_power_ev_send_callbacks(AP_POWER_RESUME); /* @@ -251,7 +258,6 @@ void ap_power_chipset_handle_host_sleep_event( ap_power_sleep_set_notify(AP_POWER_SLEEP_SUSPEND); ap_power_ev_send_callbacks(AP_POWER_S0IX_SUSPEND_START); power_signal_enable(PWR_SLP_S0); - } else if (state == HOST_SLEEP_EVENT_S0IX_RESUME) { /* * Set sleep state to resume; restore SCI/SMI masks; |