diff options
| -rw-r--r-- | chip/npcx/flash.c | 36 | ||||
| -rw-r--r-- | chip/npcx/gpio.c | 8 | ||||
| -rw-r--r-- | common/spi_flash_reg.c | 10 |
3 files changed, 54 insertions, 0 deletions
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c index 457cbf4c91..9c73bbdb3c 100644 --- a/chip/npcx/flash.c +++ b/chip/npcx/flash.c @@ -191,6 +191,18 @@ static uint8_t flash_get_status2(void) return ret; } +#ifdef NPCX_INT_FLASH_SUPPORT +static void flash_protect_int_flash(int enable) +{ + /* + * Please notice the type of WP_IF bit is R/W1S. Once it's set, + * only rebooting EC can clear it. + */ + if (enable && !IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF)) + SET_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF); +} +#endif + #ifdef CONFIG_HOSTCMD_FLASH_SPI_INFO void flash_get_mfr_dev_id(uint8_t *dest) @@ -263,6 +275,14 @@ static int flash_set_status_for_prot(int reg1, int reg2) flash_uma_lock(0); } + /* + * If WP# is active and ec doesn't protect the status registers of + * internal spi-flash, protect it now before setting them. + */ +#ifdef NPCX_INT_FLASH_SUPPORT + flash_protect_int_flash(!gpio_get_level(GPIO_WP_L)); +#endif + /* Lock physical flash operations */ flash_lock_mapped_storage(1); @@ -308,6 +328,14 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes) uint8_t sr1, sr2; int rv = EC_SUCCESS; + /* + * If WP# is active and ec doesn't protect the status registers of + * internal spi-flash, protect it now. + */ +#ifdef NPCX_INT_FLASH_SUPPORT + flash_protect_int_flash(!gpio_get_level(GPIO_WP_L)); +#endif + sr1 = flash_get_status1(); sr2 = flash_get_status2(); @@ -647,6 +675,14 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) int flash_pre_init(void) { + /* + * Protect status registers of internal spi-flash if WP# is active + * during ec initialization. + */ +#ifdef NPCX_INT_FLASH_SUPPORT + flash_protect_int_flash(!gpio_get_level(GPIO_WP_L)); +#endif + /* Enable FIU interface */ flash_pinmux(1); diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index db9be12b1d..1b32297013 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -360,6 +360,14 @@ void gpio_pre_init(void) int flags; int i, j; +#ifdef CHIP_FAMILY_NPCX7 + /* + * TODO: Set bit 7 of DEVCNT again for npcx7 series. Please see Errata + * for more information. It will be fixed in next chip. + */ + SET_BIT(NPCX_DEVCNT, 7); +#endif + /* Pin_Mux for FIU/SPI (set to GPIO) */ SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP); SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); diff --git a/common/spi_flash_reg.c b/common/spi_flash_reg.c index 547fe06d6c..2e9fbbd469 100644 --- a/common/spi_flash_reg.c +++ b/common/spi_flash_reg.c @@ -63,6 +63,16 @@ static const struct protect_range spi_flash_protect_ranges[] = { { 0, 0, 1, { 1, 1, 0 }, 0, 0x400000 }, /* Lower 1/2 */ { 0, 0, 1, { 1, 0, 1 }, 0, 0x200000 }, /* Lower 1/4 */ }; + +#elif defined(CONFIG_SPI_FLASH_W25Q80) +static const struct protect_range spi_flash_protect_ranges[] = { + /* CMP = 0 */ + { 0, X, X, { 0, 0, 0 }, 0, 0 }, /* No protection */ + { 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/8 */ + { 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/4 */ + { 0, 0, 1, { 1, 0, 0 }, 0, 0x80000 }, /* Lower 1/2 */ +}; + #endif /** |