diff options
| -rw-r--r-- | board/glados/board.c | 38 | ||||
| -rw-r--r-- | board/glados/board.h | 29 | ||||
| -rw-r--r-- | board/glados/build.mk | 1 | ||||
| -rw-r--r-- | board/glados/ec.tasklist | 4 | ||||
| -rw-r--r-- | board/glados/gpio.inc | 6 | ||||
| -rw-r--r-- | board/glados/usb_pd_policy.c | 352 | ||||
| l--------- | board/glados_pd/Makefile | 1 | ||||
| -rw-r--r-- | board/glados_pd/board.c | 105 | ||||
| -rw-r--r-- | board/glados_pd/board.h | 94 | ||||
| -rw-r--r-- | board/glados_pd/build.mk | 13 | ||||
| -rw-r--r-- | board/glados_pd/ec.tasklist | 23 | ||||
| -rw-r--r-- | board/glados_pd/gpio.inc | 63 | ||||
| -rw-r--r-- | board/glados_pd/usb_pd_config.h | 327 |
13 files changed, 1052 insertions, 4 deletions
diff --git a/board/glados/board.c b/board/glados/board.c index ecbb85552f..7645929225 100644 --- a/board/glados/board.c +++ b/board/glados/board.c @@ -17,8 +17,14 @@ #include "power.h" #include "power_button.h" #include "switch.h" +#include "task.h" +#include "timer.h" +#include "usb_pd_tcpm.h" #include "util.h" +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) + #define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP) #define GPIO_KB_OUTPUT (GPIO_ODR_HIGH) @@ -27,14 +33,18 @@ /* Exchange status with PD MCU. */ static void pd_mcu_interrupt(enum gpio_signal signal) { + hook_call_deferred(tcpc_alert, 0); } void vbus0_evt(enum gpio_signal signal) { + CPRINTF("VBUS C0, %d\n", !gpio_get_level(signal)); + task_wake(TASK_ID_PD); } void vbus1_evt(enum gpio_signal signal) { + CPRINTF("VBUS C1, %d\n", !gpio_get_level(signal)); } void usb0_evt(enum gpio_signal signal) @@ -75,6 +85,23 @@ int board_discharge_on_ac(int enable) return charger_discharge_on_ac(enable); } +/** + * Reset PD MCU + */ +void board_reset_pd_mcu(void) +{ + gpio_set_level(GPIO_PD_RST_L, 0); + usleep(100); + gpio_set_level(GPIO_PD_RST_L, 1); +} + +void __board_i2c_set_timeout(int port, uint32_t timeout) +{ +} + +void i2c_set_timeout(int port, uint32_t timeout) + __attribute__((weak, alias("__board_i2c_set_timeout"))); + struct motion_sensor_t motion_sensors[] = { }; @@ -95,3 +122,14 @@ static void pmic_init(void) i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x38, 0x7a); } DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, pmic_init, HOOK_PRIO_DEFAULT); + +/* Initialize board. */ +static void board_init(void) +{ + /* Enable PD MCU interrupt */ + gpio_enable_interrupt(GPIO_PD_MCU_INT); + /* Enable VBUS interrupt */ + gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L); + gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L); +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/glados/board.h b/board/glados/board.h index 393c12182d..e7476cb3ff 100644 --- a/board/glados/board.h +++ b/board/glados/board.h @@ -31,6 +31,13 @@ #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_COMMON +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_CUSTOM_VDM +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_PORT_COUNT 1 +#define CONFIG_USB_PD_TCPM_TCPCI #define CONFIG_SCI_GPIO GPIO_PCH_SCI_L #define CONFIG_SPI_PORT 1 @@ -50,6 +57,7 @@ #define I2C_PORT_BATTERY MEC1322_I2C0_0 #define I2C_PORT_CHARGER MEC1322_I2C0_0 #define I2C_PORT_PD_MCU MEC1322_I2C1 +#define I2C_PORT_TCPC MEC1322_I2C1 #define I2C_PORT_ALS MEC1322_I2C2 #define I2C_PORT_ACCEL MEC1322_I2C2 #define I2C_PORT_PMIC MEC1322_I2C3 @@ -72,8 +80,29 @@ enum power_signal { POWER_SIGNAL_COUNT }; +/* start as a sink in case we have no other power supply/battery */ +#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED + +/* TODO: determine the following board specific type-C power constants */ +/* + * delay to turn on the power supply max is ~16ms. + * delay to turn off the power supply max is about ~180ms. + */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ + +/* Define typical operating power and max power */ +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 + /* Discharge battery when on AC power for factory test. */ int board_discharge_on_ac(int enable); + +/* Reset PD MCU */ +void board_reset_pd_mcu(void); + #endif /* !__ASSEMBLER__ */ #endif /* __BOARD_H */ diff --git a/board/glados/build.mk b/board/glados/build.mk index 51dfe75e15..3995654f1e 100644 --- a/board/glados/build.mk +++ b/board/glados/build.mk @@ -12,3 +12,4 @@ CHIP_SPI_SIZE_KB:=512 board-y=board.o led.o board-$(CONFIG_BATTERY_SMART)+=battery.o +board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/board/glados/ec.tasklist b/board/glados/ec.tasklist index 06f8db5965..481d8dc91c 100644 --- a/board/glados/ec.tasklist +++ b/board/glados/ec.tasklist @@ -21,7 +21,9 @@ TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \ TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \ TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \ TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \ TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \ TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \ - TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD, pd_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/glados/gpio.inc b/board/glados/gpio.inc index a03bb45faf..34a9ee850f 100644 --- a/board/glados/gpio.inc +++ b/board/glados/gpio.inc @@ -19,9 +19,9 @@ GPIO_INT(PCH_SLP_SUS_L, PIN(12), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal GPIO_INT(VOLUME_UP_L, PIN(31), GPIO_INT_FALLING | GPIO_PULL_UP, button_interrupt) GPIO_INT(VOLUME_DOWN_L, PIN(47), GPIO_INT_FALLING | GPIO_PULL_UP, button_interrupt) GPIO_INT(PMIC_INT_L, PIN(50), GPIO_INT_FALLING, power_signal_interrupt) -GPIO_INT(PD_MCU_INT, PIN(122), GPIO_INT_RISING | GPIO_INT_DSLEEP, pd_mcu_interrupt) -GPIO_INT(USB_C0_VBUS_WAKE, PIN(152), GPIO_INT_BOTH, vbus1_evt) -GPIO_INT(USB_C1_VBUS_WAKE, PIN(123), GPIO_INT_BOTH, vbus0_evt) +GPIO_INT(PD_MCU_INT, PIN(122), GPIO_INT_FALLING | GPIO_INT_DSLEEP, pd_mcu_interrupt) +GPIO_INT(USB_C0_VBUS_WAKE_L,PIN(152), GPIO_INT_BOTH, vbus0_evt) +GPIO_INT(USB_C1_VBUS_WAKE_L,PIN(123), GPIO_INT_BOTH, vbus1_evt) GPIO_INT(USB_C0_BC12_INT_L, PIN(124), GPIO_INT_FALLING, usb0_evt) GPIO_INT(USB_C1_BC12_INT_L, PIN(145), GPIO_INT_FALLING, usb1_evt) /* Delayed PWR_OK from PMIC */ diff --git a/board/glados/usb_pd_policy.c b/board/glados/usb_pd_policy.c new file mode 100644 index 0000000000..891008f7ce --- /dev/null +++ b/board/glados/usb_pd_policy.c @@ -0,0 +1,352 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "atomic.h" +#include "charge_manager.h" +#include "common.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "timer.h" +#include "util.h" +#include "usb_pd.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP) + +/* TODO: fill in correct source and sink capabilities */ +const uint32_t pd_src_pdo[] = { + PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), +}; +const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); + +const uint32_t pd_snk_pdo[] = { + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_BATT(5000, 20000, 15000), + PDO_VAR(5000, 20000, 3000), +}; +const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); + +int pd_is_valid_input_voltage(int mv) +{ + return 1; +} + +int pd_check_requested_voltage(uint32_t rdo) +{ + int max_ma = rdo & 0x3FF; + int op_ma = (rdo >> 10) & 0x3FF; + int idx = rdo >> 28; + uint32_t pdo; + uint32_t pdo_ma; + + if (!idx || idx > pd_src_pdo_cnt) + return EC_ERROR_INVAL; /* Invalid index */ + + /* check current ... */ + pdo = pd_src_pdo[idx - 1]; + pdo_ma = (pdo & 0x3ff); + if (op_ma > pdo_ma) + return EC_ERROR_INVAL; /* too much op current */ + if (max_ma > pdo_ma) + return EC_ERROR_INVAL; /* too much max current */ + + CPRINTF("Requested %d V %d mA (for %d/%d mA)\n", + ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10, + ((rdo >> 10) & 0x3ff) * 10, (rdo & 0x3ff) * 10); + + return EC_SUCCESS; +} + +void pd_transition_voltage(int idx) +{ + /* No-operation: we are always 5V */ +} + +int pd_set_power_supply_ready(int port) +{ + /* + * TODO: this only works on port 0 for now. need to include + * charge manager to manage CHARGE_L + */ + if (port == 0) { + /* Disable charging */ + gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1); + /* Provide VBUS */ + gpio_set_level(GPIO_USB_C0_5V_EN, 1); + } + return EC_SUCCESS; /* we are ready */ +} + +void pd_power_supply_reset(int port) +{ + /* + * TODO: this only works on port 0 for now. need to include + * charge manager to manage CHARGE_L + */ + if (port == 0) { + /* Disable VBUS */ + gpio_set_level(GPIO_USB_C0_5V_EN, 0); + /* Enable charging */ + gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0); + } +} + +void pd_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ +#ifdef CONFIG_CHARGE_MANAGER + struct charge_port_info charge; + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge); +#endif + /* notify host of power info change */ +} + +void typec_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ +#ifdef CONFIG_CHARGE_MANAGER + struct charge_port_info charge; + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge); +#endif + + /* notify host of power info change */ +} + +int pd_snk_is_vbus_provided(int port) +{ + return !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L : + GPIO_USB_C0_VBUS_WAKE_L); +} + +int pd_board_checks(void) +{ + return EC_SUCCESS; +} + +int pd_check_power_swap(int port) +{ + /* + * Allow power swap as long as we are acting as a dual role device, + * otherwise assume our role is fixed (not in S0 or console command + * to fix our role). + */ + return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0; +} + +int pd_check_data_swap(int port, int data_role) +{ + /* Allow data swap if we are a UFP, otherwise don't allow */ + return (data_role == PD_ROLE_UFP) ? 1 : 0; +} + +void pd_execute_data_swap(int port, int data_role) +{ + /* TODO: need to open/close D+/D- switch based on role */ +} + +void pd_check_pr_role(int port, int pr_role, int partner_pr_swap) +{ + /* If sink, and dual role toggling is on, then switch to source */ + if (partner_pr_swap && pr_role == PD_ROLE_SINK && + pd_get_dual_role() == PD_DRP_TOGGLE_ON) + pd_request_power_swap(port); +} + +void pd_check_dr_role(int port, int dr_role, int partner_dr_swap) +{ + /* If UFP, try to switch to DFP */ + if (partner_dr_swap && dr_role == PD_ROLE_UFP) + pd_request_data_swap(port); +} +/* ----------------- Vendor Defined Messages ------------------ */ +const struct svdm_response svdm_rsp = { + .identity = NULL, + .svids = NULL, + .modes = NULL, +}; + +int pd_custom_vdm(int port, int cnt, uint32_t *payload, + uint32_t **rpayload) +{ + int cmd = PD_VDO_CMD(payload[0]); + uint16_t dev_id = 0; + int is_rw; + + /* make sure we have some payload */ + if (cnt == 0) + return 0; + + switch (cmd) { + case VDO_CMD_VERSION: + /* guarantee last byte of payload is null character */ + *(payload + cnt - 1) = 0; + CPRINTF("version: %s\n", (char *)(payload+1)); + break; + case VDO_CMD_READ_INFO: + case VDO_CMD_SEND_INFO: + /* copy hash */ + if (cnt == 7) { + dev_id = VDO_INFO_HW_DEV_ID(payload[6]); + is_rw = VDO_INFO_IS_RW(payload[6]); + + CPRINTF("DevId:%d.%d SW:%d RW:%d\n", + HW_DEV_ID_MAJ(dev_id), + HW_DEV_ID_MIN(dev_id), + VDO_INFO_SW_DBG_VER(payload[6]), + is_rw); + } else if (cnt == 6) { + /* really old devices don't have last byte */ + pd_dev_store_rw_hash(port, dev_id, payload + 1, + SYSTEM_IMAGE_UNKNOWN); + } + break; + case VDO_CMD_CURRENT: + CPRINTF("Current: %dmA\n", payload[1]); + break; + case VDO_CMD_FLIP: + /* board_flip_usb_mux(port); */ + break; +#ifdef CONFIG_USB_PD_LOGGING + case VDO_CMD_GET_LOG: + pd_log_recv_vdm(port, cnt, payload); + break; +#endif /* CONFIG_USB_PD_LOGGING */ + } + + return 0; +} + +#ifdef CONFIG_USB_PD_ALT_MODE_DFP +static int dp_flags[CONFIG_USB_PD_PORT_COUNT]; + +static void svdm_safe_dp_mode(int port) +{ + /* make DP interface safe until configure */ + dp_flags[port] = 0; + /* board_set_usb_mux(port, TYPEC_MUX_NONE, pd_get_polarity(port)); */ +} + +static int svdm_enter_dp_mode(int port, uint32_t mode_caps) +{ + /* Only enter mode if device is DFP_D capable */ + if (mode_caps & MODE_DP_SNK) { + svdm_safe_dp_mode(port); + return 0; + } + + return -1; +} + +static int svdm_dp_status(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_STATUS | VDO_OPOS(opos)); + payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */ + 0, /* HPD level ... not applicable */ + 0, /* exit DP? ... no */ + 0, /* usb mode? ... no */ + 0, /* multi-function ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON)), + 0, /* power low? ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON))); + return 2; +}; + +static int svdm_dp_config(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + /* board_set_usb_mux(port, TYPEC_MUX_DP, pd_get_polarity(port)); */ + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(MODE_DP_PIN_E, /* sink pins */ + MODE_DP_PIN_E, /* src pins */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ + return 2; +}; + +static void svdm_dp_post_config(int port) +{ + dp_flags[port] |= DP_FLAGS_DP_ON; + if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) + return; +} + +static int svdm_dp_attention(int port, uint32_t *payload) +{ + /* ack */ + return 1; +} + +static void svdm_exit_dp_mode(int port) +{ + svdm_safe_dp_mode(port); + /* gpio_set_level(PORT_TO_HPD(port), 0); */ +} + +static int svdm_enter_gfu_mode(int port, uint32_t mode_caps) +{ + /* Always enter GFU mode */ + return 0; +} + +static void svdm_exit_gfu_mode(int port) +{ +} + +static int svdm_gfu_status(int port, uint32_t *payload) +{ + /* + * This is called after enter mode is successful, send unstructured + * VDM to read info. + */ + pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0); + return 0; +} + +static int svdm_gfu_config(int port, uint32_t *payload) +{ + return 0; +} + +static int svdm_gfu_attention(int port, uint32_t *payload) +{ + return 0; +} + +const struct svdm_amode_fx supported_modes[] = { + { + .svid = USB_SID_DISPLAYPORT, + .enter = &svdm_enter_dp_mode, + .status = &svdm_dp_status, + .config = &svdm_dp_config, + .post_config = &svdm_dp_post_config, + .attention = &svdm_dp_attention, + .exit = &svdm_exit_dp_mode, + }, + { + .svid = USB_VID_GOOGLE, + .enter = &svdm_enter_gfu_mode, + .status = &svdm_gfu_status, + .config = &svdm_gfu_config, + .attention = &svdm_gfu_attention, + .exit = &svdm_exit_gfu_mode, + } +}; +const int supported_modes_cnt = ARRAY_SIZE(supported_modes); +#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ + diff --git a/board/glados_pd/Makefile b/board/glados_pd/Makefile new file mode 120000 index 0000000000..94aaae2c4d --- /dev/null +++ b/board/glados_pd/Makefile @@ -0,0 +1 @@ +../../Makefile
\ No newline at end of file diff --git a/board/glados_pd/board.c b/board/glados_pd/board.c new file mode 100644 index 0000000000..38853f86db --- /dev/null +++ b/board/glados_pd/board.c @@ -0,0 +1,105 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* glados_pd board configuration */ + +#include "adc.h" +#include "adc_chip.h" +#include "common.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "i2c.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) + +void pd_send_ec_int(void) +{ + gpio_set_level(GPIO_EC_INT, 0); + + /* + * Delay long enough to guarantee EC see's the change. + * TODO: make sure this delay is sufficient. + */ + usleep(5); + + gpio_set_level(GPIO_EC_INT, 1); +} + +void vbus0_evt(enum gpio_signal signal) +{ + task_wake(TASK_ID_PD); +} + +void vbus1_evt(enum gpio_signal signal) +{ +#ifdef HAS_TASK_PD_C1 + task_wake(TASK_ID_PD_C1); +#endif +} + +void board_config_pre_init(void) +{ + /* enable SYSCFG clock */ + STM32_RCC_APB2ENR |= 1 << 0; + /* + * the DMA mapping is : + * Chan 2 : TIM1_CH1 (C0 RX) + * Chan 3 : SPI1_TX (C0 TX) + * Chan 4 : TIM3_CH1 (C1 RX) + * Chan 5 : SPI2_TX (C1 TX) + */ +} + +#include "gpio_list.h" + +/* Initialize board. */ +static void board_init(void) +{ + /* Enable interrupts on VBUS transitions. */ + gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L); + gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L); +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); + +/* ADC channels */ +const struct adc_t adc_channels[] = { + /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ + [ADC_C1_CC1_PD] = {"C1_CC1_PD", 3300, 4096, 0, STM32_AIN(0)}, + [ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(2)}, + [ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)}, + [ADC_C1_CC2_PD] = {"C1_CC2_PD", 3300, 4096, 0, STM32_AIN(5)}, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); + +/* I2C ports */ +const struct i2c_port_t i2c_ports[] = { + {"slave", I2C_PORT_SLAVE, 1000, GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA} +}; +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +void tcpc_alert(void) +{ + pd_send_ec_int(); +} + +/****************************************************************************/ +/* Console commands */ +static int command_ec_int(int argc, char **argv) +{ + pd_send_ec_int(); + + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(ecint, command_ec_int, + "", + "Toggle EC interrupt line", + NULL); diff --git a/board/glados_pd/board.h b/board/glados_pd/board.h new file mode 100644 index 0000000000..660610992b --- /dev/null +++ b/board/glados_pd/board.h @@ -0,0 +1,94 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* gladoes_pd board configuration */ + +#ifndef __BOARD_H +#define __BOARD_H + +/* + * The flash size is only 32kB. + * No space for 2 partitions, + * put only RW at the beginning of the flash + */ +#undef CONFIG_FW_INCLUDE_RO +#undef CONFIG_RW_MEM_OFF +#define CONFIG_RW_MEM_OFF 0 +#undef CONFIG_RO_SIZE +#define CONFIG_RO_SIZE 0 +/* Fake full size if we had a RO partition */ +#undef CONFIG_FW_IMAGE_SIZE +#define CONFIG_FW_IMAGE_SIZE (64*1024) + +/* 48 MHz SYSCLK clock frequency */ +#define CPU_CLOCK 48000000 + +/* the UART console is on USART1 (PA9/PA10) */ +#undef CONFIG_UART_CONSOLE +#define CONFIG_UART_CONSOLE 1 + +/* Optional features */ +#define CONFIG_ADC +#define CONFIG_BOARD_PRE_INIT +#define CONFIG_FORCE_CONSOLE_RESUME +#undef CONFIG_HOSTCMD_EVENTS +#define CONFIG_HW_CRC +#define CONFIG_I2C +#undef CONFIG_LID_SWITCH +#undef CONFIG_LOW_POWER_IDLE +#define CONFIG_STM_HWTIMER32 +#undef CONFIG_TASK_PROFILING +#undef CONFIG_UART_TX_BUF_SIZE +#undef CONFIG_UART_TX_DMA +#undef CONFIG_UART_RX_DMA +#define CONFIG_UART_TX_BUF_SIZE 128 +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_INTERNAL_COMP +#define CONFIG_USB_PD_PORT_COUNT 1 +#define CONFIG_USB_PD_TCPC +#define CONFIG_USBC_VCONN +#define CONFIG_VBOOT_HASH +#define CONFIG_WATCHDOG +#undef CONFIG_WATCHDOG_HELP + +/* Use PSTATE embedded in the RO image, not in its own erase block */ +#undef CONFIG_FLASH_PSTATE_BANK +#undef CONFIG_FW_PSTATE_SIZE +#define CONFIG_FW_PSTATE_SIZE 0 + +/* I2C ports configuration */ +#define I2C_PORT_SLAVE 0 +#define I2C_PORT_EC I2C_PORT_SLAVE + +/* slave address for host commands */ +#ifdef HAS_TASK_HOSTCMD +#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR CONFIG_USB_PD_I2C_SLAVE_ADDR +#endif + +#ifndef __ASSEMBLER__ + +/* Timer selection */ +#define TIM_CLOCK32 2 +#define TIM_ADC 3 + +#include "gpio_signal.h" + +/* ADC signal */ +enum adc_channel { + ADC_C1_CC1_PD = 0, + ADC_C0_CC1_PD, + ADC_C0_CC2_PD, + ADC_C1_CC2_PD, + /* Number of ADC channels */ + ADC_CH_COUNT +}; + +/* 1.5A Rp */ +#define PD_SRC_VNC PD_SRC_1_5_VNC_MV +#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV + +#endif /* !__ASSEMBLER__ */ + +#endif /* __BOARD_H */ diff --git a/board/glados_pd/build.mk b/board/glados_pd/build.mk new file mode 100644 index 0000000000..392c3026e3 --- /dev/null +++ b/board/glados_pd/build.mk @@ -0,0 +1,13 @@ +# -*- makefile -*- +# Copyright 2015 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build + +# the IC is STmicro STM32F051C8T +CHIP:=stm32 +CHIP_FAMILY:=stm32f0 +CHIP_VARIANT:=stm32f05x + +board-y=board.o diff --git a/board/glados_pd/ec.tasklist b/board/glados_pd/ec.tasklist new file mode 100644 index 0000000000..c001ade46f --- /dev/null +++ b/board/glados_pd/ec.tasklist @@ -0,0 +1,23 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + */ +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD, pd_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/glados_pd/gpio.inc b/board/glados_pd/gpio.inc new file mode 100644 index 0000000000..67f52124d6 --- /dev/null +++ b/board/glados_pd/gpio.inc @@ -0,0 +1,63 @@ +/* -*- mode:c -*- + * + * Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Interrupts */ +GPIO_INT(USB_C0_VBUS_WAKE_L, PIN(C, 14), GPIO_INT_BOTH, vbus0_evt) +GPIO_INT(USB_C1_VBUS_WAKE_L, PIN(C, 15), GPIO_INT_BOTH, vbus1_evt) + +/* PD RX/TX */ +GPIO(USB_C0_CC1_PD, PIN(A, 2), GPIO_ANALOG) +GPIO(USB_C_REF, PIN(A, 1), GPIO_ANALOG) +GPIO(USB_C1_CC1_PD, PIN(A, 0), GPIO_ANALOG) +GPIO(USB_C0_CC2_PD, PIN(A, 4), GPIO_ANALOG) +GPIO(USB_C1_CC2_PD, PIN(A, 5), GPIO_ANALOG) + +GPIO(USB_C1_CCX_TX_DATA, PIN(B, 14), GPIO_INPUT) +GPIO(USB_C0_CC1_TX_DATA, PIN(B, 4), GPIO_INPUT) +GPIO(USB_C1_CC2_TX_SEL, PIN(B, 0), GPIO_OUT_LOW) /* C1_CC2_TX_SEL */ +GPIO(USB_C0_CC2_TX_DATA, PIN(A, 6), GPIO_INPUT) +GPIO(USB_PD_VBUS_WAKE, PIN(C, 13), GPIO_INPUT) + +GPIO(PP3300_USB_PD_EN, PIN(A, 15), GPIO_OUT_HIGH) +GPIO(USB_C0_CC1_VCONN1_EN, PIN(B, 1), GPIO_OUT_LOW) +GPIO(USB_C0_CC2_VCONN1_EN, PIN(B, 2), GPIO_OUT_LOW) +GPIO(USB_C1_CC1_VCONN1_EN, PIN(B, 9), GPIO_OUT_LOW) +GPIO(USB_C1_CC2_VCONN1_EN, PIN(F, 0), GPIO_OUT_LOW) + +GPIO(USB_C0_HOST_HIGH, PIN(A, 3), GPIO_OUT_LOW) +GPIO(USB_C1_HOST_HIGH, PIN(A, 7), GPIO_OUT_LOW) +GPIO(USB_C0_CC1_ODL, PIN(A, 11), GPIO_ODR_LOW) +GPIO(USB_C0_CC2_ODL, PIN(A, 12), GPIO_ODR_LOW) +GPIO(USB_C1_CC1_ODL, PIN(B, 12), GPIO_ODR_LOW) +GPIO(USB_C1_CC2_ODL, PIN(A, 8), GPIO_ODR_LOW) + +/* + * I2C pins should be configured as inputs until I2C module is + * initialized. This will avoid driving the lines unintentionally. + */ +GPIO(SLAVE_I2C_SCL, PIN(B, 6), GPIO_INPUT) +GPIO(SLAVE_I2C_SDA, PIN(B, 7), GPIO_INPUT) + +/* Case closed debugging. */ +GPIO(EC_INT, PIN(A, 14), GPIO_OUT_HIGH) +UNIMPLEMENTED(WP_L) +UNIMPLEMENTED(ENTERING_RW) + +#if 0 +/* Alternate functions */ +GPIO(USB_C1_TX_CLKOUT, PIN(B, 15), GPIO_OUT_LOW) +GPIO(USB_C0_TX_CLKOUT, PIN(B, 8), GPIO_OUT_LOW) +GPIO(USB_C1_TX_CLKIN, PIN(B, 13), GPIO_OUT_LOW) +GPIO(USB_C0_TX_CLKIN, PIN(B, 3), GPIO_OUT_LOW) +#endif + +ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */ +ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2: SCK(PB13) */ +ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8 */ +ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15 */ +ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0) /* USART1: PA9/PA10 */ +ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 */ diff --git a/board/glados_pd/usb_pd_config.h b/board/glados_pd/usb_pd_config.h new file mode 100644 index 0000000000..345bcf7038 --- /dev/null +++ b/board/glados_pd/usb_pd_config.h @@ -0,0 +1,327 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "adc.h" +#include "chip/stm32/registers.h" +#include "gpio.h" +#include "ec_commands.h" + +/* USB Power delivery board configuration */ + +#ifndef __USB_PD_CONFIG_H +#define __USB_PD_CONFIG_H + +/* Timer selection for baseband PD communication */ +#define TIM_CLOCK_PD_TX_C0 16 +#define TIM_CLOCK_PD_RX_C0 1 +#define TIM_CLOCK_PD_TX_C1 15 +#define TIM_CLOCK_PD_RX_C1 3 + +/* Timer channel */ +#define TIM_TX_CCR_C0 1 +#define TIM_RX_CCR_C0 1 +#define TIM_TX_CCR_C1 2 +#define TIM_RX_CCR_C1 1 + +#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_C1 : TIM_CLOCK_PD_TX_C0) +#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_C1 : TIM_CLOCK_PD_RX_C0) + +/* RX timer capture/compare register */ +#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0)) +#define TIM_CCR_C1 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C1, TIM_RX_CCR_C1)) +#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_C1 : TIM_CCR_C0) + +/* TX and RX timer register */ +#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0)) +#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0)) +#define TIM_REG_TX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C1)) +#define TIM_REG_RX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C1)) +#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_C1 : TIM_REG_TX_C0) +#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_C1 : TIM_REG_RX_C0) + +/* use the hardware accelerator for CRC */ +#define CONFIG_HW_CRC + +/* TX uses SPI1 on PB3-4 for port C0, SPI2 on PB 13-14 for port C1 */ +#define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS) +static inline void spi_enable_clock(int port) +{ + if (port == 0) + STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; + else + STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; +} + +/* DMA for transmit uses DMA CH3 for C0 and DMA_CH5 for C1 */ +#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH5 : STM32_DMAC_CH3) + +/* RX uses COMP1 and TIM1 CH1 on port C0 and COMP2 and TIM3_CH1 for port C1*/ +/* C1 RX use CMP1, TIM3_CH1, DMA_CH4 */ +#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM3_IC1 +/* C0 RX use CMP2, TIM1_CH1, DMA_CH2 */ +#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1 + +#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0) +#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0) +#define TIM_CCR_CS 1 + +/* + * EXTI line 21 is connected to the CMP1 output, + * EXTI line 22 is connected to the CMP2 output, + * C0 uses CMP2, and C1 uses CMP1. + */ +#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22)) + +#define IRQ_COMP STM32_IRQ_COMP +/* triggers packet detection on comparator falling edge */ +#define EXTI_XTSR STM32_EXTI_FTSR + +/* DMA for receive uses DMA_CH2 for C0 and DMA_CH4 for C1 */ +#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH4 : STM32_DMAC_CH2) + +/* the pins used for communication need to be hi-speed */ +static inline void pd_set_pins_speed(int port) +{ + if (port == 0) { + /* 40 MHz pin speed on SPI PB3&4, + * (USB_C0_TX_CLKIN & USB_C0_CC1_TX_DATA) + */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000003C0; + /* 40 MHz pin speed on TIM16_CH1 (PB8), + * (USB_C0_TX_CLKOUT) + */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000; + } else { + /* 40 MHz pin speed on SPI PB13/14, + * (USB_C1_TX_CLKIN & USB_C1_CCX_TX_DATA) + */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000; + /* 40 MHz pin speed on TIM15_CH2 (PB15) */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0xC0000000; + } +} + +/* Reset SPI peripheral used for TX */ +static inline void pd_tx_spi_reset(int port) +{ + if (port == 0) { + /* Reset SPI1 */ + STM32_RCC_APB2RSTR |= (1 << 12); + STM32_RCC_APB2RSTR &= ~(1 << 12); + } else { + /* Reset SPI2 */ + STM32_RCC_APB1RSTR |= (1 << 14); + STM32_RCC_APB1RSTR &= ~(1 << 14); + } +} + +/* Drive the CC line from the TX block */ +static inline void pd_tx_enable(int port, int polarity) +{ + if (port == 0) { + /* put SPI function on TX pin */ + if (polarity) { + /* USB_C0_CC2_TX_DATA: PA6 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_A, 0x0040, 0); + /* MCU ADC PA4 pin output low */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + & ~(3 << (2*4))) /* PA4 disable ADC */ + | (1 << (2*4)); /* Set as GPO */ + gpio_set_level(GPIO_USB_C0_CC2_PD, 0); + } else { + /* USB_C0_CC1_TX_DATA: PB4 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_B, 0x0010, 0); + /* MCU ADC PA2 pin output low */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + & ~(3 << (2*2))) /* PA2 disable ADC */ + | (1 << (2*2)); /* Set as GPO */ + gpio_set_level(GPIO_USB_C0_CC1_PD, 0); + } + } else { + /* put SPI function on TX pin */ + /* USB_C1_CCX_TX_DATA: PB14 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_B, 0x4000, 0); + /* MCU ADC pin output low */ + if (polarity) { + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + & ~(3 << (2*5))) /* PA5 disable ADC */ + | (1 << (2*5)); /* Set as GPO */ + gpio_set_level(GPIO_USB_C1_CC2_PD, 0); + } else { + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + & ~(3 << (2*0))) /* PA0 disable ADC */ + | (1 << (2*0)); /* Set as GPO */ + gpio_set_level(GPIO_USB_C1_CC2_PD, 0); + } + + /* + * There is a pin muxer to select CC1 or CC2 TX_DATA, + * Pin mux is controlled by USB_C1_CC2_TX_SEL pin, + * USB_C1_CC1_TX_DATA will be selected, if polarity is 0, + * USB_C1_CC2_TX_DATA will be selected, if polarity is 1 . + */ + gpio_set_level(GPIO_USB_C1_CC2_TX_SEL, polarity); + } +} + +/* Put the TX driver in Hi-Z state */ +static inline void pd_tx_disable(int port, int polarity) +{ + if (port == 0) { + /* output low on SPI TX to disable the FET */ + if (polarity) {/* PA6 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_A, 0x0040, -1); + /* set ADC PA4 pin to ADC function (Hi-Z) */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + | (3 << (2*4))) /* PA4 as ADC */ + & ~(1 << (2*4)); /* disable GPO */ + } else {/* PB4 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_B, 0x0010, -1); + /* set ADC PA4 pin to ADC function (Hi-Z) */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + | (3 << (2*2))) /* PA2 as ADC */ + & ~(1 << (2*2)); /* disable GPO */ + } + } else { + /* output low on SPI TX to disable the FET (PB14) */ + gpio_set_alternate_function(GPIO_B, 0x4000, -1); + if (polarity) { + /* set ADC PA4 pin to ADC function (Hi-Z) */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + | (3 << (2*5))) /* PA5 as ADC */ + & ~(1 << (2*5)); /* disable GPO */ + } else { + /* set ADC PA4 pin to ADC function (Hi-Z) */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + | (3 << (2*0))) /* PA0 as ADC */ + & ~(1 << (2*0)); /* disable GPO */ + } + } +} + +/* we know the plug polarity, do the right configuration */ +static inline void pd_select_polarity(int port, int polarity) +{ + uint32_t val = STM32_COMP_CSR; + + /* Use window mode so that COMP1 and COMP2 share non-inverting input */ + val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN; + + if (port == 0) { + /* C0 use the right comparator inverted input for COMP2 */ + STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) | + (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */ + : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */ + } else { + /* C1 use the right comparator inverted input for COMP1 */ + STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) | + (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */ + : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */ + } +} + +/* Initialize pins used for TX and put them in Hi-Z */ +static inline void pd_tx_init(void) +{ + gpio_config_module(MODULE_USB_PD, 1); +} +static inline void pd_set_host_mode(int port, int enable) +{ + if (port == 0) { + if (enable) { + /* Pull up for host mode */ + gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_OUTPUT); + gpio_set_level(GPIO_USB_C0_HOST_HIGH, 1); + /* High-Z is used for host mode. */ + gpio_set_level(GPIO_USB_C0_CC1_ODL, 1); + gpio_set_level(GPIO_USB_C0_CC2_ODL, 1); + /* Set TX Hi-Z */ + gpio_set_flags(GPIO_USB_C0_CC1_TX_DATA, GPIO_INPUT); + gpio_set_flags(GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT); + } else { + /* Set HOST_HIGH to High-Z for device mode. */ + gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_INPUT); + /* Pull low for device mode. */ + gpio_set_level(GPIO_USB_C0_CC1_ODL, 0); + gpio_set_level(GPIO_USB_C0_CC2_ODL, 0); + } + } else { + if (enable) { + /* Pull up for host mode */ + gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_OUTPUT); + gpio_set_level(GPIO_USB_C1_HOST_HIGH, 1); + /* High-Z is used for host mode. */ + gpio_set_level(GPIO_USB_C1_CC1_ODL, 1); + gpio_set_level(GPIO_USB_C1_CC2_ODL, 1); + /* Set TX Hi-Z */ + gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT); + } else { + /* Set HOST_HIGH to High-Z for device mode. */ + gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_INPUT); + /* Pull low for device mode. */ + gpio_set_level(GPIO_USB_C1_CC1_ODL, 0); + gpio_set_level(GPIO_USB_C1_CC2_ODL, 0); + } + } +} + +/** + * Initialize various GPIOs and interfaces to safe state at start of pd_task. + * + * These include: + * VBUS, charge path based on power role. + * Physical layer CC transmit. + * VCONNs disabled. + * + * @param port USB-C port number + * @param power_role Power role of device + */ +static inline void pd_config_init(int port, uint8_t power_role) +{ + /* + * Set CC pull resistors, and charge_en and vbus_en GPIOs to match + * the initial role. + */ + pd_set_host_mode(port, power_role); + + /* Initialize TX pins and put them in Hi-Z */ + pd_tx_init(); + + if (port == 0) { + gpio_set_level(GPIO_USB_C0_CC1_VCONN1_EN, 0); + gpio_set_level(GPIO_USB_C0_CC2_VCONN1_EN, 0); + } else { + gpio_set_level(GPIO_USB_C1_CC1_VCONN1_EN, 0); + gpio_set_level(GPIO_USB_C1_CC2_VCONN1_EN, 0); + } +} + +static inline int pd_adc_read(int port, int cc) +{ + if (port == 0) + return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD); + else + return adc_read_channel(cc ? ADC_C1_CC2_PD : ADC_C1_CC1_PD); +} + +static inline void pd_set_vconn(int port, int polarity, int enable) +{ + /* Set VCONN on the opposite CC line from the polarity */ + if (port == 0) { + gpio_set_level(polarity ? GPIO_USB_C0_CC1_VCONN1_EN : + GPIO_USB_C0_CC2_VCONN1_EN, enable); + /* Set TX_DATA pin to Hi-Z */ + gpio_set_flags(polarity ? GPIO_USB_C0_CC1_TX_DATA : + GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT); + } else { + gpio_set_level(polarity ? GPIO_USB_C1_CC1_VCONN1_EN : + GPIO_USB_C1_CC2_VCONN1_EN, enable); + /* Set TX_DATA pin to Hi-Z */ + gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT); + } +} + +#endif /* __USB_PD_CONFIG_H */ + |