diff options
-rw-r--r-- | zephyr/Kconfig | 1 | ||||
-rw-r--r-- | zephyr/Kconfig.watchdog | 3 | ||||
-rw-r--r-- | zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec | 22 | ||||
-rw-r--r-- | zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x | 51 | ||||
-rw-r--r-- | zephyr/linker/CMakeLists.txt | 4 | ||||
-rw-r--r-- | zephyr/linker/mchp-xec-lfw.ld | 19 |
6 files changed, 99 insertions, 1 deletions
diff --git a/zephyr/Kconfig b/zephyr/Kconfig index 639edc1c97..5502ccf868 100644 --- a/zephyr/Kconfig +++ b/zephyr/Kconfig @@ -34,6 +34,7 @@ menuconfig PLATFORM_EC if PLATFORM_EC rsource "shim/chip/npcx/Kconfig.npcx" +rsource "shim/chip/mchp/Kconfig.xec" rsource "Kconfig.adc" rsource "Kconfig.ap_power" rsource "Kconfig.battery" diff --git a/zephyr/Kconfig.watchdog b/zephyr/Kconfig.watchdog index 7d5860ce34..e1a51c29eb 100644 --- a/zephyr/Kconfig.watchdog +++ b/zephyr/Kconfig.watchdog @@ -14,7 +14,7 @@ config PLATFORM_EC_WATCHDOG_PERIOD_MS config PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS int "Leading time of the watchdog warning timer in ms" default 500 - depends on !WDT_NPCX && !WDT_ITE_IT8XXX2 + depends on !WDT_NPCX && !WDT_ITE_IT8XXX2 && !WDT_XEC help Set the leading time of the watchdog warning timer. Chromium EC system uses an auxiliary timer to handle the system warning event. The @@ -23,6 +23,7 @@ config PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS. For the NPCX chip, use WDT_NPCX_DELAY_CYCLES instead of this config. + For the MCHP chip, use WDT_XEC_DELAY_CYCLES instead of this config. For the ITE chip, use CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS instead of this config. diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec new file mode 100644 index 0000000000..d05ad020e7 --- /dev/null +++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec @@ -0,0 +1,22 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# +# This file defines the default config values shared by all MEC chipsets +# + +if SOC_FAMILY_MEC + +# ADC +config PLATFORM_EC_ADC_RESOLUTION + default 10 + +config PLATFORM_EC_ADC_OVERSAMPLING + default 0 + +# Set the system clock +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +endif # SOC_FAMILY_MEC diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x new file mode 100644 index 0000000000..998116c243 --- /dev/null +++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x @@ -0,0 +1,51 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# +# This file defines the correct defaults when using the MEC172x series chipset +# + +if SOC_SERIES_MEC172X + +# +# MEC1727NSZ: 416KB total SRAM as 352 KiB Code and 64 KiB data. +# Top 2KB of data SRAM used by Boot-ROM and a 1KB persistent +# region for customer use. +# 512 KiB internal SPI flash + +# Code RAM base for MEC172x series +# First 4KB reserved for SRAM based EC LFW functionality +# Experiment remove reserve of first 4KB and use ROM load API +config CROS_EC_PROGRAM_MEMORY_BASE + default 0xc0000 + +config CROS_EC_RAM_BASE + default 0xc0000 + +# Data size: 64K - 2K, top 1KB is persistent +config CROS_EC_DATA_RAM_SIZE + default 0x00F800 + +# Code + Data: Top 1KB is peristent +config CROS_EC_RAM_SIZE + default 0x067800 + +config FLASH_SIZE + default 512 + +config CROS_EC_RO_MEM_OFF + default 0x0 + +config CROS_EC_RO_SIZE + default 0x40000 + +# RW firmware in program memory - Identical to RO, only one image loaded at a +# time. +config CROS_EC_RW_MEM_OFF + default 0x0 + +config CROS_EC_RW_SIZE + default 0x40000 + +endif # SOC_SERIES_MEC172X diff --git a/zephyr/linker/CMakeLists.txt b/zephyr/linker/CMakeLists.txt index 71955c6d9d..982e2b0218 100644 --- a/zephyr/linker/CMakeLists.txt +++ b/zephyr/linker/CMakeLists.txt @@ -15,5 +15,9 @@ zephyr_linker_sources(RAM_SECTIONS image_size.ld) zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_NPCX ROM_START SORT_KEY 1 npcx-lfw.ld) +# Little FW with specific purposes used by MCHP XEC EC family +zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_MEC ROM_START SORT_KEY 1 + mchp-xec-lfw.ld) + zephyr_linker_sources(DATA_SECTIONS iterables-ram.ld) zephyr_linker_sources(SECTIONS iterables-rom.ld) diff --git a/zephyr/linker/mchp-xec-lfw.ld b/zephyr/linker/mchp-xec-lfw.ld new file mode 100644 index 0000000000..4c28f16bdf --- /dev/null +++ b/zephyr/linker/mchp-xec-lfw.ld @@ -0,0 +1,19 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +. = ALIGN(4); +__lfw_text_start = .; +*(.lfw.*) +. = ALIGN(4); +__lfw_text_end = .; + +#ifdef CONFIG_PLATFORM_EC_EXTERNAL_STORAGE +. = ALIGN(4); +__flash_lplfw_start = .; +/* QSPI load and jump to EC image */ +KEEP(*(.code_in_sram2)) +. = ALIGN(4); +__flash_lplfw_end = .; +#endif /* CONFIG_PLATFORM_EC_EXTERNAL_STORAGE */ |