diff options
-rw-r--r-- | baseboard/herobrine/baseboard.h | 2 | ||||
-rw-r--r-- | baseboard/trogdor/baseboard.h | 2 | ||||
-rw-r--r-- | board/coral/gpio.inc | 2 | ||||
-rw-r--r-- | board/npcx_evb_arm/board.h | 2 | ||||
-rw-r--r-- | board/reef/gpio.inc | 3 | ||||
-rw-r--r-- | board/reef_mchp/gpio.inc | 3 | ||||
-rw-r--r-- | chip/npcx/build.mk | 2 | ||||
-rw-r--r-- | chip/npcx/gpio-npcx5.c | 2 | ||||
-rw-r--r-- | chip/npcx/gpio-npcx9.c | 2 | ||||
-rw-r--r-- | chip/npcx/gpio.c | 2 | ||||
-rw-r--r-- | chip/npcx/shi_chip.h | 8 | ||||
-rw-r--r-- | docs/configuration/config_ap_to_ec_comm.md | 2 | ||||
-rw-r--r-- | include/config.h | 2 | ||||
-rw-r--r-- | util/config_allowed.txt | 2 | ||||
-rw-r--r-- | zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig | 3 |
15 files changed, 18 insertions, 21 deletions
diff --git a/baseboard/herobrine/baseboard.h b/baseboard/herobrine/baseboard.h index 108f7f8cf5..ae5b2a3d33 100644 --- a/baseboard/herobrine/baseboard.h +++ b/baseboard/herobrine/baseboard.h @@ -42,7 +42,7 @@ #undef CONFIG_PECI -#define CONFIG_HOSTCMD_SHI +#define CONFIG_HOST_INTERFACE_SHI #define CONFIG_HOST_COMMAND_STATUS #define CONFIG_HOSTCMD_SECTION_SORTED #define CONFIG_KEYBOARD_COL2_INVERTED diff --git a/baseboard/trogdor/baseboard.h b/baseboard/trogdor/baseboard.h index 32d797e03a..d361aeaac8 100644 --- a/baseboard/trogdor/baseboard.h +++ b/baseboard/trogdor/baseboard.h @@ -41,7 +41,7 @@ #undef CONFIG_PECI -#define CONFIG_HOSTCMD_SHI +#define CONFIG_HOST_INTERFACE_SHI #define CONFIG_HOST_COMMAND_STATUS #define CONFIG_HOSTCMD_SECTION_SORTED #define CONFIG_KEYBOARD_COL2_INVERTED diff --git a/board/coral/gpio.inc b/board/coral/gpio.inc index 0f3acc3375..da15615c86 100644 --- a/board/coral/gpio.inc +++ b/board/coral/gpio.inc @@ -62,7 +62,7 @@ GPIO(EC_I2C_POWER_SCL, PIN(D, 1), GPIO_INPUT) * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case). * - * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SHI option. + * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOST_INTERFACE_SHI option. */ GPIO(PCH_SMI_L, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */ diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h index c3fd341365..a56cec9783 100644 --- a/board/npcx_evb_arm/board.h +++ b/board/npcx_evb_arm/board.h @@ -11,7 +11,7 @@ /* Optional modules */ #define CONFIG_ADC #define CONFIG_PWM -#define CONFIG_HOSTCMD_SHI /* Used in ARM-based platform for host interface */ +#define CONFIG_HOST_INTERFACE_SHI /* ARM-based platform for host interface */ /* Optional features */ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc index 5bf83f88bc..f508d7a84e 100644 --- a/board/reef/gpio.inc +++ b/board/reef/gpio.inc @@ -67,7 +67,8 @@ GPIO(EC_I2C_POWER_SCL, PIN(D, 1), GPIO_INPUT) * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case). * - * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SHI option. + * See also the NO_LPC_ESPI bit in DEVALT1 and the + * CONFIG_HOST_INTERFACE_SHI option. */ GPIO(PCH_SMI_L, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */ diff --git a/board/reef_mchp/gpio.inc b/board/reef_mchp/gpio.inc index 0385d82102..3274af3bff 100644 --- a/board/reef_mchp/gpio.inc +++ b/board/reef_mchp/gpio.inc @@ -84,7 +84,8 @@ GPIO(EC_I2C_POWER_SCL, PIN(010), GPIO_INPUT) * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case). * - * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SHI option. + * See also the NO_LPC_ESPI bit in DEVALT1 and the + * CONFIG_HOST_INTERFACE_SHI option. */ GPIO(PCH_SMI_L, PIN(0227), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */ diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index f872b2d051..246ab84f34 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -35,7 +35,7 @@ chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o chip-$(CONFIG_HOSTCMD_X86)+=lpc.o chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o chip-$(CONFIG_PECI)+=peci.o -chip-$(CONFIG_HOSTCMD_SHI)+=shi.o +chip-$(CONFIG_HOST_INTERFACE_SHI)+=shi.o chip-$(CONFIG_CEC)+=cec.o # pwm functions are implemented with the fan functions chip-$(CONFIG_PWM)+=pwm.o diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c index 8e7c76abf1..9412aa9d9f 100644 --- a/chip/npcx/gpio-npcx5.c +++ b/chip/npcx/gpio-npcx5.c @@ -179,7 +179,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SHI +#ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c index c5b7e900f7..31ed4e62ac 100644 --- a/chip/npcx/gpio-npcx9.c +++ b/chip/npcx/gpio-npcx9.c @@ -195,7 +195,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SHI +#ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index e740f0aa9f..5f1e3c78b6 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -560,7 +560,7 @@ void gpio_pre_init(void) #endif /* Pin_Mux for LPC & SHI */ -#ifdef CONFIG_HOSTCMD_SHI +#ifdef CONFIG_HOST_INTERFACE_SHI /* Switching to eSPI mode for SHI interface */ NPCX_DEVCNT |= 0x08; /* Alternate Intel bus interface LPC/eSPI to GPIOs first */ diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h index c14aec196e..3fd73e8119 100644 --- a/chip/npcx/shi_chip.h +++ b/chip/npcx/shi_chip.h @@ -5,10 +5,9 @@ /* NPCX-specific SHI module for Chrome EC */ -#ifndef SHI_CHIP_H_ -#define SHI_CHIP_H_ +#ifndef __CROS_EC_SHI_CHIP_H_ +#define __CROS_EC_SHI_CHIP_H_ -#ifdef CONFIG_HOSTCMD_SHI /** * Called when the NSS level changes, signalling the start of a SHI * transaction. @@ -19,6 +18,5 @@ void shi_cs_event(enum gpio_signal signal); #ifdef NPCX_SHI_V2 void shi_cs_gpio_int(enum gpio_signal signal); #endif -#endif -#endif /* SHI_CHIP_H_ */ +#endif /* __CROS_EC_SHI_CHIP_H_ */ diff --git a/docs/configuration/config_ap_to_ec_comm.md b/docs/configuration/config_ap_to_ec_comm.md index c19f781936..0a517401be 100644 --- a/docs/configuration/config_ap_to_ec_comm.md +++ b/docs/configuration/config_ap_to_ec_comm.md @@ -9,7 +9,7 @@ details a system level of the operation of this feature. Configure the AP to EC communication channel, picking exactly one of the following options. -- `CONFIG_HOSTCMD_SHI` - [SPI Host Interface](../ec_terms.md#shi) (SHI) +- `CONFIG_HOST_INTERFACE_SHI` - [SPI Host Interface](../ec_terms.md#shi) (SHI) - `CONFIG_HOST_INTERFACE_HECI` - HECI interface - `CONFIG_HOST_INTERFACE_LPC` - [LPC](../ec_terms.md#lpc) bus - `CONFIG_HOST_INTERFACE_ESPI` - [eSPI](../ec_terms.md#espi) bus diff --git a/include/config.h b/include/config.h index 8ec78bf174..ffebac08a4 100644 --- a/include/config.h +++ b/include/config.h @@ -2395,7 +2395,7 @@ * Accept EC host commands over the SPI host interface. The AP is SPI * controller and the EC is the SPI peripheral for this configuration. */ -#undef CONFIG_HOSTCMD_SHI +#undef CONFIG_HOST_INTERFACE_SHI /* * Host command rate limiting assures EC will have time to process lower diff --git a/util/config_allowed.txt b/util/config_allowed.txt index be80cd1721..8aff943b61 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -509,7 +509,6 @@ CONFIG_HOSTCMD_RATE_LIMITING_PERIOD CONFIG_HOSTCMD_RATE_LIMITING_RECESS CONFIG_HOSTCMD_RWHASHPD CONFIG_HOSTCMD_SECTION_SORTED -CONFIG_HOSTCMD_SHI CONFIG_HOSTCMD_SKUID CONFIG_HOSTCMD_X86 CONFIG_HOST_COMMAND_STATUS @@ -520,6 +519,7 @@ CONFIG_HOST_EVENT_REPORT_MASK CONFIG_HOST_INTERFACE_ESPI CONFIG_HOST_INTERFACE_HECI CONFIG_HOST_INTERFACE_LPC +CONFIG_HOST_INTERFACE_SHI CONFIG_HWTIMER_64BIT CONFIG_HW_CRC CONFIG_HW_SPECIFIC_UDELAY diff --git a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig index b0a2db9686..385c98f275 100644 --- a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig +++ b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig @@ -81,9 +81,6 @@ CONFIG_PWM_ITE_IT8XXX2=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# Serial Host Interface (SHI) device. -CONFIG_CROS_SHI_IT8XXX2=y - # Timer configuration CONFIG_ITE_IT8XXX2_TIMER=y |