5 files changed, 0 insertions, 461 deletions
diff --git a/baseboard/brask/baseboard.c b/baseboard/brask/baseboard.c
deleted file mode 100644
index 2e60b565f8..0000000000
--- a/baseboard/brask/baseboard.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "gpio_signal.h"
-
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
diff --git a/baseboard/brask/baseboard.h b/baseboard/brask/baseboard.h
deleted file mode 100644
index 4b9d8f386a..0000000000
--- a/baseboard/brask/baseboard.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brask baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/*
- * By default, enable all console messages excepted HC
- */
-#define CC_DEFAULT     (CC_ALL & ~(BIT(CC_HOSTCMD)))
-
-/* NPCX9 config */
-#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-/*
- * This defines which pads (GPIO10/11 or GPIO64/65) are connected to
- * the "UART1" (NPCX_UART_PORT0) controller when used for
- * CONSOLE_UART.
- */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 for UART1 */
-
-/* CrOS Board Info */
-#define CONFIG_CBI_EEPROM
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_CRC8
-
-/* EC Defines */
-#define CONFIG_LTO
-#define CONFIG_FPU
-
-/* Verified boot configs */
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Work around double CR50 reset by waiting in initial power on. */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-/* Host communication */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-
-/* LED */
-#define CONFIG_LED_COMMON
-
-/* Common charger defines */
-#define CONFIG_CHARGE_MANAGER
-
-/* USBC BC1.2 */
-#define CONFIG_USB_CHARGER
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Support Barrel Jack */
-#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-/*
- * TODO(b/197475210): Don't allow the system to boot to S0 when
- * the power is lower than CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
- * since there is no battery.
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		30000
-
-/* Chipset config */
-#define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/*
- * TODO(b/191742284): When DAM enabled coreboot image is flashed on top of DAM
- * disabled coreboot, S5 exit is taking more than 4 seconds, then EC triggers
- * system shutdown. This WA deselects CONFIG_BOARD_HAS_RTC_RESET to prevent
- * EC from system shutdown.
- */
-/* #define CONFIG_BOARD_HAS_RTC_RESET */
-
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Buttons */
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_BUTTON_X86
-
-/* Matrix Keyboard Protocol */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-
-/* Thermal features */
-#define CONFIG_DPTF
-#define CONFIG_THROTTLE_AP
-
-#define CONFIG_PWM
-
-/* Enable I2C Support */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-/* UART COMMAND */
-#define CONFIG_CMD_CHARGEN
-
-/* USB Type C and USB PD defines */
-/* Enable the new USB-C PD stack */
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_REV30
-
-#define CONFIG_CMD_HCDEBUG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_ALT_MODE_UFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_NCT38XX
-
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_HOSTCMD_PD_CONTROL		/* Needed for TCPC FW update */
-#define CONFIG_CMD_USB_PD_PE
-
-/*
- * The PS8815 TCPC was found to require a 50ms delay to consistently work
- * with non-PD chargers.  Override the default low-power mode exit delay.
- */
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(50*MSEC)
-
-/* Enable USB3.2 DRD */
-#define CONFIG_USB_PD_USB32_DRD
-
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-
-#define CONFIG_USBC_PPC
-/* Note - SN5S330 support automatically adds
- * CONFIG_USBC_PPC_POLARITY
- * CONFIG_USBC_PPC_SBU
- * CONFIG_USBC_PPC_VCONN
- */
-#define CONFIG_USBC_PPC_DEDICATED_INT
-
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_MUX_VIRTUAL
-
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Enabling SOP* communication */
-#define CONFIG_CMD_USB_PD_CABLE
-#define CONFIG_USB_PD_DECODE_SOP
-
-/*
- * USB ID
- * This is allocated specifically for Brask
- * http://google3/hardware/standards/usb/
- */
-#define CONFIG_USB_PID 0x5058
-/* Device version of product. */
-#define CONFIG_USB_BCD_DEV 0x0000
-
-/* Remove predefined features */
-#undef CONFIG_HIBERNATE
-#undef CONFIG_KEYBOARD_BOOT_KEYS
-#undef CONFIG_KEYBOARD_RUNTIME_KEYS
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_KEYBOARD_VIVALDI
-
-#ifndef __ASSEMBLER__
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#include "common.h"
-#include "baseboard_usbc_config.h"
-#include "extpower.h"
-
-/*
- * Configure run-time data structures and operation based on CBI data. This
- * typically includes customization for changes in the BOARD_VERSION and
- * FW_CONFIG fields in CBI. This routine is called from the baseboard after
- * the CBI data has been initialized.
- */
-__override_proto void board_cbi_init(void);
-
-/*
- * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the
- * FW_CONFIG to the board specific defaults.
- */
-__override_proto void board_init_fw_config(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/brask/baseboard_usbc_config.h b/baseboard/brask/baseboard_usbc_config.h
deleted file mode 100644
index 1b3d9e5d3f..0000000000
--- a/baseboard/brask/baseboard_usbc_config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* brask family-specific USB-C configuration */
-
-#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
-#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
-
-#include "gpio_signal.h"
-
-/* Common definition for the USB PD interrupt handlers. */
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void retimer_interrupt(enum gpio_signal signal);
-void tcpc_alert_event(enum gpio_signal signal);
-
-#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/baseboard/brask/build.mk b/baseboard/brask/build.mk
deleted file mode 100644
index 5ba6b135f9..0000000000
--- a/baseboard/brask/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Brask baseboard specific files build
-#
-
-baseboard-y=
-baseboard-y+=baseboard.o
-baseboard-y+=usb_pd_policy.o
diff --git a/baseboard/brask/usb_pd_policy.c b/baseboard/brask/usb_pd_policy.c
deleted file mode 100644
index 33de5ca5eb..0000000000
--- a/baseboard/brask/usb_pd_policy.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Brask boards */
-
-#include <stddef.h>
-#include <stdint.h>
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "usbc_ppc.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd_vdo.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap after the PP5000_Z1 rail is enabled */
-	return gpio_get_level(GPIO_SEQ_EC_DSW_PWROK);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-/* Responses specifically for the enablement of TBT mode in the role of UFP */
-
-#define OPOS_TBT 1
-
-static const union tbt_mode_resp_device vdo_tbt_modes[1] = {
-		{
-			.tbt_alt_mode = 0x0001,
-			.tbt_adapter = TBT_ADAPTER_TBT3,
-			.intel_spec_b0 = 0,
-			.vendor_spec_b0 = 0,
-			.vendor_spec_b1 = 0,
-		}
-};
-
-static const uint32_t vdo_idh = VDO_IDH(
-				1, /* Data caps as USB host     */
-				0, /* Not a USB device   */
-				IDH_PTYPE_PERIPH,
-				1, /* Supports alt modes */
-				USB_VID_GOOGLE);
-
-static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
-				 1, /* Data caps as USB host     */
-				 0, /* Not a USB device   */
-				 IDH_PTYPE_PERIPH,
-				 1, /* Supports alt modes */
-				 IDH_PTYPE_DFP_HOST,
-				 USB_TYPEC_RECEPTACLE,
-				 USB_VID_GOOGLE);
-
-static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID,
-						CONFIG_USB_BCD_DEV);
-
-/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
-static const uint32_t vdo_ufp1 = VDO_UFP1(
-				   (VDO_UFP1_CAPABILITY_USB20
-				   | VDO_UFP1_CAPABILITY_USB32),
-				   USB_TYPEC_RECEPTACLE,
-				   VDO_UFP1_ALT_MODE_TBT3,
-				   USB_R30_SS_U40_GEN3);
-
-static const uint32_t vdo_dfp = VDO_DFP(
-				 (VDO_DFP_HOST_CAPABILITY_USB20
-				 | VDO_DFP_HOST_CAPABILITY_USB32
-				 | VDO_DFP_HOST_CAPABILITY_USB4),
-				 USB_TYPEC_RECEPTACLE,
-				 1  /* Port 1 */);
-
-static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
-{
-	/* TODO(b/154962766): Get an XID */
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-
-	if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
-		/* PD Revision 3.0 */
-		payload[VDO_I(IDH)] = vdo_idh_rev30;
-		payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1;
-		/* TODO(b/181620145): Customize for brya */
-		payload[VDO_I(PTYPE_UFP2_VDO)] = 0;
-		payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp;
-		return VDO_I(PTYPE_DFP_VDO) + 1;
-	}
-
-	/* PD Revision 2.0 */
-	payload[VDO_I(IDH)] = vdo_idh;
-	return VDO_I(PRODUCT) + 1;
-}
-
-static int svdm_tbt_compat_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_VID_INTEL, 0);
-	return 2;
-}
-
-static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) {
-		memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes));
-		return ARRAY_SIZE(vdo_tbt_modes) + 1;
-	} else {
-		return 0; /* NAK */
-	}
-}
-
-static int svdm_tbt_compat_response_enter_mode(
-	int port, uint32_t *payload)
-{
-	mux_state_t mux_state = 0;
-
-	/* Do not enter mode while CPU is off. */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		return 0; /* NAK */
-
-	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
-		(PD_VDO_OPOS(payload[0]) != OPOS_TBT))
-		return 0; /* NAK */
-
-	mux_state = usb_mux_get(port);
-	/*
-	 * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence
-	 * UFP (responder) should be in USB mode or safe mode before sending
-	 * Enter Mode Command response.
-	 */
-	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
-		(mux_state & USB_PD_MUX_SAFE_MODE)) {
-		pd_ufp_set_enter_mode(port, payload);
-		set_tbt_compat_mode_ready(port);
-		CPRINTS("UFP Enter TBT mode");
-		return 1; /* ACK */
-	}
-
-	CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state);
-	return 0;
-}
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_tbt_compat_response_identity,
-	.svids = &svdm_tbt_compat_response_svids,
-	.modes = &svdm_tbt_compat_response_modes,
-	.enter_mode = &svdm_tbt_compat_response_enter_mode,
-	.amode = NULL,
-	.exit_mode = NULL,
-};