diff options
Diffstat (limited to 'baseboard/dedede')
| -rw-r--r-- | baseboard/dedede/baseboard.c | 311 | ||||
| -rw-r--r-- | baseboard/dedede/baseboard.h | 269 | ||||
| -rw-r--r-- | baseboard/dedede/build.mk | 13 | ||||
| -rw-r--r-- | baseboard/dedede/cbi_fw_config.c | 64 | ||||
| -rw-r--r-- | baseboard/dedede/cbi_fw_config.h | 81 | ||||
| -rw-r--r-- | baseboard/dedede/variant_ec_it8320.c | 107 | ||||
| -rw-r--r-- | baseboard/dedede/variant_ec_npcx796fc.c | 191 |
7 files changed, 0 insertions, 1036 deletions
diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c deleted file mode 100644 index 2f71f03068..0000000000 --- a/baseboard/dedede/baseboard.c +++ /dev/null @@ -1,311 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Dedede family-specific configuration */ - -#include "adc.h" -#include "board_config.h" -#include "cbi_fw_config.h" -#include "charger/isl923x_public.h" -#include "charger/sm5803.h" -#include "chipset.h" -#include "common.h" -#include "extpower.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "power/icelake.h" -#include "power/intel_x86.h" -#include "system.h" -#include "usb_pd.h" - -/******************************************************************************/ -/* - * PWROK signal configuration, see the PWROK Generation Flow Diagram in the - * Jasper Lake Platform Design Guide for the list of potential signals. - * - * Dedede boards use this PWROK sequence: - * GPIO_ALL_SYS_PWRGD - turns on VCCIN rail - * GPIO_EC_AP_VCCST_PWRGD_OD - asserts VCCST_PWRGD to AP, requires 2ms - * delay from VCCST stable to meet the tCPU00 platform sequencing - * timing - * GPIO_EC_AP_PCH_PWROK_OD - asserts PMC_PCH_PWROK to the AP. Note that - * PMC_PCH_PWROK is also gated by the IMVP9_VRRDY_OD output from - * the VCCIN voltage rail controller. - * GPIO_EC_AP_SYS_PWROK - asserts PMC_SYS_PWROK to the AP - * - * Both PMC_PCH_PWROK and PMC_SYS_PWROK signals must both be asserted before - * the Jasper Lake SoC deasserts PMC_RLTRST_N. The platform may deassert - * PMC_PCH_PWROK and PMC_SYS_PWROK in any order to optimize overall boot - * latency. - */ -const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = { - { - .gpio = GPIO_ALL_SYS_PWRGD, - }, - { - .gpio = GPIO_EC_AP_VCCST_PWRGD_OD, - .delay_ms = 2, - }, - { - .gpio = GPIO_EC_AP_PCH_PWROK_OD, - }, - { - .gpio = GPIO_EC_AP_SYS_PWROK, - }, -}; -const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); - -const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { - /* No delays needed during S0 exit */ - { - .gpio = GPIO_EC_AP_VCCST_PWRGD_OD, - }, - { - .gpio = GPIO_EC_AP_PCH_PWROK_OD, - }, - { - .gpio = GPIO_EC_AP_SYS_PWROK, - }, - /* Turn off the VCCIN rail last */ - { - .gpio = GPIO_ALL_SYS_PWRGD, - }, -}; -const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list); - - -/* - * Dedede does not use hibernate wake pins, but the super low power "Z-state" - * instead in which the EC is powered off entirely. Power will be restored to - * the EC once one of the wake up events occurs. These events are ACOK, lid - * open, and a power button press. - */ -const enum gpio_signal hibernate_wake_pins[] = {}; -const int hibernate_wake_pins_used; - -__override void board_after_rsmrst(int rsmrst) -{ - /* - * b:148688874: If RSMRST# is de-asserted, enable the pull-up on - * PG_PP1050_ST_OD. It won't be enabled prior to this signal going high - * because the load switch for PP1050_ST cannot pull the PG low. Once - * it's asserted, disable the pull up so we don't inidicate that the - * power is good before the rail is actually ready. - */ - int flags = rsmrst ? GPIO_PULL_UP : 0; - - flags |= GPIO_INT_BOTH; - - gpio_set_flags(GPIO_PG_PP1050_ST_OD, flags); -} - -/* - * Dedede does not have a GPIO indicating ACOK, therefore the charger or TCPC - * can call this function once it detects a VBUS presence change with which we - * can trigger the HOOK_AC_CHANGE hook. - */ -__override void board_check_extpower(void) -{ - static int last_extpower_present; - int extpower_present = extpower_is_present(); - - if (last_extpower_present ^ extpower_present) - extpower_handle_update(extpower_present); - - last_extpower_present = extpower_present; -} - -uint32_t pp3300_a_pgood; -__override int intel_x86_get_pg_ec_dsw_pwrok(void) -{ - /* - * The PP3300_A rail is an input to generate DPWROK. Assuming that - * power is good if voltage is at least 80% of nominal level. We cannot - * read the ADC values during an interrupt, therefore, this power good - * value is updated via ADC threshold interrupts. - */ - return pp3300_a_pgood; -} - -/* Store away PP300_A good status before sysjumps */ -#define BASEBOARD_SYSJUMP_TAG 0x4242 /* BB */ -#define BASEBOARD_HOOK_VERSION 1 - -static void pp3300_a_pgood_preserve(void) -{ - system_add_jump_tag(BASEBOARD_SYSJUMP_TAG, BASEBOARD_HOOK_VERSION, - sizeof(pp3300_a_pgood), &pp3300_a_pgood); -} -DECLARE_HOOK(HOOK_SYSJUMP, pp3300_a_pgood_preserve, HOOK_PRIO_DEFAULT); - -static void baseboard_prepare_power_signals(void) -{ - const int *stored; - int version, size; - - stored = (const int *)system_get_jump_tag(BASEBOARD_SYSJUMP_TAG, - &version, &size); - if (stored && (version == BASEBOARD_HOOK_VERSION) && - (size == sizeof(pp3300_a_pgood))) - /* Valid PP3300 status found, restore before CHIPSET init */ - pp3300_a_pgood = *stored; - - /* Restore pull-up on PG_PP1050_ST_OD */ - if (system_jumped_to_this_image() && - gpio_get_level(GPIO_RSMRST_L_PGOOD)) - board_after_rsmrst(1); -} -DECLARE_HOOK(HOOK_INIT, baseboard_prepare_power_signals, HOOK_PRIO_FIRST); - -__override int intel_x86_get_pg_ec_all_sys_pwrgd(void) -{ - /* - * SLP_S3_L is a qualifying input signal to ALL_SYS_PWRGD logic. - * So ensure ALL_SYS_PWRGD remains LOW during SLP_S3_L assertion. - */ - if (!gpio_get_level(GPIO_SLP_S3_L)) - return 0; - /* - * ALL_SYS_PWRGD is an AND of DRAM PGOOD, VCCST PGOOD, and VCCIO_EXT - * PGOOD. - */ - return gpio_get_level(GPIO_PG_PP1050_ST_OD) && - gpio_get_level(GPIO_PG_DRAM_OD) && - gpio_get_level(GPIO_PG_VCCIO_EXT_OD); -} - -__override int power_signal_get_level(enum gpio_signal signal) -{ - if (signal == GPIO_PG_EC_DSW_PWROK) - return intel_x86_get_pg_ec_dsw_pwrok(); - - if (signal == GPIO_PG_EC_ALL_SYS_PWRGD) - return intel_x86_get_pg_ec_all_sys_pwrgd(); - - if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) { - /* Check signal is from GPIOs or VWs */ - if (espi_signal_is_vw(signal)) - return espi_vw_get_wire(signal); - } - return gpio_get_level(signal); - -} - -void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal) -{ - /* - * We need to deassert ALL_SYS_PGOOD within 200us of SLP_S3_L asserting. - * that is why we do this here instead of waiting for the chipset - * driver to. - * Early protos do not pull VCCST_PWRGD below Vil in hardware logic, - * so we need to do the same for this signal. - * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW during - * SLP_S3_L assertion. - */ - if (!gpio_get_level(GPIO_SLP_S3_L)) { - gpio_set_level(GPIO_ALL_SYS_PWRGD, 0); - gpio_set_level(GPIO_EN_VCCIO_EXT, 0); - gpio_set_level(GPIO_EC_AP_VCCST_PWRGD_OD, 0); - gpio_set_level(GPIO_EC_AP_PCH_PWROK_OD, 0); - } - /* Now chain off to the normal power signal interrupt handler. */ - power_signal_interrupt(signal); -} - -void baseboard_chipset_startup(void) -{ -#ifdef CONFIG_PWM_KBLIGHT - /* Allow keyboard backlight to be enabled */ - gpio_set_level(GPIO_EN_KB_BL, 1); -#endif -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup, - HOOK_PRIO_DEFAULT); - -void baseboard_chipset_shutdown(void) -{ -#ifdef CONFIG_PWM_KBLIGHT - /* Turn off the keyboard backlight if it's on. */ - gpio_set_level(GPIO_EN_KB_BL, 0); -#endif -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown, - HOOK_PRIO_DEFAULT); - -void board_hibernate_late(void) -{ - volatile uint32_t busy = 0; - - /* Disable any pull-ups on C0 and C1 interrupt lines */ - gpio_set_flags(GPIO_USB_C0_INT_ODL, GPIO_INPUT); - #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT); - #endif - /* - * Turn on the Z state. This will not return as it will cut power to - * the EC. - */ - gpio_set_level(GPIO_EN_SLP_Z, 1); - - /* - * Interrupts are disabled at this point, so busy-loop to consume some - * time (something on the order of at least 1 second, depending on EC - * chip being used) - */ - while (busy < 100000) - busy++; - - /* - * Still awake despite turning on zombie state? Reset with AP off is - * the best we can do in this situation. - */ - system_reset(SYSTEM_RESET_LEAVE_AP_OFF); - - /* Await our reset */ - while (1) - ; -} - -int board_is_i2c_port_powered(int port) -{ - if (port != I2C_PORT_SENSOR) - return 1; - - /* Sensor rails are off in S5/G3 */ - return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1; -} - -int extpower_is_present(void) -{ - int port; - int rv; - bool acok; - enum ec_error_list (*check_acok)(int port, bool *acok); - - if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) - check_acok = raa489000_is_acok; - else if (IS_ENABLED(CONFIG_CHARGER_SM5803)) - check_acok = sm5803_is_acok; - - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - rv = check_acok(port, &acok); - if ((rv == EC_SUCCESS) && acok) - return 1; - } - - return 0; -} - -__override uint32_t board_override_feature_flags0(uint32_t flags0) -{ - /* - * Remove keyboard backlight feature for devices that don't support it. - */ - if (get_cbi_fw_config_kblight() == KB_BL_ABSENT) - return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)); - else - return flags0; -} diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h deleted file mode 100644 index a8a0ed3ff2..0000000000 --- a/baseboard/dedede/baseboard.h +++ /dev/null @@ -1,269 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Dedede board configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* - * By default, enable all console messages excepted HC, ACPI and event: - * The sensor stack is generating a lot of activity. - */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) - -/* - * Variant EC defines. Pick one: - * VARIANT_DEDEDE_EC_NPCX796FC - */ -#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || \ - defined(VARIANT_KEEBY_EC_NPCX797FC) - /* NPCX7 config */ - #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ - #define NPCX_TACH_SEL2 0 /* No tach. */ - - /* Internal SPI flash on NPCX7 */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) - #define CONFIG_SPI_FLASH_REGS - #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ -#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ - defined(VARIANT_KEEBY_EC_IT8320) - /* IT83XX config */ - #define CONFIG_IT83XX_VCC_1P8V - /* I2C Bus Configuration */ - #define I2C_PORT_EEPROM IT83XX_I2C_CH_A - #define I2C_PORT_BATTERY IT83XX_I2C_CH_B - #define I2C_PORT_SENSOR IT83XX_I2C_CH_C - #define I2C_PORT_SUB_USB_C1 IT83XX_I2C_CH_E - #define I2C_PORT_USB_C0 IT83XX_I2C_CH_F - - #define I2C_ADDR_EEPROM_FLAGS 0x50 - - #define CONFIG_ADC_VOLTAGE_COMPARATOR /* ITE ADC thresholds */ - - #undef CONFIG_UART_TX_BUF_SIZE /* UART */ - #define CONFIG_UART_TX_BUF_SIZE 4096 -#else -#error "Must define a VARIANT_[DEDEDE|KEEBY]_EC!" -#endif - -/* - * The key difference between Keeby and Dedede is that Keeby variants don't have - * a connection to H1 and therefore do not use EFS2. - */ -#if defined(VARIANT_KEEBY_EC_NPCX797FC) || defined(VARIANT_KEEBY_EC_IT8320) -#define KEEBY_VARIANT 1 -#else -#define KEEBY_VARIANT 0 -#endif - -/* - * Remapping of schematic GPIO names to common GPIO names expected (hardcoded) - * in the EC code base. - */ -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_MKBP_INT_L -#define GPIO_EN_PP5000 GPIO_EN_PP5000_U -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#if !KEEBY_VARIANT -#define GPIO_PACKET_MODE_EN GPIO_ECH1_PACKET_MODE -#endif -#define GPIO_PCH_DSW_PWROK GPIO_EC_AP_DPWROK -#define GPIO_PCH_PWRBTN_L GPIO_EC_AP_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_AP_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_AP_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L -#if KEEBY_VARIANT -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#else -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#endif -#define GPIO_RSMRST_L_PGOOD GPIO_RSMRST_PWRGD_L -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_USB_C0_DP_HPD GPIO_EC_AP_USB_C0_HPD -#define GPIO_USB_C1_DP_HPD GPIO_EC_AP_USB_C1_HDMI_HPD -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_WP GPIO_EC_WP_OD -#define GMR_TABLET_MODE_GPIO_L GPIO_LID_360_L - -/* Common EC defines */ - -/* Work around double CR50 reset by waiting in initial power on. */ -#if !KEEBY_VARIANT -#define CONFIG_BOARD_RESET_AFTER_POWER_ON -#endif - -/* Optional console commands */ -#define CONFIG_CMD_CHARGER_DUMP - -/* Enable AP Reset command for TPM with old firmware version to detect it. */ -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_HOSTCMD_AP_RESET - -/* Enable i2ctrace command */ -#define CONFIG_I2C_DEBUG - -/* Assert CCD when a debug device is connected */ -#if !KEEBY_VARIANT -#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT -#endif - -/* EC Modules */ -#define CONFIG_ADC -#define CONFIG_CRC8 -#define CONFIG_HOSTCMD_ESPI -#define CONFIG_HOSTCMD_EVENTS -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_POWER_PP5000_CONTROL -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 -#if !KEEBY_VARIANT -#define CONFIG_VBOOT_EFS2 -#endif - -/* Battery */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATTERY_PRES_ODL -#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_BATTERY_SMART - -/* Buttons / Switches */ -#define CONFIG_SWITCH -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_WP_ACTIVE_HIGH - -/* CBI */ -#define CONFIG_CBI_EEPROM -#define CONFIG_BOARD_VERSION_CBI -#if KEEBY_VARIANT -#define CONFIG_EEPROM_CBI_WP -#endif - -/* Charger */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 256 -#define CONFIG_USB_CHARGER -#define CONFIG_TRICKLE_CHARGING - -/* Keyboard */ -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#define CONFIG_MKBP_INPUT_DEVICES - -/* Backlight */ -#define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EN_BL_OD - -/* LED */ -#define CONFIG_LED_COMMON - -/* Sensors */ -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT - -/* SoC */ -#define CONFIG_BOARD_HAS_RTC_RESET -#define CONFIG_CHIPSET_JASPERLAKE -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_CPU_PROCHOT_ACTIVE_LOW - -/* USB Type-C */ -#define CONFIG_USB_MUX_PI3USB31532 -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_SS_MUX_DFP_ONLY -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP - -/* Temp Sensor */ -#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A -#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500 - -/* USB PD */ -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DP_HPD_GPIO -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_REV30 -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TRY_SRC -/* #define CONFIG_USB_PD_VBUS_DETECT_CHARGER */ -#define CONFIG_USB_PD_VBUS_MEASURE_CHARGER -#define CONFIG_USB_PD_DECODE_SOP -#if KEEBY_VARIANT -#define CONFIG_USB_PID 0x5059 -#else -#define CONFIG_USB_PID 0x5042 -#endif -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_HOSTCMD_PD_CONTROL - -#if !KEEBY_VARIANT -/* UART COMMAND */ -#define CONFIG_CMD_CHARGEN -#endif - -/* Define typical operating power and max power. */ -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_POWER_MW 45000 -#define PD_OPERATING_POWER_MW 15000 - -/* TODO(b:147314141): Verify these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -#ifndef __ASSEMBLER__ - -#include "common.h" -#include "gpio_signal.h" - -/* Common enums */ -#if defined(VARIANT_DEDEDE_EC_NPCX796FC) -#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ - defined(VARIANT_KEEBY_EC_IT8320) - enum board_vcmp { - VCMP_SNS_PP3300_LOW, - VCMP_SNS_PP3300_HIGH, - VCMP_COUNT - }; -#endif - -/* Interrupt handler for signals that are used to generate ALL_SYS_PGOOD. */ -void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal); - -/* Reset all TCPCs */ -void board_reset_pd_mcu(void); - -/* - * Bit to indicate if the PP3000_A rail's power is good. Will be updated by ADC - * interrupt. - */ -extern uint32_t pp3300_a_pgood; - -#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/dedede/build.mk b/baseboard/dedede/build.mk deleted file mode 100644 index 6d7452081e..0000000000 --- a/baseboard/dedede/build.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o cbi_fw_config.o -baseboard-$(VARIANT_DEDEDE_EC_NPCX796FC)+=variant_ec_npcx796fc.o -baseboard-$(VARIANT_KEEBY_EC_NPCX797FC)+=variant_ec_npcx796fc.o -baseboard-$(VARIANT_DEDEDE_EC_IT8320)+=variant_ec_it8320.o -baseboard-$(VARIANT_KEEBY_EC_IT8320)+=variant_ec_it8320.o diff --git a/baseboard/dedede/cbi_fw_config.c b/baseboard/dedede/cbi_fw_config.c deleted file mode 100644 index 27d23733de..0000000000 --- a/baseboard/dedede/cbi_fw_config.c +++ /dev/null @@ -1,64 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "cbi_fw_config.h" -#include "common.h" -#include "console.h" -#include "cros_board_info.h" -#include "hooks.h" - -/**************************************************************************** - * Dedede CBI FW Configuration - */ - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) - -/* Cache FW_CONFIG on init since we don't expect it to change in runtime */ -static uint32_t cached_fw_config; - -static void cbi_fw_config_init(void) -{ - if (cbi_get_fw_config(&cached_fw_config) != EC_SUCCESS) - /* Default to 0 when CBI isn't populated */ - cached_fw_config = 0; - - CPRINTS("FW_CONFIG: 0x%04X", cached_fw_config); -} -DECLARE_HOOK(HOOK_INIT, cbi_fw_config_init, HOOK_PRIO_FIRST); - -enum fw_config_db get_cbi_fw_config_db(void) -{ - return ((cached_fw_config & FW_CONFIG_DB_MASK) >> FW_CONFIG_DB_OFFSET); -} - -enum fw_config_kblight_type get_cbi_fw_config_kblight(void) -{ - return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) - >> FW_CONFIG_KB_BL_OFFSET); -} - -enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void) -{ - return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK) - >> FW_CONFIG_TABLET_MODE_OFFSET); -} - -int get_cbi_fw_config_keyboard(void) -{ - return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) - >> FW_CONFIG_KB_LAYOUT_OFFSET); -} - -enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void) -{ - return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK) - >> FW_CONFIG_KB_NUMPAD_OFFSET); -} - -enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void) -{ - return ((cached_fw_config & FW_CONFIG_HDMI_MASK) - >> FW_CONFIG_HDMI_OFFSET); -} diff --git a/baseboard/dedede/cbi_fw_config.h b/baseboard/dedede/cbi_fw_config.h deleted file mode 100644 index c9782522fa..0000000000 --- a/baseboard/dedede/cbi_fw_config.h +++ /dev/null @@ -1,81 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef _DEDEDE_CBI_FW_CONFIG__H_ -#define _DEDEDE_CBI_FW_CONFIG__H_ - -/**************************************************************************** - * Dedede CBI FW Configuration - */ - -/* - * Daughter Board (Bits 0-3) - */ -enum fw_config_db { - DB_NONE, - DB_2C, - DB_1C_LTE, - DB_1A_HDMI, - DB_1C_1A, - DB_LTE_HDMI, - DB_1C_1A_LTE, - DB_1C, - DB_1A_HDMI_LTE, -}; -#define FW_CONFIG_DB_OFFSET 0 -#define FW_CONFIG_DB_MASK GENMASK(3, 0) - -/* - * Keyboard backlight (1 bit) - */ -enum fw_config_kblight_type { - KB_BL_ABSENT = 0, - KB_BL_PRESENT = 1, -}; -#define FW_CONFIG_KB_BL_OFFSET 8 -#define FW_CONFIG_KB_BL_MASK GENMASK(8, 8) - -/* - * Keyboard numeric pad (1 bit) - */ -enum fw_config_numeric_pad_type { - NUMERIC_PAD_ABSENT = 0, - NUMERIC_PAD_PRESENT = 1, -}; -#define FW_CONFIG_KB_NUMPAD_OFFSET 9 -#define FW_CONFIG_KB_NUMPAD_MASK GENMASK(9, 9) - -/* - * Tablet Mode (1 bit) - */ -enum fw_config_tablet_mode_type { - TABLET_MODE_ABSENT = 0, - TABLET_MODE_PRESENT = 1, -}; -#define FW_CONFIG_TABLET_MODE_OFFSET 10 -#define FW_CONFIG_TABLET_MODE_MASK GENMASK(10, 10) - -#define FW_CONFIG_KB_LAYOUT_OFFSET 12 -#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(13, 12) - -/* - * Hdmi (1 bit) - */ -enum fw_config_hdmi_type { - HDMI_ABSENT = 0, - HDMI_PRESENT = 1, -}; -#define FW_CONFIG_HDMI_OFFSET 17 -#define FW_CONFIG_HDMI_MASK GENMASK(17, 17) - -enum fw_config_db get_cbi_fw_config_db(void); -enum fw_config_kblight_type get_cbi_fw_config_kblight(void); -enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void); -enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void); -enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void); - -int get_cbi_fw_config_keyboard(void); - -#endif /* _DEDEDE_CBI_FW_CONFIG__H_ */ diff --git a/baseboard/dedede/variant_ec_it8320.c b/baseboard/dedede/variant_ec_it8320.c deleted file mode 100644 index 59f07da086..0000000000 --- a/baseboard/dedede/variant_ec_it8320.c +++ /dev/null @@ -1,107 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_[DEDEDE|KEEBY]_IT8320 configuration */ - -#include "adc_chip.h" -#include "atomic.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "power.h" -#include "registers.h" - -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) - -static void pp3300_a_pgood_low(void) -{ - atomic_clear_bits(&pp3300_a_pgood, 1); - - /* Disable low interrupt while asserted */ - vcmp_enable(VCMP_SNS_PP3300_LOW, 0); - - /* Enable high interrupt */ - vcmp_enable(VCMP_SNS_PP3300_HIGH, 1); - - /* - * Call power_signal_interrupt() with a fake GPIO in order for the - * chipset task to pick up the change in power sequencing signals. - */ - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} - -static void pp3300_a_pgood_high(void) -{ - atomic_or(&pp3300_a_pgood, 1); - - /* Disable high interrupt while asserted */ - vcmp_enable(VCMP_SNS_PP3300_HIGH, 0); - - /* Enable low interrupt */ - vcmp_enable(VCMP_SNS_PP3300_LOW, 1); - - /* - * Call power_signal_interrupt() with a fake GPIO in order for the - * chipset task to pick up the change in power sequencing signals. - */ - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} - -const struct vcmp_t vcmp_list[] = { - [VCMP_SNS_PP3300_LOW] = { - .name = "VCMP_SNS_PP3300_LOW", - .threshold = 600, /* mV */ - .flag = LESS_EQUAL_THRESHOLD, - .vcmp_thresh_cb = &pp3300_a_pgood_low, - .scan_period = VCMP_SCAN_PERIOD_600US, - .adc_ch = CHIP_ADC_CH0, - }, - [VCMP_SNS_PP3300_HIGH] = { - .name = "VCMP_SNS_PP3300_HIGH", - .threshold = 2700, /* mV */ - .flag = GREATER_THRESHOLD, - .vcmp_thresh_cb = &pp3300_a_pgood_high, - .scan_period = VCMP_SCAN_PERIOD_600US, - .adc_ch = CHIP_ADC_CH0, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(vcmp_list) <= CHIP_VCMP_COUNT); -BUILD_ASSERT(ARRAY_SIZE(vcmp_list) == VCMP_COUNT); - -/* I2C Ports */ -const struct i2c_port_t i2c_ports[] = { - { - "eeprom", I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL, - GPIO_EC_I2C_EEPROM_SDA - }, - - { - "battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL, - GPIO_EC_I2C_BATTERY_SDA - }, -#ifdef HAS_TASK_MOTIONSENSE - { - "sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL, - GPIO_EC_I2C_SENSOR_SDA - }, -#endif - -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - "sub_usbc1", I2C_PORT_SUB_USB_C1, 1000, - GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA - }, -#endif - - { - "usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL, - GPIO_EC_I2C_USB_C0_SDA - }, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - diff --git a/baseboard/dedede/variant_ec_npcx796fc.c b/baseboard/dedede/variant_ec_npcx796fc.c deleted file mode 100644 index 6d9dfb368a..0000000000 --- a/baseboard/dedede/variant_ec_npcx796fc.c +++ /dev/null @@ -1,191 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_[DEDEDE|KEEBY]_NPCX79[6/7]FC configuration */ - -#include "adc.h" -#include "atomic.h" -#include "chipset.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "lid_switch.h" -#include "power.h" -#include "registers.h" -#include "task.h" -#include "timer.h" - -/* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - -void pp3300_a_pgood_high(void) -{ - atomic_or(&pp3300_a_pgood, 1); - - /* Disable this interrupt while it's asserted. */ - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 0); - /* Enable the voltage low interrupt. */ - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); - - /* - * Call power_signal_interrupt() with a fake GPIO in order for the - * chipset task to pick up the change in power sequencing signals. - */ - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} - -void pp3300_a_pgood_low(void) -{ - atomic_clear_bits(&pp3300_a_pgood, 1); - - /* Disable this interrupt while it's asserted. */ - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 0); - /* Enable the voltage high interrupt. */ - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); - - /* - * Call power_signal_interrupt() with a fake GPIO in order for the - * chipset task to pick up the change in power sequencing signals. - */ - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} - -const struct npcx_adc_thresh_t adc_pp3300_a_pgood_high = { - .adc_ch = ADC_VSNS_PP3300_A, - .adc_thresh_cb = pp3300_a_pgood_high, - .thresh_assert = 2700, -}; - -const struct npcx_adc_thresh_t adc_pp3300_a_pgood_low = { - .adc_ch = ADC_VSNS_PP3300_A, - .adc_thresh_cb = pp3300_a_pgood_low, - .lower_or_higher = 1, - .thresh_assert = 600, -}; - -static void set_up_adc_irqs(void) -{ - /* Set interrupt thresholds for the ADC. */ - npcx_adc_register_thresh_irq(NPCX_ADC_THRESH1, - &adc_pp3300_a_pgood_high); - npcx_adc_register_thresh_irq(NPCX_ADC_THRESH2, &adc_pp3300_a_pgood_low); - npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, 1); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); -} -DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC+1); - -static void disable_adc_irqs_deferred(void) -{ - CPRINTS("%s", __func__); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 0); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 0); - npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, 0); - - /* - * If we're already in G3, PP3300_A is already off. Since the ADC - * interrupts were already disabled, this data is stale. Therefore, - * force the PGOOD value to 0 and have the chipset task re-evaluate. - * This should help prevent leakage. - */ - if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) - pp3300_a_pgood = 0; - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} -DECLARE_DEFERRED(disable_adc_irqs_deferred); - -/* - * The ADC interrupts are only needed for booting up. The assumption is that - * the PP3300_A rail will not go down during runtime. Therefore, we'll disable - * the ADC interrupts shortly after booting up and also after shutting down. - */ -static void disable_adc_irqs(void) -{ - int delay = 200 * MSEC; - - /* - * The EC stays in S5 for about 10s after shutting before heading down - * to G3. Therefore, we'll postpone disabling the ADC IRQs until after - * this occurs. - */ - if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) - delay = 15 * SECOND; - hook_call_deferred(&disable_adc_irqs_deferred_data, delay); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, disable_adc_irqs, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_RESUME, disable_adc_irqs, HOOK_PRIO_DEFAULT); - -/* - * We only need the ADC interrupts functional when powering up. Therefore, only - * enable them from our wake sources. These will be the power button, or lid - * open. Below is a summary of the ADC interrupt action per power state and - * wake source. - * - * Powering up to S0: ADC interrupts will be disabled after ~200ms. - * S0ix/S3: No action as ADC interrupts are already disabled if suspending. - * Powering down to S5/G3: ADC interrupts will be disabled after ~15s. - * Powering up from S5/G3: ADC interrupts will be enabled. They will be - * disabled ~200ms after passing thru S3. - * Power button press: If the system is in S5/G3, ADC interrupts will be - * enabled. - * Lid open: ADC interrupts will be enabled. - */ -static void enable_adc_irqs(void) -{ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) { - CPRINTS("%s", __func__); - hook_call_deferred(&disable_adc_irqs_deferred_data, -1); - npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, - 1); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); - } -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, enable_adc_irqs, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, enable_adc_irqs, HOOK_PRIO_DEFAULT); - -static void enable_adc_irqs_via_lid(void) -{ - if (lid_is_open()) - enable_adc_irqs(); -} -DECLARE_HOOK(HOOK_LID_CHANGE, enable_adc_irqs_via_lid, HOOK_PRIO_DEFAULT); - -/* I2C Ports */ -__attribute__((weak)) const struct i2c_port_t i2c_ports[] = { - { - "eeprom", I2C_PORT_EEPROM, 1000, GPIO_EC_I2C_EEPROM_SCL, - GPIO_EC_I2C_EEPROM_SDA - }, - - { - "battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL, - GPIO_EC_I2C_BATTERY_SDA - }, - -#ifdef HAS_TASK_MOTIONSENSE - { - "sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL, - GPIO_EC_I2C_SENSOR_SDA - }, -#endif - - { - "usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL, - GPIO_EC_I2C_USB_C0_SDA - }, -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - "sub_usbc1", I2C_PORT_SUB_USB_C1, 1000, - GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA - }, -#endif -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - |