diff options
Diffstat (limited to 'baseboard/herobrine')
| -rw-r--r-- | baseboard/herobrine/baseboard.c | 2 | ||||
| -rw-r--r-- | baseboard/herobrine/baseboard.h | 90 | ||||
| -rw-r--r-- | baseboard/herobrine/build.mk | 2 | ||||
| -rw-r--r-- | baseboard/herobrine/usb_pd_policy.c | 41 | ||||
| -rw-r--r-- | baseboard/herobrine/usbc_config.c | 6 |
5 files changed, 68 insertions, 73 deletions
diff --git a/baseboard/herobrine/baseboard.c b/baseboard/herobrine/baseboard.c index 41d40dd7ae..fca6e9c66d 100644 --- a/baseboard/herobrine/baseboard.c +++ b/baseboard/herobrine/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/herobrine/baseboard.h b/baseboard/herobrine/baseboard.h index ae5b2a3d33..0782612cb8 100644 --- a/baseboard/herobrine/baseboard.h +++ b/baseboard/herobrine/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,12 +13,12 @@ * The sensor stack is generating a lot of activity. * They can be enabled through the console command 'chan'. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ #define CONFIG_SPI_FLASH_REGS @@ -140,13 +140,13 @@ #define CONFIG_CMD_ACCEL_INFO /* PD */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ -#define PD_OPERATING_POWER_MW 10000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 10000 +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Chipset */ #define CONFIG_CHIPSET_SC7280 @@ -163,56 +163,54 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_LID_OPEN GPIO_LID_OPEN_EC -#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L -#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 -#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 -#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_LID_OPEN GPIO_LID_OPEN_EC +#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L +#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 +#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 +#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* I2C Ports */ #define I2C_PORT_BATTERY I2C_PORT_POWER #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_WLC NPCX_I2C_PORT3_0 -#define I2C_PORT_RTC NPCX_I2C_PORT4_1 -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_WLC NPCX_I2C_PORT3_0 +#define I2C_PORT_RTC NPCX_I2C_PORT4_1 +#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 /* UART */ #define CONFIG_CMD_CHARGEN /* Define the host events which are allowed to wake AP up from S3 */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) /* And the MKBP events */ #ifdef HAS_TASK_KEYSCAN -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) +#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT) | \ + BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #else #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) + (BIT(EC_MKBP_EVENT_HOST_EVENT) | BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #endif #endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/herobrine/build.mk b/baseboard/herobrine/build.mk index f007fd7118..67c2e2143f 100644 --- a/baseboard/herobrine/build.mk +++ b/baseboard/herobrine/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/herobrine/usb_pd_policy.c b/baseboard/herobrine/usb_pd_policy.c index 7ca2688aef..9fa725c845 100644 --- a/baseboard/herobrine/usb_pd_policy.c +++ b/baseboard/herobrine/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,8 +12,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) int pd_check_vconn_swap(int port) { @@ -23,10 +23,10 @@ int pd_check_vconn_swap(int port) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; #if CONFIG_USB_PD_PORT_MAX_COUNT == 1 -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 }; #else -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; #endif static void board_vbus_update_source_current(int port) @@ -107,11 +107,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) * (3) plug a monitor to the port-1 dongle. */ - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -187,8 +187,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) * because of the board USB-C topology (limited to 2 * lanes DP). */ - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } else { /* Disconnect the DP port selection mux. */ @@ -200,13 +199,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload) ppc_set_sbu(port, 0); /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -231,16 +228,16 @@ __override int svdm_dp_attention(int port, uint32_t *payload) gpio_set_level(hpd, 1); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } else if (irq & !lvl) { CPRINTF("ERR:HPD:IRQ&LOW\n"); return 0; } else { gpio_set_level(hpd, lvl); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } return 1; @@ -255,7 +252,7 @@ __override void svdm_exit_dp_mode(int port) /* Signal AP for the HPD low event */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0); } } diff --git a/baseboard/herobrine/usbc_config.c b/baseboard/herobrine/usbc_config.c index f5ee9c157d..2ebb8ae029 100644 --- a/baseboard/herobrine/usbc_config.c +++ b/baseboard/herobrine/usbc_config.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,8 +11,8 @@ #include "console.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { |