diff options
Diffstat (limited to 'baseboard/octopus')
| -rw-r--r-- | baseboard/octopus/baseboard.c | 384 | ||||
| -rw-r--r-- | baseboard/octopus/baseboard.h | 322 | ||||
| -rw-r--r-- | baseboard/octopus/build.mk | 15 | ||||
| -rw-r--r-- | baseboard/octopus/cbi_ssfc.c | 49 | ||||
| -rw-r--r-- | baseboard/octopus/cbi_ssfc.h | 66 | ||||
| -rw-r--r-- | baseboard/octopus/usb_pd_policy.c | 78 | ||||
| -rw-r--r-- | baseboard/octopus/variant_ec_ite8320.c | 37 | ||||
| -rw-r--r-- | baseboard/octopus/variant_ec_npcx796fb.c | 53 | ||||
| -rw-r--r-- | baseboard/octopus/variant_usbc_ec_tcpcs.c | 159 | ||||
| -rw-r--r-- | baseboard/octopus/variant_usbc_standalone_tcpcs.c | 216 |
10 files changed, 0 insertions, 1379 deletions
diff --git a/baseboard/octopus/baseboard.c b/baseboard/octopus/baseboard.c deleted file mode 100644 index 4f338ab131..0000000000 --- a/baseboard/octopus/baseboard.c +++ /dev/null @@ -1,384 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Octopus family-specific configuration */ - -#include "charge_manager.h" -#include "charge_state.h" -#include "chipset.h" -#include "common.h" -#include "console.h" -#include "driver/bc12/max14637.h" -#include "driver/charger/isl923x.h" -#include "driver/ppc/nx20p348x.h" -#include "gpio.h" -#include "hooks.h" -#ifdef VARIANT_OCTOPUS_EC_ITE8320 -#include "intc.h" -#endif -#include "keyboard_scan.h" -#include "power.h" -#include "system.h" -#include "task.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -/******************************************************************************/ -/* Keyboard scan setting */ -__override struct keyboard_scan_config keyscan_config = { - /* - * F3 key scan cycle completed but scan input is not - * charging to logic high when EC start scan next - * column for "T" key, so we set .output_settle_us - * to 80us from 50us. - */ - .output_settle_us = 80, - .debounce_down_us = 9 * MSEC, - .debounce_up_us = 30 * MSEC, - .scan_period_us = 3 * MSEC, - .min_post_scan_delay_us = 1000, - .poll_timeout_us = 100 * MSEC, - .actual_key_mask = { -#ifndef CONFIG_KEYBOARD_KEYPAD - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ -#else - 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff, /* full set */ -#endif - }, -}; - -/******************************************************************************/ -/* USB-A Configuration */ -const int usb_port_enable[USB_PORT_COUNT] = { - GPIO_EN_USB_A0_5V, - GPIO_EN_USB_A1_5V, -}; - -/******************************************************************************/ -/* BC 1.2 chip Configuration */ -const struct max14637_config_t max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON, - .chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L, - .flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW, - }, - { - .chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON, - .chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L, - .flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW, - }, -}; - -/******************************************************************************/ -/* Charger Chip Configuration */ -#ifdef VARIANT_OCTOPUS_CHARGER_ISL9238 -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - }, -}; -#endif - -/******************************************************************************/ -/* Chipset callbacks/hooks */ - -/* Called by APL power state machine when transitioning from G3 to S5 */ -void chipset_pre_init_callback(void) -{ -#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED - /* - * Since we disable eSPI module for IT8320 part when system goes into G3 - * state, so we need to enable it at system startup. - */ - espi_enable_pad(1); -#endif - - /* Enable 5.0V and 3.3V rails, and wait for Power Good */ - power_5v_enable(task_get_current(), 1); - - gpio_set_level(GPIO_EN_PP3300, 1); - while (!gpio_get_level(GPIO_PP5000_PG) || - !gpio_get_level(GPIO_PP3300_PG)) - ; - - /* Enable PMIC */ - gpio_set_level(GPIO_PMIC_EN, 1); -} - -/* Called on AP S5 -> S3 transition */ -static void baseboard_chipset_startup(void) -{ - /* Enable Trackpad in S3+, so it can be an AP wake source. */ - gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup, - HOOK_PRIO_DEFAULT); - -/* Called on AP S3 -> S0 transition */ -static void baseboard_chipset_resume(void) -{ - /* - * GPIO_ENABLE_BACKLIGHT is AND'ed with SOC_EDP_BKLTEN from the SoC and - * LID_OPEN connection in hardware. - */ - gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1); - /* Enable the keyboard backlight */ - gpio_set_level(GPIO_KB_BL_PWR_EN, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); - -/* Called on AP S0 -> S3 transition */ -static void baseboard_chipset_suspend(void) -{ - /* - * GPIO_ENABLE_BACKLIGHT is AND'ed with SOC_EDP_BKLTEN from the SoC and - * LID_OPEN connection in hardware. - */ - gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0); - /* Disable the keyboard backlight */ - gpio_set_level(GPIO_KB_BL_PWR_EN, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend, - HOOK_PRIO_DEFAULT); - -/* Called on AP S3 -> S5 transition */ -static void baseboard_chipset_shutdown(void) -{ - /* Disable Trackpad in S5- to save power; not a low power wake source */ - gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown, - HOOK_PRIO_DEFAULT); - -/* Called by APL power state machine when transitioning to G3. */ -void chipset_do_shutdown(void) -{ -#ifdef VARIANT_OCTOPUS_EC_ITE8320 - /* - * We want the processor to be reset before dropping the PP3300_A rail - * below, otherwise the PP3300_LDO and PP3300_EC rails can be overloaded - */ - if (gpio_get_level(GPIO_PCH_SLP_S4_L)) { - /* assert RSMRST to PCH */ - gpio_set_level(GPIO_PCH_RSMRST_L, 0); - /* Wait SLP_S4 goes low; would rather watchdog than continue */ - while (gpio_get_level(GPIO_PCH_SLP_S4_L)) - ; - } -#endif - - /* Disable PMIC */ - gpio_set_level(GPIO_PMIC_EN, 0); - - /* Disable 5.0V and 3.3V rails, and wait until they power down. */ - power_5v_enable(task_get_current(), 0); - - /* - * Shutdown the 3.3V rail and wait for it to go down. We cannot wait - * for the 5V rail since other tasks may be using it. - */ - gpio_set_level(GPIO_EN_PP3300, 0); - while (gpio_get_level(GPIO_PP3300_PG)) - ; - -#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED - /* - * The IT8320 part doesn't go into its lowest power state in idle task - * when the eSPI module is on and CS# is asserted, so we need to - * manually disable it. - */ - espi_enable_pad(0); -#endif -} - -int board_is_i2c_port_powered(int port) -{ - if (port != I2C_PORT_SENSOR) - return 1; - - /* Sensor rails are off in S5/G3 */ - return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1; -} - -/******************************************************************************/ -/* Power Delivery and charing functions */ - -#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT -enum adc_channel board_get_vbus_adc(int port) -{ - if (port == 0) - return ADC_VBUS_C0; - if (port == 1) - return ADC_VBUS_C1; - CPRINTSUSB("Unknown vbus adc port id: %d", port); - return ADC_VBUS_C0; -} -#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */ - -void baseboard_tcpc_init(void) -{ - /* Only reset TCPC if not sysjump */ - if (!system_jumped_late()) - board_reset_pd_mcu(); - - /* - * Initialize HPD to low; after sysjump SOC needs to see - * HPD pulse to enable video path - */ - for (int port = 0; port < board_get_usb_pd_port_count(); ++port) - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); -} -/* Called after the cbi_init (via +2) */ -DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 2); - -int board_set_active_charge_port(int port) -{ - int is_valid_port = (port >= 0 && - port < board_get_usb_pd_port_count()); - int i; - - if (!is_valid_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; (i < ppc_cnt) && - (i < board_get_usb_pd_port_count()); i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTFUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; (i < ppc_cnt) && - (i < board_get_usb_pd_port_count()); i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - /* - * Empirically, the charger seems to draw a little more current that - * it is set to, so we reduce our limit by 5%. - */ -#if defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_ISL9238) - charge_ma = (charge_ma * 95) / 100; -#endif - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); -} - -void board_hibernate(void) -{ - int port; - - /* - * To support hibernate called from console commands, ectool commands - * and key sequence, shutdown the AP before hibernating. - * - * If board_hibernate() is called from within chipset task, then - * chipset_do_shutdown needs to be called directly since - * chipset_force_shutdown basically just sets wake event for chipset - * task. But that will not help since chipset task is in board_hibernate - * and never returns back to the power state machine to take down power - * rails. - */ -#ifdef HAS_TASK_CHIPSET - if (task_get_current() == TASK_ID_CHIPSET) - chipset_do_shutdown(); - else -#endif - chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM); - -#ifdef CONFIG_USBC_PPC_NX20P3483 - /* - * If we are charging, then drop the Vbus level down to 5V to ensure - * that we don't get locked out of the 6.8V OVLO for our PPCs in - * dead-battery mode. This is needed when the TCPC/PPC rails go away. - * (b/79218851) - */ - port = charge_manager_get_active_charge_port(); - if (port != CHARGE_PORT_NONE) - pd_request_source_voltage(port, NX20P348X_SAFE_RESET_VBUS_MV); -#endif - - /* - * If Vbus isn't already on this port, then we need to put the PPC into - * low power mode or open the SNK FET based on which signals wake up - * the EC from hibernate. - */ - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - if (!pd_is_vbus_present(port)) { -#ifdef VARIANT_OCTOPUS_EC_ITE8320 - /* - * ITE variant uses the PPC interrupts instead of - * AC_PRESENT to wake up, so we do not need to enable - * the SNK FETS. - */ - ppc_enter_low_power_mode(port); -#else - /* - * Open the SNK path to allow AC to pass through to the - * charger when connected. This is need if the TCPC/PPC - * rails do not go away and AC_PRESENT wakes up the EC - * (b/79173959). - */ - ppc_vbus_sink_enable(port, 1); -#endif - } - } - - /* - * Delay allows AP power state machine to settle down along - * with any PD contract renegotiation, and tcpm to put TCPC into low - * power mode if required. - */ - msleep(1500); -} diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h deleted file mode 100644 index 8b05c30f4c..0000000000 --- a/baseboard/octopus/baseboard.h +++ /dev/null @@ -1,322 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Octopus board configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/******************************************************************************* - * EC Config - */ - -/* - * By default, enable all console messages excepted HC, ACPI and event: - * The sensor stack is generating a lot of activity. - */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) - -/* - * Variant EC defines. Pick one: - * VARIANT_OCTOPUS_EC_NPCX796FB - * VARIANT_OCTOPUS_EC_ITE8320 - */ -#if defined(VARIANT_OCTOPUS_EC_NPCX796FB) - /* NPCX7 config */ - #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ - #define NPCX_TACH_SEL2 0 /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */ - #define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ - - /* Internal SPI flash on NPCX7 */ - /* Flash is 1MB but reserve half for future use. */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) - - #define CONFIG_SPI_FLASH_REGS - #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ - - /* I2C Bus Configuration */ - #define I2C_PORT_BATTERY NPCX_I2C_PORT0_0 - #define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 - #define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 - #define I2C_PORT_EEPROM NPCX_I2C_PORT3_0 - #define I2C_PORT_CHARGER NPCX_I2C_PORT4_1 - #define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 - #define I2C_ADDR_EEPROM_FLAGS 0x50 - - /* Enable PSL hibernate mode. */ - #define CONFIG_HIBERNATE_PSL - - /* EC variant determines USB-C variant */ - #define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS - - /* Allow the EC to enter deep sleep in S0 */ - #define CONFIG_LOW_POWER_S0 -#elif defined(VARIANT_OCTOPUS_EC_ITE8320) - /* IT83XX config */ - #define CONFIG_IT83XX_VCC_1P8V - /* I2C Bus Configuration */ - #define I2C_PORT_BATTERY IT83XX_I2C_CH_A /* Shared bus */ - #define I2C_PORT_CHARGER IT83XX_I2C_CH_A /* Shared bus */ - #define I2C_PORT_SENSOR IT83XX_I2C_CH_B - #define I2C_PORT_USBC0 IT83XX_I2C_CH_C - #define I2C_PORT_USBC1 IT83XX_I2C_CH_E - #define I2C_PORT_USB_MUX I2C_PORT_USBC0 /* For MUX driver */ - #define I2C_PORT_EEPROM IT83XX_I2C_CH_F - #define I2C_ADDR_EEPROM_FLAGS 0x50 - #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 - - /* EC variant determines USB-C variant */ - #define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS -#else - #error Must define a VARIANT_OCTOPUS_EC -#endif /* VARIANT_OCTOPUS_EC */ - -/* Common EC defines */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 -#define CONFIG_CRC8 -#define CONFIG_CBI_EEPROM -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_DPTF -#define CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA -#define CONFIG_BOARD_HAS_RTC_RESET -#define CONFIG_LED_ONOFF_STATES -#define CONFIG_CMD_CHARGEN - -/* Port80 -- allow larger buffer for port80 messages */ -#undef CONFIG_PORT80_HISTORY_LEN -#define CONFIG_PORT80_HISTORY_LEN 256 - -/* - * We don't need CONFIG_BACKLIGHT_LID since hardware AND's LID_OPEN and AP - * signals with EC backlight enable signal. - */ - -/******************************************************************************* - * Battery/Charger/Power Config - */ - -/* - * Variant charger defines. Pick one: - * VARIANT_OCTOPUS_CHARGER_ISL9238 - * VARIANT_OCTOPUS_CHARGER_BQ25703 - */ -#if defined(VARIANT_OCTOPUS_CHARGER_ISL9238) - #define CONFIG_CHARGER_ISL9238 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 - /* - * ISL923x driver sets "Adapter insertion to Switching Debounce" - * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms - */ - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 -#elif defined(VARIANT_OCTOPUS_CHARGER_BQ25703) - #define CONFIG_CHARGER_BQ25703 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 - /* - * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time. - */ - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 50 -#elif defined(CONFIG_CHARGER_RUNTIME_CONFIG) - #define CONFIG_CHARGER_ISL9238 - #define CONFIG_CHARGER_BQ25710 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC_BQ25710 10 - - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 -#else - #error Must define a VARIANT_OCTOPUS_CHARGER -#endif /* VARIANT_OCTOPUS_CHARGER */ - -/* Common charger defines */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER -#define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_USB_CHARGER - -/* Common battery defines */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_BATTERY_SMART - -/******************************************************************************* - * USB-C Configs - * Automatically defined by VARIANT_OCTOPUS_EC_ variant. - */ - - /* - * Variant USBC defines. Pick one: - * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS - * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires) - */ -#if defined(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS) - #define CONFIG_USB_PD_TCPC_LOW_POWER - #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#if !defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - #define CONFIG_USB_PD_TCPM_ANX7447 /* C0 TCPC: ANX7447QN */ -#endif - #define CONFIG_USB_PD_TCPM_PS8751 /* C1 TCPC: PS8751 */ - #define CONFIG_USB_PD_VBUS_DETECT_TCPC - #define CONFIG_USBC_PPC_NX20P3483 -#elif defined(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS) - #undef CONFIG_USB_PD_TCPC_LOW_POWER - #undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - #define CONFIG_USB_PD_VBUS_DETECT_PPC - #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0 & C1 TCPC: ITE EC */ - #define CONFIG_USB_MUX_IT5205 /* C0 MUX: IT5205 */ - #define CONFIG_USB_PD_TCPM_PS8751 /* C1 Mux: PS8751 */ - #define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER - #define CONFIG_USBC_PPC_SN5S330 /* C0 & C1 PPC: each SN5S330 */ - #define CONFIG_USBC_PPC_VCONN - #define CONFIG_USBC_PPC_DEDICATED_INT -#else - #error Must define a VARIANT_OCTOPUS_USBC -#endif /* VARIANT_OCTOPUS_USBC */ - -/* Common USB-C defines */ -#define USB_PD_PORT_TCPC_0 0 -#define USB_PD_PORT_TCPC_1 1 -#define CONFIG_USB_PID 0x5046 - -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_PD_3A_PORTS 0 -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_COMM_LOCKED -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_BC12_DETECT_MAX14637 -#undef CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS -#define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 100 -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_CMD_PPC_DUMP - -/* TODO(b/76218141): Use correct PD delay values */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* TODO(b/76218141): Use correct PD power values */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 - -/******************************************************************************* - * USB-A Configs - */ - -/* Common USB-A defines */ -#define USB_PORT_COUNT 2 -#define CONFIG_USB_PORT_POWER_SMART -#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY -#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP -#define CONFIG_USB_PORT_POWER_SMART_INVERTED -#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L -#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L - -/******************************************************************************* - * SoC / PCH Config - */ - - /* Common SoC / PCH defines */ -#define CONFIG_CHIPSET_GEMINILAKE -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_HOSTCMD_ESPI -/* TODO(b/74123961): Enable Virtual Wires after bringup */ -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_PP5000_CONTROL -#define CONFIG_EXTPOWER_GPIO - -/******************************************************************************* - * Keyboard Config - */ - -/* Common Keyboard Defines */ -#define CONFIG_CMD_KEYBOARD - -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 -#undef CONFIG_KEYBOARD_VIVALDI - -/******************************************************************************* - * Sensor Config - */ - -/* Common Sensor Defines */ -#define CONFIG_TABLET_MODE -#define CONFIG_GMR_TABLET_MODE -#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L -/* - * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup. - */ -#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US -#define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC) - -#ifndef VARIANT_OCTOPUS_NO_SENSORS -/* - * Interrupt and fifo are only used for base accelerometer - * and the lid sensor is polled real-time (in forced mode). - */ -#define CONFIG_ACCEL_INTERRUPTS -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#define CONFIG_ACCEL_FIFO -/* Power of 2 - Too large of a fifo causes too much timestamp jitter */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -/* Depends on how fast the AP boots and typical ODRs */ -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#endif /* VARIANT_OCTOPUS_NO_SENSORS */ - -/* - * Sensor stack in EC/Kernel depends on a hardware interrupt pin from EC->AP, so - * do not define CONFIG_MKBP_USE_HOST_EVENT since all octopus boards use - * hardware pin to send interrupt from EC -> AP (except casta). - */ -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" - -/* Forward declare common (within octopus) board-specific functions */ -void board_reset_pd_mcu(void); - -#ifdef VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS -void tcpc_alert_event(enum gpio_signal signal); -#endif - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/octopus/build.mk b/baseboard/octopus/build.mk deleted file mode 100644 index bb8a6f8267..0000000000 --- a/baseboard/octopus/build.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o cbi_ssfc.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o -baseboard-$(VARIANT_OCTOPUS_EC_NPCX796FB)+=variant_ec_npcx796fb.o -baseboard-$(VARIANT_OCTOPUS_EC_ITE8320)+=variant_ec_ite8320.o -baseboard-$(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS)+= \ - variant_usbc_standalone_tcpcs.o -baseboard-$(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS)+=variant_usbc_ec_tcpcs.o diff --git a/baseboard/octopus/cbi_ssfc.c b/baseboard/octopus/cbi_ssfc.c deleted file mode 100644 index 80d8614eb5..0000000000 --- a/baseboard/octopus/cbi_ssfc.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "cbi_ssfc.h" -#include "common.h" -#include "console.h" -#include "cros_board_info.h" -#include "hooks.h" - -/**************************************************************************** - * Octopus CBI Second Source Factory Cache - */ - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) - -/* Cache SSFC on init since we don't expect it to change in runtime */ -static uint32_t cached_ssfc; - -static void cbi_ssfc_init(void) -{ - if (cbi_get_ssfc(&cached_ssfc) != EC_SUCCESS) - /* Default to 0 when CBI isn't populated */ - cached_ssfc = 0; - - CPRINTS("CBI SSFC: 0x%04X", cached_ssfc); -} -DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); - -enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void) -{ - return ((cached_ssfc & SSFC_TCPC_P1_MASK) >> SSFC_TCPC_P1_OFFSET); -} - -enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void) -{ - return ((cached_ssfc & SSFC_PPC_P1_MASK) >> SSFC_PPC_P1_OFFSET); -} - -enum ssfc_charger get_cbi_ssfc_charger(void) -{ - return ((cached_ssfc & SSFC_CHARGER_MASK) >> SSFC_CHARGER_OFFSET); -} - -enum ssfc_sensor get_cbi_ssfc_sensor(void) -{ - return ((cached_ssfc & SSFC_SENSOR_MASK) >> SSFC_SENSOR_OFFSET); -} diff --git a/baseboard/octopus/cbi_ssfc.h b/baseboard/octopus/cbi_ssfc.h deleted file mode 100644 index b762336e59..0000000000 --- a/baseboard/octopus/cbi_ssfc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef _OCTOPUS_CBI_SSFC__H_ -#define _OCTOPUS_CBI_SSFC__H_ - -/**************************************************************************** - * Octopus CBI Second Source Factory Cache - */ - -/* - * TCPC Port 1 (Bits 0-2) - */ -enum ssfc_tcpc_p1 { - SSFC_TCPC_P1_DEFAULT, - SSFC_TCPC_P1_PS8751, - SSFC_TCPC_P1_PS8755, -}; -#define SSFC_TCPC_P1_OFFSET 0 -#define SSFC_TCPC_P1_MASK GENMASK(2, 0) - -/* - * PPC Port 1 (Bits 3-5) - */ -enum ssfc_ppc_p1 { - SSFC_PPC_P1_DEFAULT, - SSFC_PPC_P1_NX20P348X, - SSFC_PPC_P1_SYV682X, -}; -#define SSFC_PPC_P1_OFFSET 3 -#define SSFC_PPC_P1_MASK GENMASK(5, 3) - -/* - * Charger (Bits 8-6) - */ -enum ssfc_charger { - SSFC_CHARGER_DEFAULT, - SSFC_CHARGER_ISL9238, - SSFC_CHARGER_BQ25710, -}; -#define SSFC_CHARGER_OFFSET 6 -#define SSFC_CHARGER_MASK GENMASK(8, 6) - -/* - * Audio (Bits 11-9) - */ - -/* - * Sensor (Bits 14-12) - */ -enum ssfc_sensor { - SSFC_SENSOR_DEFAULT, - SSFC_SENSOR_BMI160, - SSFC_SENSOR_ICM426XX, -}; -#define SSFC_SENSOR_OFFSET 12 -#define SSFC_SENSOR_MASK GENMASK(14, 12) - -enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void); -enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void); -enum ssfc_charger get_cbi_ssfc_charger(void); -enum ssfc_sensor get_cbi_ssfc_sensor(void); - -#endif /* _OCTOPUS_CBI_SSFC__H_ */ diff --git a/baseboard/octopus/usb_pd_policy.c b/baseboard/octopus/usb_pd_policy.c deleted file mode 100644 index 3dd6ad29f5..0000000000 --- a/baseboard/octopus/usb_pd_policy.c +++ /dev/null @@ -1,78 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Shared USB-C policy for octopus boards */ - -#include "charge_manager.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "system.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -int pd_check_vconn_swap(int port) -{ - /* Only allow vconn swap if pp5000_A rail is enabled */ - return gpio_get_level(GPIO_EN_PP5000); -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC -int pd_snk_is_vbus_provided(int port) -{ - return ppc_is_vbus_present(port); -} -#endif - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} diff --git a/baseboard/octopus/variant_ec_ite8320.c b/baseboard/octopus/variant_ec_ite8320.c deleted file mode 100644 index 459ea113b3..0000000000 --- a/baseboard/octopus/variant_ec_ite8320.c +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_OCTOPUS_EC_ITE8320 configuration */ - -#include "gpio.h" -#include "i2c.h" -#include "util.h" - -/******************************************************************************/ -/* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_POWER_BUTTON_L, - /* - * The PPC interrupts (which fire when Vbus changes) is a proxy for - * AC_PRESENT. This allows us to turn off the PPC SNK FETS during - * hibernation which saves power. Once the EC wakes up, it will enable - * the SNK FETs and power will make it to the rest of the system. - */ - GPIO_USB_C0_PD_INT_ODL, - GPIO_USB_C1_PD_INT_ODL, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/******************************************************************************/ -/* I2C port map configuration */ -const struct i2c_port_t i2c_ports[] = { - {"power", IT83XX_I2C_CH_A, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA}, - {"sensor", IT83XX_I2C_CH_B, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA}, - {"usbc0", IT83XX_I2C_CH_C, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, - {"usbc1", IT83XX_I2C_CH_E, 400, GPIO_I2C4_SCL, GPIO_I2C4_SDA}, - {"eeprom", IT83XX_I2C_CH_F, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA}, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); diff --git a/baseboard/octopus/variant_ec_npcx796fb.c b/baseboard/octopus/variant_ec_npcx796fb.c deleted file mode 100644 index bccb360563..0000000000 --- a/baseboard/octopus/variant_ec_npcx796fb.c +++ /dev/null @@ -1,53 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_OCTOPUS_EC_NPCX796FB configuration */ - -#include "charge_manager.h" -#include "gpio.h" -#include "i2c.h" -#include "power.h" -#ifdef CONFIG_PWM -#include "pwm.h" -#include "pwm_chip.h" -#endif -#include "timer.h" -#include "usbc_ppc.h" -#include "util.h" - -/******************************************************************************/ -/* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_AC_PRESENT, - GPIO_POWER_BUTTON_L, - /* EC_RST_ODL needs to wake device while in PSL hibernate. */ - GPIO_EC_RST_ODL, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/******************************************************************************/ -/* I2C port map configuration */ -const struct i2c_port_t i2c_ports[] = { - {"battery", I2C_PORT_BATTERY, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA}, - {"tcpc0", I2C_PORT_TCPC0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA}, - {"tcpc1", I2C_PORT_TCPC1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, - {"eeprom", I2C_PORT_EEPROM, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA}, - {"charger", I2C_PORT_CHARGER, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA}, -#ifndef VARIANT_OCTOPUS_NO_SENSORS - {"sensor", I2C_PORT_SENSOR, 100, GPIO_I2C7_SCL, GPIO_I2C7_SDA}, -#endif -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -#ifdef CONFIG_PWM -/******************************************************************************/ -/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = PWM_CONFIG_DSLEEP, - .freq = 100 }, -}; -BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -#endif diff --git a/baseboard/octopus/variant_usbc_ec_tcpcs.c b/baseboard/octopus/variant_usbc_ec_tcpcs.c deleted file mode 100644 index 2e3248410f..0000000000 --- a/baseboard/octopus/variant_usbc_ec_tcpcs.c +++ /dev/null @@ -1,159 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_OCTOPUS_USBC_EC_TCPCS configuration */ - -#include "charge_state.h" -#include "common.h" -#include "console.h" -#include "driver/ppc/sn5s330.h" -#include "driver/tcpm/it83xx_pd.h" -#include "driver/usb_mux/it5205.h" -#include "driver/tcpm/ps8xxx.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/tcpm.h" -#include "gpio.h" -#include "hooks.h" -#include "system.h" -#include "tcpm/tcpci.h" -#include "usb_mux.h" -#include "usbc_ppc.h" -#include "util.h" - -#define USB_PD_PORT_ITE_0 0 -#define USB_PD_PORT_ITE_1 1 - -/******************************************************************************/ -/* USB-C TPCP Configuration */ -const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_ITE_0] = { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it83xx_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, - [USB_PD_PORT_ITE_1] = { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it83xx_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, -}; - -/******************************************************************************/ -/* USB-C MUX Configuration */ - -/* TODO(crbug.com/826441): Consolidate this logic with other impls */ -static void board_it83xx_hpd_status(const struct usb_mux *me, - mux_state_t mux_state) -{ - int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0; - int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0; - enum gpio_signal gpio = me->usb_port ? - GPIO_USB_C1_HPD_1V8_ODL : GPIO_USB_C0_HPD_1V8_ODL; - - /* Invert HPD level since GPIOs are active low. */ - hpd_lvl = !hpd_lvl; - - gpio_set_level(gpio, hpd_lvl); - if (hpd_irq) { - gpio_set_level(gpio, 1); - msleep(1); - gpio_set_level(gpio, hpd_lvl); - } -} - -/* This configuration might be override by each boards */ -struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_ITE_0] = { - .usb_port = USB_PD_PORT_ITE_0, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, - .driver = &it5205_usb_mux_driver, - .hpd_update = &board_it83xx_hpd_status, - }, - [USB_PD_PORT_ITE_1] = { - .usb_port = USB_PD_PORT_ITE_1, - /* Use PS8751 as mux only */ - .i2c_port = I2C_PORT_USBC1, - .i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS, - .flags = USB_MUX_FLAG_NOT_TCPC, - .driver = &ps8xxx_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - } -}; - -/******************************************************************************/ -/* USB-C PPC Configuration */ -struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_ITE_0] = { - .i2c_port = I2C_PORT_USBC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_ITE_1] = { - .i2c_port = I2C_PORT_USBC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/******************************************************************************/ -/* Power Delivery and charing functions */ - -void variant_tcpc_init(void) -{ - /* Enable PPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL); -} -/* Called after the baseboard_tcpc_init (via +3) */ -DECLARE_HOOK(HOOK_INIT, variant_tcpc_init, HOOK_PRIO_INIT_I2C + 3); - -uint16_t tcpc_get_alert_status(void) -{ - /* - * Since C0/C1 TCPC are embedded within EC, we don't need the PDCMD - * tasks.The (embedded) TCPC status since chip driver code will - * handles its own interrupts and forward the correct events to - * the PD_C0 task. See it83xx/intc.c - */ - return 0; -} - -/** - * Reset all system PD/TCPC MCUs -- currently called from both - * handle_pending_reboot() in common/system.c and baseboard_tcpc_init() in the - * octopus/baseboard.c - */ -void board_reset_pd_mcu(void) -{ - /* - * C0 & C1: The internal TCPC on ITE EC does not have a reset signal, - * but it will get reset when the EC gets reset. We will, however, - * reset the USB muxes here. - */ - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0); - gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0); - - msleep(PS8XXX_RESET_DELAY_MS); - - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1); - gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1); -} - -void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) -{ - /* - * We ignore the cc_pin because the polarity should already be set - * correctly in the PPC driver via the pd state machine. - */ - if (ppc_set_vconn(port, enabled) != EC_SUCCESS) - cprints(CC_USBPD, "C%d: Failed %sabling vconn", - port, enabled ? "en" : "dis"); -} diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c deleted file mode 100644 index fb5d466e65..0000000000 --- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c +++ /dev/null @@ -1,216 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS configuration */ - -#include "charge_state.h" -#include "common.h" -#include "console.h" -#include "driver/ppc/nx20p348x.h" -#include "driver/tcpm/anx7447.h" -#include "driver/tcpm/ps8xxx.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/tcpm.h" -#include "gpio.h" -#include "hooks.h" -#include "system.h" -#include "tcpm/tcpci.h" -#include "usb_mux.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) - -/******************************************************************************/ -/* USB-C TPCP Configuration */ -const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC0, - .addr_flags = PS8751_I2C_ADDR1_FLAGS, - }, - .drv = &ps8xxx_tcpm_drv, -#else - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC0, - .addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS, - }, - .drv = &anx7447_tcpm_drv, -#endif - }, - [USB_PD_PORT_TCPC_1] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC1, - .addr_flags = PS8751_I2C_ADDR1_FLAGS, - }, - .drv = &ps8xxx_tcpm_drv, - }, -}; - -/******************************************************************************/ -/* USB-C MUX Configuration */ - -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) -static int ps8751_tune_mux(const struct usb_mux *me) -{ - /* Tune USB mux registers for casta's port 0 Rx measurement */ - mux_write(me, PS8XXX_REG_MUX_USB_C2SS_EQ, 0x40); - return EC_SUCCESS; -} -#endif - -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .usb_port = USB_PD_PORT_TCPC_0, -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - .board_init = &ps8751_tune_mux, -#else - .driver = &anx7447_usb_mux_driver, - .hpd_update = &anx7447_tcpc_update_hpd_status, -#endif - }, - [USB_PD_PORT_TCPC_1] = { - .usb_port = USB_PD_PORT_TCPC_1, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - } -}; - -/******************************************************************************/ -/* USB-C PPC Configuration */ -struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, - .drv = &nx20p348x_drv, - }, - [USB_PD_PORT_TCPC_1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, - .drv = &nx20p348x_drv, - }, -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/******************************************************************************/ -/* Power Delivery and charing functions */ - -void tcpc_alert_event(enum gpio_signal signal) -{ - int port = -1; - - switch (signal) { - case GPIO_USB_C0_MUX_INT_ODL: - port = 0; - break; - case GPIO_USB_C1_MUX_INT_ODL: - port = 1; - break; - default: - return; - } - - schedule_deferred_pd_interrupt(port); -} - -void variant_tcpc_init(void) -{ - /* Enable PPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_PD_C0_INT_ODL); - gpio_enable_interrupt(GPIO_USB_PD_C1_INT_ODL); - - /* Enable TCPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_MUX_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_MUX_INT_ODL); -} -/* Called after the baseboard_tcpc_init (via +3) */ -DECLARE_HOOK(HOOK_INIT, variant_tcpc_init, HOOK_PRIO_INIT_I2C + 3); - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - - if (!gpio_get_level(GPIO_USB_C0_MUX_INT_ODL)) { -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - if (gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) -#else - if (!gpio_is_implemented(GPIO_USB_C0_PD_RST) || - !gpio_get_level(GPIO_USB_C0_PD_RST)) -#endif - status |= PD_STATUS_TCPC_ALERT_0; - } - - if (!gpio_get_level(GPIO_USB_C1_MUX_INT_ODL)) { - if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL)) - status |= PD_STATUS_TCPC_ALERT_1; - } - - return status; -} - -/** - * Reset all system PD/TCPC MCUs -- currently only called from - * handle_pending_reboot() in common/power.c just before hard - * resetting the system. This logic is likely not needed as the - * PP3300_A rail should be dropped on EC reset. - */ -void board_reset_pd_mcu(void) -{ -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - /* - * C0: Assert reset to TCPC0 (PS8751) for required delay if we have a - * battery - */ - if (battery_is_present() == BP_YES) { - /* - * TODO(crbug:846412): After refactor, ensure that battery has - * enough charge to last the reboot as well - */ - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0); - msleep(PS8XXX_RESET_DELAY_MS); - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1); - } -#else - /* - * C0: Assert reset to TCPC0 (ANX7447) for required delay (1ms) only if - * we have a battery - * - * Note: The TEST_R pin is not hooked up to a GPIO on all boards, so - * verify the name exists before setting it. After the name is - * introduced for later board firmware, this pin will still be wired - * to USB2_OTG_ID on the proto boards, which should be set to open - * drain so it can't be driven high. - */ - if (gpio_is_implemented(GPIO_USB_C0_PD_RST) && - battery_is_present() == BP_YES) { - gpio_set_level(GPIO_USB_C0_PD_RST, 1); - msleep(ANX74XX_RESET_HOLD_MS); - gpio_set_level(GPIO_USB_C0_PD_RST, 0); - msleep(ANX74XX_RESET_FINISH_MS); - } -#endif - /* - * C1: Assert reset to TCPC1 (PS8751) for required delay (1ms) only if - * we have a battery, otherwise we may brown out the system. - */ - if (battery_is_present() == BP_YES) { - /* - * TODO(crbug:846412): After refactor, ensure that battery has - * enough charge to last the reboot as well - */ - gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0); - msleep(PS8XXX_RESET_DELAY_MS); - gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1); - } else { - CPRINTS("Skipping C1 TCPC reset because no battery"); - } -} |