diff options
Diffstat (limited to 'board/adlrvpp_ite')
-rw-r--r-- | board/adlrvpp_ite/board.c | 2 | ||||
-rw-r--r-- | board/adlrvpp_ite/board.h | 82 | ||||
-rw-r--r-- | board/adlrvpp_ite/build.mk | 2 | ||||
-rw-r--r-- | board/adlrvpp_ite/ec.tasklist | 2 | ||||
-rw-r--r-- | board/adlrvpp_ite/gpio.inc | 6 |
5 files changed, 47 insertions, 47 deletions
diff --git a/board/adlrvpp_ite/board.c b/board/adlrvpp_ite/board.c index 15aa1c46d7..aa2764f823 100644 --- a/board/adlrvpp_ite/board.c +++ b/board/adlrvpp_ite/board.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/board/adlrvpp_ite/board.h b/board/adlrvpp_ite/board.h index 55b56854ea..37662a5d52 100644 --- a/board/adlrvpp_ite/board.h +++ b/board/adlrvpp_ite/board.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,56 +19,56 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC -#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC -#define GPIO_LID_OPEN GPIO_SMC_LID -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC -#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N -#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC -#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC -#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L -#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC -#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP -#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R -#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT -#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R -#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC -#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC -#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC -#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC -#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC -#define GPIO_EN_PP3300_A GPIO_EC_DS3 -#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION +#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC +#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC +#define GPIO_LID_OPEN GPIO_SMC_LID +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC +#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N +#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC +#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC +#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L +#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP +#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R +#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT +#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R +#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC +#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC +#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC +#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC +#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC +#define GPIO_EN_PP3300_A GPIO_EC_DS3 +#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION /* I2C ports & Configs */ #define CONFIG_IT83XX_SMCLK2_ON_GPC7 -#define I2C_PORT_CHARGER IT83XX_I2C_CH_B +#define I2C_PORT_CHARGER IT83XX_I2C_CH_B /* Battery */ -#define I2C_PORT_BATTERY IT83XX_I2C_CH_B +#define I2C_PORT_BATTERY IT83XX_I2C_CH_B /* Board ID */ -#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B +#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B /* Port 80 */ -#define I2C_PORT_PORT80 IT83XX_I2C_CH_B +#define I2C_PORT_PORT80 IT83XX_I2C_CH_B /* USB-C I2C */ -#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C -#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F +#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C +#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F #if defined(HAS_TASK_PD_C2) -#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E -#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D +#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E +#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D #endif /* TCPC */ @@ -76,12 +76,12 @@ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 /* Config Fan */ -#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N -#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC +#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N +#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC /* Increase EC speed */ #undef PLL_CLOCK -#define PLL_CLOCK 96000000 +#define PLL_CLOCK 96000000 #ifndef __ASSEMBLER__ diff --git a/board/adlrvpp_ite/build.mk b/board/adlrvpp_ite/build.mk index fe5f548324..9da9f60561 100644 --- a/board/adlrvpp_ite/build.mk +++ b/board/adlrvpp_ite/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/board/adlrvpp_ite/ec.tasklist b/board/adlrvpp_ite/ec.tasklist index c110617d6b..8bd63b1730 100644 --- a/board/adlrvpp_ite/ec.tasklist +++ b/board/adlrvpp_ite/ec.tasklist @@ -1,5 +1,5 @@ /* - * Copyright 2020 The Chromium OS Authors. All rights reserved. + * Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/board/adlrvpp_ite/gpio.inc b/board/adlrvpp_ite/gpio.inc index f7cb8ea19c..22b97a7eff 100644 --- a/board/adlrvpp_ite/gpio.inc +++ b/board/adlrvpp_ite/gpio.inc @@ -1,6 +1,6 @@ /* -*- mode:c -*- * - * Copyright 2020 The Chromium OS Authors. All rights reserved. + * Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,10 +21,10 @@ GPIO_INT(PCH_SLP_S0_N, PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(VCCPDSW_3P3_EC, PIN(I, 3), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(VCCST_PWRGD, PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PM_SLP_SUS_EC, PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt) -#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 +#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3 GPIO_INT(SLP_S3_R_L, PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt) #endif -#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 +#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 GPIO_INT(SLP_S4_R_L, PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt) #endif |