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-rw-r--r--board/adlrvpp_ite/board.c117
-rw-r--r--board/adlrvpp_ite/board.h103
-rw-r--r--board/adlrvpp_ite/build.mk14
-rw-r--r--board/adlrvpp_ite/ec.tasklist27
-rw-r--r--board/adlrvpp_ite/gpio.inc202
-rw-r--r--board/adlrvpp_ite/vif_override.xml3
6 files changed, 0 insertions, 466 deletions
diff --git a/board/adlrvpp_ite/board.c b/board/adlrvpp_ite/board.c
deleted file mode 100644
index 835cdcb986..0000000000
--- a/board/adlrvpp_ite/board.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADLRVP-ITE board-specific configuration */
-#include "button.h"
-#include "fan.h"
-#include "fusb302.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "it83xx_pd.h"
-#include "lid_switch.h"
-#include "pca9675.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
- [I2C_CHAN_FLASH] = {
- .name = "ec_flash",
- .port = IT83XX_I2C_CH_A,
- .kbps = 100,
- .scl = GPIO_EC_I2C_PROG_SCL,
- .sda = GPIO_EC_I2C_PROG_SDA,
- },
- [I2C_CHAN_BATT_CHG] = {
- .name = "batt_chg",
- .port = IT83XX_I2C_CH_B,
- .kbps = 100,
- .scl = GPIO_SMB_BS_CLK,
- .sda = GPIO_SMB_BS_DATA,
- },
- [I2C_CHAN_TYPEC_0] = {
- .name = "typec_0",
- .port = IT83XX_I2C_CH_C,
- .kbps = 400,
- .scl = GPIO_USBC_TCPC_I2C_CLK_P0,
- .sda = GPIO_USBC_TCPC_I2C_DATA_P0,
- },
- [I2C_CHAN_TYPEC_1] = {
- .name = "typec_1",
- .port = IT83XX_I2C_CH_F,
- .kbps = 400,
- .scl = GPIO_USBC_TCPC_I2C_CLK_P2,
- .sda = GPIO_USBC_TCPC_I2C_DATA_P2,
- },
-#if defined(HAS_TASK_PD_C2)
- [I2C_CHAN_TYPEC_2] = {
- .name = "typec_2",
- .port = IT83XX_I2C_CH_E,
- .kbps = 400,
- .scl = GPIO_USBC_TCPC_I2C_CLK_P1,
- .sda = GPIO_USBC_TCPC_I2C_DATA_P1,
- },
- [I2C_CHAN_TYPEC_3] = {
- .name = "typec_3",
- .port = IT83XX_I2C_CH_D,
- .kbps = 400,
- .scl = GPIO_USBC_TCPC_I2C_CLK_P3,
- .sda = GPIO_USBC_TCPC_I2C_DATA_P3,
- },
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[] = {
- [TYPE_C_PORT_0] = {
- .bus_type = EC_BUS_TYPE_EMBEDDED,
- /* TCPC is embedded within EC so no i2c config needed */
- .drv = &it83xx_tcpm_drv,
- },
-#if defined(HAS_TASK_PD_C1)
- [TYPE_C_PORT_1] = {
- .bus_type = EC_BUS_TYPE_I2C,
- .i2c_info = {
- .port = I2C_PORT_TYPEC_1,
- .addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
- },
- .drv = &fusb302_tcpm_drv,
- },
-#endif
-#if defined(HAS_TASK_PD_C2)
- [TYPE_C_PORT_2] = {
- .bus_type = EC_BUS_TYPE_I2C,
- .i2c_info = {
- .port = I2C_PORT_TYPEC_2,
- .addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
- },
- .drv = &fusb302_tcpm_drv,
- },
-#endif
-#if defined(HAS_TASK_PD_C3)
- [TYPE_C_PORT_3] = {
- .bus_type = EC_BUS_TYPE_I2C,
- .i2c_info = {
- .port = I2C_PORT_TYPEC_3,
- .addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
- },
- .drv = &fusb302_tcpm_drv,
- },
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
diff --git a/board/adlrvpp_ite/board.h b/board/adlrvpp_ite/board.h
deleted file mode 100644
index a5f5c445ad..0000000000
--- a/board/adlrvpp_ite/board.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-ITE board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* ITE EC variant */
-#define VARIANT_INTELRVP_EC_IT8320
-
-#include "adlrvp.h"
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC
-#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC
-#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC
-#define GPIO_LID_OPEN GPIO_SMC_LID
-#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC
-#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N
-#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC
-#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC
-#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
-#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L
-#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC
-#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD GPIO_RSMRST_PWRGD_EC
-#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC
-#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC
-#define GPIO_WP_L GPIO_EC_WP_ODL
-#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
-#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R
-#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
-#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R
-#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC
-#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC
-#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC
-#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC
-#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC
-#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
-#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC
-#define GPIO_EN_PP3300_A GPIO_EC_DS3
-#define GMR_TABLET_MODE_GPIO_L GPIO_SLATE_MODE_INDICATION
-
-/* I2C ports & Configs */
-#define CONFIG_IT83XX_SMCLK2_ON_GPC7
-
-#define I2C_PORT_CHARGER IT83XX_I2C_CH_B
-
-/* Battery */
-#define I2C_PORT_BATTERY IT83XX_I2C_CH_B
-
-/* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B
-
-/* Port 80 */
-#define I2C_PORT_PORT80 IT83XX_I2C_CH_B
-
-/* USB-C I2C */
-#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C
-#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F
-#if defined(HAS_TASK_PD_C2)
-#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E
-#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D
-#endif
-
-/* TCPC */
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-
-/* Config Fan */
-#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N
-#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
-
-/* Increase EC speed */
-#undef PLL_CLOCK
-#define PLL_CLOCK 96000000
-
-#ifndef __ASSEMBLER__
-
-enum adlrvp_i2c_channel {
- I2C_CHAN_FLASH,
- I2C_CHAN_BATT_CHG,
- I2C_CHAN_TYPEC_0,
- I2C_CHAN_TYPEC_1,
-#if defined(HAS_TASK_PD_C2)
- I2C_CHAN_TYPEC_2,
- I2C_CHAN_TYPEC_3,
-#endif
- I2C_CHAN_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_ite/build.mk b/board/adlrvpp_ite/build.mk
deleted file mode 100644
index fe5f548324..0000000000
--- a/board/adlrvpp_ite/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel ADL-P-RVP-ITE board-specific configuration
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=intelrvp
-
-board-y=board.o
diff --git a/board/adlrvpp_ite/ec.tasklist b/board/adlrvpp_ite/ec.tasklist
deleted file mode 100644
index 5cb10b2907..0000000000
--- a/board/adlrvpp_ite/ec.tasklist
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel ADL-P-RVP-ITE board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
- TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
- TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
- TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
- TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
- TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
- TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
- TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
- TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_C2, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_C3, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_INT_C3, pd_interrupt_handler_task, 3, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_ite/gpio.inc b/board/adlrvpp_ite/gpio.inc
deleted file mode 100644
index f4db15c4d5..0000000000
--- a/board/adlrvpp_ite/gpio.inc
+++ /dev/null
@@ -1,202 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-ITE board-specific configuration */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
-
-/* Power sequencing interrupts */
-GPIO_INT(ALL_SYS_PWRGD_EC, PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_EC, PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_N, PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCPDSW_3P3_EC, PIN(I, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCST_PWRGD, PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PM_SLP_SUS_EC, PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_R_L, PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_R_L, PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP, PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOL_DN_EC_R, PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(SMC_LID, PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(MECH_PWR_BTN_ODL, PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(EC_WP_ODL, PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)
-
-/* DC Jack presence coming from +VADP_OUT */
-GPIO_INT(STD_ADP_PRSNT, PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
-
-GPIO_INT(BC_ACOK_EC, PIN(K, 3), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
-
-GPIO_INT(UART_SERVO_TX_EC_RX, PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)
-
-/* USB-C interrupts */
-/* Using embedded TCPC for Port-0 */
-UNIMPLEMENTED(USBC_TCPC_ALRT_P0)
-GPIO(NC_USBC_TCPC_ALRT_P0, PIN(I, 7), GPIO_INPUT)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(J, 5), GPIO_INT_FALLING, ppc_interrupt)
-
-#if defined(HAS_TASK_PD_C1)
-GPIO_INT(USBC_TCPC_ALRT_P1, PIN(G, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(C, 4), GPIO_INT_FALLING, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P1, PIN(G, 0), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P1, PIN(C, 4), GPIO_INPUT)
-#endif
-
-#if defined(HAS_TASK_PD_C2)
-GPIO_INT(USBC_TCPC_ALRT_P2, PIN(J, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(E, 5), GPIO_INT_FALLING, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P2, PIN(J, 1), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P2, PIN(E, 5), GPIO_INPUT)
-#endif
-
-#if defined(HAS_TASK_PD_C3)
-GPIO_INT(USBC_TCPC_ALRT_P3, PIN(J, 3), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(E, 6), GPIO_INT_FALLING, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P3, PIN(J, 3), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P3, PIN(E, 6), GPIO_INPUT)
-#endif
-
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(ESPI_RST_R, PIN(D, 2), GPIO_INPUT)
-#endif
-
-#ifdef CONFIG_HOSTCMD_ESPI
-/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
-GPIO_INT(ESPI_RST_R, PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
-#endif
-
-/* Sensor Interrupts */
-GPIO_INT(SLATE_MODE_INDICATION, PIN(K, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, gmr_tablet_switch_isr)
-
-/* Power sequencing GPIOs */
-GPIO(SYS_RST_ODL_EC, PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(PROCHOT_EC, PIN(C, 0), GPIO_INPUT)
-GPIO(PM_RSMRST_EC, PIN(C, 6), GPIO_OUT_LOW)
-GPIO(PM_PWRBTN_N_EC, PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(EC_SPI_OE_N, PIN(I, 2), GPIO_OUT_LOW)
-
-GPIO(EC_PCH_MKBP_INT_ODL_EC, PIN(B, 7), GPIO_ODR_HIGH)
-GPIO(EDP_BKLT_EN, PIN(J, 6), GPIO_OUT_HIGH)
-GPIO(EC_DS3, PIN(L, 4), GPIO_OUT_LOW)
-UNIMPLEMENTED(EN_PP5000)
-
-/*
- * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86
- * power sequencing expects that PCH_SYS_PWROK is an output and will drive
- * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect
- * so that state can be monitored using the console.
- */
-GPIO(PCH_PWROK_EC_R, PIN(K, 4), GPIO_INPUT)
-GPIO(SYS_PWROK_EC, PIN(D, 1), GPIO_OUT_LOW)
-GPIO(DSW_PWROK_EC, PIN(L, 6), GPIO_OUT_LOW)
-
-/* Host communication GPIOs */
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(PLT_RST_L, PIN(H, 6), GPIO_INPUT | GPIO_PULL_UP) /* PCH_PLTRST_L */
-#endif
-GPIO(PCH_WAKE_N, PIN(J, 0), GPIO_ODR_HIGH)
-
-/* Battery present */
-GPIO(BAT_DET_EC, PIN(K, 0), GPIO_INPUT)
-
-/* LED */
-GPIO(LED_1_L_EC, PIN(A, 6), GPIO_OUT_HIGH) /* BAT_LED_GREEN_L LED_2_L */
-GPIO(LED_2_L_EC, PIN(A, 7), GPIO_OUT_HIGH) /* AC_LED_GREEN_L LED_1_L */
-
-/* H1 pins */
-GPIO(EC_H1_PACKET_MODE_EC, PIN(J, 4), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW_EC, PIN(K, 7), GPIO_OUT_LOW)
-
-/* Case Closed Debug Mode */
-GPIO_INT(CCD_MODE_ODL, PIN(B, 5), GPIO_INT_BOTH, board_connect_c0_sbu)
-
-/* FAN control pins */
-GPIO(EC_THRM_SEN_PWRGATE_N, PIN(K, 6), GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(EC_I2C_PROG_SCL, PIN(B, 3), GPIO_INPUT) /* I2C_A_SCL */
-GPIO(EC_I2C_PROG_SDA, PIN(B, 4), GPIO_INPUT) /* I2C_A_SDA */
-GPIO(SMB_BS_CLK, PIN(C, 1), GPIO_INPUT) /* I2C_B_SCL */
-GPIO(SMB_BS_DATA, PIN(C, 2), GPIO_INPUT) /* I2C_B_SDA */
-
-/* P0 IT83XX_I2C_CH_C */
-GPIO(USBC_TCPC_I2C_CLK_P0, PIN(C, 7), GPIO_INPUT) /* I2C_C_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P0, PIN(F, 7), GPIO_INPUT) /* I2C_C_SDA */
-
-/* P1 IT83XX_I2C_CH_F */
-GPIO(USBC_TCPC_I2C_CLK_P2, PIN(A, 4), GPIO_INPUT) /* I2C_F_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P2, PIN(A, 5), GPIO_INPUT) /* I2C_F_SDA */
-
-/* P2 IT83XX_I2C_CH_E */
-GPIO(USBC_TCPC_I2C_CLK_P1, PIN(E, 0), GPIO_INPUT) /* I2C_E_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P1, PIN(E, 7), GPIO_INPUT) /* I2C_E_SDA */
-
-/* P3 IT83XX_I2C_CH_D */
-GPIO(USBC_TCPC_I2C_CLK_P3, PIN(H, 1), GPIO_INPUT) /* I2C_D_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P3, PIN(H, 2), GPIO_INPUT) /* I2C_D_SDA */
-
-/* Unused 1.8V or 3.3V compatiable pins */
-GPIO(TP_DEVELOPER_MODE_EC, PIN(B, 2), GPIO_INPUT)
-GPIO(ESPI_CS1_N_R, PIN(D, 3), GPIO_INPUT)
-GPIO(SUSWARN, PIN(E, 1), GPIO_INPUT)
-GPIO(CPU_C10_GATE, PIN(G, 1), GPIO_INPUT)
-GPIO(TP_GPIO_G2, PIN(G, 2), GPIO_INPUT)
-GPIO(TP_GPIO_G6, PIN(G, 6), GPIO_INPUT)
-GPIO(BATT_DISABLE_EC, PIN(H, 0), GPIO_INPUT)
-GPIO(ME_G3_TO_M3_EC, PIN(H, 5), GPIO_INPUT)
-GPIO(SLP_S0_CS_EC, PIN(I, 0), GPIO_INPUT)
-GPIO(SMC_SHUTDOWN, PIN(K, 5), GPIO_INPUT)
-GPIO(CPU_CAT_ERR_MECC, PIN(L, 1), GPIO_INPUT)
-GPIO(SMC_ONOFF_N, PIN(L, 3), GPIO_INPUT) /* Power button interrupt without H1 */
-GPIO(STD_ADPT_CNTRL_EC, PIN(L, 5), GPIO_INPUT)
-GPIO(SMB_PCH_ALRT, PIN(L, 7), GPIO_INPUT)
-GPIO(ESPI_ALERT0_R, PIN(M, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Unused 3.3V compatiable pins */
-GPIO(TP_GPIO_A0, PIN(A, 0), GPIO_INPUT)
-GPIO(TP_GPIO_A1, PIN(A, 1), GPIO_INPUT)
-GPIO(TP_GPIO_A3, PIN(A, 3), GPIO_INPUT)
-GPIO(TP_GPC3, PIN(C, 3), GPIO_INPUT)
-GPIO(TP_GPC5, PIN(C, 5), GPIO_INPUT)
-GPIO(TP_GPIO_E3, PIN(E, 3), GPIO_INPUT)
-GPIO(TP_GPIO_H3, PIN(H, 3), GPIO_INPUT)
-GPIO(TP_GPIO_H4, PIN(H, 4), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C F SCL/SDA A4/A5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C A SCL/SDA B3/B4 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C B SCL/SDA C1/C2 */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C E SCL/SDA E0/E7 */
-ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C C SCL C7 */
-ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C C SDA F7 */
-ALTERNATE(PIN_MASK(H, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C D SCL/SDA H1/H2 */
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) /* UART1 B0/B1 */
-
-/* Alternate pins for ADC */
-ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE) /* ADC 1,6 -> I1,I6 */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE) /* ADC 13,15 -> L0,L2 */
-
-/* Alternate pins for FAN */
-ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE) /* PWM2 A2 */
-ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE) /* TACH1A D7 */
diff --git a/board/adlrvpp_ite/vif_override.xml b/board/adlrvpp_ite/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/adlrvpp_ite/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
- Definition from the USB-IF.
--->
View Lorry Controller Status