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-rw-r--r--board/adlrvpp_npcx/board.c105
-rw-r--r--board/adlrvpp_npcx/board.h113
-rw-r--r--board/adlrvpp_npcx/build.mk14
-rw-r--r--board/adlrvpp_npcx/ec.tasklist28
-rw-r--r--board/adlrvpp_npcx/gpio.inc176
-rw-r--r--board/adlrvpp_npcx/vif_override.xml3
6 files changed, 0 insertions, 439 deletions
diff --git a/board/adlrvpp_npcx/board.c b/board/adlrvpp_npcx/board.c
deleted file mode 100644
index d4221696f1..0000000000
--- a/board/adlrvpp_npcx/board.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADLRVP-NPCX board-specific configuration */
-#include "button.h"
-#include "fusb302.h"
-#include "lid_switch.h"
-#include "pca9675.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_pd_tcpm.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
- [I2C_CHAN_BATT_CHG] = {
- .name = "batt_chg",
- .port = I2C_PORT_CHARGER,
- .kbps = 100,
- .scl = GPIO_SMB_BS_CLK,
- .sda = GPIO_SMB_BS_DATA,
- },
- [I2C_CHAN_TYPEC_0] = {
- .name = "typec_0",
- .port = I2C_PORT_TYPEC_0,
- .kbps = 400,
- .scl = GPIO_USBC_TCPC_I2C_CLK_P0,
- .sda = GPIO_USBC_TCPC_I2C_DATA_P0,
- },
- [I2C_CHAN_TYPEC_1] = {
- .name = "typec_1",
- .port = I2C_PORT_TYPEC_1,
- .kbps = 400,
- .scl = GPIO_USBC_TCPC_I2C_CLK_P2,
- .sda = GPIO_USBC_TCPC_I2C_DATA_P2,
- },
-#if defined(HAS_TASK_PD_C2)
- [I2C_CHAN_TYPEC_2] = {
- .name = "typec_2",
- .port = I2C_PORT_TYPEC_2,
- .kbps = 400,
- .scl = GPIO_USBC_TCPC_I2C_CLK_P1,
- .sda = GPIO_USBC_TCPC_I2C_DATA_P1,
- },
-#endif
-#if defined(HAS_TASK_PD_C3)
- [I2C_CHAN_TYPEC_3] = {
- .name = "typec_3",
- .port = I2C_PORT_TYPEC_3,
- .kbps = 400,
- .scl = GPIO_USBC_TCPC_I2C_CLK_P3,
- .sda = GPIO_USBC_TCPC_I2C_DATA_P3,
- },
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[] = {
- [TYPE_C_PORT_0] = {
- .bus_type = EC_BUS_TYPE_I2C,
- .i2c_info = {
- .port = I2C_PORT_TYPEC_0,
- .addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
- },
- .drv = &fusb302_tcpm_drv,
- },
- [TYPE_C_PORT_1] = {
- .bus_type = EC_BUS_TYPE_I2C,
- .i2c_info = {
- .port = I2C_PORT_TYPEC_1,
- .addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
- },
- .drv = &fusb302_tcpm_drv,
- },
-#if defined(HAS_TASK_PD_C2)
- [TYPE_C_PORT_2] = {
- .bus_type = EC_BUS_TYPE_I2C,
- .i2c_info = {
- .port = I2C_PORT_TYPEC_2,
- .addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
- },
- .drv = &fusb302_tcpm_drv,
- },
-#endif
-#if defined(HAS_TASK_PD_C3)
- [TYPE_C_PORT_3] = {
- .bus_type = EC_BUS_TYPE_I2C,
- .i2c_info = {
- .port = I2C_PORT_TYPEC_3,
- .addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
- },
- .drv = &fusb302_tcpm_drv,
- },
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
diff --git a/board/adlrvpp_npcx/board.h b/board/adlrvpp_npcx/board.h
deleted file mode 100644
index 8cf70b81a8..0000000000
--- a/board/adlrvpp_npcx/board.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-NPCX board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* ITE EC variant */
-#define VARIANT_INTELRVP_EC_NPCX
-
-#include "adlrvp.h"
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-/* Power sequencing */
-#define GPIO_EC_SPI_OE_N GPIO_EC_SPI_OE_MECC
-#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD
-#define GPIO_RSMRST_L_PGOOD GPIO_RSMRST_PWRGD
-#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD
-#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
-#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3
-#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC_N
-#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_N
-#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N
-#define GPIO_EN_PP3300_A GPIO_EC_DS3
-#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK
-#define GPIO_PCH_DSW_PWROK GPIO_EC_DSW_PWROK
-
-/* Sensors */
-#define GMR_TABLET_MODE_GPIO_L GPIO_SLATE_MODE_INDICATION
-#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_N
-
-/* Buttons */
-#define GPIO_LID_OPEN GPIO_SMC_LID
-#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
-#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC
-#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
-
-/* H1 */
-#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
-#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
-#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
-
-/* AC & Battery */
-#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
-#define GPIO_AC_PRESENT GPIO_BC_ACOK
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET
-
-/* eSPI/Host communication */
-#define GPIO_ESPI_RESET_L GPIO_LPC_ESPI_RST_N
-#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N_MECC
-#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL
-
-/* LED */
-#define GPIO_BAT_LED_RED_L GPIO_LED_1_L
-#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L
-
-/* FAN */
-#define GPIO_FAN_POWER_EN GPIO_THERM_SEN_MECC
-
-/* I2C ports & Configs */
-/* Charger */
-#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
-
-/* Battery */
-#define I2C_PORT_BATTERY NPCX_I2C_PORT7_0
-
-/* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO NPCX_I2C_PORT7_0
-
-/* Port 80 */
-#define I2C_PORT_PORT80 NPCX_I2C_PORT7_0
-
-/* USB-C I2C */
-#define I2C_PORT_TYPEC_0 NPCX_I2C_PORT0_0
-/*
- * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2
- * on the RVP to reduce BOM stuffing options.
- */
-#define I2C_PORT_TYPEC_1 NPCX_I2C_PORT2_0
-#if defined(HAS_TASK_PD_C2)
-#define I2C_PORT_TYPEC_2 NPCX_I2C_PORT1_0
-#endif
-#if defined(HAS_TASK_PD_C3)
-#define I2C_PORT_TYPEC_3 NPCX_I2C_PORT3_0
-#endif
-
-#ifndef __ASSEMBLER__
-
-enum adlrvp_i2c_channel {
- I2C_CHAN_BATT_CHG,
- I2C_CHAN_TYPEC_0,
- I2C_CHAN_TYPEC_1,
-#if defined(HAS_TASK_PD_C2)
- I2C_CHAN_TYPEC_2,
-#endif
-#if defined(HAS_TASK_PD_C3)
- I2C_CHAN_TYPEC_3,
-#endif
- I2C_CHAN_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_npcx/build.mk b/board/adlrvpp_npcx/build.mk
deleted file mode 100644
index ec3450ee7e..0000000000
--- a/board/adlrvpp_npcx/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel ADL-P-RVP-NPCX board-specific configuration
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=intelrvp
-
-board-y=board.o
diff --git a/board/adlrvpp_npcx/ec.tasklist b/board/adlrvpp_npcx/ec.tasklist
deleted file mode 100644
index 6dddaa994c..0000000000
--- a/board/adlrvpp_npcx/ec.tasklist
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel ADL-P-RVP-NPCX board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
- TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
- TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
- TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
- TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
- TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
- TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
- TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
- TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_C2, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_C3, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, ULTRA_TASK_STACK_SIZE) \
- TASK_ALWAYS(PD_INT_C3, pd_interrupt_handler_task, 3, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_npcx/gpio.inc b/board/adlrvpp_npcx/gpio.inc
deleted file mode 100644
index a059b1c6b6..0000000000
--- a/board/adlrvpp_npcx/gpio.inc
+++ /dev/null
@@ -1,176 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-NPCX board-specific configuration */
-
-#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
-
-/* Power sequencing interrupts */
-GPIO_INT(ALL_SYS_PWRGD, PIN(7, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD, PIN(3, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_N, PIN(A, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCPDSW_3P3, PIN(4, 5), GPIO_INT_BOTH, power_signal_interrupt)
-/* TODO: GPIO_INT(VCCST_PWRGD_MECC, PIN(7, 1), GPIO_INT_BOTH, power_signal_interrupt) */
-GPIO_INT(PM_SLP_SUS_EC_N, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PM_SLP_S3_N, PIN(B, 0), GPIO_INT_BOTH, power_signal_interrupt)
-#else
-GPIO(PM_SLP_S3_N, PIN(B, 0), GPIO_INPUT)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PM_SLP_S4_N, PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#else
-GPIO(PM_SLP_S4_N, PIN(A, 5), GPIO_INPUT)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP, PIN(6, 1), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOL_DN_EC, PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(SMC_LID, PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(MECH_PWR_BTN_ODL, PIN(0, 0), GPIO_INT_BOTH, power_button_interrupt)
-
-/* DC Jack presence coming from +VADP_OUT */
-GPIO_INT(STD_ADP_PRSNT, PIN(0, 2), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
-
-GPIO_INT(BC_ACOK, PIN(C, 6), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
-
-/* USB-C interrupts */
-GPIO_INT(USBC_TCPC_ALRT_P0, PIN(4, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_ALRT_P1, PIN(6, 2), GPIO_INT_BOTH, tcpc_alert_event)
-#if defined(HAS_TASK_PD_C2)
-GPIO_INT(USBC_TCPC_ALRT_P2, PIN(6, 3), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_ALRT_P3, PIN(6, 7), GPIO_INT_BOTH, tcpc_alert_event)
-#else
-GPIO(USBC_TCPC_ALRT_P2, PIN(6, 3), GPIO_INPUT)
-GPIO(USBC_TCPC_ALRT_P3, PIN(6, 7), GPIO_INPUT)
-#endif
-
-GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(F, 0), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(F, 1), GPIO_INT_BOTH, ppc_interrupt)
-#if defined(HAS_TASK_PD_C2)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(F, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(F, 3), GPIO_INT_BOTH, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_PPC_ALRT_P2, PIN(F, 2), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P3, PIN(F, 3), GPIO_INPUT)
-#endif
-
-/* Host communication GPIOs */
-GPIO(SMC_WAKE_SCI_N_MECC, PIN(A, 4), GPIO_ODR_HIGH)
-GPIO(EC_PCH_MKBP_INT_ODL, PIN(F, 5), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(LPC_ESPI_RST_N, PIN(5, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(PLT_RST_L, PIN(A, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PLTRST_L */
-#endif
-
-/* Sensor Interrupts */
-GPIO_INT(SLATE_MODE_INDICATION, PIN(E, 5), GPIO_INT_BOTH | GPIO_SEL_1P8V, gmr_tablet_switch_isr)
-GPIO(PROCHOT_EC_N, PIN(A, 7), GPIO_INPUT)
-
-/* Power sequencing GPIOs */
-GPIO(SYS_RST_ODL, PIN(C, 5), GPIO_ODR_HIGH)
-/* GPIOD3 (Rework: CPU_TACHO_FAN is swapped with PM_RSMRST_N) */
-GPIO(PM_RSMRST_N, PIN(D, 3), GPIO_OUT_LOW)
-GPIO(PM_PWRBTN_N, PIN(9, 7), GPIO_ODR_HIGH)
-GPIO(EC_SPI_OE_MECC, PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EC_DS3, PIN(C, 4), GPIO_OUT_LOW)
-UNIMPLEMENTED(EN_PP5000)
-
-/* PCH_PWROK_EC is an input, as it's driven by the Silego chip on RVP */
-GPIO(PCH_PWROK_EC, PIN(A, 0), GPIO_INPUT)
-GPIO(SYS_PWROK, PIN(9, 3), GPIO_OUT_LOW)
-GPIO(EC_DSW_PWROK, PIN(9, 5), GPIO_OUT_LOW)
-
-/* H1 pins */
-GPIO_INT(EC_FLASH_WP_ODL, PIN(9, 4), GPIO_INT_BOTH, switch_interrupt)
-GPIO(EC_H1_PACKET_MODE, PIN(E, 2), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW, PIN(D, 4), GPIO_OUT_LOW)
-
-/* Case Closed Debug Mode */
-GPIO_INT(CCD_MODE_ODL, PIN(F, 4), GPIO_INT_BOTH, board_connect_c0_sbu)
-
-/* Battery present */
-GPIO(BAT_DET, PIN(7, 6), GPIO_INPUT)
-
-/* EDP */
-GPIO(EDP_BKLT_EN_MECC, PIN(E, 1), GPIO_OUT_HIGH)
-
-/* LED */
-GPIO(LED_1_L, PIN(B, 6), GPIO_OUT_HIGH)
-GPIO(LED_2_L, PIN(B, 7), GPIO_OUT_HIGH)
-
-/* FAN control pins */
-GPIO(THERM_SEN_MECC, PIN(C, 0), GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(SMB_BS_CLK, PIN(B, 3), GPIO_INPUT) /* I2C7_SCL0 */
-GPIO(SMB_BS_DATA, PIN(B, 2), GPIO_INPUT) /* I2C7_SDA0 */
-GPIO(USBC_TCPC_I2C_CLK_P0, PIN(B, 5), GPIO_INPUT) /* I2C0_SCL0 */
-GPIO(USBC_TCPC_I2C_DATA_P0, PIN(B, 4), GPIO_INPUT) /* I2C0_SDA0 */
-GPIO(USBC_TCPC_I2C_CLK_P2, PIN(9, 2), GPIO_INPUT) /* I2C2_SCL0 */
-GPIO(USBC_TCPC_I2C_DATA_P2, PIN(9, 1), GPIO_INPUT) /* I2C2_SDA0 */
-GPIO(USBC_TCPC_I2C_CLK_P1, PIN(9, 0), GPIO_INPUT) /* I2C1_SCL0 */
-GPIO(USBC_TCPC_I2C_DATA_P1, PIN(8, 7), GPIO_INPUT) /* I2C1_SCL0 */
-GPIO(USBC_TCPC_I2C_CLK_P3, PIN(D, 1), GPIO_INPUT) /* I2C3_SCL0 */
-GPIO(USBC_TCPC_I2C_DATA_P3, PIN(D, 0), GPIO_INPUT) /* I2C3_SCL0 */
-
-/* Unused pins */
-GPIO(SML1_CLK_MECC, PIN(3, 3), GPIO_INPUT)
-GPIO(SML1_DATA_MECC, PIN(3, 6), GPIO_INPUT)
-GPIO(SMB_PCH_CLK, PIN(C, 2), GPIO_INPUT)
-GPIO(SMB_PCH_DATA, PIN(C, 1), GPIO_INPUT)
-GPIO(I3C_0_SCL, PIN(E, 4), GPIO_INPUT)
-GPIO(I3C_0_SDA, PIN(E, 3), GPIO_INPUT)
-GPIO(CPU_CAT_ERR_MECC, PIN(3, 4), GPIO_INPUT)
-GPIO(TP29, PIN(5, 0), GPIO_INPUT)
-GPIO(TP28, PIN(5, 6), GPIO_INPUT)
-GPIO(ESPI_ALERT0_N, PIN(5, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(BATT_DISABLE_EC, PIN(6, 6), GPIO_INPUT)
-GPIO(TP33, PIN(7, 2), GPIO_INPUT)
-GPIO(TP26, PIN(7, 3), GPIO_INPUT)
-GPIO(SLP_S0_CS_N, PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PECI, PIN(8, 1), GPIO_INPUT)
-GPIO(CPU_C10_GATE_MECC, PIN(9, 6), GPIO_INPUT)
-GPIO(SMB_PCH_ALRT, PIN(A, 3), GPIO_INPUT)
-GPIO(SMC_SDOWN_MECC, PIN(B, 1), GPIO_INPUT)
-GPIO(STD_ADPT_CNTRL_GPIO, PIN(C, 3), GPIO_INPUT)
-GPIO(SML1_ALERT, PIN(C, 7), GPIO_INPUT)
-GPIO(SMC_ONOFF_N, PIN(D, 2), GPIO_INPUT) /* Power button interrupt without H1 */
-GPIO(SUSWARN, PIN(D, 5), GPIO_INPUT)
-GPIO(TP_GPIOD6_EC, PIN(D, 6), GPIO_INPUT)
-GPIO(TP_GPIOD7_EC, PIN(D, 7), GPIO_INPUT)
-GPIO(ME_G3_TO_M3_EC, PIN(E, 0), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(8, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3) | BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP)
-
-/* Alternate pins for ADC */
-/* VR_TMP/V_1P05 - GPIO44, SKIN_THERM_IN_EC - GPIO43, AMBIENT_TEMP - GPIO42, DDR_TEMP/EC_5V - GPIO41 */
-ALTERNATE(PIN_MASK(4, BIT(1) | BIT(2) | BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)
-
-/* Alternate pins for FAN */
-ALTERNATE(PIN_MASK(8, BIT(0)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE) /* CPU_FAN_MECC GPIO80/PWM3_LED3 */
-/* GPIOA6 (Rework: CPU_TACHO_FAN is swapped with PM_RSMRST_N) */
-ALTERNATE(PIN_MASK(A, BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0xFF), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_02-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x0C), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14-15 */
diff --git a/board/adlrvpp_npcx/vif_override.xml b/board/adlrvpp_npcx/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/adlrvpp_npcx/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
- Definition from the USB-IF.
--->
View Lorry Controller Status