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-rw-r--r--board/chocodile_vpdmcu/board.c44
-rw-r--r--board/chocodile_vpdmcu/board.h44
-rw-r--r--board/chocodile_vpdmcu/build.mk2
-rw-r--r--board/chocodile_vpdmcu/chocodile.html2
-rw-r--r--board/chocodile_vpdmcu/ec.tasklist2
-rw-r--r--board/chocodile_vpdmcu/gpio.inc2
-rw-r--r--board/chocodile_vpdmcu/usb_pd_config.h29
-rw-r--r--board/chocodile_vpdmcu/vpd_api.c108
-rw-r--r--board/chocodile_vpdmcu/vpd_api.h26
9 files changed, 135 insertions, 124 deletions
diff --git a/board/chocodile_vpdmcu/board.c b/board/chocodile_vpdmcu/board.c
index b3e49fc547..a64da1633e 100644
--- a/board/chocodile_vpdmcu/board.c
+++ b/board/chocodile_vpdmcu/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -20,7 +20,7 @@
#include "util.h"
#include "vpd_api.h"
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
void board_config_pre_init(void)
{
@@ -40,26 +40,26 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
/* ADC channels */
const struct adc_t adc_channels[] = {
/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
- [ADC_VCONN_VSENSE] = {
- "VCONN_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_VCONN_VSENSE)},
- [ADC_CC_VPDMCU] = {
- "CC_VPDMCU", 3000, 4096, 0, STM32_AIN(ADC_CC_VPDMCU)},
- [ADC_CC_RP3A0_RD_L] = {
- "CC_RP3A0_RD_L", 3000, 4096, 0, STM32_AIN(ADC_CC_RP3A0_RD_L)},
- [ADC_RDCONNECT_REF] = {
- "RDCONNECT_REF", 3000, 4096, 0, STM32_AIN(ADC_RDCONNECT_REF)},
- [ADC_CC1_RP3A0_RD_L] = {
- "CC1_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RP3A0_RD_L)},
- [ADC_CC2_RP3A0_RD_L] = {
- "CC2_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RP3A0_RD_L)},
- [ADC_HOST_VBUS_VSENSE] = {
- "HOST_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_HOST_VBUS_VSENSE)},
- [ADC_CHARGE_VBUS_VSENSE] = {
- "CHARGE_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_CHARGE_VBUS_VSENSE)},
- [ADC_CC1_RPUSB_ODH] = {
- "CC1_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RPUSB_ODH)},
- [ADC_CC2_RPUSB_ODH] = {
- "CC2_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RPUSB_ODH)},
+ [ADC_VCONN_VSENSE] = { "VCONN_VSENSE", 3000, 4096, 0,
+ STM32_AIN(ADC_VCONN_VSENSE) },
+ [ADC_CC_VPDMCU] = { "CC_VPDMCU", 3000, 4096, 0,
+ STM32_AIN(ADC_CC_VPDMCU) },
+ [ADC_CC_RP3A0_RD_L] = { "CC_RP3A0_RD_L", 3000, 4096, 0,
+ STM32_AIN(ADC_CC_RP3A0_RD_L) },
+ [ADC_RDCONNECT_REF] = { "RDCONNECT_REF", 3000, 4096, 0,
+ STM32_AIN(ADC_RDCONNECT_REF) },
+ [ADC_CC1_RP3A0_RD_L] = { "CC1_RP1A5_ODH", 3000, 4096, 0,
+ STM32_AIN(ADC_CC1_RP3A0_RD_L) },
+ [ADC_CC2_RP3A0_RD_L] = { "CC2_RP1A5_ODH", 3000, 4096, 0,
+ STM32_AIN(ADC_CC2_RP3A0_RD_L) },
+ [ADC_HOST_VBUS_VSENSE] = { "HOST_VBUS_VSENSE", 3000, 4096, 0,
+ STM32_AIN(ADC_HOST_VBUS_VSENSE) },
+ [ADC_CHARGE_VBUS_VSENSE] = { "CHARGE_VBUS_VSENSE", 3000, 4096, 0,
+ STM32_AIN(ADC_CHARGE_VBUS_VSENSE) },
+ [ADC_CC1_RPUSB_ODH] = { "CC1_RPUSB_ODH", 3000, 4096, 0,
+ STM32_AIN(ADC_CC1_RPUSB_ODH) },
+ [ADC_CC2_RPUSB_ODH] = { "CC2_RPUSB_ODH", 3000, 4096, 0,
+ STM32_AIN(ADC_CC2_RPUSB_ODH) },
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
diff --git a/board/chocodile_vpdmcu/board.h b/board/chocodile_vpdmcu/board.h
index 552f00aa09..ede07dd9a0 100644
--- a/board/chocodile_vpdmcu/board.h
+++ b/board/chocodile_vpdmcu/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -34,7 +34,7 @@
#define CPU_CLOCK 48000000
/* the UART console is on USART1 (PA9/PA10) */
-#undef CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
#define CONFIG_UART_CONSOLE 1
/* Optional features */
@@ -43,23 +43,23 @@
#undef CONFIG_CMD_PD
#undef CONFIG_USBC_VCONN
#define CONFIG_ADC
-#undef CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_41_5_CY
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_COMMON_GPIO_SHORTNAMES
-#undef CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_ASSERT
#define CONFIG_FORCE_CONSOLE_RESUME
#define CONFIG_HIBERNATE
-#undef CONFIG_HOSTCMD_EVENTS
+#undef CONFIG_HOSTCMD_EVENTS
#define CONFIG_HW_CRC
-#undef CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_LTO
#define CONFIG_STM_HWTIMER32
-#undef CONFIG_TASK_PROFILING
-#undef CONFIG_UART_TX_BUF_SIZE
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
+#undef CONFIG_TASK_PROFILING
+#undef CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_DMA
+#undef CONFIG_UART_RX_DMA
#define CONFIG_UART_TX_BUF_SIZE 128
#define CONFIG_USB_PD_PORT_MAX_COUNT 1
#define CONFIG_USB_PD_TCPC
@@ -74,7 +74,7 @@
#define CONFIG_USB_PD_INTERNAL_COMP
#define CONFIG_VBOOT_HASH
#define CONFIG_WATCHDOG
-#undef CONFIG_WATCHDOG_HELP
+#undef CONFIG_WATCHDOG_HELP
#define CONFIG_USB_PID 0x5036
#define VPD_HW_VERSION 0x0001
@@ -92,10 +92,10 @@
/* GND impedance in milliohms */
#define VPD_GND_IMPEDANCE 33
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW 45000
-#define PD_MAX_CURRENT_MA 3000
-#define PD_MAX_VOLTAGE_MV 20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
/*
* TODO(crosbug.com/p/50519): Remove CONFIG_SYSTEM_UNLOCKED prior to building
* MP FW.
@@ -103,19 +103,19 @@
#define CONFIG_SYSTEM_UNLOCKED
#ifdef HAS_TASK_CONSOLE
-#undef CONFIG_CONSOLE_HISTORY
+#undef CONFIG_CONSOLE_HISTORY
#define CONFIG_CONSOLE_HISTORY 2
#else
-#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_CMDHELP
#define CONFIG_DEBUG_PRINTF
#define UARTN CONFIG_UART_CONSOLE
#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
#endif /* HAS_TASK_CONSOLE */
/* Use PSTATE embedded in the RO image, not in its own erase block */
-#undef CONFIG_FLASH_PSTATE_BANK
-#undef CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FLASH_PSTATE_BANK
+#undef CONFIG_FW_PSTATE_SIZE
#define CONFIG_FW_PSTATE_SIZE 0
/* Include math_util for bitmask_uint64 used in pd_timers */
@@ -125,7 +125,7 @@
/* Timer selection */
#define TIM_CLOCK32 2
-#define TIM_ADC 3
+#define TIM_ADC 3
#include "gpio_signal.h"
@@ -146,8 +146,8 @@ enum adc_channel {
};
/* 1.5A Rp */
-#define PD_SRC_VNC PD_SRC_1_5_VNC_MV
-#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_1_5_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV
#endif /* !__ASSEMBLER__ */
diff --git a/board/chocodile_vpdmcu/build.mk b/board/chocodile_vpdmcu/build.mk
index d4e5f58962..21c257bd7e 100644
--- a/board/chocodile_vpdmcu/build.mk
+++ b/board/chocodile_vpdmcu/build.mk
@@ -1,5 +1,5 @@
# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
diff --git a/board/chocodile_vpdmcu/chocodile.html b/board/chocodile_vpdmcu/chocodile.html
index b38edf94ec..6aec670f2a 100644
--- a/board/chocodile_vpdmcu/chocodile.html
+++ b/board/chocodile_vpdmcu/chocodile.html
@@ -866,7 +866,7 @@ th.expander input {
<text stroke="none" x="4750" y="-25" font-size="40" text-anchor="middle">10</text>
<text stroke="none" x="250" y="-25" font-size="40" text-anchor="middle">1</text>
<text stroke="none" x="38" y="-250" font-size="40" text-anchor="middle">A</text>
-<text stroke="none" x="99" y="-97" font-size="24">FOLLOWING NOTICE SHALL APPLY: &nbsp;COPYRIGHT C 2009 GOOGLE, INC. &nbsp;ALL RIGHTS RESERVED.</text>
+<text stroke="none" x="99" y="-97" font-size="24">FOLLOWING NOTICE SHALL APPLY: &nbsp;COPYRIGHT 2009 GOOGLE LLC</text>
<text stroke="none" x="38" y="-3750" font-size="40" text-anchor="middle">H</text>
<text stroke="none" x="5750" y="-25" font-size="40" text-anchor="middle">12</text>
<text stroke="none" x="92" y="-200" font-size="24">THESE MATERIALS (INCLUDING ALL TEXT, SOFTWARE,CODE, DISPLAYS, ARTWORK, AND IMAGES) CONTAIN TRADE SECRETS AND CONFIDENTIAL INFORMATION WHICH ARE PROPRIETARY TO GOOGLE, INC. &nbsp;ANY USE, REPRODUCTION, DISTRIBUTION,</text>
diff --git a/board/chocodile_vpdmcu/ec.tasklist b/board/chocodile_vpdmcu/ec.tasklist
index 6753502b92..ecbd3b052c 100644
--- a/board/chocodile_vpdmcu/ec.tasklist
+++ b/board/chocodile_vpdmcu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
diff --git a/board/chocodile_vpdmcu/gpio.inc b/board/chocodile_vpdmcu/gpio.inc
index a34c617ef1..060054f719 100644
--- a/board/chocodile_vpdmcu/gpio.inc
+++ b/board/chocodile_vpdmcu/gpio.inc
@@ -1,6 +1,6 @@
/* -*- mode:c -*-
*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
diff --git a/board/chocodile_vpdmcu/usb_pd_config.h b/board/chocodile_vpdmcu/usb_pd_config.h
index 048bbf3988..7fe608eb2a 100644
--- a/board/chocodile_vpdmcu/usb_pd_config.h
+++ b/board/chocodile_vpdmcu/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -55,7 +55,7 @@ static inline void spi_enable_clock(int port)
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS 1
+#define TIM_CCR_CS 1
/* EXTI line 21 is connected to the CMP1 output */
#define EXTI_COMP1_MASK (1 << 21)
@@ -95,13 +95,15 @@ static inline void pd_tx_spi_reset(int port)
static inline void pd_tx_enable(int port, int polarity)
{
/* USB_CC_TX_DATA: PB4 is SPI1 MISO */
- STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
- & ~(3 << (2*4))) /* PB4 disable ADC */
- | (2 << (2*4)); /* Set as SPI1_MISO */
+ STM32_GPIO_MODER(GPIO_B) =
+ (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) /* PB4 disable ADC
+ */
+ | (2 << (2 * 4)); /* Set as SPI1_MISO */
/* MCU ADC PA1 pin output low */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- & ~(3 << (2*1))) /* PA1 disable ADC */
- | (1 << (2*1)); /* Set as GPO */
+ STM32_GPIO_MODER(GPIO_A) =
+ (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 1))) /* PA1 disable ADC
+ */
+ | (1 << (2 * 1)); /* Set as GPO */
gpio_set_level(GPIO_CC_VPDMCU, 0);
}
@@ -109,11 +111,10 @@ static inline void pd_tx_enable(int port, int polarity)
static inline void pd_tx_disable(int port, int polarity)
{
/* Set CC_TX_DATA to Hi-Z, PB4 is SPI1 MISO */
- STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
- & ~(3 << (2*4)));
+ STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4)));
/* set ADC PA1 pin to ADC function (Hi-Z) */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- | (3 << (2*1))); /* PA1 as ADC */
+ STM32_GPIO_MODER(GPIO_A) =
+ (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 1))); /* PA1 as ADC */
}
/* we know the plug polarity, do the right configuration */
@@ -123,8 +124,8 @@ static inline void pd_select_polarity(int port, int polarity)
* use the right comparator : CC1 -> PA1 (COMP1 INP)
* use VrefInt / 2 as INM (about 600mV)
*/
- STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
- | STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+ STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+ STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
}
/* Initialize pins used for TX and put them in Hi-Z */
diff --git a/board/chocodile_vpdmcu/vpd_api.c b/board/chocodile_vpdmcu/vpd_api.c
index cdd2d9776d..fdfdf47efc 100644
--- a/board/chocodile_vpdmcu/vpd_api.c
+++ b/board/chocodile_vpdmcu/vpd_api.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -35,7 +35,7 @@
#endif
#undef CC_RA
-#define CC_RA(cc, sel) (cc < pd_src_rd_threshold[sel])
+#define CC_RA(cc, sel) (cc < pd_src_rd_threshold[sel])
#undef CC_RD
#define CC_RD(cc, sel) ((cc >= pd_src_rd_threshold[sel]) && (cc < PD_SRC_VNC))
@@ -47,16 +47,16 @@
#define VBUS_DETECT_THRESHOLD 2500 /* mV */
#define VCONN_DETECT_THRESHOLD 2500 /* mV */
-#define SCALE(vmeas, sfactor) (((vmeas) * 1000) / (sfactor))
+#define SCALE(vmeas, sfactor) (((vmeas)*1000) / (sfactor))
/*
* Type C power source charge current limits are identified by their cc
* voltage (set by selecting the proper Rd resistor). Any voltage below
* TYPE_C_SRC_500_THRESHOLD will not be identified as a type C charger.
*/
-#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */
-#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */
+#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */
+#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */
+#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */
/* Charge-Through pull up/down enabled */
static int ct_cc_pull;
@@ -86,7 +86,7 @@ static int vpd_cc_voltage_to_status(int cc_volt, int cc_pull)
return TYPEC_CC_VOLT_RA;
else
return TYPEC_CC_VOLT_OPEN;
- /* If we have a pull-down, then we are sink, check for Rp. */
+ /* If we have a pull-down, then we are sink, check for Rp. */
} else if (cc_pull == TYPEC_CC_RD || cc_pull == TYPEC_CC_RA_RD) {
if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD)
return TYPEC_CC_VOLT_RP_3_0;
@@ -218,8 +218,8 @@ void vpd_host_set_pull(int pull, int rp_value)
void vpd_host_get_cc(int *cc)
{
- *cc = vpd_cc_voltage_to_status(
- adc_read_channel(ADC_CC_VPDMCU), host_cc_pull);
+ *cc = vpd_cc_voltage_to_status(adc_read_channel(ADC_CC_VPDMCU),
+ host_cc_pull);
}
void vpd_rx_enable(int en)
@@ -237,17 +237,23 @@ void vpd_config_cc_rp3a0_rd_l(enum vpd_pin cfg, int en)
gpio_set_level(GPIO_CC_RP3A0_RD_L, en ? 1 : 0);
/* Disable Analog mode and Enable GPO */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- & ~(3 << (2*2))) /* PA2 disable ADC */
- | (1 << (2*2)); /* Set as GPO */
+ STM32_GPIO_MODER(GPIO_A) =
+ (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 2))) /* PA2
+ disable
+ ADC */
+ | (1 << (2 * 2)); /* Set as GPO */
} else {
/* Set PA2 pin to ANALOG function */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- | (3 << (2*2))); /* PA2 in ANALOG mode */
+ STM32_GPIO_MODER(GPIO_A) =
+ (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 2))); /* PA2 in
+ ANALOG
+ mode */
/* Set PA3 pin to ANALOG function */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- | (3 << (2*3))); /* PA3 in ANALOG mode */
+ STM32_GPIO_MODER(GPIO_A) =
+ (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 3))); /* PA3 in
+ ANALOG
+ mode */
/* Disable Window Mode. Select PA3 */
STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
@@ -276,9 +282,11 @@ void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en)
gpio_set_level(GPIO_CC1_RP3A0_RD_L, en ? 1 : 0);
/* Disable Analog mode and Enable GPO */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- & ~(3 << (2*4))) /* PA4 disable ADC */
- | (1 << (2*4)); /* Set as GPO */
+ STM32_GPIO_MODER(GPIO_A) =
+ (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 4))) /* PA4
+ disable
+ ADC */
+ | (1 << (2 * 4)); /* Set as GPO */
}
if (cfg == PIN_ADC || cfg == PIN_CMP) {
@@ -286,13 +294,17 @@ void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en)
STM32_COMP_CSR &= ~STM32_COMP_CMP2EN;
/* Set PA4 pin to Analog mode */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- | (3 << (2*4))); /* PA4 in ANALOG mode */
+ STM32_GPIO_MODER(GPIO_A) =
+ (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 4))); /* PA4 in
+ ANALOG
+ mode */
if (cfg == PIN_CMP) {
/* Set PA3 pin to ANALOG function */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- | (3 << (2*3))); /* PA3 in ANALOG mode */
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) |
+ (3 << (2 * 3))); /* PA3 in
+ ANALOG
+ mode */
/* Disable Window Mode. Select PA3*/
STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
@@ -319,9 +331,11 @@ void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en)
gpio_set_level(GPIO_CC2_RP3A0_RD_L, en ? 1 : 0);
/* Disable Analog mode and Enable GPO */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- & ~(3 << (2*5))) /* PA5 disable ADC */
- | (1 << (2*5)); /* Set as GPO */
+ STM32_GPIO_MODER(GPIO_A) =
+ (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 5))) /* PA5
+ disable
+ ADC */
+ | (1 << (2 * 5)); /* Set as GPO */
}
if (cfg == PIN_ADC || cfg == PIN_CMP) {
@@ -329,13 +343,17 @@ void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en)
STM32_COMP_CSR &= ~STM32_COMP_CMP2EN;
/* Set PA5 pin to ANALOG function */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- | (3 << (2*5))); /* PA5 in ANALOG mode */
+ STM32_GPIO_MODER(GPIO_A) =
+ (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 5))); /* PA5 in
+ ANALOG
+ mode */
if (cfg == PIN_CMP) {
/* Set PA3 pin to ANALOG function */
- STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
- | (3 << (2*3))); /* PA3 in ANALOG mode */
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) |
+ (3 << (2 * 3))); /* PA3 in
+ ANALOG
+ mode */
/* Disable Window Mode. */
STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
@@ -362,13 +380,17 @@ void vpd_config_cc1_rpusb_odh(enum vpd_pin cfg, int en)
gpio_set_level(GPIO_CC1_RPUSB_ODH, en ? 1 : 0);
/* Disable Analog mode and Enable GPO */
- STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
- & ~(3 << (2*0))) /* PB0 disable ADC */
- | (1 << (2*0)); /* Set as GPO */
+ STM32_GPIO_MODER(GPIO_B) =
+ (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 0))) /* PB0
+ disable
+ ADC */
+ | (1 << (2 * 0)); /* Set as GPO */
} else {
/* Enable Analog mode */
- STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
- | (3 << (2*0))); /* PB0 in ANALOG mode */
+ STM32_GPIO_MODER(GPIO_B) =
+ (STM32_GPIO_MODER(GPIO_B) | (3 << (2 * 0))); /* PB0 in
+ ANALOG
+ mode */
}
}
@@ -382,13 +404,17 @@ void vpd_config_cc2_rpusb_odh(enum vpd_pin cfg, int en)
gpio_set_level(GPIO_CC2_RPUSB_ODH, en ? 1 : 0);
/* Disable Analog mode and Enable GPO */
- STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
- & ~(3 << (2*1))) /* PB1 disable ADC */
- | (1 << (2*1)); /* Set as GPO */
+ STM32_GPIO_MODER(GPIO_B) =
+ (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 1))) /* PB1
+ disable
+ ADC */
+ | (1 << (2 * 1)); /* Set as GPO */
} else {
/* Enable Analog mode */
- STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
- | (3 << (2*1))); /* PB1 in ANALOG mode */
+ STM32_GPIO_MODER(GPIO_B) =
+ (STM32_GPIO_MODER(GPIO_B) | (3 << (2 * 1))); /* PB1 in
+ ANALOG
+ mode */
}
}
@@ -405,7 +431,7 @@ inline int vpd_read_host_vbus(void)
inline int vpd_read_ct_vbus(void)
{
return SCALE(adc_read_channel(ADC_CHARGE_VBUS_VSENSE),
- VBUS_SCALE_FACTOR);
+ VBUS_SCALE_FACTOR);
}
inline int vpd_read_vconn(void)
diff --git a/board/chocodile_vpdmcu/vpd_api.h b/board/chocodile_vpdmcu/vpd_api.h
index df50f92006..5d2fd24afb 100644
--- a/board/chocodile_vpdmcu/vpd_api.h
+++ b/board/chocodile_vpdmcu/vpd_api.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -12,34 +12,18 @@
#include "gpio.h"
#include "usb_pd.h"
-enum vpd_pin {
- PIN_ADC,
- PIN_CMP,
- PIN_GPO
-};
+enum vpd_pin { PIN_ADC, PIN_CMP, PIN_GPO };
-enum vpd_gpo {
- GPO_HZ,
- GPO_HIGH,
- GPO_LOW
-};
+enum vpd_gpo { GPO_HZ, GPO_HIGH, GPO_LOW };
enum vpd_pwr {
PWR_VCONN,
PWR_VBUS,
};
-enum vpd_cc {
- CT_OPEN,
- CT_CC1,
- CT_CC2
-};
+enum vpd_cc { CT_OPEN, CT_CC1, CT_CC2 };
-enum vpd_billboard {
- BB_NONE,
- BB_SRC,
- BB_SNK
-};
+enum vpd_billboard { BB_NONE, BB_SRC, BB_SNK };
/**
* Set Charge-Through Rp or Rd on CC lines
View Lorry Controller Status