diff options
Diffstat (limited to 'board/genesis/pse.c')
| -rw-r--r-- | board/genesis/pse.c | 85 |
1 files changed, 42 insertions, 43 deletions
diff --git a/board/genesis/pse.c b/board/genesis/pse.c index 671288ccf5..bda7e1994d 100644 --- a/board/genesis/pse.c +++ b/board/genesis/pse.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,44 +18,44 @@ #include "timer.h" #include "util.h" -#define LTC4291_I2C_ADDR 0x2C - -#define LTC4291_REG_SUPEVN_COR 0x0B -#define LTC4291_REG_STATPWR 0x10 -#define LTC4291_REG_STATPIN 0x11 -#define LTC4291_REG_OPMD 0x12 -#define LTC4291_REG_DISENA 0x13 -#define LTC4291_REG_DETENA 0x14 -#define LTC4291_REG_DETPB 0x18 -#define LTC4291_REG_PWRPB 0x19 -#define LTC4291_REG_RSTPB 0x1A -#define LTC4291_REG_ID 0x1B -#define LTC4291_REG_DEVID 0x43 -#define LTC4291_REG_HPMD1 0x46 -#define LTC4291_REG_HPMD2 0x4B -#define LTC4291_REG_HPMD3 0x50 -#define LTC4291_REG_HPMD4 0x55 -#define LTC4291_REG_LPWRPB 0x6E - -#define LTC4291_FLD_STATPIN_AUTO BIT(0) -#define LTC4291_FLD_RSTPB_RSTALL BIT(4) - -#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port)) -#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port)) -#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port)) -#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port)) - -#define LTC4291_OPMD_AUTO 0xFF -#define LTC4291_DISENA_ALL 0x0F -#define LTC4291_DETENA_ALL 0xFF -#define LTC4291_ID 0x64 -#define LTC4291_DEVID 0x38 -#define LTC4291_HPMD_MIN 0x00 -#define LTC4291_HPMD_MAX 0xA8 - -#define LTC4291_PORT_MAX 4 - -#define LTC4291_RESET_DELAY_US (20 * MSEC) +#define LTC4291_I2C_ADDR 0x2C + +#define LTC4291_REG_SUPEVN_COR 0x0B +#define LTC4291_REG_STATPWR 0x10 +#define LTC4291_REG_STATPIN 0x11 +#define LTC4291_REG_OPMD 0x12 +#define LTC4291_REG_DISENA 0x13 +#define LTC4291_REG_DETENA 0x14 +#define LTC4291_REG_DETPB 0x18 +#define LTC4291_REG_PWRPB 0x19 +#define LTC4291_REG_RSTPB 0x1A +#define LTC4291_REG_ID 0x1B +#define LTC4291_REG_DEVID 0x43 +#define LTC4291_REG_HPMD1 0x46 +#define LTC4291_REG_HPMD2 0x4B +#define LTC4291_REG_HPMD3 0x50 +#define LTC4291_REG_HPMD4 0x55 +#define LTC4291_REG_LPWRPB 0x6E + +#define LTC4291_FLD_STATPIN_AUTO BIT(0) +#define LTC4291_FLD_RSTPB_RSTALL BIT(4) + +#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port)) +#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port)) +#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port)) +#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port)) + +#define LTC4291_OPMD_AUTO 0xFF +#define LTC4291_DISENA_ALL 0x0F +#define LTC4291_DETENA_ALL 0xFF +#define LTC4291_ID 0x64 +#define LTC4291_DEVID 0x38 +#define LTC4291_HPMD_MIN 0x00 +#define LTC4291_HPMD_MAX 0xA8 + +#define LTC4291_PORT_MAX 4 + +#define LTC4291_RESET_DELAY_US (20 * MSEC) #define I2C_PSE_READ(reg, data) \ i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) @@ -63,7 +63,7 @@ #define I2C_PSE_WRITE(reg, data) \ i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static int pse_write_hpmd(int port, int val) { @@ -173,7 +173,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT); /* Also reset the PSE on a reboot to toggle the power. */ DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT); -static int command_pse(int argc, char **argv) +static int command_pse(int argc, const char **argv) { int port; @@ -205,8 +205,7 @@ static int command_pse(int argc, char **argv) else return EC_ERROR_PARAM2; } -DECLARE_CONSOLE_COMMAND(pse, command_pse, - "<port# 0-3> <off | on | min | max>", +DECLARE_CONSOLE_COMMAND(pse, command_pse, "<port# 0-3> <off | on | min | max>", "Set PSE port power"); static int ec_command_pse_status(int port, uint8_t *status) |