diff options
Diffstat (limited to 'board/hatch_fp')
| -rw-r--r-- | board/hatch_fp/OWNERS | 1 | ||||
| -rw-r--r-- | board/hatch_fp/board.c | 131 | ||||
| -rw-r--r-- | board/hatch_fp/board.h | 258 | ||||
| -rw-r--r-- | board/hatch_fp/board_rw.c | 60 | ||||
| -rw-r--r-- | board/hatch_fp/board_rw.h | 13 | ||||
| -rw-r--r-- | board/hatch_fp/build.mk | 53 | ||||
| -rw-r--r-- | board/hatch_fp/dev_key.pem | 39 | ||||
| -rw-r--r-- | board/hatch_fp/ec.tasklist | 14 | ||||
| -rw-r--r-- | board/hatch_fp/fpsensor_detect.c | 29 | ||||
| -rw-r--r-- | board/hatch_fp/fpsensor_detect_rw.c | 38 | ||||
| -rw-r--r-- | board/hatch_fp/gpio.inc | 45 | ||||
| -rw-r--r-- | board/hatch_fp/gpio_rw.inc | 28 |
12 files changed, 0 insertions, 709 deletions
diff --git a/board/hatch_fp/OWNERS b/board/hatch_fp/OWNERS deleted file mode 100644 index ba92c193e0..0000000000 --- a/board/hatch_fp/OWNERS +++ /dev/null @@ -1 +0,0 @@ -include ../../common/fpsensor/OWNERS diff --git a/board/hatch_fp/board.c b/board/hatch_fp/board.c deleted file mode 100644 index b48dce2b7e..0000000000 --- a/board/hatch_fp/board.c +++ /dev/null @@ -1,131 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "fpsensor_detect.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "spi.h" -#include "system.h" -#include "task.h" -#include "usart_host_command.h" - -/** - * Disable restricted commands when the system is locked. - * - * @see console.h system.c - */ -int console_is_restricted(void) -{ - return system_is_locked(); -} - -#include "gpio_list.h" - -/* - * Some platforms have a broken SLP_S0_L signal (stuck to 0 in S0) - * if set, ignore it and only uses SLP_S3_L for the AP state. - */ -static bool broken_slp; - -static void ap_deferred(void) -{ - /* - * Behavior: - * AP Active (ex. Intel S0): SLP_L is 1 - * AP Suspend (ex. Intel S0ix): SLP_L is 0 - * The alternative SLP_ALT_L should be pulled high at all the times. - * - * Legacy Intel behavior: - * in S3: SLP_ALT_L is 0 and SLP_L is X. - * in S0ix: SLP_ALT_L is 1 and SLP_L is 0. - * in S0: SLP_ALT_L is 1 and SLP_L is 1. - * in S5/G3, the FP MCU should not be running. - */ - int running = gpio_get_level(GPIO_SLP_ALT_L) && - (gpio_get_level(GPIO_SLP_L) || broken_slp); - - if (running) { /* S0 */ - disable_sleep(SLEEP_MASK_AP_RUN); - hook_notify(HOOK_CHIPSET_RESUME); - } else { /* S0ix/S3 */ - hook_notify(HOOK_CHIPSET_SUSPEND); - enable_sleep(SLEEP_MASK_AP_RUN); - } -} -DECLARE_DEFERRED(ap_deferred); - -/* PCH power state changes */ -void slp_event(enum gpio_signal signal) -{ - hook_call_deferred(&ap_deferred_data, 0); -} - -static void board_init_transport(void) -{ - enum fp_transport_type ret_transport = get_fp_transport_type(); - - ccprints("TRANSPORT_SEL: %s", fp_transport_type_to_str(ret_transport)); - - /* Initialize transport based on bootstrap */ - switch (ret_transport) { - case FP_TRANSPORT_TYPE_UART: - /* - * The Zork variants currently have a broken SLP_S0_L signal - * (stuck to 0 in S0). For now, unconditionally ignore it here - * as they are the only UART users and the AP has no S0ix state. - * TODO(b/174695987) once the RW AP firmware has been updated - * on all those machines, remove this workaround. - */ - broken_slp = true; - - /* Check if CONFIG_USART_HOST_COMMAND is enabled. */ - if (IS_ENABLED(CONFIG_USART_HOST_COMMAND)) - usart_host_command_init(); - else - ccprints("ERROR: UART not supported in fw build."); - - /* Disable SPI interrupt to disable SPI transport layer */ - gpio_disable_interrupt(GPIO_SPI1_NSS); - break; - - case FP_TRANSPORT_TYPE_SPI: - /* SPI transport is enabled. SPI1_NSS interrupt will process - * incoming request/ - */ - break; - default: - ccprints("ERROR: Selected transport is not valid."); - } - - ccprints("TRANSPORT_SEL: %s", - fp_transport_type_to_str(get_fp_transport_type())); -} - -/* Initialize board. */ -static void board_init(void) -{ - /* Run until the first S3 entry */ - disable_sleep(SLEEP_MASK_AP_RUN); - - board_init_transport(); - - /* Enable interrupt on PCH power signals */ - gpio_enable_interrupt(GPIO_SLP_ALT_L); - gpio_enable_interrupt(GPIO_SLP_L); - - if (IS_ENABLED(SECTION_IS_RW)) - board_init_rw(); - - /* - * Enable the SPI slave interface if the PCH is up. - * Do not use hook_call_deferred(), because ap_deferred() will be - * called after tasks with priority higher than HOOK task (very late). - */ - ap_deferred(); -} -DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/hatch_fp/board.h b/board/hatch_fp/board.h deleted file mode 100644 index aa097d8b7e..0000000000 --- a/board/hatch_fp/board.h +++ /dev/null @@ -1,258 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * STM32F412 + FPC 1025 Fingerprint MCU configuration - * - * Alternate names that share this same board file: - * hatch_fp - * bloonchipper - * dragonclaw - */ - -#ifndef __BOARD_H -#define __BOARD_H - -#undef CONFIG_SYSTEM_UNLOCKED - -/*-------------------------------------------------------------------------* - * Flash layout: - * - * +++++++++++++ - * | RO | - * | ......... | - * | Rollback | (two sectors) - * +-----------+ - * | RW | - * | | - * | | - * | | - * | | - * +++++++++++++ - * - * We adjust the following macros to accommodate a for a rollback, RO, - * and RW region of different sizes. - * - *-------------------------------------------------------------------------*/ - -#undef _IMAGE_SIZE -#undef CONFIG_ROLLBACK_OFF -#undef CONFIG_ROLLBACK_SIZE -#undef CONFIG_FLASH_PSTATE -#undef CONFIG_FW_PSTATE_SIZE -#undef CONFIG_FW_PSTATE_OFF -#undef CONFIG_SHAREDLIB_SIZE -#undef CONFIG_RO_MEM_OFF -#undef CONFIG_RO_STORAGE_OFF -#undef CONFIG_RO_SIZE -#undef CONFIG_RW_MEM_OFF -#undef CONFIG_RW_STORAGE_OFF -#undef CONFIG_RW_SIZE -#undef CONFIG_EC_PROTECTED_STORAGE_OFF -#undef CONFIG_EC_PROTECTED_STORAGE_SIZE -#undef CONFIG_EC_WRITABLE_STORAGE_OFF -#undef CONFIG_EC_WRITABLE_STORAGE_SIZE -#undef CONFIG_WP_STORAGE_OFF -#undef CONFIG_WP_STORAGE_SIZE - -#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300 - -#define CONFIG_SHAREDLIB_SIZE 0 - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) - -/* EC rollback protection block */ -#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) -#define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */ - -#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) - -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* - * We want to prevent flash readout, and use it as indicator of protection - * status. - */ -#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE - -/*-------------------------------------------------------------------------* - * USART Transport Setup - *-------------------------------------------------------------------------*/ -/* Enable USART host commands */ -#define CONFIG_USART_HOST_COMMAND -/* Enable USART and USART1 stream */ -#define CONFIG_STREAM_USART -#define CONFIG_STREAM_USART1 -/* Allocate and configure hw instance of USART */ -#undef CONFIG_UART_HOST_COMMAND_HW -#define CONFIG_UART_HOST_COMMAND_HW usart1_hw -/* Set baud rate of USART */ -#undef CONFIG_UART_HOST_COMMAND_BAUD_RATE -#define CONFIG_UART_HOST_COMMAND_BAUD_RATE 3000000 - -/*-------------------------------------------------------------------------* - * UART Console Setup - *-------------------------------------------------------------------------*/ - -/* The UART console is on USART2 */ -#undef CONFIG_UART_CONSOLE -#define CONFIG_UART_CONSOLE 2 -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 -/* We don't currently use DMA. */ -#undef CONFIG_UART_TX_DMA_PH -#undef CONFIG_UART_TX_DMA -#undef CONFIG_UART_RX_DMA -#undef CONFIG_UART_TX_REQ_CH -#undef CONFIG_UART_RX_REQ_CH - -/*-------------------------------------------------------------------------* - * Console Commands - *-------------------------------------------------------------------------*/ - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IDLE_STATS - -#ifdef SECTION_IS_RW -#define CONFIG_CMD_SPI_XFER -/* TODO(b/130249462): remove for release */ -#define CONFIG_CMD_FPSENSOR_DEBUG -#endif - -/* - * These allow console commands to be flagged as restricted. - * Restricted commands will only be permitted to run when - * console_is_restricted() returns false. - * See console_is_restricted's definition in board.c. - */ -#define CONFIG_CONSOLE_COMMAND_FLAGS -#define CONFIG_RESTRICTED_CONSOLE_COMMANDS - -/*-------------------------------------------------------------------------* - * Rollback Block - *-------------------------------------------------------------------------*/ - -#define CONFIG_ROLLBACK -#define CONFIG_ROLLBACK_SECRET_SIZE 32 -#define CONFIG_MPU -#define CONFIG_ROLLBACK_MPU_PROTECT - -/* - * We do not use any "locally" generated entropy: this is normally used - * to add local entropy when the main source of entropy is remote. - */ -#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE -#ifdef SECTION_IS_RW -#undef CONFIG_ROLLBACK_UPDATE -#endif - -/*-------------------------------------------------------------------------* - * RW Signature Verification - *-------------------------------------------------------------------------*/ - -#ifdef SECTION_IS_RO -/* RO verifies the RW partition signature */ -#define CONFIG_RSA -#define CONFIG_RWSIG -#endif /* SECTION_IS_RO */ -#define CONFIG_RSA_KEY_SIZE 3072 -#define CONFIG_RSA_EXPONENT_3 -#define CONFIG_RWSIG_TYPE_RWSIG - -/*-------------------------------------------------------------------------* - * Watchdog - *-------------------------------------------------------------------------*/ - -/* - * RW does slow compute, RO does slow flash erase. - */ -#undef CONFIG_WATCHDOG_PERIOD_MS -#define CONFIG_WATCHDOG_PERIOD_MS 10000 -#define CONFIG_WATCHDOG_HELP - -/*-------------------------------------------------------------------------* - * Fingerprint Specific - *-------------------------------------------------------------------------*/ - -/* SPI configuration for the fingerprint sensor */ -#define CONFIG_SPI_CONTROLLER -#define CONFIG_SPI_FP_PORT 0 /* SPI2: first master config */ -#define CONFIG_FINGERPRINT_MCU -#ifdef SECTION_IS_RW -#define CONFIG_FP_SENSOR_FPC1025 -/* - * Use the malloc code only in the RW section (for the private library), - * we cannot enable it in RO since it is not compatible with the RW verification - * (shared_mem_init done too late). - */ -#define CONFIG_MALLOC -/* - * FP buffers are allocated in regular SRAM on STM32F4. - * TODO(b/124773209): Instead of defining to empty, #undef once all CLs that - * depend on FP_*_SECTION have landed. Also rename the variables to CONFIG_*. - */ -#define FP_FRAME_SECTION -#define FP_TEMPLATE_SECTION -#endif /* SECTION_IS_RW */ - -/*-------------------------------------------------------------------------* - * Disable Features - *-------------------------------------------------------------------------*/ - -#undef CONFIG_ADC -#undef CONFIG_HIBERNATE -#undef CONFIG_I2C -#undef CONFIG_LID_SWITCH -#undef CONFIG_TASK_PROFILING - -/*-------------------------------------------------------------------------* - * Other - *-------------------------------------------------------------------------*/ - -#define CONFIG_AES -#define CONFIG_AES_GCM -#define CONFIG_DMA -#define CONFIG_FPU -#define CONFIG_HOST_COMMAND_STATUS -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO -#define CONFIG_PRINTF_LEGACY_LI_FORMAT -#define CONFIG_RNG -#define CONFIG_SHA256 -#define CONFIG_SHA256_UNROLLED -#define CONFIG_SPI -#define CONFIG_STM_HWTIMER32 -#define CONFIG_WP_ACTIVE_HIGH -#define CONFIG_PANIC_STRIP_GPR - -#ifdef SECTION_IS_RW -#define CONFIG_LOW_POWER_IDLE -#endif /* SECTION_IS_RW */ - -#ifndef __ASSEMBLER__ - -/* Timer selection */ -#define TIM_CLOCK32 2 -#define TIM_WATCHDOG 9 - -#include "gpio_signal.h" -#include "board_rw.h" - -void slp_event(enum gpio_signal signal); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __BOARD_H */ diff --git a/board/hatch_fp/board_rw.c b/board/hatch_fp/board_rw.c deleted file mode 100644 index 4c83c8723c..0000000000 --- a/board/hatch_fp/board_rw.c +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "fpsensor_detect.h" -#include "gpio.h" -#include "registers.h" -#include "spi.h" -#include "task.h" -#include "usart_host_command.h" -#include "util.h" - -#ifndef SECTION_IS_RW -#error "This file should only be built for RW." -#endif - -/* SPI devices */ -struct spi_device_t spi_devices[] = { - /* Fingerprint sensor (SCLK at 4Mhz) */ - { .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI2_NSS } -}; -const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); - -static void configure_fp_sensor_spi(void) -{ - /* The dragonclaw development board needs this enabled to enable the - * AND gate (U10) to CS. Production boards could disable this to save - * power since it's only needed for initial detection on those boards. - */ - gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1); - - /* Configure SPI GPIOs */ - gpio_config_module(MODULE_SPI_CONTROLLER, 1); - - /* Set all SPI master signal pins to very high speed: B12/13/14/15 */ - STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000; - - /* Enable clocks to SPI2 module (master) */ - STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; - - spi_enable(&spi_devices[0], 1); -} - -void board_init_rw(void) -{ - /* - * FP_RST_ODL pin is defined in gpio_rw.inc (with GPIO_OUT_HIGH - * flag) but not in gpio.inc, so RO leaves this pin set to 0 (reset - * default), but RW doesn't initialize this pin to 1 because sysjump - * to RW is a warm reset (see gpio_pre_init() in chip/stm32/gpio.c). - * Explicitly reset FP_RST_ODL pin to default value. - */ - gpio_reset(GPIO_FP_RST_ODL); - - /* Configure and enable SPI as master for FP sensor */ - configure_fp_sensor_spi(); -} diff --git a/board/hatch_fp/board_rw.h b/board/hatch_fp/board_rw.h deleted file mode 100644 index 1bee6c947d..0000000000 --- a/board/hatch_fp/board_rw.h +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H -#define __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H - -void fps_event(enum gpio_signal signal); - -void board_init_rw(void); - -#endif /* __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H */ diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk deleted file mode 100644 index bb7f738704..0000000000 --- a/board/hatch_fp/build.mk +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright 2019 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Board specific files build - -# the IC is STmicro STM32F412 -CHIP:=stm32 -CHIP_FAMILY:=stm32f4 -CHIP_VARIANT:=stm32f412 - -# Don't forget that the board build.mk is included more than once to allow -# conditional variables to be realized. This means that we need to redefine all -# variable or the "+=" lines will compound. -board-rw=board_rw.o -board-y=board.o - -# If we're mocking the sensor detection for testing (so we can test -# sensor/transport permutations in the unit tests), don't build the real sensor -# detection. -ifeq ($(HAS_MOCK_FPSENSOR_DETECT),) - board-y+=fpsensor_detect.o - board-rw+=fpsensor_detect_rw.o -endif - -# Do not build rsa test because this board uses RSA exponent 3 and the rsa test -# will fail on device. -test-list-y=\ - aes \ - cec \ - compile_time_macros \ - crc \ - flash_physical \ - flash_write_protect \ - fpsensor \ - fpsensor_hw \ - mpu \ - mutex \ - pingpong \ - printf \ - queue \ - rollback \ - rollback_entropy \ - rsa3 \ - rtc \ - scratchpad \ - sha256 \ - sha256_unrolled \ - static_if \ - stm32f_rtc \ - timer_dos \ - utils \ - utils_str \ diff --git a/board/hatch_fp/dev_key.pem b/board/hatch_fp/dev_key.pem deleted file mode 100644 index e3273cbccf..0000000000 --- a/board/hatch_fp/dev_key.pem +++ /dev/null @@ -1,39 +0,0 @@ ------BEGIN RSA PRIVATE KEY----- -MIIG4wIBAAKCAYEAwVaB9PsLDGaHIMGp+uouwQvQGhNbIifTTX40aO7Sh00Pw9va -tqggEe7AyeEKQLy7uxCfwLFkUABCmEIusLpsp7iGvAXz3R1N80pyszNGhsqV2UQH -WW/M5L/3nPNjqjffje0ZMwoCNeE4YBqn+puiKEBEZXnnZsPV/f5lOn6v4GP7wzkF -lTEq9InLhoWEKjuyL6gwfVZiEvNs52umzjSx/OaY9ux1SrnR6768xQdCRpah/RDC -DAdL1v7lnzagBXq1p5WFFkAsIQhgSk7FhC0MX3BPqGE2c68t/g5AkyT1M7SZk4+5 -sY6oor7vVmfzUsShJOP1xb/Gv91cgRMOIU4y6mnQcf7YO68ex9YpnTnL2JGpZj/j -MHzocI9l9a6R0PX17UOvXfVg2tQg+mU+zLqCG2xMe8R7+sA893/wgQdSXDiB5Nvh -Vbp+89WxrX2vQK5lIObCUlKNLABsdeAMiTBN9IXMLdK5EP3gbL+wKG+/82DgAwaz -l6hJZ2TLhV+BWdE3AgEDAoIBgQCA5FajUgddma9rK8anRsnWB+ARYjzBb+IzqXhF -9IxaM1/X5+ckcBVhSdXb61wrKH0nYGqAdkLgACxlgXR10Z3FJa8oA/fovjP3hvci -Ii8Ehw6Q2ATmSoiYf/pookJxepUJSLt3XAF5QNBAEcVRvRbFgC2Y+++Z1+P+qZjR -qcqVl/0s0K5jdhyjBoevA61xfSF1Gsr+OZa3TPNE8m80IyFTRGX58vjce+FH1H3Y -r4GEZGv+CywIBN05/0O/ecADpyKZ1m8PYrkpCwuNc+BK+BkEeEary61Y/IoQLVUx -ntb4Y2meciFj5yr7PtRLcuwllWjEU5IfKPl2bB96fxITC6ALZVI9ksC6YDfCBXuU -rWQNG1UFC6Ux//g1BdXhuPgl9MHS0nA37oJ8BxhdIgbQ1OxLlkY+VLwWN0IrC3vp -+MDTufSPh7sR7r4sMVTYcncyc4kE0pnXQw+LHg3lnwadwlFeKP2mJKAyeveMqTWd -GdB0eMuyv2cp77/nrESWYDUa9ysCgcEA/dwIdGjXmhz9T4zleZUTM9/D+uzW5kG0 -eB/br+ztzP/9YC+W0+DDlHVG2bdrsJsooZEyuzDaiGd/JiW9wPTjdjtSpCksJUEE -KImymQ2GFbs7If1ZCgcxFqdywjk8WVqxCcv/Bqhsa7lcIGOFiV9X8x067xpwNU3t -yw8IRXchfUK80BKFPf8quP4RoYy6o4rkos28+Q+zIPSZlBaZXKsSKPQElyN0SysN -UwGSpOJ4b9TOH88GZFLymKOY4DUhvSJXAoHBAML31grDPsla0aaUD5oj06TcIavC -24fyqm2qZRjJxPIffcW08MfTJJVraguEJWnJW1zVZ9vRdgXTriMutUPH32MWgnF5 -iv7dxvxEPaUoL68tbryxElt1wwpfMmDf4T6sIic8CANnMLUQIE5Orwobx7btqC8q -8aQfa+vfrlybD6Fe1j19w3zVNviNoMdFQdF2MvbdHpZeQrpevgla6T/hwb5USx14 -VHoaX8bATRfmjtTW4FcYknRttvM+y8OaD/Q8IQKBwQCpPVr4ReURaKjfs0OmY2Ii -lS1R8znu1nhQFT0f80kzVVOVdQ836y0No4SRJPJ1vMXBC3cndecFmlTEGSkrTez5 -fOHCxh1uK1gbBncQs665J3zBU5CxWiC5xPcsJig7kctb3VSvGvLye5LAQlkGP4/3 -aNH0vErOM/PctLAuT2uo1yiKtwN+qhx7VAvBCHxtB0MXM9NQtSIV+GZiubuTHLbF -+AMPbPgyHLOMq7cYlvr1OIlqigRC4fcQbRCVeMEowY8CgcEAgfqOsdd/MOc2bw1f -vBfibegWcoHnr/ccSRxDZdvYoWpT2SNLL+IYY5zxXQLDm9uSPeOakoukA+J0F3R4 -19qU7LmsS6ZcqekvUtgpGMV1H3OfKHYMPPkssZTMQJVA1HLBb31arO91zgrANDR0 -sWfaefPFdMdLwr+dR+p0Pby1Fj85flPXqI4kpbPAhNjWi6Qh+ei/DumB0ZR+sOdG -KpaBKY2HaPri/BGVLyreD+8J4znq5LsMTZ55938ygma1TX1rAoHASPiGXtnpXS5d -TH2LAGcvUyopOMgdEHbm9Xvkdet3rLrNPkJ+tuTsv7MwUprnoQQhCowbVwQ8IzS0 -MHSMcqBT68dJsq9Y3OB7tYHtSYDEcHEpbdIt1oRHO0tWo/XMC/qRvTSTiEqCv4LQ -x2buZlD4KfmQOHh24EwuZMB7MsyvdMvY56LWrJExx+Cb1VcItGme9pxf5Tir0ho/ -xzKyVSGh59GI0weB/PQl1queFbSYDWeKF6Ra74appkWF1cb9z8P4 ------END RSA PRIVATE KEY----- diff --git a/board/hatch_fp/ec.tasklist b/board/hatch_fp/ec.tasklist deleted file mode 100644 index ed1e6ed294..0000000000 --- a/board/hatch_fp/ec.tasklist +++ /dev/null @@ -1,14 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * See CONFIG_TASK_LIST in config.h for details. - */ -#define CONFIG_TASK_LIST \ - TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \ - TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \ - TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096) \ - TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 4096) \ - TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) diff --git a/board/hatch_fp/fpsensor_detect.c b/board/hatch_fp/fpsensor_detect.c deleted file mode 100644 index 638b5fbfe0..0000000000 --- a/board/hatch_fp/fpsensor_detect.c +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "fpsensor_detect.h" -#include "gpio.h" -#include "timer.h" - -enum fp_transport_type get_fp_transport_type(void) -{ - enum fp_transport_type ret; - - gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1); - usleep(1); - switch (gpio_get_level(GPIO_TRANSPORT_SEL)) { - case 0: - ret = FP_TRANSPORT_TYPE_UART; - break; - case 1: - ret = FP_TRANSPORT_TYPE_SPI; - break; - default: - ret = FP_TRANSPORT_TYPE_UNKNOWN; - break; - } - gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 0); - return ret; -} diff --git a/board/hatch_fp/fpsensor_detect_rw.c b/board/hatch_fp/fpsensor_detect_rw.c deleted file mode 100644 index 274cfee054..0000000000 --- a/board/hatch_fp/fpsensor_detect_rw.c +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "fpsensor_detect.h" -#include "gpio.h" -#include "timer.h" - -enum fp_sensor_type get_fp_sensor_type(void) -{ - enum fp_sensor_type ret; - - gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1); - usleep(1); - switch (gpio_get_level(GPIO_FP_SENSOR_SEL)) { - case 0: - ret = FP_SENSOR_TYPE_ELAN; - break; - case 1: - ret = FP_SENSOR_TYPE_FPC; - break; - default: - ret = FP_SENSOR_TYPE_UNKNOWN; - break; - } - /* We leave GPIO_DIVIDER_HIGHSIDE enabled, since the dragonclaw - * development board use it to enable the AND gate (U10) to CS. - * Production boards could disable this to save power since it's - * only needed for initial detection on those boards. - */ - return ret; -} - -enum fp_sensor_spi_select get_fp_sensor_spi_select(void) -{ - return FP_SENSOR_SPI_SELECT_PRODUCTION; -} diff --git a/board/hatch_fp/gpio.inc b/board/hatch_fp/gpio.inc deleted file mode 100644 index c5319c2bee..0000000000 --- a/board/hatch_fp/gpio.inc +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Interrupts */ -GPIO_INT(SLP_L, PIN(A, 8), GPIO_INT_BOTH, slp_event) -GPIO_INT(SLP_ALT_L, PIN(B, 6), GPIO_INT_BOTH, slp_event) -GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INPUT, spi_event) - -/* Inputs */ -GPIO(TRANSPORT_SEL, PIN(B, 1), GPIO_INPUT) -GPIO(WP, PIN(B, 7), GPIO_INPUT) - -/* Outputs */ -GPIO(EC_INT_L, PIN(A, 1), GPIO_OUT_HIGH) -GPIO(DIVIDER_HIGHSIDE, PIN(B, 8), GPIO_OUT_LOW) - -/* - * Unused pins. - * Configuring unused pins as ANALOG INPUT to save power. For more info - * look at "USING STM32F4 MCU POWER MODES WITH BEST DYNAMIC EFFICIENCY" - * ("AN4365") section 1.2.6 and STM32F412 reference manual section 7.3.12. - */ -UNUSED(PIN(B, 2)) -UNUSED(PIN(B, 5)) -UNUSED(PIN(C, 13)) -UNUSED(PIN(C, 14)) -UNUSED(PIN(C, 15)) -UNUSED(PIN(H, 0)) -UNUSED(PIN(H, 1)) - -UNIMPLEMENTED(ENTERING_RW) - -/* USART1: PA9/PA10 (TX/RX) to AP */ -ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART, MODULE_UART, GPIO_PULL_UP) -/* USART2: PA2/PA3 (TX/RX) to servo */ -ALTERNATE(PIN_MASK(A, 0x000C), GPIO_ALT_USART, MODULE_UART, GPIO_PULL_UP) -/* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */ -ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI, 0) - -#ifdef SECTION_IS_RW -#include "gpio_rw.inc" -#endif diff --git a/board/hatch_fp/gpio_rw.inc b/board/hatch_fp/gpio_rw.inc deleted file mode 100644 index 3dfe890c12..0000000000 --- a/board/hatch_fp/gpio_rw.inc +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef SECTION_IS_RW -#error "This file should only be included in RW." -#endif - -/* Interrupts */ -GPIO_INT(FPS_INT, PIN(A, 0), GPIO_INT_RISING, fps_event) - -/* Inputs */ -GPIO(FP_SENSOR_SEL, PIN(B, 0), GPIO_INPUT) - -/* Outputs */ -GPIO(FP_RST_ODL, PIN(B,10), GPIO_OUT_HIGH) -GPIO(SPI2_NSS, PIN(B,12), GPIO_OUT_HIGH) -GPIO(USER_PRES_L, PIN(B, 9), GPIO_ODR_HIGH) - -/* - * SPI2 master to sensor: PB13/14/15 (CLK/MISO/MOSI) - * Note that we're not configuring NSS (PB12) here because we have already - * configured it as a GPIO above and the SPI_MASTER module expects to use it - * in software NSS management mode, not hardware management mode. - */ -ALTERNATE(PIN_MASK(B, 0xE000), GPIO_ALT_SPI, MODULE_SPI_CONTROLLER, GPIO_PULL_DOWN) |