diff options
Diffstat (limited to 'board/hyperdebug/gpio.inc')
| -rw-r--r-- | board/hyperdebug/gpio.inc | 186 |
1 files changed, 186 insertions, 0 deletions
diff --git a/board/hyperdebug/gpio.inc b/board/hyperdebug/gpio.inc new file mode 100644 index 0000000000..5dc0cebc1b --- /dev/null +++ b/board/hyperdebug/gpio.inc @@ -0,0 +1,186 @@ +/* -*- mode:c -*- + * + * Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * List of all GPIO pins available for Host computer to manipulate. + * The are named based on their location on the two 70-pin DIL + * connectors on either side of the HyperDebug board. Pins with + * special functions are commented out, and declared with relevant + * symbolic name further below. + */ + +GPIO(CN7_1, PIN(C, 6), GPIO_INPUT) +/*GPIO(CN7_2, PIN(B, 8), GPIO_INPUT) I2C1 */ +GPIO(CN7_3, PIN(D, 11), GPIO_INPUT) +/*GPIO(CN7_4, PIN(B, 9), GPIO_INPUT) I2C1 */ +GPIO(CN7_5, PIN(B, 13), GPIO_INPUT) +/* CN7_6 is VREFP */ +GPIO(CN7_7, PIN(D, 12), GPIO_INPUT) +/* CN7_8 is GND */ +/*GPIO(CN7_9, PIN(A, 4), GPIO_INPUT) CC1 */ +/*GPIO(CN7_10, PIN(A, 5), GPIO_INPUT) CC2 */ +GPIO(CN7_11, PIN(B, 4), GPIO_INPUT) +GPIO(CN7_12, PIN(A, 6), GPIO_INPUT) +/*GPIO(CN7_13, PIN(B, 5), GPIO_INPUT) Nucleo USB-C */ +GPIO(CN7_14, PIN(A, 7), GPIO_INPUT) +GPIO(CN7_15, PIN(B, 3), GPIO_INPUT) +GPIO(CN7_16, PIN(D, 14), GPIO_INPUT) +/*GPIO(CN7_17, PIN(A, 4), GPIO_INPUT)*/ +GPIO(CN7_18, PIN(D, 15), GPIO_INPUT) +/*GPIO(CN7_19, PIN(B, 4), GPIO_INPUT)*/ +GPIO(CN7_20, PIN(F, 12), GPIO_INPUT) + +/* CN8_1 is NC */ +GPIO(CN8_2, PIN(C, 8), GPIO_INPUT) +/* CN8_3 is IOREF */ +GPIO(CN8_4, PIN(C, 9), GPIO_INPUT) +/* CN8_5 is NRST */ +/*GPIO(CN8_6, PIN(C, 10), GPIO_INPUT) UART4 */ +/* CN8_7 is 3V3 */ +/*GPIO(CN8_8, PIN(C, 11), GPIO_INPUT) UART4 */ +/* CN8_9 is 5V */ +/*GPIO(CN8_10, PIN(C, 12), GPIO_INPUT) UART5 */ +/* CN8_11 is GND */ +/*GPIO(CN8_12, PIN(D, 2), GPIO_INPUT) UART5 */ +/* CN8_13 is GND */ +GPIO(CN8_14, PIN(F, 3), GPIO_INPUT) +/* CN8_15 is VIN */ +GPIO(CN8_16, PIN(F, 5), GPIO_INPUT) + +GPIO(CN9_1, PIN(A, 3), GPIO_INPUT) +GPIO(CN9_2, PIN(D, 7), GPIO_INPUT) +GPIO(CN9_3, PIN(A, 2), GPIO_INPUT) +/*GPIO(CN9_4, PIN(D, 6), GPIO_INPUT) UART2 */ +GPIO(CN9_5, PIN(C, 3), GPIO_INPUT) +/*GPIO(CN9_6, PIN(D, 5), GPIO_INPUT) UART2 */ +GPIO(CN9_7, PIN(B, 0), GPIO_INPUT) +/*GPIO(CN9_8, PIN(D, 4), GPIO_INPUT) SPI2 */ +/*GPIO(CN9_9, PIN(C, 1), GPIO_INPUT) I2C3 */ +/*GPIO(CN9_10, PIN(D, 3), GPIO_INPUT) SPI2 */ +/*GPIO(CN9_11, PIN(C, 0), GPIO_INPUT) I2C3 */ +/* CN9_12 is GND */ +GPIO(CN9_13, PIN(B, 2), GPIO_INPUT) +GPIO(CN9_14, PIN(E, 2), GPIO_INPUT) +GPIO(CN9_15, PIN(B, 6), GPIO_INPUT) +GPIO(CN9_16, PIN(E, 4), GPIO_INPUT) +GPIO(CN9_17, PIN(F, 2), GPIO_INPUT) +GPIO(CN9_18, PIN(E, 5), GPIO_INPUT) +/*GPIO(CN9_19, PIN(F, 1), GPIO_INPUT) I2C2 */ +GPIO(CN9_20, PIN(E, 6), GPIO_INPUT) +/*GPIO(CN9_21, PIN(F, 0), GPIO_INPUT) I2C2 */ +GPIO(CN9_22, PIN(E, 3), GPIO_INPUT) +/* CN9_23 is GND */ +GPIO(CN9_24, PIN(F, 8), GPIO_INPUT) +/*GPIO(CN9_25, PIN(D, 0), GPIO_INPUT) SPI2 */ +GPIO(CN9_26, PIN(F, 7), GPIO_INPUT) +/*GPIO(CN9_27, PIN(D, 1), GPIO_INPUT) SPI2 */ +GPIO(CN9_28, PIN(F, 9), GPIO_INPUT) +GPIO(CN9_29, PIN(G, 0), GPIO_INPUT) +GPIO(CN9_30, PIN(G, 1), GPIO_INPUT) + +/* CN10_1 is AVDD */ +GPIO(CN10_2, PIN(F, 13), GPIO_INPUT) +/* CN10_3 is AGND */ +GPIO(CN10_4, PIN(E, 9), GPIO_INPUT) +/* CN10_5 is GND */ +/*GPIO(CN10_6, PIN(E, 11), GPIO_INPUT) QSPI */ +GPIO(CN10_7, PIN(B, 1), GPIO_INPUT) +GPIO(CN10_8, PIN(F, 14), GPIO_INPUT) +/*GPIO(CN10_9, PIN(C, 2), GPIO_INPUT) Nucleo USB VBUS sense */ +/*GPIO(CN10_10, PIN(E, 13), GPIO_INPUT) QSPI */ +GPIO(CN10_11, PIN(A, 1), GPIO_INPUT) +GPIO(CN10_12, PIN(F, 15), GPIO_INPUT) +/*GPIO(CN10_13, PIN(A, 2), GPIO_INPUT)*/ +/*GPIO(CN10_14, PIN(D, 8), GPIO_INPUT) UART3 */ +GPIO(CN10_15, PIN(B, 10), GPIO_INPUT) +/*GPIO(CN10_16, PIN(D, 9), GPIO_INPUT) UART3 */ +/* CN10_17 is GND */ +GPIO(CN10_18, PIN(E, 8), GPIO_INPUT) +/*GPIO(CN10_19, PIN(E, 15), GPIO_INPUT) QSPI */ +GPIO(CN10_20, PIN(E, 7), GPIO_INPUT) +/*GPIO(CN10_21, PIN(B, 0), GPIO_INPUT)*/ +/* CN10_22 is GND */ +/*GPIO(CN10_23, PIN(E, 12), GPIO_INPUT) QSPI */ +/*GPIO(CN10_24, PIN(E, 10), GPIO_INPUT) QSPI */ +/*GPIO(CN10_25, PIN(E, 14), GPIO_INPUT) QSPI */ +/*GPIO(CN10_26, PIN(E, 12), GPIO_INPUT) QSPI */ +/* CN10_27 is GND */ +/*GPIO(CN10_28, PIN(E, 14), GPIO_INPUT) QSPI */ +GPIO(CN10_29, PIN(A, 0), GPIO_INPUT) +/*GPIO(CN10_30, PIN(E, 15), GPIO_INPUT) QSPI */ +GPIO(CN10_31, PIN(A, 8), GPIO_INPUT) +/*GPIO(CN10_32, PIN(B, 10), GPIO_INPUT)*/ +GPIO(CN10_33, PIN(E, 0), GPIO_INPUT) +GPIO(CN10_34, PIN(B, 11), GPIO_INPUT) + + +/* QSPI controller */ +GPIO(QSPI_DEV_CLK, PIN(E, 10), GPIO_INPUT) +GPIO(QSPI_DEV_CS_L, PIN(E, 11), GPIO_INPUT) +GPIO(QSPI_DEV_D0, PIN(E, 12), GPIO_INPUT) +GPIO(QSPI_DEV_D1, PIN(E, 13), GPIO_INPUT) +GPIO(QSPI_DEV_D2, PIN(E, 14), GPIO_INPUT) +GPIO(QSPI_DEV_D3, PIN(E, 15), GPIO_INPUT) + +/* I2C pins should be configured as inputs until I2C module is */ +/* initialized. This will avoid driving the lines unintentionally.*/ +GPIO(TPM_I2C1_HOST_SCL, PIN(B, 8), GPIO_OUTPUT | GPIO_OPEN_DRAIN) +GPIO(TPM_I2C1_HOST_SDA, PIN(B, 9), GPIO_OUTPUT | GPIO_OPEN_DRAIN) +GPIO(INA_I2C2_DEV_SCL, PIN(F, 1), GPIO_OUTPUT | GPIO_OPEN_DRAIN) +GPIO(INA_I2C2_DEV_SDA, PIN(F, 0), GPIO_OUTPUT | GPIO_OPEN_DRAIN) +GPIO(AUX_I2C3_DEV_SCL, PIN(C, 0), GPIO_OUTPUT | GPIO_OPEN_DRAIN) +GPIO(AUX_I2C3_DEV_SDA, PIN(C, 1), GPIO_OUTPUT | GPIO_OPEN_DRAIN) + +/* These pins are used for USART and are set to alternate mode below */ +GPIO(USART2_OT_TX, PIN(D, 5), GPIO_INPUT) +GPIO(USART2_OT_RX, PIN(D, 6), GPIO_INPUT) +GPIO(USART4_AP_TX, PIN(C, 10), GPIO_INPUT) +GPIO(USART4_AP_RX, PIN(C, 11), GPIO_INPUT) +GPIO(USART5_FPMCU_TX, PIN(C, 12), GPIO_INPUT) +GPIO(USART5_FPMCU_RX, PIN(D, 2), GPIO_INPUT) +GPIO(USART3_EC_TX, PIN(D, 8), GPIO_INPUT) +GPIO(USART3_EC_RX, PIN(D, 9), GPIO_INPUT) +GPIO(LPUART1_HYPER_RX, PIN(G, 7), GPIO_INPUT) +GPIO(LPUART1_HYPER_TX, PIN(G, 8), GPIO_INPUT) + +/* Additional SPI controller, only available on CN11/CN12 */ +GPIO(SPI2_CS, PIN(D, 0), GPIO_OUT_HIGH) +GPIO(SPI2_SCK, PIN(D, 1), GPIO_ALTERNATE) +GPIO(SPI2_CIDO, PIN(D, 3), GPIO_ALTERNATE) +GPIO(SPI2_CODI, PIN(D, 4), GPIO_ALTERNATE) + +/* USB pins */ +GPIO(USB_FS_DM, PIN(A, 11), GPIO_ALTERNATE) +GPIO(USB_FS_DP, PIN(A, 12), GPIO_ALTERNATE) +GPIO(CC1, PIN(A, 4), GPIO_ANALOG) +GPIO(CC2, PIN(A, 5), GPIO_ANALOG) + +/* Signals for hardware on the Nucleo board itself */ +GPIO(NUCLEO_LED1, PIN(C, 7), GPIO_OUT_HIGH) /* Green */ +GPIO(NUCLEO_LED2, PIN(B, 7), GPIO_OUT_LOW) /* Blue */ +GPIO(NUCLEO_LED3, PIN(A, 9), GPIO_OUT_LOW) /* Red */ + +/* Unimplemented signals since we are not an EC */ +UNIMPLEMENTED(ENTERING_RW) +UNIMPLEMENTED(WP_L) + + +ALTERNATE(PIN_MASK(A, 0x1800), 10, MODULE_USB, 0) /* USB: PA11/12 */ + +ALTERNATE(PIN_MASK(D, 0x0060), 7, MODULE_UART, 0) /* USART2: PD5/PD6 - OT UART */ +ALTERNATE(PIN_MASK(C, 0x0C00), 8, MODULE_UART, 0) /* USART4: PC10/PC11 - AP UART */ +ALTERNATE(PIN_MASK(D, 0x0300), 7, MODULE_UART, 0) /* USART3: PD8/PD9 - EC UART */ +ALTERNATE(PIN_MASK(C, 0x1000), 8, MODULE_UART, 0) /* USART5: PC12 - FP MCU UART */ +ALTERNATE(PIN_MASK(D, 0x0004), 8, MODULE_UART, 0) /* USART5: PD2 - FP MCU UART */ +ALTERNATE(PIN_MASK(G, 0x0180), 8, MODULE_UART, 0) /* LPUART1: PG7/PG8 - HyperDebug console */ + +ALTERNATE(PIN_MASK(F, 0x0003), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C2: PF0/PF1 */ +ALTERNATE(PIN_MASK(B, 0x0300), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C1: PB8/PB9 */ +ALTERNATE(PIN_MASK(C, 0x0003), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C3: PC0/PC1 */ +/*ALTERNATE(PIN_MASK(E, 0xFC00), 10, MODULE_SPI_FLASH, 0) / * QSPI: PE10-15 */ +/*ALTERNATE(PIN_MASK(D, 0x0001), 5, MODULE_SPI, 0) / * SPI2: PD0 CS */ +ALTERNATE(PIN_MASK(D, 0x001A), 5, MODULE_SPI, 0) /* SPI2: PD1/PD3/PD4 SCK/CIDO/DOCI */ |