diff options
Diffstat (limited to 'board/kukui_scp/board.h')
| -rw-r--r-- | board/kukui_scp/board.h | 56 |
1 files changed, 41 insertions, 15 deletions
diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h index 0c42c0cf2a..64104060ab 100644 --- a/board/kukui_scp/board.h +++ b/board/kukui_scp/board.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,8 +16,8 @@ #define CONFIG_FLASH_SIZE_BYTES 0x58000 /* Image file size: 256KB */ #endif -#undef CONFIG_LID_SWITCH -#undef CONFIG_FW_INCLUDE_RO +#undef CONFIG_LID_SWITCH +#undef CONFIG_FW_INCLUDE_RO #define CONFIG_MKBP_EVENT /* Sent MKBP event via IPI. */ #define CONFIG_MKBP_USE_CUSTOM @@ -27,10 +27,12 @@ #define CONFIG_HOSTCMD_ALIGNED /* + * mt8183: + * * RW only, no flash * +-------------------- 0x0 * | ROM vectortable, .text, .rodata, .data LMA - * +-------------------- 0x10000 + * +-------------------- 0x58000 * | RAM .bss, .data * +-------------------- 0x7BDB0 * | IPI shared buffer with AP (288 + 8) * 2 @@ -40,11 +42,23 @@ * | 8KB D-CACHE * +-------------------- 0x80000 */ -#ifdef CHIP_VARIANT_MT8186 -#define ICACHE_BASE 0x3E000 -#else -#define ICACHE_BASE 0x7C000 -#endif + +/* + * mt8186: + * + * RW only, no flash + * +-------------------- 0x0 + * | ROM vectortable, .text, .rodata, .data LMA + * +-------------------- 0x2C000 + * | RAM .bss, .data + * +-------------------- 0x3BDB0 + * | IPI shared buffer with AP (288 + 8) * 2 => 0x250 + * +-------------------- 0x3C000 + * | 8KB I-CACHE + * +-------------------- 0x3E000 + * | 8KB D-CACHE + * +-------------------- 0x40000 + */ #define CONFIG_ROM_BASE 0x0 @@ -54,6 +68,12 @@ #define CONFIG_RAM_BASE 0x58000 #endif +#ifdef CHIP_VARIANT_MT8186 +#define ICACHE_BASE 0x3C000 +#else +#define ICACHE_BASE 0x7C000 +#endif + #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE) #define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE) #define CONFIG_CODE_RAM_SIZE CONFIG_RAM_BASE @@ -64,12 +84,19 @@ #define CONFIG_DRAM_BASE 0x10000000 /* Shared memory address in AP physical address space. */ #define CONFIG_DRAM_BASE_LOAD 0x50000000 + +#ifdef CHIP_VARIANT_MT8186 +#define CONFIG_DRAM_SIZE 0x010a0000 /* 16 MB */ +#define CACHE_TRANS_AP_SIZE 0x010a0000 +#else #define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */ +#define CACHE_TRANS_AP_SIZE 0x00400000 +#endif /* IPI configs */ #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288 -#define CONFIG_IPC_SHARED_OBJ_ADDR \ - (ICACHE_BASE - \ +#define CONFIG_IPC_SHARED_OBJ_ADDR \ + (ICACHE_BASE - \ (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2) #define CONFIG_IPI #define CONFIG_RPMSG_NAME_SERVICE @@ -95,11 +122,10 @@ #define IPI_NS_SERVICE 0xFF - #undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 8192 -#undef CONFIG_UART_CONSOLE +#undef CONFIG_UART_CONSOLE /* * CONFIG_UART_CONSOLE * 0 - SCP UART0 @@ -112,8 +138,8 @@ #define CONFIG_UART_CONSOLE 0 #endif /* We let AP setup the correct pinmux. */ -#undef UART0_PINMUX_11_12 -#undef UART0_PINMUX_110_112 +#undef UART0_PINMUX_11_12 +#undef UART0_PINMUX_110_112 /* Track AP power state */ #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE |