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-rw-r--r--board/npcx7_evb/board.c122
-rw-r--r--board/npcx7_evb/board.h147
-rw-r--r--board/npcx7_evb/build.mk24
-rw-r--r--board/npcx7_evb/ec.tasklist14
-rw-r--r--board/npcx7_evb/gpio.inc114
5 files changed, 0 insertions, 421 deletions
diff --git a/board/npcx7_evb/board.c b/board/npcx7_evb/board.c
deleted file mode 100644
index 9ddaf9bd51..0000000000
--- a/board/npcx7_evb/board.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nuvoton M4 EB board-specific configuration */
-
-#include "adc.h"
-#include "backlight.h"
-#include "chipset.h"
-#include "common.h"
-#include "driver/temp_sensor/tmp006.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "peci.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "timer.h"
-#include "thermal.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
- [ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
- [ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
- [ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
- [ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
- [ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
- [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
- [PWM_CH_KBLIGHT] = { 2, 0, 10000 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
- .flags = FAN_USE_RPM_MODE,
- .ch = 0, /* Use MFT id to control fan */
- .pgood_gpio = GPIO_PGOOD_FAN,
- .enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
- .rpm_min = 1000,
- .rpm_start = 1000,
- .rpm_max = 5200,
-};
-
-const struct fan_t fans[] = {
- [FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
- [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
- {"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
- {"master1-0", NPCX_I2C_PORT1_0, 100, GPIO_I2C1_SCL0, GPIO_I2C1_SDA0},
- {"master2-0", NPCX_I2C_PORT2_0, 100, GPIO_I2C2_SCL0, GPIO_I2C2_SDA0},
- {"master3-0", NPCX_I2C_PORT3_0, 100, GPIO_I2C3_SCL0, GPIO_I2C3_SDA0},
- {"master7-0", NPCX_I2C_PORT7_0, 100, GPIO_I2C7_SCL0, GPIO_I2C7_SDA0},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
- { CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
- GPIO_AC_PRESENT,
- GPIO_LID_OPEN,
- GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
- .output_settle_us = 40,
- .debounce_down_us = 6 * MSEC,
- .debounce_up_us = 30 * MSEC,
- .scan_period_us = 1500,
- .min_post_scan_delay_us = 1000,
- .poll_timeout_us = SECOND,
- .actual_key_mask = {
- 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
- 0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8 /* full set */
- },
-};
diff --git a/board/npcx7_evb/board.h b/board/npcx7_evb/board.h
deleted file mode 100644
index 4bad61b152..0000000000
--- a/board/npcx7_evb/board.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Nuvoton M4 EB */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * npcx7 EVB version:
- * 1 - EVB version 1 supports: npcx7m6g
- * 2 - EVB version 2 supports:
- * npcx7m6f/npcx7m6fb/npcx7m6fc/npcx7m7fc/npcx7m7wb/npcx7m7wc
- */
-#if defined(CHIP_VARIANT_NPCX7M6G)
-#define BOARD_VERSION 1
-#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
- defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
- defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define BOARD_VERSION 2
-#endif
-
-/* EC modules */
-#define CONFIG_ADC
-#define CONFIG_PWM
-#define CONFIG_SPI
-#define CONFIG_I2C
-/* Features of eSPI */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-/* Optional features */
-#define CONFIG_ENABLE_JTAG_SELECTION
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
-#define CONFIG_POWER_BUTTON
-#undef CONFIG_PSTORE
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_VBOOT_HASH
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
-
-/* EC console commands */
-#define CONFIG_CMD_TASKREADY
-#define CONFIG_CMD_STACKOVERFLOW
-#define CONFIG_CMD_JUMPTAGS
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SPI_FLASH
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_I2CWEDGE
-
-/* I2C port for CONFIG_CMD_I2CWEDGE */
-#define I2C_PORT_MASTER NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST 0
-
-/* Fans for testing */
-#define CONFIG_FANS 1
-
-/* Internal spi-flash on npcx7 ec */
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_REGS
-#if defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
- defined(CHIP_VARIANT_NPCX7M7WC)
-#define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */
-#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */
-#else
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal spi flash type */
-#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB internal spi flash */
-#endif
-
-/* New features on npcx7 ec */
-#define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */
-#if (BOARD_VERSION == 2)
-#define CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
-#define CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
-#if defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define CONFIG_AUDIO_CODEC
-#define CONFIG_AUDIO_CODEC_DMIC
-#define CONFIG_AUDIO_CODEC_I2S_RX /* Use Audio front-end for Wake-on-Voice */
-#endif
-#undef CONFIG_FANS /* Remove fan application */
-#else
-#undef CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
-#undef CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
-#endif
-
-/* Optional feature to configure npcx7 chip */
-
-/* Select which UART Controller is the Console UART */
-#undef CONFIG_CONSOLE_UART
-#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */
-/*
- * This definition below actually doesn't define which UART controller to be
- * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are
- * connected to "UART1" controller.
- */
-#if (BOARD_VERSION == 2)
-#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */
-#else
-#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 as UART1 */
-#endif
-#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG */
-#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX7_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 (only in npcx7) */
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
- ADC_CH_0 = 0,
- ADC_CH_1,
- ADC_CH_2,
- ADC_CH_3,
- ADC_CH_4,
- ADC_CH_COUNT
-};
-
-enum pwm_channel {
- PWM_CH_FAN,
- PWM_CH_KBLIGHT,
- /* Number of PWM channels */
- PWM_CH_COUNT
-};
-
-enum fan_channel {
- FAN_CH_0,
- /* Number of FAN channels */
- FAN_CH_COUNT
-};
-
-enum mft_channel {
- MFT_CH_0,
- /* Number of MFT channels */
- MFT_CH_COUNT
-};
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/npcx7_evb/build.mk b/board/npcx7_evb/build.mk
deleted file mode 100644
index 4bd829202c..0000000000
--- a/board/npcx7_evb/build.mk
+++ /dev/null
@@ -1,24 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# the IC is Nuvoton NPCX7 M-Series EC (npcx7m6g, npcx7m6f, npcx7m6fb, npcx7m6fc,
-# npcx7m7fc, npcx7m7wb, npcx7m7wc)
-# CHIP_VARIANT:
-# npcx7m6g - for npcx7 ec without internal flash
-# npcx7m6f - for npcx7 ec with internal flash
-# npcx7m6fb - for npcx7 ec with internal flash, enhanced features.
-# npcx7m6fc - the same as npcx7m6fb but internal flash size is 512 Kbytes.
-# npcx7m7fc - the same as npcx7m6fc but more RAM sizes.
-# npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV.
-# npcx7m7wc - the same as npcx7m7wb but internal flash size is 512 Kbytes.
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wb
-
-board-y=board.o
diff --git a/board/npcx7_evb/ec.tasklist b/board/npcx7_evb/ec.tasklist
deleted file mode 100644
index 88b5ffaa62..0000000000
--- a/board/npcx7_evb/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
- TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
- TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
- TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
- TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
- TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/npcx7_evb/gpio.inc b/board/npcx7_evb/gpio.inc
deleted file mode 100644
index 145a48de85..0000000000
--- a/board/npcx7_evb/gpio.inc
+++ /dev/null
@@ -1,114 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Pins for internal flash testing */
-GPIO_INT(RECOVERY_L, PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, switch_interrupt)
-GPIO_INT(WP_L, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, switch_interrupt)
-
-/* Pins for hibernate testing */
-#ifdef CONFIG_HIBERNATE_PSL
-/*
- * Please notice internal PU/PD is gone if IOs are selected to PSL_INx. The
- * power consumption of PSL is ultra-low and sensitive. Putting a large
- * external PU/PD resistance for PSL input pins is recommended.
- */
-GPIO_INT(AC_PRESENT, PIN(D, 2), GPIO_INT_BOTH, extpower_interrupt) /* PSL_IN1# (Low Active) */
-GPIO_INT(POWER_BUTTON_L, PIN(0, 0), GPIO_INT_BOTH, power_button_interrupt) /* PSL_IN2# (Low Active) */
-GPIO_INT(LID_OPEN, PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) /* PSL_IN3# (High Active) */
-#else
-GPIO_INT(AC_PRESENT, PIN(7, 4), GPIO_INT_BOTH | GPIO_PULL_UP, extpower_interrupt)
-GPIO_INT(POWER_BUTTON_L, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-GPIO_INT(LID_OPEN, PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_DOWN, lid_interrupt)
-#endif
-
-/* Pins for SPI/FAN/LPC modules testing */
-GPIO(ENTERING_RW, PIN(3, 6), GPIO_OUT_LOW )
-GPIO(PCH_WAKE_L, PIN(5, 0), GPIO_OUT_HIGH)
-GPIO(PGOOD_FAN, PIN(C, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(SPI_CS_L, PIN(A, 5), GPIO_OUT_HIGH)
-
-/* Pins for I2C module testing */
-GPIO(I2C0_SCL0, PIN(B, 5), GPIO_ODR_HIGH)
-GPIO(I2C0_SDA0, PIN(B, 4), GPIO_ODR_HIGH)
-GPIO(I2C1_SCL0, PIN(9, 0), GPIO_ODR_HIGH)
-GPIO(I2C1_SDA0, PIN(8, 7), GPIO_ODR_HIGH)
-GPIO(I2C2_SCL0, PIN(9, 2), GPIO_ODR_HIGH)
-GPIO(I2C2_SDA0, PIN(9, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SCL0, PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SDA0, PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(I2C7_SDA0, PIN(B, 2), GPIO_ODR_HIGH)
-GPIO(I2C7_SCL0, PIN(B, 3), GPIO_ODR_HIGH)
-
-/* Pins for board version command */
-GPIO(BOARD_VERSION1, PIN(6, 4), GPIO_INPUT)
-GPIO(BOARD_VERSION2, PIN(6, 5), GPIO_INPUT)
-GPIO(BOARD_VERSION3, PIN(6, 6), GPIO_INPUT)
-
-/*********************** Alternate pins for npcx7 series **********************/
-#if (CONFIG_CONSOLE_UART == 0)
-/* UART1 Tx/Rx */
-#if NPCX_UART_MODULE2
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0) /* CR_SIN/SOUT GPIO64/65 */
-#else
-ALTERNATE(PIN_MASK(1, 0x03), 1, MODULE_UART, 0) /* CR_SIN/SOUT GPIO10/11 */
-#endif
-#else
-/* UART2 Tx/Rx */
-ALTERNATE(PIN_MASK(7, 0x20), 1, MODULE_UART, 0) /* CR_SIN2 GPIO75 */
-ALTERNATE(PIN_MASK(8, 0x40), 1, MODULE_UART, 0) /* CR_SOUT2 GPIO86 */
-#endif
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x3E), 1, MODULE_ADC, 0) /* ADC0/1/2/3/4 GPIO45/44/43/42/41 */
-
-/* SPI */
-ALTERNATE(PIN_MASK(A, 0x0A), 1, MODULE_SPI, 0) /* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
-ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0) /* SPIP_MISO GPIO95 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x10), 1, MODULE_PWM, 0) /* PWM2 for KBLIGHT Test - GPIOC4 */
-
-/* Fan (Tachometer) */
-#ifdef CONFIG_FANS
-ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0) /* PWM0 for FAN Test - GPIOC3 */
-#if NPCX_TACH_SEL2
-ALTERNATE(PIN_MASK(9, 0x08), 1, MODULE_PWM, 0) /* TA1_SL1 for FAN Test - GPIO93 */
-#else
-ALTERNATE(PIN_MASK(4, 0x01), 1, MODULE_PWM, 0) /* TA1_SL2 for FAN Test - GPIO40 */
-#endif
-#endif
-
-/* I2C Ports */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0) /* I2C0SDA0/SCL0 GPIOB4/B5 */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* I2C1SDA0 GPIO87 */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0) /* I2C1SCL0/I2C2SDA0/SCL0 GPIO90/91/92 */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3SDA0/SCL0 GPIOD0/D1 */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* I2C7SDA0/SCL0 GPIOB2/B3 */
-
-/* Keyboard Columns */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(1, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
-
-/* Keyboard Rows */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
-
-/* PSL for hibernating */
-#ifdef CONFIG_HIBERNATE_PSL
-ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0) /* PSL_IN1 GPIOD2 */
-ALTERNATE(PIN_MASK(0, 0x07), 1, MODULE_PMU, 0) /* PSL_IN2/3/4 GPIO00/01/02 */
-#endif
-
-#if defined(CONFIG_AUDIO_CODEC_I2S_RX) || defined(CONFIG_AUDIO_CODEC_WOV)
-ALTERNATE(PIN_MASK(A, 0xA0), 1, MODULE_WOV, 0) /* I2S_SYNC/I2S_SCLK GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1, MODULE_WOV, 0) /* I2S_SDAT GPIOB0 */
-ALTERNATE(PIN_MASK(9, 0x90), 1, MODULE_WOV, 0) /* DMIC_CLK/DMIC_IN GPIO94/97 */
-#endif
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