diff options
Diffstat (limited to 'board/plankton/usb_pd_config.h')
| -rw-r--r-- | board/plankton/usb_pd_config.h | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/board/plankton/usb_pd_config.h b/board/plankton/usb_pd_config.h index fca6484069..47614c3fce 100644 --- a/board/plankton/usb_pd_config.h +++ b/board/plankton/usb_pd_config.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 #define EXTI_COMP_MASK(p) BIT(21) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -92,9 +92,8 @@ static inline void pd_tx_disable(int port, int polarity) { /* output low on SPI TX to disable the FET */ /* PA6 is SPI1_MISO */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*6))) - | (1 << (2*6)); + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 6))) | (1 << (2 * 6)); /* put the low level reference in Hi-Z */ gpio_set_level(GPIO_USBC_CC1_TX_EN, 0); gpio_set_level(GPIO_USBC_CC2_TX_EN, 0); @@ -104,11 +103,10 @@ static inline void pd_tx_disable(int port, int polarity) static inline void pd_select_polarity(int port, int polarity) { /* use the right comparator non inverted input for COMP1 */ - STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) - | STM32_COMP_CMP1EN - | (polarity ? - STM32_COMP_CMP1INSEL_INM4 : - STM32_COMP_CMP1INSEL_INM6); + STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) | + STM32_COMP_CMP1EN | + (polarity ? STM32_COMP_CMP1INSEL_INM4 : + STM32_COMP_CMP1INSEL_INM6); gpio_set_level(GPIO_USBC_POLARITY, polarity); } |