diff options
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 78 |
1 files changed, 0 insertions, 78 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 7fe5d2c5ab..bdd04a7cb2 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -48,7 +48,6 @@ enum ish_i2c_port { #define ISH_IOAPIC_BASE 0xFEC00000 #define ISH_HPET_BASE 0x04700000 #define ISH_LAPIC_BASE 0xFEE00000 -#define ISH_SBEP_BASE 0x04500000 #else #define ISH_I2C0_BASE 0x00100000 #define ISH_I2C1_BASE 0x00102000 @@ -129,66 +128,6 @@ enum ish_i2c_port { #define ISH_GPIO_GWSR REG32(ISH_GPIO_BASE + 0x118) /* Wake Source */ #define ISH_GPIO_GSEC REG32(ISH_GPIO_BASE + 0x130) /* Secure Input */ -#if defined(CHIP_VARIANT_ISH5P4) -/* Side Band End Point registers */ -#define SBEP_REG_CLK_GATE_ENABLE REG32(ISH_SBEP_BASE + 0x006C) -#define SB_CLK_GATE_EN_LOCAL_CLK_GATE BIT(0) -#define SB_CLK_GATE_EN_TRUNK_CLK_GATE BIT(1) -#endif - -#define SBEP_REG_UP_MSG_STATUS_ADDR (ISH_SBEP_BASE + 0x0040) -#define SBEP_REG_UP_MSG_STATUS REG32(ISH_SBEP_BASE + 0x0040) -#define SBEP_REG_UP_MSG_COMMAND REG32(ISH_SBEP_BASE + 0x0044) -#define SBEP_REG_UP_MSG_REQ_ADDR_LOW REG32(ISH_SBEP_BASE + 0x0048) -#define SBEP_REG_UP_MSG_REQ_ADDR_HIGH REG32(ISH_SBEP_BASE + 0x004C) -#define SBEP_REG_UP_MSG_REQ_DATA REG32(ISH_SBEP_BASE + 0x0050) -#define SBEP_REG_UP_MSG_REQ_ATTR REG32(ISH_SBEP_BASE + 0x0054) -#define SBEP_REG_UP_MSG_REQ_EH REG32(ISH_SBEP_BASE + 0x0058) - -#define UP_STATUS_BUSY_MASK 0x01 -#define UP_STATUS_MSG_SENT_MASK 0x02 -#define UP_STATUS_MSG_SENT_CLR 0x02 - -#define SBEP_CMD_ACTION 0x1 -#define SBEP_CMD_TYPE_WRITE 0x0 -#define SBEP_CMD_TYPE_READ 0x1 -#define SBEP_CMD_POSTED 0x1 -#define SBEP_CMD_NON_POSTED 0x0 -#define SBEP_CMD_INT_ENABLED 0x1 -#define SBEP_CMD_ACTION_OFF 0 -#define SBEP_CMD_TYPE_OFF 1 -#define SBEP_CMD_POSTED_OFF 2 -#define SBEP_CMD_INT_OFF 3 - -#define SBEP_CMD_WRITE \ - ((SBEP_CMD_ACTION << SBEP_CMD_ACTION_OFF) | \ - (SBEP_CMD_TYPE_WRITE << SBEP_CMD_TYPE_OFF) | \ - (SBEP_CMD_POSTED << SBEP_CMD_POSTED_OFF) | \ - (SBEP_CMD_INT_ENABLED << SBEP_CMD_INT_OFF)) - -#define SBEP_ATTR_LTR_OPCODE 0x43 -#define SBEP_ATTR_PMC_DEST_ID 0xCC -#define SBEP_ATTR_DEST_ID_OFF 0 -#define SBEP_ATTR_OPCODE_OFF 8 -#define SBEP_ATTR_WRITE_ALL_BYTES 0xF -#define SBEP_ATTR_BYTE_ENABLE_OFF 16 -#define LTR_CMD_ATTR \ - ((SBEP_ATTR_PMC_DEST_ID << SBEP_ATTR_DEST_ID_OFF) | \ - (SBEP_ATTR_LTR_OPCODE << SBEP_ATTR_OPCODE_OFF) | \ - (SBEP_ATTR_WRITE_ALL_BYTES << SBEP_ATTR_BYTE_ENABLE_OFF)) -#define LTR_CMD_DATA_2MS 0x90029002 -#define LTR_CMD_DATA_INFINITE 0 - -#define SBEP_SAIRS_ROOT_SPACE_PMC 0 - -#define SBEP_SAIRS_EH_PRESENT 1 -#define SBEP_SAIRS_ROOT_SPACE_OFF 16 -#define SBEP_SAIRS_EH_PRESENT_OFF 31 - -#define SBEP_PMC_SAIRS_VAL \ - ((SBEP_SAIRS_ROOT_SPACE_PMC << SBEP_SAIRS_ROOT_SPACE_OFF) | \ - (SBEP_SAIRS_EH_PRESENT << SBEP_SAIRS_EH_PRESENT_OFF)) - /* APIC interrupt vectors */ #define ISH_TS_VECTOR 0x20 /* Task switch vector */ #define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */ @@ -269,7 +208,6 @@ enum ish_i2c_port { #define PMU_PMC_PG_WAKE REG32(ISH_PMU_BASE + 0xF18) #define PMU_INTERNAL_PCE REG32(ISH_PMU_BASE + 0xF30) #define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100) -#define PMU_D3_STATUS_1 REG32(ISH_PMU_BASE + 0x104) #define PMU_HOST_RST_B BIT(0) #define PMU_PCE_SHADOW_MASK 0x1F #define PMU_PCE_PG_ALLOWED BIT(4) @@ -294,10 +232,6 @@ enum ish_i2c_port { #define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26) #define PMU_BME_BIT_RISING_EDGE_MASK BIT(27) #define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28) -#define PMU_REG_MASK_D3_RISE REG32(ISH_PMU_BASE + 0x200) -#define PMU_REG_MASK_D3_FALL REG32(ISH_PMU_BASE + 0x208) -#define PMU_REG_MASK_BME_RISE REG32(ISH_PMU_BASE + 0x220) -#define PMU_REG_MASK_BME_FALL REG32(ISH_PMU_BASE + 0x228) #endif #define PMU_GPIO_WAKE_MASK0 REG32(ISH_PMU_BASE + 0x250) @@ -322,7 +256,6 @@ enum ish_i2c_port { #define VNN_ID_DMA0 4 #define VNN_ID_DMA(chan) (VNN_ID_DMA0 + chan) -#define VNN_ID_SIDEBAND 21 /* OCP registers */ #define OCP_IOSF2OCP_BRIDGE (ISH_OCP_BASE + 0x9400) @@ -389,7 +322,6 @@ enum ish_i2c_port { #define DEST_BURST_SIZE 3 #define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10) -#define PMU_MASK_EVENT2 REG32(ISH_PMU_BASE + 0x4C) #define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin) #define PMU_MASK_EVENT_BIT_HPET BIT(16) #define PMU_MASK_EVENT_BIT_IPC BIT(17) @@ -400,16 +332,6 @@ enum ish_i2c_port { #define PMU_MASK_EVENT_BIT_SPI BIT(22) #define PMU_MASK_EVENT_BIT_UART BIT(23) #define PMU_MASK_EVENT_BIT_ALL (0xffffffff) -#define PMU_MASK_EVENT2_SRAM_ERASE1 BIT(3) -#define PMU_MASK_EVENT2_SRAM_ERASE0 BIT(4) -#define PMU_MASK_EVENT2_ISOL_ACK_RISE BIT(14) -#define PMU_MASK_EVENT2_ISOL_ACK_FALL BIT(15) -#define PMU_MASK_EVENT2_HOST_RST_RISE BIT(16) -#define PMU_MASK_EVENT2_HOST_RST_FALL BIT(17) -#define PMU_MASK2_ALL_EVENTS \ - (PMU_MASK_EVENT2_SRAM_ERASE0 | PMU_MASK_EVENT2_SRAM_ERASE1 | \ - PMU_MASK_EVENT2_ISOL_ACK_RISE | PMU_MASK_EVENT2_ISOL_ACK_FALL | \ - PMU_MASK_EVENT2_HOST_RST_RISE | PMU_MASK_EVENT2_HOST_RST_FALL) #define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30) |