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-rw-r--r--chip/mec1322/system.c57
1 files changed, 28 insertions, 29 deletions
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
index b672f72d2d..13fc2d9f81 100644
--- a/chip/mec1322/system.c
+++ b/chip/mec1322/system.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* System module for Chrome EC : MEC1322 hardware specific implementation */
+#include "builtin/assert.h"
#include "clock.h"
#include "common.h"
#include "console.h"
@@ -23,38 +24,37 @@
/* Indices for hibernate data registers (RAM backed by VBAT) */
enum hibdata_index {
- HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */
+ HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */
HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
- HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */
- HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */
- HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */
+ HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */
+ HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */
+ HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */
};
static void check_reset_cause(void)
{
uint32_t status = MEC1322_VBAT_STS;
uint32_t flags = 0;
- uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
- (MEC1322_PWR_RST_STS_VCC1 |
- MEC1322_PWR_RST_STS_VBAT);
+ uint32_t rst_sts =
+ MEC1322_PCR_CHIP_PWR_RST &
+ (MEC1322_PWR_RST_STS_VCC1 | MEC1322_PWR_RST_STS_VBAT);
/* Clear the reset causes now that we've read them */
MEC1322_VBAT_STS |= status;
MEC1322_PCR_CHIP_PWR_RST |= rst_sts;
/*
- * BIT[6] determine VCC1 reset
- */
+ * BIT[6] determine VCC1 reset
+ */
if (rst_sts & MEC1322_PWR_RST_STS_VCC1)
flags |= EC_RESET_FLAG_RESET_PIN;
-
flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0;
- if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
- EC_RESET_FLAG_HARD |
- EC_RESET_FLAG_HIBERNATE)))
+ if ((status & MEC1322_VBAT_STS_WDT) &&
+ !(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
+ EC_RESET_FLAG_HIBERNATE)))
flags |= EC_RESET_FLAG_WATCHDOG;
system_set_reset_flags(flags);
@@ -64,18 +64,18 @@ int system_is_reboot_warm(void)
{
uint32_t reset_flags;
/*
- * Check reset cause here,
- * gpio_pre_init is executed faster than system_pre_init
- */
+ * Check reset cause here,
+ * gpio_pre_init is executed faster than system_pre_init
+ */
check_reset_cause();
reset_flags = system_get_reset_flags();
if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
- (reset_flags & EC_RESET_FLAG_POWER_ON) ||
- (reset_flags & EC_RESET_FLAG_WATCHDOG) ||
- (reset_flags & EC_RESET_FLAG_HARD) ||
- (reset_flags & EC_RESET_FLAG_SOFT) ||
- (reset_flags & EC_RESET_FLAG_HIBERNATE))
+ (reset_flags & EC_RESET_FLAG_POWER_ON) ||
+ (reset_flags & EC_RESET_FLAG_WATCHDOG) ||
+ (reset_flags & EC_RESET_FLAG_HARD) ||
+ (reset_flags & EC_RESET_FLAG_SOFT) ||
+ (reset_flags & EC_RESET_FLAG_HIBERNATE))
return 0;
else
return 1;
@@ -105,8 +105,7 @@ uint32_t chip_read_reset_flags(void)
return MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
}
-noreturn
-void _system_reset(int flags, int wake_from_hibernate)
+noreturn void _system_reset(int flags, int wake_from_hibernate)
{
uint32_t save_flags = 0;
@@ -355,7 +354,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
}
}
- asm("wfi");
+ cpu_enter_suspend_mode();
/* Use 48MHz clock to speed through wake-up */
MEC1322_PCR_PROC_CLK_CTL = 1;
@@ -381,14 +380,14 @@ enum ec_image system_get_shrspi_image_copy(void)
uint32_t system_get_lfw_address(void)
{
- uint32_t * const lfw_vector =
- (uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
+ uint32_t *const lfw_vector =
+ (uint32_t *const)CONFIG_PROGRAM_MEMORY_BASE;
return *(lfw_vector + 1);
}
void system_set_image_copy(enum ec_image copy)
{
- MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ?
- EC_IMAGE_RW : EC_IMAGE_RO;
+ MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) =
+ (copy == EC_IMAGE_RW) ? EC_IMAGE_RW : EC_IMAGE_RO;
}