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-rw-r--r--chip/mt_scp/mt8192/build.mk10
-rw-r--r--chip/mt_scp/mt8192/clock.c369
-rw-r--r--chip/mt_scp/mt8192/clock_regs.h85
-rw-r--r--chip/mt_scp/mt8192/intc.h126
-rw-r--r--chip/mt_scp/mt8192/uart.c30
-rw-r--r--chip/mt_scp/mt8192/video.c19
6 files changed, 0 insertions, 639 deletions
diff --git a/chip/mt_scp/mt8192/build.mk b/chip/mt_scp/mt8192/build.mk
deleted file mode 100644
index c81bd83595..0000000000
--- a/chip/mt_scp/mt8192/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Required chip modules
-chip-y+=$(CHIP_VARIANT)/uart.o
-chip-y+=$(CHIP_VARIANT)/clock.o
-chip-y+=$(CHIP_VARIANT)/video.o
-
diff --git a/chip/mt_scp/mt8192/clock.c b/chip/mt_scp/mt8192/clock.c
deleted file mode 100644
index 43f570fc62..0000000000
--- a/chip/mt_scp/mt8192/clock.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include <assert.h>
-#include <string.h>
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "csr.h"
-#include "ec_commands.h"
-#include "power.h"
-#include "registers.h"
-#include "timer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
-
-enum scp_clock_source {
- SCP_CLK_26M = CLK_SW_SEL_26M,
- SCP_CLK_32K = CLK_SW_SEL_32K,
- SCP_CLK_ULPOSC2 = CLK_SW_SEL_ULPOSC2,
- SCP_CLK_ULPOSC1 = CLK_SW_SEL_ULPOSC1,
-};
-
-static struct opp_ulposc_cfg {
- uint32_t osc;
- uint32_t div;
- uint32_t fband;
- uint32_t mod;
- uint32_t cali;
- uint32_t target_mhz;
-} opp[] = {
- {
- .osc = 1, .target_mhz = 196, .div = 20, .fband = 10, .mod = 3,
- .cali = 64,
- },
- {
- .osc = 0, .target_mhz = 260, .div = 14, .fband = 2, .mod = 0,
- .cali = 64,
- },
- {
- .osc = 1, .target_mhz = 280, .div = 20, .fband = 2, .mod = 0,
- .cali = 64,
- },
- {
- .osc = 1, .target_mhz = 360, .div = 20, .fband = 10, .mod = 0,
- .cali = 64,
- },
-};
-
-static inline void clock_busy_udelay(int usec)
-{
- /*
- * Delaying by busy-looping, for place that can't use udelay because of
- * the clock not configured yet. The value 28 is chosen approximately
- * from experiment.
- *
- * `volatile' in order to avoid compiler to optimize the function out
- * (otherwise, the function will be eliminated).
- */
- volatile int i = usec * 28;
-
- while (--i)
- ;
-}
-
-static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
-{
- unsigned int val = 0;
-
- /* set div */
- val |= opp->div << OSC_DIV_SHIFT;
- /* set F-band; I-band = 82 */
- val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT);
- /* set calibration */
- val |= opp->cali;
- /* set control register 0 */
- AP_ULPOSC_CON0(opp->osc) = val;
-
- /* set mod */
- val = opp->mod << OSC_MOD_SHIFT;
- /* rsv2 = 0, rsv1 = 41, cali_32k = 0 */
- val |= 41 << OSC_RSV1_SHIFT;
- /* set control register 1 */
- AP_ULPOSC_CON1(opp->osc) = val;
-
- /* bias = 64 */
- AP_ULPOSC_CON2(opp->osc) = 64;
-}
-
-static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
- uint32_t cali_val)
-{
- uint32_t val;
-
- val = AP_ULPOSC_CON0(opp->osc);
- val &= ~OSC_CALI_MASK;
- val |= cali_val;
- AP_ULPOSC_CON0(opp->osc) = val;
-
- clock_busy_udelay(50);
-}
-
-static uint32_t clock_ulposc_measure_freq(uint32_t osc)
-{
- uint32_t result = 0;
- int cnt;
-
- /* before select meter clock input, bit[1:0] = b00 */
- AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
- DBG_MODE_SET_CLOCK;
-
- /* select source, bit[21:16] = clk_src */
- AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
- (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
- DBG_BIST_SOURCE_ULPOSC2);
-
- /* set meter divisor to 1, bit[31:24] = b00000000 */
- AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
- MISC_METER_DIV_1;
-
- /* enable frequency meter, without start */
- AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
-
- /* trigger frequency meter start */
- AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
-
- /*
- * Frequency meter counts cycles in 1 / (26 * 1024) second period.
- * freq_in_hz = freq_counter * 26 * 1024
- *
- * The hardware takes 38us to count cycles. Delay up to 100us,
- * as clock_busy_udelay may not be accurate when sysclk is not 26Mhz
- * (e.g. when recalibrating/measuring after boot).
- */
- for (cnt = 100; cnt > 0; --cnt) {
- clock_busy_udelay(1);
- if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
- result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
- break;
- }
- }
-
- /* disable freq meter */
- AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
-
- return result;
-}
-
-#define CAL_MIS_RATE 40
-static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
-{
- uint32_t curr, target;
-
- curr = clock_ulposc_measure_freq(opp->osc);
- target = opp->target_mhz * 1024 / 26;
-
- /* check if calibrated value is in the range of target value +- 4% */
- if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
- curr < (target * (1000 + CAL_MIS_RATE) / 1000))
- return 1;
- else
- return 0;
-}
-
-static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
-{
- uint32_t current_val = 0;
- uint32_t target_val = opp->target_mhz * 1024 / 26;
- uint32_t middle, min = 0, max = OSC_CALI_MASK;
- uint32_t diff_by_min, diff_by_max, cal_result;
-
- do {
- middle = (min + max) / 2;
- if (middle == min)
- break;
-
- clock_ulposc_config_cali(opp, middle);
- current_val = clock_ulposc_measure_freq(opp->osc);
-
- if (current_val > target_val)
- max = middle;
- else
- min = middle;
- } while (min <= max);
-
- clock_ulposc_config_cali(opp, min);
- current_val = clock_ulposc_measure_freq(opp->osc);
- if (current_val > target_val)
- diff_by_min = current_val - target_val;
- else
- diff_by_min = target_val - current_val;
-
- clock_ulposc_config_cali(opp, max);
- current_val = clock_ulposc_measure_freq(opp->osc);
- if (current_val > target_val)
- diff_by_max = current_val - target_val;
- else
- diff_by_max = target_val - current_val;
-
- if (diff_by_min < diff_by_max)
- cal_result = min;
- else
- cal_result = max;
-
- clock_ulposc_config_cali(opp, cal_result);
- if (!clock_ulposc_is_calibrated(opp))
- assert(0);
-
- return cal_result;
-}
-
-static void clock_high_enable(int osc)
-{
- /* enable high speed clock */
- SCP_CLK_ENABLE |= CLK_HIGH_EN;
-
- switch (osc) {
- case 0:
- /* after 150us, enable ULPOSC */
- clock_busy_udelay(150);
- SCP_CLK_ENABLE |= CLK_HIGH_CG;
- break;
- case 1:
- /* turn off ULPOSC2 high-core-disable switch */
- SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
- /* after 150us, turn on ULPOSC2 high core clock gate */
- clock_busy_udelay(150);
- SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG;
- clock_busy_udelay(50);
- break;
- default:
- break;
- }
-}
-
-static void clock_high_disable(int osc)
-{
- switch (osc) {
- case 0:
- SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
- clock_busy_udelay(50);
- SCP_CLK_ENABLE &= ~CLK_HIGH_EN;
- clock_busy_udelay(50);
- break;
- case 1:
- SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG;
- clock_busy_udelay(50);
- SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
- clock_busy_udelay(50);
- break;
- default:
- break;
- }
-}
-
-static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
-{
- /*
- * ULPOSC1(osc=0) is already
- * - calibrated
- * - enabled in coreboot
- * - used by pmic wrapper
- */
- if (opp->osc != 0) {
- clock_high_disable(opp->osc);
- clock_ulposc_config_default(opp);
- clock_high_enable(opp->osc);
- }
-
- /* Calibrate only if it is not accurate enough. */
- if (!clock_ulposc_is_calibrated(opp))
- opp->cali = clock_ulposc_process_cali(opp);
-
-#ifdef DEBUG
- CPRINTF("osc:%u, target=%uMHz, cal:%u\n",
- opp->osc, opp->target_mhz, opp->cali);
-#endif
-}
-
-static void clock_select_clock(enum scp_clock_source src)
-{
- /*
- * DIV2 divider takes precedence over clock selection to prevent
- * over-clocking.
- */
- if (src == SCP_CLK_ULPOSC1)
- SCP_CLK_DIV_SEL = CLK_DIV_SEL2;
-
- SCP_CLK_SW_SEL = src;
-
- if (src != SCP_CLK_ULPOSC1)
- SCP_CLK_DIV_SEL = CLK_DIV_SEL1;
-}
-
-__override void
-power_chipset_handle_host_sleep_event(enum host_sleep_event state,
- struct host_sleep_event_context *ctx)
-{
- if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
- CPRINTS("AP suspend");
- clock_select_clock(SCP_CLK_ULPOSC1);
- } else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
- CPRINTS("AP resume");
- clock_select_clock(SCP_CLK_ULPOSC2);
- }
-}
-
-void clock_init(void)
-{
- int i;
-
- /* select default 26M system clock */
- clock_select_clock(SCP_CLK_26M);
-
- /* set VREQ to HW mode */
- SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL;
- SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
- SCP_SEC_CTRL &= ~VREQ_SECURE_DIS;
-
- /* set DDREN to auto mode */
- SCP_SYS_CTRL |= AUTO_DDREN;
-
- /* set settle time */
- SCP_CLK_SYS_VAL =
- (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1);
- SCP_CLK_HIGH_VAL =
- (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1);
- SCP_SLEEP_CTRL =
- (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1);
-
- /* turn off ULPOSC2 */
- SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-
- /* calibrate ULPOSC */
- for (i = 0; i < ARRAY_SIZE(opp); ++i)
- clock_calibrate_ulposc(&opp[i]);
-
- /* select ULPOSC2 high speed CPU clock */
- clock_select_clock(SCP_CLK_ULPOSC2);
-
- /* select BCLK to use ULPOSC1 / 8 = 260MHz / 8 = 32.5MHz */
- SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8;
-
- /* enable default clock gate */
- SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
- CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
-}
-
-#ifdef DEBUG
-int command_ulposc(int argc, char *argv[])
-{
- int i;
-
- for (i = 0; i <= 1; ++i)
- ccprintf("ULPOSC%u frequency: %u kHz\n",
- i + 1,
- clock_ulposc_measure_freq(i) * 26 * 1000 / 1024);
-
- return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]",
- "Measure ULPOSC frequency");
-#endif
diff --git a/chip/mt_scp/mt8192/clock_regs.h b/chip/mt_scp/mt8192/clock_regs.h
deleted file mode 100644
index 5928ca0473..0000000000
--- a/chip/mt_scp/mt8192/clock_regs.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP clock module registers */
-
-#ifndef __CROS_EC_CLOCK_REGS_H
-#define __CROS_EC_CLOCK_REGS_H
-
-/* clock source select */
-#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000)
-#define CLK_SW_SEL_26M 0
-#define CLK_SW_SEL_32K 1
-#define CLK_SW_SEL_ULPOSC2 2
-#define CLK_SW_SEL_ULPOSC1 3
-#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004)
-#define CLK_HIGH_EN BIT(1) /* ULPOSC */
-#define CLK_HIGH_CG BIT(2)
-/* clock general control */
-#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C)
-#define VREQ_PMIC_WRAP_SEL (0x2)
-
-/* TOPCK clk */
-#define TOPCK_BASE AP_REG_BASE
-#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140)
-#define MISC_METER_DIVISOR_MASK 0xff000000
-#define MISC_METER_DIV_1 0
-/* OSC meter */
-#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C)
-#define DBG_MODE_MASK 3
-#define DBG_MODE_SET_CLOCK 0
-#define DBG_BIST_SOURCE_MASK (0x3f << 16)
-#define DBG_BIST_SOURCE_ULPOSC1 (0x25 << 16)
-#define DBG_BIST_SOURCE_ULPOSC2 (0x24 << 16)
-#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220)
-#define CFG_FREQ_METER_RUN BIT(4)
-#define CFG_FREQ_METER_ENABLE BIT(12)
-#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224)
-#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF)
-/*
- * ULPOSC
- * osc: 0 for ULPOSC1, 1 for ULPOSC2.
- */
-#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0)
-#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4)
-#define AP_ULPOSC_CON2_BASE (AP_REG_BASE + 0xC2B8)
-#define AP_ULPOSC_CON0(osc) \
- REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON1(osc) \
- REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON2(osc) \
- REG32(AP_ULPOSC_CON2_BASE + (osc) * 0x10)
-/*
- * AP_ULPOSC_CON0
- * bit0-6: calibration
- * bit7-13: iband
- * bit14-17: fband
- * bit18-23: div
- * bit24: cp_en
- * bit25-31: reserved
- */
-#define OSC_CALI_MASK 0x7f
-#define OSC_IBAND_SHIFT 7
-#define OSC_FBAND_SHIFT 14
-#define OSC_DIV_SHIFT 18
-#define OSC_CP_EN BIT(24)
-/* AP_ULPOSC_CON1
- * bit0-7: 32K calibration
- * bit 8-15: rsv1
- * bit 16-23: rsv2
- * bit 24-25: mod
- * bit26: div2_en
- * bit27-31: reserved
- */
-#define OSC_RSV1_SHIFT 8
-#define OSC_RSV2_SHIFT 16
-#define OSC_MOD_SHIFT 24
-#define OSC_DIV2_EN BIT(26)
-/* AP_ULPOSC_CON2
- * bit0-7: bias
- * bit8-31: reserved
- */
-
-#endif /* __CROS_EC_CLOCK_REGS_H */
diff --git a/chip/mt_scp/mt8192/intc.h b/chip/mt_scp/mt8192/intc.h
deleted file mode 100644
index 63eb1243b3..0000000000
--- a/chip/mt_scp/mt8192/intc.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INTC_H
-#define __CROS_EC_INTC_H
-
-/* INTC */
-#define SCP_INTC_IRQ_POL0 0xef001f20
-#define SCP_INTC_IRQ_POL1 0x0800001d
-#define SCP_INTC_IRQ_POL2 0x00000020
-#define SCP_INTC_GRP_LEN 3
-#define SCP_INTC_IRQ_COUNT 96
-
-/* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0 0
-#define SCP_IRQ_GIPC_IN1 1
-#define SCP_IRQ_GIPC_IN2 2
-#define SCP_IRQ_GIPC_IN3 3
-/* 4 */
-#define SCP_IRQ_SPM 4
-#define SCP_IRQ_AP_CIRQ 5
-#define SCP_IRQ_EINT 6
-#define SCP_IRQ_PMIC 7
-/* 8 */
-#define SCP_IRQ_UART0_TX 8
-#define SCP_IRQ_UART1_TX 9
-#define SCP_IRQ_I2C0 10
-#define SCP_IRQ_I2C1_0 11
-/* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER 12
-#define SCP_IRQ_CLK_CTRL 13
-#define SCP_IRQ_VOW 14
-#define SCP_IRQ_TIMER0 15
-/* 16 */
-#define SCP_IRQ_TIMER1 16
-#define SCP_IRQ_TIMER2 17
-#define SCP_IRQ_TIMER3 18
-#define SCP_IRQ_TIMER4 19
-/* 20 */
-#define SCP_IRQ_TIMER5 20
-#define SCP_IRQ_OS_TIMER 21
-#define SCP_IRQ_UART0_RX 22
-#define SCP_IRQ_UART1_RX 23
-/* 24 */
-#define SCP_IRQ_GDMA 24
-#define SCP_IRQ_AUDIO 25
-#define SCP_IRQ_MD_DSP 26
-#define SCP_IRQ_ADSP 27
-/* 28 */
-#define SCP_IRQ_CPU_TICK 28
-#define SCP_IRQ_SPI0 29
-#define SCP_IRQ_SPI1 30
-#define SCP_IRQ_SPI2 31
-/* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32
-#define SCP_IRQ_DBG 33
-#define SCP_IRQ_CCIF0 34
-#define SCP_IRQ_CCIF1 35
-/* 36 */
-#define SCP_IRQ_CCIF2 36
-#define SCP_IRQ_WDT 37
-#define SCP_IRQ_USB0 38
-#define SCP_IRQ_USB1 39
-/* 40 */
-#define SCP_IRQ_DPMAIF 40
-#define SCP_IRQ_INFRA 41
-#define SCP_IRQ_CLK_CTRL_CORE 42
-#define SCP_IRQ_CLK_CTRL2_CORE 43
-/* 44 */
-#define SCP_IRQ_CLK_CTRL2 44
-#define SCP_IRQ_GIPC_IN4 45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT 46
-#define SCP_IRQ_INFRABUS_TIMEOUT 47
-/* 48 */
-#define SCP_IRQ_MET0 48
-#define SCP_IRQ_MET1 49
-#define SCP_IRQ_MET2 50
-#define SCP_IRQ_MET3 51
-/* 52 */
-#define SCP_IRQ_AP_WDT 52
-#define SCP_IRQ_L2TCM_SEC_VIO 53
-#define SCP_IRQ_CPU_TICK1 54
-#define SCP_IRQ_MAD_DATAIN 55
-/* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE 56
-#define SCP_IRQ_I3C1_IBI_WAKE 57
-#define SCP_IRQ_I3C2_IBI_WAKE 58
-#define SCP_IRQ_APU_ENGINE 59
-/* 60 */
-#define SCP_IRQ_MBOX0 60
-#define SCP_IRQ_MBOX1 61
-#define SCP_IRQ_MBOX2 62
-#define SCP_IRQ_MBOX3 63
-/* 64 */
-#define SCP_IRQ_MBOX4 64
-#define SCP_IRQ_SYS_CLK_REQ 65
-#define SCP_IRQ_BUS_REQ 66
-#define SCP_IRQ_APSRC_REQ 67
-/* 68 */
-#define SCP_IRQ_APU_MBOX 68
-#define SCP_IRQ_DEVAPC_SECURE_VIO 69
-/* 72 */
-/* 76 */
-#define SCP_IRQ_I2C1_2 78
-#define SCP_IRQ_I2C2 79
-/* 80 */
-#define SCP_IRQ_AUD2AUDIODSP 80
-#define SCP_IRQ_AUD2AUDIODSP_2 81
-#define SCP_IRQ_CONN2ADSP_A2DPOL 82
-#define SCP_IRQ_CONN2ADSP_BTCVSD 83
-/* 84 */
-#define SCP_IRQ_CONN2ADSP_BLEISO 84
-#define SCP_IRQ_PCIE2ADSP 85
-#define SCP_IRQ_APU2ADSP_ENGINE 86
-#define SCP_IRQ_APU2ADSP_MBOX 87
-/* 88 */
-#define SCP_IRQ_CCIF3 88
-#define SCP_IRQ_I2C_DMA0 89
-#define SCP_IRQ_I2C_DMA1 90
-#define SCP_IRQ_I2C_DMA2 91
-/* 92 */
-#define SCP_IRQ_I2C_DMA3 92
-
-#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8192/uart.c b/chip/mt_scp/mt8192/uart.c
deleted file mode 100644
index 0ebb93cbb4..0000000000
--- a/chip/mt_scp/mt8192/uart.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module for MT8192 specific */
-
-#include "uart_regs.h"
-
-/*
- * UARTN == 0, SCP UART0
- * UARTN == 1, SCP UART1
- * UARTN == 2, AP UART1
- */
-#define UARTN CONFIG_UART_CONSOLE
-
-void uart_init_pinmux(void)
-{
-#if UARTN == 0
- SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
- SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
- /* set AP GPIO164 and GPIO165 to alt func 3 */
- AP_GPIO_MODE20_CLR = 0x00770000;
- AP_GPIO_MODE20_SET = 0x00330000;
-#elif UARTN == 1
- SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
- SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST;
-#endif
-}
diff --git a/chip/mt_scp/mt8192/video.c b/chip/mt_scp/mt8192/video.c
deleted file mode 100644
index 2f9b9a7808..0000000000
--- a/chip/mt_scp/mt8192/video.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "video.h"
-
-uint32_t video_get_enc_capability(void)
-{
- return VENC_CAP_4K;
-}
-
-uint32_t video_get_dec_capability(void)
-{
- return VDEC_CAP_4K_DISABLED | VDEC_CAP_MM21 |
- VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME |
- VDEC_CAP_VP9_FRAME;
-}
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