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-rw-r--r--chip/mt_scp/mt8195/build.mk10
-rw-r--r--chip/mt_scp/mt8195/clock.c441
-rw-r--r--chip/mt_scp/mt8195/clock_regs.h92
-rw-r--r--chip/mt_scp/mt8195/intc.h166
-rw-r--r--chip/mt_scp/mt8195/uart.c27
-rw-r--r--chip/mt_scp/mt8195/video.c19
6 files changed, 0 insertions, 755 deletions
diff --git a/chip/mt_scp/mt8195/build.mk b/chip/mt_scp/mt8195/build.mk
deleted file mode 100644
index c81bd83595..0000000000
--- a/chip/mt_scp/mt8195/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Required chip modules
-chip-y+=$(CHIP_VARIANT)/uart.o
-chip-y+=$(CHIP_VARIANT)/clock.o
-chip-y+=$(CHIP_VARIANT)/video.o
-
diff --git a/chip/mt_scp/mt8195/clock.c b/chip/mt_scp/mt8195/clock.c
deleted file mode 100644
index c6bf3cbc79..0000000000
--- a/chip/mt_scp/mt8195/clock.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include <assert.h>
-#include <string.h>
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "csr.h"
-#include "ec_commands.h"
-#include "power.h"
-#include "registers.h"
-#include "timer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
-
-enum scp_clock_source {
- SCP_CLK_SYSTEM,
- SCP_CLK_32K,
- SCP_CLK_ULPOSC1,
- SCP_CLK_ULPOSC2_LOW_SPEED,
- SCP_CLK_ULPOSC2_HIGH_SPEED,
-};
-
-enum {
- OPP_ULPOSC2_LOW_SPEED,
- OPP_ULPOSC2_HIGH_SPEED,
-};
-
-static struct opp_ulposc_cfg {
- uint32_t osc;
- uint32_t div;
- uint32_t fband;
- uint32_t mod;
- uint32_t cali;
- uint32_t target_mhz;
- uint32_t clk_div;
-} opp[] = {
- [OPP_ULPOSC2_LOW_SPEED] = {
- .osc = 1, .target_mhz = 326, .clk_div = CLK_DIV_SEL2, .div = 19,
- .fband = 10, .mod = 0, .cali = 64, /* 326MHz / 2 = 163MHz */
- },
- [OPP_ULPOSC2_HIGH_SPEED] = {
- .osc = 1, .target_mhz = 360, .clk_div = CLK_DIV_SEL1, .div = 21,
- .fband = 10, .mod = 0, .cali = 64, /* 360MHz / 1 = 360MHz */
- },
-};
-
-static inline void clock_busy_udelay(int usec)
-{
- /*
- * Delaying by busy-looping, for place that can't use udelay because of
- * the clock not configured yet. The value 28 is chosen approximately
- * from experiment.
- *
- * `volatile' in order to avoid compiler to optimize the function out
- * (otherwise, the function will be eliminated).
- */
- volatile int i = usec * 28;
-
- while (--i)
- ;
-}
-
-static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
-{
- uint32_t val = 0;
-
- /* set mod, div2_en = 0, cp_en = 0 */
- val |= opp->mod << OSC_MOD_SHIFT;
- /* set div */
- val |= opp->div << OSC_DIV_SHIFT;
- /* set F-band, I-band = 82 */
- val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT);
- /* set calibration */
- val |= opp->cali;
- /* set control register 0 */
- AP_ULPOSC_CON0(opp->osc) = val;
-
- clock_busy_udelay(50);
-
- /* bias = 65 */
- val = 65 << OSC_BIAS_SHIFT;
- /* rsv2 = 0, rsv1 = 41, cali_32k = 0 */
- val |= 41 << OSC_RSV1_SHIFT;
- /* set control register 1 */
- AP_ULPOSC_CON1(opp->osc) = val;
-
- /* set settle time */
- SCP_CLK_HIGH_VAL =
- (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(2);
-}
-
-static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
- uint32_t cali_val)
-{
- uint32_t val;
-
- val = AP_ULPOSC_CON0(opp->osc);
- val &= ~OSC_CALI_MASK;
- val |= cali_val;
- AP_ULPOSC_CON0(opp->osc) = val;
- opp->cali = cali_val;
-
- clock_busy_udelay(50);
-}
-
-static uint32_t clock_ulposc_measure_freq(uint32_t osc)
-{
- uint32_t result = 0;
- int cnt;
- uint32_t cali_0 = AP_CLK26CALI_0;
- uint32_t cali_1 = AP_CLK26CALI_1;
- uint32_t dbg_cfg = AP_CLK_DBG_CFG;
- uint32_t misc_cfg = AP_CLK_MISC_CFG_0;
-
- /* Set ckgen_load_cnt: CLK26CALI_1[25:16] */
- AP_CLK26CALI_1 = CFG_CKGEN_LOAD_CNT;
-
- /* before select meter clock input, bit[1:0] = b00 */
- AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
- DBG_MODE_SET_CLOCK;
-
- /* select monclk_ext2fqmtr_sel: AP_CLK_DBG_CFG[14:8] */
- AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
- (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
- DBG_BIST_SOURCE_ULPOSC2);
-
- /* set meter divisor to 1, bit[31:24] = b00000000 */
- AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
- MISC_METER_DIV_1;
-
- /* enable frequency meter, without start */
- AP_CLK26CALI_0 |= CFG_FREQ_METER_ENABLE;
-
- /* trigger frequency meter start */
- AP_CLK26CALI_0 |= CFG_FREQ_METER_RUN;
-
- clock_busy_udelay(45);
-
- for (cnt = 10000; cnt > 0; --cnt) {
- clock_busy_udelay(10);
- if (!(AP_CLK26CALI_0 & CFG_FREQ_METER_RUN)) {
- result = CFG_FREQ_COUNTER(AP_CLK26CALI_1);
- break;
- }
- }
-
- AP_CLK26CALI_0 = cali_0;
- AP_CLK26CALI_1 = cali_1;
- AP_CLK_DBG_CFG = dbg_cfg;
- AP_CLK_MISC_CFG_0 = misc_cfg;
-
- /* disable freq meter */
- AP_CLK26CALI_0 &= ~CFG_FREQ_METER_ENABLE;
-
- return result;
-}
-
-#define CAL_MIS_RATE 40
-static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
-{
- uint32_t curr, target;
-
- curr = clock_ulposc_measure_freq(opp->osc);
- target = opp->target_mhz * 512 / 26;
-
-#ifdef DEBUG
- CPRINTF("osc:%u, target=%uMHz, curr=%uMHz, cali:%u\n",
- opp->osc, opp->target_mhz, (curr * 26) / 512, opp->cali);
-#endif
-
- /* check if calibrated value is in the range of target value +- 4% */
- if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
- curr < (target * (1000 + CAL_MIS_RATE) / 1000))
- return 1;
- else
- return 0;
-}
-
-static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
-{
- uint32_t current_val = 0;
- uint32_t target_val = opp->target_mhz * 512 / 26;
- uint32_t middle, min = 0, max = OSC_CALI_MASK;
- uint32_t diff_by_min, diff_by_max, cal_result;
-
- do {
- middle = (min + max) / 2;
- if (middle == min)
- break;
-
- clock_ulposc_config_cali(opp, middle);
- current_val = clock_ulposc_measure_freq(opp->osc);
-
- if (current_val > target_val)
- max = middle;
- else
- min = middle;
- } while (min <= max);
-
- clock_ulposc_config_cali(opp, min);
- current_val = clock_ulposc_measure_freq(opp->osc);
- if (current_val > target_val)
- diff_by_min = current_val - target_val;
- else
- diff_by_min = target_val - current_val;
-
- clock_ulposc_config_cali(opp, max);
- current_val = clock_ulposc_measure_freq(opp->osc);
- if (current_val > target_val)
- diff_by_max = current_val - target_val;
- else
- diff_by_max = target_val - current_val;
-
- if (diff_by_min < diff_by_max)
- cal_result = min;
- else
- cal_result = max;
-
- clock_ulposc_config_cali(opp, cal_result);
- if (!clock_ulposc_is_calibrated(opp))
- assert(0);
-
- return cal_result;
-}
-
-static void clock_high_enable(int osc)
-{
- /* enable high speed clock */
- SCP_CLK_ENABLE |= CLK_HIGH_EN;
-
- switch (osc) {
- case 0:
- /* after 150us, enable ULPOSC */
- clock_busy_udelay(150);
- SCP_CLK_ENABLE |= CLK_HIGH_CG | CLK_HIGH_EN;
-
- /* topck ulposc1 clk gating off */
- AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CK;
- /* select topck ulposc1 as scp clk parent */
- AP_CLK_CFG_29_CLR = ULPOSC1_CLK_SEL;
-
- AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE;
- clock_busy_udelay(50);
- break;
- case 1:
- /* turn off ULPOSC2 high-core-disable switch */
- SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
- /* after 150us, scp requests ULPOSC2 high core clock */
- clock_busy_udelay(150);
- SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG;
- SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
- clock_busy_udelay(50);
-
- /* topck ulposc2 clk gating off */
- AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CORE_CK;
- /* select topck ulposc2 as scp clk parent */
- AP_CLK_CFG_29_CLR = ULPOSC2_CLK_SEL;
-
- AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE;
- clock_busy_udelay(50);
- break;
- default:
- break;
- }
-}
-
-static void clock_high_disable(int osc)
-{
- switch (osc) {
- case 0:
- /* topck ulposc1 clk gating on */
- AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CK;
- AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE;
- clock_busy_udelay(50);
-
- /* scp doesn't request ulposc1 clk */
- SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
- clock_busy_udelay(50);
- SCP_CLK_ENABLE &= ~CLK_HIGH_EN;
- clock_busy_udelay(50);
- break;
- case 1:
- /* topck ulposc2 clk gating on */
- AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CORE_CK;
- AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE;
- clock_busy_udelay(50);
-
- /* scp doesn't request ulposc2 clk */
- SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG;
- clock_busy_udelay(50);
- SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
- clock_busy_udelay(50);
- break;
- default:
- break;
- }
-}
-
-static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
-{
- /*
- * ULPOSC1(osc=0) is already
- * - calibrated
- * - enabled in coreboot
- * - used by pmic wrapper
- */
- if (opp->osc != 0) {
- clock_high_disable(opp->osc);
- clock_ulposc_config_default(opp);
- clock_high_enable(opp->osc);
- }
-
- /* Calibrate only if it is not accurate enough. */
- if (!clock_ulposc_is_calibrated(opp))
- opp->cali = clock_ulposc_process_cali(opp);
-}
-
-static void clock_select_clock(enum scp_clock_source src)
-{
- uint32_t sel;
- uint32_t div;
-
- switch (src) {
- case SCP_CLK_SYSTEM:
- div = CLK_DIV_SEL1;
- sel = CLK_SW_SEL_SYSTEM;
- break;
- case SCP_CLK_32K:
- div = CLK_DIV_SEL1;
- sel = CLK_SW_SEL_32K;
- break;
- case SCP_CLK_ULPOSC1:
- div = CLK_DIV_SEL1;
- sel = CLK_SW_SEL_ULPOSC1;
- break;
- case SCP_CLK_ULPOSC2_LOW_SPEED:
- /* parking at scp system clk until ulposc clk is ready */
- clock_select_clock(SCP_CLK_SYSTEM);
-
- clock_ulposc_config_cali(&opp[OPP_ULPOSC2_LOW_SPEED],
- opp[OPP_ULPOSC2_LOW_SPEED].cali);
- div = opp[OPP_ULPOSC2_LOW_SPEED].clk_div;
-
- sel = CLK_SW_SEL_ULPOSC2;
- break;
- case SCP_CLK_ULPOSC2_HIGH_SPEED:
- /* parking at scp system clk until ulposc clk is ready */
- clock_select_clock(SCP_CLK_SYSTEM);
-
- clock_ulposc_config_cali(&opp[OPP_ULPOSC2_HIGH_SPEED],
- opp[OPP_ULPOSC2_HIGH_SPEED].cali);
- div = opp[OPP_ULPOSC2_HIGH_SPEED].clk_div;
-
- sel = CLK_SW_SEL_ULPOSC2;
- break;
- default:
- div = CLK_DIV_SEL1;
- sel = CLK_SW_SEL_SYSTEM;
- break;
- }
-
- SCP_CLK_DIV_SEL = div;
- SCP_CLK_SW_SEL = sel;
-}
-
-__override void
-power_chipset_handle_host_sleep_event(enum host_sleep_event state,
- struct host_sleep_event_context *ctx)
-{
- if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
- CPRINTS("AP suspend");
- clock_select_clock(SCP_CLK_32K);
- } else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
- CPRINTS("AP resume");
- clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED);
- }
-}
-
-void clock_init(void)
-{
- uint32_t i;
-
- /* select scp system clock (default 26MHz) */
- clock_select_clock(SCP_CLK_SYSTEM);
-
- /* set VREQ to HW mode */
- SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL;
- SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
- SCP_SEC_CTRL &= ~VREQ_SECURE_DIS;
-
- /* set DDREN to auto mode */
- SCP_SYS_CTRL |= AUTO_DDREN;
-
- /* set settle time */
- SCP_CLK_SYS_VAL =
- (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1);
- SCP_CLK_HIGH_VAL =
- (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1);
- SCP_SLEEP_CTRL =
- (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1);
-
- /* turn off ULPOSC2 */
- SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-
- /* calibrate ULPOSC2 */
- for (i = 0; i < ARRAY_SIZE(opp); ++i)
- clock_calibrate_ulposc(&opp[i]);
-
- /* select ULPOSC2 high speed SCP clock */
- clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED);
-
- /* select BCLK to use ULPOSC / 8 */
- SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8;
-
- /* enable default clock gate */
- SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
- CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
-}
-
-#ifdef DEBUG
-int command_ulposc(int argc, char *argv[])
-{
- uint32_t osc;
-
- for (osc = 0; osc <= OPP_ULPOSC2_HIGH_SPEED; ++osc)
- ccprintf("ULPOSC%u frequency: %u kHz\n", osc + 1,
- clock_ulposc_measure_freq(osc) * 26 * 1000 / 512);
-
- return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]",
- "Measure ULPOSC frequency");
-#endif
diff --git a/chip/mt_scp/mt8195/clock_regs.h b/chip/mt_scp/mt8195/clock_regs.h
deleted file mode 100644
index 6e7ec6bdbb..0000000000
--- a/chip/mt_scp/mt8195/clock_regs.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP clock module registers */
-
-#ifndef __CROS_EC_CLOCK_REGS_H
-#define __CROS_EC_CLOCK_REGS_H
-
-/* clock source select */
-#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000)
-#define CLK_SW_SEL_SYSTEM 0
-#define CLK_SW_SEL_32K 1
-#define CLK_SW_SEL_ULPOSC2 2
-#define CLK_SW_SEL_ULPOSC1 3
-#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004)
-#define CLK_HIGH_EN BIT(1) /* ULPOSC */
-#define CLK_HIGH_CG BIT(2)
-/* clock general control */
-#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C)
-#define VREQ_PMIC_WRAP_SEL (0x3)
-
-/* TOPCK clk */
-#define TOPCK_BASE AP_REG_BASE
-#define AP_CLK_CFG_UPDATE3 REG32(TOPCK_BASE + 0x0010)
-#define F_ULPOSC_CK_UPDATE BIT(21)
-#define F_ULPOSC_CORE_CK_UPDATE BIT(22)
-#define AP_CLK_CFG_29_SET REG32(TOPCK_BASE + 0x0180)
-#define AP_CLK_CFG_29_CLR REG32(TOPCK_BASE + 0x0184)
-#define ULPOSC1_CLK_SEL (0x3 << 8)
-#define PDN_F_ULPOSC_CK BIT(15)
-#define ULPOSC2_CLK_SEL (0x3 << 16)
-#define PDN_F_ULPOSC_CORE_CK BIT(23)
-/* OSC meter */
-#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x020C)
-#define DBG_MODE_MASK 3
-#define DBG_MODE_SET_CLOCK 0
-#define DBG_BIST_SOURCE_MASK (0x7f << 8)
-#define DBG_BIST_SOURCE_ULPOSC1 (0x30 << 8)
-#define DBG_BIST_SOURCE_ULPOSC2 (0x32 << 8)
-#define AP_CLK26CALI_0 REG32(TOPCK_BASE + 0x0218)
-#define CFG_FREQ_METER_RUN BIT(4)
-#define CFG_FREQ_METER_ENABLE BIT(7)
-#define AP_CLK26CALI_1 REG32(TOPCK_BASE + 0x021C)
-#define CFG_CKGEN_LOAD_CNT 0x01ff0000
-#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF)
-#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x022C)
-#define MISC_METER_DIVISOR_MASK 0xff000000
-#define MISC_METER_DIV_1 0
-/*
- * ULPOSC
- * osc: 0 for ULPOSC1, 1 for ULPOSC2.
- */
-#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0)
-#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4)
-#define AP_ULPOSC_CON0(osc) \
- REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON1(osc) \
- REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10)
-/*
- * AP_ULPOSC_CON0
- * bit0-6: calibration
- * bit7-13: iband
- * bit14-17: fband
- * bit18-23: div
- * bit24: cp_en
- * bit25-26: mod
- * bit27: div2_en
- * bit28-31: reserved
- */
-#define OSC_CALI_SHIFT 0
-#define OSC_CALI_MASK 0x7f
-#define OSC_IBAND_SHIFT 7
-#define OSC_FBAND_SHIFT 14
-#define OSC_DIV_SHIFT 18
-#define OSC_CP_EN BIT(24)
-#define OSC_MOD_SHIFT 25
-#define OSC_DIV2_EN BIT(27)
-/*
- * AP_ULPOSC_CON1
- * bit0-7: rsv1
- * bit8-15: rsv2
- * bit16-23: 32K calibration
- * bit24-31: bias
- */
-#define OSC_RSV1_SHIFT 0
-#define OSC_RSV2_SHIFT 8
-#define OSC_32KCALI_SHIFT 16
-#define OSC_BIAS_SHIFT 24
-
-#endif /* __CROS_EC_CLOCK_REGS_H */
diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h
deleted file mode 100644
index 87181c46ca..0000000000
--- a/chip/mt_scp/mt8195/intc.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INTC_H
-#define __CROS_EC_INTC_H
-
-/* INTC */
-#define SCP_INTC_IRQ_POL0 0xef001f20
-#define SCP_INTC_IRQ_POL1 0x044001dd
-#define SCP_INTC_IRQ_POL2 0xffffdfe0
-#define SCP_INTC_IRQ_POL3 0xfffffff3
-#define SCP_INTC_GRP_LEN 4
-#define SCP_INTC_IRQ_COUNT 127
-
-/* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0 0
-#define SCP_IRQ_GIPC_IN1 1
-#define SCP_IRQ_GIPC_IN2 2
-#define SCP_IRQ_GIPC_IN3 3
-/* 4 */
-#define SCP_IRQ_SPM 4
-#define SCP_IRQ_AP_CIRQ 5
-#define SCP_IRQ_EINT 6
-#define SCP_IRQ_PMIC 7
-/* 8 */
-#define SCP_IRQ_UART0_TX 8
-#define SCP_IRQ_UART1_TX 9
-#define SCP_IRQ_I2C0 10
-#define SCP_IRQ_I2C1_0 11
-/* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER 12
-#define SCP_IRQ_CLK_CTRL 13
-#define SCP_IRQ_VOW 14
-#define SCP_IRQ_TIMER0 15
-/* 16 */
-#define SCP_IRQ_TIMER1 16
-#define SCP_IRQ_TIMER2 17
-#define SCP_IRQ_TIMER3 18
-#define SCP_IRQ_TIMER4 19
-/* 20 */
-#define SCP_IRQ_TIMER5 20
-#define SCP_IRQ_OS_TIMER 21
-#define SCP_IRQ_UART0_RX 22
-#define SCP_IRQ_UART1_RX 23
-/* 24 */
-#define SCP_IRQ_GDMA 24
-#define SCP_IRQ_AUDIO 25
-#define SCP_IRQ_MD_DSP 26
-#define SCP_IRQ_ADSP 27
-/* 28 */
-#define SCP_IRQ_CPU_TICK 28
-#define SCP_IRQ_SPI0 29
-#define SCP_IRQ_SPI1 30
-#define SCP_IRQ_SPI2 31
-/* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32
-#define SCP_IRQ_DBG 33
-#define SCP_IRQ_GCE 34
-#define SCP_IRQ_MDP_GCE 35
-/* 36 */
-#define SCP_IRQ_VDEC 36
-#define SCP_IRQ_WDT 37
-#define SCP_IRQ_VDEC_LAT 38
-#define SCP_IRQ_VDEC1 39
-/* 40 */
-#define SCP_IRQ_VDEC1_LAT 40
-#define SCP_IRQ_INFRA 41
-#define SCP_IRQ_CLK_CTRL_CORE 42
-#define SCP_IRQ_CLK_CTRL2_CORE 43
-/* 44 */
-#define SCP_IRQ_CLK_CTRL2 44
-#define SCP_IRQ_GIPC_IN4 45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT 46
-#define SCP_IRQ_INFRABUS_TIMEOUT 47
-/* 48 */
-#define SCP_IRQ_MET0 48
-#define SCP_IRQ_MET1 49
-#define SCP_IRQ_MET2 50
-#define SCP_IRQ_MET3 51
-/* 52 */
-#define SCP_IRQ_AP_WDT 52
-#define SCP_IRQ_L2TCM_SEC_VIO 53
-#define SCP_IRQ_VDEC_INT_LINE_CNT 54
-#define SCP_IRQ_VOW_DATAIN 55
-/* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE 56
-#define SCP_IRQ_I3C1_IBI_WAKE 57
-#define SCP_IRQ_VENC 58
-#define SCP_IRQ_APU_ENGINE 59
-/* 60 */
-#define SCP_IRQ_MBOX0 60
-#define SCP_IRQ_MBOX1 61
-#define SCP_IRQ_MBOX2 62
-#define SCP_IRQ_MBOX3 63
-/* 64 */
-#define SCP_IRQ_MBOX4 64
-#define SCP_IRQ_SYS_CLK_REQ 65
-#define SCP_IRQ_BUS_REQ 66
-#define SCP_IRQ_APSRC_REQ 67
-/* 68 */
-#define SCP_IRQ_APU_MBOX 68
-#define SCP_IRQ_DEVAPC_SECURE_VIO 69
-#define SCP_IRQ_CAMSYS_29 70
-#define SCP_IRQ_CAMSYS_28 71
-/* 72 */
-#define SCP_IRQ_CAMSYS_5 72
-#define SCP_IRQ_CAMSYS_4 73
-#define SCP_IRQ_CAMSYS_3 74
-#define SCP_IRQ_CAMSYS_2 75
-/* 76 */
-#define SCP_IRQ_HDMIRX_PM_DVI_SQH 76
-#define SCP_IRQ_HDMIRX_RESERVED 77
-#define SCP_IRQ_NNA0_0 78
-#define SCP_IRQ_NNA0_1 79
-/* 80 */
-#define SCP_IRQ_NNA0_2 80
-#define SCP_IRQ_NNA1_0 81
-#define SCP_IRQ_NNA1_1 82
-#define SCP_IRQ_NNA1_2 83
-/* 84 */
-#define SCP_IRQ_JPEGENC 84
-#define SCP_IRQ_JPEGDEC 85
-#define SCP_IRQ_JPEGDEC_C2 86
-#define SCP_IRQ_VENC_C1 87
-/* 88 */
-#define SCP_IRQ_JPEGENC_C1 88
-#define SCP_IRQ_JPEGDEC_C1 89
-#define SCP_IRQ_HDMITX 90
-#define SCP_IRQ_HDMI2 91
-/* 92 */
-#define SCP_IRQ_EARC 92
-#define SCP_IRQ_CEC 93
-#define SCP_IRQ_HDMI_DEV_DET 94
-#define SCP_IRQ_HDMIRX_OUT_ARM_PHY 95
-/* 96 */
-#define SCP_IRQ_I2C2 96
-#define SCP_IRQ_I2C3 97
-#define SCP_IRQ_I3C2_IBI_WAKE 98
-#define SCP_IRQ_I3C3_IBI_WAKE 99
-/* 100 */
-#define SCP_IRQ_SYS_I2C_0 100
-#define SCP_IRQ_SYS_I2C_1 101
-#define SCP_IRQ_SYS_I2C_2 102
-#define SCP_IRQ_SYS_I2C_3 103
-/* 104 */
-#define SCP_IRQ_SYS_I2C_4 104
-#define SCP_IRQ_SYS_I2C_5 105
-#define SCP_IRQ_SYS_I2C_6 106
-#define SCP_IRQ_SYS_I2C_7 107
-/* 108 */
-#define SCP_IRQ_DISP2ADSP_0 108
-#define SCP_IRQ_DISP2ADSP_1 109
-#define SCP_IRQ_DISP2ADSP_2 110
-#define SCP_IRQ_DISP2ADSP_3 111
-/* 112 */
-#define SCP_IRQ_DISP2ADSP_4 112
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_0 113
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_1 114
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_2 115
-/* 116 */
-#define SCP_IRQ_GCE1_SECURE 116
-#define SCP_IRQ_GCE_SECURE 117
-
-#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8195/uart.c b/chip/mt_scp/mt8195/uart.c
deleted file mode 100644
index 76674fa7d3..0000000000
--- a/chip/mt_scp/mt8195/uart.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module for MT8195 specific */
-
-#include "uart_regs.h"
-
-/*
- * UARTN == 0, SCP UART0
- * UARTN == 1, SCP UART1
- * UARTN == 2, AP UART1
- */
-#define UARTN CONFIG_UART_CONSOLE
-
-void uart_init_pinmux(void)
-{
-#if UARTN == 0
- SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
- SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
- /* set AP GPIO102 and GPIO103 to alt func 5 */
- AP_GPIO_MODE12_CLR = 0x77000000;
- AP_GPIO_MODE12_SET = 0x55000000;
-#endif
-}
diff --git a/chip/mt_scp/mt8195/video.c b/chip/mt_scp/mt8195/video.c
deleted file mode 100644
index dc4b7b3397..0000000000
--- a/chip/mt_scp/mt8195/video.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "video.h"
-
-uint32_t video_get_enc_capability(void)
-{
- return VENC_CAP_4K;
-}
-
-uint32_t video_get_dec_capability(void)
-{
- return VDEC_CAP_MT21C | VDEC_CAP_MM21 |
- VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME |
- VDEC_CAP_VP9_FRAME;
-}
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