diff options
Diffstat (limited to 'chip/mt_scp')
52 files changed, 0 insertions, 6942 deletions
diff --git a/chip/mt_scp/build.mk b/chip/mt_scp/build.mk deleted file mode 100644 index 3e8f63b5a2..0000000000 --- a/chip/mt_scp/build.mk +++ /dev/null @@ -1,21 +0,0 @@ -# -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# SCP specific files build -# - -# Required chip modules -chip-y= - -CPPFLAGS+=-Ichip/$(CHIP)/$(CHIP_VARIANT) -dirs-y+=chip/$(CHIP)/$(CHIP_VARIANT) -# Each chip variant can provide specific build.mk if any --include chip/$(CHIP)/$(CHIP_VARIANT)/build.mk - -ifeq ($(CHIP_VARIANT),$(filter $(CHIP_VARIANT),mt8192 mt8195)) -CPPFLAGS+=-Ichip/$(CHIP)/rv32i_common -dirs-y+=chip/$(CHIP)/rv32i_common -include chip/$(CHIP)/rv32i_common/build.mk -endif diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h deleted file mode 100644 index 112920a4c6..0000000000 --- a/chip/mt_scp/config_chip.h +++ /dev/null @@ -1,12 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifdef CHIP_VARIANT_MT8183 -#include "mt8183/config_chip.h" -#endif - -#if defined(CHIP_VARIANT_MT8192) || defined(CHIP_VARIANT_MT8195) -#include "rv32i_common/config_chip.h" -#endif diff --git a/chip/mt_scp/mt8183/audio_codec_wov.c b/chip/mt_scp/mt8183/audio_codec_wov.c deleted file mode 100644 index 0a4684f909..0000000000 --- a/chip/mt_scp/mt8183/audio_codec_wov.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "audio_codec.h" -#include "hooks.h" -#include "memmap.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* VIF FIFO irq is triggered above this level */ -#define WOV_TRIGGER_LEVEL 160 - -int audio_codec_wov_enable_notifier(void) -{ - SCP_VIF_FIFO_DATA_THRE = WOV_TRIGGER_LEVEL + 1; - SCP_VIF_FIFO_EN |= VIF_FIFO_IRQ_EN; - - task_enable_irq(SCP_IRQ_MAD_FIFO); - - return EC_SUCCESS; -} - -int audio_codec_wov_disable_notifier(void) -{ - SCP_VIF_FIFO_EN &= ~VIF_FIFO_IRQ_EN; - - task_disable_irq(SCP_IRQ_MAD_FIFO); - - return EC_SUCCESS; -} - -int audio_codec_wov_enable(void) -{ - SCP_VIF_FIFO_EN = 0; - - SCP_RXIF_CFG0 = (RXIF_CFG0_RESET_VAL & ~RXIF_RGDL2_MASK) | - RXIF_RGDL2_DMIC_16K; - SCP_RXIF_CFG1 = RXIF_CFG1_RESET_VAL; - - SCP_VIF_FIFO_EN |= VIF_FIFO_RSTN; - - return EC_SUCCESS; -} - -int audio_codec_wov_disable(void) -{ - SCP_VIF_FIFO_EN = 0; - - return EC_SUCCESS; -} - -static size_t wov_fifo_level(void) -{ - uint32_t fifo_status = SCP_VIF_FIFO_STATUS; - - if (!(fifo_status & VIF_FIFO_VALID)) - return 0; - - if (fifo_status & VIF_FIFO_FULL) - return VIF_FIFO_MAX; - - return VIF_FIFO_LEVEL(fifo_status); -} - -int32_t audio_codec_wov_read(void *buf, uint32_t count) -{ - int16_t *out = buf; - uint8_t gain = 1; - - if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN)) - audio_codec_dmic_get_gain_idx(0, &gain); - - count >>= 1; - - while (count-- && wov_fifo_level()) { - if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN)) - *out++ = audio_codec_s16_scale_and_clip( - SCP_VIF_FIFO_DATA, gain); - else - *out++ = SCP_VIF_FIFO_DATA; - } - - return (void *)out - buf; -} - -static void wov_fifo_interrupt_handler(void) -{ -#ifdef HAS_TASK_WOV - task_wake(TASK_ID_WOV); -#endif - - audio_codec_wov_disable_notifier(); - - /* Read to clear */ - SCP_VIF_FIFO_IRQ_STATUS; -} -DECLARE_IRQ(SCP_IRQ_MAD_FIFO, wov_fifo_interrupt_handler, 2); - -int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr) -{ - return memmap_ap_to_scp(ap_addr, ec_addr); -} diff --git a/chip/mt_scp/mt8183/build.mk b/chip/mt_scp/mt8183/build.mk deleted file mode 100644 index 206563a7c5..0000000000 --- a/chip/mt_scp/mt8183/build.mk +++ /dev/null @@ -1,35 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -CORE:=cortex-m -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 - -# Required chip modules -chip-y+=$(CHIP_VARIANT)/clock.o -chip-y+=$(CHIP_VARIANT)/gpio.o -chip-y+=$(CHIP_VARIANT)/memmap.o -chip-y+=$(CHIP_VARIANT)/system.o -chip-y+=$(CHIP_VARIANT)/uart.o - -# Optional chip modules -chip-$(CONFIG_AUDIO_CODEC_WOV)+=$(CHIP_VARIANT)/audio_codec_wov.o -chip-$(CONFIG_COMMON_TIMER)+=$(CHIP_VARIANT)/hrtimer.o -chip-$(CONFIG_I2C)+=$(CHIP_VARIANT)/i2c.o -chip-$(CONFIG_IPI)+=$(CHIP_VARIANT)/ipi.o $(CHIP_VARIANT)/ipi_table.o -chip-$(CONFIG_SPI)+=$(CHIP_VARIANT)/spi.o -chip-$(CONFIG_WATCHDOG)+=$(CHIP_VARIANT)/watchdog.o - -ifeq ($(CONFIG_IPI),y) -$(out)/RO/chip/$(CHIP)/$(CHIP_VARIANT)/ipi_table.o: $(out)/ipi_table_gen.inc -$(out)/RW/chip/$(CHIP)/$(CHIP_VARIANT)/ipi_table.o: $(out)/ipi_table_gen.inc -endif - -ifeq ($(CONFIG_AUDIO_CODEC_WOV),y) -HOTWORD_PRIVATE_LIB:=private/libkukui_scp_google_hotword_dsp_api.a -ifneq ($(wildcard $(HOTWORD_PRIVATE_LIB)),) -LDFLAGS_EXTRA+=$(HOTWORD_PRIVATE_LIB) -HAVE_PRIVATE_AUDIO_CODEC_WOV_LIBS:=y -endif -endif diff --git a/chip/mt_scp/mt8183/clock.c b/chip/mt_scp/mt8183/clock.c deleted file mode 100644 index 3029a00a01..0000000000 --- a/chip/mt_scp/mt8183/clock.c +++ /dev/null @@ -1,374 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks, PLL and power settings */ - -#include "clock.h" -#include "clock_chip.h" -#include "common.h" -#include "console.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) - -#define ULPOSC_DIV_MAX (1 << OSC_DIV_BITS) -#define ULPOSC_CALI_MAX (1 << OSC_CALI_BITS) - -void clock_init(void) -{ - /* Set VREQ to HW mode */ - SCP_CPU_VREQ = CPU_VREQ_HW_MODE; - SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ; - - /* Set DDREN auto mode */ - SCP_SYS_CTRL |= AUTO_DDREN; - - /* Initialize 26MHz system clock counter reset value to 1. */ - SCP_CLK_SYS_VAL = - (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1); - /* Initialize high frequency ULPOSC counter reset value to 1. */ - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1); - /* Initialize sleep mode control VREQ counter. */ - SCP_CLK_SLEEP_CTRL = - (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1); - - /* Set normal wake clock */ - SCP_WAKE_CKSW &= ~WAKE_CKSW_SEL_NORMAL_MASK; - - /* Enable fast wakeup support */ - SCP_CLK_SLEEP = 0; - SCP_CLK_ON_CTRL = (SCP_CLK_ON_CTRL & ~HIGH_FINAL_VAL_MASK) | - HIGH_FINAL_VAL_DEFAULT; - SCP_FAST_WAKE_CNT_END = - (SCP_FAST_WAKE_CNT_END & ~FAST_WAKE_CNT_END_MASK) | - FAST_WAKE_CNT_END_DEFAULT; - - /* Set slow wake clock */ - SCP_WAKE_CKSW = (SCP_WAKE_CKSW & ~WAKE_CKSW_SEL_SLOW_MASK) | - WAKE_CKSW_SEL_SLOW_DEFAULT; - - /* Select CLK_HIGH as wakeup clock */ - SCP_CLK_SLOW_SEL = (SCP_CLK_SLOW_SEL & - ~(CKSW_SEL_SLOW_MASK | CKSW_SEL_SLOW_DIV_MASK)) | - CKSW_SEL_SLOW_ULPOSC2_CLK; - - /* - * Set legacy wakeup - * - disable SPM sleep control - * - disable SCP sleep mode - */ - SCP_CLK_SLEEP_CTRL &= ~(EN_SLEEP_CTRL | SPM_SLEEP_MODE); - - task_enable_irq(SCP_IRQ_CLOCK); - task_enable_irq(SCP_IRQ_CLOCK2); -} - -static void scp_ulposc_config(int osc, uint32_t osc_div, uint32_t osc_cali) -{ - uint32_t val; - - /* Clear all bits */ - val = 0; - /* Enable CP */ - val |= OSC_CP_EN; - /* Set div */ - val |= osc_div << 17; - /* F-band = 0, I-band = 4 */ - val |= 4 << 6; - /* Set calibration */ - val |= osc_cali; - /* Set control register 1 */ - AP_ULPOSC_CON02(osc) = val; - /* Set control register 2, enable div2 */ - AP_ULPOSC_CON13(osc) |= OSC_DIV2_EN; -} - -static inline void busy_udelay(int usec) -{ - /* - * Delaying by busy-looping, for place that can't use udelay because of - * the clock not configured yet. The value 28 is chosen approximately - * from experiment. - */ - volatile int i = usec * 28; - - while (i--) - ; -} - -static unsigned int scp_measure_ulposc_freq(int osc) -{ - unsigned int result = 0; - int cnt; - - /* Before select meter clock input, bit[1:0] = b00 */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | - DBG_MODE_SET_CLOCK; - - /* Select source, bit[21:16] = clk_src */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | - (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : - DBG_BIST_SOURCE_ULPOSC2); - - /* Set meter divisor to 1, bit[31:24] = b00000000 */ - AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) | - MISC_METER_DIV_1; - - /* Enable frequency meter, without start */ - AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE; - - /* Trigger frequency meter start */ - AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN; - - /* - * Frequency meter counts cycles in 1 / (26 * 1024) second period. - * freq_in_hz = freq_counter * 26 * 1024 - * - * The hardware takes 38us to count cycles. Delay up to 100us, - * as busy_udelay may not be accurate when sysclk is not 26Mhz - * (e.g. when recalibrating/measuring after boot). - */ - for (cnt = 100; cnt; cnt--) { - busy_udelay(1); - if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) { - result = CFG_FREQ_COUNTER(AP_SCP_CFG_1); - break; - } - } - - /* Disable freq meter */ - AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE; - return result; -} - -static inline int signum(int v) -{ - return (v > 0) - (v < 0); -} - -static inline int abs(int v) -{ - return (v >= 0) ? v : -v; -} - -static int scp_ulposc_config_measure(int osc, int div, int cali) -{ - int freq; - - scp_ulposc_config(osc, div, cali); - freq = scp_measure_ulposc_freq(osc); - CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n", - osc + 1, div, cali, freq, - freq * 26 * 1000 / 1024); - - return freq; -} - -/** - * Calibrate ULPOSC to target frequency. - * - * @param osc 0:ULPOSC1, 1:ULPOSC2 - * @param target_mhz Target frequency to set - * @return Frequency counter output - * - */ -static int scp_calibrate_ulposc(int osc, int target_mhz) -{ - int target_freq = DIV_ROUND_NEAREST(target_mhz * 1024, 26); - struct ulposc { - int div; /* frequency divisor/multiplier */ - int cali; /* variable resistor calibrator */ - int freq; /* frequency counter measure result */ - } curr, prev = {0}; - enum { STAGE_DIV, STAGE_CALI } stage = STAGE_DIV; - int param, param_max; - - curr.div = ULPOSC_DIV_MAX / 2; - curr.cali = ULPOSC_CALI_MAX / 2; - - param = curr.div; - param_max = ULPOSC_DIV_MAX; - - /* - * In the loop below, linear search closest div value to get desired - * frequency counter value. Then adjust cali to get a better result. - * Note that this doesn't give optimal output frequency, but it's - * usually close enough. - * TODO(b:120176040): See if we can efficiently calibrate the clock with - * more precision by exploring more of the cali/div space. - * - * The frequency function follows. Note that f is positively correlated - * with both div and cali: - * f(div, cali) = k1 * (div + k2) / R(cali) * C - * Where: - * R(cali) = k3 / (1 + k4 * (cali - k4)) - */ - while (1) { - curr.freq = scp_ulposc_config_measure(osc, curr.div, curr.cali); - - if (!curr.freq) - return 0; - - /* - * If previous and current are on either side of the desired - * frequency, pick the closest one. - */ - if (prev.freq && signum(target_freq - curr.freq) != - signum(target_freq - prev.freq)) { - if (abs(target_freq - prev.freq) < - abs(target_freq - curr.freq)) - curr = prev; - - if (stage == STAGE_CALI) - break; - - /* Switch to optimizing cali */ - stage = STAGE_CALI; - param = curr.cali; - param_max = ULPOSC_CALI_MAX; - } - - prev = curr; - param += signum(target_freq - curr.freq); - - if (param < 0 || param >= param_max) - return 0; - - if (stage == STAGE_DIV) - curr.div = param; - else - curr.cali = param; - } - - /* - * It's possible we end up using prev, so reset the configuration and - * measure again. - */ - return scp_ulposc_config_measure(osc, curr.div, curr.cali); -} - -static void scp_clock_high_enable(int osc) -{ - /* Enable high speed clock */ - SCP_CLK_EN |= EN_CLK_HIGH; - - switch (osc) { - case 0: - /* After 25ms, enable ULPOSC */ - busy_udelay(25 * MSEC); - SCP_CLK_EN |= CG_CLK_HIGH; - break; - case 1: - /* Turn off ULPOSC2 high-core-disable switch */ - SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB; - /* After 25ms, turn on ULPOSC2 high core clock gate */ - busy_udelay(25 * MSEC); - SCP_CLK_HIGH_CORE |= CLK_HIGH_CORE_CG; - break; - default: - break; - } -} - -void scp_use_clock(enum scp_clock_source src) -{ - /* - * DIV2 divider takes precedence over clock selection to prevent - * over-clocking. - */ - if (src == SCP_CLK_ULPOSC1) - SCP_CLK_DIV_SEL = CLK_DIV2; - - SCP_CLK_SEL = src; - - if (src != SCP_CLK_ULPOSC1) - SCP_CLK_DIV_SEL = CLK_DIV1; -} - -void scp_enable_clock(void) -{ - /* Select default CPU clock */ - scp_use_clock(SCP_CLK_26M); - - /* VREQ */ - SCP_CPU_VREQ = 0x10001; - SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ; - - /* DDREN auto mode */ - SCP_SYS_CTRL |= AUTO_DDREN; - - /* Set settle time */ - SCP_CLK_SYS_VAL = 1; /* System clock */ - SCP_CLK_HIGH_VAL = 1; /* ULPOSC */ - SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | 2; - - /* Disable slow wake */ - SCP_CLK_SLEEP = SLOW_WAKE_DISABLE; - /* Disable SPM sleep control, disable sleep mode */ - SCP_CLK_SLEEP_CTRL &= ~(SPM_SLEEP_MODE | EN_SLEEP_CTRL); - - /* Turn off ULPOSC2 */ - SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB; - scp_ulposc_config(0, 12, 32); - scp_clock_high_enable(0); /* Turn on ULPOSC1 */ - scp_ulposc_config(1, 16, 32); - scp_clock_high_enable(1); /* Turn on ULPOSC2 */ - - /* Calibrate ULPOSC */ - scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ); - scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ); - - /* Select ULPOSC2 high speed CPU clock */ - scp_use_clock(SCP_CLK_ULPOSC2); - - /* Enable default clock gate */ - SCP_CLK_GATE |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 | - CG_I2C_M | CG_MAD_M | CG_AP2P_M; - - /* Select pwrap_ulposc */ - AP_CLK_CFG_5 = (AP_CLK_CFG_5 & ~PWRAP_ULPOSC_MASK) | OSC_D16; - - /* Enable pwrap_ulposc clock gate */ - AP_CLK_CFG_5_CLR = PWRAP_ULPOSC_CG; -} - -DECLARE_IRQ(SCP_IRQ_CLOCK, clock_control_irq, 3); -void clock_control_irq(void) -{ - /* Read ack CLK_IRQ */ - (SCP_CLK_IRQ_ACK); - task_clear_pending_irq(SCP_IRQ_CLOCK); -} - -DECLARE_IRQ(SCP_IRQ_CLOCK2, clock_fast_wakeup_irq, 3); -void clock_fast_wakeup_irq(void) -{ - /* Ack fast wakeup */ - SCP_SLEEP_IRQ2 = 1; - task_clear_pending_irq(SCP_IRQ_CLOCK2); -} - -/* Console command */ -int command_ulposc(int argc, char *argv[]) -{ - if (argc > 1 && !strncmp(argv[1], "cal", 3)) { - scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ); - scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ); - } - - /* SCP clock meter counts every (26MHz / 1024) tick */ - ccprintf("ULPOSC1 frequency: %u kHz\n", - scp_measure_ulposc_freq(0) * 26 * 1000 / 1024); - ccprintf("ULPOSC2 frequency: %u kHz\n", - scp_measure_ulposc_freq(1) * 26 * 1000 / 1024); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[calibrate]", - "Calibrate ULPOSC frequency"); diff --git a/chip/mt_scp/mt8183/clock_chip.h b/chip/mt_scp/mt8183/clock_chip.h deleted file mode 100644 index a16bf2e54e..0000000000 --- a/chip/mt_scp/mt8183/clock_chip.h +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks, PLL and power settings */ - -#ifndef __CROS_EC_CLOCK_CHIP_H -#define __CROS_EC_CLOCK_CHIP_H - -#include "common.h" -#include "registers.h" - -/* Default ULPOSC clock speed in MHz */ -#ifndef ULPOSC1_CLOCK_MHZ -#define ULPOSC1_CLOCK_MHZ 240 -#endif -#ifndef ULPOSC2_CLOCK_MHZ -#define ULPOSC2_CLOCK_MHZ 330 -#endif - -void scp_enable_clock(void); - -enum scp_clock_source { - SCP_CLK_26M = CLK_SEL_SYS_26M, - SCP_CLK_32K = CLK_SEL_32K, - SCP_CLK_ULPOSC2 = CLK_SEL_ULPOSC_2, - SCP_CLK_ULPOSC1 = CLK_SEL_ULPOSC_1, -}; - -/* Switches to use 'src' clock */ -void scp_use_clock(enum scp_clock_source src); - -#endif /* __CROS_EC_CLOCK_CHIP_H */ diff --git a/chip/mt_scp/mt8183/config_chip.h b/chip/mt_scp/mt8183/config_chip.h deleted file mode 100644 index e0710a908b..0000000000 --- a/chip/mt_scp/mt8183/config_chip.h +++ /dev/null @@ -1,64 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -#include "core/cortex-m/config_core.h" - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* Default to UART 2 (AP UART) for EC console */ -#define CONFIG_UART_CONSOLE 2 - -/* Number of IRQ vectors */ -#define CONFIG_IRQ_COUNT 56 - -/* - * Number of EINT can be 0 ~ 160. Change this to conditional macro - * on adding other variants. - */ -#define MAX_NUM_EINT 8 -#define MAX_EINT_PORT (MAX_NUM_EINT / 32) - -/* RW only, no flash */ -#undef CONFIG_FW_INCLUDE_RO -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE 0 -#define CONFIG_RW_MEM_OFF 0 -#define CONFIG_RW_SIZE 0x40000 /* 256KB */ -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_PROGRAM_MEMORY_BASE 0 -#define CONFIG_MAPPED_STORAGE_BASE 0 -/* Enable MPU to protect code RAM from writing, and data RAM from execution.*/ -#define CONFIG_MPU - -/* Unsupported features/commands */ -#undef CONFIG_CMD_FLASHINFO -#undef CONFIG_CMD_POWER_AP -#undef CONFIG_FLASH_CROS -#undef CONFIG_FLASH_PHYSICAL -#undef CONFIG_FMAP -#undef CONFIG_HIBERNATE - -/* Task stack size */ -#define CONFIG_STACK_SIZE 1024 -#define IDLE_TASK_STACK_SIZE 256 -#define SMALLER_TASK_STACK_SIZE 384 -#define TASK_STACK_SIZE 512 -#define LARGER_TASK_STACK_SIZE 640 -#define VENTI_TASK_STACK_SIZE 768 - -#define CONFIG_CHIP_PRE_INIT - -#define GPIO_PIN(num) ((num) / 32), ((num) % 32) -#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/mt_scp/mt8183/gpio.c b/chip/mt_scp/mt8183/gpio.c deleted file mode 100644 index a4896aae72..0000000000 --- a/chip/mt_scp/mt8183/gpio.c +++ /dev/null @@ -1,180 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module */ - -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" - -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - int bit, mode_reg_index, shift; - uint32_t mode_bits, mode_mask; - - /* Up to 8 alt functions per port */ - if (func > GPIO_ALT_FUNC_7) - return; - - if (func == GPIO_ALT_FUNC_NONE) - func = GPIO_ALT_FUNC_DEFAULT; - - while (mask) { - /* 32 gpio per port */ - bit = get_next_bit(&mask); - /* 8 gpio per mode reg */ - mode_reg_index = (port << 2) | (bit >> 3); - /* - * b[3] - write enable(?) - * b[2:0] - mode - */ - shift = (bit & 7) << 2; - mode_bits = func << shift; - mode_mask = ~(0xf << shift); - AP_GPIO_MODE(mode_reg_index) = (AP_GPIO_MODE(mode_reg_index) & - mode_mask) | mode_bits; - } -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - return !!(AP_GPIO_DIN(gpio_list[signal].port) & - gpio_list[signal].mask); -} - - -void gpio_set_level(enum gpio_signal signal, int value) -{ - if (value) - AP_GPIO_DOUT(gpio_list[signal].port) |= gpio_list[signal].mask; - else - AP_GPIO_DOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask; -} - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - /* Set input/output mode */ - if (flags & GPIO_OUTPUT) { - /* Set level before changing to output mode */ - if (flags & GPIO_HIGH) - AP_GPIO_DOUT(port) |= mask; - if (flags & GPIO_LOW) - AP_GPIO_DOUT(port) &= ~mask; - AP_GPIO_DIR(port) |= mask; - } else { - AP_GPIO_DIR(port) &= ~mask; - } - - if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH)) - SCP_EINT_POLARITY_SET[port] = mask; - - if (flags & (GPIO_INT_F_FALLING | GPIO_INT_F_LOW)) - SCP_EINT_POLARITY_CLR[port] = mask; - else - SCP_EINT_POLARITY_SET[port] = mask; - - /* Set sensitivity register on edge trigger */ - if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) - SCP_EINT_SENS_SET[port] = mask; - else - SCP_EINT_SENS_CLR[port] = mask; -} - -int gpio_get_flags_by_mask(uint32_t port, uint32_t mask) -{ - /* TODO(b/120167145): implement get flags */ - return 0; -} - -int gpio_enable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - if (signal >= GPIO_IH_COUNT || !g->mask) - return EC_ERROR_INVAL; - - SCP_EINT_MASK_CLR[g->port] = g->mask; - - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - if (signal >= GPIO_IH_COUNT || !g->mask) - return EC_ERROR_INVAL; - - SCP_EINT_MASK_SET[g->port] = g->mask; - - return EC_SUCCESS; -} - -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - if (signal >= GPIO_IH_COUNT || !g->mask) - return EC_ERROR_INVAL; - - SCP_EINT_ACK[g->port] = g->mask; - - return EC_SUCCESS; -} - -void gpio_pre_init(void) -{ - const struct gpio_info *g = gpio_list; - int i; - int is_warm = system_is_reboot_warm(); - - for (i = 0; i < GPIO_COUNT; i++, g++) { - int flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - gpio_set_flags_by_mask(g->port, g->mask, flags); - } -} - -void gpio_init(void) -{ - /* Enable EINT IRQ */ - task_enable_irq(SCP_IRQ_EINT); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -/* Interrupt handler */ -void __keep gpio_interrupt(void) -{ - int bit, port; - uint32_t pending; - enum gpio_signal signal; - - for (port = 0; port <= MAX_EINT_PORT; port++) { - pending = SCP_EINT_STATUS[port]; - - while (pending) { - bit = get_next_bit(&pending); - SCP_EINT_ACK[port] = BIT(bit); - /* Skip masked gpio */ - if (SCP_EINT_MASK_GET[port] & BIT(bit)) - continue; - /* Call handler */ - signal = port * 32 + bit; - if (signal < GPIO_IH_COUNT) - gpio_irq_handlers[signal](signal); - } - } -} -DECLARE_IRQ(SCP_IRQ_EINT, gpio_interrupt, 1); diff --git a/chip/mt_scp/mt8183/hrtimer.c b/chip/mt_scp/mt8183/hrtimer.c deleted file mode 100644 index 92887af2a7..0000000000 --- a/chip/mt_scp/mt8183/hrtimer.c +++ /dev/null @@ -1,253 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * High-res hardware timer - * - * SCP hardware 32bit count down timer can be configured to source clock from - * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a - * source, countdown mode and converts to micro second value matching common - * timer. - */ - -#include "clock.h" -#include "clock_chip.h" -#include "common.h" -#include "console.h" -#include "hooks.h" -#include "hwtimer.h" -#include "panic.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "watchdog.h" - -#define IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n) - -#define TIMER_SYSTEM 5 -#define TIMER_EVENT 3 - -/* ULPOSC1 should be a multiple of 8. */ -BUILD_ASSERT((ULPOSC1_CLOCK_MHZ % 8) == 0); -#define TIMER_CLOCK_MHZ (ULPOSC1_CLOCK_MHZ / 8) - -/* Common timer overflows at 0x100000000 micro seconds */ -#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1) - -static uint8_t sys_high; -static uint8_t event_high; - -/* Convert hardware countdown timer to 64bit countup ticks */ -static inline uint64_t timer_read_raw_system(void) -{ - uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(TIMER_SYSTEM); - uint32_t sys_high_adj = sys_high; - - /* - * If an IRQ is pending, but has not been serviced yet, adjust the - * sys_high value. - */ - if (timer_ctrl & TIMER_IRQ_STATUS) - sys_high_adj = sys_high ? (sys_high - 1) : (TIMER_CLOCK_MHZ-1); - - return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) | - SCP_TIMER_VAL(TIMER_SYSTEM)); -} - -static inline uint64_t timer_read_raw_event(void) -{ - return OVERFLOW_TICKS - (((uint64_t)event_high << 32) | - SCP_TIMER_VAL(TIMER_EVENT)); -} - -static inline void timer_set_clock(int n, uint32_t clock_source) -{ - SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) | - clock_source; -} - -static inline void timer_ack_irq(int n) -{ - SCP_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLEAR; -} - -/* Set hardware countdown value */ -static inline void timer_set_reset_value(int n, uint32_t reset_value) -{ - SCP_TIMER_RESET_VAL(n) = reset_value; -} - -static void timer_reset(int n) -{ - __hw_timer_enable_clock(n, 0); - timer_ack_irq(n); - timer_set_reset_value(n, 0xffffffff); - timer_set_clock(n, TIMER_CLK_32K); -} - -/* Reload a new 32bit countdown value */ -static void timer_reload(int n, uint32_t value) -{ - __hw_timer_enable_clock(n, 0); - timer_set_reset_value(n, value); - __hw_timer_enable_clock(n, 1); -} - -static int timer_reload_event_high(void) -{ - if (event_high) { - if (SCP_TIMER_RESET_VAL(TIMER_EVENT) == 0xffffffff) - __hw_timer_enable_clock(TIMER_EVENT, 1); - else - timer_reload(TIMER_EVENT, 0xffffffff); - event_high--; - return 1; - } - - /* Disable event timer clock when done. */ - __hw_timer_enable_clock(TIMER_EVENT, 0); - return 0; -} - -void __hw_clock_event_clear(void) -{ - __hw_timer_enable_clock(TIMER_EVENT, 0); - timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4); - event_high = 0; -} - -void __hw_clock_event_set(uint32_t deadline) -{ - uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ; - uint64_t now_raw = timer_read_raw_system(); - uint32_t event_deadline; - - if (deadline_raw > now_raw) { - deadline_raw -= now_raw; - event_deadline = (uint32_t)deadline_raw; - event_high = deadline_raw >> 32; - } else { - event_deadline = 1; - event_high = 0; - } - - if (event_deadline) - timer_reload(TIMER_EVENT, event_deadline); - else - timer_reload_event_high(); -} - -void __hw_timer_enable_clock(int n, int enable) -{ - if (enable) { - SCP_TIMER_IRQ_CTRL(n) |= 1; - SCP_TIMER_EN(n) |= 1; - } else { - SCP_TIMER_EN(n) &= ~1; - SCP_TIMER_IRQ_CTRL(n) &= ~1; - } -} - -int __hw_clock_source_init(uint32_t start_t) -{ - int t; - - /* - * TODO(b/120169529): check clock tree to see if we need to turn on - * MCLK and BCLK gate. - */ - SCP_CLK_GATE |= (CG_TIMER_M | CG_TIMER_B); - - /* Reset all timer, select 32768Hz clock source */ - for (t = 0; t < NUM_TIMERS; t++) - timer_reset(t); - - /* Enable timer IRQ wake source */ - SCP_INTC_IRQ_WAKEUP |= (1 << IRQ_TIMER(0)) | (1 << IRQ_TIMER(1)) | - (1 << IRQ_TIMER(2)) | (1 << IRQ_TIMER(3)) | - (1 << IRQ_TIMER(4)) | (1 << IRQ_TIMER(5)); - /* - * Timer configuration: - * OS TIMER - count up @ 13MHz, 64bit value with latch. - * SYS TICK - count down @ 26MHz - * EVENT TICK - count down @ 26MHz - */ - - /* Turn on OS TIMER, tick at 13MHz */ - SCP_OSTIMER_CON |= 1; - - /* System timestamp timer from BCLK (sourced from ULPOSC) */ - SCP_CLK_BCLK = CLK_BCLK_SEL_ULPOSC1_DIV8; - - timer_set_clock(TIMER_SYSTEM, TIMER_CLK_BCLK); - sys_high = TIMER_CLOCK_MHZ-1; - timer_set_reset_value(TIMER_SYSTEM, 0xffffffff); - __hw_timer_enable_clock(TIMER_SYSTEM, 1); - task_enable_irq(IRQ_TIMER(TIMER_SYSTEM)); - /* Event tick timer */ - timer_set_clock(TIMER_EVENT, TIMER_CLK_BCLK); - task_enable_irq(IRQ_TIMER(TIMER_EVENT)); - - return IRQ_TIMER(TIMER_SYSTEM); -} - -uint32_t __hw_clock_source_read(void) -{ - return timer_read_raw_system() / TIMER_CLOCK_MHZ; -} - -uint32_t __hw_clock_event_get(void) -{ - return (timer_read_raw_event() + timer_read_raw_system()) - / TIMER_CLOCK_MHZ; -} - -static void __hw_clock_source_irq(int n) -{ - uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(n); - - /* Ack if we're hardware interrupt */ - if (timer_ctrl & TIMER_IRQ_STATUS) - timer_ack_irq(n); - - switch (n) { - case TIMER_EVENT: - if (timer_ctrl & TIMER_IRQ_STATUS) { - if (timer_reload_event_high()) - return; - } - process_timers(0); - break; - case TIMER_SYSTEM: - /* If this is a hardware irq, check overflow */ - if (timer_ctrl & TIMER_IRQ_STATUS) { - if (sys_high) { - sys_high--; - process_timers(0); - } else { - /* Overflow, reload system timer */ - sys_high = TIMER_CLOCK_MHZ-1; - process_timers(1); - } - } else { - process_timers(0); - } - break; - default: - return; - } - -} - -#define DECLARE_TIMER_IRQ(n) \ - DECLARE_IRQ(IRQ_TIMER(n), __hw_clock_source_irq_##n, 2); \ - void __hw_clock_source_irq_##n(void) { __hw_clock_source_irq(n); } - -DECLARE_TIMER_IRQ(0); -DECLARE_TIMER_IRQ(1); -DECLARE_TIMER_IRQ(2); -DECLARE_TIMER_IRQ(3); -DECLARE_TIMER_IRQ(4); -DECLARE_TIMER_IRQ(5); diff --git a/chip/mt_scp/mt8183/ipi.c b/chip/mt_scp/mt8183/ipi.c deleted file mode 100644 index 8e13781db3..0000000000 --- a/chip/mt_scp/mt8183/ipi.c +++ /dev/null @@ -1,394 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Inter-Processor Communication (IPC) and Inter-Processor Interrupt (IPI) - * - * IPC is a communication bridge between AP and SCP. AP/SCP sends an IPC - * interrupt to SCP/AP to inform to collect the commmunication mesesages in the - * shared buffer. - * - * There are 4 IPCs in the current architecture, from IPC0 to IPC3. The - * priority of IPC is proportional to its IPC index. IPC3 has the highest - * priority and IPC0 has the lowest one. - * - * IPC0 may contain zero or more IPIs. Each IPI represents a task or a service, - * e.g. host command, or video encoding. IPIs are recognized by IPI ID, which - * should sync across AP and SCP. Shared buffer should designated which IPI - * ID it talks to. - * - * Currently, we don't have IPC handlers for IPC1, IPC2, and IPC3. - */ - -#include "clock_chip.h" -#include "console.h" -#include "hooks.h" -#include "host_command.h" -#include "ipi_chip.h" -#include "mkbp_event.h" -#include "power.h" -#include "system.h" -#include "task.h" -#include "util.h" -#include "hwtimer.h" - -#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args) -#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args) - -#define IPI_MAX_REQUEST_SIZE CONFIG_IPC_SHARED_OBJ_BUF_SIZE -/* Reserve 1 extra byte for HOSTCMD_TYPE and 3 bytes for padding. */ -#define IPI_MAX_RESPONSE_SIZE (CONFIG_IPC_SHARED_OBJ_BUF_SIZE - 4) -#define HOSTCMD_TYPE_HOSTCMD 1 -#define HOSTCMD_TYPE_HOSTEVENT 2 - -static volatile int16_t ipc0_enabled_count; -static struct mutex ipc0_lock; -static struct mutex ipi_lock; -/* IPC0 shared objects, including send object and receive object. */ -static struct ipc_shared_obj *const scp_send_obj = - (struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR; -static struct ipc_shared_obj *const scp_recv_obj = - (struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR + - sizeof(struct ipc_shared_obj)); -static char ipi_ready; - -#ifdef HAS_TASK_HOSTCMD -/* - * hostcmd and hostevent share the same IPI ID, and use first byte type to - * indicate its type. - */ -static struct hostcmd_data { - const uint8_t type; - /* To be compatible with CONFIG_HOSTCMD_ALIGNED */ - uint8_t response[IPI_MAX_RESPONSE_SIZE] __aligned(4); -} hc_cmd_obj = { .type = HOSTCMD_TYPE_HOSTCMD }; -BUILD_ASSERT(sizeof(struct hostcmd_data) == CONFIG_IPC_SHARED_OBJ_BUF_SIZE); - -static struct host_packet ipi_packet; -#endif - -/* Check if SCP to AP IPI is in use. */ -static inline int is_ipi_busy(void) -{ - return SCP_HOST_INT & IPC_SCP2HOST_BIT; -} - -/* If IPI is declared as a wake-up source, wake AP up. */ -static inline void try_to_wakeup_ap(int32_t id) -{ -#ifdef CONFIG_RPMSG_NAME_SERVICE - if (id == IPI_NS_SERVICE) - return; -#endif - - if (*ipi_wakeup_table[id]) - SCP_SPM_INT = SPM_INT_A2SPM; -} - -void ipi_disable_irq(int irq) -{ - /* Only support SCP_IRQ_IPC0 for now. */ - if (irq != SCP_IRQ_IPC0) - return; - - mutex_lock(&ipc0_lock); - - if ((--ipc0_enabled_count) == 0) - task_disable_irq(irq); - - mutex_unlock(&ipc0_lock); -} - -void ipi_enable_irq(int irq) -{ - /* Only support SCP_IRQ_IPC0 for now. */ - if (irq != SCP_IRQ_IPC0) - return; - - mutex_lock(&ipc0_lock); - - if ((++ipc0_enabled_count) == 1) { - int pending_ipc = SCP_GIPC_IN & SCP_GPIC_IN_CLEAR_ALL; - - task_enable_irq(irq); - - if (ipi_ready && pending_ipc) - /* - * IPC may be triggered while SCP_IRQ_IPC0 was disabled. - * AP will still updates SCP_GIPC_IN. - * Trigger the IRQ handler if it has a - * pending IPC. - */ - task_trigger_irq(irq); - } - - mutex_unlock(&ipc0_lock); -} - -__override void -power_chipset_handle_host_sleep_event(enum host_sleep_event state, - struct host_sleep_event_context *ctx) -{ - int i; - const task_id_t s3_suspend_tasks[] = { -#ifndef S3_SUSPEND_TASK_LIST -#define S3_SUSPEND_TASK_LIST -#endif -#define TASK(n, ...) TASK_ID_##n, - S3_SUSPEND_TASK_LIST - }; - - if (state == HOST_SLEEP_EVENT_S3_SUSPEND) { - ccprints("AP suspend"); - /* - * On AP suspend, Vcore is 0.6V, and we should not use ULPOSC2, - * which needs at least 0.7V. Switch to ULPOSC1 instead. - */ - scp_use_clock(SCP_CLK_ULPOSC1); - - for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i) - task_disable_task(s3_suspend_tasks[i]); - } else if (state == HOST_SLEEP_EVENT_S3_RESUME) { - ccprints("AP resume"); - /* Vcore is raised to >=0.7V, switch back to ULPSOC2 */ - scp_use_clock(SCP_CLK_ULPOSC2); - - for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i) - task_enable_task(s3_suspend_tasks[i]); - } -} - -/* Send data from SCP to AP. */ -int ipi_send(int32_t id, const void *buf, uint32_t len, int wait) -{ - if (!ipi_ready) - return EC_ERROR_BUSY; - - /* TODO(b:117917141): Remove this check completely. */ - if (in_interrupt_context()) { - CPRINTS("Err: invoke %s() in ISR CTX", __func__); - return EC_ERROR_BUSY; - } - - if (len > sizeof(scp_send_obj->buffer)) - return EC_ERROR_INVAL; - - ipi_disable_irq(SCP_IRQ_IPC0); - mutex_lock(&ipi_lock); - - /* Check if there is already an IPI pending in AP. */ - if (is_ipi_busy()) { - /* - * If the following conditions meet, - * 1) There is an IPI pending in AP. - * 2) The incoming IPI is a wakeup IPI. - * then it assumes that AP is in suspend state. - * Send a AP wakeup request to SPM. - * - * The incoming IPI will be checked if it's a wakeup source. - */ - try_to_wakeup_ap(id); - - mutex_unlock(&ipi_lock); - ipi_enable_irq(SCP_IRQ_IPC0); - CPRINTS("Err: IPI Busy, %d", id); - - return EC_ERROR_BUSY; - } - - - scp_send_obj->id = id; - scp_send_obj->len = len; - memcpy(scp_send_obj->buffer, buf, len); - - /* Send IPI to AP: interrutp AP to receive IPI messages. */ - try_to_wakeup_ap(id); - SCP_HOST_INT = IPC_SCP2HOST_BIT; - - while (wait && is_ipi_busy()) - ; - - mutex_unlock(&ipi_lock); - ipi_enable_irq(SCP_IRQ_IPC0); - - return EC_SUCCESS; -} - -static void ipi_handler(void) -{ - if (scp_recv_obj->id >= IPI_COUNT) { - CPRINTS("#ERR IPI %d", scp_recv_obj->id); - return; - } - - /* - * Only print IPI that is not host command channel, which will - * be printed by host command driver. - */ - if (scp_recv_obj->id != IPI_HOST_COMMAND) - CPRINTS("IPI %d", scp_recv_obj->id); - - /* - * Pass the buffer to handler. Each handler should be in charge of - * the buffer copying/reading before returning from handler. - */ - ipi_handler_table[scp_recv_obj->id]( - scp_recv_obj->id, scp_recv_obj->buffer, scp_recv_obj->len); -} - -void ipi_inform_ap(void) -{ - struct scp_run_t scp_run; - int ret; -#ifdef CONFIG_RPMSG_NAME_SERVICE - struct rpmsg_ns_msg ns_msg; -#endif - - scp_run.signaled = 1; - strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW), - SCP_FW_VERSION_LEN); - scp_run.dec_capability = VCODEC_CAPABILITY_4K_DISABLED; - scp_run.enc_capability = 0; - - ret = ipi_send(IPI_SCP_INIT, (void *)&scp_run, sizeof(scp_run), 1); - - if (ret) - ccprintf("Failed to send initialization IPC messages.\n"); - -#ifdef CONFIG_RPMSG_NAME_SERVICE - ns_msg.id = IPI_HOST_COMMAND; - strncpy(ns_msg.name, "cros-ec-rpmsg", RPMSG_NAME_SIZE); - ret = ipi_send(IPI_NS_SERVICE, &ns_msg, sizeof(ns_msg), 1); - if (ret) - ccprintf("Failed to announce host command channel.\n"); -#endif -} - -#ifdef HAS_TASK_HOSTCMD -#if defined(CONFIG_MKBP_USE_CUSTOM) -int mkbp_set_host_active_via_custom(int active, uint32_t *timestamp) -{ - static const uint8_t hc_evt_obj = HOSTCMD_TYPE_HOSTEVENT; - - /* This should be moved into ipi_send for more accuracy */ - if (timestamp) - *timestamp = __hw_clock_source_read(); - - if (active) - return ipi_send(IPI_HOST_COMMAND, &hc_evt_obj, - sizeof(hc_evt_obj), 1); - return EC_SUCCESS; -} -#endif - -static void ipi_send_response_packet(struct host_packet *pkt) -{ - int ret; - - ret = ipi_send(IPI_HOST_COMMAND, &hc_cmd_obj, - pkt->response_size + - offsetof(struct hostcmd_data, response), - 1); - if (ret) - CPRINTS("#ERR IPI HOSTCMD %d", ret); -} - -static void ipi_hostcmd_handler(int32_t id, void *buf, uint32_t len) -{ - uint8_t *in_msg = buf; - struct ec_host_request *r = (struct ec_host_request *)in_msg; - int i; - - if (in_msg[0] != EC_HOST_REQUEST_VERSION) { - CPRINTS("ERROR: Protocol V2 is not supported!"); - CPRINTF("in_msg=["); - for (i = 0; i < len; i++) - CPRINTF("%02x ", in_msg[i]); - CPRINTF("]\n"); - return; - } - - /* Protocol version 3 */ - - ipi_packet.send_response = ipi_send_response_packet; - - /* - * Just assign the buffer to request, host_packet_receive - * handles the buffer copy. - */ - ipi_packet.request = (void *)r; - ipi_packet.request_temp = NULL; - ipi_packet.request_max = IPI_MAX_REQUEST_SIZE; - ipi_packet.request_size = host_request_expected_size(r); - - ipi_packet.response = hc_cmd_obj.response; - /* Reserve space for the preamble and trailing byte */ - ipi_packet.response_max = IPI_MAX_RESPONSE_SIZE; - ipi_packet.response_size = 0; - - ipi_packet.driver_result = EC_RES_SUCCESS; - - host_packet_receive(&ipi_packet); -} -DECLARE_IPI(IPI_HOST_COMMAND, ipi_hostcmd_handler, 0); - -/* - * Get protocol information - */ -static enum ec_status ipi_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); - r->protocol_versions |= BIT(3); - r->max_request_packet_size = IPI_MAX_REQUEST_SIZE; - r->max_response_packet_size = IPI_MAX_RESPONSE_SIZE; - - args->response_size = sizeof(*r); - - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, ipi_get_protocol_info, - EC_VER_MASK(0)); -#endif - -static void ipi_enable_ipc0_deferred(void) -{ - /* Clear IPC0 IRQs. */ - SCP_GIPC_IN = SCP_GPIC_IN_CLEAR_ALL; - - /* All tasks are up, we can safely enable IPC0 IRQ now. */ - SCP_INTC_IRQ_ENABLE |= IPC0_IRQ_EN; - ipi_enable_irq(SCP_IRQ_IPC0); - - ipi_ready = 1; - - /* Inform AP that SCP is inited. */ - ipi_inform_ap(); - - CPRINTS("ipi init"); -} -DECLARE_DEFERRED(ipi_enable_ipc0_deferred); - -/* Initialize IPI. */ -static void ipi_init(void) -{ - /* Clear send share buffer. */ - memset(scp_send_obj, 0, sizeof(struct ipc_shared_obj)); - - /* Enable IRQ after all tasks are up. */ - hook_call_deferred(&ipi_enable_ipc0_deferred_data, 0); -} -DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(SCP_IRQ_IPC0, ipc_handler, 4); -void ipc_handler(void) -{ - /* TODO(b/117917141): We only support IPC_ID(0) for now. */ - if (SCP_GIPC_IN & SCP_GIPC_IN_CLEAR_IPCN(0)) { - ipi_handler(); - SCP_GIPC_IN &= SCP_GIPC_IN_CLEAR_IPCN(0); - } - - SCP_GIPC_IN &= (SCP_GPIC_IN_CLEAR_ALL & ~SCP_GIPC_IN_CLEAR_IPCN(0)); -} diff --git a/chip/mt_scp/mt8183/ipi_chip.h b/chip/mt_scp/mt8183/ipi_chip.h deleted file mode 100644 index 758047951f..0000000000 --- a/chip/mt_scp/mt8183/ipi_chip.h +++ /dev/null @@ -1,116 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_IPI_CHIP_H -#define __CROS_EC_IPI_CHIP_H - -#include "common.h" -#include "registers.h" - -#define IPC_MAX 1 -#define IPC_ID(n) (n) - -/* - * Length of EC version string is at most 32 byte (NULL included), which - * also aligns SCP fw_version length. - */ -#define SCP_FW_VERSION_LEN 32 - -/* - * Video decoder supported capability: - * BIT(4): 0 enable 4K - * 1 disable 4K - */ -#define VCODEC_CAPABILITY_4K_DISABLED BIT(4) - -#ifndef IPI_SCP_INIT -#error If CONFIG_IPI is enabled, IPI_SCP_INIT must be defined. -#endif - -/* - * Share buffer layout for IPI_SCP_INIT response. This structure should sync - * across kernel and EC. - */ -struct scp_run_t { - uint32_t signaled; - int8_t fw_ver[SCP_FW_VERSION_LEN]; - uint32_t dec_capability; - uint32_t enc_capability; -}; - -/* - * The layout of the IPC0 AP/SCP shared buffer. - * This should sync across kernel and EC. - */ -struct ipc_shared_obj { - /* IPI ID */ - int32_t id; - /* Length of the contents in buffer. */ - uint32_t len; - /* Shared buffer contents. */ - uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE]; -}; - -/* Send a IPI contents to AP. This shouldn't be used in ISR context. */ -int ipi_send(int32_t id, const void *buf, uint32_t len, int wait); - -/* Size of the rpmsg device name, should sync across kernel and EC. */ -#define RPMSG_NAME_SIZE 32 - -/* - * The layout of name service message. - * This should sync across kernel and EC. - */ -struct rpmsg_ns_msg { - /* Name of the corresponding rpmsg_driver. */ - char name[RPMSG_NAME_SIZE]; - /* IPC ID */ - uint32_t id; -}; - -/* - * IPC Handler. - */ -void ipc_handler(void); - -/* - * An IPC IRQ could be shared across many IPI handlers. - * Those handlers would usually operate on disabling or enabling the IPC IRQ. - * This may disorder the actual timing to on/off the IRQ when there are many - * tasks try to operate on it. As a result, any access to the SCP_IRQ_* - * should go through ipi_{en,dis}able_irq(), which support a counter to - * enable/disable the IRQ at correct timeing. - */ -/* Disable IPI IRQ. */ -void ipi_disable_irq(int irq); -/* Enable IPI IRQ. */ -void ipi_enable_irq(int irq); - -/* IPI tables */ -extern void (*ipi_handler_table[])(int32_t, void *, uint32_t); -extern int *ipi_wakeup_table[]; - -/* Helper macros to build the IPI handler and wakeup functions. */ -#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler) -#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup) - -/* - * Macro to declare an IPI handler. - * _id: The ID of the IPI - * handler: The IPI handler function - * is_wakeup_src: Declare IPI ID as a wake-up source or not - */ -#define DECLARE_IPI(_id, handler, is_wakeup_src) \ - struct ipi_num_check##_id { \ - int tmp1[_id < IPI_COUNT ? 1 : -1]; \ - int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ - }; \ - void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ - { \ - handler(id, buf, len); \ - } \ - const int __keep IPI_WAKEUP(_id) = is_wakeup_src - -#endif /* __CROS_EC_IPI_CHIP_H */ diff --git a/chip/mt_scp/mt8183/ipi_table.c b/chip/mt_scp/mt8183/ipi_table.c deleted file mode 100644 index 8569ab24a7..0000000000 --- a/chip/mt_scp/mt8183/ipi_table.c +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * IPI handlers declaration - */ - -#include "common.h" -#include "ipi_chip.h" - -typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len); - -#ifndef PASS -#define PASS 1 -#endif - -#define ipi_arguments int32_t id, void *data, uint32_t len - -#if PASS == 1 -void ipi_handler_undefined(ipi_arguments) { } - -const int ipi_wakeup_undefined; - -#define table(type, name, x) x - -#define ipi_x_func(suffix, args, number) \ - extern void __attribute__( \ - (used, weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ - ipi_##number##_##suffix(args); - -#define ipi_x_var(suffix, number) \ - extern int __attribute__( \ - (weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ - ipi_##number##_##suffix; - -#endif /* PASS == 1 */ - -#if PASS == 2 - -#undef table -#undef ipi_x_func -#undef ipi_x_var - -#define table(type, name, x) \ - type name[] __aligned(4) \ - __attribute__((section(".rodata.ipi, \"a\" @"))) = {x} - -#define ipi_x_var(suffix, number) \ - [number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix, - -#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number) - -#endif /* PASS == 2 */ - -/* - * Include generated IPI table (by util/gen_ipi_table). The contents originate - * from IPI_COUNT definition in board.h - */ -#include "ipi_table_gen.inc" - -#if PASS == 1 -#undef PASS -#define PASS 2 -#include "ipi_table.c" -BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT); -BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT); -#endif diff --git a/chip/mt_scp/mt8183/memmap.c b/chip/mt_scp/mt8183/memmap.c deleted file mode 100644 index 6d8f2b0c87..0000000000 --- a/chip/mt_scp/mt8183/memmap.c +++ /dev/null @@ -1,322 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SCP memory map - */ - -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "hooks.h" -#include "memmap.h" -#include "registers.h" -#include "util.h" - -/* - * Map SCP address (bits 31~28) to AP address - * - * SCP addr : AP addr - * 0x20000000 0x40000000 - * 0x30000000 0x50000000 - * 0x60000000 0x60000000 - * 0x70000000 0x70000000 - * 0x80000000 0x80000000 - * 0x90000000 0x00000000 - * 0xA0000000 0x10000000 - * 0xB0000000 0x20000000 - * 0xC0000000 0x30000000 - * 0xD0000000 0x10000000 - * 0xE0000000 0xA0000000 - * 0xF0000000 0x90000000 - */ - -#define MAP_INVALID 0xff - -static const uint8_t addr_map[16] = { - MAP_INVALID, /* 0x0: SRAM */ - MAP_INVALID, /* 0x1: Cached access (see below) */ - 0x4, 0x5, /* 0x2-0x3 */ - MAP_INVALID, MAP_INVALID, /* 0x4-0x5 (unmapped: registers) */ - 0x6, 0x7, 0x8, /* 0x6-0x8 */ - 0x0, 0x1, 0x2, 0x3, /* 0x9-0xc */ - 0x1, 0xa, 0x9 /* 0xd-0xf */ -}; - -/* - * AP addr : SCP cache addr - * 0x50000000 0x10000000 - */ -#define CACHE_TRANS_AP_ADDR 0x50000000 -#define CACHE_TRANS_SCP_CACHE_ADDR 0x10000000 -/* FIXME: This should be configurable */ -#define CACHE_TRANS_AP_SIZE 0x00400000 - -#ifdef CONFIG_DRAM_BASE -BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR); -BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR); -#endif - -static void cpu_invalidate_icache(void) -{ - SCP_CACHE_OP(CACHE_ICACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_ICACHE) |= - OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; - asm volatile("dsb; isb"); -} - -void cpu_invalidate_dcache(void) -{ - SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; - /* Read is necessary to confirm the invalidation finish. */ - REG32(CACHE_TRANS_SCP_CACHE_ADDR); - asm volatile("dsb;"); -} - -void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length) -{ - size_t pos; - uintptr_t addr; - - for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) { - addr = base + pos; - SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN; - /* Read necessary to confirm the invalidation finish. */ - REG32(addr); - } - asm volatile("dsb;"); -} - -void cpu_clean_invalidate_dcache(void) -{ - SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_CACHE_FLUSH_ALL_LINES | SCP_CACHE_OP_EN; - SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; - /* Read necessary to confirm the invalidation finish. */ - REG32(CACHE_TRANS_SCP_CACHE_ADDR); - asm volatile("dsb;"); -} - -void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length) -{ - size_t pos; - uintptr_t addr; - - for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) { - addr = base + pos; - SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN; - SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN; - /* Read necessary to confirm the invalidation finish. */ - REG32(addr); - } - asm volatile("dsb;"); -} - -static void scp_cache_init(void) -{ - int c; - const int region = 0; - - /* First make sure all caches are disabled, and reset stats. */ - for (c = 0; c < CACHE_COUNT; c++) { - /* - * Changing cache-size config may change the SRAM logical - * address in the mean time. This may break the loaded - * memory layout, and thus break the system. Cache-size - * should only be be configured in kernel driver before - * laoding the firmware. b/137920815#comment18 - */ - SCP_CACHE_CON(c) &= (SCP_CACHE_CON_CACHESIZE_MASK | - SCP_CACHE_CON_WAYEN); - SCP_CACHE_REGION_EN(c) = 0; - SCP_CACHE_ENTRY(c, region) = 0; - SCP_CACHE_END_ENTRY(c, region) = 0; - - /* Reset statistics. */ - SCP_CACHE_HCNT0U(c) = 0; - SCP_CACHE_HCNT0L(c) = 0; - SCP_CACHE_CCNT0U(c) = 0; - SCP_CACHE_CCNT0L(c) = 0; - } - - /* No "normal" remap. */ - SCP_L1_REMAP_CFG0 = 0; - SCP_L1_REMAP_CFG1 = 0; - SCP_L1_REMAP_CFG2 = 0; - SCP_L1_REMAP_CFG3 = 0; - /* - * Setup OTHER1: Remap register for addr msb 31 to 28 equal to 0x1 and - * not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7. - */ - SCP_L1_REMAP_OTHER = - (CACHE_TRANS_AP_ADDR >> SCP_L1_EXT_ADDR_OTHER_SHIFT) << 8; - - /* Disable sleep protect */ - SCP_SLP_PROTECT_CFG = SCP_SLP_PROTECT_CFG & - ~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN); - - /* Enable region 0 for both I-cache and D-cache. */ - for (c = 0; c < CACHE_COUNT; c++) { - SCP_CACHE_ENTRY(c, region) = CACHE_TRANS_SCP_CACHE_ADDR; - SCP_CACHE_END_ENTRY(c, region) = - CACHE_TRANS_SCP_CACHE_ADDR + CACHE_TRANS_AP_SIZE; - SCP_CACHE_ENTRY(c, region) |= SCP_CACHE_ENTRY_C; - - SCP_CACHE_REGION_EN(c) |= 1 << region; - - /* - * Enable cache. Note that cache size setting should have been - * done in kernel driver. b/137920815#comment18 - */ - SCP_CACHE_CON(c) |= SCP_CACHE_CON_MCEN | SCP_CACHE_CON_CNTEN0; - } - - cpu_invalidate_icache(); - cpu_invalidate_dcache(); -} - -static int command_cacheinfo(int argc, char **argv) -{ - const char cache_name[] = {'I', 'D'}; - int c; - - for (c = 0; c < 2; c++) { - uint64_t hit = ((uint64_t)SCP_CACHE_HCNT0U(c) << 32) | - SCP_CACHE_HCNT0L(c); - uint64_t access = ((uint64_t)SCP_CACHE_CCNT0U(c) << 32) | - SCP_CACHE_CCNT0L(c); - - ccprintf("%ccache hit count: %llu\n", cache_name[c], hit); - ccprintf("%ccache access count: %llu\n", cache_name[c], access); - } - - return EC_SUCCESS; -} -DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo, - NULL, - "Dump cache info"); - -void scp_memmap_init(void) -{ - /* - * Default config, LARGE DRAM not active: - * REG32(0xA0001F00) & 0x2000 != 0 - */ - - /* - * SCP_REMAP_CFG1 - * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7 - * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6 - * EXT_ADDR1[13:8] remap register for addr msb 31~28 equal to 0x3 - * EXT_ADDR0[5:0] remap register for addr msb 31~28 equal to 0x2 - */ - SCP_REMAP_CFG1 = - (uint32_t)addr_map[0x7] << 24 | - (uint32_t)addr_map[0x6] << 16 | - (uint32_t)addr_map[0x3] << 8 | - (uint32_t)addr_map[0x2]; - - /* - * SCP_REMAP_CFG2 - * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb - * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa - * EXT_ADDR5[13:8] remap register for addr msb 31~28 equal to 0x9 - * EXT_ADDR4[5:0] remap register for addr msb 31~28 equal to 0x8 - */ - SCP_REMAP_CFG2 = - (uint32_t)addr_map[0xb] << 24 | - (uint32_t)addr_map[0xa] << 16 | - (uint32_t)addr_map[0x9] << 8 | - (uint32_t)addr_map[0x8]; - /* - * SCP_REMAP_CFG3 - * AUD_ADDR[31:28] remap register for addr msb 31~28 equal to 0xd - * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf - * EXT_ADDR9[13:8] remap register for addr msb 31~28 equal to 0xe - * EXT_ADDR8[5:0] remap register for addr msb 31~28 equal to 0xc - */ - SCP_REMAP_CFG3 = - (uint32_t)addr_map[0xd] << 28 | - (uint32_t)addr_map[0xf] << 16 | - (uint32_t)addr_map[0xe] << 8 | - (uint32_t)addr_map[0xc]; - - /* Initialize cache remapping. */ - scp_cache_init(); -} - -int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr) -{ - int i; - uint8_t msb = ap_addr >> SCP_REMAP_ADDR_SHIFT; - - for (i = 0; i < ARRAY_SIZE(addr_map); i++) { - if (addr_map[i] != msb) - continue; - - *scp_addr = (ap_addr & SCP_REMAP_ADDR_LSB_MASK) | - (i << SCP_REMAP_ADDR_SHIFT); - return EC_SUCCESS; - } - - return EC_ERROR_INVAL; -} - -int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr) -{ - int i = scp_addr >> SCP_REMAP_ADDR_SHIFT; - - if (addr_map[i] == MAP_INVALID) - return EC_ERROR_INVAL; - - *ap_addr = (scp_addr & SCP_REMAP_ADDR_LSB_MASK) | - (addr_map[i] << SCP_REMAP_ADDR_SHIFT); - return EC_SUCCESS; -} - -#ifdef CONFIG_DRAM_BASE -BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR); -BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR); -#endif - -int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr) -{ - uintptr_t lsb; - - if ((ap_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != CACHE_TRANS_AP_ADDR) - return EC_ERROR_INVAL; - - lsb = ap_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK; - if (lsb > CACHE_TRANS_AP_SIZE) - return EC_ERROR_INVAL; - - *scp_addr = CACHE_TRANS_SCP_CACHE_ADDR | lsb; - return EC_SUCCESS; -} - -int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr) -{ - uintptr_t lsb; - - if ((scp_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != - CACHE_TRANS_SCP_CACHE_ADDR) - return EC_ERROR_INVAL; - - lsb = scp_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK; - if (lsb >= CACHE_TRANS_AP_SIZE) - return EC_ERROR_INVAL; - - *ap_addr = CACHE_TRANS_AP_ADDR | lsb; - return EC_SUCCESS; -} diff --git a/chip/mt_scp/mt8183/memmap.h b/chip/mt_scp/mt8183/memmap.h deleted file mode 100644 index fbecb5e8cf..0000000000 --- a/chip/mt_scp/mt8183/memmap.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SCP memory map - */ - -#ifndef __CROS_EC_MEMMAP_H -#define __CROS_EC_MEMMAP_H - -void scp_memmap_init(void); - -/** - * Translate AP addr to SCP addr. - * - * @param ap_addr AP address to translate - * @param scp_addr Tranlated AP address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr); - -/** - * Translate SCP addr to AP addr. - * - * @param scp_addr SCP address to tranlate - * @param ap_addr Translated SCP address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr); - -/** - * Translate AP addr to SCP cache addr. - * - * @param ap_addr AP address to translate - * @param scp_addr Tranlated AP cache address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr); - -/** - * Translate SCP addr to AP addr. - * - * @param scp_addr SCP cache address to tranlate - * @param ap_addr Translated SCP cache address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr); - -#endif /* #ifndef __CROS_EC_MEMMAP_H */ diff --git a/chip/mt_scp/mt8183/registers.h b/chip/mt_scp/mt8183/registers.h deleted file mode 100644 index 21270b452d..0000000000 --- a/chip/mt_scp/mt8183/registers.h +++ /dev/null @@ -1,645 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for SCP - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" -#include "compile_time_macros.h" - -/* IRQ numbers */ -#define SCP_IRQ_IPC0 0 -#define SCP_IRQ_IPC1 1 -#define SCP_IRQ_IPC2 2 -#define SCP_IRQ_IPC3 3 -#define SCP_IRQ_SPM 4 -#define SCP_IRQ_CIRQ 5 -#define SCP_IRQ_EINT 6 -#define SCP_IRQ_PMIC 7 -#define SCP_IRQ_UART0 8 -#define SCP_IRQ_UART1 9 -#define SCP_IRQ_I2C0 10 -#define SCP_IRQ_I2C1 11 -#define SCP_IRQ_I2C2 12 -#define SCP_IRQ_CLOCK 13 -#define SCP_IRQ_MAD_FIFO 14 -#define SCP_IRQ_TIMER0 15 -#define SCP_IRQ_TIMER1 16 -#define SCP_IRQ_TIMER2 17 -#define SCP_IRQ_TIMER3 18 -#define SCP_IRQ_TIMER4 19 -#define SCP_IRQ_TIMER5 20 -#define SCP_IRQ_TIMER_STATUS 21 -#define SCP_IRQ_UART0_RX 22 -#define SCP_IRQ_UART1_RX 23 -#define SCP_IRQ_DMA 24 -#define SCP_IRQ_AUDIO 25 -#define SCP_IRQ_MD1_F216 26 -#define SCP_IRQ_MD1 27 -#define SCP_IRQ_C2K 28 -#define SCP_IRQ_SPI0 29 -#define SCP_IRQ_SPI1 30 -#define SCP_IRQ_SPI2 31 -#define SCP_IRQ_AP_EINT 32 -#define SCP_IRQ_DEBUG 33 -#define SCP_CCIF0 34 -#define SCP_CCIF1 35 -#define SCP_CCIF2 36 -#define SCP_IRQ_WDT 37 -#define SCP_IRQ_USB0 38 -#define SCP_IRQ_USB1 39 -#define SCP_IRQ_TWAM 40 -#define SCP_IRQ_INFRA 41 -#define SCP_IRQ_HWDVFS_HIGH 42 -#define SCP_IRQ_HWDVFS_LOW 43 -#define SCP_IRQ_CLOCK2 44 -/* RESERVED 45-52 */ -#define SCP_IRQ_AP_EINT2 53 -#define SCP_IRQ_AP_EINT_EVT 54 -#define SCP_IRQ_MAD_DATA 55 - -#define SCP_CFG_BASE 0x405C0000 - -#define SCP_AP_RESOURCE REG32(SCP_CFG_BASE + 0x04) -#define SCP_BUS_RESOURCE REG32(SCP_CFG_BASE + 0x08) - -/* SCP to host interrupt */ -#define SCP_HOST_INT REG32(SCP_CFG_BASE + 0x1C) -#define IPC_SCP2HOST_SSHUB 0xff0000 -#define WDT_INT 0x100 -#define IPC_SCP2HOST 0xff -#define IPC_SCP2HOST_BIT 0x1 - -/* SCP to SPM interrupt */ -#define SCP_SPM_INT REG32(SCP_CFG_BASE + 0x20) -#define SPM_INT_A2SPM BIT(0) -#define SPM_INT_B2SPM BIT(1) -#define SCP_SPM_INT2 REG32(SCP_CFG_BASE + 0x24) - -/* - * AP side to SCP IPC - * APMCU writes 1 bit to trigger ith IPC to SCP. - * SCP writes 1 bit to ith bit to clear ith IPC. - */ -#define SCP_GIPC_IN REG32(SCP_CFG_BASE + 0x28) - #define SCP_GIPC_IN_CLEAR_IPCN(n) (1 << (n)) - #define SCP_GPIC_IN_CLEAR_ALL 0x7FFFF -#define SCP_CONN_INT REG32(SCP_CFG_BASE + 0x2C) - -/* 8 general purpose registers, 0 ~ 7 */ -#define SCP_GPR REG32_ADDR(SCP_CFG_BASE + 0x50) -/* - * SCP_GPR[0] - * b15-b0 : scratchpad - * b31-b16 : saved flags - * SCP_GPR[1] - * b15-b0 : power on state - */ -#define SCP_PWRON_STATE SCP_GPR[1] -#define PWRON_DEFAULT 0xdee80000 -#define PWRON_WATCHDOG BIT(0) -#define PWRON_RESET BIT(1) -/* AP defined features */ -#define SCP_EXPECTED_FREQ SCP_GPR[3] -#define SCP_CURRENT_FREQ SCP_GPR[4] -#define SCP_REBOOT SCP_GPR[5] -#define READY_TO_REBOOT 0x34 -#define REBOOT_OK 1 - -/* Miscellaneous */ -#define SCP_SEMAPHORE REG32(SCP_CFG_BASE + 0x90) -#define CORE_CONTROL REG32(SCP_CFG_BASE + 0xA0) -#define CORE_FPU_FLAGS REG32(SCP_CFG_BASE + 0xA4) -#define CORE_REG_SP REG32(SCP_CFG_BASE + 0xA8) -#define CORE_REG_LR REG32(SCP_CFG_BASE + 0xAC) -#define CORE_REG_PSP REG32(SCP_CFG_BASE + 0xB0) -#define CORE_REG_PC REG32(SCP_CFG_BASE + 0xB4) -#define SCP_SLP_PROTECT_CFG REG32(SCP_CFG_BASE + 0xC8) -#define P_CACHE_SLP_PROT_EN BIT(3) -#define D_CACHE_SLP_PROT_EN BIT(4) -#define SCP_ONE_TIME_LOCK REG32(SCP_CFG_BASE + 0xDC) -#define SCP_SECURE_CTRL REG32(SCP_CFG_BASE + 0xE0) -#define ENABLE_SPM_MASK_VREQ BIT(28) -#define DISABLE_REMAP BIT(22) -#define DISABLE_JTAG BIT(21) -#define DISABLE_AP_TCM BIT(20) -#define SCP_SYS_CTRL REG32(SCP_CFG_BASE + 0xE4) -#define DDREN_FIX_VALUE BIT(28) -#define AUTO_DDREN BIT(18) - -/* Memory remap control */ -/* - * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7 - * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6 - * EXT_ADDR1[13:8] remap register for addr msb 31~28 equal to 0x3 - * EXT_ADDR0[5:0] remap register for addr msb 31~28 equal to 0x2 - */ -#define SCP_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x120) -/* - * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb - * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa - * EXT_ADDR5[13:8] remap register for addr msb 31~28 equal to 0x9 - * EXT_ADDR4[5:0] remap register for addr msb 31~28 equal to 0x8 - */ -#define SCP_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x124) -/* - * AUD_ADDR[31:28] remap register for addr msb 31~28 equal to 0xd - * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf - * EXT_ADDR9[13:8] remap register for addr msb 31~28 equal to 0xe - * EXT_ADDR8[5:0] remap register for addr msb 31~28 equal to 0xc - */ -#define SCP_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x128) - -#define SCP_REMAP_ADDR_SHIFT 28 -#define SCP_REMAP_ADDR_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) -#define SCP_REMAP_ADDR_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) - -/* Cached memory remap control */ -#define SCP_L1_REMAP_CFG0 REG32(SCP_CFG_BASE + 0x12C) -/* - * L1C_EXT_ADDR1[29:16] remap register for addr msb 31~20 equal to 0x401 - * L1C_EXT_ADDR0[13:0] remap register for addr msb 31~20 equal to 0x400 - */ -#define SCP_L1_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x130) -/* - * L1C_EXT_ADDR3[29:16] remap register for addr msb 31~20 equal to 0x403 - * L1C_EXT_ADDR2[13:0] remap register for addr msb 31~20 equal to 0x402 - */ -#define SCP_L1_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x134) -/* - * L1C_EXT_ADDR5[29:16] remap register for addr msb 31~20 equal to 0x405 - * L1C_EXT_ADDR4[13:0] remap register for addr msb 31~20 equal to 0x404 - */ -#define SCP_L1_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x138) -/* - * L1C_EXT_ADDR_OTHER1[13:8] Remap register for addr msb 31 to 28 equal to 0x1 - * L1C_EXT_ADDR_OTHER0[5:0] Remap register for addr msb 31 to 28 equal to 0x0 - * and not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7 - */ -#define SCP_L1_REMAP_OTHER REG32(SCP_CFG_BASE + 0x13C) - -#define SCP_L1_EXT_ADDR_SHIFT 20 -#define SCP_L1_EXT_ADDR_OTHER_SHIFT 28 -#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) -#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) - -/* Audio/voice FIFO */ -#define SCP_AUDIO_BASE (SCP_CFG_BASE + 0x1000) -#define SCP_VIF_FIFO_EN REG32(SCP_AUDIO_BASE) -#define VIF_FIFO_RSTN (1 << 0) -#define VIF_FIFO_IRQ_EN (1 << 1) -#define VIF_FIFO_SRAM_PWR (1 << 2) -#define VIF_FIFO_RSTN_STATUS (1 << 4) -#define SCP_VIF_FIFO_STATUS REG32(SCP_AUDIO_BASE + 0x04) -#define VIF_FIFO_VALID (1 << 0) -#define VIF_FIFO_FULL (1 << 4) -#define VIF_FIFO_LEVEL(status) (((status) >> 16) & 0xff) -#define VIF_FIFO_MAX 256 -#define SCP_VIF_FIFO_DATA REG32(SCP_AUDIO_BASE + 0x08) -#define SCP_VIF_FIFO_DATA_THRE REG32(SCP_AUDIO_BASE + 0x0C) -/* VIF IRQ status clears on read! */ -#define SCP_VIF_FIFO_IRQ_STATUS REG32(SCP_AUDIO_BASE + 0x10) -/* Audio/voice serial interface */ -#define SCP_RXIF_CFG0 REG32(SCP_AUDIO_BASE + 0x14) -#define RXIF_CFG0_RESET_VAL 0x2A130001 -#define RXIF_AFE_ON (1 << 0) -#define RXIF_SCKINV (1 << 1) -#define RXIF_RG_DL_2_IN_MODE(mode) (((mode) & 0xf) << 8) -#define RXIF_RGDL2_AMIC_16K (0x1 << 8) -#define RXIF_RGDL2_DMIC_16K (0x2 << 8) -#define RXIF_RGDL2_DMIC_LP_16K (0x3 << 8) -#define RXIF_RGDL2_AMIC_32K (0x5 << 8) -#define RXIF_RGDL2_MASK (0xf << 8) -#define RXIF_UP8X_RSP(p) (((p) & 0x7) << 16) -#define RXIF_RG_RX_READEN (1 << 19) -#define RXIF_MONO (1 << 20) -#define RXIF_RG_CLK_A16P7K_EN(cnt) (((cnt) & 0xff) << 24) -#define SCP_RXIF_CFG1 REG32(SCP_AUDIO_BASE + 0x18) -#define RXIF_CFG1_RESET_VAL 0x33180014 -#define RXIF_RG_SYNC_CNT_TBL(t) ((t) & 0x1ff) -#define RXIF_RG_SYNC_SEARCH_TBL(t) (((t) & 0x1f) << 16) -#define RXIF_RG_SYNC_CHECK_ROUND(r) (((r) & 0xf) << 24) -#define RXIF_RG_INSYNC_CHECK_ROUND(r) (((r) & 0xf) << 28) -#define SCP_RXIF_CFG2 REG32(SCP_AUDIO_BASE + 0x1C) -#define RXIF_SYNC_WORD(w) ((w) & 0xffff) -#define SCP_RXIF_OUT REG32(SCP_AUDIO_BASE + 0x20) -#define SCP_RXIF_STATUS REG32(SCP_AUDIO_BASE + 0x24) -#define SCP_RXIF_IRQ_EN REG32(SCP_AUDIO_BASE + 0x28) - -/* INTC control */ -#define SCP_INTC_BASE (SCP_CFG_BASE + 0x2000) -#define SCP_INTC_IRQ_STATUS REG32(SCP_INTC_BASE) -#define SCP_INTC_IRQ_ENABLE REG32(SCP_INTC_BASE + 0x04) -#define IPC0_IRQ_EN BIT(0) -#define SCP_INTC_IRQ_OUTPUT REG32(SCP_INTC_BASE + 0x08) -#define SCP_INTC_IRQ_WAKEUP REG32(SCP_INTC_BASE + 0x0C) -#define SCP_INTC_NMI REG32(SCP_INTC_BASE + 0x10) -#define SCP_INTC_SPM_WAKEUP REG32(SCP_INTC_BASE + 0x14) -#define SCP_INTC_SPM_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x18) -#define SCP_INTC_UART_RX_IRQ REG32(SCP_INTC_BASE + 0x1C) -#define SCP_INTC_IRQ_STATUS_MSB REG32(SCP_INTC_BASE + 0x80) -#define SCP_INTC_IRQ_ENABLE_MSB REG32(SCP_INTC_BASE + 0x84) -#define SCP_INTC_IRQ_OUTPUT_MSB REG32(SCP_INTC_BASE + 0x88) -#define SCP_INTC_IRQ_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x8C) - -/* Timer */ -#define NUM_TIMERS 6 -#define SCP_TIMER_BASE(n) (SCP_CFG_BASE + 0x3000 + (0x10 * (n))) -#define SCP_TIMER_EN(n) REG32(SCP_TIMER_BASE(n)) -#define SCP_TIMER_RESET_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x04) -#define SCP_TIMER_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x08) -#define SCP_TIMER_IRQ_CTRL(n) REG32(SCP_TIMER_BASE(n) + 0x0C) -#define TIMER_IRQ_ENABLE BIT(0) -#define TIMER_IRQ_STATUS BIT(4) -#define TIMER_IRQ_CLEAR BIT(5) -#define SCP_TIMER_CLK_SEL(n) REG32(SCP_TIMER_BASE(n) + 0x40) -#define TIMER_CLK_32K (0 << 4) -#define TIMER_CLK_26M BIT(4) -#define TIMER_CLK_BCLK (2 << 4) -#define TIMER_CLK_PCLK (3 << 4) -#define TIMER_CLK_MASK (3 << 4) -/* OS timer */ -#define SCP_OSTIMER_BASE (SCP_CFG_BASE + 0x3080) -#define SCP_OSTIMER_CON REG32(SCP_OSTIMER_BASE) -#define SCP_OSTIMER_INIT_L REG32(SCP_OSTIMER_BASE + 0x04) -#define SCP_OSTIMER_INIT_H REG32(SCP_OSTIMER_BASE + 0x08) -#define SCP_OSTIMER_VAL_L REG32(SCP_OSTIMER_BASE + 0x0C) -#define SCP_OSTIMER_VAL_H REG32(SCP_OSTIMER_BASE + 0x10) -#define SCP_OSTIMER_TVAL REG32(SCP_OSTIMER_BASE + 0x14) -#define SCP_OSTIMER_IRQ_ACK REG32(SCP_OSTIMER_BASE + 0x18) -#define OSTIMER_LATCH0_EN BIT(5) -#define OSTIMER_LATCH1_EN BIT(13) -#define OSTIMER_LATCH2_EN BIT(21) -#define SCP_OSTIMER_LATCH_CTRL REG32(SCP_OSTIMER_BASE + 0x20) -#define SCP_OSTIMER_LATCH0_L REG32(SCP_OSTIMER_BASE + 0x24) -#define SCP_OSTIMER_LATCH0_H REG32(SCP_OSTIMER_BASE + 0x28) -#define SCP_OSTIMER_LATCH1_L REG32(SCP_OSTIMER_BASE + 0x2C) -#define SCP_OSTIMER_LATCH1_H REG32(SCP_OSTIMER_BASE + 0x30) -#define SCP_OSTIMER_LATCH2_L REG32(SCP_OSTIMER_BASE + 0x34) -#define SCP_OSTIMER_LATCH2_H REG32(SCP_OSTIMER_BASE + 0x38) - -/* Clock, PMIC wrapper, etc. */ -#define SCP_CLK_BASE (SCP_CFG_BASE + 0x4000) -#define SCP_CLK_SEL REG32(SCP_CLK_BASE) -#define CLK_SEL_SYS_26M 0 -#define CLK_SEL_32K 1 -#define CLK_SEL_ULPOSC_2 2 -#define CLK_SEL_ULPOSC_1 3 - -#define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04) -#define EN_CLK_SYS BIT(0) /* System clock */ -#define EN_CLK_HIGH BIT(1) /* ULPOSC */ -#define CG_CLK_HIGH BIT(2) -#define EN_SYS_IRQ BIT(16) -#define EN_HIGH_IRQ BIT(17) -#define SCP_CLK_SAFE_ACK REG32(SCP_CLK_BASE + 0x08) -#define SCP_CLK_ACK REG32(SCP_CLK_BASE + 0x0C) -#define SCP_CLK_IRQ_ACK REG32(SCP_CLK_BASE + 0x10) -/* - * System clock counter value. - * CLK_SYS_VAL[9:0] System clock counter initial/reset value. - */ -#define SCP_CLK_SYS_VAL REG32(SCP_CLK_BASE + 0x14) -#define CLK_SYS_VAL_MASK 0x3ff /* 10 bits */ -#define CLK_SYS_VAL(n) ((n) & CLK_SYS_VAL_MASK) -/* - * ULPOSC clock counter value. - * CLK_HIGH_VAL[9:0] ULPOSC clock counter initial/reset value. - */ -#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_BASE + 0x18) -#define CLK_HIGH_VAL_MASK 0x3ff /* 10 bits */ -#define CLK_HIGH_VAL(n) ((n) & CLK_HIGH_VAL_MASK) -#define SCP_CLK_SLOW_SEL REG32(SCP_CLK_BASE + 0x1C) -#define CKSW_SEL_SLOW_MASK 0x3 -#define CKSW_SEL_SLOW_DIV_MASK 0x30 -#define CKSW_SEL_SLOW_SYS_CLK 0 -#define CKSW_SEL_SLOW_32K_CLK 1 -#define CKSW_SEL_SLOW_ULPOSC2_CLK 2 -#define CKSW_SEL_SLOW_ULPOSC1_CLK 3 -/* - * Sleep mode control. - * VREQ_COUNT[7:1] Number of cycles to wait when requesting PMIC to raise the - * voltage after returning from sleep mode. - */ -#define SCP_CLK_SLEEP_CTRL REG32(SCP_CLK_BASE + 0x20) -#define EN_SLEEP_CTRL BIT(0) -#define VREQ_COUNTER_MASK 0xfe -#define VREQ_COUNTER_VAL(v) (((v) << 1) & VREQ_COUNTER_MASK) -#define SPM_SLEEP_MODE BIT(8) -#define SPM_SLEEP_MODE_CLK_AO BIT(9) -#define SCP_CLK_DIV_SEL REG32(SCP_CLK_BASE + 0x24) -#define CLK_DIV1 0 -#define CLK_DIV2 1 -#define CLK_DIV4 2 -#define CLK_DIV8 3 -#define SCP_CLK_DEBUG REG32(SCP_CLK_BASE + 0x28) -#define SCP_CLK_SRAM_POWERDOWN REG32(SCP_CLK_BASE + 0x2C) -#define SCP_CLK_GATE REG32(SCP_CLK_BASE + 0x30) -#define CG_TIMER_M BIT(0) -#define CG_TIMER_B BIT(1) -#define CG_MAD_M BIT(2) -#define CG_I2C_M BIT(3) -#define CG_I2C_B BIT(4) -#define CG_GPIO_M BIT(5) -#define CG_AP2P_M BIT(6) -#define CG_UART_M BIT(7) -#define CG_UART_B BIT(8) -#define CG_UART_RSTN BIT(9) -#define CG_UART1_M BIT(10) -#define CG_UART1_B BIT(11) -#define CG_UART1_RSTN BIT(12) -#define CG_SPI0 BIT(13) -#define CG_SPI1 BIT(14) -#define CG_SPI2 BIT(15) -#define CG_DMA_CH0 BIT(16) -#define CG_DMA_CH1 BIT(17) -#define CG_DMA_CH2 BIT(18) -#define CG_DMA_CH3 BIT(19) -#define CG_TWAM BIT(20) -#define CG_CACHE_I_CTRL BIT(21) -#define CG_CACHE_D_CTRL BIT(22) -#define SCP_PMICW_CTRL REG32(SCP_CLK_BASE + 0x34) -#define PMICW_SLEEP_REQ BIT(0) -#define PMICW_SLEEP_ACK BIT(4) -#define PMICW_CLK_MUX BIT(8) -#define PMICW_DCM BIT(9) -#define SCP_SLEEP_WAKE_DEBUG REG32(SCP_CLK_BASE + 0x38) -#define SCP_DCM_EN REG32(SCP_CLK_BASE + 0x3C) -#define SCP_WAKE_CKSW REG32(SCP_CLK_BASE + 0x40) -#define WAKE_CKSW_SEL_NORMAL_MASK 0x3 -#define WAKE_CKSW_SEL_SLOW_MASK 0x30 -#define WAKE_CKSW_SEL_SLOW_DEFAULT 0x10 -#define SCP_CLK_UART REG32(SCP_CLK_BASE + 0x44) -#define CLK_UART_SEL_MASK 0x3 -#define CLK_UART_SEL_26M 0x0 -#define CLK_UART_SEL_32K 0x1 -/* This is named ulposc_div_to_26m in datasheet */ -#define CLK_UART_SEL_ULPOSC1_DIV10 0x2 -#define CLK_UART1_SEL_MASK (0x3 << 16) -#define CLK_UART1_SEL_26M (0x0 << 16) -#define CLK_UART1_SEL_32K (0x1 << 16) -/* This is named ulposc_div_to_26m in datasheet */ -#define CLK_UART1_SEL_ULPOSC1_DIV10 (0x2 << 16) -#define SCP_CLK_BCLK REG32(SCP_CLK_BASE + 0x48) -#define CLK_BCLK_SEL_MASK 0x3 -#define CLK_BCLK_SEL_SYS_DIV8 0x0 -#define CLK_BCLK_SEL_32K 0x1 -#define CLK_BCLK_SEL_ULPOSC1_DIV8 0x2 -#define SCP_CLK_SPI_BCK REG32(SCP_CLK_BASE + 0x4C) -#define SCP_CLK_DIV_CNT REG32(SCP_CLK_BASE + 0x50) -#define SCP_CPU_VREQ REG32(SCP_CLK_BASE + 0x54) -#define CPU_VREQ_HW_MODE 0x10001 -#define SCP_CLK_CLEAR REG32(SCP_CLK_BASE + 0x58) -#define SCP_CLK_HIGH_CORE REG32(SCP_CLK_BASE + 0x5C) -#define CLK_HIGH_CORE_CG (1 << 1) -#define SCP_SLEEP_IRQ2 REG32(SCP_CLK_BASE + 0x64) -#define SCP_CLK_ON_CTRL REG32(SCP_CLK_BASE + 0x6C) -#define HIGH_AO BIT(0) -#define HIGH_CG_AO BIT(2) -#define HIGH_CORE_AO BIT(4) -#define HIGH_CORE_DIS_SUB BIT(5) -#define HIGH_CORE_CG_AO BIT(6) -#define HIGH_FINAL_VAL_MASK 0x1f00 -#define HIGH_FINAL_VAL_DEFAULT 0x300 -#define SCP_CLK_L1_SRAM_PD REG32(SCP_CLK_BASE + 0x80) -#define SCP_CLK_TCM_TAIL_SRAM_PD REG32(SCP_CLK_BASE + 0x94) -#define SCP_CLK_SLEEP REG32(SCP_CLK_BASE + 0xA0) -#define SLOW_WAKE_DISABLE 1 -#define SCP_FAST_WAKE_CNT_END REG32(SCP_CLK_BASE + 0xA4) -#define FAST_WAKE_CNT_END_MASK 0xfff -#define FAST_WAKE_CNT_END_DEFAULT 0x18 -#define MEM_CK_CS_ISO_CNT_END_MASK 0x7f0000 - -/* Peripherals */ -#define SCP_I2C0_BASE (SCP_CFG_BASE + 0x5000) -#define SCP_I2C1_BASE (SCP_CFG_BASE + 0x6000) -#define SCP_I2C2_BASE (SCP_CFG_BASE + 0x7000) - -#define SCP_GPIO_BASE (SCP_CFG_BASE + 0x8000) -#define SCP_UART0_BASE (SCP_CFG_BASE + 0x9000) -#define SCP_UART1_BASE (SCP_CFG_BASE + 0xE000) -#define SCP_UART_COUNT 2 - -/* External GPIO interrupt */ -#define SCP_EINT_BASE (SCP_CFG_BASE + 0xA000) -#define SCP_EINT_STATUS REG32_ADDR(SCP_EINT_BASE) -#define SCP_EINT_ACK REG32_ADDR(SCP_EINT_BASE + 0x040) -#define SCP_EINT_MASK_GET REG32_ADDR(SCP_EINT_BASE + 0x080) -#define SCP_EINT_MASK_SET REG32_ADDR(SCP_EINT_BASE + 0x0C0) -#define SCP_EINT_MASK_CLR REG32_ADDR(SCP_EINT_BASE + 0x100) -#define SCP_EINT_SENS_GET REG32_ADDR(SCP_EINT_BASE + 0x140) -#define SCP_EINT_SENS_SET REG32_ADDR(SCP_EINT_BASE + 0x180) -#define SCP_EINT_SENS_CLR REG32_ADDR(SCP_EINT_BASE + 0x1C0) -#define SCP_EINT_SOFT_GET REG32_ADDR(SCP_EINT_BASE + 0x200) -#define SCP_EINT_SOFT_SET REG32_ADDR(SCP_EINT_BASE + 0x240) -#define SCP_EINT_SOFT_CLR REG32_ADDR(SCP_EINT_BASE + 0x280) -#define SCP_EINT_POLARITY_GET REG32_ADDR(SCP_EINT_BASE + 0x300) -#define SCP_EINT_POLARITY_SET REG32_ADDR(SCP_EINT_BASE + 0x340) -#define SCP_EINT_POLARITY_CLR REG32_ADDR(SCP_EINT_BASE + 0x380) -#define SCP_EINT_D0_EN REG32_ADDR(SCP_EINT_BASE + 0x400) -#define SCP_EINT_D1_EN REG32_ADDR(SCP_EINT_BASE + 0x420) -#define SCP_EINT_DBNC_GET REG32_ADDR(SCP_EINT_BASE + 0x500) -#define SCP_EINT_DBNC_SET REG32_ADDR(SCP_EINT_BASE + 0x600) -#define SCP_EINT_DBNC_CLR REG32_ADDR(SCP_EINT_BASE + 0x700) - -#define SCP_PMICWP2P_BASE (SCP_CFG_BASE + 0xB000) -#define PMICW_WACS_CMD REG32(SCP_PMICWP2P_BASE + 0x200) -#define PMICW_WACS_RDATA REG32(SCP_PMICWP2P_BASE + 0x204) -#define PMICW_WACS_VLDCLR REG32(SCP_PMICWP2P_BASE + 0x208) -#define SCP_SPMP2P_BASE (SCP_CFG_BASE + 0xC000) -#define SCP_DMA_BASE (SCP_CFG_BASE + 0xD000) -#define DMA_ACKINT_CHX REG32(SCP_DMA_BASE + 0x20) -#define SCP_SPI0_BASE (SCP_CFG_BASE + 0xF000) -#define SCP_SPI1_BASE (SCP_CFG_BASE + 0x10000) -#define SCP_SPI2_BASE (SCP_CFG_BASE + 0x11000) - -#define CACHE_ICACHE 0 -#define CACHE_DCACHE 1 -#define CACHE_COUNT 2 -#define SCP_CACHE_BASE (SCP_CFG_BASE + 0x14000) -#define SCP_CACHE_SEL(x) (SCP_CACHE_BASE + (x)*0x3000) -#define SCP_CACHE_CON(x) REG32(SCP_CACHE_SEL(x)) -#define SCP_CACHE_CON_MCEN BIT(0) -#define SCP_CACHE_CON_CNTEN0 BIT(2) -#define SCP_CACHE_CON_CNTEN1 BIT(3) -#define SCP_CACHE_CON_CACHESIZE_SHIFT 8 -#define SCP_CACHE_CON_CACHESIZE_MASK (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_0KB (0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_8KB (0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_16KB (0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_32KB (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_WAYEN BIT(10) - -#define SCP_CACHE_OP(x) REG32(SCP_CACHE_SEL(x) + 0x04) -#define SCP_CACHE_OP_EN BIT(0) -#define SCP_CACHE_OP_OP_SHIFT 1 -#define SCP_CACHE_OP_OP_MASK (0xf << SCP_CACHE_OP_OP_SHIFT) - -#define OP_INVALIDATE_ALL_LINES (0x1 << SCP_CACHE_OP_OP_SHIFT) -#define OP_INVALIDATE_ONE_LINE_BY_ADDRESS (0x2 << SCP_CACHE_OP_OP_SHIFT) -#define OP_INVALIDATE_ONE_LINE_BY_SET_WAY (0x4 << SCP_CACHE_OP_OP_SHIFT) -#define OP_CACHE_FLUSH_ALL_LINES (0x9 << SCP_CACHE_OP_OP_SHIFT) -#define OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS (0xa << SCP_CACHE_OP_OP_SHIFT) -#define OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY (0xc << SCP_CACHE_OP_OP_SHIFT) - -#define SCP_CACHE_OP_TADDR_SHIFT 5 -#define SCP_CACHE_OP_TADDR_MASK (0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT) -#define SCP_CACHE_LINE_SIZE BIT(SCP_CACHE_OP_TADDR_SHIFT) - -/* Cache statistics */ -#define SCP_CACHE_HCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x08) -#define SCP_CACHE_HCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x0c) -#define SCP_CACHE_CCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x10) -#define SCP_CACHE_CCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x14) -#define SCP_CACHE_HCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x18) -#define SCP_CACHE_HCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x1c) -#define SCP_CACHE_CCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x20) -#define SCP_CACHE_CCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x24) - -#define SCP_CACHE_REGION_EN(x) REG32(SCP_CACHE_SEL(x) + 0x2c) - -#define SCP_CACHE_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2000) -#define SCP_CACHE_ENTRY(x, reg) REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4) -#define SCP_CACHE_END_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2040) -#define SCP_CACHE_END_ENTRY(x, reg) REG32(SCP_CACHE_END_ENTRY_BASE(x) + \ - (reg)*4) -#define SCP_CACHE_ENTRY_C BIT(8) -#define SCP_CACHE_ENTRY_BASEADDR_MASK (0xfffff << 12) - -/* ARMV7 regs */ -#define ARM_SCB_SCR REG32(0xE000ED10) -#define SCR_DEEPSLEEP BIT(2) - -/* AP regs */ -#define AP_BASE 0xA0000000 -#define TOPCK_BASE AP_BASE /* Top clock */ -#define SCP_UART2_BASE (AP_BASE + 0x01002000) /* AP UART0 */ - -/* CLK_CFG_5 regs */ -#define AP_CLK_CFG_5 REG32(TOPCK_BASE + 0x0090) -#define PWRAP_ULPOSC_MASK (0x3000000) -#define CLK26M (0 << 24) -#define OSC_D16 (1 << 24) -#define OSC_D4 (2 << 24) -#define OSC_D8 (3 << 24) -#define AP_CLK_CFG_5_CLR REG32(TOPCK_BASE + 0x0098) -#define PWRAP_ULPOSC_CG BIT(31) - -/* OSC meter */ -#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0104) -#define MISC_METER_DIVISOR_MASK 0xff000000 -#define MISC_METER_DIV_1 0 -#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x010C) -#define DBG_MODE_MASK 3 -#define DBG_MODE_SET_CLOCK 0 -#define DBG_BIST_SOURCE_MASK (0x3f << 16) -#define DBG_BIST_SOURCE_ULPOSC1 (0x26 << 16) -#define DBG_BIST_SOURCE_ULPOSC2 (0x25 << 16) -#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220) -#define CFG_FREQ_METER_RUN (1 << 4) -#define CFG_FREQ_METER_ENABLE (1 << 12) -#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224) -#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF) - -/* GPIO */ -#define AP_GPIO_BASE (AP_BASE + 0x00005000) -/* - * AP_GPIO_DIR - * GPIO input/out direction, 1 bit per pin. - * 0:input 1:output - */ -#define AP_GPIO_DIR(n) REG32(AP_GPIO_BASE + ((n) << 4)) -/* - * AP_GPIO_DOUT, n in [0..5] - * GPIO output level, 1 bit per pin - * 0:low 1:high - */ -#define AP_GPIO_DOUT(n) REG32(AP_GPIO_BASE + 0x100 + ((n) << 4)) -/* - * AP_GPIO_DIN, n in [0..5] - * GPIO input level, 1 bit per pin - * 0:low 1:high - */ -#define AP_GPIO_DIN(n) REG32(AP_GPIO_BASE + 0x200 + ((n) << 4)) -/* - * AP_GPIO_MODE, n in [0..22] - * Pin mode selection, 4 bit per pin - * bit3 - write enable, set to 1 for hw to fetch bit2,1,0. - * bit2-0 - mode 0 ~ 7 - */ -#define AP_GPIO_MODE(n) REG32(AP_GPIO_BASE + 0x300 + ((n) << 4)) -#define AP_GPIO_TRAP REG32(AP_GPIO_BASE + 0x6B0) -#define AP_GPIO_UNIMPLEMENTED REG32(AP_GPIO_BASE + 0x6C0) -#define AP_GPIO_DBG REG32(AP_GPIO_BASE + 0x6D0) -#define AP_GPIO_BANK REG32(AP_GPIO_BASE + 0x6E0) -/* AP_GPIO_SEC, n in [0..5] */ -#define AP_GPIO_SEC(n) REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4)) - -/* - * PLL ULPOSC - * ULPOSC1: AP_ULPOSC_CON[0] AP_ULPOSC_CON[1] - * ULPOSC2: AP_ULPOSC_CON[2] AP_ULPOSC_CON[3] - * osc: 0 for ULPOSC1, 1 for ULPSOC2. - */ -#define AP_ULPOSC_BASE0 (AP_BASE + 0xC700) -#define AP_ULPOSC_BASE1 (AP_BASE + 0xC704) -#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc) * 0x8) -#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc) * 0x8) -/* - * AP_ULPOSC_CON[0,2] - * bit0-5: calibration - * bit6-12: I-band - * bit13-16: F-band - * bit17-22: div - * bit23: CP_EN - * bit24-31: reserved - */ -#define OSC_CALI_MSK (0x3f << 0) -#define OSC_CALI_BITS 6 -#define OSC_IBAND_MASK (0x7f << 6) -#define OSC_FBAND_MASK (0x0f << 13) -#define OSC_DIV_MASK (0x1f << 17) -#define OSC_DIV_BITS 5 -#define OSC_CP_EN BIT(23) -#define OSC_RESERVED_MASK (0xff << 24) -/* AP_ULPOSC_CON[1,3] */ -#define OSC_MOD_MASK (0x03 << 0) -#define OSC_DIV2_EN BIT(2) - -#define UNIMPLEMENTED_GPIO_BANK 0 - -#ifndef __ASSEMBLER__ - -/* - * Cortex-M4 mod - * Available power saving features: - * 1. FPU freeze - freeze FPU operand when FPU is not used - * 2. LSU gating - gate LSU clock when not LSU operation - * 3. Trace clk disable - gate trace clock - * 4. DCM for CPU stall - gate CPU clock when CPU stall - */ -#define CM4_MODIFICATION REG32(0xE00FE000) -#define CM4_DCM_FEATURE REG32(0xE00FE004) -/* UART, 16550 compatible */ -#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE) -#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset] -#define UART_IRQ(n) CONCAT2(SCP_IRQ_UART, n) -#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX) - -/* Watchdog */ -#define SCP_WDT_BASE (SCP_CFG_BASE + 0x84) -#define SCP_WDT_REG(offset) REG32(SCP_WDT_BASE + offset) -#define SCP_WDT_CFG SCP_WDT_REG(0) -#define SCP_WDT_FREQ 33825 -#define SCP_WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ -#define SCP_WDT_PERIOD(ms) (SCP_WDT_FREQ * (ms) / 1000) -#define SCP_WDT_ENABLE BIT(31) -#define SCP_WDT_RELOAD SCP_WDT_REG(4) -#define SCP_WDT_RELOAD_VALUE 1 - -#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/mt_scp/mt8183/serial_reg.h b/chip/mt_scp/mt8183/serial_reg.h deleted file mode 100644 index 5344566272..0000000000 --- a/chip/mt_scp/mt8183/serial_reg.h +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * UART register map - */ - -#ifndef __CROS_EC_SERIAL_REG_H -#define __CROS_EC_SERIAL_REG_H - -#include "registers.h" - -/* Number of hardware ports */ -#define HW_UART_PORTS 2 - -/* DLAB (Divisor Latch Access Bit) == 0 */ - -/* Data register - * (Read) Rcvr buffer register - * (Write) Xmit holding register - */ -#define UART_DATA(n) UART_REG(n, 0) -/* (Write) Interrupt enable register */ -#define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI BIT(0) /* Recv data int */ -#define UART_IER_THRI BIT(1) /* Xmit holding register int */ -#define UART_IER_RLSI BIT(2) /* Rcvr line status int */ -#define UART_IER_MSI BIT(3) /* Modem status int */ -/* (Read) Interrupt ID register */ -#define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_NO_INT BIT(0) /* No int pending */ -#define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */ -#define UART_IIR_MSI 0x00 -#define UART_IIR_THRI 0x02 -#define UART_IIR_RDI 0x04 -#define UART_IIR_RLSI 0x06 -#define UART_IIR_BUSY 0x07 /* DW APB busy */ -/* (Write) FIFO control register */ -#define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */ -#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */ -#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */ -#define UART_FCR_DMA_SELECT BIT(3) -/* FIFO trigger levels */ -#define UART_FCR_T_TRIG_00 0x00 -#define UART_FCR_T_TRIG_01 0x10 -#define UART_FCR_T_TRIG_10 0x20 -#define UART_FCR_T_TRIG_11 0x30 -#define UART_FCR_R_TRIG_00 0x00 -#define UART_FCR_R_TRIG_01 0x40 -#define UART_FCR_R_TRIG_10 0x80 -#define UART_FCR_R_TRIG_11 0x80 -/* (Write) Line control register */ -#define UART_LCR(n) UART_REG(n, 3) -#define UART_LCR_WLEN5 0 /* Word length 5 bits */ -#define UART_LCR_WLEN6 1 -#define UART_LCR_WLEN7 2 -#define UART_LCR_WLEN8 3 -#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY BIT(3) /* Parity enable */ -#define UART_LCR_EPAR BIT(4) /* Even parity */ -#define UART_LCR_SPAR BIT(5) /* Stick parity */ -#define UART_LCR_SBC BIT(6) /* Set break control */ -#define UART_LCR_DLAB BIT(7) /* Divisor latch access */ -/* (Write) Modem control register */ -#define UART_MCR(n) UART_REG(n, 4) -/* (Read) Line status register */ -#define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR BIT(0) /* Data ready */ -#define UART_LSR_OE BIT(1) /* Overrun error */ -#define UART_LSR_PE BIT(2) /* Parity error */ -#define UART_LSR_FE BIT(3) /* Frame error */ -#define UART_LSR_BI BIT(4) /* Break interrupt */ -#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */ -#define UART_LSR_TEMT BIT(6) /* Xmit empty */ -#define UART_LSR_FIFOE BIT(7) /* FIFO error */ - -/* DLAB == 1 */ - -/* (Write) Divisor latch */ -#define UART_DLL(n) UART_REG(n, 0) /* Low */ -#define UART_DLH(n) UART_REG(n, 1) /* High */ - -/* MTK extension */ -#define UART_HIGHSPEED(n) UART_REG(n, 9) -#define UART_SAMPLE_COUNT(n) UART_REG(n, 10) -#define UART_SAMPLE_POINT(n) UART_REG(n, 11) -#define UART_RATE_FIX(n) UART_REG(n, 13) - -#endif /* __CROS_EC_SERIAL_REG_H */ diff --git a/chip/mt_scp/mt8183/system.c b/chip/mt_scp/mt8183/system.c deleted file mode 100644 index 03f39298c9..0000000000 --- a/chip/mt_scp/mt8183/system.c +++ /dev/null @@ -1,176 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System : hardware specific implementation */ - -#include "clock_chip.h" -#include "console.h" -#include "cpu.h" -#include "cros_version.h" -#include "flash.h" -#include "hooks.h" -#include "host_command.h" -#include "memmap.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" -#include "watchdog.h" - -/* - * SCP_GPR[0] b15-b0 - scratchpad - * SCP_GPR[0] b31-b16 - saved_flags - */ - -int system_set_scratchpad(uint32_t value) -{ - /* Check if value fits in 16 bits */ - if (value & 0xffff0000) - return EC_ERROR_INVAL; - - SCP_GPR[0] = (SCP_GPR[0] & 0xffff0000) | value; - - return EC_SUCCESS; -} - -int system_get_scratchpad(uint32_t *value) -{ - *value = SCP_GPR[0] & 0xffff; - return EC_SUCCESS; -} - -const char *system_get_chip_vendor(void) -{ - return "mtk"; -} - -const char *system_get_chip_name(void) -{ - /* Support only SCP_A for now */ - return "scp_a"; -} - -const char *system_get_chip_revision(void) -{ - return ""; -} - -void chip_pre_init(void) -{ -} - -static void scp_cm4_mod(void) -{ - CM4_MODIFICATION = 3; - CM4_DCM_FEATURE = 3; -} - -static void scp_enable_pirq(void) -{ - /* Enable all peripheral to SCP IRQ, except IPC0. */ - SCP_INTC_IRQ_ENABLE = 0xFFFFFFFE; - SCP_INTC_IRQ_ENABLE_MSB = 0xFFFFFFFF; -} - -void system_pre_init(void) -{ - /* CM4 Modification */ - scp_cm4_mod(); - /* Clock */ - scp_enable_clock(); - /* Peripheral IRQ */ - scp_enable_pirq(); - /* Init dram mapping (and cache) */ - scp_memmap_init(); - /* Disable jump (mt_scp has only RW) and enable MPU. */ - system_disable_jump(); -} - -void system_reset(int flags) -{ - uint32_t save_flags = 0; - - /* Disable interrupts to avoid task swaps during reboot */ - interrupt_disable(); - - /* Save current reset reasons if necessary */ - if (flags & SYSTEM_RESET_PRESERVE_FLAGS) - save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED; - - if (flags & SYSTEM_RESET_LEAVE_AP_OFF) - save_flags |= EC_RESET_FLAG_AP_OFF; - - /* Remember that the software asked us to hard reboot */ - if (flags & SYSTEM_RESET_HARD) - save_flags |= EC_RESET_FLAG_HARD; - - /* Reset flags are 32-bits, but save only 16 bits. */ - ASSERT(!(save_flags >> 16)); - SCP_GPR[0] = (save_flags << 16) | (SCP_GPR[0] & 0xffff); - - /* SCP can not hard reset itself */ - ASSERT(!(flags & SYSTEM_RESET_HARD)); - - if (flags & SYSTEM_RESET_WAIT_EXT) { - int i; - - /* Wait 10 seconds for external reset */ - for (i = 0; i < 1000; i++) { - watchdog_reload(); - udelay(10000); - } - } - - /* Set watchdog timer to small value, and spin wait for watchdog reset */ - SCP_WDT_CFG = 0; - SCP_WDT_CFG = SCP_WDT_ENABLE | SCP_WDT_PERIOD(1); - watchdog_reload(); - while (1) - ; -} - -static void check_reset_cause(void) -{ - uint32_t flags = 0; - uint32_t raw_reset_cause = SCP_GPR[1]; - - /* Set state to power-on */ - SCP_PWRON_STATE = PWRON_DEFAULT; - - if ((raw_reset_cause & 0xffff0000) == PWRON_DEFAULT) { - /* Reboot */ - if (raw_reset_cause & PWRON_WATCHDOG) - flags |= EC_RESET_FLAG_WATCHDOG; - else if (raw_reset_cause & PWRON_RESET) - flags |= EC_RESET_FLAG_POWER_ON; - else - flags |= EC_RESET_FLAG_OTHER; - } else { - /* Power lost restart */ - flags |= EC_RESET_FLAG_POWER_ON; - } - system_set_reset_flags(SCP_GPR[0] >> 16); - SCP_GPR[0] &= 0xffff; -} - -int system_is_reboot_warm(void) -{ - const uint32_t cold_flags = - EC_RESET_FLAG_RESET_PIN | - EC_RESET_FLAG_POWER_ON | - EC_RESET_FLAG_WATCHDOG | - EC_RESET_FLAG_HARD | - EC_RESET_FLAG_SOFT | - EC_RESET_FLAG_HIBERNATE; - - check_reset_cause(); - - return !(system_get_reset_flags() & cold_flags); -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - return EC_ERROR_INVAL; -} diff --git a/chip/mt_scp/mt8183/uart.c b/chip/mt_scp/mt8183/uart.c deleted file mode 100644 index 7907f9537d..0000000000 --- a/chip/mt_scp/mt8183/uart.c +++ /dev/null @@ -1,179 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SCP UART module */ - -#include "clock_chip.h" -#include "console.h" -#include "registers.h" -#include "serial_reg.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" - -/* Console UART index */ -#define UARTN CONFIG_UART_CONSOLE -#define UART_IDLE_WAIT_US 500 - -static uint8_t uart_done, tx_started; - -int uart_init_done(void) -{ - /* - * TODO: AP UART support - * When access AP UART port, wait for AP peripheral clock - */ - return uart_done; -} - -void uart_tx_start(void) -{ - tx_started = 1; - - /* AP UART mode doesn't support interrupt */ - if (UARTN >= SCP_UART_COUNT) - return; - - if (UART_IER(UARTN) & UART_IER_THRI) - return; - disable_sleep(SLEEP_MASK_UART); - UART_IER(UARTN) |= UART_IER_THRI; -} - -void uart_tx_stop(void) -{ - tx_started = 0; - - /* AP UART mode doesn't support interrupt */ - if (UARTN >= SCP_UART_COUNT) - return; - - UART_IER(UARTN) &= ~UART_IER_THRI; - enable_sleep(SLEEP_MASK_UART); -} - -void uart_tx_flush(void) -{ - while (!(UART_LSR(UARTN) & UART_LSR_TEMT)) - ; -} - -int uart_tx_ready(void) -{ - /* Check xmit FIFO empty */ - return UART_LSR(UARTN) & UART_LSR_THRE; -} - -int uart_rx_available(void) -{ - /* Check rcvr data ready */ - return UART_LSR(UARTN) & UART_LSR_DR; -} - -void uart_write_char(char c) -{ - while (!uart_tx_ready()) - ; - - UART_DATA(UARTN) = c; -} - -int uart_read_char(void) -{ - return UART_DATA(UARTN); -} - -void uart_process(void) -{ - uart_process_input(); - uart_process_output(); -} - -#if (UARTN < SCP_UART_COUNT) -DECLARE_IRQ(UART_IRQ(UARTN), uart_interrupt, 2); -void uart_interrupt(void) -{ - uint8_t ier; - - task_clear_pending_irq(UART_IRQ(UARTN)); - uart_process(); - ier = UART_IER(UARTN); - UART_IER(UARTN) = 0; - UART_IER(UARTN) = ier; -} - -DECLARE_IRQ(UART_RX_IRQ(UARTN), uart_rx_interrupt, 2); -void uart_rx_interrupt(void) -{ - uint8_t ier; - - task_clear_pending_irq(UART_RX_IRQ(UARTN)); - SCP_INTC_UART_RX_IRQ &= ~BIT(UARTN); - uart_process(); - ier = UART_IER(UARTN); - UART_IER(UARTN) = 0; - UART_IER(UARTN) = ier; - SCP_INTC_UART_RX_IRQ |= 1 << UARTN; -} -#endif - -void uart_task(void) -{ -#if (UARTN >= SCP_UART_COUNT) - while (1) { - if (uart_rx_available() || tx_started) - uart_process(); - else - task_wait_event(UART_IDLE_WAIT_US); - } -#endif -} - -void uart_init(void) -{ - const uint32_t baud_rate = CONFIG_UART_BAUD_RATE; - /* - * UART clock source is set to ULPOSC1 / 10 below. - * - * TODO(b:134035444): We could get slightly more precise frequency by - * using the _measured_ ULPOSC1 frequency (instead of the target). - */ - const uint32_t uart_clock = ULPOSC1_CLOCK_MHZ * 1000 / 10 * 1000; - const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16); - - /* Init clock */ -#if UARTN == 0 - SCP_CLK_UART = CLK_UART_SEL_ULPOSC1_DIV10; - SCP_CLK_GATE |= CG_UART_M | CG_UART_B | CG_UART_RSTN; -#elif UARTN == 1 - SCP_CLK_UART = CLK_UART1_SEL_ULPOSC1_DIV10; - SCP_CLK_GATE |= CG_UART1_M | CG_UART1_B | CG_UART1_RSTN; -#endif - - /* Init and clear FIFO */ - UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO - | UART_FCR_CLEAR_RCVR - | UART_FCR_CLEAR_XMIT; - /* Line control: parity none, 8 bit, 1 stop bit */ - UART_LCR(UARTN) = UART_LCR_WLEN8; - /* For baud rate <= 115200 */ - UART_HIGHSPEED(UARTN) = 0; - /* DLAB = 1 and update DLL DLH */ - UART_LCR(UARTN) |= UART_LCR_DLAB; - UART_DLL(UARTN) = div & 0xff; - UART_DLH(UARTN) = (div >> 8) & 0xff; - UART_LCR(UARTN) &= ~UART_LCR_DLAB; - UART_IER(UARTN) |= UART_IER_RDI; - -#if (UARTN < SCP_UART_COUNT) - task_enable_irq(UART_IRQ(UARTN)); - task_enable_irq(UART_RX_IRQ(UARTN)); - /* UART RX IRQ needs an extra enable */ - SCP_INTC_UART_RX_IRQ |= 1 << UARTN; -#endif - gpio_config_module(MODULE_UART, 1); - uart_done = 1; -} diff --git a/chip/mt_scp/mt8183/watchdog.c b/chip/mt_scp/mt8183/watchdog.c deleted file mode 100644 index 74e2cad8e5..0000000000 --- a/chip/mt_scp/mt8183/watchdog.c +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "common.h" -#include "hooks.h" -#include "panic.h" -#include "registers.h" -#include "watchdog.h" - -void watchdog_reload(void) -{ - SCP_WDT_RELOAD = SCP_WDT_RELOAD_VALUE; -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ - const uint32_t watchdog_timeout = - SCP_WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS); - - /* Disable watchdog */ - SCP_WDT_CFG = 0; - /* Enable watchdog */ - SCP_WDT_CFG = SCP_WDT_ENABLE | watchdog_timeout; - /* Reload watchdog */ - watchdog_reload(); - - return EC_SUCCESS; -} diff --git a/chip/mt_scp/mt8192/build.mk b/chip/mt_scp/mt8192/build.mk deleted file mode 100644 index c81bd83595..0000000000 --- a/chip/mt_scp/mt8192/build.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Required chip modules -chip-y+=$(CHIP_VARIANT)/uart.o -chip-y+=$(CHIP_VARIANT)/clock.o -chip-y+=$(CHIP_VARIANT)/video.o - diff --git a/chip/mt_scp/mt8192/clock.c b/chip/mt_scp/mt8192/clock.c deleted file mode 100644 index 43f570fc62..0000000000 --- a/chip/mt_scp/mt8192/clock.c +++ /dev/null @@ -1,369 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks, PLL and power settings */ - -#include <assert.h> -#include <string.h> - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "csr.h" -#include "ec_commands.h" -#include "power.h" -#include "registers.h" -#include "timer.h" - -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) - -enum scp_clock_source { - SCP_CLK_26M = CLK_SW_SEL_26M, - SCP_CLK_32K = CLK_SW_SEL_32K, - SCP_CLK_ULPOSC2 = CLK_SW_SEL_ULPOSC2, - SCP_CLK_ULPOSC1 = CLK_SW_SEL_ULPOSC1, -}; - -static struct opp_ulposc_cfg { - uint32_t osc; - uint32_t div; - uint32_t fband; - uint32_t mod; - uint32_t cali; - uint32_t target_mhz; -} opp[] = { - { - .osc = 1, .target_mhz = 196, .div = 20, .fband = 10, .mod = 3, - .cali = 64, - }, - { - .osc = 0, .target_mhz = 260, .div = 14, .fband = 2, .mod = 0, - .cali = 64, - }, - { - .osc = 1, .target_mhz = 280, .div = 20, .fband = 2, .mod = 0, - .cali = 64, - }, - { - .osc = 1, .target_mhz = 360, .div = 20, .fband = 10, .mod = 0, - .cali = 64, - }, -}; - -static inline void clock_busy_udelay(int usec) -{ - /* - * Delaying by busy-looping, for place that can't use udelay because of - * the clock not configured yet. The value 28 is chosen approximately - * from experiment. - * - * `volatile' in order to avoid compiler to optimize the function out - * (otherwise, the function will be eliminated). - */ - volatile int i = usec * 28; - - while (--i) - ; -} - -static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp) -{ - unsigned int val = 0; - - /* set div */ - val |= opp->div << OSC_DIV_SHIFT; - /* set F-band; I-band = 82 */ - val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT); - /* set calibration */ - val |= opp->cali; - /* set control register 0 */ - AP_ULPOSC_CON0(opp->osc) = val; - - /* set mod */ - val = opp->mod << OSC_MOD_SHIFT; - /* rsv2 = 0, rsv1 = 41, cali_32k = 0 */ - val |= 41 << OSC_RSV1_SHIFT; - /* set control register 1 */ - AP_ULPOSC_CON1(opp->osc) = val; - - /* bias = 64 */ - AP_ULPOSC_CON2(opp->osc) = 64; -} - -static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp, - uint32_t cali_val) -{ - uint32_t val; - - val = AP_ULPOSC_CON0(opp->osc); - val &= ~OSC_CALI_MASK; - val |= cali_val; - AP_ULPOSC_CON0(opp->osc) = val; - - clock_busy_udelay(50); -} - -static uint32_t clock_ulposc_measure_freq(uint32_t osc) -{ - uint32_t result = 0; - int cnt; - - /* before select meter clock input, bit[1:0] = b00 */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | - DBG_MODE_SET_CLOCK; - - /* select source, bit[21:16] = clk_src */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | - (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : - DBG_BIST_SOURCE_ULPOSC2); - - /* set meter divisor to 1, bit[31:24] = b00000000 */ - AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) | - MISC_METER_DIV_1; - - /* enable frequency meter, without start */ - AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE; - - /* trigger frequency meter start */ - AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN; - - /* - * Frequency meter counts cycles in 1 / (26 * 1024) second period. - * freq_in_hz = freq_counter * 26 * 1024 - * - * The hardware takes 38us to count cycles. Delay up to 100us, - * as clock_busy_udelay may not be accurate when sysclk is not 26Mhz - * (e.g. when recalibrating/measuring after boot). - */ - for (cnt = 100; cnt > 0; --cnt) { - clock_busy_udelay(1); - if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) { - result = CFG_FREQ_COUNTER(AP_SCP_CFG_1); - break; - } - } - - /* disable freq meter */ - AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE; - - return result; -} - -#define CAL_MIS_RATE 40 -static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp) -{ - uint32_t curr, target; - - curr = clock_ulposc_measure_freq(opp->osc); - target = opp->target_mhz * 1024 / 26; - - /* check if calibrated value is in the range of target value +- 4% */ - if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) && - curr < (target * (1000 + CAL_MIS_RATE) / 1000)) - return 1; - else - return 0; -} - -static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp) -{ - uint32_t current_val = 0; - uint32_t target_val = opp->target_mhz * 1024 / 26; - uint32_t middle, min = 0, max = OSC_CALI_MASK; - uint32_t diff_by_min, diff_by_max, cal_result; - - do { - middle = (min + max) / 2; - if (middle == min) - break; - - clock_ulposc_config_cali(opp, middle); - current_val = clock_ulposc_measure_freq(opp->osc); - - if (current_val > target_val) - max = middle; - else - min = middle; - } while (min <= max); - - clock_ulposc_config_cali(opp, min); - current_val = clock_ulposc_measure_freq(opp->osc); - if (current_val > target_val) - diff_by_min = current_val - target_val; - else - diff_by_min = target_val - current_val; - - clock_ulposc_config_cali(opp, max); - current_val = clock_ulposc_measure_freq(opp->osc); - if (current_val > target_val) - diff_by_max = current_val - target_val; - else - diff_by_max = target_val - current_val; - - if (diff_by_min < diff_by_max) - cal_result = min; - else - cal_result = max; - - clock_ulposc_config_cali(opp, cal_result); - if (!clock_ulposc_is_calibrated(opp)) - assert(0); - - return cal_result; -} - -static void clock_high_enable(int osc) -{ - /* enable high speed clock */ - SCP_CLK_ENABLE |= CLK_HIGH_EN; - - switch (osc) { - case 0: - /* after 150us, enable ULPOSC */ - clock_busy_udelay(150); - SCP_CLK_ENABLE |= CLK_HIGH_CG; - break; - case 1: - /* turn off ULPOSC2 high-core-disable switch */ - SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB; - /* after 150us, turn on ULPOSC2 high core clock gate */ - clock_busy_udelay(150); - SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG; - clock_busy_udelay(50); - break; - default: - break; - } -} - -static void clock_high_disable(int osc) -{ - switch (osc) { - case 0: - SCP_CLK_ENABLE &= ~CLK_HIGH_CG; - clock_busy_udelay(50); - SCP_CLK_ENABLE &= ~CLK_HIGH_EN; - clock_busy_udelay(50); - break; - case 1: - SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG; - clock_busy_udelay(50); - SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB; - clock_busy_udelay(50); - break; - default: - break; - } -} - -static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp) -{ - /* - * ULPOSC1(osc=0) is already - * - calibrated - * - enabled in coreboot - * - used by pmic wrapper - */ - if (opp->osc != 0) { - clock_high_disable(opp->osc); - clock_ulposc_config_default(opp); - clock_high_enable(opp->osc); - } - - /* Calibrate only if it is not accurate enough. */ - if (!clock_ulposc_is_calibrated(opp)) - opp->cali = clock_ulposc_process_cali(opp); - -#ifdef DEBUG - CPRINTF("osc:%u, target=%uMHz, cal:%u\n", - opp->osc, opp->target_mhz, opp->cali); -#endif -} - -static void clock_select_clock(enum scp_clock_source src) -{ - /* - * DIV2 divider takes precedence over clock selection to prevent - * over-clocking. - */ - if (src == SCP_CLK_ULPOSC1) - SCP_CLK_DIV_SEL = CLK_DIV_SEL2; - - SCP_CLK_SW_SEL = src; - - if (src != SCP_CLK_ULPOSC1) - SCP_CLK_DIV_SEL = CLK_DIV_SEL1; -} - -__override void -power_chipset_handle_host_sleep_event(enum host_sleep_event state, - struct host_sleep_event_context *ctx) -{ - if (state == HOST_SLEEP_EVENT_S3_SUSPEND) { - CPRINTS("AP suspend"); - clock_select_clock(SCP_CLK_ULPOSC1); - } else if (state == HOST_SLEEP_EVENT_S3_RESUME) { - CPRINTS("AP resume"); - clock_select_clock(SCP_CLK_ULPOSC2); - } -} - -void clock_init(void) -{ - int i; - - /* select default 26M system clock */ - clock_select_clock(SCP_CLK_26M); - - /* set VREQ to HW mode */ - SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL; - SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL; - SCP_SEC_CTRL &= ~VREQ_SECURE_DIS; - - /* set DDREN to auto mode */ - SCP_SYS_CTRL |= AUTO_DDREN; - - /* set settle time */ - SCP_CLK_SYS_VAL = - (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1); - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1); - SCP_SLEEP_CTRL = - (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1); - - /* turn off ULPOSC2 */ - SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB; - - /* calibrate ULPOSC */ - for (i = 0; i < ARRAY_SIZE(opp); ++i) - clock_calibrate_ulposc(&opp[i]); - - /* select ULPOSC2 high speed CPU clock */ - clock_select_clock(SCP_CLK_ULPOSC2); - - /* select BCLK to use ULPOSC1 / 8 = 260MHz / 8 = 32.5MHz */ - SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8; - - /* enable default clock gate */ - SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 | - CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK; -} - -#ifdef DEBUG -int command_ulposc(int argc, char *argv[]) -{ - int i; - - for (i = 0; i <= 1; ++i) - ccprintf("ULPOSC%u frequency: %u kHz\n", - i + 1, - clock_ulposc_measure_freq(i) * 26 * 1000 / 1024); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]", - "Measure ULPOSC frequency"); -#endif diff --git a/chip/mt_scp/mt8192/clock_regs.h b/chip/mt_scp/mt8192/clock_regs.h deleted file mode 100644 index 5928ca0473..0000000000 --- a/chip/mt_scp/mt8192/clock_regs.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SCP clock module registers */ - -#ifndef __CROS_EC_CLOCK_REGS_H -#define __CROS_EC_CLOCK_REGS_H - -/* clock source select */ -#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000) -#define CLK_SW_SEL_26M 0 -#define CLK_SW_SEL_32K 1 -#define CLK_SW_SEL_ULPOSC2 2 -#define CLK_SW_SEL_ULPOSC1 3 -#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004) -#define CLK_HIGH_EN BIT(1) /* ULPOSC */ -#define CLK_HIGH_CG BIT(2) -/* clock general control */ -#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C) -#define VREQ_PMIC_WRAP_SEL (0x2) - -/* TOPCK clk */ -#define TOPCK_BASE AP_REG_BASE -#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140) -#define MISC_METER_DIVISOR_MASK 0xff000000 -#define MISC_METER_DIV_1 0 -/* OSC meter */ -#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C) -#define DBG_MODE_MASK 3 -#define DBG_MODE_SET_CLOCK 0 -#define DBG_BIST_SOURCE_MASK (0x3f << 16) -#define DBG_BIST_SOURCE_ULPOSC1 (0x25 << 16) -#define DBG_BIST_SOURCE_ULPOSC2 (0x24 << 16) -#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220) -#define CFG_FREQ_METER_RUN BIT(4) -#define CFG_FREQ_METER_ENABLE BIT(12) -#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224) -#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF) -/* - * ULPOSC - * osc: 0 for ULPOSC1, 1 for ULPOSC2. - */ -#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0) -#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4) -#define AP_ULPOSC_CON2_BASE (AP_REG_BASE + 0xC2B8) -#define AP_ULPOSC_CON0(osc) \ - REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10) -#define AP_ULPOSC_CON1(osc) \ - REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10) -#define AP_ULPOSC_CON2(osc) \ - REG32(AP_ULPOSC_CON2_BASE + (osc) * 0x10) -/* - * AP_ULPOSC_CON0 - * bit0-6: calibration - * bit7-13: iband - * bit14-17: fband - * bit18-23: div - * bit24: cp_en - * bit25-31: reserved - */ -#define OSC_CALI_MASK 0x7f -#define OSC_IBAND_SHIFT 7 -#define OSC_FBAND_SHIFT 14 -#define OSC_DIV_SHIFT 18 -#define OSC_CP_EN BIT(24) -/* AP_ULPOSC_CON1 - * bit0-7: 32K calibration - * bit 8-15: rsv1 - * bit 16-23: rsv2 - * bit 24-25: mod - * bit26: div2_en - * bit27-31: reserved - */ -#define OSC_RSV1_SHIFT 8 -#define OSC_RSV2_SHIFT 16 -#define OSC_MOD_SHIFT 24 -#define OSC_DIV2_EN BIT(26) -/* AP_ULPOSC_CON2 - * bit0-7: bias - * bit8-31: reserved - */ - -#endif /* __CROS_EC_CLOCK_REGS_H */ diff --git a/chip/mt_scp/mt8192/intc.h b/chip/mt_scp/mt8192/intc.h deleted file mode 100644 index 63eb1243b3..0000000000 --- a/chip/mt_scp/mt8192/intc.h +++ /dev/null @@ -1,126 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_INTC_H -#define __CROS_EC_INTC_H - -/* INTC */ -#define SCP_INTC_IRQ_POL0 0xef001f20 -#define SCP_INTC_IRQ_POL1 0x0800001d -#define SCP_INTC_IRQ_POL2 0x00000020 -#define SCP_INTC_GRP_LEN 3 -#define SCP_INTC_IRQ_COUNT 96 - -/* IRQ numbers */ -#define SCP_IRQ_GIPC_IN0 0 -#define SCP_IRQ_GIPC_IN1 1 -#define SCP_IRQ_GIPC_IN2 2 -#define SCP_IRQ_GIPC_IN3 3 -/* 4 */ -#define SCP_IRQ_SPM 4 -#define SCP_IRQ_AP_CIRQ 5 -#define SCP_IRQ_EINT 6 -#define SCP_IRQ_PMIC 7 -/* 8 */ -#define SCP_IRQ_UART0_TX 8 -#define SCP_IRQ_UART1_TX 9 -#define SCP_IRQ_I2C0 10 -#define SCP_IRQ_I2C1_0 11 -/* 12 */ -#define SCP_IRQ_BUS_DBG_TRACKER 12 -#define SCP_IRQ_CLK_CTRL 13 -#define SCP_IRQ_VOW 14 -#define SCP_IRQ_TIMER0 15 -/* 16 */ -#define SCP_IRQ_TIMER1 16 -#define SCP_IRQ_TIMER2 17 -#define SCP_IRQ_TIMER3 18 -#define SCP_IRQ_TIMER4 19 -/* 20 */ -#define SCP_IRQ_TIMER5 20 -#define SCP_IRQ_OS_TIMER 21 -#define SCP_IRQ_UART0_RX 22 -#define SCP_IRQ_UART1_RX 23 -/* 24 */ -#define SCP_IRQ_GDMA 24 -#define SCP_IRQ_AUDIO 25 -#define SCP_IRQ_MD_DSP 26 -#define SCP_IRQ_ADSP 27 -/* 28 */ -#define SCP_IRQ_CPU_TICK 28 -#define SCP_IRQ_SPI0 29 -#define SCP_IRQ_SPI1 30 -#define SCP_IRQ_SPI2 31 -/* 32 */ -#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32 -#define SCP_IRQ_DBG 33 -#define SCP_IRQ_CCIF0 34 -#define SCP_IRQ_CCIF1 35 -/* 36 */ -#define SCP_IRQ_CCIF2 36 -#define SCP_IRQ_WDT 37 -#define SCP_IRQ_USB0 38 -#define SCP_IRQ_USB1 39 -/* 40 */ -#define SCP_IRQ_DPMAIF 40 -#define SCP_IRQ_INFRA 41 -#define SCP_IRQ_CLK_CTRL_CORE 42 -#define SCP_IRQ_CLK_CTRL2_CORE 43 -/* 44 */ -#define SCP_IRQ_CLK_CTRL2 44 -#define SCP_IRQ_GIPC_IN4 45 /* HALT */ -#define SCP_IRQ_PERIBUS_TIMEOUT 46 -#define SCP_IRQ_INFRABUS_TIMEOUT 47 -/* 48 */ -#define SCP_IRQ_MET0 48 -#define SCP_IRQ_MET1 49 -#define SCP_IRQ_MET2 50 -#define SCP_IRQ_MET3 51 -/* 52 */ -#define SCP_IRQ_AP_WDT 52 -#define SCP_IRQ_L2TCM_SEC_VIO 53 -#define SCP_IRQ_CPU_TICK1 54 -#define SCP_IRQ_MAD_DATAIN 55 -/* 56 */ -#define SCP_IRQ_I3C0_IBI_WAKE 56 -#define SCP_IRQ_I3C1_IBI_WAKE 57 -#define SCP_IRQ_I3C2_IBI_WAKE 58 -#define SCP_IRQ_APU_ENGINE 59 -/* 60 */ -#define SCP_IRQ_MBOX0 60 -#define SCP_IRQ_MBOX1 61 -#define SCP_IRQ_MBOX2 62 -#define SCP_IRQ_MBOX3 63 -/* 64 */ -#define SCP_IRQ_MBOX4 64 -#define SCP_IRQ_SYS_CLK_REQ 65 -#define SCP_IRQ_BUS_REQ 66 -#define SCP_IRQ_APSRC_REQ 67 -/* 68 */ -#define SCP_IRQ_APU_MBOX 68 -#define SCP_IRQ_DEVAPC_SECURE_VIO 69 -/* 72 */ -/* 76 */ -#define SCP_IRQ_I2C1_2 78 -#define SCP_IRQ_I2C2 79 -/* 80 */ -#define SCP_IRQ_AUD2AUDIODSP 80 -#define SCP_IRQ_AUD2AUDIODSP_2 81 -#define SCP_IRQ_CONN2ADSP_A2DPOL 82 -#define SCP_IRQ_CONN2ADSP_BTCVSD 83 -/* 84 */ -#define SCP_IRQ_CONN2ADSP_BLEISO 84 -#define SCP_IRQ_PCIE2ADSP 85 -#define SCP_IRQ_APU2ADSP_ENGINE 86 -#define SCP_IRQ_APU2ADSP_MBOX 87 -/* 88 */ -#define SCP_IRQ_CCIF3 88 -#define SCP_IRQ_I2C_DMA0 89 -#define SCP_IRQ_I2C_DMA1 90 -#define SCP_IRQ_I2C_DMA2 91 -/* 92 */ -#define SCP_IRQ_I2C_DMA3 92 - -#endif /* __CROS_EC_INTC_H */ diff --git a/chip/mt_scp/mt8192/uart.c b/chip/mt_scp/mt8192/uart.c deleted file mode 100644 index 0ebb93cbb4..0000000000 --- a/chip/mt_scp/mt8192/uart.c +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SCP UART module for MT8192 specific */ - -#include "uart_regs.h" - -/* - * UARTN == 0, SCP UART0 - * UARTN == 1, SCP UART1 - * UARTN == 2, AP UART1 - */ -#define UARTN CONFIG_UART_CONSOLE - -void uart_init_pinmux(void) -{ -#if UARTN == 0 - SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC); - SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST; - - /* set AP GPIO164 and GPIO165 to alt func 3 */ - AP_GPIO_MODE20_CLR = 0x00770000; - AP_GPIO_MODE20_SET = 0x00330000; -#elif UARTN == 1 - SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_ULPOSC); - SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST; -#endif -} diff --git a/chip/mt_scp/mt8192/video.c b/chip/mt_scp/mt8192/video.c deleted file mode 100644 index 2f9b9a7808..0000000000 --- a/chip/mt_scp/mt8192/video.c +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "video.h" - -uint32_t video_get_enc_capability(void) -{ - return VENC_CAP_4K; -} - -uint32_t video_get_dec_capability(void) -{ - return VDEC_CAP_4K_DISABLED | VDEC_CAP_MM21 | - VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME | - VDEC_CAP_VP9_FRAME; -} diff --git a/chip/mt_scp/mt8195/build.mk b/chip/mt_scp/mt8195/build.mk deleted file mode 100644 index c81bd83595..0000000000 --- a/chip/mt_scp/mt8195/build.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Required chip modules -chip-y+=$(CHIP_VARIANT)/uart.o -chip-y+=$(CHIP_VARIANT)/clock.o -chip-y+=$(CHIP_VARIANT)/video.o - diff --git a/chip/mt_scp/mt8195/clock.c b/chip/mt_scp/mt8195/clock.c deleted file mode 100644 index c6bf3cbc79..0000000000 --- a/chip/mt_scp/mt8195/clock.c +++ /dev/null @@ -1,441 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks, PLL and power settings */ - -#include <assert.h> -#include <string.h> - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "csr.h" -#include "ec_commands.h" -#include "power.h" -#include "registers.h" -#include "timer.h" - -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) - -enum scp_clock_source { - SCP_CLK_SYSTEM, - SCP_CLK_32K, - SCP_CLK_ULPOSC1, - SCP_CLK_ULPOSC2_LOW_SPEED, - SCP_CLK_ULPOSC2_HIGH_SPEED, -}; - -enum { - OPP_ULPOSC2_LOW_SPEED, - OPP_ULPOSC2_HIGH_SPEED, -}; - -static struct opp_ulposc_cfg { - uint32_t osc; - uint32_t div; - uint32_t fband; - uint32_t mod; - uint32_t cali; - uint32_t target_mhz; - uint32_t clk_div; -} opp[] = { - [OPP_ULPOSC2_LOW_SPEED] = { - .osc = 1, .target_mhz = 326, .clk_div = CLK_DIV_SEL2, .div = 19, - .fband = 10, .mod = 0, .cali = 64, /* 326MHz / 2 = 163MHz */ - }, - [OPP_ULPOSC2_HIGH_SPEED] = { - .osc = 1, .target_mhz = 360, .clk_div = CLK_DIV_SEL1, .div = 21, - .fband = 10, .mod = 0, .cali = 64, /* 360MHz / 1 = 360MHz */ - }, -}; - -static inline void clock_busy_udelay(int usec) -{ - /* - * Delaying by busy-looping, for place that can't use udelay because of - * the clock not configured yet. The value 28 is chosen approximately - * from experiment. - * - * `volatile' in order to avoid compiler to optimize the function out - * (otherwise, the function will be eliminated). - */ - volatile int i = usec * 28; - - while (--i) - ; -} - -static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp) -{ - uint32_t val = 0; - - /* set mod, div2_en = 0, cp_en = 0 */ - val |= opp->mod << OSC_MOD_SHIFT; - /* set div */ - val |= opp->div << OSC_DIV_SHIFT; - /* set F-band, I-band = 82 */ - val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT); - /* set calibration */ - val |= opp->cali; - /* set control register 0 */ - AP_ULPOSC_CON0(opp->osc) = val; - - clock_busy_udelay(50); - - /* bias = 65 */ - val = 65 << OSC_BIAS_SHIFT; - /* rsv2 = 0, rsv1 = 41, cali_32k = 0 */ - val |= 41 << OSC_RSV1_SHIFT; - /* set control register 1 */ - AP_ULPOSC_CON1(opp->osc) = val; - - /* set settle time */ - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(2); -} - -static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp, - uint32_t cali_val) -{ - uint32_t val; - - val = AP_ULPOSC_CON0(opp->osc); - val &= ~OSC_CALI_MASK; - val |= cali_val; - AP_ULPOSC_CON0(opp->osc) = val; - opp->cali = cali_val; - - clock_busy_udelay(50); -} - -static uint32_t clock_ulposc_measure_freq(uint32_t osc) -{ - uint32_t result = 0; - int cnt; - uint32_t cali_0 = AP_CLK26CALI_0; - uint32_t cali_1 = AP_CLK26CALI_1; - uint32_t dbg_cfg = AP_CLK_DBG_CFG; - uint32_t misc_cfg = AP_CLK_MISC_CFG_0; - - /* Set ckgen_load_cnt: CLK26CALI_1[25:16] */ - AP_CLK26CALI_1 = CFG_CKGEN_LOAD_CNT; - - /* before select meter clock input, bit[1:0] = b00 */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | - DBG_MODE_SET_CLOCK; - - /* select monclk_ext2fqmtr_sel: AP_CLK_DBG_CFG[14:8] */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | - (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : - DBG_BIST_SOURCE_ULPOSC2); - - /* set meter divisor to 1, bit[31:24] = b00000000 */ - AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) | - MISC_METER_DIV_1; - - /* enable frequency meter, without start */ - AP_CLK26CALI_0 |= CFG_FREQ_METER_ENABLE; - - /* trigger frequency meter start */ - AP_CLK26CALI_0 |= CFG_FREQ_METER_RUN; - - clock_busy_udelay(45); - - for (cnt = 10000; cnt > 0; --cnt) { - clock_busy_udelay(10); - if (!(AP_CLK26CALI_0 & CFG_FREQ_METER_RUN)) { - result = CFG_FREQ_COUNTER(AP_CLK26CALI_1); - break; - } - } - - AP_CLK26CALI_0 = cali_0; - AP_CLK26CALI_1 = cali_1; - AP_CLK_DBG_CFG = dbg_cfg; - AP_CLK_MISC_CFG_0 = misc_cfg; - - /* disable freq meter */ - AP_CLK26CALI_0 &= ~CFG_FREQ_METER_ENABLE; - - return result; -} - -#define CAL_MIS_RATE 40 -static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp) -{ - uint32_t curr, target; - - curr = clock_ulposc_measure_freq(opp->osc); - target = opp->target_mhz * 512 / 26; - -#ifdef DEBUG - CPRINTF("osc:%u, target=%uMHz, curr=%uMHz, cali:%u\n", - opp->osc, opp->target_mhz, (curr * 26) / 512, opp->cali); -#endif - - /* check if calibrated value is in the range of target value +- 4% */ - if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) && - curr < (target * (1000 + CAL_MIS_RATE) / 1000)) - return 1; - else - return 0; -} - -static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp) -{ - uint32_t current_val = 0; - uint32_t target_val = opp->target_mhz * 512 / 26; - uint32_t middle, min = 0, max = OSC_CALI_MASK; - uint32_t diff_by_min, diff_by_max, cal_result; - - do { - middle = (min + max) / 2; - if (middle == min) - break; - - clock_ulposc_config_cali(opp, middle); - current_val = clock_ulposc_measure_freq(opp->osc); - - if (current_val > target_val) - max = middle; - else - min = middle; - } while (min <= max); - - clock_ulposc_config_cali(opp, min); - current_val = clock_ulposc_measure_freq(opp->osc); - if (current_val > target_val) - diff_by_min = current_val - target_val; - else - diff_by_min = target_val - current_val; - - clock_ulposc_config_cali(opp, max); - current_val = clock_ulposc_measure_freq(opp->osc); - if (current_val > target_val) - diff_by_max = current_val - target_val; - else - diff_by_max = target_val - current_val; - - if (diff_by_min < diff_by_max) - cal_result = min; - else - cal_result = max; - - clock_ulposc_config_cali(opp, cal_result); - if (!clock_ulposc_is_calibrated(opp)) - assert(0); - - return cal_result; -} - -static void clock_high_enable(int osc) -{ - /* enable high speed clock */ - SCP_CLK_ENABLE |= CLK_HIGH_EN; - - switch (osc) { - case 0: - /* after 150us, enable ULPOSC */ - clock_busy_udelay(150); - SCP_CLK_ENABLE |= CLK_HIGH_CG | CLK_HIGH_EN; - - /* topck ulposc1 clk gating off */ - AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CK; - /* select topck ulposc1 as scp clk parent */ - AP_CLK_CFG_29_CLR = ULPOSC1_CLK_SEL; - - AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE; - clock_busy_udelay(50); - break; - case 1: - /* turn off ULPOSC2 high-core-disable switch */ - SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB; - /* after 150us, scp requests ULPOSC2 high core clock */ - clock_busy_udelay(150); - SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG; - SCP_CLK_ENABLE &= ~CLK_HIGH_CG; - clock_busy_udelay(50); - - /* topck ulposc2 clk gating off */ - AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CORE_CK; - /* select topck ulposc2 as scp clk parent */ - AP_CLK_CFG_29_CLR = ULPOSC2_CLK_SEL; - - AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE; - clock_busy_udelay(50); - break; - default: - break; - } -} - -static void clock_high_disable(int osc) -{ - switch (osc) { - case 0: - /* topck ulposc1 clk gating on */ - AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CK; - AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE; - clock_busy_udelay(50); - - /* scp doesn't request ulposc1 clk */ - SCP_CLK_ENABLE &= ~CLK_HIGH_CG; - clock_busy_udelay(50); - SCP_CLK_ENABLE &= ~CLK_HIGH_EN; - clock_busy_udelay(50); - break; - case 1: - /* topck ulposc2 clk gating on */ - AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CORE_CK; - AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE; - clock_busy_udelay(50); - - /* scp doesn't request ulposc2 clk */ - SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG; - clock_busy_udelay(50); - SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB; - clock_busy_udelay(50); - break; - default: - break; - } -} - -static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp) -{ - /* - * ULPOSC1(osc=0) is already - * - calibrated - * - enabled in coreboot - * - used by pmic wrapper - */ - if (opp->osc != 0) { - clock_high_disable(opp->osc); - clock_ulposc_config_default(opp); - clock_high_enable(opp->osc); - } - - /* Calibrate only if it is not accurate enough. */ - if (!clock_ulposc_is_calibrated(opp)) - opp->cali = clock_ulposc_process_cali(opp); -} - -static void clock_select_clock(enum scp_clock_source src) -{ - uint32_t sel; - uint32_t div; - - switch (src) { - case SCP_CLK_SYSTEM: - div = CLK_DIV_SEL1; - sel = CLK_SW_SEL_SYSTEM; - break; - case SCP_CLK_32K: - div = CLK_DIV_SEL1; - sel = CLK_SW_SEL_32K; - break; - case SCP_CLK_ULPOSC1: - div = CLK_DIV_SEL1; - sel = CLK_SW_SEL_ULPOSC1; - break; - case SCP_CLK_ULPOSC2_LOW_SPEED: - /* parking at scp system clk until ulposc clk is ready */ - clock_select_clock(SCP_CLK_SYSTEM); - - clock_ulposc_config_cali(&opp[OPP_ULPOSC2_LOW_SPEED], - opp[OPP_ULPOSC2_LOW_SPEED].cali); - div = opp[OPP_ULPOSC2_LOW_SPEED].clk_div; - - sel = CLK_SW_SEL_ULPOSC2; - break; - case SCP_CLK_ULPOSC2_HIGH_SPEED: - /* parking at scp system clk until ulposc clk is ready */ - clock_select_clock(SCP_CLK_SYSTEM); - - clock_ulposc_config_cali(&opp[OPP_ULPOSC2_HIGH_SPEED], - opp[OPP_ULPOSC2_HIGH_SPEED].cali); - div = opp[OPP_ULPOSC2_HIGH_SPEED].clk_div; - - sel = CLK_SW_SEL_ULPOSC2; - break; - default: - div = CLK_DIV_SEL1; - sel = CLK_SW_SEL_SYSTEM; - break; - } - - SCP_CLK_DIV_SEL = div; - SCP_CLK_SW_SEL = sel; -} - -__override void -power_chipset_handle_host_sleep_event(enum host_sleep_event state, - struct host_sleep_event_context *ctx) -{ - if (state == HOST_SLEEP_EVENT_S3_SUSPEND) { - CPRINTS("AP suspend"); - clock_select_clock(SCP_CLK_32K); - } else if (state == HOST_SLEEP_EVENT_S3_RESUME) { - CPRINTS("AP resume"); - clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED); - } -} - -void clock_init(void) -{ - uint32_t i; - - /* select scp system clock (default 26MHz) */ - clock_select_clock(SCP_CLK_SYSTEM); - - /* set VREQ to HW mode */ - SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL; - SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL; - SCP_SEC_CTRL &= ~VREQ_SECURE_DIS; - - /* set DDREN to auto mode */ - SCP_SYS_CTRL |= AUTO_DDREN; - - /* set settle time */ - SCP_CLK_SYS_VAL = - (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1); - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1); - SCP_SLEEP_CTRL = - (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1); - - /* turn off ULPOSC2 */ - SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB; - - /* calibrate ULPOSC2 */ - for (i = 0; i < ARRAY_SIZE(opp); ++i) - clock_calibrate_ulposc(&opp[i]); - - /* select ULPOSC2 high speed SCP clock */ - clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED); - - /* select BCLK to use ULPOSC / 8 */ - SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8; - - /* enable default clock gate */ - SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 | - CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK; -} - -#ifdef DEBUG -int command_ulposc(int argc, char *argv[]) -{ - uint32_t osc; - - for (osc = 0; osc <= OPP_ULPOSC2_HIGH_SPEED; ++osc) - ccprintf("ULPOSC%u frequency: %u kHz\n", osc + 1, - clock_ulposc_measure_freq(osc) * 26 * 1000 / 512); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]", - "Measure ULPOSC frequency"); -#endif diff --git a/chip/mt_scp/mt8195/clock_regs.h b/chip/mt_scp/mt8195/clock_regs.h deleted file mode 100644 index 6e7ec6bdbb..0000000000 --- a/chip/mt_scp/mt8195/clock_regs.h +++ /dev/null @@ -1,92 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SCP clock module registers */ - -#ifndef __CROS_EC_CLOCK_REGS_H -#define __CROS_EC_CLOCK_REGS_H - -/* clock source select */ -#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000) -#define CLK_SW_SEL_SYSTEM 0 -#define CLK_SW_SEL_32K 1 -#define CLK_SW_SEL_ULPOSC2 2 -#define CLK_SW_SEL_ULPOSC1 3 -#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004) -#define CLK_HIGH_EN BIT(1) /* ULPOSC */ -#define CLK_HIGH_CG BIT(2) -/* clock general control */ -#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C) -#define VREQ_PMIC_WRAP_SEL (0x3) - -/* TOPCK clk */ -#define TOPCK_BASE AP_REG_BASE -#define AP_CLK_CFG_UPDATE3 REG32(TOPCK_BASE + 0x0010) -#define F_ULPOSC_CK_UPDATE BIT(21) -#define F_ULPOSC_CORE_CK_UPDATE BIT(22) -#define AP_CLK_CFG_29_SET REG32(TOPCK_BASE + 0x0180) -#define AP_CLK_CFG_29_CLR REG32(TOPCK_BASE + 0x0184) -#define ULPOSC1_CLK_SEL (0x3 << 8) -#define PDN_F_ULPOSC_CK BIT(15) -#define ULPOSC2_CLK_SEL (0x3 << 16) -#define PDN_F_ULPOSC_CORE_CK BIT(23) -/* OSC meter */ -#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x020C) -#define DBG_MODE_MASK 3 -#define DBG_MODE_SET_CLOCK 0 -#define DBG_BIST_SOURCE_MASK (0x7f << 8) -#define DBG_BIST_SOURCE_ULPOSC1 (0x30 << 8) -#define DBG_BIST_SOURCE_ULPOSC2 (0x32 << 8) -#define AP_CLK26CALI_0 REG32(TOPCK_BASE + 0x0218) -#define CFG_FREQ_METER_RUN BIT(4) -#define CFG_FREQ_METER_ENABLE BIT(7) -#define AP_CLK26CALI_1 REG32(TOPCK_BASE + 0x021C) -#define CFG_CKGEN_LOAD_CNT 0x01ff0000 -#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF) -#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x022C) -#define MISC_METER_DIVISOR_MASK 0xff000000 -#define MISC_METER_DIV_1 0 -/* - * ULPOSC - * osc: 0 for ULPOSC1, 1 for ULPOSC2. - */ -#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0) -#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4) -#define AP_ULPOSC_CON0(osc) \ - REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10) -#define AP_ULPOSC_CON1(osc) \ - REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10) -/* - * AP_ULPOSC_CON0 - * bit0-6: calibration - * bit7-13: iband - * bit14-17: fband - * bit18-23: div - * bit24: cp_en - * bit25-26: mod - * bit27: div2_en - * bit28-31: reserved - */ -#define OSC_CALI_SHIFT 0 -#define OSC_CALI_MASK 0x7f -#define OSC_IBAND_SHIFT 7 -#define OSC_FBAND_SHIFT 14 -#define OSC_DIV_SHIFT 18 -#define OSC_CP_EN BIT(24) -#define OSC_MOD_SHIFT 25 -#define OSC_DIV2_EN BIT(27) -/* - * AP_ULPOSC_CON1 - * bit0-7: rsv1 - * bit8-15: rsv2 - * bit16-23: 32K calibration - * bit24-31: bias - */ -#define OSC_RSV1_SHIFT 0 -#define OSC_RSV2_SHIFT 8 -#define OSC_32KCALI_SHIFT 16 -#define OSC_BIAS_SHIFT 24 - -#endif /* __CROS_EC_CLOCK_REGS_H */ diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h deleted file mode 100644 index 87181c46ca..0000000000 --- a/chip/mt_scp/mt8195/intc.h +++ /dev/null @@ -1,166 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_INTC_H -#define __CROS_EC_INTC_H - -/* INTC */ -#define SCP_INTC_IRQ_POL0 0xef001f20 -#define SCP_INTC_IRQ_POL1 0x044001dd -#define SCP_INTC_IRQ_POL2 0xffffdfe0 -#define SCP_INTC_IRQ_POL3 0xfffffff3 -#define SCP_INTC_GRP_LEN 4 -#define SCP_INTC_IRQ_COUNT 127 - -/* IRQ numbers */ -#define SCP_IRQ_GIPC_IN0 0 -#define SCP_IRQ_GIPC_IN1 1 -#define SCP_IRQ_GIPC_IN2 2 -#define SCP_IRQ_GIPC_IN3 3 -/* 4 */ -#define SCP_IRQ_SPM 4 -#define SCP_IRQ_AP_CIRQ 5 -#define SCP_IRQ_EINT 6 -#define SCP_IRQ_PMIC 7 -/* 8 */ -#define SCP_IRQ_UART0_TX 8 -#define SCP_IRQ_UART1_TX 9 -#define SCP_IRQ_I2C0 10 -#define SCP_IRQ_I2C1_0 11 -/* 12 */ -#define SCP_IRQ_BUS_DBG_TRACKER 12 -#define SCP_IRQ_CLK_CTRL 13 -#define SCP_IRQ_VOW 14 -#define SCP_IRQ_TIMER0 15 -/* 16 */ -#define SCP_IRQ_TIMER1 16 -#define SCP_IRQ_TIMER2 17 -#define SCP_IRQ_TIMER3 18 -#define SCP_IRQ_TIMER4 19 -/* 20 */ -#define SCP_IRQ_TIMER5 20 -#define SCP_IRQ_OS_TIMER 21 -#define SCP_IRQ_UART0_RX 22 -#define SCP_IRQ_UART1_RX 23 -/* 24 */ -#define SCP_IRQ_GDMA 24 -#define SCP_IRQ_AUDIO 25 -#define SCP_IRQ_MD_DSP 26 -#define SCP_IRQ_ADSP 27 -/* 28 */ -#define SCP_IRQ_CPU_TICK 28 -#define SCP_IRQ_SPI0 29 -#define SCP_IRQ_SPI1 30 -#define SCP_IRQ_SPI2 31 -/* 32 */ -#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32 -#define SCP_IRQ_DBG 33 -#define SCP_IRQ_GCE 34 -#define SCP_IRQ_MDP_GCE 35 -/* 36 */ -#define SCP_IRQ_VDEC 36 -#define SCP_IRQ_WDT 37 -#define SCP_IRQ_VDEC_LAT 38 -#define SCP_IRQ_VDEC1 39 -/* 40 */ -#define SCP_IRQ_VDEC1_LAT 40 -#define SCP_IRQ_INFRA 41 -#define SCP_IRQ_CLK_CTRL_CORE 42 -#define SCP_IRQ_CLK_CTRL2_CORE 43 -/* 44 */ -#define SCP_IRQ_CLK_CTRL2 44 -#define SCP_IRQ_GIPC_IN4 45 /* HALT */ -#define SCP_IRQ_PERIBUS_TIMEOUT 46 -#define SCP_IRQ_INFRABUS_TIMEOUT 47 -/* 48 */ -#define SCP_IRQ_MET0 48 -#define SCP_IRQ_MET1 49 -#define SCP_IRQ_MET2 50 -#define SCP_IRQ_MET3 51 -/* 52 */ -#define SCP_IRQ_AP_WDT 52 -#define SCP_IRQ_L2TCM_SEC_VIO 53 -#define SCP_IRQ_VDEC_INT_LINE_CNT 54 -#define SCP_IRQ_VOW_DATAIN 55 -/* 56 */ -#define SCP_IRQ_I3C0_IBI_WAKE 56 -#define SCP_IRQ_I3C1_IBI_WAKE 57 -#define SCP_IRQ_VENC 58 -#define SCP_IRQ_APU_ENGINE 59 -/* 60 */ -#define SCP_IRQ_MBOX0 60 -#define SCP_IRQ_MBOX1 61 -#define SCP_IRQ_MBOX2 62 -#define SCP_IRQ_MBOX3 63 -/* 64 */ -#define SCP_IRQ_MBOX4 64 -#define SCP_IRQ_SYS_CLK_REQ 65 -#define SCP_IRQ_BUS_REQ 66 -#define SCP_IRQ_APSRC_REQ 67 -/* 68 */ -#define SCP_IRQ_APU_MBOX 68 -#define SCP_IRQ_DEVAPC_SECURE_VIO 69 -#define SCP_IRQ_CAMSYS_29 70 -#define SCP_IRQ_CAMSYS_28 71 -/* 72 */ -#define SCP_IRQ_CAMSYS_5 72 -#define SCP_IRQ_CAMSYS_4 73 -#define SCP_IRQ_CAMSYS_3 74 -#define SCP_IRQ_CAMSYS_2 75 -/* 76 */ -#define SCP_IRQ_HDMIRX_PM_DVI_SQH 76 -#define SCP_IRQ_HDMIRX_RESERVED 77 -#define SCP_IRQ_NNA0_0 78 -#define SCP_IRQ_NNA0_1 79 -/* 80 */ -#define SCP_IRQ_NNA0_2 80 -#define SCP_IRQ_NNA1_0 81 -#define SCP_IRQ_NNA1_1 82 -#define SCP_IRQ_NNA1_2 83 -/* 84 */ -#define SCP_IRQ_JPEGENC 84 -#define SCP_IRQ_JPEGDEC 85 -#define SCP_IRQ_JPEGDEC_C2 86 -#define SCP_IRQ_VENC_C1 87 -/* 88 */ -#define SCP_IRQ_JPEGENC_C1 88 -#define SCP_IRQ_JPEGDEC_C1 89 -#define SCP_IRQ_HDMITX 90 -#define SCP_IRQ_HDMI2 91 -/* 92 */ -#define SCP_IRQ_EARC 92 -#define SCP_IRQ_CEC 93 -#define SCP_IRQ_HDMI_DEV_DET 94 -#define SCP_IRQ_HDMIRX_OUT_ARM_PHY 95 -/* 96 */ -#define SCP_IRQ_I2C2 96 -#define SCP_IRQ_I2C3 97 -#define SCP_IRQ_I3C2_IBI_WAKE 98 -#define SCP_IRQ_I3C3_IBI_WAKE 99 -/* 100 */ -#define SCP_IRQ_SYS_I2C_0 100 -#define SCP_IRQ_SYS_I2C_1 101 -#define SCP_IRQ_SYS_I2C_2 102 -#define SCP_IRQ_SYS_I2C_3 103 -/* 104 */ -#define SCP_IRQ_SYS_I2C_4 104 -#define SCP_IRQ_SYS_I2C_5 105 -#define SCP_IRQ_SYS_I2C_6 106 -#define SCP_IRQ_SYS_I2C_7 107 -/* 108 */ -#define SCP_IRQ_DISP2ADSP_0 108 -#define SCP_IRQ_DISP2ADSP_1 109 -#define SCP_IRQ_DISP2ADSP_2 110 -#define SCP_IRQ_DISP2ADSP_3 111 -/* 112 */ -#define SCP_IRQ_DISP2ADSP_4 112 -#define SCP_IRQ_VDO1_DISP_MON2ADSP_0 113 -#define SCP_IRQ_VDO1_DISP_MON2ADSP_1 114 -#define SCP_IRQ_VDO1_DISP_MON2ADSP_2 115 -/* 116 */ -#define SCP_IRQ_GCE1_SECURE 116 -#define SCP_IRQ_GCE_SECURE 117 - -#endif /* __CROS_EC_INTC_H */ diff --git a/chip/mt_scp/mt8195/uart.c b/chip/mt_scp/mt8195/uart.c deleted file mode 100644 index 76674fa7d3..0000000000 --- a/chip/mt_scp/mt8195/uart.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SCP UART module for MT8195 specific */ - -#include "uart_regs.h" - -/* - * UARTN == 0, SCP UART0 - * UARTN == 1, SCP UART1 - * UARTN == 2, AP UART1 - */ -#define UARTN CONFIG_UART_CONSOLE - -void uart_init_pinmux(void) -{ -#if UARTN == 0 - SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC); - SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST; - - /* set AP GPIO102 and GPIO103 to alt func 5 */ - AP_GPIO_MODE12_CLR = 0x77000000; - AP_GPIO_MODE12_SET = 0x55000000; -#endif -} diff --git a/chip/mt_scp/mt8195/video.c b/chip/mt_scp/mt8195/video.c deleted file mode 100644 index dc4b7b3397..0000000000 --- a/chip/mt_scp/mt8195/video.c +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "video.h" - -uint32_t video_get_enc_capability(void) -{ - return VENC_CAP_4K; -} - -uint32_t video_get_dec_capability(void) -{ - return VDEC_CAP_MT21C | VDEC_CAP_MM21 | - VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME | - VDEC_CAP_VP9_FRAME; -} diff --git a/chip/mt_scp/rv32i_common/build.mk b/chip/mt_scp/rv32i_common/build.mk deleted file mode 100644 index ac7e13db77..0000000000 --- a/chip/mt_scp/rv32i_common/build.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# SCP specific files build -# - -CORE:=riscv-rv32i - -# Required chip modules -chip-y+=rv32i_common/cache.o -chip-y+=rv32i_common/gpio.o -chip-y+=rv32i_common/intc.o -chip-y+=rv32i_common/memmap.o -chip-y+=rv32i_common/system.o -chip-y+=rv32i_common/uart.o - -ifeq ($(CONFIG_IPI),y) -$(out)/RW/chip/$(CHIP)/rv32i_common/ipi_table.o: $(out)/ipi_table_gen.inc -endif - -# Optional chip modules -chip-$(CONFIG_COMMON_TIMER)+=rv32i_common/hrtimer.o -chip-$(CONFIG_IPI)+=rv32i_common/ipi.o rv32i_common/ipi_table.o -chip-$(CONFIG_WATCHDOG)+=rv32i_common/watchdog.o -chip-$(HAS_TASK_HOSTCMD)+=rv32i_common/hostcmd.o diff --git a/chip/mt_scp/rv32i_common/cache.c b/chip/mt_scp/rv32i_common/cache.c deleted file mode 100644 index 62147590fe..0000000000 --- a/chip/mt_scp/rv32i_common/cache.c +++ /dev/null @@ -1,211 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "cache.h" -#include "console.h" -#include "csr.h" - -extern struct mpu_entry mpu_entries[]; - -void cache_init(void) -{ - int i; - uint32_t mpu_en = 0; - - /* disable mpu */ - clear_csr(CSR_MCTREN, CSR_MCTREN_MPU); - - /* enable i$, d$ */ - set_csr(CSR_MCTREN, CSR_MCTREN_ICACHE); - set_csr(CSR_MCTREN, CSR_MCTREN_DCACHE); - - /* invalidate icache and dcache */ - cache_invalidate_icache(); - cache_invalidate_dcache(); - - /* set mpu entries - * - * The pragma is for force GCC unrolls the following loop. - * See b/172886808 - */ -#pragma GCC unroll 16 - for (i = 0; i < NR_MPU_ENTRIES; ++i) { - if (mpu_entries[i].end_addr - mpu_entries[i].start_addr) { - write_csr(CSR_MPU_L(i), mpu_entries[i].start_addr | - mpu_entries[i].attribute); - write_csr(CSR_MPU_H(i), mpu_entries[i].end_addr); - mpu_en |= BIT(i); - } - } - - /* enable mpu entries */ - write_csr(CSR_MPU_ENTRY_EN, mpu_en); - - /* enable mpu */ - set_csr(CSR_MCTREN, CSR_MCTREN_MPU); - - /* fence */ - asm volatile ("fence.i" ::: "memory"); -} - -#ifdef DEBUG -/* - * I for I-cache - * D for D-cache - * C for control transfer instructions (branch, jump, ret, interrupt, ...) - */ -static enum { - PMU_SELECT_I = 0, - PMU_SELECT_D, - PMU_SELECT_C -} pmu_select; - -int command_enable_pmu(int argc, char **argv) -{ - static const char * const selectors[] = { - [PMU_SELECT_I] = "I", - [PMU_SELECT_D] = "D", - [PMU_SELECT_C] = "C", - }; - int i; - - if (argc != 2) - return EC_ERROR_PARAM1; - - for (i = 0; i < ARRAY_SIZE(selectors); ++i) { - if (strcasecmp(argv[1], selectors[i]) == 0) { - pmu_select = i; - break; - } - } - if (i >= ARRAY_SIZE(selectors)) - return EC_ERROR_PARAM1; - - ccprintf("select \"%s\"\n", selectors[pmu_select]); - - /* disable all PMU */ - clear_csr(CSR_PMU_MPMUCTR, - CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | - CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 | - CSR_PMU_MPMUCTR_H5); - - /* reset cycle count */ - write_csr(CSR_PMU_MCYCLE, 0); - write_csr(CSR_PMU_MCYCLEH, 0); - /* reset retired-instruction count */ - write_csr(CSR_PMU_MINSTRET, 0); - write_csr(CSR_PMU_MINSTRETH, 0); - /* reset counter{3,4,5} */ - write_csr(CSR_PMU_MHPMCOUNTER3, 0); - write_csr(CSR_PMU_MHPMCOUNTER3H, 0); - write_csr(CSR_PMU_MHPMCOUNTER4, 0); - write_csr(CSR_PMU_MHPMCOUNTER4H, 0); - write_csr(CSR_PMU_MHPMCOUNTER5, 0); - write_csr(CSR_PMU_MHPMCOUNTER5H, 0); - - /* select different event IDs for counter{3,4,5} */ - switch (pmu_select) { - case PMU_SELECT_I: - /* I-cache access count */ - write_csr(CSR_PMU_MHPMEVENT3, 1); - /* I-cache miss count */ - write_csr(CSR_PMU_MHPMEVENT4, 3); - /* noncacheable I-AXI access count */ - write_csr(CSR_PMU_MHPMEVENT5, 5); - break; - case PMU_SELECT_D: - /* D-cache access count */ - write_csr(CSR_PMU_MHPMEVENT3, 11); - /* D-cache miss count */ - write_csr(CSR_PMU_MHPMEVENT4, 12); - /* noncacheable D-AXI access count */ - write_csr(CSR_PMU_MHPMEVENT5, 14); - break; - case PMU_SELECT_C: - /* control transfer instruction count */ - write_csr(CSR_PMU_MHPMEVENT3, 27); - /* control transfer miss-predict count */ - write_csr(CSR_PMU_MHPMEVENT4, 28); - /* interrupt count */ - write_csr(CSR_PMU_MHPMEVENT5, 29); - break; - } - - cache_invalidate_icache(); - cache_flush_dcache(); - - /* enable all PMU */ - set_csr(CSR_PMU_MPMUCTR, - CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | - CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 | - CSR_PMU_MPMUCTR_H5); - - return EC_SUCCESS; -} -DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu, - "[I | D | C]", "Enable PMU"); - -int command_disable_pmu(int argc, char **argv) -{ - clear_csr(CSR_PMU_MPMUCTR, - CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | - CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 | - CSR_PMU_MPMUCTR_H5); - return EC_SUCCESS; -} -DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu, - NULL, "Disable PMU"); - -int command_show_pmu(int argc, char **argv) -{ - uint64_t val3, val4, val5; - uint32_t p; - - val3 = ((uint64_t)read_csr(CSR_PMU_MCYCLEH) << 32) | - read_csr(CSR_PMU_MCYCLE); - ccprintf("cycles: %lld\n", val3); - - val3 = ((uint64_t)read_csr(CSR_PMU_MINSTRETH) << 32) | - read_csr(CSR_PMU_MINSTRET); - ccprintf("retired instructions: %lld\n", val3); - - val3 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER3H) << 32) | - read_csr(CSR_PMU_MHPMCOUNTER3); - val4 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER4H) << 32) | - read_csr(CSR_PMU_MHPMCOUNTER4); - val5 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER5H) << 32) | - read_csr(CSR_PMU_MHPMCOUNTER5); - - if (val3) - p = val4 * 10000 / val3; - else - p = 0; - - switch (pmu_select) { - case PMU_SELECT_I: - ccprintf("I-cache:\n"); - ccprintf(" access: %lld\n", val3); - ccprintf(" miss: %lld (%d.%d%%)\n", val4, p / 100, p % 100); - ccprintf("non-cacheable I: %lld\n", val5); - break; - case PMU_SELECT_D: - ccprintf("D-cache:\n"); - ccprintf(" access: %lld\n", val3); - ccprintf(" miss: %lld (%d.%d%%)\n", val4, p / 100, p % 100); - ccprintf("non-cacheable D: %lld\n", val5); - break; - case PMU_SELECT_C: - ccprintf("control transfer instruction:\n"); - ccprintf(" total: %lld\n", val3); - ccprintf(" miss-predict: %lld (%d.%d%%)\n", - val4, p / 100, p % 100); - ccprintf("interrupts: %lld\n", val5); - break; - } - - return EC_SUCCESS; -} -DECLARE_SAFE_CONSOLE_COMMAND(show_pmu, command_show_pmu, NULL, "Show PMU"); -#endif diff --git a/chip/mt_scp/rv32i_common/cache.h b/chip/mt_scp/rv32i_common/cache.h deleted file mode 100644 index 13e5ad1a42..0000000000 --- a/chip/mt_scp/rv32i_common/cache.h +++ /dev/null @@ -1,140 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CACHE_H -#define __CROS_EC_CACHE_H - -#include "common.h" -#include "csr.h" -#include "stdint.h" -#include "util.h" - -/* rs1 0~31 register X0~X31 */ -#define COP(rs1) (((rs1) << 15) | 0x400f) - -#define COP_OP_BARRIER_ICACHE 0x0 -#define COP_OP_INVALIDATE_ICACHE 0x8 -#define COP_OP_INVALIDATE_ICACHE_ADDR 0x9 - -#define COP_OP_BARRIER_DCACHE 0x10 -#define COP_OP_WRITEBACK_DCACHE 0x14 -#define COP_OP_WRITEBACK_DCACHE_ADDR 0x15 -#define COP_OP_INVALIDATE_DCACHE 0x18 -#define COP_OP_INVALIDATE_DCACHE_ADDR 0x19 -/* FLUSH = WRITEBACK + INVALIDATE */ -#define COP_OP_FLUSH_DCACHE 0x1C -#define COP_OP_FLUSH_DCACHE_ADDR 0x1D - -static inline void cache_op_all(uint32_t op) -{ - register int t0 asm("t0") = op; - asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0)); -} - -static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op) -{ - size_t offset; - register int t0 asm("t0"); - - /* NOTE: cache operations must use 32 byte aligned address */ - if (addr & GENMASK(3, 0)) - return EC_ERROR_INVAL; - - for (offset = 0; offset < length; offset += 4) { - t0 = addr + offset + op; - asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0)); - } - - return EC_SUCCESS; -} - -/* memory barrier of I$ */ -static inline void cache_barrier_icache(void) -{ - cache_op_all(COP_OP_BARRIER_ICACHE); -} - -/* invalidate all I$ */ -static inline void cache_invalidate_icache(void) -{ - cache_op_all(COP_OP_INVALIDATE_ICACHE); -} - -/* invalidate a range of I$ */ -static inline int cache_invalidate_icache_range(uintptr_t addr, uint32_t length) -{ - return cache_op_addr(addr, length, COP_OP_INVALIDATE_ICACHE_ADDR); -} - -/* memory barrier of D$ */ -static inline void cache_barrier_dcache(void) -{ - cache_op_all(COP_OP_BARRIER_DCACHE); -} - -/* writeback all D$ */ -static inline void cache_writeback_dcache(void) -{ - cache_op_all(COP_OP_WRITEBACK_DCACHE); - cache_barrier_icache(); - cache_barrier_dcache(); -} - -/* writeback a range of D$ */ -static inline int cache_writeback_dcache_range(uintptr_t addr, uint32_t length) -{ - int ret = cache_op_addr(addr, length, COP_OP_WRITEBACK_DCACHE_ADDR); - cache_barrier_icache(); - cache_barrier_dcache(); - return ret; -} - -/* invalidate all D$ */ -static inline void cache_invalidate_dcache(void) -{ - cache_op_all(COP_OP_INVALIDATE_DCACHE); -} - -/* invalidate a range of D$ */ -static inline int cache_invalidate_dcache_range(uintptr_t addr, uint32_t length) -{ - return cache_op_addr(addr, length, COP_OP_INVALIDATE_DCACHE_ADDR); -} - -/* writeback and invalidate all D$ */ -static inline void cache_flush_dcache(void) -{ - cache_op_all(COP_OP_FLUSH_DCACHE); - cache_barrier_icache(); - cache_barrier_dcache(); -} - -/* writeback and invalidate a range of D$ */ -static inline int cache_flush_dcache_range(uintptr_t addr, uint32_t length) -{ - int ret = cache_op_addr(addr, length, COP_OP_FLUSH_DCACHE_ADDR); - cache_barrier_icache(); - cache_barrier_dcache(); - return ret; -} - -struct mpu_entry { - /* 1k alignment and the address is inclusive */ - uintptr_t start_addr; - /* 1k alignment in 4GB boundary and non-inclusive */ - uintptr_t end_addr; - /* MPU_ATTR */ - uint32_t attribute; -}; - -void cache_init(void); - -#ifdef DEBUG -int command_enable_pmu(int argc, char **argv); -int command_disable_pmu(int argc, char **argv); -int command_show_pmu(int argc, char **argv); -#endif - -#endif /* #ifndef __CROS_EC_CACHE_H */ diff --git a/chip/mt_scp/rv32i_common/config_chip.h b/chip/mt_scp/rv32i_common/config_chip.h deleted file mode 100644 index ac53d51732..0000000000 --- a/chip/mt_scp/rv32i_common/config_chip.h +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -#include "core/riscv-rv32i/config_core.h" - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* RW only, no flash */ -#undef CONFIG_FW_INCLUDE_RO -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE 0 -#define CONFIG_RW_MEM_OFF 0 -#define CONFIG_RW_SIZE 0x40000 /* 256KB */ -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_PROGRAM_MEMORY_BASE 0 -#define CONFIG_PROGRAM_MEMORY_BASE_LOAD 0x10500000 -#define CONFIG_MAPPED_STORAGE_BASE 0 - -/* Unsupported features/commands */ -#undef CONFIG_CMD_FLASHINFO -#undef CONFIG_CMD_POWER_AP -#undef CONFIG_FLASH_CROS -#undef CONFIG_FLASH_PHYSICAL -#undef CONFIG_FMAP -#undef CONFIG_HIBERNATE -#undef CONFIG_LID_SWITCH - -/* Task stack size */ -#define CONFIG_STACK_SIZE 1024 -#define IDLE_TASK_STACK_SIZE 640 -#define SMALLER_TASK_STACK_SIZE 384 -#define TASK_STACK_SIZE 488 -#define LARGER_TASK_STACK_SIZE 640 -#define VENTI_TASK_STACK_SIZE 768 -#define ULTRA_TASK_STACK_SIZE 1056 -#define TRENTA_TASK_STACK_SIZE 1184 - -/* TODO: need to confirm, placeholder */ -#define GPIO_PIN(num) ((num) / 32), ((num) % 32) -#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) -#undef CONFIG_TASK_PROFILING -/* TODO: not yet supported */ -#undef CONFIG_MPU -/* TODO: core/riscv-rv32i pollution */ -#define __ram_code - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/mt_scp/rv32i_common/csr.h b/chip/mt_scp/rv32i_common/csr.h deleted file mode 100644 index 7c767d0592..0000000000 --- a/chip/mt_scp/rv32i_common/csr.h +++ /dev/null @@ -1,111 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Control and status register */ - -/* TODO: move to core/riscv-rv32i? */ - -#ifndef __CROS_EC_CSR_H -#define __CROS_EC_CSR_H - -#include "common.h" - -static inline uint32_t read_csr(uint32_t reg) -{ - uint32_t val; - - asm volatile("csrr %0, %1" : "=r"(val) : "i"(reg)); - return val; -} - -static inline void write_csr(uint32_t reg, uint32_t val) -{ - asm volatile ("csrw %0, %1" :: "i"(reg), "r"(val)); -} - -static inline uint32_t set_csr(uint32_t reg, uint32_t bit) -{ - uint32_t val; - - asm volatile ("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); - return val; -} - -static inline uint32_t clear_csr(uint32_t reg, uint32_t bit) -{ - uint32_t val; - - asm volatile ("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); - return val; -} - -/* VIC */ -#define CSR_VIC_MICAUSE (0x5c0) -#define CSR_VIC_MIEMS (0x5c2) -#define CSR_VIC_MIPEND_G0 (0x5d0) -#define CSR_VIC_MIMASK_G0 (0x5d8) -#define CSR_VIC_MIWAKEUP_G0 (0x5e0) -#define CSR_VIC_MILSEL_G0 (0x5e8) -#define CSR_VIC_MIEMASK_G0 (0x5f0) - -/* centralized control enable */ -#define CSR_MCTREN (0x7c0) -/* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */ -#define CSR_MCTREN_ICACHE BIT(0) -#define CSR_MCTREN_DCACHE BIT(1) -#define CSR_MCTREN_ITCM BIT(2) -#define CSR_MCTREN_DTCM BIT(3) -#define CSR_MCTREN_BTB BIT(4) -#define CSR_MCTREN_RAS BIT(5) -#define CSR_MCTREN_VIC BIT(6) -#define CSR_MCTREN_CG BIT(7) -#define CSR_MCTREN_MPU BIT(8) - -/* MPU */ -#define CSR_MPU_ENTRY_EN (0x9c0) -#define CSR_MPU_LITCM (0x9dc) -#define CSR_MPU_LDTCM (0x9dd) -#define CSR_MPU_HITCM (0x9de) -#define CSR_MPU_HDTCM (0x9df) -#define CSR_MPU_L(n) (0x9e0 + (n)) -#define CSR_MPU_H(n) (0x9f0 + (n)) -/* MPU attributes: set if permitted */ -/* Privilege, machine mode in RISC-V. We don't use the flag because - * we don't separate user / machine mode in EC OS. */ -#define MPU_ATTR_P BIT(5) -/* Readable */ -#define MPU_ATTR_R BIT(6) -/* Writable */ -#define MPU_ATTR_W BIT(7) -/* Cacheable */ -#define MPU_ATTR_C BIT(8) -/* Bufferable */ -#define MPU_ATTR_B BIT(9) - -/* PMU */ -#define CSR_PMU_MPMUCTR (0xbc0) -#define CSR_PMU_MPMUCTR_C BIT(0) -#define CSR_PMU_MPMUCTR_I BIT(1) -#define CSR_PMU_MPMUCTR_H3 BIT(2) -#define CSR_PMU_MPMUCTR_H4 BIT(3) -#define CSR_PMU_MPMUCTR_H5 BIT(4) - -#define CSR_PMU_MCYCLE (0xb00) -#define CSR_PMU_MINSTRET (0xb02) -#define CSR_PMU_MHPMCOUNTER3 (0xb03) -#define CSR_PMU_MHPMCOUNTER4 (0xb04) -#define CSR_PMU_MHPMCOUNTER5 (0xb05) - -#define CSR_PMU_MCYCLEH (0xb80) -#define CSR_PMU_MINSTRETH (0xb82) -#define CSR_PMU_MHPMCOUNTER3H (0xb83) -#define CSR_PMU_MHPMCOUNTER4H (0xb84) -#define CSR_PMU_MHPMCOUNTER5H (0xb85) - -#define CSR_PMU_MHPMEVENT3 (0x323) -#define CSR_PMU_MHPMEVENT4 (0x324) -#define CSR_PMU_MHPMEVENT5 (0x325) - -#endif /* __CROS_EC_CSR_H */ diff --git a/chip/mt_scp/rv32i_common/gpio.c b/chip/mt_scp/rv32i_common/gpio.c deleted file mode 100644 index 0ca3e3ac25..0000000000 --- a/chip/mt_scp/rv32i_common/gpio.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module */ - -#include "gpio.h" - -void gpio_pre_init(void) -{ -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - return 0; -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ -} diff --git a/chip/mt_scp/rv32i_common/hostcmd.c b/chip/mt_scp/rv32i_common/hostcmd.c deleted file mode 100644 index 42a463ee56..0000000000 --- a/chip/mt_scp/rv32i_common/hostcmd.c +++ /dev/null @@ -1,128 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "console.h" -#include "host_command.h" -#include "ipi_chip.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args) -#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args) - -#define HOSTCMD_MAX_REQUEST_SIZE CONFIG_IPC_SHARED_OBJ_BUF_SIZE -/* Reserve 1 extra byte for HOSTCMD_TYPE and 3 bytes for padding. */ -#define HOSTCMD_MAX_RESPONSE_SIZE (CONFIG_IPC_SHARED_OBJ_BUF_SIZE - 4) -#define HOSTCMD_TYPE_HOSTCMD 1 -#define HOSTCMD_TYPE_HOSTEVENT 2 - -/* - * hostcmd and hostevent share the same IPI ID, and use first byte type to - * indicate its type. - */ -static struct hostcmd_data { - const uint8_t type; - /* To be compatible with CONFIG_HOSTCMD_ALIGNED */ - uint8_t response[HOSTCMD_MAX_RESPONSE_SIZE] __aligned(4); -} hc_cmd_obj = { .type = HOSTCMD_TYPE_HOSTCMD }; -BUILD_ASSERT(sizeof(struct hostcmd_data) == CONFIG_IPC_SHARED_OBJ_BUF_SIZE); - -/* Size of the rpmsg device name, should sync across kernel and EC. */ -#define RPMSG_NAME_SIZE 32 - -/* - * The layout of name service message. - * This should sync across kernel and EC. - */ -struct rpmsg_ns_msg { - /* Name of the corresponding rpmsg_driver. */ - char name[RPMSG_NAME_SIZE]; - /* IPC ID */ - uint32_t addr; -}; - -static void hostcmd_send_response_packet(struct host_packet *pkt) -{ - int ret; - - ret = ipi_send(SCP_IPI_HOST_COMMAND, &hc_cmd_obj, - pkt->response_size + - offsetof(struct hostcmd_data, response), - 1); - if (ret) - CPRINTS("failed to %s(), ret=%d", __func__, ret); -} - -static void hostcmd_handler(int32_t id, void *buf, uint32_t len) -{ - static struct host_packet packet; - uint8_t *in_msg = buf; - struct ec_host_request *r = (struct ec_host_request *)in_msg; - int i; - - if (in_msg[0] != EC_HOST_REQUEST_VERSION) { - CPRINTS("ERROR: Protocol V2 is not supported!"); - CPRINTF("in_msg=["); - for (i = 0; i < len; i++) - CPRINTF("%02x ", in_msg[i]); - CPRINTF("]\n"); - return; - } - - /* Protocol version 3 */ - - packet.send_response = hostcmd_send_response_packet; - - /* - * Just assign the buffer to request, host_packet_receive - * handles the buffer copy. - */ - packet.request = (void *)r; - packet.request_temp = NULL; - packet.request_max = HOSTCMD_MAX_REQUEST_SIZE; - packet.request_size = host_request_expected_size(r); - - packet.response = hc_cmd_obj.response; - /* Reserve space for the preamble and trailing byte */ - packet.response_max = HOSTCMD_MAX_RESPONSE_SIZE; - packet.response_size = 0; - - packet.driver_result = EC_RES_SUCCESS; - - host_packet_receive(&packet); -} -DECLARE_IPI(SCP_IPI_HOST_COMMAND, hostcmd_handler, 0); - -/* - * Get protocol information - */ -static enum ec_status hostcmd_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); - r->protocol_versions |= BIT(3); - r->max_request_packet_size = HOSTCMD_MAX_REQUEST_SIZE; - r->max_response_packet_size = HOSTCMD_MAX_RESPONSE_SIZE; - - args->response_size = sizeof(*r); - - return EC_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, hostcmd_get_protocol_info, - EC_VER_MASK(0)); - -void hostcmd_init(void) -{ - int ret; - struct rpmsg_ns_msg ns_msg; - - if (IS_ENABLED(CONFIG_RPMSG_NAME_SERVICE)) { - ns_msg.addr = SCP_IPI_HOST_COMMAND; - strncpy(ns_msg.name, "cros-ec-rpmsg", RPMSG_NAME_SIZE); - ret = ipi_send(SCP_IPI_NS_SERVICE, &ns_msg, sizeof(ns_msg), 1); - if (ret) - CPRINTS("Failed to announce host command channel"); - } -} diff --git a/chip/mt_scp/rv32i_common/hostcmd.h b/chip/mt_scp/rv32i_common/hostcmd.h deleted file mode 100644 index b93f1e725d..0000000000 --- a/chip/mt_scp/rv32i_common/hostcmd.h +++ /dev/null @@ -1,12 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_HOSTCMD_H -#define __CROS_EC_HOSTCMD_H - -/* Initialize hostcmd. */ -void hostcmd_init(void); - -#endif /* __CROS_EC_HOSTCMD_H */ diff --git a/chip/mt_scp/rv32i_common/hrtimer.c b/chip/mt_scp/rv32i_common/hrtimer.c deleted file mode 100644 index 89ffaa2fca..0000000000 --- a/chip/mt_scp/rv32i_common/hrtimer.c +++ /dev/null @@ -1,221 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * High-res hardware timer - * - * SCP hardware 32bit count down timer can be configured to source clock from - * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a - * source, countdown mode and converts to micro second value matching common - * timer. - */ - -#include "common.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" - -#define TIMER_SYSTEM 5 -#define TIMER_EVENT 3 -#define TIMER_CLOCK_MHZ 32.5 -#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1) - -/* High 32-bit for system timer. */ -static uint8_t sys_high; -/* High 32-bit for event timer. */ -static uint8_t event_high; - -static void timer_enable(int n) -{ - /* cannot be changed when timer is enabled */ - SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_EN; - SCP_CORE0_TIMER_EN(n) |= TIMER_EN; -} - -static void timer_disable(int n) -{ - SCP_CORE0_TIMER_EN(n) &= ~TIMER_EN; - /* cannot be changed when timer is enabled */ - SCP_CORE0_TIMER_IRQ_CTRL(n) &= ~TIMER_IRQ_EN; -} - -static int timer_is_irq(int n) -{ - return SCP_CORE0_TIMER_IRQ_CTRL(n) & TIMER_IRQ_STATUS; -} - -static void timer_ack_irq(int n) -{ - SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLR; -} - -static void timer_set_reset_value(int n, uint32_t reset_value) -{ - /* cannot be changed when timer is enabled */ - SCP_CORE0_TIMER_RST_VAL(n) = reset_value; -} - -static void timer_set_clock(int n, uint32_t clock_source) -{ - SCP_CORE0_TIMER_EN(n) = - (SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) | clock_source; -} - -static void timer_reset(int n) -{ - timer_disable(n); - timer_ack_irq(n); - timer_set_reset_value(n, 0xffffffff); - timer_set_clock(n, TIMER_CLK_SRC_32K); -} - -/* Convert hardware countdown timer to 64bit countup ticks. */ -static uint64_t timer_read_raw_system(void) -{ - uint32_t timer_ctrl = SCP_CORE0_TIMER_IRQ_CTRL(TIMER_SYSTEM); - uint32_t sys_high_adj = sys_high; - - /* - * If an IRQ is pending, but has not been serviced yet, adjust the - * sys_high value. - */ - if (timer_ctrl & TIMER_IRQ_STATUS) - sys_high_adj = sys_high ? (sys_high - 1) - : (TIMER_CLOCK_MHZ - 1); - - return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) | - SCP_CORE0_TIMER_CUR_VAL(TIMER_SYSTEM)); -} - -static uint64_t timer_read_raw_event(void) -{ - return OVERFLOW_TICKS - (((uint64_t)event_high << 32) | - SCP_CORE0_TIMER_CUR_VAL(TIMER_EVENT)); -} - -static void timer_reload(int n, uint32_t value) -{ - timer_disable(n); - timer_set_reset_value(n, value); - timer_enable(n); -} - -static int timer_reload_event_high(void) -{ - if (event_high) { - if (SCP_CORE0_TIMER_RST_VAL(TIMER_EVENT) == 0xffffffff) - timer_enable(TIMER_EVENT); - else - timer_reload(TIMER_EVENT, 0xffffffff); - event_high--; - return 1; - } - - timer_disable(TIMER_EVENT); - return 0; -} - -int __hw_clock_source_init(uint32_t start_t) -{ - int t; - - /* enable clock gate */ - SCP_SET_CLK_CG |= CG_TIMER_MCLK | CG_TIMER_BCLK; - - /* reset all timer, select 32768Hz clock source */ - for (t = 0; t < NUM_TIMERS; ++t) - timer_reset(t); - - /* System timestamp timer */ - timer_set_clock(TIMER_SYSTEM, TIMER_CLK_SRC_BCLK); - sys_high = TIMER_CLOCK_MHZ - 1; - timer_set_reset_value(TIMER_SYSTEM, 0xffffffff); - task_enable_irq(SCP_IRQ_TIMER(TIMER_SYSTEM)); - timer_enable(TIMER_SYSTEM); - - /* Event tick timer */ - timer_set_clock(TIMER_EVENT, TIMER_CLK_SRC_BCLK); - task_enable_irq(SCP_IRQ_TIMER(TIMER_EVENT)); - - return SCP_IRQ_TIMER(TIMER_SYSTEM); -} - -uint32_t __hw_clock_source_read(void) -{ - return timer_read_raw_system() / TIMER_CLOCK_MHZ; -} - -uint32_t __hw_clock_event_get(void) -{ - return (timer_read_raw_event() + timer_read_raw_system()) - / TIMER_CLOCK_MHZ; -} - -void __hw_clock_event_clear(void) -{ - /* c1ea4, magic number for clear state */ - timer_disable(TIMER_EVENT); - timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4); - event_high = 0; -} - -void __hw_clock_event_set(uint32_t deadline) -{ - uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ; - uint64_t now_raw = timer_read_raw_system(); - uint32_t event_deadline; - - if (deadline_raw > now_raw) { - deadline_raw -= now_raw; - event_deadline = (uint32_t)deadline_raw; - event_high = deadline_raw >> 32; - } else { - event_deadline = 1; - event_high = 0; - } - - if (event_deadline) - timer_reload(TIMER_EVENT, event_deadline); - else - timer_reload_event_high(); -} - -static void irq_group6_handler(void) -{ - extern volatile int ec_int; - - switch (ec_int) { - case SCP_IRQ_TIMER(TIMER_EVENT): - if (timer_is_irq(TIMER_EVENT)) { - timer_ack_irq(TIMER_EVENT); - - if (!timer_reload_event_high()) - process_timers(0); - - task_clear_pending_irq(ec_int); - } - break; - case SCP_IRQ_TIMER(TIMER_SYSTEM): - /* If this is a hardware irq, check overflow */ - if (!in_soft_interrupt_context()) { - timer_ack_irq(TIMER_SYSTEM); - - if (sys_high) { - --sys_high; - process_timers(0); - } else { - /* Overflow, reload system timer */ - sys_high = TIMER_CLOCK_MHZ - 1; - process_timers(1); - } - - task_clear_pending_irq(ec_int); - } else { - process_timers(0); - } - break; - } -} -DECLARE_IRQ(6, irq_group6_handler, 0); diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c deleted file mode 100644 index 7e6b39e1f2..0000000000 --- a/chip/mt_scp/rv32i_common/intc.c +++ /dev/null @@ -1,422 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* INTC control module */ - -#include "console.h" -#include "csr.h" -#include "intc.h" -#include "registers.h" - -/* - * INTC_GRP_0 is reserved. See swirq of syscall_handler() in - * core/riscv-rv32i/task.c for more details. - * - * Lower group has higher priority. Group 0 has highest priority. - */ -enum INTC_GROUP { - INTC_GRP_0 = 0x0, - INTC_GRP_1, - INTC_GRP_2, - INTC_GRP_3, - INTC_GRP_4, - INTC_GRP_5, - INTC_GRP_6, - INTC_GRP_7, - INTC_GRP_8, - INTC_GRP_9, - INTC_GRP_10, - INTC_GRP_11, - INTC_GRP_12, - INTC_GRP_13, - INTC_GRP_14, -}; - -#ifdef BOARD_ASURADA_SCP -static struct { - uint8_t group; -} irqs[SCP_INTC_IRQ_COUNT] = { - /* 0 */ - [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, - [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, - /* 4 */ - [SCP_IRQ_SPM] = { INTC_GRP_0 }, - [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_EINT] = { INTC_GRP_0 }, - [SCP_IRQ_PMIC] = { INTC_GRP_0 }, - /* 8 */ - [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, - [SCP_IRQ_I2C0] = { INTC_GRP_0 }, - [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, - /* 12 */ - [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, - [SCP_IRQ_VOW] = { INTC_GRP_0 }, - [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, - /* 16 */ - [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, - /* 20 */ - [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, - [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, - [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, - /* 24 */ - [SCP_IRQ_GDMA] = { INTC_GRP_0 }, - [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, - [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, - [SCP_IRQ_ADSP] = { INTC_GRP_0 }, - /* 28 */ - [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, - [SCP_IRQ_SPI0] = { INTC_GRP_0 }, - [SCP_IRQ_SPI1] = { INTC_GRP_0 }, - [SCP_IRQ_SPI2] = { INTC_GRP_0 }, - /* 32 */ - [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_DBG] = { INTC_GRP_0 }, - [SCP_IRQ_CCIF0] = { INTC_GRP_0 }, - [SCP_IRQ_CCIF1] = { INTC_GRP_0 }, - /* 36 */ - [SCP_IRQ_CCIF2] = { INTC_GRP_0 }, - [SCP_IRQ_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_USB0] = { INTC_GRP_0 }, - [SCP_IRQ_USB1] = { INTC_GRP_0 }, - /* 40 */ - [SCP_IRQ_DPMAIF] = { INTC_GRP_0 }, - [SCP_IRQ_INFRA] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, - /* 44 */ - [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, - [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, - [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, - /* 48 */ - [SCP_IRQ_MET0] = { INTC_GRP_0 }, - [SCP_IRQ_MET1] = { INTC_GRP_0 }, - [SCP_IRQ_MET2] = { INTC_GRP_0 }, - [SCP_IRQ_MET3] = { INTC_GRP_0 }, - /* 52 */ - [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_CPU_TICK1] = { INTC_GRP_0 }, - [SCP_IRQ_MAD_DATAIN] = { INTC_GRP_0 }, - /* 56 */ - [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, - /* 60 */ - [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, - /* 64 */ - [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, - /* 68 */ - [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, - [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, - /* 72 */ - /* 76 */ - [SCP_IRQ_I2C1_2] = { INTC_GRP_0 }, - [SCP_IRQ_I2C2] = { INTC_GRP_0 }, - /* 80 */ - [SCP_IRQ_AUD2AUDIODSP] = { INTC_GRP_0 }, - [SCP_IRQ_AUD2AUDIODSP_2] = { INTC_GRP_0 }, - [SCP_IRQ_CONN2ADSP_A2DPOL] = { INTC_GRP_0 }, - [SCP_IRQ_CONN2ADSP_BTCVSD] = { INTC_GRP_0 }, - /* 84 */ - [SCP_IRQ_CONN2ADSP_BLEISO] = { INTC_GRP_0 }, - [SCP_IRQ_PCIE2ADSP] = { INTC_GRP_0 }, - [SCP_IRQ_APU2ADSP_ENGINE] = { INTC_GRP_0 }, - [SCP_IRQ_APU2ADSP_MBOX] = { INTC_GRP_0 }, - /* 88 */ - [SCP_IRQ_CCIF3] = { INTC_GRP_0 }, - [SCP_IRQ_I2C_DMA0] = { INTC_GRP_0 }, - [SCP_IRQ_I2C_DMA1] = { INTC_GRP_0 }, - [SCP_IRQ_I2C_DMA2] = { INTC_GRP_0 }, - /* 92 */ - [SCP_IRQ_I2C_DMA3] = { INTC_GRP_0 }, -}; -BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT); -#endif - -#ifdef BOARD_CHERRY_SCP -static struct { - uint8_t group; -} irqs[SCP_INTC_IRQ_COUNT] = { - /* 0 */ - [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, - [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, - /* 4 */ - [SCP_IRQ_SPM] = { INTC_GRP_0 }, - [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_EINT] = { INTC_GRP_0 }, - [SCP_IRQ_PMIC] = { INTC_GRP_0 }, - /* 8 */ - [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, - [SCP_IRQ_I2C0] = { INTC_GRP_0 }, - [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, - /* 12 */ - [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, - [SCP_IRQ_VOW] = { INTC_GRP_0 }, - [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, - /* 16 */ - [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, - /* 20 */ - [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, - [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, - [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, - /* 24 */ - [SCP_IRQ_GDMA] = { INTC_GRP_0 }, - [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, - [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, - [SCP_IRQ_ADSP] = { INTC_GRP_0 }, - /* 28 */ - [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, - [SCP_IRQ_SPI0] = { INTC_GRP_0 }, - [SCP_IRQ_SPI1] = { INTC_GRP_0 }, - [SCP_IRQ_SPI2] = { INTC_GRP_0 }, - /* 32 */ - [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_DBG] = { INTC_GRP_0 }, - [SCP_IRQ_GCE] = { INTC_GRP_0 }, - [SCP_IRQ_MDP_GCE] = { INTC_GRP_0 }, - /* 36 */ - [SCP_IRQ_VDEC] = { INTC_GRP_8 }, - [SCP_IRQ_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_VDEC_LAT] = { INTC_GRP_8 }, - [SCP_IRQ_VDEC1] = { INTC_GRP_8 }, - /* 40 */ - [SCP_IRQ_VDEC1_LAT] = { INTC_GRP_8 }, - [SCP_IRQ_INFRA] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, - /* 44 */ - [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, - [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, - [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, - /* 48 */ - [SCP_IRQ_MET0] = { INTC_GRP_0 }, - [SCP_IRQ_MET1] = { INTC_GRP_0 }, - [SCP_IRQ_MET2] = { INTC_GRP_0 }, - [SCP_IRQ_MET3] = { INTC_GRP_0 }, - /* 52 */ - [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_VDEC_INT_LINE_CNT] = { INTC_GRP_0 }, - [SCP_IRQ_VOW_DATAIN] = { INTC_GRP_0 }, - /* 56 */ - [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_VENC] = { INTC_GRP_8 }, - [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, - /* 60 */ - [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, - /* 64 */ - [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, - /* 68 */ - [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, - [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_29] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_28] = { INTC_GRP_0 }, - /* 72 */ - [SCP_IRQ_CAMSYS_5] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_4] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_3] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_2] = { INTC_GRP_0 }, - /* 76 */ - [SCP_IRQ_HDMIRX_PM_DVI_SQH] = { INTC_GRP_0 }, - [SCP_IRQ_HDMIRX_RESERVED] = { INTC_GRP_0 }, - [SCP_IRQ_NNA0_0] = { INTC_GRP_0 }, - [SCP_IRQ_NNA0_1] = { INTC_GRP_0 }, - /* 80 */ - [SCP_IRQ_NNA0_2] = { INTC_GRP_0 }, - [SCP_IRQ_NNA1_0] = { INTC_GRP_0 }, - [SCP_IRQ_NNA1_1] = { INTC_GRP_0 }, - [SCP_IRQ_NNA1_2] = { INTC_GRP_0 }, - /* 84 */ - [SCP_IRQ_JPEGENC] = { INTC_GRP_0 }, - [SCP_IRQ_JPEGDEC] = { INTC_GRP_0 }, - [SCP_IRQ_JPEGDEC_C2] = { INTC_GRP_0 }, - [SCP_IRQ_VENC_C1] = { INTC_GRP_8 }, - /* 88 */ - [SCP_IRQ_JPEGENC_C1] = { INTC_GRP_0 }, - [SCP_IRQ_JPEGDEC_C1] = { INTC_GRP_0 }, - [SCP_IRQ_HDMITX] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, - /* 92 */ - [SCP_IRQ_EARC] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, - /* 96 */ - [SCP_IRQ_I2C2] = { INTC_GRP_0 }, - [SCP_IRQ_I2C3] = { INTC_GRP_0 }, - [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C3_IBI_WAKE] = { INTC_GRP_0 }, - /* 100 */ - [SCP_IRQ_SYS_I2C_0] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_1] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_2] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_3] = { INTC_GRP_0 }, - /* 104 */ - [SCP_IRQ_SYS_I2C_4] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_5] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_6] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_7] = { INTC_GRP_0 }, - /* 108 */ - [SCP_IRQ_DISP2ADSP_0] = { INTC_GRP_0 }, - [SCP_IRQ_DISP2ADSP_1] = { INTC_GRP_0 }, - [SCP_IRQ_DISP2ADSP_2] = { INTC_GRP_0 }, - [SCP_IRQ_DISP2ADSP_3] = { INTC_GRP_0 }, - /* 112 */ - [SCP_IRQ_DISP2ADSP_4] = { INTC_GRP_0 }, - [SCP_IRQ_VDO1_DISP_MON2ADSP_0] = { INTC_GRP_0 }, - [SCP_IRQ_VDO1_DISP_MON2ADSP_1] = { INTC_GRP_0 }, - [SCP_IRQ_VDO1_DISP_MON2ADSP_2] = { INTC_GRP_0 }, - /* 116 */ - [SCP_IRQ_GCE1_SECURE] = { INTC_GRP_0 }, - [SCP_IRQ_GCE_SECURE] = { INTC_GRP_0 }, -}; -BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT); -#endif - -/* - * Find current interrupt source. - * - * Lower group has higher priority. - * Higher INT number has higher priority. - */ -int chip_get_ec_int(void) -{ - extern volatile int ec_int; - unsigned int group, sta; - int word; - - if (!SCP_CORE0_INTC_IRQ_OUT) - goto error; - - group = read_csr(CSR_VIC_MICAUSE); - - for (word = SCP_INTC_GRP_LEN - 1; word >= 0; --word) { - sta = SCP_CORE0_INTC_IRQ_GRP_STA(group, word); - if (sta) { - ec_int = __fls(sta) + word * 32; - return ec_int; - } - } - -error: - /* unreachable, SCP crashes and dumps registers after returning */ - return -1; -} - -int chip_get_intc_group(int irq) -{ - return irqs[irq].group; -} - -void chip_enable_irq(int irq) -{ - unsigned int word, group, mask; - - word = SCP_INTC_WORD(irq); - group = irqs[irq].group; - mask = BIT(SCP_INTC_BIT(irq)); - - /* disable interrupt */ - SCP_CORE0_INTC_IRQ_EN(word) &= ~mask; - /* set group */ - SCP_CORE0_INTC_IRQ_GRP(group, word) |= mask; - /* set as a wakeup source */ - SCP_CORE0_INTC_SLP_WAKE_EN(word) |= mask; - /* enable interrupt */ - SCP_CORE0_INTC_IRQ_EN(word) |= mask; -} - -void chip_disable_irq(int irq) -{ - /* - * Disabling INTC IRQ in runtime is unstable in MT8192 SCP. - * See b/163682416#comment17. - * - * Ideally, this function will be removed by LTO. - */ - ccprints("WARNING: %s is unsupported", __func__); -} - -void chip_clear_pending_irq(int irq) -{ - unsigned int group = irqs[irq].group; - - /* must clear interrupt source before writing this */ - write_csr(CSR_VIC_MIEMS, group); -} - -int chip_trigger_irq(int irq) -{ - extern volatile int ec_int; - - ec_int = irq; - return irqs[irq].group; -} - -void chip_init_irqs(void) -{ - unsigned int word, group; - - /* INTC init */ - /* clear enable and wakeup settings */ - for (word = 0; word < SCP_INTC_GRP_LEN; ++word) { - SCP_CORE0_INTC_IRQ_EN(word) = 0x0; - SCP_CORE0_INTC_SLP_WAKE_EN(word) = 0x0; - - /* clear group settings */ - for (group = 0; group < SCP_INTC_GRP_COUNT; ++group) - SCP_CORE0_INTC_IRQ_GRP(group, word) = 0x0; - } - /* reset to default polarity */ - SCP_CORE0_INTC_IRQ_POL(0) = SCP_INTC_IRQ_POL0; - SCP_CORE0_INTC_IRQ_POL(1) = SCP_INTC_IRQ_POL1; - SCP_CORE0_INTC_IRQ_POL(2) = SCP_INTC_IRQ_POL2; -#if SCP_INTC_GRP_LEN > 3 - SCP_CORE0_INTC_IRQ_POL(3) = SCP_INTC_IRQ_POL3; -#endif - - /* GVIC init */ - /* enable all groups as interrupt sources */ - write_csr(CSR_VIC_MIMASK_G0, 0xffffffff); - /* use level trigger */ - write_csr(CSR_VIC_MILSEL_G0, 0xffffffff); - /* enable all groups as wakeup sources */ - write_csr(CSR_VIC_MIWAKEUP_G0, 0xffffffff); - - /* enable GVIC */ - set_csr(CSR_MCTREN, CSR_MCTREN_VIC); -} diff --git a/chip/mt_scp/rv32i_common/ipi.c b/chip/mt_scp/rv32i_common/ipi.c deleted file mode 100644 index cba5c65d0b..0000000000 --- a/chip/mt_scp/rv32i_common/ipi.c +++ /dev/null @@ -1,184 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "atomic.h" -#include "cache.h" -#include "common.h" -#include "console.h" -#include "hooks.h" -#include "hostcmd.h" -#include "ipi_chip.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" -#include "video.h" - -#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args) -#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args) - -static uint8_t init_done; - -static struct mutex ipi_lock; -static struct ipc_shared_obj *const ipi_send_buf = - (struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR; -static struct ipc_shared_obj *const ipi_recv_buf = - (struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR + - sizeof(struct ipc_shared_obj)); - -static uint32_t disable_irq_count, saved_int_mask; - -void ipi_disable_irq(void) -{ - if (atomic_read_add(&disable_irq_count, 1) == 0) - saved_int_mask = read_clear_int_mask(); -} - -void ipi_enable_irq(void) -{ - if (atomic_read_sub(&disable_irq_count, 1) == 1) - set_int_mask(saved_int_mask); -} - -static int ipi_is_busy(void) -{ - return SCP_SCP2APMCU_IPC_SET & IPC_SCP2HOST; -} - -static void ipi_wake_ap(int32_t id) -{ - if (id >= IPI_COUNT) - return; - - if (*ipi_wakeup_table[id]) - SCP_SCP2SPM_IPC_SET = IPC_SCP2HOST; -} - -int ipi_send(int32_t id, const void *buf, uint32_t len, int wait) -{ - int ret; - - if (!init_done) { - CPRINTS("IPI has not initialized"); - return EC_ERROR_BUSY; - } - - if (in_interrupt_context()) { - CPRINTS("invoke %s() in ISR context", __func__); - return EC_ERROR_BUSY; - } - - if (len > sizeof(ipi_send_buf->buffer)) { - CPRINTS("data length exceeds limitation"); - return EC_ERROR_INVAL; - } - - ipi_disable_irq(); - mutex_lock(&ipi_lock); - - if (ipi_is_busy()) { - /* - * If the following conditions meet, - * 1) There is an IPI pending in AP. - * 2) The incoming IPI is a wakeup IPI. - * then it assumes that AP is in suspend state. - * Send a AP wakeup request to SPM. - * - * The incoming IPI will be checked if it's a wakeup source. - */ - ipi_wake_ap(id); - - CPRINTS("IPI busy, id=%d", id); - ret = EC_ERROR_BUSY; - goto error; - } - - ipi_send_buf->id = id; - ipi_send_buf->len = len; - memcpy(ipi_send_buf->buffer, buf, len); - - /* flush memory cache (if any) */ - cache_flush_dcache_range((uintptr_t)ipi_send_buf, - sizeof(*ipi_send_buf)); - - /* interrupt AP to handle the message */ - ipi_wake_ap(id); - SCP_SCP2APMCU_IPC_SET = IPC_SCP2HOST; - - if (wait) - while (ipi_is_busy()) - ; - - ret = EC_SUCCESS; -error: - mutex_unlock(&ipi_lock); - ipi_enable_irq(); - return ret; -} - -static void ipi_enable_deferred(void) -{ - struct scp_run_t scp_run; - int ret; - - init_done = 1; - - /* inform AP that SCP is up */ - scp_run.signaled = 1; - strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW), - SCP_FW_VERSION_LEN); - scp_run.dec_capability = video_get_dec_capability(); - scp_run.enc_capability = video_get_enc_capability(); - - ret = ipi_send(SCP_IPI_INIT, (void *)&scp_run, sizeof(scp_run), 1); - if (ret) { - CPRINTS("failed to send initialization IPC messages"); - init_done = 0; - return; - } - -#ifdef HAS_TASK_HOSTCMD - hostcmd_init(); -#endif - - task_enable_irq(SCP_IRQ_GIPC_IN0); -} -DECLARE_DEFERRED(ipi_enable_deferred); - -static void ipi_init(void) -{ - memset(ipi_send_buf, 0, sizeof(struct ipc_shared_obj)); - memset(ipi_recv_buf, 0, sizeof(struct ipc_shared_obj)); - - /* enable IRQ after all tasks are up */ - hook_call_deferred(&ipi_enable_deferred_data, 0); -} -DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT); - -static void ipi_handler(void) -{ - if (ipi_recv_buf->id >= IPI_COUNT) { - CPRINTS("invalid IPI, id=%d", ipi_recv_buf->id); - return; - } - - CPRINTS("IPI %d", ipi_recv_buf->id); - - ipi_handler_table[ipi_recv_buf->id]( - ipi_recv_buf->id, ipi_recv_buf->buffer, ipi_recv_buf->len); -} - -static void irq_group7_handler(void) -{ - extern volatile int ec_int; - - if (SCP_GIPC_IN_SET & GIPC_IN(0)) { - ipi_handler(); - SCP_GIPC_IN_CLR = GIPC_IN(0); - asm volatile ("fence.i" ::: "memory"); - task_clear_pending_irq(ec_int); - } -} -DECLARE_IRQ(7, irq_group7_handler, 0); diff --git a/chip/mt_scp/rv32i_common/ipi_chip.h b/chip/mt_scp/rv32i_common/ipi_chip.h deleted file mode 100644 index 47a9434b09..0000000000 --- a/chip/mt_scp/rv32i_common/ipi_chip.h +++ /dev/null @@ -1,86 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_IPI_CHIP_H -#define __CROS_EC_IPI_CHIP_H - -#include "common.h" - -/* - * Length of EC version string is at most 32 byte (NULL included), which - * also aligns SCP fw_version length. - */ -#define SCP_FW_VERSION_LEN 32 - -#ifndef SCP_IPI_INIT -#error If CONFIG_IPI is enabled, SCP_IPI_INIT must be defined. -#endif - -/* - * Share buffer layout for SCP_IPI_INIT response. This structure should sync - * across kernel and EC. - */ -struct scp_run_t { - uint32_t signaled; - int8_t fw_ver[SCP_FW_VERSION_LEN]; - uint32_t dec_capability; - uint32_t enc_capability; -}; - -/* - * The layout of the IPC0 AP/SCP shared buffer. - * This should sync across kernel and EC. - */ -struct ipc_shared_obj { - /* IPI ID */ - int32_t id; - /* Length of the contents in buffer. */ - uint32_t len; - /* Shared buffer contents. */ - uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE]; -}; - -/* Send a IPI contents to AP. This shouldn't be used in ISR context. */ -int ipi_send(int32_t id, const void *buf, uint32_t len, int wait); - -/* - * An IPC IRQ could be shared across many IPI handlers. - * Those handlers would usually operate on disabling or enabling the IPC IRQ. - * This may disorder the actual timing to on/off the IRQ when there are many - * tasks try to operate on it. As a result, any access to the SCP_IRQ_* - * should go through ipi_{en,dis}able_irq(), which support a counter to - * enable/disable the IRQ at correct timing. - */ -/* Disable IPI IRQ. */ -void ipi_disable_irq(void); -/* Enable IPI IRQ. */ -void ipi_enable_irq(void); - -/* IPI tables */ -extern void (*const ipi_handler_table[])(int32_t, void *, uint32_t); -extern int *const ipi_wakeup_table[]; - -/* Helper macros to build the IPI handler and wakeup functions. */ -#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler) -#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup) - -/* - * Macro to declare an IPI handler. - * _id: The ID of the IPI - * handler: The IPI handler function - * is_wakeup_src: Declare IPI ID as a wake-up source or not - */ -#define DECLARE_IPI(_id, handler, is_wakeup_src) \ - struct ipi_num_check##_id { \ - int tmp1[_id < IPI_COUNT ? 1 : -1]; \ - int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ - }; \ - void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ - { \ - handler(id, buf, len); \ - } \ - const int __keep IPI_WAKEUP(_id) = is_wakeup_src - -#endif /* __CROS_EC_IPI_CHIP_H */ diff --git a/chip/mt_scp/rv32i_common/ipi_table.c b/chip/mt_scp/rv32i_common/ipi_table.c deleted file mode 100644 index 8fe3f1e598..0000000000 --- a/chip/mt_scp/rv32i_common/ipi_table.c +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * IPI handlers declaration - */ - -#include "common.h" -#include "ipi_chip.h" - -typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len); - -#ifndef PASS -#define PASS 1 -#endif - -#define ipi_arguments int32_t id, void *data, uint32_t len - -#if PASS == 1 -void ipi_handler_undefined(ipi_arguments) { } - -const int ipi_wakeup_undefined; - -#define table(type, name, x) x - -#define ipi_x_func(suffix, args, number) \ - extern void __attribute__( \ - (used, weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ - ipi_##number##_##suffix(args); - -#define ipi_x_var(suffix, number) \ - extern int __attribute__( \ - (weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ - ipi_##number##_##suffix; - -#endif /* PASS == 1 */ - -#if PASS == 2 - -#undef table -#undef ipi_x_func -#undef ipi_x_var - -#define table(type, name, x) \ - type const name[] \ - __attribute__((aligned(4), used, section(".rodata.ipi"))) = {x} - -#define ipi_x_var(suffix, number) \ - [number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix, - -#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number) - -#endif /* PASS == 2 */ - -/* - * Include generated IPI table (by util/gen_ipi_table). The contents originate - * from IPI_COUNT definition in board.h - */ -#include "ipi_table_gen.inc" - -#if PASS == 1 -#undef PASS -#define PASS 2 -#include "ipi_table.c" -BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT); -BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT); -#endif diff --git a/chip/mt_scp/rv32i_common/memmap.c b/chip/mt_scp/rv32i_common/memmap.c deleted file mode 100644 index a666bb23d7..0000000000 --- a/chip/mt_scp/rv32i_common/memmap.c +++ /dev/null @@ -1,114 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "cache.h" -#include "registers.h" -#include "stdint.h" - -/* - * Map SCP address (bits 31~28) to AP address - * - * SCP address AP address Note - * - * 0x0000_0000 SRAM - * 0x1000_0000 0x5000_0000 CPU DRAM - * 0x2000_0000 0x7000_0000 - * 0x3000_0000 - * - * 0x4000_0000 - * 0x5000_0000 0x0000_0000 - * 0x6000_0000 0x1000_0000 - * 0x7000_0000 0xa000_0000 - * - * 0x8000_0000 - * 0x9000_0000 0x8000_0000 - * 0xa000_0000 0x9000_0000 - * 0xb000_0000 - * - * 0xc000_0000 0x8000_0000 - * 0xd000_0000 0x2000_0000 - * 0xe000_0000 0x3000_0000 - * 0xf000_0000 0x6000_0000 - */ - -#define REMAP_ADDR_SHIFT 28 -#define REMAP_ADDR_LSB_MASK (BIT(REMAP_ADDR_SHIFT) - 1) -#define REMAP_ADDR_MSB_MASK ((~0) << REMAP_ADDR_SHIFT) -#define MAP_INVALID 0xff - -static const uint8_t addr_map[16] = { - MAP_INVALID, /* SRAM */ - 0x5, /* ext_addr_0x1 */ - 0x7, /* ext_addr_0x2 */ - MAP_INVALID, /* no ext_addr_0x3 */ - - MAP_INVALID, /* no ext_addr_0x4 */ - 0x0, /* ext_addr_0x5 */ - 0x1, /* ext_addr_0x6 */ - 0xa, /* ext_addr_0x7 */ - - MAP_INVALID, /* no ext_addr_0x8 */ - 0x8, /* ext_addr_0x9 */ - 0x9, /* ext_addr_0xa */ - MAP_INVALID, /* no ext_addr_0xb */ - - 0x8, /* ext_addr_0xc */ - 0x2, /* ext_addr_0xd */ - 0x3, /* ext_addr_0xe */ - 0x6, /* ext_addr_0xf */ -}; - -void memmap_init(void) -{ - SCP_R_REMAP_0X0123 = - (uint32_t)addr_map[0x1] << 8 | - (uint32_t)addr_map[0x2] << 16; - - SCP_R_REMAP_0X4567 = - (uint32_t)addr_map[0x5] << 8 | - (uint32_t)addr_map[0x6] << 16 | - (uint32_t)addr_map[0x7] << 24; - - SCP_R_REMAP_0X89AB = - (uint32_t)addr_map[0x9] << 8 | - (uint32_t)addr_map[0xa] << 16; - - SCP_R_REMAP_0XCDEF = - (uint32_t)addr_map[0xc] | - (uint32_t)addr_map[0xd] << 8 | - (uint32_t)addr_map[0xe] << 16 | - (uint32_t)addr_map[0xf] << 24; - - cache_init(); -} - -int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr) -{ - int i; - uint8_t msb = ap_addr >> REMAP_ADDR_SHIFT; - - for (i = 0; i < ARRAY_SIZE(addr_map); ++i) { - if (addr_map[i] != msb) - continue; - - *scp_addr = (ap_addr & REMAP_ADDR_LSB_MASK) | - (i << REMAP_ADDR_SHIFT); - return EC_SUCCESS; - } - - return EC_ERROR_INVAL; -} - -int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr) -{ - int i = scp_addr >> REMAP_ADDR_SHIFT; - - if (addr_map[i] == MAP_INVALID) - return EC_ERROR_INVAL; - - *ap_addr = (scp_addr & REMAP_ADDR_LSB_MASK) | - (addr_map[i] << REMAP_ADDR_SHIFT); - return EC_SUCCESS; -} diff --git a/chip/mt_scp/rv32i_common/memmap.h b/chip/mt_scp/rv32i_common/memmap.h deleted file mode 100644 index 0857c9a89e..0000000000 --- a/chip/mt_scp/rv32i_common/memmap.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_MEMMAP_H -#define __CROS_EC_MEMMAP_H - -#include "stdint.h" - -void memmap_init(void); - -/** - * Translate AP addr to SCP addr. - * - * @param ap_addr AP address to translate - * @param scp_addr Translated AP address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr); - -/** - * Translate SCP addr to AP addr. - * - * @param scp_addr SCP address to translate - * @param ap_addr Translated SCP address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr); - -#endif /* #ifndef __CROS_EC_MEMMAP_H */ diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h deleted file mode 100644 index adbef5f98b..0000000000 --- a/chip/mt_scp/rv32i_common/registers.h +++ /dev/null @@ -1,211 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Register map */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" -#include "compile_time_macros.h" -#include "intc.h" - -#define UNIMPLEMENTED_GPIO_BANK 0 - -#define SCP_REG_BASE 0x70000000 - -/* clock control */ -#define SCP_CLK_CTRL_BASE (SCP_REG_BASE + 0x21000) -/* system clock counter value */ -#define SCP_CLK_SYS_VAL REG32(SCP_CLK_CTRL_BASE + 0x0014) -#define CLK_SYS_VAL_MASK (0x3ff << 0) -#define CLK_SYS_VAL_VAL(v) ((v) & CLK_SYS_VAL_MASK) -/* ULPOSC clock counter value */ -#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_CTRL_BASE + 0x0018) -#define CLK_HIGH_VAL_MASK (0x1f << 0) -#define CLK_HIGH_VAL_VAL(v) ((v) & CLK_HIGH_VAL_MASK) -/* sleep mode control */ -#define SCP_SLEEP_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0020) -#define SLP_CTRL_EN BIT(0) -#define VREQ_COUNT_MASK (0x7F << 1) -#define VREQ_COUNT_VAL(v) (((v) << 1) & VREQ_COUNT_MASK) -#define SPM_SLP_MODE BIT(8) -/* clock divider select */ -#define SCP_CLK_DIV_SEL REG32(SCP_CLK_CTRL_BASE + 0x0024) -#define CLK_DIV_SEL1 0 -#define CLK_DIV_SEL2 1 -#define CLK_DIV_SEL4 2 -#define CLK_DIV_SEL3 3 -/* clock gate */ -#define SCP_SET_CLK_CG REG32(SCP_CLK_CTRL_BASE + 0x0030) -#define CG_TIMER_MCLK BIT(0) -#define CG_TIMER_BCLK BIT(1) -#define CG_MAD_MCLK BIT(2) -#define CG_I2C_MCLK BIT(3) -#define CG_I2C_BCLK BIT(4) -#define CG_GPIO_MCLK BIT(5) -#define CG_AP2P_MCLK BIT(6) -#define CG_UART0_MCLK BIT(7) -#define CG_UART0_BCLK BIT(8) -#define CG_UART0_RST BIT(9) -#define CG_UART1_MCLK BIT(10) -#define CG_UART1_BCLK BIT(11) -#define CG_UART1_RST BIT(12) -#define CG_SPI0 BIT(13) -#define CG_SPI1 BIT(14) -#define CG_SPI2 BIT(15) -#define CG_DMA_CH0 BIT(16) -#define CG_DMA_CH1 BIT(17) -#define CG_DMA_CH2 BIT(18) -#define CG_DMA_CH3 BIT(19) -#define CG_I3C0 BIT(21) -#define CG_I3C1 BIT(22) -#define CG_DMA2_CH0 BIT(23) -#define CG_DMA2_CH1 BIT(24) -#define CG_DMA2_CH2 BIT(25) -#define CG_DMA2_CH3 BIT(26) -/* UART clock select */ -#define SCP_UART_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0044) -#define UART0_CK_SEL_SHIFT 0 -#define UART0_CK_SEL_MASK (0x3 << UART0_CK_SEL_SHIFT) -#define UART0_CK_SEL_VAL(v) ((v) & UART0_CK_SEL_MASK) -#define UART0_CK_SW_STATUS_MASK (0xf << 8) -#define UART0_CK_SW_STATUS_VAL(v) ((v) & UART0_CK_SW_STATUS_MASK) -#define UART1_CK_SEL_SHIFT 16 -#define UART1_CK_SEL_MASK (0x3 << UART1_CK_SEL_SHIFT) -#define UART1_CK_SEL_VAL(v) ((v) & UART1_CK_SEL_MASK) -#define UART1_CK_SW_STATUS_MASK (0xf << 24) -#define UART1_CK_SW_STATUS_VAL(v) ((v) & UART1_CK_SW_STATUS_MASK) -#define UART_CK_SEL_26M 0 -#define UART_CK_SEL_32K 1 -#define UART_CK_SEL_ULPOSC 2 -#define UART_CK_SW_STATUS_26M BIT(0) -#define UART_CK_SW_STATUS_32K BIT(1) -#define UART_CK_SW_STATUS_ULPOS BIT(2) -/* BCLK clock select */ -#define SCP_BCLK_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0048) -#define BCLK_CK_SEL_SYS_DIV8 0 -#define BCLK_CK_SEL_32K 1 -#define BCLK_CK_SEL_ULPOSC_DIV8 2 -/* VREQ control */ -#define SCP_CPU_VREQ_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0054) -#define VREQ_SEL BIT(0) -#define VREQ_VALUE BIT(4) -#define VREQ_EXT_SEL BIT(8) -#define VREQ_DVFS_SEL BIT(16) -#define VREQ_DVFS_VALUE BIT(20) -#define VREQ_DVFS_EXT_SEL BIT(24) -#define VREQ_SRCLKEN_SEL BIT(27) -#define VREQ_SRCLKEN_VALUE BIT(28) -/* clock on control */ -#define SCP_CLK_HIGH_CORE_CG REG32(SCP_CLK_CTRL_BASE + 0x005C) -#define HIGH_CORE_CG BIT(1) -#define SCP_CLK_ON_CTRL REG32(SCP_CLK_CTRL_BASE + 0x006C) -#define HIGH_AO BIT(0) -#define HIGH_DIS_SUB BIT(1) -#define HIGH_CG_AO BIT(2) -#define HIGH_CORE_AO BIT(4) -#define HIGH_CORE_DIS_SUB BIT(5) -#define HIGH_CORE_CG_AO BIT(6) - -/* system control */ -#define SCP_SYS_CTRL REG32(SCP_REG_BASE + 0x24000) -#define AUTO_DDREN BIT(9) - -/* IPC */ -#define SCP_SCP2APMCU_IPC_SET REG32(SCP_REG_BASE + 0x24080) -#define SCP_SCP2SPM_IPC_SET REG32(SCP_REG_BASE + 0x24090) -#define IPC_SCP2HOST BIT(0) -#define SCP_GIPC_IN_SET REG32(SCP_REG_BASE + 0x24098) -#define SCP_GIPC_IN_CLR REG32(SCP_REG_BASE + 0x2409C) -#define GIPC_IN(n) BIT(n) - -/* UART */ -#define SCP_UART_COUNT 2 -#define UART_TX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _TX) -#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX) -#define SCP_UART0_BASE (SCP_REG_BASE + 0x26000) -#define SCP_UART1_BASE (SCP_REG_BASE + 0x27000) -#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE) -#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset] - -/* WDT */ -#define SCP_CORE0_WDT_IRQ REG32(SCP_REG_BASE + 0x30030) -#define SCP_CORE0_WDT_CFG REG32(SCP_REG_BASE + 0x30034) -#define WDT_FREQ 33825 /* 0xFFFFF / 31 */ -#define WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ -#define WDT_PERIOD(ms) (WDT_FREQ * (ms) / 1000) -#define WDT_EN BIT(31) -#define SCP_CORE0_WDT_KICK REG32(SCP_REG_BASE + 0x30038) -#define SCP_CORE0_WDT_CUR_VAL REG32(SCP_REG_BASE + 0x3003C) - -/* INTC */ -#define SCP_INTC_WORD(irq) ((irq) >> 5) /* word length = 2^5 */ -#define SCP_INTC_BIT(irq) ((irq) & 0x1F) /* bit shift =LSB[0:4] */ -#define SCP_INTC_GRP_COUNT 15 -#define SCP_INTC_GRP_GAP 4 - -#define SCP_CORE0_INTC_IRQ_BASE (SCP_REG_BASE + 0x32000) -#define SCP_CORE0_INTC_IRQ_STA(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)] -#define SCP_CORE0_INTC_IRQ_EN(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)] -#define SCP_CORE0_INTC_IRQ_POL(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)] -#define SCP_CORE0_INTC_IRQ_GRP(g, w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \ - ((g) << SCP_INTC_GRP_GAP))[(w)] -#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \ - ((g) << SCP_INTC_GRP_GAP))[(w)] -#define SCP_CORE0_INTC_SLP_WAKE_EN(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)] -#define SCP_CORE0_INTC_IRQ_OUT REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250) -/* UART */ -#define SCP_CORE0_INTC_UART0_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258) -#define SCP_CORE0_INTC_UART1_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C) -#define SCP_CORE0_INTC_UART_RX_IRQ(n) CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ) - -/* XGPT (general purpose timer) */ -#define NUM_TIMERS 6 -#define SCP_CORE0_TIMER_BASE(n) (SCP_REG_BASE + 0x33000 + (0x10 * (n))) -#define SCP_CORE0_TIMER_EN(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000) -#define TIMER_EN BIT(0) -#define TIMER_CLK_SRC_32K (0 << 4) -#define TIMER_CLK_SRC_26M (1 << 4) -#define TIMER_CLK_SRC_BCLK (2 << 4) -#define TIMER_CLK_SRC_MCLK (3 << 4) -#define TIMER_CLK_SRC_MASK (3 << 4) -#define SCP_CORE0_TIMER_RST_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004) -#define SCP_CORE0_TIMER_CUR_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008) -#define SCP_CORE0_TIMER_IRQ_CTRL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C) -#define TIMER_IRQ_EN BIT(0) -#define TIMER_IRQ_STATUS BIT(4) -#define TIMER_IRQ_CLR BIT(5) -#define SCP_IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n) - -/* secure control */ -#define SCP_SEC_CTRL REG32(SCP_REG_BASE + 0xA5000) -#define VREQ_SECURE_DIS BIT(4) -/* memory remap */ -#define SCP_R_REMAP_0X0123 REG32(SCP_REG_BASE + 0xA5060) -#define SCP_R_REMAP_0X4567 REG32(SCP_REG_BASE + 0xA5064) -#define SCP_R_REMAP_0X89AB REG32(SCP_REG_BASE + 0xA5068) -#define SCP_R_REMAP_0XCDEF REG32(SCP_REG_BASE + 0xA506C) - -/* external address: AP */ -#define AP_REG_BASE 0x60000000 /* 0x10000000 remap to 0x6 */ -/* AP GPIO */ -#define AP_GPIO_BASE (AP_REG_BASE + 0x5000) -#define AP_GPIO_MODE11_SET REG32(AP_GPIO_BASE + 0x03B4) -#define AP_GPIO_MODE11_CLR REG32(AP_GPIO_BASE + 0x03B8) -#define AP_GPIO_MODE12_SET REG32(AP_GPIO_BASE + 0x03C4) -#define AP_GPIO_MODE12_CLR REG32(AP_GPIO_BASE + 0x03C8) -#define AP_GPIO_MODE20_SET REG32(AP_GPIO_BASE + 0x0444) -#define AP_GPIO_MODE20_CLR REG32(AP_GPIO_BASE + 0x0448) - -#include "clock_regs.h" - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/mt_scp/rv32i_common/system.c b/chip/mt_scp/rv32i_common/system.c deleted file mode 100644 index 0e12154f6d..0000000000 --- a/chip/mt_scp/rv32i_common/system.c +++ /dev/null @@ -1,50 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System : hardware specific implementation */ - -#include "csr.h" -#include "memmap.h" -#include "registers.h" -#include "system.h" - -void system_pre_init(void) -{ - memmap_init(); - - /* enable CPU and platform low power CG */ - /* enable CPU DCM */ - set_csr(CSR_MCTREN, CSR_MCTREN_CG); - - /* Disable jump (it has only RW) */ - system_disable_jump(); -} - -void system_reset(int flags) -{ - while (1) - ; -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - return EC_ERROR_INVAL; -} - -const char *system_get_chip_vendor(void) -{ - return "mtk"; -} - -const char *system_get_chip_name(void) -{ - /* Support only SCP_A for now */ - return "scp_a"; -} - -const char *system_get_chip_revision(void) -{ - return ""; -} diff --git a/chip/mt_scp/rv32i_common/uart.c b/chip/mt_scp/rv32i_common/uart.c deleted file mode 100644 index 35b4003c9f..0000000000 --- a/chip/mt_scp/rv32i_common/uart.c +++ /dev/null @@ -1,161 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SCP UART module */ - -#include "csr.h" -#include "system.h" -#include "uart.h" -#include "uart_regs.h" -#include "util.h" - -/* - * UARTN == 0, SCP UART0 - * UARTN == 1, SCP UART1 - * UARTN == 2, AP UART1 - */ -#define UARTN CONFIG_UART_CONSOLE -#define UART_IDLE_WAIT_US 500 -#define UART_INTC_GROUP 12 - -static uint8_t init_done, tx_started; - -void uart_init(void) -{ - const uint32_t baud_rate = CONFIG_UART_BAUD_RATE; - const uint32_t uart_clock = 26000000; - const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16); - - uart_init_pinmux(); - - /* Clear FIFO */ - UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO - | UART_FCR_CLEAR_RCVR - | UART_FCR_CLEAR_XMIT; - /* Line control: parity none, 8 bit, 1 stop bit */ - UART_LCR(UARTN) = UART_LCR_WLEN8; - /* For baud rate <= 115200 */ - UART_HIGHSPEED(UARTN) = 0; - - /* DLAB start */ - UART_LCR(UARTN) |= UART_LCR_DLAB; - UART_DLL(UARTN) = div & 0xff; - UART_DLH(UARTN) = (div >> 8) & 0xff; - UART_LCR(UARTN) &= ~UART_LCR_DLAB; - /* DLAB end */ - - /* Enable received data interrupt */ - UART_IER(UARTN) |= UART_IER_RDI; - -#if (UARTN < SCP_UART_COUNT) - task_enable_irq(UART_TX_IRQ(UARTN)); - task_enable_irq(UART_RX_IRQ(UARTN)); -#endif - - init_done = 1; -} - -int uart_init_done(void) -{ - return init_done; -} - -void uart_tx_flush(void) -{ - while (!(UART_LSR(UARTN) & UART_LSR_TEMT)) - ; -} - -int uart_tx_ready(void) -{ - return UART_LSR(UARTN) & UART_LSR_THRE; -} - -int uart_rx_available(void) -{ - return UART_LSR(UARTN) & UART_LSR_DR; -} - -void uart_write_char(char c) -{ - while (!uart_tx_ready()) - ; - - UART_THR(UARTN) = c; -} - -int uart_read_char(void) -{ - return UART_RBR(UARTN); -} - -void uart_tx_start(void) -{ - tx_started = 1; - if (UART_IER(UARTN) & UART_IER_THRI) - return; - disable_sleep(SLEEP_MASK_UART); - UART_IER(UARTN) |= UART_IER_THRI; -} - -void uart_tx_stop(void) -{ - /* - * Workaround for b/157541273. - * Don't unset the THRI flag unless we are in the UART ISR. - * - * Note: - * MICAUSE denotes current INTC group number. - */ - if (in_interrupt_context() && - read_csr(CSR_VIC_MICAUSE) != UART_INTC_GROUP) - return; - - tx_started = 0; - UART_IER(UARTN) &= ~UART_IER_THRI; - enable_sleep(SLEEP_MASK_UART); -} - -static void uart_process(void) -{ - uart_process_input(); - uart_process_output(); -} - -#if (UARTN < SCP_UART_COUNT) -static void uart_irq_handler(void) -{ - extern volatile int ec_int; - - switch (ec_int) { - case UART_TX_IRQ(UARTN): - uart_process(); - task_clear_pending_irq(ec_int); - break; - case UART_RX_IRQ(UARTN): - uart_process(); - SCP_CORE0_INTC_UART_RX_IRQ(UARTN) = BIT(0); - asm volatile ("fence.i" ::: "memory"); - task_clear_pending_irq(ec_int); - break; - } -} -DECLARE_IRQ(UART_INTC_GROUP, uart_irq_handler, 0); -#else - -#ifndef HAS_TASK_APUART -#error "APUART task hasn't defined in ec.tasklist." -#endif - -void uart_task(void) -{ - while (1) { - if (uart_rx_available() || tx_started) - uart_process(); - else - task_wait_event(UART_IDLE_WAIT_US); - } -} -#endif diff --git a/chip/mt_scp/rv32i_common/uart_regs.h b/chip/mt_scp/rv32i_common/uart_regs.h deleted file mode 100644 index c88b9c758b..0000000000 --- a/chip/mt_scp/rv32i_common/uart_regs.h +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SCP UART module registers */ - -#ifndef __CROS_EC_UART_REGS_H -#define __CROS_EC_UART_REGS_H - -#include "registers.h" - -/* Chip specific function for setting UART pinmux. */ -void uart_init_pinmux(void); - -/* DLAB (Divisor Latch Access Bit) == 0 */ - -/* (Read) receiver buffer register */ -#define UART_RBR(n) UART_REG(n, 0) -/* (Write) transmitter holding register */ -#define UART_THR(n) UART_REG(n, 0) -/* (Write) interrupt enable register */ -#define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI BIT(0) /* received data */ -#define UART_IER_THRI BIT(1) /* THR empty */ -#define UART_IER_RLSI BIT(2) /* receiver LSR change */ -#define UART_IER_MSI BIT(3) /* MSR change */ -/* (Read) interrupt identification register */ -#define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_ID_MASK 0x0e -#define UART_IIR_MSI 0x00 /* modem status change */ -#define UART_IIR_NO_INT 0x01 /* no int pending */ -#define UART_IIR_THRI 0x02 /* THR empty */ -#define UART_IIR_RDI 0x04 /* received data available */ -#define UART_IIR_RLSI 0x06 /* line status change */ -/* (Write) FIFO control register */ -#define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO BIT(0) /* enable FIFO */ -#define UART_FCR_CLEAR_RCVR BIT(1) /* clear receive FIFO */ -#define UART_FCR_CLEAR_XMIT BIT(2) /* clear transmit FIFO */ -#define UART_FCR_DMA_SELECT BIT(3) /* select DMA mode */ -/* (Write) line control register */ -#define UART_LCR(n) UART_REG(n, 3) -#define UART_LCR_WLEN5 0 /* word length 5 bits */ -#define UART_LCR_WLEN6 1 -#define UART_LCR_WLEN7 2 -#define UART_LCR_WLEN8 3 -#define UART_LCR_STOP BIT(2) /* stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY BIT(3) /* parity enable */ -#define UART_LCR_EPAR BIT(4) /* even parity */ -#define UART_LCR_SPAR BIT(5) /* stick parity */ -#define UART_LCR_SBC BIT(6) /* set break control */ -#define UART_LCR_DLAB BIT(7) /* divisor latch access */ -/* (Write) modem control register */ -#define UART_MCR(n) UART_REG(n, 4) -/* (Read) line status register */ -#define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR BIT(0) /* data ready */ -#define UART_LSR_OE BIT(1) /* overrun error */ -#define UART_LSR_PE BIT(2) /* parity error */ -#define UART_LSR_FE BIT(3) /* frame error */ -#define UART_LSR_BI BIT(4) /* break interrupt */ -#define UART_LSR_THRE BIT(5) /* THR empty */ -#define UART_LSR_TEMT BIT(6) /* THR empty, line idle */ -#define UART_LSR_FIFOE BIT(7) /* FIFO error */ -/* (Read) modem status register */ -#define UART_MSR(n) UART_REG(n, 6) -/* (Read/Write) scratch register */ -#define UART_SCR(n) UART_REG(n, 7) - -/* DLAB == 1 */ - -/* (Write) divisor latch */ -#define UART_DLL(n) UART_REG(n, 0) -#define UART_DLH(n) UART_REG(n, 1) - -/* MTK extension */ -#define UART_HIGHSPEED(n) UART_REG(n, 9) - -#endif /* __CROS_EC_UART_REGS_H */ diff --git a/chip/mt_scp/rv32i_common/video.h b/chip/mt_scp/rv32i_common/video.h deleted file mode 100644 index e4538c4456..0000000000 --- a/chip/mt_scp/rv32i_common/video.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_VIDEO_H -#define __CROS_EC_VIDEO_H - -#include "common.h" - -/* - * Video decoder supported capability - */ -#define VDEC_CAP_4K_DISABLED BIT(4) -#define VDEC_CAP_MM21 BIT(5) -#define VDEC_CAP_MT21C BIT(6) -#define VDEC_CAP_H264_SLICE BIT(8) -#define VDEC_CAP_VP8_FRAME BIT(9) -#define VDEC_CAP_VP9_FRAME BIT(10) -#define VDEC_CAP_IRQ_IN_SCP BIT(16) - -/* - * Video encoder supported capability: - * BIT(0): enable 4K - */ -#define VENC_CAP_4K BIT(0) - -uint32_t video_get_enc_capability(void); -uint32_t video_get_dec_capability(void); - -#endif /* #ifndef __CROS_EC_VIDEO_H */ diff --git a/chip/mt_scp/rv32i_common/watchdog.c b/chip/mt_scp/rv32i_common/watchdog.c deleted file mode 100644 index 72ca5edad8..0000000000 --- a/chip/mt_scp/rv32i_common/watchdog.c +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "common.h" -#include "hooks.h" -#include "registers.h" -#include "watchdog.h" - -void watchdog_reload(void) -{ - SCP_CORE0_WDT_KICK = BIT(0); -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ - const uint32_t timeout = WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS); - - /* disable watchdog */ - SCP_CORE0_WDT_CFG &= ~WDT_EN; - /* clear watchdog irq */ - SCP_CORE0_WDT_IRQ |= BIT(0); - /* enable watchdog */ - SCP_CORE0_WDT_CFG = WDT_EN | timeout; - /* reload watchdog */ - watchdog_reload(); - - return EC_SUCCESS; -} |