diff options
Diffstat (limited to 'chip/npcx/spiflashfw')
| -rw-r--r-- | chip/npcx/spiflashfw/monitor_hdr.c | 4 | ||||
| -rw-r--r-- | chip/npcx/spiflashfw/npcx_monitor.c | 19 | ||||
| -rw-r--r-- | chip/npcx/spiflashfw/npcx_monitor.h | 12 | ||||
| -rw-r--r-- | chip/npcx/spiflashfw/npcx_monitor.ld | 2 |
4 files changed, 18 insertions, 19 deletions
diff --git a/chip/npcx/spiflashfw/monitor_hdr.c b/chip/npcx/spiflashfw/monitor_hdr.c index 219a037d27..09606c4c31 100644 --- a/chip/npcx/spiflashfw/monitor_hdr.c +++ b/chip/npcx/spiflashfw/monitor_hdr.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -20,7 +20,7 @@ const struct monitor_header_tag monitor_hdr = { * programed into the SPI flash. */ CONFIG_PROGRAM_MEMORY_BASE, - /* 0x0C:The Flash start address to be programmed*/ +/* 0x0C:The Flash start address to be programmed*/ #ifdef SECTION_IS_RO /* Default: RO image is programed from the start of SPI flash */ CONFIG_EC_PROTECTED_STORAGE_OFF, diff --git a/chip/npcx/spiflashfw/npcx_monitor.c b/chip/npcx/spiflashfw/npcx_monitor.c index f22037f8de..5b7a767992 100644 --- a/chip/npcx/spiflashfw/npcx_monitor.c +++ b/chip/npcx/spiflashfw/npcx_monitor.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -49,7 +49,7 @@ void sspi_flash_execute_cmd(uint8_t code, uint8_t cts) /* set UMA_CODE */ NPCX_UMA_CODE = code; /* execute UMA flash transaction */ - NPCX_UMA_CTS = cts; + NPCX_UMA_CTS = cts; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } @@ -76,7 +76,7 @@ void sspi_flash_wait_ready(void) sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY); do { /* Read status register */ - NPCX_UMA_CTS = MASK_RD_1BYTE; + NPCX_UMA_CTS = MASK_RD_1BYTE; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */ @@ -108,7 +108,7 @@ void sspi_flash_set_address(uint32_t dest_addr) } void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes, - const char *data) + const char *data) { unsigned int i; /* Chip Select down. */ @@ -197,7 +197,7 @@ void sspi_flash_physical_erase(int offset, int size) /* Alignment has been checked in upper layer */ for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE, - offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { + offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { /* Enable write */ sspi_flash_write_enable(); /* Set erase address */ @@ -221,7 +221,7 @@ int sspi_flash_verify(int offset, int size, const char *data) uint8_t cmp_data; ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset); - ptr_mram = (uint8_t *)data; + ptr_mram = (uint8_t *)data; result = 1; /* Disable tri-state */ @@ -255,12 +255,11 @@ int sspi_flash_get_image_used(const char *fw_base) for (size--; size > 0 && image[size] != 0xea; size--) ; - return size ? size + 1 : 0; /* 0xea byte IS part of the image */ - + return size ? size + 1 : 0; /* 0xea byte IS part of the image */ } /* Entry function of spi upload function */ -uint32_t __attribute__ ((section(".startup_text"))) +uint32_t __attribute__((section(".startup_text"))) sspi_flash_upload(int spi_offset, int spi_size) { /* @@ -315,7 +314,7 @@ sspi_flash_upload(int spi_offset, int spi_size) /* Start to write */ if (image_base != NULL) sspi_flash_physical_write(spi_offset, sz_image, - image_base); + image_base); /* Verify data */ if (sspi_flash_verify(spi_offset, sz_image, image_base)) *flag_upload |= 0x02; diff --git a/chip/npcx/spiflashfw/npcx_monitor.h b/chip/npcx/spiflashfw/npcx_monitor.h index f4f30454d2..54303958d6 100644 --- a/chip/npcx/spiflashfw/npcx_monitor.h +++ b/chip/npcx/spiflashfw/npcx_monitor.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,11 +7,11 @@ #include <stdint.h> -#define NPCX_MONITOR_UUT_TAG 0xA5075001 -#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 +#define NPCX_MONITOR_UUT_TAG 0xA5075001 +#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 /* Flag to record the progress of programming SPI flash */ -#define SPI_PROGRAMMING_FLAG 0x200C4000 +#define SPI_PROGRAMMING_FLAG 0x200C4000 struct monitor_header_tag { /* offset 0x00: TAG NPCX_MONITOR_TAG */ @@ -23,9 +23,9 @@ struct monitor_header_tag { /* offset 0x0C: The Flash address to be programmed (Absolute address) */ uint32_t dest_addr; /* offset 0x10: Maximum allowable flash clock frequency */ - uint8_t max_clock; + uint8_t max_clock; /* offset 0x11: SPI Flash read mode */ - uint8_t read_mode; + uint8_t read_mode; /* offset 0x12: Reserved */ uint16_t reserved; } __packed; diff --git a/chip/npcx/spiflashfw/npcx_monitor.ld b/chip/npcx/spiflashfw/npcx_monitor.ld index ae7760c519..434945b04c 100644 --- a/chip/npcx/spiflashfw/npcx_monitor.ld +++ b/chip/npcx/spiflashfw/npcx_monitor.ld @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * |