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Diffstat (limited to 'chip/stm32/dma.c')
-rw-r--r--chip/stm32/dma.c76
1 files changed, 37 insertions, 39 deletions
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c
index ae5a83789d..fbf0d59627 100644
--- a/chip/stm32/dma.c
+++ b/chip/stm32/dma.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
+#include "builtin/assert.h"
#include "clock.h"
#include "common.h"
#include "console.h"
@@ -15,15 +16,14 @@
/* Console output macros */
#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_DMA, format, ##args)
/* Callback data to use when IRQ fires */
static struct {
- void (*cb)(void *); /* Callback function to call */
- void *cb_data; /* Callback data for callback function */
+ void (*cb)(void *); /* Callback function to call */
+ void *cb_data; /* Callback data for callback function */
} dma_irq[STM32_DMAC_COUNT];
-
/**
* Return the IRQ for the DMA channel
*
@@ -36,9 +36,8 @@ static int dma_get_irq(enum dma_channel channel)
if (channel == STM32_DMAC_CH1)
return STM32_IRQ_DMA_CHANNEL_1;
- return channel > STM32_DMAC_CH3 ?
- STM32_IRQ_DMA_CHANNEL_4_7 :
- STM32_IRQ_DMA_CHANNEL_2_3;
+ return channel > STM32_DMAC_CH3 ? STM32_IRQ_DMA_CHANNEL_4_7 :
+ STM32_IRQ_DMA_CHANNEL_2_3;
#elif defined(CHIP_FAMILY_STM32L4)
if (channel < STM32_DMAC_PER_CTLR)
return STM32_IRQ_DMA_CHANNEL_1 + channel;
@@ -55,7 +54,7 @@ static int dma_get_irq(enum dma_channel channel)
return STM32_IRQ_DMA_CHANNEL_1 + channel;
else
return STM32_IRQ_DMA2_CHANNEL1 +
- (channel - STM32_DMAC_PER_CTLR);
+ (channel - STM32_DMAC_PER_CTLR);
#endif
}
@@ -127,7 +126,7 @@ void dma_disable_all(void)
* 0 for rx
*/
static void prepare_channel(enum dma_channel channel, unsigned int count,
- void *periph, void *memory, unsigned int flags)
+ void *periph, void *memory, unsigned int flags)
{
stm32_dma_chan_t *chan = dma_get_channel(channel);
uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
@@ -161,8 +160,7 @@ void dma_prepare_tx(const struct dma_option *option, unsigned int count,
* we're preparing the channel for transmit.
*/
prepare_channel(option->channel, count, option->periph, (void *)memory,
- STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR |
- option->flags);
+ STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR | option->flags);
}
void dma_start_rx(const struct dma_option *option, unsigned int count,
@@ -191,10 +189,9 @@ void dma_dump(enum dma_channel channel)
stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
stm32_dma_chan_t *chan = dma_get_channel(channel);
- CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr,
- chan->cndtr, chan->cpar, chan->cmar);
- CPRINTF("chan %d, isr=%x, ifcr=%x\n",
- channel,
+ CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr, chan->cndtr,
+ chan->cpar, chan->cmar);
+ CPRINTF("chan %d, isr=%x, ifcr=%x\n", channel,
(dma->isr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf,
(dma->ifcr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf);
}
@@ -238,11 +235,12 @@ void dma_test(enum dma_channel channel)
ctrl = STM32_DMA_CCR_PL_MEDIUM;
chan->ccr = ctrl;
- ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */;
+ ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */
+ ;
ctrl |= STM32_DMA_CCR_MEM2MEM;
ctrl |= STM32_DMA_CCR_PINC;
-/* ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */
-/* ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */
+ /* ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */
+ /* ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */
chan->ccr = ctrl;
chan->ccr = ctrl | STM32_DMA_CCR_EN;
@@ -254,11 +252,13 @@ void dma_test(enum dma_channel channel)
void dma_init(void)
{
-#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
- STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN;
-#elif defined(CHIP_FAMILY_STM32G4)
- STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN |
- STM32_RCC_AHB1ENR_DMAMUXEN;
+#if defined(CHIP_FAMILY_STM32L4)
+ STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN |
+ STM32_RCC_AHB1ENR_DMA2EN;
+#elif defined(CHIP_FAMILY_STM32G4) || defined(CHIP_FAMILY_STM32L5)
+ STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN |
+ STM32_RCC_AHB1ENR_DMA2EN |
+ STM32_RCC_AHB1ENR_DMAMUXEN;
#else
STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
#endif
@@ -337,8 +337,8 @@ static void dma_event_interrupt_channel_1(void)
if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) {
dma_clear_isr(STM32_DMAC_CH1);
if (dma_irq[STM32_DMAC_CH1].cb != NULL)
- (*dma_irq[STM32_DMAC_CH1].cb)
- (dma_irq[STM32_DMAC_CH1].cb_data);
+ (*dma_irq[STM32_DMAC_CH1].cb)(
+ dma_irq[STM32_DMAC_CH1].cb_data);
}
}
DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 1);
@@ -360,9 +360,7 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 1);
static void dma_event_interrupt_channel_4_7(void)
{
int i;
- const unsigned int max_chan = MIN(STM32_DMAC_CH7, STM32_DMAC_COUNT);
-
- for (i = STM32_DMAC_CH4; i <= max_chan; i++) {
+ for (i = STM32_DMAC_CH4; i < STM32_DMAC_COUNT; i++) {
if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) {
dma_clear_isr(i);
if (dma_irq[i].cb != NULL)
@@ -374,15 +372,15 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1);
#else /* !CHIP_FAMILY_STM32F0 */
-#define DECLARE_DMA_IRQ(x) \
- static void CONCAT2(dma_event_interrupt_channel_, x)(void) \
- { \
- dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \
- if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \
- (*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb) \
- (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \
- } \
- DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \
+#define DECLARE_DMA_IRQ(x) \
+ static void CONCAT2(dma_event_interrupt_channel_, x)(void) \
+ { \
+ dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \
+ if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \
+ (*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb)( \
+ dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \
+ } \
+ DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \
CONCAT2(dma_event_interrupt_channel_, x), 1)
DECLARE_DMA_IRQ(1);
@@ -396,7 +394,7 @@ DECLARE_DMA_IRQ(7);
DECLARE_DMA_IRQ(9);
DECLARE_DMA_IRQ(10);
#endif
-#ifdef CHIP_FAMILY_STM32L4
+#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
DECLARE_DMA_IRQ(9);
DECLARE_DMA_IRQ(10);
DECLARE_DMA_IRQ(11);
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