diff options
Diffstat (limited to 'chip/stm32/hwtimer.c')
| -rw-r--r-- | chip/stm32/hwtimer.c | 116 |
1 files changed, 60 insertions, 56 deletions
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index 8748b7f870..3521347f3f 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -1,10 +1,11 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Hardware timers driver */ +#include "builtin/assert.h" #include "clock.h" #include "clock-f.h" #include "common.h" @@ -33,20 +34,20 @@ * -------------------- * ts = 0 1 2 3 */ -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_17 3 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_1 0 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_1 0 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_15 2 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_15_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_15_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_17 3 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_1 0 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_1 0 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_15 2 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_15_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_15_PRIMARY_3 1 #define STM32_TIM_TS_SECONDARY_15_PRIMARY_16 2 #define STM32_TIM_TS_SECONDARY_15_PRIMARY_17 3 #elif defined(CHIP_FAMILY_STM32F3) @@ -61,28 +62,28 @@ * --------------------- * ts = 0 1 2 3 */ -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_19 0 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_19 0 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_5 2 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_19 0 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_15 3 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_3 1 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_4 2 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_15 3 -#define STM32_TIM_TS_SECONDARY_12_PRIMARY_4 0 -#define STM32_TIM_TS_SECONDARY_12_PRIMARY_5 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_19 0 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_19 0 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_5 2 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_19 0 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_15 3 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_4 2 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_15 3 +#define STM32_TIM_TS_SECONDARY_12_PRIMARY_4 0 +#define STM32_TIM_TS_SECONDARY_12_PRIMARY_5 1 #define STM32_TIM_TS_SECONDARY_12_PRIMARY_13 2 #define STM32_TIM_TS_SECONDARY_12_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_19_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_19_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_19_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_19_PRIMARY_3 1 #define STM32_TIM_TS_SECONDARY_19_PRIMARY_15 2 #define STM32_TIM_TS_SECONDARY_19_PRIMARY_16 3 #else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */ @@ -97,23 +98,23 @@ * ts = 0 1 2 3 */ #define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_4 3 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_9 0 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_4 3 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_9 0 #define STM32_TIM_TS_SECONDARY_2_PRIMARY_10 1 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_4 3 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_9 0 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_4 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_9 0 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 #define STM32_TIM_TS_SECONDARY_3_PRIMARY_11 2 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_4 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_4 3 #define STM32_TIM_TS_SECONDARY_4_PRIMARY_10 0 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_9 3 -#define STM32_TIM_TS_SECONDARY_9_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_9_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_9 3 +#define STM32_TIM_TS_SECONDARY_9_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_9_PRIMARY_3 1 #define STM32_TIM_TS_SECONDARY_9_PRIMARY_10 2 #define STM32_TIM_TS_SECONDARY_9_PRIMARY_11 3 #endif /* !CHIP_FAMILY_STM32F0 */ @@ -126,7 +127,7 @@ */ #define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB) #define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB) -#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) +#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) /* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */ #if defined TIM_WATCHDOG && (TIM_WATCHDOG == 1) @@ -360,8 +361,8 @@ int __hw_clock_source_init(uint32_t start_t) STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000; STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020; - STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 | - (TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4); + STM32_TIM_SMCR(TIM_CLOCK_MSB) = + 0x0007 | (TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4); STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000; /* Auto-reload value : 16-bit free-running counters */ @@ -419,9 +420,12 @@ void IRQ_HANDLER(IRQ_WD)(void) "pop {r0,pc}\n"); } const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) - = {IRQ_WD, 0}; /* put the watchdog at the highest - priority */ + __attribute__((section(".rodata.irqprio"))) = { + IRQ_WD, 0 + }; /* put the watchdog + at the highest + priority + */ void hwtimer_setup_watchdog(void) { @@ -474,4 +478,4 @@ void hwtimer_reset_watchdog(void) timer->cnt = timer->arr; } -#endif /* defined(CONFIG_WATCHDOG_HELP) */ +#endif /* defined(CONFIG_WATCHDOG_HELP) */ |