diff options
Diffstat (limited to 'chip')
52 files changed, 441 insertions, 135 deletions
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c index ab3749477f..e2106abf0a 100644 --- a/chip/ish/aontaskfw/ish_aontask.c +++ b/chip/ish/aontaskfw/ish_aontask.c @@ -788,7 +788,7 @@ static void handle_reset(enum ish_pm_state pm_state) * ISH ipc host driver will set DMA_ENABLED_MASK bit when it * is loaded and starts, and clear this bit when it is removed. * - * see: https://github.com/torvalds/linux/blob/master/drivers/ + * see: https://github.com/torvalds/linux/blob/HEAD/drivers/ * hid/intel-ish-hid/ipc/ipc.c * * we have two kinds of reset situations need to handle here: diff --git a/chip/ish/build.mk b/chip/ish/build.mk index 9f220abd21..8072a20791 100644 --- a/chip/ish/build.mk +++ b/chip/ish/build.mk @@ -20,8 +20,8 @@ endif chip-y+=clock.o gpio.o system.o hwtimer.o uart.o flash.o ish_persistent_data.o chip-$(CONFIG_I2C)+=i2c.o chip-$(CONFIG_WATCHDOG)+=watchdog.o -chip-$(CONFIG_HOSTCMD_HECI)+=host_command_heci.o -chip-$(CONFIG_HOSTCMD_HECI)+=heci.o system_state_subsys.o ipc_heci.o +chip-$(CONFIG_HOST_INTERFACE_HECI)+=host_command_heci.o +chip-$(CONFIG_HOST_INTERFACE_HECI)+=heci.o system_state_subsys.o ipc_heci.o chip-$(CONFIG_HID_HECI)+=hid_subsys.o chip-$(CONFIG_HID_HECI)+=heci.o system_state_subsys.o ipc_heci.o chip-$(CONFIG_DMA_PAGING)+=dma.o diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h index b573ef7710..5bfc7b9a6b 100644 --- a/chip/ish/uart_defs.h +++ b/chip/ish/uart_defs.h @@ -10,6 +10,7 @@ #include <stdint.h> #include <stddef.h> +#include "atomic.h" #define UART_ERROR -1 #define UART_BUSY -2 @@ -354,7 +355,7 @@ struct uart_ctx { uint32_t id; uint32_t base; uint32_t addr_interval; - uint32_t uart_state; + atomic_t uart_state; uint32_t is_open; uint32_t baud_rate; uint32_t input_freq; diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk index bbff9f009b..cffd7c68f8 100644 --- a/chip/it83xx/build.mk +++ b/chip/it83xx/build.mk @@ -29,7 +29,7 @@ chip-$(CONFIG_PWM)+=pwm.o chip-$(CONFIG_ADC)+=adc.o chip-$(CONFIG_DAC)+=dac.o chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o -chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o +chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o chip-$(CONFIG_SPI_CONTROLLER)+=spi_master.o chip-$(CONFIG_SPI)+=spi.o chip-$(CONFIG_PECI)+=peci.o diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index 41f800721a..c1e9df4265 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -232,7 +232,7 @@ static void clock_set_pll(enum pll_freq_idx idx) ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 1, 5, 1, 0); task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI /* * Workaround for (b:70537592): * We have to set chip select pin as input mode in order to @@ -249,7 +249,7 @@ static void clock_set_pll(enum pll_freq_idx idx) #endif /* Update PLL settings. */ clock_pll_changed(); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI #ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED /* Enable eSPI pad after changing PLL sequence. */ espi_enable_pad(1); @@ -301,7 +301,8 @@ void clock_init(void) */ IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40; -#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI) +#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && \ + defined(CONFIG_HOST_INTERFACE_ESPI) /* * Because we don't support eSPI HW reset function (b/111480168) on DX * version, so we have to reset eSPI configurations during init to @@ -539,7 +540,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds) /* EC sleep */ ec_sleep = 1; #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \ -defined(CONFIG_HOSTCMD_ESPI) +defined(CONFIG_HOST_INTERFACE_ESPI) /* Disable eSPI pad. */ espi_enable_pad(0); #endif @@ -565,7 +566,7 @@ void clock_sleep_mode_wakeup_isr(void) /* trigger a reboot if wake up EC from sleep mode (system hibernate) */ if (clock_ec_wake_from_sleep()) { #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \ -defined(CONFIG_HOSTCMD_ESPI) +defined(CONFIG_HOST_INTERFACE_ESPI) /* * Enable eSPI pad. * We will not need to enable eSPI pad here if Dx is able to @@ -636,6 +637,12 @@ void __ram_code __idle(void) while (1) { /* Disable interrupts */ interrupt_disable(); +#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE + if (i2c_idle_not_allowed()) { + interrupt_enable(); + continue; + } +#endif /* Check if the EC can enter deep doze mode or not */ if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) { /* reset low power mode hw timer */ diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c index be02a8f813..5542d455a9 100644 --- a/chip/it83xx/ec2i.c +++ b/chip/it83xx/ec2i.c @@ -20,7 +20,7 @@ static const struct ec2i_t keyboard_settings[] = { /* Set IRQ=01h for logical device */ {HOST_INDEX_IRQNUMX, 0x01}, /* Configure IRQTP for KBC. */ -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI /* * Interrupt request type select (IRQTP) for KBC. * bit 1, 0: IRQ request is buffered and applied to SERIRQ diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c index 5aa8f8a460..836ee7a82f 100644 --- a/chip/it83xx/i2c.c +++ b/chip/it83xx/i2c.c @@ -21,6 +21,48 @@ /* Default maximum time we allow for an I2C transfer */ #define I2C_TIMEOUT_DEFAULT_US (100 * MSEC) +#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE + +#ifdef CHIP_CORE_NDS32 +#error "Remapping DLM base is required on it8320 series" +#endif + +/* It is allowed to configure the size up to 2K bytes. */ +#define I2C_CQ_MODE_MAX_PAYLOAD_SIZE 128 +/* reserved 5 bytes for ID and CMD_x */ +#define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5) +uint8_t i2c_cq_mode_tx_dlm[I2C_ENHANCED_PORT_COUNT] + [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4); +uint8_t i2c_cq_mode_rx_dlm[I2C_ENHANCED_PORT_COUNT] + [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4); + +/* Repeat Start */ +#define I2C_CQ_CMD_L_RS BIT(7) +/* + * R/W (Read/ Write) decides the I2C read or write direction + * 1: read, 0: write + */ +#define I2C_CQ_CMD_L_RW BIT(6) +/* P (STOP) is the I2C STOP condition */ +#define I2C_CQ_CMD_L_P BIT(5) +/* E (End) is this device end flag */ +#define I2C_CQ_CMD_L_E BIT(4) +/* LA (Last ACK) is Last ACK in master receiver */ +#define I2C_CQ_CMD_L_LA BIT(3) +/* bit[2:0] are number of transfer out or receive data which depends on R/W. */ +#define I2C_CQ_CMD_L_NUM_BIT_2_0 GENMASK(2, 0) + +struct i2c_cq_packet { + uint8_t id; + uint8_t cmd_l; + uint8_t cmd_h; + uint8_t wdata[0]; +}; + +/* Preventing CPU going into idle mode during command queue I2C transaction. */ +static uint32_t i2c_idle_disabled; +#endif /* CONFIG_IT83XX_I2C_CMD_QUEUE */ + enum enhanced_i2c_transfer_direct { TX_DIRECT, RX_DIRECT, @@ -98,6 +140,8 @@ enum enhanced_i2c_ctl { E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST), /* Generate stop condition */ E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST), + /* start with command queue mode */ + E_START_CQ = (E_INT_EN | E_MODE_SEL | E_ACK | E_START), }; enum i2c_reset_cause { @@ -587,11 +631,199 @@ static int enhanced_i2c_error(int p) return pd->err; } -static int i2c_transaction(int p) +#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE +static void enhanced_i2c_set_cmd_addr_regs(int p) +{ + int dlm_index = p - I2C_STANDARD_PORT_COUNT; + int p_ch = i2c_ch_reg_shift(p); + uint32_t dlm_base; + + /* set "Address Register" to store the I2C data */ + dlm_base = (uint32_t)&i2c_cq_mode_rx_dlm[dlm_index] & 0xffffff; + IT83XX_I2C_RAMH2A(p_ch) = (dlm_base >> 16) & 0xff; + IT83XX_I2C_RAMHA(p_ch) = (dlm_base >> 8) & 0xff; + IT83XX_I2C_RAMLA(p_ch) = dlm_base & 0xff; + + /* Set "Command Address Register" to get commands */ + dlm_base = (uint32_t)&i2c_cq_mode_tx_dlm[dlm_index] & 0xffffff; + IT83XX_I2C_CMD_ADDH2(p_ch) = (dlm_base >> 16) & 0xff; + IT83XX_I2C_CMD_ADDH(p_ch) = (dlm_base >> 8) & 0xff; + IT83XX_I2C_CMD_ADDL(p_ch) = dlm_base & 0xff; +} + +static void i2c_enable_idle(int port) +{ + i2c_idle_disabled &= ~BIT(port); +} + +static void i2c_disable_idle(int port) +{ + i2c_idle_disabled |= BIT(port); +} + +uint32_t i2c_idle_not_allowed(void) +{ + return i2c_idle_disabled; +} + +static int command_i2c_idle_mask(int argc, char **argv) +{ + ccprintf("i2c idle mask: %08x\n", i2c_idle_disabled); + + return EC_SUCCESS; +} +DECLARE_SAFE_CONSOLE_COMMAND(i2cidlemask, command_i2c_idle_mask, + NULL, "Display i2c idle mask"); + +static void enhanced_i2c_cq_write(int p) +{ + struct i2c_port_data *pd = pdata + p; + struct i2c_cq_packet *i2c_cq_pckt; + uint8_t num_bit_2_0 = (pd->out_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0; + uint8_t num_bit_10_3 = ((pd->out_size - 1) >> 3) & 0xff; + int dlm_index = p - I2C_STANDARD_PORT_COUNT; + + i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index]; + /* Set commands in RAM. */ + i2c_cq_pckt->id = pd->addr_8bit; + i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0; + i2c_cq_pckt->cmd_h = num_bit_10_3; + for (int i = 0; i < pd->out_size; i++) + i2c_cq_pckt->wdata[i] = pd->out[i]; +} + +static void enhanced_i2c_cq_read(int p) +{ + struct i2c_port_data *pd = pdata + p; + struct i2c_cq_packet *i2c_cq_pckt; + uint8_t num_bit_2_0 = (pd->in_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0; + uint8_t num_bit_10_3 = ((pd->in_size - 1) >> 3) & 0xff; + int dlm_index = p - I2C_STANDARD_PORT_COUNT; + + i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index]; + /* Set commands in RAM. */ + i2c_cq_pckt->id = pd->addr_8bit; + i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P | + I2C_CQ_CMD_L_E | num_bit_2_0; + i2c_cq_pckt->cmd_h = num_bit_10_3; +} + +static void enhanced_i2c_cq_write_to_read(int p) +{ + struct i2c_port_data *pd = pdata + p; + struct i2c_cq_packet *i2c_cq_pckt; + uint8_t num_bit_2_0 = (pd->out_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0; + uint8_t num_bit_10_3 = ((pd->out_size - 1) >> 3) & 0xff; + int dlm_index = p - I2C_STANDARD_PORT_COUNT; + int i; + + i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index]; + /* Set commands in RAM. (command byte for write) */ + i2c_cq_pckt->id = pd->addr_8bit; + i2c_cq_pckt->cmd_l = num_bit_2_0; + i2c_cq_pckt->cmd_h = num_bit_10_3; + for (i = 0; i < pd->out_size; i++) + i2c_cq_pckt->wdata[i] = pd->out[i]; + /* Set commands in RAM. (command byte for read) */ + num_bit_2_0 = (pd->in_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0; + num_bit_10_3 = ((pd->in_size - 1) >> 3) & 0xff; + i2c_cq_pckt->wdata[i++] = I2C_CQ_CMD_L_RS | I2C_CQ_CMD_L_RW | + I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0; + i2c_cq_pckt->wdata[i] = num_bit_10_3; +} + +static int enhanced_i2c_cmd_queue_trans(int p) +{ + struct i2c_port_data *pd = pdata + p; + int p_ch = i2c_ch_reg_shift(p); + int dlm_index = p - I2C_STANDARD_PORT_COUNT; + + /* ISR of command queue mode */ + if (in_interrupt_context()) { + /* device 1 finish IRQ */ + if (IT83XX_I2C_FST(p_ch) & IT83XX_I2C_FST_DEV1_IRQ) { + /* get data if this is a read transaction */ + for (int i = 0; i < pd->in_size; i++) + pd->in[i] = i2c_cq_mode_rx_dlm[dlm_index][i]; + } else { + /* device 1 error have occurred. eg. nack, timeout... */ + if (IT83XX_I2C_NST(p_ch) & IT83XX_I2C_NST_ID_NACK) + pd->err = E_HOSTA_ACK; + else + pd->err = IT83XX_I2C_STR(p_ch) & + E_HOSTA_ANY_ERROR; + } + /* reset bus */ + IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; + IT83XX_I2C_CTR1(p_ch) = 0; + + return 0; + } + + if ((pd->out_size > I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE) || + (pd->in_size > I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) { + pd->err = EC_ERROR_INVAL; + return 0; + } + + /* State reset and hardware reset */ + IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; + /* Set "PSR" registers to decide the i2c speed. */ + IT83XX_I2C_PSR(p_ch) = pdata[p].freq; + IT83XX_I2C_HSPR(p_ch) = pdata[p].freq; + /* Set time out register. port D, E, or F clock/data low timeout. */ + IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT; + + /* i2c write to read */ + if (pd->out_size && pd->in_size) + enhanced_i2c_cq_write_to_read(p); + /* i2c write */ + else if (pd->out_size) + enhanced_i2c_cq_write(p); + /* i2c read */ + else if (pd->in_size) + enhanced_i2c_cq_read(p); + + /* enable i2c module with command queue mode */ + IT83XX_I2C_CTR1(p_ch) = IT83XX_I2C_MDL_EN | IT83XX_I2C_COMQ_EN; + /* one shot on device 1 */ + IT83XX_I2C_MODE_SEL(p_ch) = 0; + IT83XX_I2C_CTR2(p_ch) = 1; + /* start */ + i2c_disable_idle(p); + IT83XX_I2C_CTR(p_ch) = E_START_CQ; + + return 0; +} +#endif /* CONFIG_IT83XX_I2C_CMD_QUEUE */ + +static int enhanced_i2c_pio_trans(int p) { struct i2c_port_data *pd = pdata + p; int p_ch; + /* no error */ + if (!(enhanced_i2c_error(p))) { + /* i2c write */ + if (pd->out_size) + return enhanced_i2c_tran_write(p); + /* i2c read */ + else if (pd->in_size) + return enhanced_i2c_tran_read(p); + } + + p_ch = i2c_ch_reg_shift(p); + IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; + IT83XX_I2C_CTR1(p_ch) = 0; + + return 0; +} + +static int i2c_transaction(int p) +{ + struct i2c_port_data *pd = pdata + p; + int ret; + if (p < I2C_STANDARD_PORT_COUNT) { /* any error */ if (IT83XX_SMB_HOSTA(p) & HOSTA_ANY_ERROR) { @@ -612,18 +844,13 @@ static int i2c_transaction(int p) /* disable the SMBus host interface */ IT83XX_SMB_HOCTL2(p) = 0x00; } else { - /* no error */ - if (!(enhanced_i2c_error(p))) { - /* i2c write */ - if (pd->out_size) - return enhanced_i2c_tran_write(p); - /* i2c read */ - else if (pd->in_size) - return enhanced_i2c_tran_read(p); - } - p_ch = i2c_ch_reg_shift(p); - IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; - IT83XX_I2C_CTR1(p_ch) = 0; +#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE + if (pd->flags == I2C_XFER_SINGLE) + ret = enhanced_i2c_cmd_queue_trans(p); + else +#endif + ret = enhanced_i2c_pio_trans(p); + return ret; } /* done doing work */ return 0; @@ -713,6 +940,10 @@ int chip_i2c_xfer(int port, uint16_t addr_flags, if (pd->err) pd->i2ccs = I2C_CH_NORMAL; +#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE + i2c_enable_idle(port); +#endif + return pd->err; } @@ -933,6 +1164,10 @@ void i2c_init(void) IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; /* bit1, Module enable */ IT83XX_I2C_CTR1(p_ch) = 0; +#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE + /* set command address registers */ + enhanced_i2c_set_cmd_addr_regs(p); +#endif } pdata[i].task_waiting = TASK_ID_INVALID; } diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c index 5e6fd734c4..45fff30c1e 100644 --- a/chip/it83xx/intc.c +++ b/chip/it83xx/intc.c @@ -84,7 +84,7 @@ static void intc_cpu_int_group_12(void) peci_interrupt(); break; #endif -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI case IT83XX_IRQ_ESPI: espi_interrupt(); break; diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h index 62ceb34576..50d31999f9 100644 --- a/chip/it83xx/intc.h +++ b/chip/it83xx/intc.h @@ -50,5 +50,8 @@ void spi_peripheral_int_handler(void); void lpc_kbc_ibf_interrupt(void); void lpc_kbc_obe_interrupt(void); #endif +#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE +uint32_t i2c_idle_not_allowed(void); +#endif #endif /* __CROS_EC_INTC_H */ diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c index 867d9e024f..8a90bd426d 100644 --- a/chip/it83xx/lpc.c +++ b/chip/it83xx/lpc.c @@ -136,7 +136,7 @@ static void keyboard_irq_assert(void) */ static void lpc_generate_smi(void) { -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI espi_vw_set_wire(VW_SMI_L, 0); udelay(65); espi_vw_set_wire(VW_SMI_L, 1); @@ -149,7 +149,7 @@ static void lpc_generate_smi(void) static void lpc_generate_sci(void) { -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI espi_vw_set_wire(VW_SCI_L, 0); udelay(65); espi_vw_set_wire(VW_SCI_L, 1); @@ -377,7 +377,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask) pm_set_status(LPC_ACPI_CMD, mask, 0); } -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI int lpc_get_pltrst_asserted(void) { return !gpio_get_level(GPIO_PCH_PLTRST_L); @@ -688,7 +688,7 @@ static void lpc_init(void) */ IT83XX_GCTRL_SPCTRL1 |= 0xC2; -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI gpio_enable_interrupt(GPIO_PCH_PLTRST_L); #endif @@ -711,7 +711,7 @@ static void lpc_init(void) task_clear_pending_irq(IT83XX_IRQ_PMC3_IN); task_enable_irq(IT83XX_IRQ_PMC3_IN); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI espi_init(); #endif /* Sufficiently initialized */ @@ -726,7 +726,7 @@ static void lpc_init(void) */ DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC); -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI void lpcrst_interrupt(enum gpio_signal signal) { if (lpc_get_pltrst_asserted()) diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 34a2ddd6ae..b752f012d8 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1456,7 +1456,7 @@ enum bram_indices { BRAM_IDX_EC_LOG_STATUS = 0xc, /* offset 0x0d ~ 0x1f are reserved for future use. */ -#if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI) +#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI) /* * offset 0x20 ~ 0x7b are reserved for future use. * (apply to x86 platform) @@ -1508,7 +1508,7 @@ enum bram_ec_logs_status { * And they will be used to save panic data if the GPG1 reset mechanism * is enabled. */ -#if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI) +#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI) /* offset 0x80 ~ 0xbf */ #define IT83XX_BRAM_BANK1(i) REG8(IT83XX_BRAM_BASE + 0x80 + i) #else @@ -1552,7 +1552,20 @@ enum bram_ec_logs_status { #define IT83XX_I2C_IDR(ch) REG8(IT83XX_I2C_BASE+0x06+(ch << 7)) #define IT83XX_I2C_TOS(ch) REG8(IT83XX_I2C_BASE+0x07+(ch << 7)) #define IT83XX_I2C_CLK_STR (1 << 7) +#define IT83XX_I2C_STR2(ch) REG8(IT83XX_I2C_BASE+0x12+(ch << 7)) +#define IT83XX_I2C_NST(ch) REG8(IT83XX_I2C_BASE+0x13+(ch << 7)) +#define IT83XX_I2C_NST_CNS BIT(7) +#define IT83XX_I2C_NST_ID_NACK BIT(3) +#define IT83XX_I2C_TO_ARB_ST(ch) REG8(IT83XX_I2C_BASE+0x18+(ch << 7)) +#define IT83XX_I2C_ERR_ST(ch) REG8(IT83XX_I2C_BASE+0x19+(ch << 7)) +#define IT83XX_I2C_ERR_ST_DEV1_EIRQ BIT(0) +#define IT83XX_I2C_FST(ch) REG8(IT83XX_I2C_BASE+0x1b+(ch << 7)) +#define IT83XX_I2C_FST_DEV1_IRQ BIT(4) +#define IT83XX_I2C_EM(ch) REG8(IT83XX_I2C_BASE+0x1c+(ch << 7)) +#define IT83XX_I2C_EM_DEV1_IRQ BIT(4) +#define IT83XX_I2C_MODE_SEL(ch) REG8(IT83XX_I2C_BASE+0x1d+(ch << 7)) #define IT83XX_I2C_IDR2(ch) REG8(IT83XX_I2C_BASE+0x1F+(ch << 7)) +#define IT83XX_I2C_CTR2(ch) REG8(IT83XX_I2C_BASE+0x20+(ch << 7)) #define IT83XX_I2C_RAMHA(ch) REG8(IT83XX_I2C_BASE+0x23+(ch << 7)) #define IT83XX_I2C_RAMLA(ch) REG8(IT83XX_I2C_BASE+0x24+(ch << 7)) #define IT83XX_I2C_RAMHA2(ch) REG8(IT83XX_I2C_BASE+0x2B+(ch << 7)) diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c index 16871e5826..ae7fd627bf 100644 --- a/chip/it83xx/system.c +++ b/chip/it83xx/system.c @@ -50,7 +50,7 @@ static void clear_reset_flags(void) } DECLARE_HOOK(HOOK_INIT, clear_reset_flags, HOOK_PRIO_LAST); -#if !defined(CONFIG_HOSTCMD_LPC) && !defined(CONFIG_HOSTCMD_ESPI) +#if !defined(CONFIG_HOST_INTERFACE_LPC) && !defined(CONFIG_HOST_INTERFACE_ESPI) static void system_save_panic_data_to_bram(void) { uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR; diff --git a/chip/lm4/build.mk b/chip/lm4/build.mk index 26419d3a04..c1d7787bf3 100644 --- a/chip/lm4/build.mk +++ b/chip/lm4/build.mk @@ -20,7 +20,7 @@ chip-$(CONFIG_EEPROM)+=eeprom.o chip-$(CONFIG_FANS)+=fan.o chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o chip-$(CONFIG_I2C)+=i2c.o -chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o +chip-$(CONFIG_HOST_INTERFACE_LPC)+=lpc.o chip-$(CONFIG_PECI)+=peci.o # pwm functions are implemented with the fan functions chip-$(CONFIG_PWM)+=pwm.o fan.o diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h index 4e442004c9..8e1ea51785 100644 --- a/chip/lm4/config_chip.h +++ b/chip/lm4/config_chip.h @@ -93,7 +93,7 @@ /* Optional features present on this chip */ #define CONFIG_ADC #define CONFIG_HOSTCMD_ALIGNED -#define CONFIG_HOSTCMD_LPC +#define CONFIG_HOST_INTERFACE_LPC #define CONFIG_PECI #define CONFIG_RTC #define CONFIG_SWITCH diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h index 0c59da19f6..1065cd7f5e 100644 --- a/chip/lm4/registers.h +++ b/chip/lm4/registers.h @@ -8,6 +8,7 @@ #ifndef __CROS_EC_REGISTERS_H #define __CROS_EC_REGISTERS_H +#include "atomic.h" #include "common.h" #define LM4_UART_CH0_BASE 0x4000c000 @@ -265,7 +266,7 @@ static inline int lm4_fan_addr(int ch, int offset) #define LM4_SYSTEM_SRI2C REG32(0x400fe520) #define LM4_SYSTEM_SREEPROM REG32(0x400fe558) -#define LM4_SYSTEM_SRI2C_ADDR ((uint32_t *)0x400fe520) +#define LM4_SYSTEM_SRI2C_ADDR ((atomic_t *)0x400fe520) #define LM4_SYSTEM_RCGC_BASE ((volatile uint32_t *)0x400fe600) #define LM4_SYSTEM_RCGCGPIO REG32(0x400fe608) diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c index 0b923f0692..83136d0b46 100644 --- a/chip/lm4/uart.c +++ b/chip/lm4/uart.c @@ -123,7 +123,7 @@ static void uart_host_interrupt(void) /* Clear transmit and receive interrupt status */ LM4_UART_ICR(CONFIG_UART_HOST) = 0x70; -#ifdef CONFIG_HOSTCMD_LPC +#ifdef CONFIG_HOST_INTERFACE_LPC /* * If we have space in our FIFO and a character is pending in LPC, * handle that character. diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk index 155fbf385f..226fe23363 100644 --- a/chip/mchp/build.mk +++ b/chip/mchp/build.mk @@ -32,7 +32,7 @@ endif chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o tfdp.o chip-$(CONFIG_ADC)+=adc.o chip-$(CONFIG_DMA)+=dma.o -chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o +chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o chip-$(CONFIG_FANS)+=fan.o chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o chip-$(CONFIG_I2C)+=i2c.o diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c index 362025ee1c..e646470ac6 100644 --- a/chip/mchp/clock.c +++ b/chip/mchp/clock.c @@ -395,7 +395,7 @@ static void prepare_for_deep_sleep(void) #endif -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI; MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI; #else @@ -475,7 +475,7 @@ static void resume_from_deep_sleep(void) */ MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI #ifdef CONFIG_POWER_S0IX MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI; MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI; @@ -763,7 +763,7 @@ static int command_dsleep(int argc, char **argv) } } - ccprintf("Sleep mask: %08x\n", sleep_mask); + ccprintf("Sleep mask: %08x\n", (int)sleep_mask); ccprintf("Console in use timeout: %d sec\n", console_in_use_timeout_sec); diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c index a7db914f3b..778990b852 100644 --- a/chip/mchp/espi.c +++ b/chip/mchp/espi.c @@ -1386,7 +1386,7 @@ void espi_init(void) (CONFIG_HOSTCMD_ESPI_EC_MODE << MCHP_ESPI_CAP1_IO_BITPOS); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW; #else MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_PIN; diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c index 9f6a731eb5..9e64281276 100644 --- a/chip/mchp/lpc.c +++ b/chip/mchp/lpc.c @@ -88,7 +88,7 @@ static void keyboard_irq_assert(void) static void lpc_generate_smi(void) { CPUTS("LPC Pulse SMI"); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI /* eSPI: pulse SMI# Virtual Wire low */ espi_vw_pulse_wire(VW_SMI_L, 0); #else @@ -106,7 +106,7 @@ static void lpc_generate_sci(void) udelay(65); gpio_set_level(CONFIG_SCI_GPIO, 1); #else -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI espi_vw_pulse_wire(VW_SCI_L, 0); #else MCHP_ACPI_PM_STS |= 1; @@ -129,7 +129,7 @@ static void lpc_update_wake(host_event_t wake_events) */ wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI espi_vw_set_wire(VW_WAKE_L, !wake_events); #else /* Signal is asserted low when wake events is non-zero */ @@ -304,7 +304,7 @@ const int acpi_ec_nvic_ibf[] = { }; BUILD_ASSERT(ARRAY_SIZE(acpi_ec_nvic_ibf) == MCHP_ACPI_EC_INSTANCES); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI const int acpi_ec_espi_bar_id[] = { MCHP_ESPI_IO_BAR_ID_ACPI_EC0, MCHP_ESPI_IO_BAR_ID_ACPI_EC1, @@ -326,7 +326,7 @@ void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask) MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) = mask; MCHP_ESPI_IO_BAR(acpi_ec_espi_bar_id[instance]) = @@ -350,7 +350,7 @@ void chip_8042_config(uint32_t io_base) { MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_8042); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_8042) = 0x04; MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) = (io_base << 16) + 0x01ul; @@ -372,7 +372,7 @@ void chip_8042_config(uint32_t io_base) #ifndef CONFIG_KEYBOARD_IRQ_GPIO /* Set up SERIRQ for keyboard */ MCHP_8042_KB_CTRL |= BIT(5); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI /* Delivery 8042 keyboard interrupt as IRQ1 using eSPI SERIRQ */ MCHP_ESPI_IO_SERIRQ_REG(MCHP_ESPI_SIRQ_8042_KB) = 1; #else @@ -392,7 +392,7 @@ void chip_8042_config(uint32_t io_base) */ void chip_emi0_config(uint32_t io_base) { -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_EMI0) = 0x0F; MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) = (io_base << 16) + 0x01ul; @@ -442,7 +442,7 @@ void chip_port80_config(uint32_t io_base) MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO + MCHP_P80_RESET_TIMESTAMP_WO; -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_P80_0) = 0x00; MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) = (io_base << 16) + 0x01ul; @@ -484,7 +484,7 @@ static void chip_lpc_iobar_debug(void) * For eSPI PLATFORM_RESET# virtual wire is used as LRESET# * */ -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI static void setup_lpc(void) { MCHP_LPC_CFG_BAR |= (1ul << 15); @@ -545,7 +545,7 @@ static void lpc_init(void) MCHP_PCR_SLP_EN2_ACPI_EC0 + MCHP_PCR_SLP_EN2_MIF8042); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI espi_init(); @@ -621,7 +621,7 @@ void lpc_set_init_done(int val) */ void lpcrst_interrupt(enum gpio_signal signal) { -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI /* Initialize LPC module when LRESET# is de-asserted */ if (!lpc_get_pltrst_asserted()) { setup_lpc(); @@ -941,10 +941,10 @@ void lpc_clear_acpi_status_mask(uint8_t mask) */ int lpc_get_pltrst_asserted(void) { -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI /* * eSPI PLTRST# a VWire or side-band signal - * Controlled by CONFIG_HOSTCMD_ESPI + * Controlled by CONFIG_HOST_INTERFACE_ESPI */ return !espi_vw_get_wire(VW_PLTRST_L); #else diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h index dcb5577fc1..434b307968 100644 --- a/chip/mchp/lpc_chip.h +++ b/chip/mchp/lpc_chip.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_LPC_CHIP_H #define __CROS_EC_LPC_CHIP_H -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI #include "espi.h" @@ -37,7 +37,7 @@ void lpc_set_init_done(int val); void lpc_mem_mapped_init(void); -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI void lpcrst_interrupt(enum gpio_signal signal); #endif diff --git a/chip/mchp/system.c b/chip/mchp/system.c index 5591c818c4..72c96bef8f 100644 --- a/chip/mchp/system.c +++ b/chip/mchp/system.c @@ -178,7 +178,7 @@ void system_pre_init(void) MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */ /* Manual voltage selection only required for MEC170x and MEC152x */ - if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) + if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) vtr3_voltage_select(1); else vtr3_voltage_select(0); @@ -427,7 +427,7 @@ int system_get_scratchpad(uint32_t *value) * defined for MEC170x and the IS_ENABLED() macro causes the * compiler to evaluate both true and false code paths. */ -#if defined(CONFIG_HOSTCMD_ESPI) +#if defined(CONFIG_HOST_INTERFACE_ESPI) static void disable_host_ifc_clocks(void) { MCHP_ESPI_ACTIVATE &= ~0x01; diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk index 2b0c9cc229..dd0ef8cd90 100644 --- a/chip/mec1322/build.mk +++ b/chip/mec1322/build.mk @@ -22,7 +22,7 @@ chip-$(CONFIG_ADC)+=adc.o chip-$(CONFIG_FANS)+=fan.o chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o chip-$(CONFIG_I2C)+=i2c.o -chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o +chip-$(CONFIG_HOST_INTERFACE_LPC)+=lpc.o chip-$(CONFIG_PWM)+=pwm.o chip-$(CONFIG_WATCHDOG)+=watchdog.o ifndef CONFIG_KEYBOARD_NOT_RAW diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h index 414fb492bf..951de3fb4f 100644 --- a/chip/mec1322/config_chip.h +++ b/chip/mec1322/config_chip.h @@ -103,7 +103,7 @@ #define CONFIG_MPU #endif #define CONFIG_DMA -#define CONFIG_HOSTCMD_LPC +#define CONFIG_HOST_INTERFACE_LPC #define CONFIG_SPI #define CONFIG_SWITCH diff --git a/chip/mt_scp/mt8195/clock.c b/chip/mt_scp/mt8195/clock.c index 1ad1706e6a..eac6436a46 100644 --- a/chip/mt_scp/mt8195/clock.c +++ b/chip/mt_scp/mt8195/clock.c @@ -378,11 +378,11 @@ power_chipset_handle_host_sleep_event(enum host_sleep_event state, { if (state == HOST_SLEEP_EVENT_S3_SUSPEND) { CPRINTS("AP suspend"); - disable_watchdog(); + watchdog_disable(); clock_select_clock(SCP_CLK_SYSTEM); } else if (state == HOST_SLEEP_EVENT_S3_RESUME) { clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED); - enable_watchdog(); + watchdog_enable(); CPRINTS("AP resume"); } } diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h index 87181c46ca..ba77f069f2 100644 --- a/chip/mt_scp/mt8195/intc.h +++ b/chip/mt_scp/mt8195/intc.h @@ -102,13 +102,13 @@ /* 68 */ #define SCP_IRQ_APU_MBOX 68 #define SCP_IRQ_DEVAPC_SECURE_VIO 69 -#define SCP_IRQ_CAMSYS_29 70 -#define SCP_IRQ_CAMSYS_28 71 +#define SCP_IRQ_APDMA0 70 +#define SCP_IRQ_APDMA1 71 /* 72 */ -#define SCP_IRQ_CAMSYS_5 72 -#define SCP_IRQ_CAMSYS_4 73 -#define SCP_IRQ_CAMSYS_3 74 -#define SCP_IRQ_CAMSYS_2 75 +#define SCP_IRQ_APDMA2 72 +#define SCP_IRQ_APDMA3 73 +#define SCP_IRQ_APDMA4 74 +#define SCP_IRQ_APDMA5 75 /* 76 */ #define SCP_IRQ_HDMIRX_PM_DVI_SQH 76 #define SCP_IRQ_HDMIRX_RESERVED 77 diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c index 7e6b39e1f2..1e4fd1cef4 100644 --- a/chip/mt_scp/rv32i_common/intc.c +++ b/chip/mt_scp/rv32i_common/intc.c @@ -243,13 +243,13 @@ static struct { /* 68 */ [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_29] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_28] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA0] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA1] = { INTC_GRP_0 }, /* 72 */ - [SCP_IRQ_CAMSYS_5] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_4] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_3] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_2] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA2] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA3] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA4] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA5] = { INTC_GRP_0 }, /* 76 */ [SCP_IRQ_HDMIRX_PM_DVI_SQH] = { INTC_GRP_0 }, [SCP_IRQ_HDMIRX_RESERVED] = { INTC_GRP_0 }, @@ -272,9 +272,9 @@ static struct { [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, /* 92 */ [SCP_IRQ_EARC] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, + [SCP_IRQ_CEC] = { INTC_GRP_0 }, + [SCP_IRQ_HDMI_DEV_DET] = { INTC_GRP_0 }, + [SCP_IRQ_HDMIRX_OUT_ARM_PHY] = { INTC_GRP_0 }, /* 96 */ [SCP_IRQ_I2C2] = { INTC_GRP_0 }, [SCP_IRQ_I2C3] = { INTC_GRP_0 }, diff --git a/chip/mt_scp/rv32i_common/ipi.c b/chip/mt_scp/rv32i_common/ipi.c index cba5c65d0b..a7fc720d42 100644 --- a/chip/mt_scp/rv32i_common/ipi.c +++ b/chip/mt_scp/rv32i_common/ipi.c @@ -28,7 +28,7 @@ static struct ipc_shared_obj *const ipi_recv_buf = (struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR + sizeof(struct ipc_shared_obj)); -static uint32_t disable_irq_count, saved_int_mask; +static atomic_t disable_irq_count, saved_int_mask; void ipi_disable_irq(void) { diff --git a/chip/mt_scp/rv32i_common/scp_watchdog.h b/chip/mt_scp/rv32i_common/scp_watchdog.h index 0277aeaec7..87309a2f82 100644 --- a/chip/mt_scp/rv32i_common/scp_watchdog.h +++ b/chip/mt_scp/rv32i_common/scp_watchdog.h @@ -9,7 +9,7 @@ #include "watchdog.h" -void disable_watchdog(void); -void enable_watchdog(void); +void watchdog_disable(void); +void watchdog_enable(void); #endif /* __SCP_WATCHDOG_H */ diff --git a/chip/mt_scp/rv32i_common/watchdog.c b/chip/mt_scp/rv32i_common/watchdog.c index 05acf6ea29..f77a948da3 100644 --- a/chip/mt_scp/rv32i_common/watchdog.c +++ b/chip/mt_scp/rv32i_common/watchdog.c @@ -17,7 +17,7 @@ void watchdog_reload(void) } DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); -void disable_watchdog(void) +void watchdog_disable(void) { /* disable watchdog */ SCP_CORE0_WDT_CFG &= ~WDT_EN; @@ -25,7 +25,7 @@ void disable_watchdog(void) SCP_CORE0_WDT_IRQ |= BIT(0); } -void enable_watchdog(void) +void watchdog_enable(void) { const uint32_t timeout = WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS); @@ -41,7 +41,7 @@ void enable_watchdog(void) int watchdog_init(void) { - enable_watchdog(); + watchdog_enable(); return EC_SUCCESS; } diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index 3a41cfbd53..246ab84f34 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -33,9 +33,9 @@ chip-$(CONFIG_FANS)+=fan.o chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o chip-$(CONFIG_HOSTCMD_X86)+=lpc.o -chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o +chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o chip-$(CONFIG_PECI)+=peci.o -chip-$(CONFIG_HOSTCMD_SHI)+=shi.o +chip-$(CONFIG_HOST_INTERFACE_SHI)+=shi.o chip-$(CONFIG_CEC)+=cec.o # pwm functions are implemented with the fan functions chip-$(CONFIG_PWM)+=pwm.o diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c index e7cd0ae7b9..eb1cfefa0f 100644 --- a/chip/npcx/cec.c +++ b/chip/npcx/cec.c @@ -251,7 +251,7 @@ static int cap_charge; static uint8_t cec_addr = UINT8_MAX; /* Events to send to AP */ -static uint32_t cec_events; +static atomic_t cec_events; /* APB1 frequency. Store divided by 10k to avoid some runtime divisions */ static uint32_t apb1_freq_div_10k; diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index ad611973be..4656e83a52 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -422,7 +422,7 @@ void __idle(void) * CSAE bit is set. Please notice this symptom only * occurs at npcx5. */ -#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI) +#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOST_INTERFACE_ESPI) /* Enable Host access wakeup */ SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); #endif @@ -499,7 +499,7 @@ static int command_dsleep(int argc, char **argv) } } - ccprintf("Sleep mask: %08x\n", sleep_mask); + ccprintf("Sleep mask: %08x\n", (int)sleep_mask); ccprintf("Console in use timeout: %d sec\n", console_in_use_timeout_sec); ccprintf("PMCSR register: 0x%02x\n", NPCX_PMCSR); diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c index c6fcf7351b..9412aa9d9f 100644 --- a/chip/npcx/gpio-npcx5.c +++ b/chip/npcx/gpio-npcx5.c @@ -67,7 +67,7 @@ static void __gpio_wk0efgh_interrupt(void) SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6); return; } - if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) { + if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) { if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5) && IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) { @@ -179,7 +179,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SHI +#ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c index e9e8ad2ad9..31ed4e62ac 100644 --- a/chip/npcx/gpio-npcx9.c +++ b/chip/npcx/gpio-npcx9.c @@ -70,7 +70,7 @@ static void __gpio_host_interrupt(void) SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6); return; } - if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) { + if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) { if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5) && IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) { @@ -195,7 +195,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SHI +#ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index e740f0aa9f..5f1e3c78b6 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -560,7 +560,7 @@ void gpio_pre_init(void) #endif /* Pin_Mux for LPC & SHI */ -#ifdef CONFIG_HOSTCMD_SHI +#ifdef CONFIG_HOST_INTERFACE_SHI /* Switching to eSPI mode for SHI interface */ NPCX_DEVCNT |= 0x08; /* Alternate Intel bus interface LPC/eSPI to GPIOs first */ diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 9bb2de8936..d52b9c968a 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -86,7 +86,7 @@ static void lpc_task_enable_irq(void) #endif task_enable_irq(NPCX_IRQ_PM_CHAN_IBF); task_enable_irq(NPCX_IRQ_PORT80); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI task_enable_irq(NPCX_IRQ_ESPI); /* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */ task_enable_irq(NPCX_IRQ_WKINTA_2); @@ -105,7 +105,7 @@ static void lpc_task_disable_irq(void) #endif task_disable_irq(NPCX_IRQ_PM_CHAN_IBF); task_disable_irq(NPCX_IRQ_PORT80); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI task_disable_irq(NPCX_IRQ_ESPI); /* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */ task_disable_irq(NPCX_IRQ_WKINTA_2); @@ -137,7 +137,7 @@ static void lpc_generate_smi(void) udelay(65); /* Set signal high, now that we've generated the edge */ gpio_set_level(GPIO_PCH_SMI_L, 1); -#elif defined(CONFIG_HOSTCMD_ESPI) +#elif defined(CONFIG_HOST_INTERFACE_ESPI) /* * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead. @@ -183,7 +183,7 @@ static void lpc_generate_sci(void) udelay(65); /* Set signal high, now that we've generated the edge */ gpio_set_level(CONFIG_SCI_GPIO, 1); -#elif defined(CONFIG_HOSTCMD_ESPI) +#elif defined(CONFIG_HOST_INTERFACE_ESPI) /* * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead. @@ -584,7 +584,8 @@ static void lpc_port80_interrupt(void) uint32_t code = 0; /* buffer Port80 data to the local buffer if FIFO is not empty */ - while (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FNE)) + while (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FNE) && + (count < ARRAY_SIZE(port80_buf))) port80_buf[count++] = NPCX_DP80BUF; for (i = 0; i < count; i++) { @@ -698,7 +699,7 @@ void host_register_init(void) * EC hardware will put those 4 bytes of Port80 code to DP80BUF FIFO. * This is only supported when CHIP_FAMILY >= NPCX9. */ - if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) + if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) sib_write_reg(SIO_OFFSET, 0xFD, 0x0F); /* enable SHM */ sib_write_reg(SIO_OFFSET, 0x30, 0x01); @@ -721,7 +722,7 @@ int lpc_get_pltrst_asserted(void) return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT); } -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI /* Initialize host settings by interrupt */ void lpc_lreset_pltrst_handler(void) { @@ -771,7 +772,7 @@ static void lpc_init(void) * In npcx9, the booter will not do this anymore. The HIF_TYP_SEL * field should be set by firmware. */ -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI /* Initialize eSPI module */ NPCX_DEVCNT |= 0x08; espi_init(); @@ -787,7 +788,7 @@ static void lpc_init(void) /* Clear Host Access Hold state */ NPCX_SMC_CTL = 0xC0; -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI /* * Set alternative pin from GPIO to CLKRUN no matter SERIRQ is under * continuous or quiet mode. @@ -800,7 +801,7 @@ static void lpc_init(void) * valid if CONFIG_SCI_GPIO isn't defined. eSPI sends SMI/SCI through VW * automatically by toggling them, too. It's unnecessary to set pin mux. */ -#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOSTCMD_ESPI) +#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOST_INTERFACE_ESPI) SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_EC_SCI_SL); SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_SMI_SL); #endif @@ -876,7 +877,7 @@ static void lpc_init(void) * Init PORT80 * Enable Port80, Enable Port80 function & Interrupt & Read auto */ -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI NPCX_DP80CTL = 0x2b; #else NPCX_DP80CTL = 0x29; @@ -926,7 +927,7 @@ static void lpc_init(void) /* initial IO port address via SIB-write modules */ host_register_init(); #else -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI /* * Initialize LRESET# interrupt only in case of LPC. For eSPI, there is * no dedicated GPIO pin for LRESET/PLTRST. PLTRST is indicated as a VW diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h index c14aec196e..3fd73e8119 100644 --- a/chip/npcx/shi_chip.h +++ b/chip/npcx/shi_chip.h @@ -5,10 +5,9 @@ /* NPCX-specific SHI module for Chrome EC */ -#ifndef SHI_CHIP_H_ -#define SHI_CHIP_H_ +#ifndef __CROS_EC_SHI_CHIP_H_ +#define __CROS_EC_SHI_CHIP_H_ -#ifdef CONFIG_HOSTCMD_SHI /** * Called when the NSS level changes, signalling the start of a SHI * transaction. @@ -19,6 +18,5 @@ void shi_cs_event(enum gpio_signal signal); #ifdef NPCX_SHI_V2 void shi_cs_gpio_int(enum gpio_signal signal); #endif -#endif -#endif /* SHI_CHIP_H_ */ +#endif /* __CROS_EC_SHI_CHIP_H_ */ diff --git a/chip/npcx/sib.c b/chip/npcx/sib.c index b62946fc96..424048518e 100644 --- a/chip/npcx/sib.c +++ b/chip/npcx/sib.c @@ -19,7 +19,7 @@ * For eSPI - it is 200 us. * For LPC - it is 5 us. */ -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI #define HOST_TRANSACTION_TIMEOUT_US 200 #else #define HOST_TRANSACTION_TIMEOUT_US 5 diff --git a/chip/npcx/system.c b/chip/npcx/system.c index ac7056330f..97fcd01c41 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -872,7 +872,7 @@ void system_pre_init(void) BIT(NPCX_PWDWN_CTL6_ITIM6_PD) | #endif BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */ -#if !defined(CONFIG_HOSTCMD_ESPI) +#if !defined(CONFIG_HOST_INTERFACE_ESPI) pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD; #endif NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6; diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c index 0b339399c9..aadbde08c2 100644 --- a/chip/stm32/pwm.c +++ b/chip/stm32/pwm.c @@ -17,7 +17,7 @@ #include "util.h" /* Bitmap of currently active PWM channels. 1 bit per channel. */ -static uint32_t using_pwm; +static atomic_t using_pwm; void pwm_set_duty(enum pwm_channel ch, int percent) { diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index bafca58c46..6be0790c63 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -176,7 +176,14 @@ static void uart_interrupt(void) #if defined(CHIP_FAMILY_STM32F4) STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC; #else - STM32_USART_ICR(UARTN_BASE) |= STM32_USART_SR_TC; + /* + * ST reference code does blind write to this register, as is + * usual with the "write 1 to clear" convention, despite the + * datasheet listing the bits as "keep at reset value", (which + * we assume is due to copying from the description of + * reserved bits in read/write registers.) + */ + STM32_USART_ICR(UARTN_BASE) = STM32_USART_SR_TC; #endif if (!(STM32_USART_SR(UARTN_BASE) & ~STM32_USART_SR_TC)) return; diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c index b4e7c924a8..740d3929bc 100644 --- a/chip/stm32/usart-stm32f0.c +++ b/chip/stm32/usart-stm32f0.c @@ -82,7 +82,14 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); void usart_clear_tc(struct usart_config const *config) { - STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF; + /* + * ST reference code does blind write to this register, as is usual + * with the "write 1 to clear" convention, despite the datasheet + * listing the bits as "keep at reset value", (which we assume is due + * to copying from the description of reserved bits in read/write + * registers.) + */ + STM32_USART_ICR(config->hw->base) = STM32_USART_ICR_TCCF; } /* diff --git a/chip/stm32/usart-stm32f3.c b/chip/stm32/usart-stm32f3.c index 18452cb3fb..887d79d21f 100644 --- a/chip/stm32/usart-stm32f3.c +++ b/chip/stm32/usart-stm32f3.c @@ -56,7 +56,14 @@ static struct usart_hw_ops const usart_variant_hw_ops = { void usart_clear_tc(struct usart_config const *config) { - STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF; + /* + * ST reference code does blind write to this register, as is usual + * with the "write 1 to clear" convention, despite the datasheet + * listing the bits as "keep at reset value", (which we assume is due + * to copying from the description of reserved bits in read/write + * registers.) + */ + STM32_USART_ICR(config->hw->base) = STM32_USART_ICR_TCCF; } /* diff --git a/chip/stm32/usart_info_command.c b/chip/stm32/usart_info_command.c index 2649a97351..7b7dc1362a 100644 --- a/chip/stm32/usart_info_command.c +++ b/chip/stm32/usart_info_command.c @@ -20,13 +20,14 @@ static int command_usart_info(int argc, char **argv) if (config == NULL) continue; - ccprintf( - "USART%d\n" - " dropped %d bytes\n" - " overran %d times\n", - config->hw->index + 1, - atomic_clear((uint32_t *)&(config->state->rx_dropped)), - atomic_clear((uint32_t *)&(config->state->rx_overrun))); + ccprintf("USART%d\n" + " dropped %d bytes\n" + " overran %d times\n", + config->hw->index + 1, + (int)atomic_clear( + (atomic_t *)&(config->state->rx_dropped)), + (int)atomic_clear( + (atomic_t *)&(config->state->rx_overrun))); if (config->rx->info) config->rx->info(config); diff --git a/chip/stm32/usart_rx_dma.c b/chip/stm32/usart_rx_dma.c index a185878261..c75ebdde41 100644 --- a/chip/stm32/usart_rx_dma.c +++ b/chip/stm32/usart_rx_dma.c @@ -81,7 +81,7 @@ static void usart_rx_dma_interrupt_common( /* (new_index == old_index): nothing to add to the queue. */ } - atomic_add((uint32_t *)&(config->state->rx_dropped), new_bytes - added); + atomic_add((atomic_t *)&(config->state->rx_dropped), new_bytes - added); if (dma_config->state->max_bytes < new_bytes) dma_config->state->max_bytes = new_bytes; @@ -115,5 +115,5 @@ void usart_rx_dma_info(struct usart_config const *config) DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx); ccprintf(" DMA RX max_bytes %d\n", - atomic_clear((uint32_t *)&dma_config->state->max_bytes)); + (int)atomic_clear((atomic_t *)&dma_config->state->max_bytes)); } diff --git a/chip/stm32/usart_rx_interrupt-stm32f4.c b/chip/stm32/usart_rx_interrupt-stm32f4.c index 198c6dd180..b796ae1175 100644 --- a/chip/stm32/usart_rx_interrupt-stm32f4.c +++ b/chip/stm32/usart_rx_interrupt-stm32f4.c @@ -33,7 +33,7 @@ static void usart_rx_interrupt_handler(struct usart_config const *config) uint8_t byte = STM32_USART_RDR(base); if (!queue_add_unit(config->producer.queue, &byte)) - atomic_add((uint32_t *)&(config->state->rx_dropped), 1); + atomic_add((atomic_t *)&(config->state->rx_dropped), 1); } } diff --git a/chip/stm32/usart_rx_interrupt-stm32l.c b/chip/stm32/usart_rx_interrupt-stm32l.c index 24ca7a0487..a89d474d05 100644 --- a/chip/stm32/usart_rx_interrupt-stm32l.c +++ b/chip/stm32/usart_rx_interrupt-stm32l.c @@ -30,7 +30,24 @@ static void usart_rx_interrupt_handler(struct usart_config const *config) * we can't disable it. */ if (status & STM32_USART_SR_ORE) { +#ifdef STM32_USART_ICR_ORECF /* + * Newer series (STM32L4xx and STM32L5xx) have an explicit + * "interrupt clear" register. + * + * ST reference code does blind write to this register, as is + * usual with the "write 1 to clear" convention, despite the + * datasheet listing the bits as "keep at reset value", (which + * we assume is due to copying from the description of + * reserved bits in read/write registers.) + */ + STM32_USART_ICR(config->hw->base) = STM32_USART_ICR_ORECF; +#else + /* + * On the older series STM32L1xx, the overrun bit is cleared + * by a read of the status register, followed by a read of the + * data register. + * * In the unlikely event that the overrun error bit was set but * the RXNE bit was not (possibly because a read was done from * RDR without first reading the status register) we do a read @@ -38,15 +55,16 @@ static void usart_rx_interrupt_handler(struct usart_config const *config) */ if (!(status & STM32_USART_SR_RXNE)) (void)STM32_USART_RDR(config->hw->base); +#endif - atomic_add((uint32_t *)&(config->state->rx_overrun), 1); + atomic_add((atomic_t *)&(config->state->rx_overrun), 1); } if (status & STM32_USART_SR_RXNE) { uint8_t byte = STM32_USART_RDR(base); if (!queue_add_unit(config->producer.queue, &byte)) - atomic_add((uint32_t *)&(config->state->rx_dropped), 1); + atomic_add((atomic_t *)&(config->state->rx_dropped), 1); } } diff --git a/chip/stm32/usart_rx_interrupt.c b/chip/stm32/usart_rx_interrupt.c index 3bc30d4aaf..49d4e83894 100644 --- a/chip/stm32/usart_rx_interrupt.c +++ b/chip/stm32/usart_rx_interrupt.c @@ -30,7 +30,7 @@ static void usart_rx_interrupt_handler(struct usart_config const *config) uint8_t byte = STM32_USART_RDR(base); if (!queue_add_unit(config->producer.queue, &byte)) - atomic_add((uint32_t *)&(config->state->rx_dropped), 1); + atomic_add((atomic_t *)&(config->state->rx_dropped), 1); } } diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c index dde84efaea..a1f60e8906 100644 --- a/chip/stm32/usb.c +++ b/chip/stm32/usb.c @@ -578,7 +578,7 @@ void usb_wake(void) } /* Only allow one caller at a time. */ - if (!atomic_clear((int *)&usb_wake_done)) + if (!atomic_clear((atomic_t *)&usb_wake_done)) return; CPRINTF("WAKE\n"); diff --git a/chip/stm32/usb_hid_keyboard.c b/chip/stm32/usb_hid_keyboard.c index ac4a9f5a1f..b4561d591f 100644 --- a/chip/stm32/usb_hid_keyboard.c +++ b/chip/stm32/usb_hid_keyboard.c @@ -397,7 +397,7 @@ static void write_keyboard_report(void) return; } - if (atomic_clear((int *)&hid_ep_data_ready)) { + if (atomic_clear((atomic_t *)&hid_ep_data_ready)) { /* * Endpoint is not busy, and interrupt handler did not just * send the buffer: enable TX. diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h index 591975234d..a1be2c11fb 100644 --- a/chip/stm32/usb_spi.h +++ b/chip/stm32/usb_spi.h @@ -366,11 +366,18 @@ enum usb_spi_request { * If a platform has a small maximum SPI transfer size, it can be optimized * by setting these limits to the maximum transfer size. */ +#ifdef CONFIG_USB_SPI_BUFFER_SIZE +#define USB_SPI_BUFFER_SIZE CONFIG_USB_SPI_BUFFER_SIZE +#else #define USB_SPI_BUFFER_SIZE (USB_SPI_PAYLOAD_SIZE_V2_START + \ (4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE)) +#endif #define USB_SPI_MAX_WRITE_COUNT USB_SPI_BUFFER_SIZE #define USB_SPI_MAX_READ_COUNT USB_SPI_BUFFER_SIZE +/* Protocol uses two-byte length fields. Larger buffer makes no sense. */ +BUILD_ASSERT(USB_SPI_BUFFER_SIZE <= 65536); + struct usb_spi_transfer_ctx { /* Address of transfer buffer. */ uint8_t *buffer; @@ -520,7 +527,7 @@ struct usb_spi_config { .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI, \ .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI, \ - .iInterface = 0, \ + .iInterface = USB_STR_SPI_NAME, \ }; \ const struct usb_endpoint_descriptor \ USB_EP_DESC(INTERFACE, 0) = { \ |