477 files changed, 0 insertions, 140356 deletions

diff --git a/chip/host/adc_chip.h b/chip/host/adc_chip.h
deleted file mode 100644
index 8754be266e..0000000000
--- a/chip/host/adc_chip.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Host-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-/* Place-holder data structure to define ADC channels. */
-struct adc_t {
-	int unused;
-};
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/host/build.mk b/chip/host/build.mk
deleted file mode 100644
index 6f8ea250ca..0000000000
--- a/chip/host/build.mk
+++ /dev/null
@@ -1,21 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# emulator specific files build
-#
-
-CORE:=host
-
-chip-y=system.o gpio.o uart.o persistence.o flash.o lpc.o reboot.o \
-	clock.o spi_controller.o trng.o
-
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-chip-$(CONFIG_USB_PD_TCPC)+=usb_pd_phy.o
-
-dirs-y += chip/host/dcrypto
-
-chip-$(CONFIG_I2C)+= i2c.o
diff --git a/chip/host/clock.c b/chip/host/clock.c
deleted file mode 100644
index 2c3c48661e..0000000000
--- a/chip/host/clock.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock clock driver for unit test.
- */
-
-#include "clock.h"
-
-int clock_get_freq(void)
-{
-	return 16000000;
-}
diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h
deleted file mode 100644
index 84e254d8a0..0000000000
--- a/chip/host/config_chip.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Chip config header file */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* Memory mapping */
-#if !defined(TEST_NVMEM) && !defined(TEST_CR50_FUZZ)
-#define CONFIG_FLASH_SIZE_BYTES 0x00020000
-#define CONFIG_FLASH_BANK_SIZE 0x1000
-#else
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_FLASH_BANK_SIZE 0x800
-#endif
-
-extern char __host_flash[CONFIG_FLASH_SIZE_BYTES];
-
-#define CONFIG_PROGRAM_MEMORY_BASE ((uintptr_t)__host_flash)
-#define CONFIG_FLASH_ERASE_SIZE 0x0010	     /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002	     /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 /* ideal write size */
-#define CONFIG_RAM_BASE 0x0		     /* Not supported */
-#define CONFIG_RAM_SIZE                0x0 /* Not supported */
-
-#define CONFIG_FPU
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 250
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Do NOT use common panic code (designed to output information on the UART) */
-#undef CONFIG_COMMON_PANIC_OUTPUT
-/* Do NOT use common timer code which is designed for hardware counters. */
-#undef CONFIG_COMMON_TIMER
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#define I2C_PORT_COUNT 1
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/host/flash.c b/chip/host/flash.c
deleted file mode 100644
index 75212737e0..0000000000
--- a/chip/host/flash.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash module for emulator */
-
-#include <stdio.h>
-
-#include "common.h"
-#include "config_chip.h"
-#include "flash.h"
-#include "persistence.h"
-#include "util.h"
-
-/* This needs to be aligned to the erase bank size for NVCTR. */
-__aligned(CONFIG_FLASH_ERASE_SIZE) char __host_flash[CONFIG_FLASH_SIZE_BYTES];
-uint8_t __host_flash_protect[PHYSICAL_BANKS];
-
-/* Override this function to make flash erase/write operation fail */
-test_mockable int flash_pre_op(void)
-{
-	return EC_SUCCESS;
-}
-
-static int flash_check_protect(int offset, int size)
-{
-	int first_bank = offset / CONFIG_FLASH_BANK_SIZE;
-	int last_bank = DIV_ROUND_UP(offset + size,
-				     CONFIG_FLASH_BANK_SIZE);
-	int bank;
-
-	for (bank = first_bank; bank < last_bank; ++bank)
-		if (__host_flash_protect[bank])
-			return 1;
-	return 0;
-}
-
-static void flash_set_persistent(void)
-{
-	FILE *f = get_persistent_storage("flash", "wb");
-	int sz;
-
-	ASSERT(f != NULL);
-
-	sz = fwrite(__host_flash, sizeof(__host_flash), 1, f);
-	ASSERT(sz == 1);
-
-	release_persistent_storage(f);
-}
-
-static void flash_get_persistent(void)
-{
-	FILE *f = get_persistent_storage("flash", "rb");
-	int sz;
-
-	if (f == NULL) {
-		fprintf(stderr,
-			"No flash storage found. Initializing to 0xff.\n");
-		memset(__host_flash, 0xff, sizeof(__host_flash));
-		return;
-	}
-
-	sz = fread(__host_flash, sizeof(__host_flash), 1, f);
-	ASSERT(sz == 1);
-
-	release_persistent_storage(f);
-}
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	ASSERT((size & (CONFIG_FLASH_WRITE_SIZE - 1)) == 0);
-
-	if (flash_pre_op() != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	if (flash_check_protect(offset, size))
-		return EC_ERROR_ACCESS_DENIED;
-
-	memcpy(__host_flash + offset, data, size);
-	flash_set_persistent();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	ASSERT((size & (CONFIG_FLASH_ERASE_SIZE - 1)) == 0);
-
-	if (flash_pre_op() != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	if (flash_check_protect(offset, size))
-		return EC_ERROR_ACCESS_DENIED;
-
-	memset(__host_flash + offset, 0xff, size);
-	flash_set_persistent();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_get_protect(int bank)
-{
-	return __host_flash_protect[bank];
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	int i;
-	uint32_t flags = EC_FLASH_PROTECT_ALL_NOW;
-
-	for (i = 0; i < PHYSICAL_BANKS; ++i)
-		if (__host_flash_protect[i] == 0)
-			flags = 0;
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	memset(__host_flash_protect, 1, all ? PHYSICAL_BANKS : WP_BANK_COUNT);
-	return EC_SUCCESS;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-int crec_flash_pre_init(void)
-{
-	uint32_t prot_flags;
-
-	flash_get_persistent();
-
-	prot_flags = crec_flash_get_protect();
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = crec_flash_get_protect();
-		}
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/chip/host/gpio.c b/chip/host/gpio.c
deleted file mode 100644
index 3c15205ad5..0000000000
--- a/chip/host/gpio.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for emulator */
-
-#include "console.h"
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "timer.h"
-#include "util.h"
-
-static int gpio_values[GPIO_COUNT];
-static int gpio_interrupt_enabled[GPIO_COUNT];
-
-/* Create a dictionary of names for debug console print */
-#define GPIO_INT(name, pin, flags, signal) #name,
-#define GPIO(name, pin, flags) #name,
-const char * gpio_names[GPIO_COUNT] = {
-	#include "gpio.wrap"
-};
-#undef GPIO
-#undef GPIO_INT
-
-test_mockable void gpio_pre_init(void)
-{
-	/* Nothing */
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return gpio_values[signal];
-}
-
-static int gpio_interrupt_check(uint32_t flags, int old, int new)
-{
-	if ((flags & GPIO_INT_F_RISING) && old == 0 && new == 1)
-		return 1;
-	if ((flags & GPIO_INT_F_FALLING) && old == 1 && new == 0)
-		return 1;
-	if ((flags & GPIO_INT_F_LOW) && new == 0)
-		return 1;
-	if ((flags & GPIO_INT_F_HIGH) && new == 1)
-		return 1;
-	return 0;
-}
-
-test_mockable void gpio_set_level(enum gpio_signal signal, int value)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	const uint32_t flags = g->flags;
-	const int old_value = gpio_values[signal];
-	void (*ih)(enum gpio_signal signal);
-
-	gpio_values[signal] = value;
-
-	ccprints("Setting GPIO_%s to %d", gpio_names[signal], value);
-
-	if (signal >= GPIO_IH_COUNT || !gpio_interrupt_enabled[signal])
-		return;
-
-	ih = gpio_irq_handlers[signal];
-
-	if (gpio_interrupt_check(flags, old_value, value))
-		ih(signal);
-}
-
-test_mockable int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	gpio_interrupt_enabled[signal] = 1;
-	return EC_SUCCESS;
-}
-
-test_mockable int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	gpio_interrupt_enabled[signal] = 0;
-	return EC_SUCCESS;
-}
-
-test_mockable int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable void gpio_set_flags_by_mask(uint32_t port, uint32_t mask,
-					  uint32_t flags)
-{
-	/* Nothing */
-}
-
-test_mockable void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-						enum gpio_alternate_func func)
-{
-	/* Nothing */
-}
diff --git a/chip/host/host_test.h b/chip/host/host_test.h
deleted file mode 100644
index e2bf5448c3..0000000000
--- a/chip/host/host_test.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Unit testing for Chrome EC */
-
-#ifndef __CROS_EC_HOST_TEST_H
-#define __CROS_EC_HOST_TEST_H
-
-/* Emulator exit codes */
-#define EXIT_CODE_HIBERNATE BIT(7)
-
-/* Get emulator executable name */
-const char *__get_prog_name(void);
-
-#endif  /* __CROS_EC_HOST_TEST_H */
diff --git a/chip/host/i2c.c b/chip/host/i2c.c
deleted file mode 100644
index ba4ab376d2..0000000000
--- a/chip/host/i2c.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock I2C driver for unit test.
- */
-
-#include "hooks.h"
-#include "i2c.h"
-#include "i2c_private.h"
-#include "link_defs.h"
-#include "test_util.h"
-
-#define MAX_DETACHED_DEV_COUNT 3
-
-struct i2c_dev {
-	int port;
-	uint16_t addr_flags;
-	int valid;
-};
-
-static struct i2c_dev detached_devs[MAX_DETACHED_DEV_COUNT];
-
-static void detach_init(void)
-{
-	int i;
-	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		detached_devs[i].valid = 0;
-}
-DECLARE_HOOK(HOOK_INIT, detach_init, HOOK_PRIO_FIRST);
-
-int test_detach_i2c(const int port, const uint16_t addr_flags)
-{
-	int i;
-
-	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid == 0)
-			break;
-
-	if (i == MAX_DETACHED_DEV_COUNT)
-		return EC_ERROR_OVERFLOW;
-
-	detached_devs[i].port = port;
-	detached_devs[i].addr_flags = addr_flags;
-	detached_devs[i].valid = 1;
-
-	return EC_SUCCESS;
-}
-
-int test_attach_i2c(const int port, const uint16_t addr_flags)
-{
-	int i;
-
-	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid &&
-		    detached_devs[i].port == port &&
-		    detached_devs[i].addr_flags == addr_flags)
-			break;
-
-	if (i == MAX_DETACHED_DEV_COUNT)
-		return EC_ERROR_INVAL;
-
-	detached_devs[i].valid = 0;
-	return EC_SUCCESS;
-}
-
-static int test_check_detached(const int port,
-			       const uint16_t addr_flags)
-{
-	int i;
-
-	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid &&
-		    detached_devs[i].port == port &&
-		    detached_devs[i].addr_flags == addr_flags)
-			return 1;
-	return 0;
-}
-
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	const struct test_i2c_xfer *p;
-	int rv;
-
-	if (test_check_detached(port, addr_flags))
-		return EC_ERROR_UNKNOWN;
-	for (p = __test_i2c_xfer; p < __test_i2c_xfer_end; ++p) {
-		rv = p->routine(port, addr_flags,
-				out, out_size,
-				in, in_size, flags);
-		if (rv != EC_ERROR_INVAL)
-			return rv;
-	}
-	return EC_ERROR_UNKNOWN;
-}
-
-int chip_i2c_set_freq(int port, enum i2c_freq freq)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-enum i2c_freq chip_i2c_get_freq(int port)
-{
-	switch (i2c_ports[port].kbps) {
-	case 1000:
-		return I2C_FREQ_1000KHZ;
-	case 400:
-		return I2C_FREQ_400KHZ;
-	case 100:
-		return I2C_FREQ_100KHZ;
-	}
-
-	/* fallback to 100k */
-	return I2C_FREQ_100KHZ;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return 0;
-}
-
-void i2c_init(void)
-{
-	/* We don't actually need to initialize anything here for host tests */
-}
diff --git a/chip/host/keyboard_raw.c b/chip/host/keyboard_raw.c
deleted file mode 100644
index 3e1f755f7f..0000000000
--- a/chip/host/keyboard_raw.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Raw keyboard I/O layer for emulator */
-
-#include "common.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "task.h"
-#include "util.h"
-
-test_mockable void keyboard_raw_init(void)
-{
-	/* Nothing */
-}
-
-test_mockable void keyboard_raw_task_start(void)
-{
-	/* Nothing */
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	/* Nothing */
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Nothing pressed */
-	return 0;
-}
-
-test_mockable void keyboard_raw_enable_interrupt(int enable)
-{
-	/* Nothing */
-}
-
-test_mockable void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
-{
-#ifdef HAS_TASK_KEYSCAN
-	task_wake(TASK_ID_KEYSCAN);
-#endif
-}
diff --git a/chip/host/lpc.c b/chip/host/lpc.c
deleted file mode 100644
index dd64be9275..0000000000
--- a/chip/host/lpc.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for Chrome EC emulator */
-
-#include "lpc.h"
-
-test_mockable int lpc_keyboard_has_char(void)
-{
-	return 0;
-}
-
-test_mockable int lpc_keyboard_input_pending(void)
-{
-	return 0;
-}
-
-test_mockable void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	/* Do nothing */
-}
-
-test_mockable void lpc_keyboard_clear_buffer(void)
-{
-	/* Do nothing */
-}
-
-test_mockable void lpc_keyboard_resume_irq(void)
-{
-	/* Do nothing */
-}
diff --git a/chip/host/persistence.c b/chip/host/persistence.c
deleted file mode 100644
index 44d60f1bb8..0000000000
--- a/chip/host/persistence.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Persistence module for emulator */
-
-/* This provides storage that can be opened, closed and reopened by the
- * current process at will, whose naming even remains stable across multiple
- * invocations of the same executable, while providing a unique name for
- * each executable (as determined by path) that uses these routines.
- *
- * Useful when semi-permanent storage is required even with many
- * similar processes running in parallel (e.g. in a highly parallel
- * test suite run.
- *
- * mkstemp and friends don't provide these properties which is why we have
- * this homegrown implementation of something similar-yet-different.
- */
-
-#include <linux/limits.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <string.h>
-
-#include "util.h"
-
-/* The longest path in a chroot seems to be about 280 characters (as of
- * April 2021) so define a cut-off instead of just hoping for the best:
- * If we were to run into a path that is nearly PATH_MAX bytes long,
- * file names could end up being reused inadvertedly because the various
- * snprintf calls would cut off the trailing characters, so the "tag" (and
- * maybe more) is gone even though it only exists for differentiation.
- *
- * Instead bail out if we encounter a path (to an executable using these
- * routines) that is longer than we expect.
- *
- * Round up for some spare room because why not?
- */
-static const int max_len = 300;
-
-/* This must be at least the size of the prefix added in get_storage_path */
-static const int max_prefix_len = 25;
-
-static void get_storage_path(char *out)
-{
-	char buf[PATH_MAX];
-	int sz;
-	char *current;
-
-	sz = readlink("/proc/self/exe", buf, PATH_MAX - 1);
-	buf[sz] = '\0';
-
-	ASSERT(sz <= max_len);
-
-	/* replace / by underscores in the path to get the shared memory name */
-	current = strchr(buf, '/');
-	while (current) {
-		*current = '_';
-		current = strchr(current, '/');
-	}
-
-
-	sz = snprintf(out, PATH_MAX - 1, "/dev/shm/EC_persist_%.*s",
-		max_len, buf);
-	out[PATH_MAX - 1] = '\0';
-
-	ASSERT(sz <= max_len + max_prefix_len);
-}
-
-FILE *get_persistent_storage(const char *tag, const char *mode)
-{
-	char buf[PATH_MAX];
-	char path[PATH_MAX];
-
-	/* There's no longer tag in use right now, and there shouldn't be. */
-	ASSERT(strlen(tag) < 32);
-
-	/*
-	 * The persistent storage with tag 'foo' for test 'bar' would
-	 * be named 'bar_persist_foo'
-	 */
-	get_storage_path(buf);
-	snprintf(path, PATH_MAX - 1, "%.*s_%32s",
-		max_len + max_prefix_len, buf, tag);
-	path[PATH_MAX - 1] = '\0';
-
-	return fopen(path, mode);
-}
-
-void release_persistent_storage(FILE *ps)
-{
-	fclose(ps);
-}
-
-void remove_persistent_storage(const char *tag)
-{
-	char buf[PATH_MAX];
-	char path[PATH_MAX];
-
-	/* There's no longer tag in use right now, and there shouldn't be. */
-	ASSERT(strlen(tag) < 32);
-
-	get_storage_path(buf);
-	snprintf(path, PATH_MAX - 1, "%.*s_%32s",
-		max_len + max_prefix_len, buf, tag);
-	path[PATH_MAX - 1] = '\0';
-
-	unlink(path);
-}
diff --git a/chip/host/persistence.h b/chip/host/persistence.h
deleted file mode 100644
index a473f8dfb0..0000000000
--- a/chip/host/persistence.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Persistence module for emulator */
-
-#ifndef __CROS_EC_PERSISTENCE_H
-#define __CROS_EC_PERSISTENCE_H
-
-#include <stdio.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-FILE *get_persistent_storage(const char *tag, const char *mode);
-
-void release_persistent_storage(FILE *ps);
-
-void remove_persistent_storage(const char *tag);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CROS_EC_PERSISTENCE_H */
diff --git a/chip/host/reboot.c b/chip/host/reboot.c
deleted file mode 100644
index e932c5f11a..0000000000
--- a/chip/host/reboot.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Emulator self-reboot procedure */
-
-#include <string.h>
-#include <unistd.h>
-
-#include "console.h"
-#include "host_test.h"
-#include "reboot.h"
-#include "test_util.h"
-
-#ifdef TEST_FUZZ
-/* reboot breaks fuzzing, let's just not do it. */
-void emulator_reboot(void)
-{
-	ccprints("Emulator would reboot here. Fuzzing: doing nothing.");
-}
-#else /* !TEST_FUZZ */
-noreturn
-void emulator_reboot(void)
-{
-	char *argv[] = {strdup(__get_prog_name()), NULL};
-	emulator_flush();
-	execv(__get_prog_name(), argv);
-	while (1)
-		;
-}
-#endif /* !TEST_FUZZ */
diff --git a/chip/host/reboot.h b/chip/host/reboot.h
deleted file mode 100644
index 1c1201f451..0000000000
--- a/chip/host/reboot.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Emulator self-reboot procedure */
-
-#ifndef __CROS_EC_REBOOT_H
-#define __CROS_EC_REBOOT_H
-
-#include <stdnoreturn.h>
-
-#ifndef TEST_FUZZ
-noreturn
-#endif
-void emulator_reboot(void);
-
-#endif
diff --git a/chip/host/registers.h b/chip/host/registers.h
deleted file mode 100644
index 7347ce04d3..0000000000
--- a/chip/host/registers.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Empty registers header for emulator */
-
-/*
- * There is no register for emulator, but this file exists to prevent
- * compilation failure if any file includes registers.h
- */
diff --git a/chip/host/spi_controller.c b/chip/host/spi_controller.c
deleted file mode 100644
index c7afea5d39..0000000000
--- a/chip/host/spi_controller.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock SPI Controller driver for unit test.
- */
-
-#include <stdint.h>
-
-#include "common.h"
-#include "gpio.h"
-
-#include "spi.h"
-
-test_mockable int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction(const struct spi_device_t *spi_device,
-				  const uint8_t *txdata, int txlen,
-				  uint8_t *rxdata, int rxlen)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction_async(const struct spi_device_t *spi_device,
-					const uint8_t *txdata, int txlen,
-					uint8_t *rxdata, int rxlen)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	return EC_SUCCESS;
-}
diff --git a/chip/host/system.c b/chip/host/system.c
deleted file mode 100644
index 60d765deab..0000000000
--- a/chip/host/system.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for emulator */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "host_test.h"
-#include "panic.h"
-#include "persistence.h"
-#include "reboot.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-// Forward declaration from <stdlib.h> to avoid declaration conflicts.
-void exit(int);
-
-#define SHARED_MEM_SIZE 0x2000 /* bytes */
-#define RAM_DATA_SIZE (sizeof(struct panic_data) + 512) /* bytes */
-uint8_t __shared_mem_buf[SHARED_MEM_SIZE + RAM_DATA_SIZE];
-
-static char *__ram_data = __shared_mem_buf + SHARED_MEM_SIZE;
-
-static enum ec_image __running_copy;
-
-static void ramdata_set_persistent(void)
-{
-	FILE *f = get_persistent_storage("ramdata", "wb");
-	int sz;
-
-	ASSERT(f != NULL);
-
-	sz = fwrite(__ram_data, RAM_DATA_SIZE, 1, f);
-	ASSERT(sz == 1);
-
-	release_persistent_storage(f);
-}
-
-static void ramdata_get_persistent(void)
-{
-	FILE *f = get_persistent_storage("ramdata", "rb");
-
-	if ((f == NULL) || (fread(__ram_data, RAM_DATA_SIZE, 1, f) != 1)) {
-		fprintf(stderr,
-			"No RAM data found. Initializing to 0x00.\n");
-		memset(__ram_data, 0, RAM_DATA_SIZE);
-		return;
-	}
-
-	release_persistent_storage(f);
-
-	/*
-	 * Assumes RAM data doesn't preserve across reboot except for sysjump.
-	 * Clear persistent data once it's read.
-	 */
-	remove_persistent_storage("ramdata");
-}
-
-static void set_image_copy(uint32_t copy)
-{
-	FILE *f = get_persistent_storage("image_copy", "wb");
-
-	ASSERT(f != NULL);
-	ASSERT(fwrite(&copy, sizeof(copy), 1, f) == 1);
-
-	release_persistent_storage(f);
-}
-
-static uint32_t get_image_copy(void)
-{
-	FILE *f = get_persistent_storage("image_copy", "rb");
-	uint32_t ret;
-
-	if ((f == NULL) || (fread(&ret, sizeof(ret), 1, f) != 1))
-		return EC_IMAGE_UNKNOWN;
-	release_persistent_storage(f);
-	remove_persistent_storage("image_copy");
-
-	return ret;
-}
-
-static void save_reset_flags(uint32_t flags)
-{
-	FILE *f = get_persistent_storage("reset_flags", "wb");
-
-	ASSERT(f != NULL);
-	ASSERT(fwrite(&flags, sizeof(flags), 1, f) == 1);
-
-	release_persistent_storage(f);
-}
-
-static uint32_t load_reset_flags(void)
-{
-	FILE *f = get_persistent_storage("reset_flags", "rb");
-	uint32_t ret;
-
-	if ((f == NULL) || (fread(&ret, sizeof(ret), 1, f) != 1))
-		return EC_RESET_FLAG_POWER_ON;
-	release_persistent_storage(f);
-	remove_persistent_storage("reset_flags");
-
-	return ret;
-}
-
-static void save_time(timestamp_t t)
-{
-	FILE *f = get_persistent_storage("time", "wb");
-
-	ASSERT(f != NULL);
-	ASSERT(fwrite(&t, sizeof(t), 1, f) == 1);
-
-	release_persistent_storage(f);
-}
-
-static int load_time(timestamp_t *t)
-{
-	FILE *f = get_persistent_storage("time", "rb");
-
-	if ((f == NULL) || (fread(t, sizeof(*t), 1, f) != 1))
-		return 0;
-	release_persistent_storage(f);
-	remove_persistent_storage("time");
-
-	return 1;
-}
-
-test_mockable struct panic_data *panic_get_data(void)
-{
-	return (struct panic_data *)
-		(__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data));
-}
-
-test_mockable uintptr_t get_panic_data_start()
-{
-	return (uintptr_t)
-		(__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data));
-}
-
-test_mockable void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-	if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-	if (save_flags)
-		save_reset_flags(save_flags);
-	emulator_reboot();
-}
-
-test_mockable void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	uint32_t i;
-
-	if (board_hibernate)
-		board_hibernate();
-
-	save_reset_flags(EC_RESET_FLAG_HIBERNATE);
-
-	if (!seconds && !microseconds)
-		exit(EXIT_CODE_HIBERNATE);
-
-	for (i = 0; i < seconds; ++i)
-		udelay(SECOND);
-	udelay(microseconds);
-	emulator_reboot();
-}
-
-test_mockable int system_is_locked(void)
-{
-	return 0;
-}
-
-#ifdef TEST_FUZZ
-/* When fuzzing, do not allow sysjumps. */
-int system_run_image_copy(enum ec_image copy)
-{
-	ccprints("Emulator would sysjump here. Fuzzing: doing nothing.");
-	return EC_ERROR_UNKNOWN;
-}
-#endif
-
-const char *system_get_chip_vendor(void)
-{
-	return "chromeos";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "emu";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-enum ec_image system_get_image_copy(void)
-{
-	return __running_copy;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	FILE *f = get_persistent_storage("scratchpad", "w");
-
-	fprintf(f, "%u", value);
-	release_persistent_storage(f);
-
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	FILE *f = get_persistent_storage("scratchpad", "r");
-	int success;
-
-	if (f == NULL)
-		return EC_ERROR_UNKNOWN;
-
-	success = fscanf(f, "%u", value);
-	release_persistent_storage(f);
-
-	if (success)
-		return EC_SUCCESS;
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-static void __jump_resetvec(void)
-{
-	save_time(get_time());
-	ramdata_set_persistent();
-	emulator_reboot();
-}
-
-static void __ro_jump_resetvec(void)
-{
-	set_image_copy(EC_IMAGE_RO);
-	__jump_resetvec();
-}
-
-static void __rw_jump_resetvec(void)
-{
-	set_image_copy(EC_IMAGE_RW);
-	__jump_resetvec();
-}
-
-void system_pre_init(void)
-{
-	timestamp_t t;
-
-	if (load_time(&t))
-		force_time(t);
-
-	ramdata_get_persistent();
-	__running_copy = get_image_copy();
-	if (__running_copy == EC_IMAGE_UNKNOWN) {
-		__running_copy = EC_IMAGE_RO;
-		system_set_reset_flags(load_reset_flags());
-	}
-
-	*(uintptr_t *)(__host_flash + CONFIG_RO_MEM_OFF + 4) =
-		(uintptr_t)__ro_jump_resetvec;
-	*(uintptr_t *)(__host_flash + CONFIG_RW_MEM_OFF + 4) =
-		(uintptr_t)__rw_jump_resetvec;
-}
diff --git a/chip/host/trng.c b/chip/host/trng.c
deleted file mode 100644
index 8407aa6ea1..0000000000
--- a/chip/host/trng.c
+++ /dev/null
@@ -1,40 +0,0 @@
-
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock TRNG driver for unit test.
- *
- * Although a TRNG is designed to be anything but predictable,
- * this implementation strives to be as predictable and defined
- * as possible to allow reproducing unit tests and fuzzer crashes.
- */
-
-#ifndef TEST_BUILD
-#error "This fake trng driver must not be used in non-test builds."
-#endif
-
-#include <stdint.h>
-#include <stdlib.h> /* Only valid for host */
-
-#include "common.h"
-
-static unsigned int seed;
-
-test_mockable void init_trng(void)
-{
-	seed = 0;
-	srand(seed);
-}
-
-test_mockable void exit_trng(void)
-{
-}
-
-test_mockable void rand_bytes(void *buffer, size_t len)
-{
-	uint8_t *b, *end;
-
-	for (b = buffer, end = b+len; b != end; b++)
-		*b = (uint8_t)rand_r(&seed);
-}
diff --git a/chip/host/uart.c b/chip/host/uart.c
deleted file mode 100644
index 578924612f..0000000000
--- a/chip/host/uart.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART driver for emulator */
-
-#include <pthread.h>
-#include <signal.h>
-#include <stdio.h>
-#include <termio.h>
-#include <unistd.h>
-
-#include "common.h"
-#include "queue.h"
-#include "task.h"
-#include "test_util.h"
-#include "uart.h"
-#include "util.h"
-
-static int stopped = 1;
-static int init_done;
-
-#ifndef TEST_FUZZ
-static pthread_t input_thread;
-#endif
-
-#define INPUT_BUFFER_SIZE 16
-static int char_available;
-
-static struct queue const cached_char = QUEUE_NULL(INPUT_BUFFER_SIZE, char);
-
-#define CONSOLE_CAPTURE_SIZE 2048
-static char capture_buf[CONSOLE_CAPTURE_SIZE];
-static int capture_size;
-static int capture_enabled;
-
-void test_capture_console(int enabled)
-{
-	if (enabled == capture_enabled)
-		return;
-
-	if (enabled)
-		capture_size = 0;
-	else
-		capture_buf[capture_size] = '\0';
-
-	capture_enabled = enabled;
-}
-
-static void test_capture_char(char c)
-{
-	if (capture_size == CONSOLE_CAPTURE_SIZE)
-		return;
-	capture_buf[capture_size++] = c;
-}
-
-
-const char *test_get_captured_console(void)
-{
-	return (const char *)capture_buf;
-}
-
-static void uart_interrupt(void)
-{
-	uart_process_input();
-	uart_process_output();
-}
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	stopped = 0;
-	task_trigger_test_interrupt(uart_interrupt);
-}
-
-void uart_tx_stop(void)
-{
-	stopped = 1;
-}
-
-int uart_tx_stopped(void)
-{
-	return stopped;
-}
-
-void uart_tx_flush(void)
-{
-	/* Nothing */
-}
-
-int uart_tx_ready(void)
-{
-	return 1;
-}
-
-int uart_rx_available(void)
-{
-	return char_available;
-}
-
-void uart_write_char(char c)
-{
-	if (capture_enabled)
-		test_capture_char(c);
-	printf("%c", c);
-	fflush(stdout);
-}
-
-int uart_read_char(void)
-{
-	char ret;
-	ASSERT(in_interrupt_context());
-	queue_remove_unit(&cached_char, &ret);
-	--char_available;
-	return ret;
-}
-
-void uart_inject_char(char *s, int sz)
-{
-	int i;
-	int num_char;
-
-	for (i = 0; i < sz; i += INPUT_BUFFER_SIZE - 1) {
-		num_char = MIN(INPUT_BUFFER_SIZE - 1, sz - i);
-		if (queue_space(&cached_char) < num_char)
-			return;
-		queue_add_units(&cached_char, s + i, num_char);
-		char_available = num_char;
-		task_trigger_test_interrupt(uart_interrupt);
-	}
-}
-
-/*
- * We do not really need console input when fuzzing, and having it enabled
- * breaks terminal when an error is detected.
- */
-#ifndef TEST_FUZZ
-static pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
-static pthread_cond_t uart_monitor_initialized = PTHREAD_COND_INITIALIZER;
-
-void *uart_monitor_stdin(void *d)
-{
-	struct termios org_settings, new_settings;
-	char buf[INPUT_BUFFER_SIZE];
-	int rv;
-
-	pthread_mutex_lock(&mutex);
-	tcgetattr(0, &org_settings);
-	new_settings = org_settings;
-	new_settings.c_lflag &= ~(ECHO | ICANON);
-	new_settings.c_cc[VTIME] = 0;
-	new_settings.c_cc[VMIN] = 1;
-
-	printf("Console input initialized\n");
-	/* Allow uart_init to proceed now that UART monitor is initialized. */
-	pthread_cond_signal(&uart_monitor_initialized);
-	pthread_mutex_unlock(&mutex);
-	while (1) {
-		tcsetattr(0, TCSANOW, &new_settings);
-		rv = read(0, buf, INPUT_BUFFER_SIZE);
-		if (queue_space(&cached_char) >= rv) {
-			queue_add_units(&cached_char, buf, rv);
-			char_available = rv;
-		}
-		tcsetattr(0, TCSANOW, &org_settings);
-		/*
-		 * Trigger emulated interrupt to process input. Keyboard
-		 * input while interrupt handler runs is queued by the
-		 * system.
-		 */
-		task_trigger_test_interrupt(uart_interrupt);
-	}
-
-	return 0;
-}
-#endif /* !TEST_FUZZ */
-
-void uart_init(void)
-{
-#ifndef TEST_FUZZ
-	/* Create UART monitor thread and wait for it to initialize. */
-	pthread_mutex_lock(&mutex);
-	pthread_create(&input_thread, NULL, uart_monitor_stdin, NULL);
-	pthread_cond_wait(&uart_monitor_initialized, &mutex);
-	pthread_mutex_unlock(&mutex);
-#endif
-
-	stopped = 1;  /* Not transmitting yet */
-	init_done = 1;
-}
diff --git a/chip/host/usb_pd_phy.c b/chip/host/usb_pd_phy.c
deleted file mode 100644
index ba81b986ad..0000000000
--- a/chip/host/usb_pd_phy.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "crc.h"
-#include "task.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-#include "util.h"
-
-#define PREAMBLE_OFFSET 60 /* Any number should do */
-
-/*
- * Maximum size of a Power Delivery packet (in bits on the wire) :
- *    16-bit header + 0..7 32-bit data objects  (+ 4b5b encoding)
- * 64-bit preamble + SOP (4x 5b) + message in 4b5b + 32-bit CRC + EOP (1x 5b)
- * = 64 + 4*5 + 16 * 5/4 + 7 * 32 * 5/4 + 32 * 5/4 + 5
- */
-#define PD_BIT_LEN 429
-
-static struct pd_physical {
-	int hw_init_done;
-
-	uint8_t bits[PD_BIT_LEN];
-	int total;
-	int has_preamble;
-	int rx_started;
-	int rx_monitoring;
-
-	int preamble_written;
-	int has_msg;
-	int last_edge_written;
-	uint8_t out_msg[PD_BIT_LEN / 5];
-	int verified_idx;
-} pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static const uint16_t enc4b5b[] = {
-	0x1E, 0x09, 0x14, 0x15, 0x0A, 0x0B, 0x0E, 0x0F, 0x12, 0x13, 0x16,
-	0x17, 0x1A, 0x1B, 0x1C, 0x1D};
-
-/* Test utilities */
-static void pd_test_reset_phy(int port)
-{
-	int i;
-	int enc_len = PD_BIT_LEN / 5;
-
-	for (i = 0; i < PD_BIT_LEN; i++)
-		pd_phy[port].bits[i] = 0;
-
-	for (i = 0; i < enc_len; i++)
-		pd_phy[port].out_msg[i] = 0;
-
-	pd_phy[port].total = 0;
-	pd_phy[port].has_preamble = 0;
-	pd_phy[port].rx_started = 0;
-	pd_phy[port].rx_monitoring = 0;
-	pd_phy[port].preamble_written = 0;
-	pd_phy[port].has_msg = 0;
-	pd_phy[port].last_edge_written = 0;
-	pd_phy[port].verified_idx = 0;
-}
-
-void pd_test_rx_set_preamble(int port, int has_preamble)
-{
-	pd_phy[port].total = 0;
-	pd_phy[port].has_preamble = has_preamble;
-}
-
-void pd_test_rx_msg_append_bits(int port, uint32_t bits, int nb)
-{
-	int i;
-
-	for (i = 0; i < nb; ++i) {
-		pd_phy[port].bits[pd_phy[port].total++] = bits & 1;
-		bits >>= 1;
-	}
-}
-
-void pd_test_rx_msg_append_kcode(int port, uint8_t kcode)
-{
-	pd_test_rx_msg_append_bits(port, kcode, 5);
-}
-
-void pd_test_rx_msg_append_sop(int port)
-{
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC2);
-}
-
-void pd_test_rx_msg_append_sop_prime(int port)
-{
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC3);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC3);
-}
-
-void pd_test_rx_msg_append_sop_prime_prime(int port)
-{
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC3);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC3);
-}
-
-void pd_test_rx_msg_append_eop(int port)
-{
-	pd_test_rx_msg_append_kcode(port, PD_EOP);
-}
-
-void pd_test_rx_msg_append_last_edge(int port)
-{
-	/* end with 1, 1, 0 similar to pd_write_last_edge() */
-	pd_test_rx_msg_append_bits(port, 3, 6);
-}
-
-void pd_test_rx_msg_append_4b(int port, uint8_t val)
-{
-	pd_test_rx_msg_append_bits(port, enc4b5b[val & 0xF], 5);
-}
-
-void pd_test_rx_msg_append_short(int port, uint16_t val)
-{
-	pd_test_rx_msg_append_4b(port, (val >> 0) & 0xF);
-	pd_test_rx_msg_append_4b(port, (val >> 4) & 0xF);
-	pd_test_rx_msg_append_4b(port, (val >> 8) & 0xF);
-	pd_test_rx_msg_append_4b(port, (val >> 12) & 0xF);
-}
-
-void pd_test_rx_msg_append_word(int port, uint32_t val)
-{
-	pd_test_rx_msg_append_short(port, val & 0xFFFF);
-	pd_test_rx_msg_append_short(port, val >> 16);
-}
-
-void pd_simulate_rx(int port)
-{
-	if (!pd_phy[port].rx_monitoring)
-		return;
-
-	pd_phy[port].rx_started = 1;
-	pd_rx_disable_monitoring(port);
-	pd_rx_event(port);
-}
-
-static int pd_test_tx_msg_verify(int port, uint8_t raw)
-{
-	int verified_idx = pd_phy[port].verified_idx++;
-	return pd_phy[port].out_msg[verified_idx] == raw;
-}
-
-int pd_test_tx_msg_verify_kcode(int port, uint8_t kcode)
-{
-	return pd_test_tx_msg_verify(port, kcode);
-}
-
-int pd_test_tx_msg_verify_sop(int port)
-{
-	crc32_init();
-	return pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC2);
-}
-
-int pd_test_tx_msg_verify_sop_prime(int port)
-{
-	crc32_init();
-	return pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC3) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC3);
-}
-
-int pd_test_tx_msg_verify_sop_prime_prime(int port)
-{
-	crc32_init();
-	return pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC3) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC3);
-}
-
-int pd_test_tx_msg_verify_eop(int port)
-{
-	return pd_test_tx_msg_verify_kcode(port, PD_EOP);
-}
-
-int pd_test_tx_msg_verify_4b5b(int port, uint8_t b4)
-{
-	return pd_test_tx_msg_verify(port, enc4b5b[b4]);
-}
-
-int pd_test_tx_msg_verify_short(int port, uint16_t val)
-{
-	crc32_hash16(val);
-	return pd_test_tx_msg_verify_4b5b(port, (val >> 0) & 0xF) &&
-	       pd_test_tx_msg_verify_4b5b(port, (val >> 4) & 0xF) &&
-	       pd_test_tx_msg_verify_4b5b(port, (val >> 8) & 0xF) &&
-	       pd_test_tx_msg_verify_4b5b(port, (val >> 12) & 0xF);
-}
-
-int pd_test_tx_msg_verify_word(int port, uint32_t val)
-{
-	return pd_test_tx_msg_verify_short(port, val & 0xFFFF) &&
-	       pd_test_tx_msg_verify_short(port, val >> 16);
-}
-
-int pd_test_tx_msg_verify_crc(int port)
-{
-	return pd_test_tx_msg_verify_word(port, crc32_result());
-}
-
-
-/* Mock functions */
-
-void pd_init_dequeue(int port)
-{
-}
-
-int pd_dequeue_bits(int port, int off, int len, uint32_t *val)
-{
-	int i;
-
-	/* Rx must have started to receive message */
-	ASSERT(pd_phy[port].rx_started);
-
-	if (pd_phy[port].total <= off + len - PREAMBLE_OFFSET)
-		return -1;
-	*val = 0;
-	for (i = 0; i < len; ++i)
-		*val |= pd_phy[port].bits[off + i - PREAMBLE_OFFSET] << i;
-	return off + len;
-}
-
-int pd_find_preamble(int port)
-{
-	return pd_phy[port].has_preamble ? PREAMBLE_OFFSET : -1;
-}
-
-int pd_write_preamble(int port)
-{
-	ASSERT(pd_phy[port].preamble_written == 0);
-	pd_phy[port].preamble_written = 1;
-	ASSERT(pd_phy[port].has_msg == 0);
-	return 0;
-}
-
-static uint8_t decode_bmc(uint32_t val10)
-{
-	uint8_t ret = 0;
-	int i;
-
-	for (i = 0; i < 5; ++i)
-		if (!!(val10 & (1 << (2 * i))) !=
-		    !!(val10 & (1 << (2 * i + 1))))
-			ret |= BIT(i);
-	return ret;
-}
-
-int pd_write_sym(int port, int bit_off, uint32_t val10)
-{
-	pd_phy[port].out_msg[bit_off] = decode_bmc(val10);
-	pd_phy[port].has_msg = 1;
-	return bit_off + 1;
-}
-
-int pd_write_last_edge(int port, int bit_off)
-{
-	pd_phy[port].last_edge_written = 1;
-	return bit_off;
-}
-
-void pd_dump_packet(int port, const char *msg)
-{
-	/* Not implemented */
-}
-
-void pd_tx_set_circular_mode(int port)
-{
-	/* Not implemented */
-}
-
-void pd_tx_clear_circular_mode(int port)
-{
-	/* Not implemented */
-}
-
-int pd_start_tx(int port, int polarity, int bit_len)
-{
-	ASSERT(pd_phy[port].hw_init_done);
-	pd_phy[port].has_msg = 0;
-	pd_phy[port].preamble_written = 0;
-	pd_phy[port].verified_idx = 0;
-	pd_phy[port].total = 0;
-
-	/*
-	 * Hand over to test runner. The test runner must wake us after
-	 * processing the packet.
-	 */
-	task_wake(TASK_ID_TEST_RUNNER);
-	task_wait_event(-1);
-
-	return bit_len;
-}
-
-void pd_tx_done(int port, int polarity)
-{
-	pd_test_reset_phy(port);
-}
-
-void pd_rx_start(int port)
-{
-	ASSERT(pd_phy[port].hw_init_done);
-
-	task_wake(TASK_ID_TEST_RUNNER);
-	task_wait_event(-1);
-
-	pd_phy[port].rx_started = 1;
-}
-
-void pd_rx_complete(int port)
-{
-	ASSERT(pd_phy[port].hw_init_done);
-	pd_test_reset_phy(port);
-}
-
-int pd_rx_started(int port)
-{
-	return pd_phy[port].rx_started;
-}
-
-void pd_rx_enable_monitoring(int port)
-{
-	ASSERT(pd_phy[port].hw_init_done);
-	pd_phy[port].rx_monitoring = 1;
-}
-
-void pd_rx_disable_monitoring(int port)
-{
-	/*
-	 * We disabled RX monitoring in TCPMv1 in set_state when
-	 * transitioning from suspended to disconnected, but we only
-	 * reinitialize after we have fully transitioned to disconnected. Don't
-	 * assert that hw_init_done here since we have "valid" code that
-	 * requires hw_init_done to be false when a port is suspended.
-	 */
-	pd_phy[port].rx_monitoring = 0;
-}
-
-void pd_hw_release(int port)
-{
-	pd_phy[port].hw_init_done = 0;
-}
-
-void pd_hw_init(int port, enum pd_power_role role)
-{
-	pd_config_init(port, role);
-	pd_phy[port].hw_init_done = 1;
-}
-
-void pd_set_clock(int port, int freq)
-{
-	/* Not implemented */
-}
diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c
deleted file mode 100644
index 2839da5af2..0000000000
--- a/chip/it83xx/adc.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT83xx ADC module for Chrome EC */
-
-#include "adc.h"
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/* Global variables */
-static struct mutex adc_lock;
-static int adc_init_done;
-static volatile task_id_t task_waiting;
-
-/* Data structure of ADC channel control registers. */
-const struct adc_ctrl_t adc_ctrl_regs[] = {
-	{&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL},
-	{&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL},
-	{&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL},
-	{&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL},
-	{&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL},
-	{&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL},
-	{&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL},
-	{&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL},
-	{&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL},
-	{&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL},
-	{&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL},
-	{&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT);
-
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-#define VCMP_ADC_CH_MASK_H           BIT(3)
-#define VCMP_ADC_CH_MASK_L           0x7
-/* 10-bits resolution */
-#define VCMP_RESOLUTION              BIT(10)
-#define VCMP_MAX_MVOLT               3000
-
-/* Data structure of voltage comparator control registers. */
-const struct vcmp_ctrl_t vcmp_ctrl_regs[] = {
-	{&IT83XX_ADC_VCMP0CTL, &IT83XX_ADC_VCMP0CSELM, &IT83XX_ADC_CMP0THRDATM,
-		&IT83XX_ADC_CMP0THRDATL},
-	{&IT83XX_ADC_VCMP1CTL, &IT83XX_ADC_VCMP1CSELM, &IT83XX_ADC_CMP1THRDATM,
-		&IT83XX_ADC_CMP1THRDATL},
-	{&IT83XX_ADC_VCMP2CTL, &IT83XX_ADC_VCMP2CSELM, &IT83XX_ADC_CMP2THRDATM,
-		&IT83XX_ADC_CMP2THRDATL},
-	{&IT83XX_ADC_VCMP3CTL, &IT83XX_ADC_VCMP3CSELM, &IT83XX_ADC_CMP3THRDATM,
-		&IT83XX_ADC_CMP3THRDATL},
-	{&IT83XX_ADC_VCMP4CTL, &IT83XX_ADC_VCMP4CSELM, &IT83XX_ADC_CMP4THRDATM,
-		&IT83XX_ADC_CMP4THRDATL},
-	{&IT83XX_ADC_VCMP5CTL, &IT83XX_ADC_VCMP5CSELM, &IT83XX_ADC_CMP5THRDATM,
-		&IT83XX_ADC_CMP5THRDATL},
-};
-BUILD_ASSERT(ARRAY_SIZE(vcmp_ctrl_regs) == CHIP_VCMP_COUNT);
-#endif
-
-static void adc_enable_channel(int ch)
-{
-	if (ch < CHIP_ADC_CH4)
-		/*
-		 * for channel 0, 1, 2, and 3
-		 * bit4 ~ bit0 : indicates voltage channel[x]
-		 *               input is selected for measurement (enable)
-		 * bit5 : data valid interrupt of adc.
-		 * bit7 : W/C data valid flag
-		 */
-		*adc_ctrl_regs[ch].adc_ctrl = 0xa0 + ch;
-	else
-		/*
-		 * for channel 4 ~ 7 and 13 ~ 16.
-		 * bit4 : voltage channel enable (ch 4~7 and 13 ~ 16)
-		 * bit5 : data valid interrupt of adc.
-		 * bit7 : W/C data valid flag
-		 */
-		*adc_ctrl_regs[ch].adc_ctrl = 0xb0;
-
-	task_clear_pending_irq(IT83XX_IRQ_ADC);
-	task_enable_irq(IT83XX_IRQ_ADC);
-
-	/* bit 0 : adc module enable */
-	IT83XX_ADC_ADCCFG |= 0x01;
-}
-
-static void adc_disable_channel(int ch)
-{
-	if (ch < CHIP_ADC_CH4)
-		/*
-		 * for channel 0, 1, 2, and 3
-		 * bit4 ~ bit0 : indicates voltage channel[x]
-		 *               input is selected for measurement (disable)
-		 * bit 7 : W/C data valid flag
-		 */
-		*adc_ctrl_regs[ch].adc_ctrl = 0x9F;
-	else
-		/*
-		 * for channel 4 ~ 7 and 13 ~ 16.
-		 * bit4 : voltage channel disable (ch 4~7 and 13 ~ 16)
-		 * bit7 : W/C data valid flag
-		 */
-		*adc_ctrl_regs[ch].adc_ctrl = 0x80;
-
-	/* bit 0 : adc module disable */
-	IT83XX_ADC_ADCCFG &= ~0x01;
-
-	task_disable_irq(IT83XX_IRQ_ADC);
-}
-
-static int adc_data_valid(enum chip_adc_channel adc_ch)
-{
-	return (adc_ch <= CHIP_ADC_CH7) ?
-		(IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) :
-		(IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13)));
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	uint32_t events;
-	/* voltage 0 ~ 3v = adc data register raw data 0 ~ 3FFh (10-bit ) */
-	uint16_t adc_raw_data;
-	int valid = 0;
-	int adc_ch, mv;
-
-	if (!adc_init_done)
-		return ADC_READ_ERROR;
-
-	mutex_lock(&adc_lock);
-
-	disable_sleep(SLEEP_MASK_ADC);
-	task_waiting = task_get_current();
-	adc_ch = adc_channels[ch].channel;
-	adc_enable_channel(adc_ch);
-	/* Wait for interrupt */
-	events = task_wait_event_mask(TASK_EVENT_ADC_DONE, ADC_TIMEOUT_US);
-	task_waiting = TASK_ID_INVALID;
-	/*
-	 * Ensure EC won't post the adc done event which is set after getting
-	 * events (events |= __wait_evt() in task_wait_event_mask()) to next
-	 * adc read.
-	 * NOTE: clear TASK_EVENT_ADC_DONE event must happen after setting
-	 * task_waiting to invalid. So TASK_EVENT_ADC_DONE would not set until
-	 * next read.
-	 */
-	atomic_clear_bits(task_get_event_bitmap(task_get_current()),
-		TASK_EVENT_ADC_DONE);
-
-	/* data valid of adc channel[x] */
-	if (adc_data_valid(adc_ch)) {
-		/* read adc raw data msb and lsb */
-		adc_raw_data = (*adc_ctrl_regs[adc_ch].adc_datm << 8) +
-			*adc_ctrl_regs[adc_ch].adc_datl;
-
-		/* W/C data valid flag */
-		if (adc_ch <= CHIP_ADC_CH7)
-			IT83XX_ADC_ADCDVSTS = BIT(adc_ch);
-		else
-			IT83XX_ADC_ADCDVSTS2 = (1 << (adc_ch - CHIP_ADC_CH13));
-
-		mv = adc_raw_data * adc_channels[ch].factor_mul /
-			adc_channels[ch].factor_div + adc_channels[ch].shift;
-		valid = 1;
-	}
-
-	if (!valid) {
-		CPRINTS("ADC failed to read!!! (regs=%x, %x, ch=%d, evt=%x)",
-			IT83XX_ADC_ADCDVSTS,
-			IT83XX_ADC_ADCDVSTS2,
-			adc_ch, events);
-	}
-
-	adc_disable_channel(adc_ch);
-	enable_sleep(SLEEP_MASK_ADC);
-
-	mutex_unlock(&adc_lock);
-
-	return valid ? mv : ADC_READ_ERROR;
-}
-
-void adc_interrupt(void)
-{
-	/*
-	 * Clear the interrupt status.
-	 *
-	 * NOTE:
-	 * The ADC interrupt pending flag won't be cleared unless
-	 * we W/C data valid flag of ADC module as well.
-	 * (If interrupt type setting is high-level triggered)
-	 */
-	task_clear_pending_irq(IT83XX_IRQ_ADC);
-	/*
-	 * We disable ADC interrupt here, because current setting of
-	 * interrupt type is high-level triggered.
-	 * The interrupt will be triggered again and again until
-	 * we W/C data valid flag if we don't disable it.
-	 */
-	task_disable_irq(IT83XX_IRQ_ADC);
-	/* Wake up the task which was waiting for the interrupt */
-	if (task_waiting != TASK_ID_INVALID)
-		task_set_event(task_waiting, TASK_EVENT_ADC_DONE);
-}
-
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-/* Clear voltage comparator interrupt status */
-void clear_vcmp_status(int vcmp_x)
-{
-	if (vcmp_x <= CHIP_VCMP2)
-		IT83XX_ADC_VCMPSTS = BIT(vcmp_x);
-	else
-		IT83XX_ADC_VCMPSTS2 = BIT(vcmp_x - CHIP_VCMP3);
-}
-
-/* Enable/Disable voltage comparator interrupt */
-void vcmp_enable(int idx, int enable)
-{
-	if (enable) {
-		/* Enable comparator interrupt */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |= ADC_VCMP_CMPINTEN;
-		/* Start voltage comparator */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |= ADC_VCMP_CMPEN;
-	} else {
-		/* Stop voltage comparator */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl &= ~ADC_VCMP_CMPEN;
-		/* Disable comparator interrupt */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl &= ~ADC_VCMP_CMPINTEN;
-	}
-}
-
-/* Set voltage comparator conditions */
-void set_voltage_comparator_condition(int idx)
-{
-	int val;
-
-	/* CMPXTHRDAT[9:0] = threshold(mv) * 1024 / 3000(mv) */
-	val = vcmp_list[idx].threshold * VCMP_RESOLUTION / VCMP_MAX_MVOLT;
-	*vcmp_ctrl_regs[idx].vcmp_datl = (uint8_t)(val & 0xff);
-	*vcmp_ctrl_regs[idx].vcmp_datm = (uint8_t)((val >> 8) & 0xff);
-
-	/* Select greater or less equal than threshold */
-	if (vcmp_list[idx].flag & GREATER_THRESHOLD)
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |= ADC_VCMP_GREATER_THRESHOLD;
-	else
-		*vcmp_ctrl_regs[idx].vcmp_ctrl &= ~ADC_VCMP_GREATER_THRESHOLD;
-}
-
-/* Voltage comparator interrupt, handle one channel at a time. */
-void voltage_comparator_interrupt(void)
-{
-	int idx, status;
-
-	/* Find out which voltage comparator triggered */
-	status = IT83XX_ADC_VCMPSTS & 0x07;
-	status |= (IT83XX_ADC_VCMPSTS2 & 0x07) << 3;
-
-	for (idx = CHIP_VCMP0; idx < VCMP_COUNT; idx++) {
-		if (status & BIT(idx)) {
-			/* Called back to board-level function */
-			if (vcmp_list[idx].vcmp_thresh_cb)
-				vcmp_list[idx].vcmp_thresh_cb();
-			/* Clear voltage comparator interrupt status */
-			clear_vcmp_status(idx);
-		}
-	}
-
-	/* Clear interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_V_COMP);
-}
-
-/* Voltage comparator initialization */
-static void voltage_comparator_init(void)
-{
-	int idx;
-
-	/* No voltage comparator is declared */
-	if (!VCMP_COUNT)
-		return;
-
-	for (idx = CHIP_VCMP0; idx < VCMP_COUNT; idx++) {
-		/*
-		 * Select voltage comparator:
-		 * vcmp_list[i] use voltage comparator i, i = 0 ~ 5.
-		 */
-
-		/* Select which ADC channel output voltage into comparator */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |=
-			vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_L;
-		if (vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_H)
-			*vcmp_ctrl_regs[idx].vcmp_adc_chm |= ADC_VCMP_VCMPCSELM;
-
-		/* Set "all voltage comparator" scan period */
-		IT83XX_ADC_VCMPSCP = vcmp_list[idx].scan_period;
-		/* Set voltage comparator conditions */
-		set_voltage_comparator_condition(idx);
-		/* Clear voltage comparator interrupt status */
-		clear_vcmp_status(idx);
-		/* Enable comparator interrupt and start */
-		vcmp_enable(idx, 1);
-	}
-
-	/* Clear interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_V_COMP);
-	/* Enable voltage comparator to interrupt MCU */
-	task_enable_irq(IT83XX_IRQ_V_COMP);
-}
-#endif
-
-/*
- * ADC analog accuracy initialization (only once after VSTBY power on)
- *
- * Write 1 to this bit and write 0 to this bit immediately once and
- * only once during the firmware initialization and do not write 1 again
- * after initialization since IT83xx takes much power consumption
- * if this bit is set as 1
- */
-static void adc_accuracy_initialization(void)
-{
-	/* bit3 : start adc accuracy initialization */
-	IT83XX_ADC_ADCSTS |= 0x08;
-	/* Enable automatic HW calibration. */
-	IT83XX_ADC_KDCTL |= IT83XX_ADC_AHCE;
-	/* short delay for adc accuracy initialization */
-	IT83XX_GCTRL_WNCKR = 0;
-	/* bit3 : stop adc accuracy initialization */
-	IT83XX_ADC_ADCSTS &= ~0x08;
-}
-
-/* ADC module Initialization */
-static void adc_init(void)
-{
-	/* ADC analog accuracy initialization */
-	adc_accuracy_initialization();
-
-	/* Enable alternate function */
-	gpio_config_module(MODULE_ADC, 1);
-	/*
-	 * bit7@ADCSTS     : ADCCTS1 = 0
-	 * bit5@ADCCFG     : ADCCTS0 = 0
-	 * bit[5-0]@ADCCTL : SCLKDIV
-	 * The ADC channel conversion time is 30.8*(SCLKDIV+1) us.
-	 * (Current setting is 61.6us)
-	 *
-	 * NOTE: A sample time delay (60us) also need to be included in
-	 * conversion time, so the final result is ~= 121.6us.
-	 */
-	IT83XX_ADC_ADCSTS &= ~BIT(7);
-	IT83XX_ADC_ADCCFG &= ~BIT(5);
-	IT83XX_ADC_ADCCTL = 1;
-	/*
-	 * Enable this bit, and data of VCHxDATL/VCHxDATM will be
-	 * kept until data valid is cleared.
-	 */
-	IT83XX_ADC_ADCGCR |= IT83XX_ADC_DBKEN;
-
-	task_waiting = TASK_ID_INVALID;
-	/* disable adc interrupt */
-	task_disable_irq(IT83XX_IRQ_ADC);
-
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-	/*
-	 * Init voltage comparator
-	 * NOTE:ADC channel signal output to voltage comparator,
-	 *      so we need set the channel to ADC alternate mode first.
-	 */
-	voltage_comparator_init();
-#endif
-
-	adc_init_done = 1;
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/it83xx/adc_chip.h b/chip/it83xx/adc_chip.h
deleted file mode 100644
index 15a8e68e94..0000000000
--- a/chip/it83xx/adc_chip.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT83xx ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-#include <stdint.h>
-
-#include "common.h"
-
-/*
- * Maximum time we allow for an ADC conversion.
- * NOTE:
- * Because this setting greater than "SLEEP_SET_HTIMER_DELAY_USEC" in clock.c,
- * so we enabled sleep mask to prevent going in to deep sleep while ADC
- * converting.
- */
-#define ADC_TIMEOUT_US MSEC
-
-/* Minimum and maximum values returned by adc_read_channel(). */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 1023
-#define ADC_MAX_MVOLT 3000
-
-/* List of ADC channels. */
-enum chip_adc_channel {
-	CHIP_ADC_CH0 = 0,
-	CHIP_ADC_CH1,
-	CHIP_ADC_CH2,
-	CHIP_ADC_CH3,
-	CHIP_ADC_CH4,
-	CHIP_ADC_CH5,
-	CHIP_ADC_CH6,
-	CHIP_ADC_CH7,
-	CHIP_ADC_CH13,
-	CHIP_ADC_CH14,
-	CHIP_ADC_CH15,
-	CHIP_ADC_CH16,
-	CHIP_ADC_COUNT,
-};
-
-/* List of voltage comparator. */
-enum chip_vcmp {
-	CHIP_VCMP0 = 0,
-	CHIP_VCMP1,
-	CHIP_VCMP2,
-	CHIP_VCMP3,
-	CHIP_VCMP4,
-	CHIP_VCMP5,
-	CHIP_VCMP_COUNT,
-};
-
-/* List of voltage comparator scan period times. */
-enum vcmp_scan_period {
-	VCMP_SCAN_PERIOD_100US = 0x10,
-	VCMP_SCAN_PERIOD_200US = 0x20,
-	VCMP_SCAN_PERIOD_400US = 0x30,
-	VCMP_SCAN_PERIOD_600US = 0x40,
-	VCMP_SCAN_PERIOD_800US = 0x50,
-	VCMP_SCAN_PERIOD_1MS   = 0x60,
-	VCMP_SCAN_PERIOD_1_5MS = 0x70,
-	VCMP_SCAN_PERIOD_2MS   = 0x80,
-	VCMP_SCAN_PERIOD_2_5MS = 0x90,
-	VCMP_SCAN_PERIOD_3MS   = 0xA0,
-	VCMP_SCAN_PERIOD_4MS   = 0xB0,
-	VCMP_SCAN_PERIOD_5MS   = 0xC0,
-};
-
-/* Data structure to define ADC channel control registers. */
-struct adc_ctrl_t {
-	volatile uint8_t *adc_ctrl;
-	volatile uint8_t *adc_datm;
-	volatile uint8_t *adc_datl;
-};
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	enum chip_adc_channel channel;
-};
-
-/* Data structure to define voltage comparator control registers. */
-struct vcmp_ctrl_t {
-	volatile uint8_t *vcmp_ctrl;
-	volatile uint8_t *vcmp_adc_chm;
-	volatile uint8_t *vcmp_datm;
-	volatile uint8_t *vcmp_datl;
-};
-
-/* supported flags (member "flag" in struct vcmp_t) for voltage comparator */
-#define GREATER_THRESHOLD         BIT(0)
-#define LESS_EQUAL_THRESHOLD      BIT(1)
-
-/* Data structure for board to define voltage comparator list. */
-struct vcmp_t {
-	const char *name;
-	int threshold;
-	/*
-	 * Select greater/less equal threshold.
-	 * NOTE: once edge trigger interrupt fires, we need disable the voltage
-	 *       comparator, or the matching threshold level will infinitely
-	 *       triggers interrupt.
-	 */
-	char flag;
-	/* Called when the interrupt fires */
-	void (*vcmp_thresh_cb)(void);
-	/*
-	 * Select "all voltage comparator" scan period time.
-	 * The power consumption is positively relative with scan frequency.
-	 */
-	enum vcmp_scan_period scan_period;
-	/*
-	 * Select which ADC channel output voltage into comparator and we
-	 * should set the ADC channel pin in alternate mode via adc_channels[].
-	 */
-	enum chip_adc_channel adc_ch;
-};
-
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-/*
- * Boards must provide this list of voltage comparator definitions.
- * This must match the enum board_vcmp list provided by the board.
- */
-extern const struct vcmp_t vcmp_list[];
-#endif
-void vcmp_enable(int index, int enable);
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk
deleted file mode 100644
index bbff9f009b..0000000000
--- a/chip/it83xx/build.mk
+++ /dev/null
@@ -1,40 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# IT83xx chip specific files build
-#
-
-# IT8xxx1 and IT83xx are Andes N8 core.
-# IT8xxx2 is RISC-V core.
-ifeq ($(CHIP_FAMILY), it8xxx2)
-CORE:=riscv-rv32i
-else
-CORE:=nds32
-endif
-
-# Required chip modules
-chip-y=hwtimer.o uart.o gpio.o system.o clock.o irq.o intc.o
-
-# Optional chip modules
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-chip-$(CONFIG_FANS)+=fan.o pwm.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-# IT8xxx2 series use the FPU instruction set of RISC-V (single-precision only).
-ifneq ($(CHIP_FAMILY), it8xxx2)
-chip-$(CONFIG_FPU)+=it83xx_fpu.o
-endif
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_DAC)+=dac.o
-chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
-chip-$(CONFIG_SPI_CONTROLLER)+=spi_master.o
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_PECI)+=peci.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-chip-$(CONFIG_I2C_CONTROLLER)+=i2c.o
-chip-$(CONFIG_I2C_PERIPHERAL)+=i2c_peripheral.o
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
deleted file mode 100644
index 41f800721a..0000000000
--- a/chip/it83xx/clock.c
+++ /dev/null
@@ -1,701 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "adc_chip.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "intc.h"
-#include "irq_chip.h"
-#include "it83xx_pd.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros. */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#ifdef CONFIG_LOW_POWER_IDLE
-#define SLEEP_SET_HTIMER_DELAY_USEC 250
-#define SLEEP_FTIMER_SKIP_USEC      (HOOK_TICK_INTERVAL * 2)
-
-static timestamp_t sleep_mode_t0;
-static timestamp_t sleep_mode_t1;
-static int idle_doze_cnt;
-static int idle_sleep_cnt;
-static uint64_t total_idle_sleep_time_us;
-static uint32_t ec_sleep;
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the heavy sleep mode is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-static int console_in_use_timeout_sec = 5;
-static timestamp_t console_expire_time;
-
-/* clock source is 32.768KHz */
-#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt) * 1000000 / 32768)
-#define TIMER_CNT_8M_32P768K(cnt)    (((cnt) / (8000000 / 32768)) + 1)
-#endif /*CONFIG_LOW_POWER_IDLE */
-
-static int freq;
-
-struct clock_gate_ctrl {
-	volatile uint8_t *reg;
-	uint8_t mask;
-};
-
-static void clock_module_disable(void)
-{
-	/* bit0: FSPI interface tri-state */
-	IT83XX_SMFI_FLHCTRL3R |= BIT(0);
-	/* bit7: USB pad power-on disable */
-	IT83XX_GCTRL_PMER2 &= ~BIT(7);
-	/* bit7: USB debug disable */
-	IT83XX_GCTRL_MCCR &= ~BIT(7);
-	clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0);
-	clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB |
-		CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE |
-		CGC_OFFSET_SMBF), 0, 0);
-	clock_disable_peripheral((CGC_OFFSET_SSPI | CGC_OFFSET_PECI |
-		CGC_OFFSET_USB), 0, 0);
-}
-
-enum pll_freq_idx {
-	PLL_24_MHZ = 1,
-	PLL_48_MHZ = 2,
-	PLL_96_MHZ = 4,
-};
-
-static const uint8_t pll_to_idx[8] = {
-	0,
-	0,
-	PLL_24_MHZ,
-	0,
-	PLL_48_MHZ,
-	0,
-	0,
-	PLL_96_MHZ
-};
-
-struct clock_pll_t {
-	int     pll_freq;
-	uint8_t pll_setting;
-	uint8_t div_fnd;
-	uint8_t div_uart;
-	uint8_t div_usb;
-	uint8_t div_smb;
-	uint8_t div_sspi;
-	uint8_t div_ec;
-	uint8_t div_jtag;
-	uint8_t div_pwm;
-	uint8_t div_usbpd;
-};
-
-const struct clock_pll_t clock_pll_ctrl[] = {
-	/*
-	 * UART:  24MHz
-	 * SMB:   24MHz
-	 * EC:     8MHz
-	 * JTAG:  24MHz
-	 * USBPD:  8MHz
-	 * USB:   48MHz(no support if PLL=24MHz)
-	 * SSPI:  48MHz(24MHz if PLL=24MHz)
-	 */
-	/* PLL:24MHz, MCU:24MHz, Fnd(e-flash):24MHz */
-	[PLL_24_MHZ] = {24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2},
-#ifdef CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-	/* PLL:48MHz, MCU:48MHz, Fnd:48MHz */
-	[PLL_48_MHZ] = {48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5},
-	/* PLL:96MHz, MCU:96MHz, Fnd:48MHz */
-	[PLL_96_MHZ] = {96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb},
-#else
-	/* PLL:48MHz, MCU:48MHz, Fnd:24MHz */
-	[PLL_48_MHZ] = {48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5},
-	/* PLL:96MHz, MCU:96MHz, Fnd:32MHz */
-	[PLL_96_MHZ] = {96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb},
-#endif
-};
-
-static uint8_t pll_div_fnd;
-static uint8_t pll_div_ec;
-static uint8_t pll_div_jtag;
-static uint8_t pll_setting;
-
-void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode)
-{
-	volatile uint8_t _pll_ctrl __unused;
-
-	IT83XX_ECPM_PLLCTRL = mode;
-	/*
-	 * for deep doze / sleep mode
-	 * This load operation will ensure PLL setting is taken into
-	 * control register before wait for interrupt instruction.
-	 */
-	_pll_ctrl = IT83XX_ECPM_PLLCTRL;
-
-#ifdef IT83XX_CHIP_FLASH_NO_DEEP_POWER_DOWN
-	/*
-	 * WORKAROUND: this workaround is used to fix EC gets stuck in low power
-	 * mode when WRST# is asserted.
-	 *
-	 * By default, flash will go into deep power down mode automatically
-	 * when EC is in low power mode. But we got an issue on IT83202BX that
-	 * flash won't be able to wake up correctly when WRST# is asserted
-	 * under this condition.
-	 * This issue might cause cold reset failure so we fix it.
-	 *
-	 * NOTE: this fix will increase power number about 40uA in low power
-	 * mode.
-	 */
-	if (mode == EC_PLL_DOZE)
-		IT83XX_SMFI_SMECCS &= ~IT83XX_SMFI_MASK_HOSTWA;
-	else
-		/*
-		 * Don't send deep power down mode command to flash when EC in
-		 * low power mode.
-		 */
-		IT83XX_SMFI_SMECCS |= IT83XX_SMFI_MASK_HOSTWA;
-#endif
-	/*
-	 * barrier: ensure low power mode setting is taken into control
-	 * register before standby instruction.
-	 */
-	data_serialization_barrier();
-}
-
-void __ram_code clock_pll_changed(void)
-{
-	IT83XX_GCTRL_SSCR &= ~BIT(0);
-	/*
-	 * Update PLL settings.
-	 * Writing data to this register doesn't change the
-	 * PLL frequency immediately until the status is changed
-	 * into wakeup from the sleep mode.
-	 * The following code is intended to make the system
-	 * enter sleep mode, and set up a HW timer to wakeup EC to
-	 * complete PLL update.
-	 */
-	IT83XX_ECPM_PLLFREQR = pll_setting;
-	/* Pre-set FND clock frequency = PLL / 3 */
-	IT83XX_ECPM_SCDCR0 = (2 << 4);
-	/* JTAG and EC */
-	IT83XX_ECPM_SCDCR3 = (pll_div_jtag << 4) | pll_div_ec;
-	/* EC sleep after standby instruction */
-	clock_ec_pll_ctrl(EC_PLL_SLEEP);
-	if (IS_ENABLED(CHIP_CORE_NDS32)) {
-		/* Global interrupt enable */
-		asm volatile ("setgie.e");
-		/* EC sleep */
-		asm("standby wake_grant");
-		/* Global interrupt disable */
-		asm volatile ("setgie.d");
-	} else if (IS_ENABLED(CHIP_CORE_RISCV)) {
-		/* Global interrupt enable */
-		asm volatile ("csrsi mstatus, 0x8");
-		/* EC sleep */
-		asm("wfi");
-		/* Global interrupt disable */
-		asm volatile ("csrci mstatus, 0x8");
-	}
-	/* New FND clock frequency */
-	IT83XX_ECPM_SCDCR0 = (pll_div_fnd << 4);
-	/* EC doze after standby instruction */
-	clock_ec_pll_ctrl(EC_PLL_DOZE);
-}
-
-/* NOTE: Don't use this function in other place. */
-static void clock_set_pll(enum pll_freq_idx idx)
-{
-	int pll;
-
-	pll_div_fnd  = clock_pll_ctrl[idx].div_fnd;
-	pll_div_ec   = clock_pll_ctrl[idx].div_ec;
-	pll_div_jtag = clock_pll_ctrl[idx].div_jtag;
-	pll_setting  = clock_pll_ctrl[idx].pll_setting;
-
-	/* Update PLL settings or not */
-	if (((IT83XX_ECPM_PLLFREQR & 0xf) != pll_setting) ||
-		((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) ||
-		((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) {
-		/* Enable hw timer to wakeup EC from the sleep mode */
-		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
-				1, 1, 5, 1, 0);
-		task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
-#ifdef CONFIG_HOSTCMD_ESPI
-		/*
-		 * Workaround for (b:70537592):
-		 * We have to set chip select pin as input mode in order to
-		 * change PLL.
-		 */
-		IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | BIT(7);
-#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-		/*
-		 * On DX version, we have to disable eSPI pad before changing
-		 * PLL sequence or sequence will fail if CS# pin is low.
-		 */
-		espi_enable_pad(0);
-#endif
-#endif
-		/* Update PLL settings. */
-		clock_pll_changed();
-#ifdef CONFIG_HOSTCMD_ESPI
-#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-		/* Enable eSPI pad after changing PLL sequence. */
-		espi_enable_pad(1);
-#endif
-		/* (b:70537592) Change back to ESPI CS# function. */
-		IT83XX_GPIO_GPCRM5 &= ~0xc0;
-#endif
-	}
-
-	/* Get new/current setting of PLL frequency */
-	pll = pll_to_idx[IT83XX_ECPM_PLLFREQR & 0xf];
-	/* USB and UART */
-	IT83XX_ECPM_SCDCR1 = (clock_pll_ctrl[pll].div_usb << 4) |
-				clock_pll_ctrl[pll].div_uart;
-	/* SSPI and SMB */
-	IT83XX_ECPM_SCDCR2 = (clock_pll_ctrl[pll].div_sspi << 4) |
-				clock_pll_ctrl[pll].div_smb;
-	/* USBPD and PWM */
-	IT83XX_ECPM_SCDCR4 = (clock_pll_ctrl[pll].div_usbpd << 4) |
-				clock_pll_ctrl[pll].div_pwm;
-	/* Current PLL frequency  */
-	freq = clock_pll_ctrl[pll].pll_freq;
-}
-
-void clock_init(void)
-{
-	uint32_t image_type = (uint32_t)clock_init;
-
-	/* To change interrupt vector base if at RW image */
-	if (image_type > CONFIG_RW_MEM_OFF)
-		/* Interrupt Vector Table Base Address, in 64k Byte unit */
-		IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF;
-
-#if (PLL_CLOCK == 24000000)     || \
-	(PLL_CLOCK == 48000000) || \
-	(PLL_CLOCK == 96000000)
-	/* Set PLL frequency */
-	clock_set_pll(PLL_CLOCK / 24000000);
-#else
-#error "Support only for PLL clock speed of 24/48/96MHz."
-#endif
-	/*
-	 * The VCC power status is treated as power-on.
-	 * The VCC supply of LPC and related functions (EC2I,
-	 * KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI).
-	 * It means VCC (pin 11) should be logic high before using
-	 * these functions, or firmware treats VCC logic high
-	 * as following setting.
-	 */
-	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40;
-
-#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI)
-	/*
-	 * Because we don't support eSPI HW reset function (b/111480168) on DX
-	 * version, so we have to reset eSPI configurations during init to
-	 * ensure Host and EC are synchronized (especially for the field of
-	 * I/O mode)
-	 */
-	if (!system_jumped_to_this_image())
-		espi_fw_reset_module();
-#endif
-	/* Turn off auto clock gating. */
-	IT83XX_ECPM_AUTOCG = 0x00;
-
-	/* Default doze mode */
-	clock_ec_pll_ctrl(EC_PLL_DOZE);
-
-	clock_module_disable();
-
-#ifdef CONFIG_HOSTCMD_X86
-	IT83XX_WUC_WUESR4 = BIT(2);
-	task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
-	/* bit2, wake-up enable for LPC access */
-	IT83XX_WUC_WUENR4 |= BIT(2);
-#endif
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-/**
- * Enable clock to specified peripheral
- *
- * @param offset Should be element of clock_gate_offsets enum.
- *               Bits 8-15 specify the ECPM offset of the specific clock reg.
- *               Bits 0-7 specify the mask for the clock register.
- * @param mask   Unused
- * @param mode   Unused
- */
-void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	volatile uint8_t *reg = (volatile uint8_t *)
-			(IT83XX_ECPM_BASE + (offset >> 8));
-	uint8_t reg_mask = offset & 0xff;
-
-	/*
-	 * Note: CGCTRL3R, bit 6, must always write 1, but since there is no
-	 * offset argument that addresses this bit, then we are guaranteed
-	 * that this line will write a 1 to that bit.
-	 */
-	*reg &= ~reg_mask;
-}
-
-/**
- * Disable clock to specified peripheral
- *
- * @param offset Should be element of clock_gate_offsets enum.
- *               Bits 8-15 specify the ECPM offset of the specific clock reg.
- *               Bits 0-7 specify the mask for the clock register.
- * @param mask   Unused
- * @param mode   Unused
- */
-void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	volatile uint8_t *reg = (volatile uint8_t *)
-			(IT83XX_ECPM_BASE + (offset >> 8));
-	uint8_t reg_mask = offset & 0xff;
-	uint8_t tmp_mask = 0;
-
-	/* CGCTRL3R, bit 6, must always write a 1. */
-	tmp_mask |= ((offset >> 8) == IT83XX_ECPM_CGCTRL3R_OFF) ? 0x40 : 0x00;
-
-	*reg |= reg_mask | tmp_mask;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void clock_refresh_console_in_use(void)
-{
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-}
-
-static void clock_event_timer_clock_change(enum ext_timer_clock_source clock,
-					uint32_t count)
-{
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
-	IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock;
-	IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = count;
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x3;
-}
-
-static void clock_htimer_enable(void)
-{
-	uint32_t c;
-
-	/* change event timer clock source to 32.768 KHz */
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-	c = TIMER_CNT_8M_32P768K(ext_observation_reg_read(EVENT_EXT_TIMER));
-#else
-	c = TIMER_CNT_8M_32P768K(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER));
-#endif
-	clock_event_timer_clock_change(EXT_PSR_32P768K_HZ, c);
-}
-
-static int clock_allow_low_power_idle(void)
-{
-	/*
-	 * Avoiding using low frequency clock run the same count as awaken in
-	 * sleep mode, so don't go to sleep mode before timer reload count.
-	 */
-	if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)))
-		return 0;
-
-	/* If timer interrupt status is set, don't go to sleep mode. */
-	if (*et_ctrl_regs[EVENT_EXT_TIMER].isr &
-		et_ctrl_regs[EVENT_EXT_TIMER].mask)
-		return 0;
-
-	/*
-	 * If timer is less than 250us to expire, then we don't go to sleep
-	 * mode.
-	 */
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-	if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) <
-#else
-	if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) <
-#endif
-		SLEEP_SET_HTIMER_DELAY_USEC)
-		return 0;
-
-	/*
-	 * We calculate 32bit free clock overflow counts for 64bit value,
-	 * if clock almost reach overflow, we don't go to sleep mode for
-	 * avoiding miss overflow count.
-	 */
-	sleep_mode_t0 = get_time();
-	if ((sleep_mode_t0.le.lo > (0xffffffff - SLEEP_FTIMER_SKIP_USEC)) ||
-		(sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC))
-		return 0;
-
-	/* If we are waked up by console, then keep awake at least 5s. */
-	if (sleep_mode_t0.val < console_expire_time.val)
-		return 0;
-
-	return 1;
-}
-
-int clock_ec_wake_from_sleep(void)
-{
-	return ec_sleep;
-}
-
-void __ram_code clock_cpu_standby(void)
-{
-	/* standby instruction */
-	if (IS_ENABLED(CHIP_CORE_NDS32)) {
-		asm("standby wake_grant");
-	} else if (IS_ENABLED(CHIP_CORE_RISCV)) {
-		if (!IS_ENABLED(IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED))
-			/*
-			 * we have to enable interrupts before
-			 * standby instruction on IT83202 bx version.
-			 */
-			interrupt_enable();
-
-		asm("wfi");
-	}
-}
-
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-
-	/* disable all interrupts */
-	interrupt_disable();
-	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
-		chip_disable_irq(i);
-		chip_clear_pending_irq(i);
-	}
-	/* bit5: watchdog is disabled. */
-	IT83XX_ETWD_ETWCTRL |= BIT(5);
-
-	/*
-	 * Setup GPIOs for hibernate.  On some boards, it's possible that this
-	 * may not return at all.  On those boards, power to the EC is likely
-	 * being turn off entirely.
-	 */
-	if (board_hibernate_late) {
-		/*
-		 * Set reset flag in case board_hibernate_late() doesn't
-		 * return.
-		 */
-		chip_save_reset_flags(EC_RESET_FLAG_HIBERNATE);
-		board_hibernate_late();
-	}
-
-	if (seconds || microseconds) {
-		/* At least 1 ms for hibernate. */
-		uint64_t c = (seconds * 1000 + microseconds / 1000 + 1) * 1024;
-
-		uint64divmod(&c, 1000);
-		/* enable a 56-bit timer and clock source is 1.024 KHz */
-		ext_timer_stop(FREE_EXT_TIMER_L, 1);
-		ext_timer_stop(FREE_EXT_TIMER_H, 1);
-		IT83XX_ETWD_ETXPSR(FREE_EXT_TIMER_L) = EXT_PSR_1P024K_HZ;
-		IT83XX_ETWD_ETXPSR(FREE_EXT_TIMER_H) = EXT_PSR_1P024K_HZ;
-		IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_L) = c & 0xffffff;
-		IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = (c >> 24) & 0xffffffff;
-		ext_timer_start(FREE_EXT_TIMER_H, 1);
-		ext_timer_start(FREE_EXT_TIMER_L, 0);
-	}
-
-	if (IS_ENABLED(CONFIG_USB_PD_TCPM_ITE_ON_CHIP)) {
-		/*
-		 * Disable active cc and pd modules and only left Rd_5.1k (Not
-		 * Rd_DB) alive in hibernate for better power consumption.
-		 */
-		for (i = 0; i < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT; i++)
-			it83xx_Rd_5_1K_only_for_hibernate(i);
-	}
-
-	if (IS_ENABLED(CONFIG_ADC_VOLTAGE_COMPARATOR)) {
-		/*
-		 * Disable all voltage comparator modules in hibernate
-		 * for better power consumption.
-		 */
-		for (i = CHIP_VCMP0; i < CHIP_VCMP_COUNT; i++)
-			vcmp_enable(i, 0);
-	}
-
-	for (i = 0; i < hibernate_wake_pins_used; ++i)
-		gpio_enable_interrupt(hibernate_wake_pins[i]);
-
-	/* EC sleep */
-	ec_sleep = 1;
-#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
-	/* Disable eSPI pad. */
-	espi_enable_pad(0);
-#endif
-	clock_ec_pll_ctrl(EC_PLL_SLEEP);
-	interrupt_enable();
-	/* standby instruction */
-	clock_cpu_standby();
-
-	/* we should never reach that point */
-	__builtin_unreachable();
-}
-
-/* use data type int here not bool to get better instruction number. */
-static volatile int wait_interrupt_fired;
-void clock_sleep_mode_wakeup_isr(void)
-{
-	uint32_t st_us, c;
-
-	/* Clear flag on each interrupt. */
-	if (IS_ENABLED(CHIP_CORE_RISCV))
-		wait_interrupt_fired = 0;
-
-	/* trigger a reboot if wake up EC from sleep mode (system hibernate) */
-	if (clock_ec_wake_from_sleep()) {
-#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
-		/*
-		 * Enable eSPI pad.
-		 * We will not need to enable eSPI pad here if Dx is able to
-		 * enable watchdog hardware reset function. But the function is
-		 * failed (b:111264984), so the following system reset is
-		 * software reset (PLL setting is not reset).
-		 * We will not go into the change PLL sequence on reboot if PLL
-		 * setting is the same, so the operation of enabling eSPI pad we
-		 * added in clock_set_pll() will not be applied.
-		 */
-		espi_enable_pad(1);
-#endif
-		system_reset(SYSTEM_RESET_HARD);
-	}
-
-	if (IT83XX_ECPM_PLLCTRL == EC_PLL_DEEP_DOZE) {
-		clock_ec_pll_ctrl(EC_PLL_DOZE);
-		/* update free running timer */
-		c = LOW_POWER_TIMER_MASK -
-			IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER);
-		st_us = TIMER_32P768K_CNT_TO_US(c);
-		sleep_mode_t1.val = sleep_mode_t0.val + st_us;
-		__hw_clock_source_set(sleep_mode_t1.le.lo);
-
-		/* reset event timer and clock source is 8 MHz */
-		clock_event_timer_clock_change(EXT_PSR_8M_HZ, 0xffffffff);
-		task_clear_pending_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
-		process_timers(0);
-#ifdef CONFIG_HOSTCMD_X86
-		/* disable lpc access wui */
-		task_disable_irq(IT83XX_IRQ_WKINTAD);
-		IT83XX_WUC_WUESR4 = BIT(2);
-		task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
-#endif
-		/* disable uart wui */
-		uart_exit_dsleep();
-		/* Record time spent in sleep. */
-		total_idle_sleep_time_us += st_us;
-	}
-}
-
-void __keep __idle_init(void)
-{
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-	/* init hw timer and clock source is 32.768 KHz */
-	ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0,
-		0xffffffff, 1, 1);
-
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	CPRINTS("low power idle task started");
-}
-
-/**
- * Low power idle task. Executed when no tasks are ready to be scheduled.
- */
-void __ram_code __idle(void)
-{
-	/*
-	 * There is not enough space from ram code section to cache entire idle
-	 * function, hence pull initialization function out of the section.
-	 */
-	__idle_init();
-
-	while (1) {
-		/* Disable interrupts */
-		interrupt_disable();
-		/* Check if the EC can enter deep doze mode or not */
-		if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) {
-			/* reset low power mode hw timer */
-			IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= BIT(1);
-			sleep_mode_t0 = get_time();
-#ifdef CONFIG_HOSTCMD_X86
-			/* enable lpc access wui */
-			task_enable_irq(IT83XX_IRQ_WKINTAD);
-#endif
-			/* enable uart wui */
-			uart_enter_dsleep();
-			/* enable hw timer for deep doze / sleep mode wake-up */
-			clock_htimer_enable();
-			/* deep doze mode */
-			clock_ec_pll_ctrl(EC_PLL_DEEP_DOZE);
-			idle_sleep_cnt++;
-		} else {
-			/* doze mode */
-			clock_ec_pll_ctrl(EC_PLL_DOZE);
-			idle_doze_cnt++;
-		}
-		/* Set flag before entering low power mode. */
-		if (IS_ENABLED(CHIP_CORE_RISCV))
-			wait_interrupt_fired = 1;
-		clock_cpu_standby();
-		interrupt_enable();
-		/*
-		 * Sometimes wfi instruction may fail due to CPU's MTIP@mip
-		 * register is non-zero.
-		 * If the wait_interrupt_fired flag is true at this point,
-		 * it means that EC waked-up by the above issue not an
-		 * interrupt. Hence we loop running wfi instruction here until
-		 * wfi success.
-		 */
-		while (IS_ENABLED(CHIP_CORE_RISCV) && wait_interrupt_fired)
-			clock_cpu_standby();
-	}
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-#ifdef CONFIG_LOW_POWER_IDLE
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that doze:            %d\n", idle_doze_cnt);
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-
-	ccprintf("Total Time spent in sleep(sec):      %.6lld(s)\n",
-						total_idle_sleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-
-#endif /* CONFIG_CMD_IDLE_STATS */
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
deleted file mode 100644
index 2f552c794a..0000000000
--- a/chip/it83xx/config_chip.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
-#include "config_chip_it8320.h"
-#elif defined(CHIP_FAMILY_IT8XXX2) /* RISCV core */
-#include "config_chip_it8xxx2.h"
-#else
-#error "Unsupported chip family!"
-#endif
-
-/* Number of IRQ vectors on the IVIC */
-#define CONFIG_IRQ_COUNT IT83XX_IRQ_COUNT
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Default PLL frequency. */
-#define PLL_CLOCK 48000000
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 6
-
-/* I2C ports on chip
- * IT83xx - There are three i2c standard ports.
- *          There are three i2c enhanced ports.
- */
-#define I2C_STANDARD_PORT_COUNT 3
-#define I2C_ENHANCED_PORT_COUNT 3
-
-/* System stack size */
-#define CONFIG_STACK_SIZE           1024
-
-/* non-standard task stack sizes */
-#define SMALLER_TASK_STACK_SIZE     (384 + CHIP_EXTRA_STACK_SPACE)
-#define IDLE_TASK_STACK_SIZE        (512 + CHIP_EXTRA_STACK_SPACE)
-#define LARGER_TASK_STACK_SIZE      (768 + CHIP_EXTRA_STACK_SPACE)
-#define VENTI_TASK_STACK_SIZE       (896 + CHIP_EXTRA_STACK_SPACE)
-#define ULTRA_TASK_STACK_SIZE       (1056 + CHIP_EXTRA_STACK_SPACE)
-#define TRENTA_TASK_STACK_SIZE      (1184 + CHIP_EXTRA_STACK_SPACE)
-
-/* Default task stack size */
-#define TASK_STACK_SIZE             (512 + CHIP_EXTRA_STACK_SPACE)
-
-#ifdef IT83XX_CHIP_FLASH_IS_KGD
-#define CONFIG_FLASH_BANK_SIZE      0x00001000  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00001000  /* erase bank size */
-#else
-#define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
-#endif
-#define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
-
-/*
- * This is the block size of the ILM on the it83xx chip.
- * The ILM for static code cache, CPU fetch instruction from
- * ILM(ILM -> CPU)instead of flash(flash -> IMMU -> CPU) if enabled.
- */
-#define IT83XX_ILM_BLOCK_SIZE       0x00001000
-
-#ifdef IT83XX_CHIP_FLASH_IS_KGD
-/*
- * One page program instruction allows maximum 256 bytes (a page) of data
- * to be programmed.
- */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
-#else
-/*
- * The AAI program instruction allows continue write flash
- * until write disable instruction.
- */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_ERASE_SIZE
-#endif
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/****************************************************************************/
-/* H2RAM memory mapping */
-
-/*
- * Only it839x series and IT838x DX support mapping LPC I/O cycle 800h ~ 9FFh
- * to 0x8D800h ~ 0x8D9FFh of DLM13.
- *
- * IT8xxx2 series support mapping LPC/eSPI I/O cycle 800h ~ 9FFh
- * to 0x80081800 ~ 0x800819FF of DLM1.
- */
-#define CONFIG_H2RAM_BASE               (CHIP_H2RAM_BASE)
-#define CONFIG_H2RAM_SIZE               0x00001000
-#define CONFIG_H2RAM_HOST_LPC_IO_BASE   0x800
-
-/****************************************************************************/
-/* Customize the build */
-
-#define CONFIG_FW_RESET_VECTOR
-
-/* Optional features present on this chip */
-#define CHIP_FAMILY_IT83XX
-#define CONFIG_ADC
-#define CONFIG_SWITCH
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#define __RAM_CODE_SECTION_NAME ".ram_code"
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h
deleted file mode 100644
index 53f4a1cbd3..0000000000
--- a/chip/it83xx/config_chip_it8320.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_IT8320_H
-#define __CROS_EC_CONFIG_CHIP_IT8320_H
-
-/* CPU core BFD configuration */
-#include "core/nds32/config_core.h"
-
-/* N8 core */
-#define CHIP_CORE_NDS32
-/* The base address of EC interrupt controller registers. */
-#define CHIP_EC_INTC_BASE           0x00F01100
-
-/****************************************************************************/
-/* Memory mapping */
-
-#define CHIP_H2RAM_BASE             0x0008D000 /* 0x0008D000~0x0008DFFF */
-#define CHIP_RAMCODE_BASE           0x0008E000 /* 0x0008E000~0x0008EFFF */
-#define CHIP_EXTRA_STACK_SPACE      0
-
-#define CONFIG_RAM_BASE             0x00080000
-#define CONFIG_RAM_SIZE             0x0000C000
-
-#define CONFIG_PROGRAM_MEMORY_BASE  0x00000000
-
-/****************************************************************************/
-/* Chip IT8320 is used with IT83XX TCPM driver */
-#define CONFIG_USB_PD_TCPM_DRIVER_IT83XX
-
-#if defined(CHIP_VARIANT_IT8320BX)
-/* This is the physical size of the flash on the chip. We'll reserve one bank
- * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
- * doesn't support a write-protect pin, and if we make the write-protection
- * permanent, it can't be undone easily enough to support RMA.
- */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000
-/* For IT8320BX, we have to reload cc parameters after ec softreset. */
-#define IT83XX_USBPD_CC_PARAMETER_RELOAD
-/*
- * The voltage detector of CC1 and CC2 is enabled/disabled by different bit
- * of the control register (bit1 and bit5 at register IT83XX_USBPD_CCCSR).
- */
-#define IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
-/* Chip IT8320BX actually has TCPC physical port count */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
-/* For IT8320BX, we have to write 0xff to clear pending bit.*/
-#define IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR
-/* For IT8320BX, we have to read observation register of external timer two
- * times to get correct time.
- */
-#define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-#elif defined(CHIP_VARIANT_IT8320DX)
-#define CONFIG_FLASH_SIZE_BYTES  0x00080000
-#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-/*
- * Disable eSPI pad, then PLL change
- * (include EC clock frequency) is succeed even CS# is low.
- */
-#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/*
- * The peripheral frequency is adjustable
- * (bit[2-0] at register IT83XX_ESPI_GCAC1)
- */
-#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
-/*
- * TODO(b/111480168): eSPI HW reset can't be used because the DMA address
- * gets set incorrectly resulting in a memory access exception.
- */
-#define IT83XX_ESPI_RESET_MODULE_BY_FW
-/* Watchdog reset supports hardware reset. */
-/* TODO(b/111264984): watchdog hardware reset function failed. */
-#undef IT83XX_ETWD_HW_RESET_SUPPORT
-/*
- * (b/112452221):
- * Floating-point multiplication single-precision is failed on DX version,
- * so we use the formula "A/(1/B)" to replace a multiplication operation
- * (A*B = A/(1/B)).
- */
-#define IT83XX_FPU_MUL_BY_DIV
-/*
- * More GPIOs can be set as 1.8v input.
- * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs.
- */
-#define IT83XX_GPIO_1P8V_PIN_EXTENDED
-/* All GPIOs support interrupt on rising, falling, and either edge. */
-#define IT83XX_GPIO_INT_FLEXIBLE
-/* Enable FRS detection interrupt. */
-#define IT83XX_INTC_FAST_SWAP_SUPPORT
-/* Enable interrupts of group 21 and 22. */
-#define IT83XX_INTC_GROUP_21_22_SUPPORT
-/* Enable detect type-c plug in and out interrupt. */
-#define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
-/* Chip Dx transmit status bit of PD register is different from Bx. */
-#define IT83XX_PD_TX_ERROR_STATUS_BIT5
-/* Chip IT8320DX actually has TCPC physical port count */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
-#else
-#error "Unsupported chip variant!"
-#endif
-
-#endif  /* __CROS_EC_CONFIG_CHIP_IT8320_H */
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h
deleted file mode 100644
index a5b4096c8b..0000000000
--- a/chip/it83xx/config_chip_it8xxx2.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_IT8XXX2_H
-#define __CROS_EC_CONFIG_CHIP_IT8XXX2_H
-
-/* CPU core BFD configuration */
-#include "core/riscv-rv32i/config_core.h"
-
-/* RISCV core */
-#define CHIP_CORE_RISCV
-#define CHIP_ILM_DLM_ORDER
-/* The base address of EC interrupt controller registers. */
-#define CHIP_EC_INTC_BASE           0x00F03F00
-#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-/*
- * ILM/DLM size register.
- * bit[3-0] ILM size:
- *     7: 512K byte (default setting), 8: 1M byte
- */
-#define IT83XX_GCTRL_EIDSR 0xf02031
-
-/****************************************************************************/
-/* Memory mapping */
-
-#define CHIP_ILM_BASE               0x80000000
-#define CHIP_EXTRA_STACK_SPACE      128
-/* We reserve 12KB space for ramcode, h2ram, and immu sections. */
-#define CHIP_RAM_SPACE_RESERVED     0x3000
-#define CONFIG_PROGRAM_MEMORY_BASE  (CHIP_ILM_BASE)
-
-/****************************************************************************/
-/* Chip IT83202 is used with IT8XXX2 TCPM driver */
-#define CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
-
-#if defined(CHIP_VARIANT_IT83202BX)
-/* TODO(b/133460224): enable properly chip config option. */
-#define CONFIG_FLASH_SIZE_BYTES           0x00080000
-#define CONFIG_RAM_BASE             0x80080000
-#define CONFIG_RAM_SIZE             0x00010000
-
-/* Embedded flash is KGD */
-#define IT83XX_CHIP_FLASH_IS_KGD
-/* Don't let internal flash go into deep power down mode. */
-#define IT83XX_CHIP_FLASH_NO_DEEP_POWER_DOWN
-/* chip id is 3 bytes */
-#define IT83XX_CHIP_ID_3BYTES
-/*
- * The bit19 of ram code base address is controlled by bit7 of register SCARxH
- * instead of bit3.
- */
-#define IT83XX_DAM_ADDR_BIT19_AT_REG_SCARXH_BIT7
-/*
- * Disable eSPI pad, then PLL change
- * (include EC clock frequency) is succeed even CS# is low.
- */
-#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/*
- * The peripheral frequency is adjustable
- * (bit[2-0] at register IT83XX_ESPI_GCAC1)
- */
-#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
-/* Watchdog reset supports hardware reset. */
-#define IT83XX_ETWD_HW_RESET_SUPPORT
-/*
- * More GPIOs can be set as 1.8v input.
- * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs.
- */
-#define IT83XX_GPIO_1P8V_PIN_EXTENDED
-/* All GPIOs support interrupt on rising, falling, and either edge. */
-#define IT83XX_GPIO_INT_FLEXIBLE
-/* Remap host I/O cycles to base address of H2RAM section. */
-#define IT83XX_H2RAM_REMAPPING
-/* Enable FRS detection interrupt. */
-#define IT83XX_INTC_FAST_SWAP_SUPPORT
-/* Enable detect type-c plug in and out interrupt. */
-#define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
-/* Chip IT83202BX actually has TCPC physical port count. */
-#define IT83XX_USBPD_PHY_PORT_COUNT    3
-#elif defined(CHIP_VARIANT_IT81302AX_1024) \
-|| defined(CHIP_VARIANT_IT81202AX_1024) \
-|| defined(CHIP_VARIANT_IT81302BX_1024) \
-|| defined(CHIP_VARIANT_IT81202BX_1024)
-#define CONFIG_FLASH_SIZE_BYTES           0x00100000
-#define CONFIG_RAM_BASE             0x80100000
-#define CONFIG_RAM_SIZE             0x0000f000
-
-/* Embedded flash is KGD */
-#define IT83XX_CHIP_FLASH_IS_KGD
-/* Set ILM (instruction local memory) size up to 1M bytes */
-#define IT83XX_CHIP_FLASH_SIZE_1MB
-/* chip id is 3 bytes */
-#define IT83XX_CHIP_ID_3BYTES
-/*
- * The bit19 of ram code base address is controlled by bit7 of register SCARxH
- * instead of bit3.
- */
-#define IT83XX_DAM_ADDR_BIT19_AT_REG_SCARXH_BIT7
-/*
- * Disable eSPI pad, then PLL change
- * (include EC clock frequency) is succeed even CS# is low.
- */
-#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/*
- * The peripheral frequency is adjustable
- * (bit[2-0] at register IT83XX_ESPI_GCAC1)
- */
-#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
-/* Watchdog reset supports hardware reset. */
-#define IT83XX_ETWD_HW_RESET_SUPPORT
-/*
- * More GPIOs can be set as 1.8v input.
- * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs.
- */
-#define IT83XX_GPIO_1P8V_PIN_EXTENDED
-#if defined(CHIP_VARIANT_IT81202AX_1024) || defined(CHIP_VARIANT_IT81202BX_1024)
-/* Pins of group K and L are set as internal pull-down at initialization. */
-#define IT83XX_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
-#endif
-/* GPIOH7 is set as output low at initialization. */
-#define IT83XX_GPIO_H7_DEFAULT_OUTPUT_LOW
-/* All GPIOs support interrupt on rising, falling, and either edge. */
-#define IT83XX_GPIO_INT_FLEXIBLE
-/* Remap host I/O cycles to base address of H2RAM section. */
-#define IT83XX_H2RAM_REMAPPING
-/* Enable FRS detection interrupt. */
-#define IT83XX_INTC_FAST_SWAP_SUPPORT
-/* Enable detect type-c plug in and out interrupt. */
-#define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
-/* Wake up CPU from low power mode even if interrupts are disabled */
-#define IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED
-/* Individual setting CC1 and CC2 resistance. */
-#define IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE
-/* Chip actually has TCPC physical port count. */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
-#else
-#error "Unsupported chip variant!"
-#endif
-
-#define CHIP_RAMCODE_ILM0 (CONFIG_RAM_BASE + 0)      /* base+0000h~base+0FFF */
-#define CHIP_H2RAM_BASE   (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */
-#define CHIP_RAMCODE_BASE (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF */
-
-#ifdef BASEBOARD_KUKUI
-/*
- * Reserved 0x80000~0xfffff 512kb on flash for saving EC logs (8kb space is
- * enough to save the logs). This configuration reduces EC FW binary size to
- * 512kb. With this config, we still have 4x kb space on RO and 6x kb space on
- * RW.
- */
-#define CHIP_FLASH_PRESERVE_LOGS_BASE 0x80000
-#define CHIP_FLASH_PRESERVE_LOGS_SIZE 0x2000
-#undef CONFIG_FLASH_SIZE_BYTES
-#define CONFIG_FLASH_SIZE_BYTES CHIP_FLASH_PRESERVE_LOGS_BASE
-#endif
-
-#endif  /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */
diff --git a/chip/it83xx/dac.c b/chip/it83xx/dac.c
deleted file mode 100644
index 695d1cbc68..0000000000
--- a/chip/it83xx/dac.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT83xx DAC module for Chrome EC */
-
-#include "console.h"
-#include "dac_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "util.h"
-
-/* DAC module enable */
-void dac_enable_channel(enum chip_dac_channel ch)
-{
-	IT83XX_DAC_DACPDREG &= ~IT83XX_DAC_POWDN(ch);
-}
-
-/* DAC module disable */
-void dac_disable_channel(enum chip_dac_channel ch)
-{
-	IT83XX_DAC_DACPDREG |= IT83XX_DAC_POWDN(ch);
-}
-
-/* Set DAC output voltage */
-void dac_set_output_voltage(enum chip_dac_channel ch, int mv)
-{
-	IT83XX_DAC_DACDAT(ch) = mv * DAC_RAW_DATA / DAC_AVCC;
-}
-
-/* Get DAC output voltage */
-int dac_get_output_voltage(enum chip_dac_channel ch)
-{
-	return IT83XX_DAC_DACDAT(ch) * DAC_AVCC / DAC_RAW_DATA;
-}
-
-/* DAC module Initialization */
-static void dac_init(void)
-{
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_DAC, 1);
-}
-DECLARE_HOOK(HOOK_INIT, dac_init, HOOK_PRIO_INIT_DAC);
-
-static int command_dac(int argc, char **argv)
-{
-	char *e;
-	int ch, mv, rv;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	ch = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-	if (ch < 2 || ch > 5) {
-		ccprintf("ch%d is not supported\n", ch);
-		return EC_ERROR_PARAM1;
-	}
-
-	if (argc == 2) {
-		if (!(IT83XX_DAC_DACPDREG & IT83XX_DAC_POWDN(ch))) {
-			/* Get DAC output voltage */
-			rv = dac_get_output_voltage(ch);
-			ccprintf("DAC ch%d VOLT=%dmV\n", ch, rv);
-		} else
-			ccprintf("The DAC ch%d is powered down.\n", ch);
-	} else {
-		/*
-		 * DAC data register raw data
-		 * 0 ~ 0xFF(8-bit) = voltage 0 ~ 3300mV
-		 */
-		mv = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-		if (mv) {
-			/* Set DAC output voltage */
-			dac_set_output_voltage(ch, mv);
-			dac_enable_channel(ch);
-		} else
-			dac_disable_channel(ch);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dac, command_dac,
-			"[ch2-5] [0-3300mV]",
-			"Enable or disable(0mV) DAC output voltage.");
diff --git a/chip/it83xx/dac_chip.h b/chip/it83xx/dac_chip.h
deleted file mode 100644
index fa50769c85..0000000000
--- a/chip/it83xx/dac_chip.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT83xx DAC module for Chrome EC */
-
-#ifndef __CROS_EC_DAC_CHIP_H
-#define __CROS_EC_DAC_CHIP_H
-
-#define DAC_AVCC 3300
-/*
- * Each channel generates an output ranging
- * from 0V to AVCC with 8-bit resolution.
- */
-#define DAC_RAW_DATA (BIT(8) - 1)
-
-/* List of DAC channels. */
-enum chip_dac_channel {
-	CHIP_DAC_CH2 = 2,
-	CHIP_DAC_CH3,
-	CHIP_DAC_CH4,
-	CHIP_DAC_CH5,
-};
-
-/**
- * DAC module enable.
- *
- * @param ch		Channel to enable.
- */
-void dac_enable_channel(enum chip_dac_channel ch);
-
-/**
- * DAC module disable.
- *
- * @param ch		Channel to disable.
- */
-void dac_disable_channel(enum chip_dac_channel ch);
-
-/**
- * Set DAC output voltage.
- *
- * @param ch		Channel to set.
- * @param mv		Setting ch output voltage.
- */
-void dac_set_output_voltage(enum chip_dac_channel ch, int mv);
-
-/**
- * Get DAC output voltage.
- *
- * @param ch		Channel to get.
- *
- * @return		Getting ch output voltage.
- */
-int dac_get_output_voltage(enum chip_dac_channel ch);
-
-#endif /* __CROS_EC_DAC_CHIP_H */
-
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
deleted file mode 100644
index be02a8f813..0000000000
--- a/chip/it83xx/ec2i.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* EC2I control module for IT83xx. */
-
-#include "common.h"
-#include "console.h"
-#include "ec2i_chip.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-static const struct ec2i_t keyboard_settings[] = {
-	/* Select logical device 06h(keyboard) */
-	{HOST_INDEX_LDN, LDN_KBC_KEYBOARD},
-	/* Set IRQ=01h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x01},
-	/* Configure IRQTP for KBC. */
-#ifdef CONFIG_HOSTCMD_ESPI
-	/*
-	 * Interrupt request type select (IRQTP) for KBC.
-	 * bit 1, 0: IRQ request is buffered and applied to SERIRQ
-	 *        1: IRQ request is inverted before being applied to SERIRQ
-	 * bit 0, 0: Edge triggered mode
-	 *        1: Level triggered mode
-	 *
-	 * SERIRQ# is by default deasserted level high. However, when using
-	 * eSPI, SERIRQ# is routed over virtual wire as interrupt event. As
-	 * per eSPI base spec (doc#327432), all virtual wire interrupt events
-	 * are deasserted level low. Thus, it is necessary to configure this
-	 * interrupt as inverted. ITE hardware takes care of routing the SERIRQ#
-	 * signal appropriately over eSPI / LPC depending upon the selected
-	 * mode.
-	 *
-	 * Additionally, this interrupt is configured as edge-triggered on the
-	 * host side. So, match the trigger mode on the EC side as well.
-	 */
-	{HOST_INDEX_IRQTP, 0x02},
-#endif
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-#ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
-static const struct ec2i_t mouse_settings[] = {
-	/* Select logical device 05h(mouse) */
-	{HOST_INDEX_LDN, LDN_KBC_MOUSE},
-	/* Set IRQ=0Ch for logical device */
-	{HOST_INDEX_IRQNUMX, 0x0C},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-#endif
-
-static const struct ec2i_t pm1_settings[] = {
-	/* Select logical device 11h(PM1 ACPI) */
-	{HOST_INDEX_LDN, LDN_PMC1},
-	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-static const struct ec2i_t pm2_settings[] = {
-	/* Select logical device 12h(PM2) */
-	{HOST_INDEX_LDN, LDN_PMC2},
-	/* I/O Port Base Address 200h/204h */
-	{HOST_INDEX_IOBAD0_MSB, 0x02},
-	{HOST_INDEX_IOBAD0_LSB, 0x00},
-	{HOST_INDEX_IOBAD1_MSB, 0x02},
-	{HOST_INDEX_IOBAD1_LSB, 0x04},
-	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-static const struct ec2i_t smfi_settings[] = {
-	/* Select logical device 0Fh(SMFI) */
-	{HOST_INDEX_LDN, LDN_SMFI},
-	/* H2RAM LPC I/O cycle Dxxx */
-	{HOST_INDEX_DSLDC6, 0x00},
-	/* Enable H2RAM LPC I/O cycle */
-	{HOST_INDEX_DSLDC7, 0x01},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-/*
- * PM3 is enabled and base address is set to 80h so that we are able to get an
- * interrupt when host outputs data to port 80.
- */
-static const struct ec2i_t pm3_settings[] = {
-	/* Select logical device 17h(PM3) */
-	{HOST_INDEX_LDN, LDN_PMC3},
-	/* I/O Port Base Address 80h */
-	{HOST_INDEX_IOBAD0_MSB, 0x00},
-	{HOST_INDEX_IOBAD0_LSB, 0x80},
-	{HOST_INDEX_IOBAD1_MSB, 0x00},
-	{HOST_INDEX_IOBAD1_LSB, 0x00},
-	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-/*
- * This logical device is not enabled, however P80L* settings need to be
- * performed on this logical device to ensure that port80 BRAM index is
- * initialized correctly.
- */
-static const struct ec2i_t rtct_settings[] = {
-	/* Select logical device 10h(RTCT) */
-	{HOST_INDEX_LDN, LDN_RTCT},
-	/* P80L Begin Index */
-	{HOST_INDEX_DSLDC4, P80L_P80LB},
-	/* P80L End Index */
-	{HOST_INDEX_DSLDC5, P80L_P80LE},
-	/* P80L Current Index */
-	{HOST_INDEX_DSLDC6, P80L_P80LC},
-};
-
-#ifdef CONFIG_UART_HOST
-static const struct ec2i_t uart2_settings[] = {
-	/* Select logical device 2h(UART2) */
-	{HOST_INDEX_LDN, LDN_UART2},
-	/*
-	 * I/O port base address is 2F8h.
-	 * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2.
-	 * See specification 7.24.4 for more detial.
-	 */
-	{HOST_INDEX_IOBAD0_MSB, 0x02},
-	{HOST_INDEX_IOBAD0_LSB, 0xF8},
-	/* IRQ number is 3 */
-	{HOST_INDEX_IRQNUMX, 0x03},
-	/*
-	 * Interrupt Request Type Select
-	 * bit1, 0: IRQ request is buffered and applied to SERIRQ.
-	 *       1: IRQ request is inverted before being applied to SERIRQ.
-	 * bit0, 0: Edge triggered mode.
-	 *       1: Level triggered mode.
-	 */
-	{HOST_INDEX_IRQTP, 0x02},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-#endif
-
-/* EC2I access index/data port */
-enum ec2i_access {
-	/* index port */
-	EC2I_ACCESS_INDEX = 0,
-	/* data port */
-	EC2I_ACCESS_DATA = 1,
-};
-
-enum ec2i_status_mask {
-	/* 1: EC read-access is still processing. */
-	EC2I_STATUS_CRIB = BIT(1),
-	/* 1: EC write-access is still processing with IHD register. */
-	EC2I_STATUS_CWIB = BIT(2),
-	EC2I_STATUS_ALL  = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB),
-};
-
-static int ec2i_wait_status_bit_cleared(enum ec2i_status_mask mask)
-{
-	/* delay ~15.25us */
-	IT83XX_GCTRL_WNCKR = 0;
-
-	return (IT83XX_EC2I_IBCTL & mask);
-}
-
-static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data)
-{
-	int rv = EC_ERROR_UNKNOWN;
-
-	/* bit1 : VCC power on */
-	if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
-		/*
-		 * Wait that both CRIB and CWIB bits in IBCTL register
-		 * are cleared.
-		 */
-		rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_ALL);
-		if (!rv) {
-			/* Set indirect host I/O offset. */
-			IT83XX_EC2I_IHIOA = sel;
-			/* Write the data to IHD register */
-			IT83XX_EC2I_IHD = data;
-			/* Enable EC access to the PNPCFG registers */
-			IT83XX_EC2I_IBMAE |= BIT(0);
-			/* bit0: EC to I-Bus access enabled. */
-			IT83XX_EC2I_IBCTL |= BIT(0);
-			/* Wait the CWIB bit in IBCTL cleared. */
-			rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CWIB);
-			/* Disable EC access to the PNPCFG registers. */
-			IT83XX_EC2I_IBMAE &= ~BIT(0);
-			/* Disable EC to I-Bus access. */
-			IT83XX_EC2I_IBCTL &= ~BIT(0);
-		}
-	}
-
-	return rv ? EC2I_WRITE_ERROR : EC2I_WRITE_SUCCESS;
-}
-
-static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel)
-{
-	int rv = EC_ERROR_UNKNOWN;
-	uint8_t ihd = 0;
-
-	/* bit1 : VCC power on */
-	if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
-		/*
-		 * Wait that both CRIB and CWIB bits in IBCTL register
-		 * are cleared.
-		 */
-		rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_ALL);
-		if (!rv) {
-			/* Set indirect host I/O offset. */
-			IT83XX_EC2I_IHIOA = sel;
-			/* Enable EC access to the PNPCFG registers */
-			IT83XX_EC2I_IBMAE |= BIT(0);
-			/* bit1: a read-action */
-			IT83XX_EC2I_IBCTL |= BIT(1);
-			/* bit0: EC to I-Bus access enabled. */
-			IT83XX_EC2I_IBCTL |= BIT(0);
-			/* Wait the CRIB bit in IBCTL cleared. */
-			rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CRIB);
-			/* Read the data from IHD register */
-			ihd = IT83XX_EC2I_IHD;
-			/* Disable EC access to the PNPCFG registers. */
-			IT83XX_EC2I_IBMAE &= ~BIT(0);
-			/* Disable EC to I-Bus access. */
-			IT83XX_EC2I_IBCTL &= ~BIT(0);
-		}
-	}
-
-	return rv ? EC2I_READ_ERROR : (EC2I_READ_SUCCESS + ihd);
-}
-
-/* EC2I read */
-enum ec2i_message ec2i_read(enum host_pnpcfg_index index)
-{
-	enum ec2i_message ret = EC2I_READ_ERROR;
-	/* critical section with interrupts off */
-	uint32_t int_mask = read_clear_int_mask();
-
-	/* Set index */
-	if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS)
-		/* read data port */
-		ret = ec2i_read_pnpcfg(EC2I_ACCESS_DATA);
-	/* restore interrupts */
-	set_int_mask(int_mask);
-
-	return ret;
-}
-
-/* EC2I write */
-enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data)
-{
-	enum ec2i_message ret = EC2I_WRITE_ERROR;
-	/* critical section with interrupts off */
-	uint32_t int_mask = read_clear_int_mask();
-
-	/* Set index */
-	if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS)
-		/* Set data */
-		ret = ec2i_write_pnpcfg(EC2I_ACCESS_DATA, data);
-	/* restore interrupts */
-	set_int_mask(int_mask);
-
-	return ret;
-}
-
-static void pnpcfg_configure(const struct ec2i_t *settings, size_t entries)
-{
-	size_t i;
-
-	for (i = 0; i < entries; i++) {
-		if (ec2i_write(settings[i].index_port, settings[i].data_port) ==
-		    EC2I_WRITE_ERROR) {
-			ccprints("Failed to apply %zd", i);
-			break;
-		}
-	}
-}
-
-#define PNPCFG(_s)						\
-	pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings))
-
-static void pnpcfg_init(void)
-{
-	/* Host access is disabled */
-	IT83XX_EC2I_LSIOHA |= 0x3;
-
-	PNPCFG(keyboard);
-#ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
-	PNPCFG(mouse);
-#endif
-	PNPCFG(pm1);
-	PNPCFG(pm2);
-	PNPCFG(smfi);
-	PNPCFG(pm3);
-	PNPCFG(rtct);
-#ifdef CONFIG_UART_HOST
-	PNPCFG(uart2);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, pnpcfg_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/it83xx/ec2i_chip.h b/chip/it83xx/ec2i_chip.h
deleted file mode 100644
index c8069f4ff5..0000000000
--- a/chip/it83xx/ec2i_chip.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* EC2I control module for IT83xx. */
-
-#ifndef __CROS_EC_EC2I_CHIP_H
-#define __CROS_EC_EC2I_CHIP_H
-
-#define P80L_P80LB               0
-#define P80L_P80LE               0x3F
-#define P80L_P80LC               0
-#define P80L_BRAM_BANK1_SIZE_MASK 0x3F
-
-/* Index list of the host interface registers of PNPCFG */
-enum host_pnpcfg_index {
-	/* Logical Device Number */
-	HOST_INDEX_LDN = 0x07,
-	/* Chip ID Byte 1 */
-	HOST_INDEX_CHIPID1 = 0x20,
-	/* Chip ID Byte 2 */
-	HOST_INDEX_CHIPID2 = 0x21,
-	/* Chip Version */
-	HOST_INDEX_CHIPVER = 0x22,
-	/* Super I/O Control */
-	HOST_INDEX_SIOCTRL = 0x23,
-	/* Super I/O IRQ Configuration */
-	HOST_INDEX_SIOIRQ = 0x25,
-	/* Super I/O General Purpose */
-	HOST_INDEX_SIOGP = 0x26,
-	/* Super I/O Power Mode */
-	HOST_INDEX_SIOPWR = 0x2D,
-	/* Depth 2 I/O Address */
-	HOST_INDEX_D2ADR = 0x2E,
-	/* Depth 2 I/O Data */
-	HOST_INDEX_D2DAT = 0x2F,
-	/* Logical Device Activate Register */
-	HOST_INDEX_LDA = 0x30,
-	/* I/O Port Base Address Bits [15:8] for Descriptor 0 */
-	HOST_INDEX_IOBAD0_MSB = 0x60,
-	/* I/O Port Base Address Bits [7:0] for Descriptor 0 */
-	HOST_INDEX_IOBAD0_LSB = 0x61,
-	/* I/O Port Base Address Bits [15:8] for Descriptor 1 */
-	HOST_INDEX_IOBAD1_MSB = 0x62,
-	/* I/O Port Base Address Bits [7:0] for Descriptor 1 */
-	HOST_INDEX_IOBAD1_LSB = 0x63,
-	/* Interrupt Request Number and Wake-Up on IRQ Enabled */
-	HOST_INDEX_IRQNUMX = 0x70,
-	/* Interrupt Request Type Select */
-	HOST_INDEX_IRQTP = 0x71,
-	/* DMA Channel Select 0 */
-	HOST_INDEX_DMAS0 = 0x74,
-	/* DMA Channel Select 1 */
-	HOST_INDEX_DMAS1 = 0x75,
-	/* Device Specific Logical Device Configuration 1 to 10 */
-	HOST_INDEX_DSLDC1 = 0xF0,
-	HOST_INDEX_DSLDC2 = 0xF1,
-	HOST_INDEX_DSLDC3 = 0xF2,
-	HOST_INDEX_DSLDC4 = 0xF3,
-	HOST_INDEX_DSLDC5 = 0xF4,
-	HOST_INDEX_DSLDC6 = 0xF5,
-	HOST_INDEX_DSLDC7 = 0xF6,
-	HOST_INDEX_DSLDC8 = 0xF7,
-	HOST_INDEX_DSLDC9 = 0xF8,
-	HOST_INDEX_DSLDC10 = 0xF9,
-};
-
-/* List of logical device number (LDN) assignments */
-enum logical_device_number {
-	/* Serial Port 1 */
-	LDN_UART1 = 0x01,
-	/* Serial Port 2 */
-	LDN_UART2 = 0x02,
-	/* System Wake-Up Control */
-	LDN_SWUC = 0x04,
-	/* KBC/Mouse Interface */
-	LDN_KBC_MOUSE = 0x05,
-	/* KBC/Keyboard Interface */
-	LDN_KBC_KEYBOARD = 0x06,
-	/* Consumer IR */
-	LDN_CIR = 0x0A,
-	/* Shared Memory/Flash Interface */
-	LDN_SMFI = 0x0F,
-	/* RTC-like Timer */
-	LDN_RTCT = 0x10,
-	/* Power Management I/F Channel 1 */
-	LDN_PMC1 = 0x11,
-	/* Power Management I/F Channel 2 */
-	LDN_PMC2 = 0x12,
-	/* Serial Peripheral Interface */
-	LDN_SSPI = 0x13,
-	/* Platform Environment Control Interface */
-	LDN_PECI = 0x14,
-	/* Power Management I/F Channel 3 */
-	LDN_PMC3 = 0x17,
-	/* Power Management I/F Channel 4 */
-	LDN_PMC4 = 0x18,
-	/* Power Management I/F Channel 5 */
-	LDN_PMC5 = 0x19,
-};
-
-/* EC2I read/write message */
-enum ec2i_message {
-	/* EC2I write success */
-	EC2I_WRITE_SUCCESS = 0x00,
-	/* EC2I write error */
-	EC2I_WRITE_ERROR = 0x01,
-	/* EC2I read success */
-	EC2I_READ_SUCCESS = 0x8000,
-	/* EC2I read error */
-	EC2I_READ_ERROR = 0x8100,
-};
-
-/* Data structure for initializing PNPCFG via ec2i. */
-struct ec2i_t {
-	/* index port */
-	enum host_pnpcfg_index index_port;
-	/* data port */
-	uint8_t data_port;
-};
-
-/* EC2I write */
-enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data);
-
-/* EC2I read */
-enum ec2i_message ec2i_read(enum host_pnpcfg_index index);
-
-#endif /* __CROS_EC_EC2I_CHIP_H */
diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c
deleted file mode 100644
index 7385e83a93..0000000000
--- a/chip/it83xx/espi.c
+++ /dev/null
@@ -1,624 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ESPI module for Chrome EC */
-
-#include "console.h"
-#include "espi.h"
-#include "hooks.h"
-#include "port80.h"
-#include "power.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-struct vw_channel_t {
-	uint8_t  index;         /* VW index of signal */
-	uint8_t  level_mask;    /* level bit of signal */
-	uint8_t  valid_mask;    /* valid bit of signal */
-};
-
-/* VW settings after the controller enables the VW channel. */
-static const struct vw_channel_t en_vw_setting[] = {
-	/* EC sends SUS_ACK# = 1 VW to PCH. That does not apply to GLK SoC. */
-#ifndef CONFIG_CHIPSET_GEMINILAKE
-	{ESPI_SYSTEM_EVENT_VW_IDX_40,
-		VW_LEVEL_FIELD(0),
-		VW_VALID_FIELD(VW_IDX_40_SUS_ACK)},
-#endif
-};
-
-/* VW settings after the controller enables the OOB channel. */
-static const struct vw_channel_t en_oob_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(0),
-		VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)},
-};
-
-/* VW settings after the controller enables the flash channel. */
-static const struct vw_channel_t en_flash_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
-		VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)},
-};
-
-/* VW settings at host startup */
-static const struct vw_channel_t vw_host_startup_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI |
-				VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK),
-		VW_VALID_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI |
-				VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK)},
-};
-
-#define VW_CHAN(name, idx, level, valid) \
-	[(name - VW_SIGNAL_START)] = {idx, level, valid}
-
-/* VW signals used in eSPI (NOTE: must match order of enum espi_vw_signal). */
-static const struct vw_channel_t vw_channel_list[] = {
-	/* index 02h: controller to peripheral. */
-	VW_CHAN(VW_SLP_S3_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
-		VW_LEVEL_FIELD(VW_IDX_2_SLP_S3),
-		VW_VALID_FIELD(VW_IDX_2_SLP_S3)),
-	VW_CHAN(VW_SLP_S4_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
-		VW_LEVEL_FIELD(VW_IDX_2_SLP_S4),
-		VW_VALID_FIELD(VW_IDX_2_SLP_S4)),
-	VW_CHAN(VW_SLP_S5_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
-		VW_LEVEL_FIELD(VW_IDX_2_SLP_S5),
-		VW_VALID_FIELD(VW_IDX_2_SLP_S5)),
-	/* index 03h: controller to peripheral. */
-	VW_CHAN(VW_SUS_STAT_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
-		VW_LEVEL_FIELD(VW_IDX_3_SUS_STAT),
-		VW_VALID_FIELD(VW_IDX_3_SUS_STAT)),
-	VW_CHAN(VW_PLTRST_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
-		VW_LEVEL_FIELD(VW_IDX_3_PLTRST),
-		VW_VALID_FIELD(VW_IDX_3_PLTRST)),
-	VW_CHAN(VW_OOB_RST_WARN,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
-		VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN),
-		VW_VALID_FIELD(VW_IDX_3_OOB_RST_WARN)),
-	/* index 04h: peripheral to controller. */
-	VW_CHAN(VW_OOB_RST_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_OOB_RST_ACK),
-		VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)),
-	VW_CHAN(VW_WAKE_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_WAKE),
-		VW_VALID_FIELD(VW_IDX_4_WAKE)),
-	VW_CHAN(VW_PME_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_PME),
-		VW_VALID_FIELD(VW_IDX_4_PME)),
-	/* index 05h: peripheral to controller. */
-	VW_CHAN(VW_ERROR_FATAL,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_FATAL),
-		VW_VALID_FIELD(VW_IDX_5_FATAL)),
-	VW_CHAN(VW_ERROR_NON_FATAL,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_NON_FATAL),
-		VW_VALID_FIELD(VW_IDX_5_NON_FATAL)),
-	VW_CHAN(VW_PERIPHERAL_BTLD_STATUS_DONE,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
-		VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)),
-	/* index 06h: peripheral to controller. */
-	VW_CHAN(VW_SCI_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SCI),
-		VW_VALID_FIELD(VW_IDX_6_SCI)),
-	VW_CHAN(VW_SMI_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SMI),
-		VW_VALID_FIELD(VW_IDX_6_SMI)),
-	VW_CHAN(VW_RCIN_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_RCIN),
-		VW_VALID_FIELD(VW_IDX_6_RCIN)),
-	VW_CHAN(VW_HOST_RST_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_HOST_RST_ACK),
-		VW_VALID_FIELD(VW_IDX_6_HOST_RST_ACK)),
-	/* index 07h: controller to peripheral. */
-	VW_CHAN(VW_HOST_RST_WARN,
-		ESPI_SYSTEM_EVENT_VW_IDX_7,
-		VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN),
-		VW_VALID_FIELD(VW_IDX_7_HOST_RST_WARN)),
-	/* index 40h: peripheral to controller. */
-	VW_CHAN(VW_SUS_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_40,
-		VW_LEVEL_FIELD(VW_IDX_40_SUS_ACK),
-		VW_VALID_FIELD(VW_IDX_40_SUS_ACK)),
-	/* index 41h: controller to peripheral. */
-	VW_CHAN(VW_SUS_WARN_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
-		VW_LEVEL_FIELD(VW_IDX_41_SUS_WARN),
-		VW_VALID_FIELD(VW_IDX_41_SUS_WARN)),
-	VW_CHAN(VW_SUS_PWRDN_ACK_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
-		VW_LEVEL_FIELD(VW_IDX_41_SUS_PWRDN_ACK),
-		VW_VALID_FIELD(VW_IDX_41_SUS_PWRDN_ACK)),
-	VW_CHAN(VW_SLP_A_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
-		VW_LEVEL_FIELD(VW_IDX_41_SLP_A),
-		VW_VALID_FIELD(VW_IDX_41_SLP_A)),
-	/* index 42h: controller to peripheral. */
-	VW_CHAN(VW_SLP_LAN,
-		ESPI_SYSTEM_EVENT_VW_IDX_42,
-		VW_LEVEL_FIELD(VW_IDX_42_SLP_LAN),
-		VW_VALID_FIELD(VW_IDX_42_SLP_LAN)),
-	VW_CHAN(VW_SLP_WLAN,
-		ESPI_SYSTEM_EVENT_VW_IDX_42,
-		VW_LEVEL_FIELD(VW_IDX_42_SLP_WLAN),
-		VW_VALID_FIELD(VW_IDX_42_SLP_WLAN)),
-};
-BUILD_ASSERT(ARRAY_SIZE(vw_channel_list) == VW_SIGNAL_COUNT);
-
-/* Get vw index & value information by signal */
-static int espi_vw_get_signal_index(enum espi_vw_signal event)
-{
-	uint32_t i = event - VW_SIGNAL_START;
-
-	return (i < ARRAY_SIZE(vw_channel_list)) ? i : -1;
-}
-
-/**
- * Set eSPI Virtual-Wire signal to Host
- *
- * @param signal vw signal needs to set
- * @param level  level of vw signal
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
-{
-	/* Get index of vw signal list by signale name */
-	int i = espi_vw_get_signal_index(signal);
-
-	if (i < 0)
-		return EC_ERROR_PARAM1;
-
-	/* critical section with interrupts off */
-	interrupt_disable();
-	if (level)
-		IT83XX_ESPI_VWIDX(vw_channel_list[i].index) |=
-			vw_channel_list[i].level_mask;
-	else
-		IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &=
-			~vw_channel_list[i].level_mask;
-	/* restore interrupts */
-	interrupt_enable();
-
-	return EC_SUCCESS;
-}
-
-/**
- * Get eSPI Virtual-Wire signal from host
- *
- * @param signal vw signal needs to get
- * @return      1: set by host, otherwise: no signal
- */
-int espi_vw_get_wire(enum espi_vw_signal signal)
-{
-	/* Get index of vw signal list by signale name */
-	int i = espi_vw_get_signal_index(signal);
-
-	if (i < 0)
-		return 0;
-
-	/* Not valid */
-	if (!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &
-		vw_channel_list[i].valid_mask))
-		return 0;
-
-	return !!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &
-		vw_channel_list[i].level_mask);
-}
-
-/**
- * Enable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to enable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_enable_wire_int(enum espi_vw_signal signal)
-{
-	/*
-	 * Common code calls this function to enable VW interrupt of power
-	 * sequence signal.
-	 * IT83xx only use a bit (bit7@IT83XX_ESPI_VWCTRL0) to enable VW
-	 * interrupt.
-	 * VW interrupt will be triggerd with any updated VW index flag
-	 * if this control bit is set.
-	 * So we will always return success here.
-	 */
-	return EC_SUCCESS;
-}
-
-/**
- * Disable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to disable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_disable_wire_int(enum espi_vw_signal signal)
-{
-	/*
-	 * We can't disable VW interrupt of power sequence signal
-	 * individually.
-	 */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-/* Configure virtual wire outputs */
-static void espi_configure_vw(const struct vw_channel_t *settings,
-						size_t entries)
-{
-	size_t i;
-
-	for (i = 0; i < entries; i++)
-		IT83XX_ESPI_VWIDX(settings[i].index) |=
-			(settings[i].level_mask | settings[i].valid_mask);
-}
-
-static void espi_vw_host_startup(void)
-{
-	espi_configure_vw(vw_host_startup_setting,
-				ARRAY_SIZE(vw_host_startup_setting));
-}
-
-static void espi_vw_no_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	CPRINTS("espi VW interrupt event is ignored! (bit%d at VWCTRL1)",
-								vw_evt);
-}
-
-#ifndef CONFIG_CHIPSET_GEMINILAKE
-static void espi_vw_idx41_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_41_SUS_WARN))
-		espi_vw_set_wire(VW_SUS_ACK, espi_vw_get_wire(VW_SUS_WARN_L));
-}
-#endif
-
-static void espi_vw_idx7_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN))
-		espi_vw_set_wire(VW_HOST_RST_ACK,
-			espi_vw_get_wire(VW_HOST_RST_WARN));
-}
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void espi_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(espi_chipset_reset);
-#endif
-
-static void espi_vw_idx3_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_3_PLTRST)) {
-		int pltrst = espi_vw_get_wire(VW_PLTRST_L);
-
-		if (pltrst) {
-			espi_vw_host_startup();
-		} else {
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-			hook_call_deferred(&espi_chipset_reset_data, MSEC);
-#endif
-			/* Store port 80 reset event */
-			port_80_write(PORT_80_EVENT_RESET);
-		}
-
-		CPRINTS("VW PLTRST_L %sasserted", pltrst ? "de" : "");
-	}
-
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN))
-		espi_vw_set_wire(VW_OOB_RST_ACK,
-			espi_vw_get_wire(VW_OOB_RST_WARN));
-}
-
-static void espi_vw_idx2_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_2_SLP_S3))
-		power_signal_interrupt(VW_SLP_S3_L);
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_2_SLP_S4))
-		power_signal_interrupt(VW_SLP_S4_L);
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_2_SLP_S5))
-		power_signal_interrupt(VW_SLP_S5_L);
-}
-
-struct vw_interrupt_t {
-	void (*vw_isr)(uint8_t flag_changed, uint8_t vw_evt);
-	uint8_t vw_index;
-};
-
-/*
- * The ISR of espi VW interrupt in array needs to match bit order in
- * IT83XX_ESPI_VWCTRL1 register.
- */
-#ifdef CONFIG_CHIPSET_GEMINILAKE
-static const struct vw_interrupt_t vw_isr_list[] = {
-	[0] = {espi_vw_idx2_isr,  ESPI_SYSTEM_EVENT_VW_IDX_2},
-	[1] = {espi_vw_idx3_isr,  ESPI_SYSTEM_EVENT_VW_IDX_3},
-	[2] = {espi_vw_idx7_isr,  ESPI_SYSTEM_EVENT_VW_IDX_7},
-	[3] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_41},
-	[4] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_42},
-	[5] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_43},
-	[6] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_44},
-	[7] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_47},
-};
-#else
-static const struct vw_interrupt_t vw_isr_list[] = {
-	[0] = {espi_vw_idx2_isr,  ESPI_SYSTEM_EVENT_VW_IDX_2},
-	[1] = {espi_vw_idx3_isr,  ESPI_SYSTEM_EVENT_VW_IDX_3},
-	[2] = {espi_vw_idx7_isr,  ESPI_SYSTEM_EVENT_VW_IDX_7},
-	[3] = {espi_vw_idx41_isr, ESPI_SYSTEM_EVENT_VW_IDX_41},
-	[4] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_42},
-	[5] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_43},
-	[6] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_44},
-	[7] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_47},
-};
-#endif
-
-/*
- * This is used to record the previous VW valid / level field state to discover
- * changes. Then do following sequence only when state is changed.
- */
-static uint8_t vw_index_flag[ARRAY_SIZE(vw_isr_list)];
-
-void espi_vw_interrupt(void)
-{
-	int i;
-	uint8_t vwidx_updated = IT83XX_ESPI_VWCTRL1;
-
-#ifdef IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR
-	/* For IT8320BX, we have to write 0xff to clear pending bit.*/
-	IT83XX_ESPI_VWCTRL1 = 0xff;
-#else
-	/* write-1 to clear */
-	IT83XX_ESPI_VWCTRL1 = vwidx_updated;
-#endif
-	task_clear_pending_irq(IT83XX_IRQ_ESPI_VW);
-
-	for (i = 0; i < ARRAY_SIZE(vw_isr_list); i++) {
-		if (vwidx_updated & BIT(i)) {
-			uint8_t idx_flag;
-
-			idx_flag = IT83XX_ESPI_VWIDX(vw_isr_list[i].vw_index);
-			vw_isr_list[i].vw_isr(vw_index_flag[i] ^ idx_flag, i);
-			vw_index_flag[i] = idx_flag;
-		}
-	}
-}
-
-static void espi_reset_vw_index_flags(void)
-{
-	int i;
-
-	/* reset vw_index_flag */
-	for (i = 0; i < ARRAY_SIZE(vw_isr_list); i++)
-		vw_index_flag[i] = IT83XX_ESPI_VWIDX(vw_isr_list[i].vw_index);
-}
-
-#ifdef IT83XX_ESPI_RESET_MODULE_BY_FW
-void __ram_code espi_fw_reset_module(void)
-{
-	/*
-	 * (b/111480168): Force a reset of logic VCC domain in EC. This will
-	 * reset both LPC and eSPI blocks. The IT8320DX spec describes the
-	 * purpose of these bits as deciding whether VCC power status is used as
-	 * an internal "power good" signal. However, toggling this field while
-	 * VCC is applied results in resettig VCC domain logic in EC. This code
-	 * must reside in SRAM to prevent DMA address corruption.
-	 *
-	 * bit[7-6]:
-	 * 00b: The VCC power status is treated as power-off.
-	 * 01b: The VCC power status is treated as power-on.
-	 */
-	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0);
-	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | BIT(6);
-}
-#endif
-
-void espi_reset_pin_asserted_interrupt(enum gpio_signal signal)
-{
-#ifdef IT83XX_ESPI_RESET_MODULE_BY_FW
-	espi_fw_reset_module();
-	/*
-	 * bit[7], enable P80L function.
-	 * bit[6], accept port 80h cycle.
-	 * bit[1-0], 10b: I2EC is read-only.
-	 */
-	IT83XX_GCTRL_SPCTRL1 |= 0xC2;
-#endif
-	/* reset vw_index_flag when espi_reset# asserted. */
-	espi_reset_vw_index_flags();
-}
-
-static int espi_get_reset_enable_config(void)
-{
-	uint8_t config;
-	const struct gpio_info *espi_rst = gpio_list + GPIO_ESPI_RESET_L;
-
-	/*
-	 * Determine if eSPI HW reset is connected to eiter B7 or D2.
-	 * bit[2-1]:
-	 * 00b: reserved.
-	 * 01b: espi_reset# is enabled on GPB7.
-	 * 10b: espi_reset# is enabled on GPD2.
-	 * 11b: reset is disabled.
-	 */
-	if (espi_rst->port == GPIO_D && espi_rst->mask == BIT(2)) {
-		config = IT83XX_GPIO_GCR_LPC_RST_D2;
-	} else if (espi_rst->port == GPIO_B && espi_rst->mask == BIT(7)) {
-		config = IT83XX_GPIO_GCR_LPC_RST_B7;
-	} else {
-		config = IT83XX_GPIO_GCR_LPC_RST_DISABLE;
-		CPRINTS("EC's espi_reset pin is not enabled correctly");
-	}
-
-	return config;
-}
-
-static void espi_enable_reset(void)
-{
-	int config = espi_get_reset_enable_config();
-
-#ifdef IT83XX_ESPI_RESET_MODULE_BY_FW
-	/*
-	 * Need to overwrite the config to ensure that eSPI HW reset is
-	 * disabled. The reset function is instead handled by FW in the
-	 * interrupt handler.
-	 */
-	config = IT83XX_GPIO_GCR_LPC_RST_DISABLE;
-	CPRINTS("EC's espi_reset pin hw auto reset is disabled");
-
-#endif
-	IT83XX_GPIO_GCR = (IT83XX_GPIO_GCR & ~0x6) |
-		(config << IT83XX_GPIO_GCR_LPC_RST_POS);
-
-	/* enable interrupt of EC's espi_reset pin */
-	gpio_clear_pending_interrupt(GPIO_ESPI_RESET_L);
-	gpio_enable_interrupt(GPIO_ESPI_RESET_L);
-}
-
-/* Interrupt event of controller enables the VW channel. */
-static void espi_vw_en_asserted(uint8_t evt)
-{
-	/*
-	 * Configure peripheral to controller virtual wire outputs after
-	 * receiving the event of controller enables the VW channel.
-	 */
-	espi_configure_vw(en_vw_setting, ARRAY_SIZE(en_vw_setting));
-}
-
-/* Interrupt event of controller enables the OOB channel. */
-static void espi_oob_en_asserted(uint8_t evt)
-{
-	/*
-	 * Configure peripheral to controller virtual wire outputs after
-	 * receiving the event of controller enables the OOB channel.
-	 */
-	espi_configure_vw(en_oob_setting, ARRAY_SIZE(en_oob_setting));
-}
-
-/* Interrupt event of controller enables the flash channel. */
-static void espi_flash_en_asserted(uint8_t evt)
-{
-	/*
-	 * Configure peripheral to controller virtual wire outputs after
-	 * receiving the event of controller enables the flash channel.
-	 */
-	espi_configure_vw(en_flash_setting, ARRAY_SIZE(en_flash_setting));
-}
-
-static void espi_no_isr(uint8_t evt)
-{
-	CPRINTS("espi interrupt event is ignored! (bit%d at ESGCTRL0)", evt);
-}
-
-/*
- * The ISR of espi interrupt event in array need to be matched bit order in
- * IT83XX_ESPI_ESGCTRL0 register.
- */
-static void (*espi_isr[])(uint8_t evt) = {
-	[0] = espi_no_isr,
-	[1] = espi_vw_en_asserted,
-	[2] = espi_oob_en_asserted,
-	[3] = espi_flash_en_asserted,
-	[4] = espi_no_isr,
-	[5] = espi_no_isr,
-	[6] = espi_no_isr,
-	[7] = espi_no_isr,
-};
-
-void espi_interrupt(void)
-{
-	int i;
-	/* get espi interrupt events */
-	uint8_t espi_event = IT83XX_ESPI_ESGCTRL0;
-
-	/* write-1 to clear */
-	IT83XX_ESPI_ESGCTRL0 = espi_event;
-	/* process espi interrupt events */
-	for (i = 0; i < ARRAY_SIZE(espi_isr); i++) {
-		if (espi_event & BIT(i))
-			espi_isr[i](i);
-	}
-	/*
-	 * bit7: the peripheral has received a peripheral posted/completion.
-	 * This bit indicates the peripheral has received a packet from eSPI
-	 * peripheral channel. We can check cycle type (bit[3-0] at ESPCTRL0)
-	 * and make corresponding modification if needed.
-	 */
-	if (IT83XX_ESPI_ESPCTRL0 & ESPI_INTERRUPT_EVENT_PUT_PC) {
-		/* write-1-clear to release PC_FREE */
-		IT83XX_ESPI_ESPCTRL0 = ESPI_INTERRUPT_EVENT_PUT_PC;
-		CPRINTS("A packet from peripheral channel is ignored!");
-	}
-
-	task_clear_pending_irq(IT83XX_IRQ_ESPI);
-}
-
-#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/* Enable/Disable eSPI pad */
-void espi_enable_pad(int enable)
-{
-	if (enable)
-		/* Enable eSPI pad. */
-		IT83XX_ESPI_ESGCTRL2 &= ~BIT(6);
-	else
-		/* Disable eSPI pad. */
-		IT83XX_ESPI_ESGCTRL2 |= BIT(6);
-}
-#endif
-
-void espi_init(void)
-{
-	/*
-	 * bit[2-0], the maximum frequency of operation supported by peripheral:
-	 * 000b: 20MHz
-	 * 001b: 25MHz
-	 * 010b: 33MHz
-	 * 011b: 50MHz
-	 * 100b: 66MHz
-	 */
-#ifdef IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
-	IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | BIT(2);
-#endif
-	/* reset vw_index_flag at initialization */
-	espi_reset_vw_index_flags();
-
-	/*
-	 * bit[3]: The reset source of PNPCFG is RSTPNP bit in RSTCH
-	 * register and WRST#.
-	 */
-	IT83XX_GCTRL_RSTS &= ~BIT(3);
-	task_clear_pending_irq(IT83XX_IRQ_ESPI_VW);
-	/* bit7: VW interrupt enable */
-	IT83XX_ESPI_VWCTRL0 |= BIT(7);
-	task_enable_irq(IT83XX_IRQ_ESPI_VW);
-
-	/* bit7: eSPI interrupt enable */
-	IT83XX_ESPI_ESGCTRL1 |= BIT(7);
-	/* bit4: eSPI to WUC enable */
-	IT83XX_ESPI_ESGCTRL2 |= BIT(4);
-	task_enable_irq(IT83XX_IRQ_ESPI);
-
-	/* enable interrupt and reset from eSPI_reset# */
-	espi_enable_reset();
-}
diff --git a/chip/it83xx/fan.c b/chip/it83xx/fan.c
deleted file mode 100644
index adb3985025..0000000000
--- a/chip/it83xx/fan.c
+++ /dev/null
@@ -1,478 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fan control module. */
-
-#include "clock.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer_chip.h"
-#include "math_util.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#define TACH_EC_FREQ                8000000
-#define FAN_CTRL_BASED_MS           10
-#define FAN_CTRL_INTERVAL_MAX_MS    60
-
-/* The sampling rate (fs) is FreqEC / 128 */
-#define TACH_DATA_VALID_TIMEOUT_MS  (0xFFFF * 128 / (TACH_EC_FREQ / 1000))
-
-/*
- * Fan Speed (RPM) = 60 / (1/fs sec * {FnTMRR, FnTLRR} * P)
- * n denotes 1 or 2.
- * P denotes the numbers of square pulses per revolution.
- * And {FnTMRR, FnTLRR} = 0000h denotes Fan Speed is zero.
- * The sampling rate (fs) is FreqEC / 128.
- */
-/* pulse, the numbers of square pulses per revolution. */
-#define TACH0_TO_RPM(pulse, raw) (60 * TACH_EC_FREQ / 128 / pulse / raw)
-#define TACH1_TO_RPM(pulse, raw) (raw * 120 / (pulse * 2))
-
-enum fan_output_s {
-	FAN_DUTY_I  = 0x01,
-	FAN_DUTY_R  = 0x02,
-	FAN_DUTY_OV = 0x03,
-	FAN_DUTY_DONE = 0x04,
-};
-
-struct fan_info {
-	unsigned int    flags;
-	int             fan_mode;
-	int             fan_p;
-	int             rpm_target;
-	int             rpm_actual;
-	int             tach_valid_ms;
-	int             rpm_re;
-	int             fan_ms;
-	int             fan_ms_idx;
-	int             startup_duty;
-	enum fan_status fan_sts;
-	int             enabled;
-};
-static struct fan_info fan_info_data[TACH_CH_COUNT];
-
-static enum tach_ch_sel tach_bind(int ch)
-{
-	return fan_tach[pwm_channels[ch].channel].ch_tach;
-}
-
-static void fan_set_interval(int ch)
-{
-	int diff, fan_ms;
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	diff = ABS(fan_info_data[tach_ch].rpm_target -
-		fan_info_data[tach_ch].rpm_actual) / 100;
-
-	fan_ms = FAN_CTRL_INTERVAL_MAX_MS;
-
-	fan_ms -= diff;
-	if (fan_ms < FAN_CTRL_BASED_MS)
-		fan_ms = FAN_CTRL_BASED_MS;
-
-	fan_info_data[tach_ch].fan_ms = fan_ms;
-}
-
-static void fan_init_start(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		fan_set_duty(ch, fan_info_data[tach_ch].startup_duty);
-}
-
-static int fan_all_disabled(void)
-{
-	int fan, all_disabled = 0;
-
-	for (fan = 0; fan < fan_get_count(); fan++) {
-		if (!fan_get_enabled(FAN_CH(fan)))
-			all_disabled++;
-	}
-
-	if (all_disabled >= fan_get_count())
-		return 1;
-
-	return 0;
-}
-
-void fan_set_enabled(int ch, int enabled)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	/* enable */
-	if (enabled) {
-		if (tach_ch < TACH_CH_COUNT)
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_CHANGING;
-
-		disable_sleep(SLEEP_MASK_FAN);
-		/* enable timer interrupt for fan control */
-		ext_timer_start(FAN_CTRL_EXT_TIMER, 1);
-	/* disable */
-	} else {
-		fan_set_duty(ch, 0);
-
-		if (tach_ch < TACH_CH_COUNT) {
-			fan_info_data[tach_ch].rpm_actual = 0;
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_STOPPED;
-		}
-	}
-
-	/* on/off */
-	if (tach_ch < TACH_CH_COUNT) {
-		fan_info_data[tach_ch].enabled = enabled;
-		fan_info_data[tach_ch].tach_valid_ms = 0;
-	}
-
-	pwm_enable(ch, enabled);
-
-	if (!enabled) {
-		/* disable timer interrupt if all fan off. */
-		if (fan_all_disabled()) {
-			ext_timer_stop(FAN_CTRL_EXT_TIMER, 1);
-			enable_sleep(SLEEP_MASK_FAN);
-		}
-	}
-}
-
-int fan_get_enabled(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return pwm_get_enabled(ch) && fan_info_data[tach_ch].enabled;
-	else
-		return 0;
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	pwm_set_duty(ch, percent);
-}
-
-int fan_get_duty(int ch)
-{
-	return pwm_get_duty(ch);
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return fan_info_data[tach_ch].fan_mode;
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		fan_info_data[tach_ch].fan_mode = rpm_mode;
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return fan_info_data[tach_ch].rpm_actual;
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-int fan_get_rpm_target(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return fan_info_data[tach_ch].rpm_target;
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-test_mockable void fan_set_rpm_target(int ch, int rpm)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		fan_info_data[tach_ch].rpm_target = rpm;
-}
-
-enum fan_status fan_get_status(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return fan_info_data[tach_ch].fan_sts;
-	else
-		return FAN_STATUS_STOPPED;
-}
-
-/**
- * Return non-zero if fan is enabled but stalled.
- */
-int fan_is_stalled(int ch)
-{
-	/* Must be enabled with non-zero target to stall */
-	if (!fan_get_enabled(ch) ||
-		fan_get_rpm_target(ch) == 0 ||
-		!fan_get_duty(ch))
-		return 0;
-
-	/* Check for stall condition */
-	return fan_get_status(ch) == FAN_STATUS_STOPPED;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		fan_info_data[tach_ch].flags = flags;
-}
-
-static void fan_ctrl(int ch)
-{
-	int status = -1, adjust = 0;
-	int rpm_actual, rpm_target, rpm_re, duty;
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	fan_info_data[tach_ch].fan_ms_idx += FAN_CTRL_BASED_MS;
-	if (fan_info_data[tach_ch].fan_ms_idx >
-		fan_info_data[tach_ch].fan_ms) {
-		fan_info_data[tach_ch].fan_ms_idx = 0x00;
-		adjust = 1;
-	}
-
-	if (adjust) {
-		/* get current pwm output duty */
-		duty = fan_get_duty(ch);
-
-		/* rpm mode */
-		if (fan_info_data[tach_ch].fan_mode) {
-			rpm_actual = fan_info_data[tach_ch].rpm_actual;
-			rpm_target = fan_info_data[tach_ch].rpm_target;
-			rpm_re = fan_info_data[tach_ch].rpm_re;
-
-			if (rpm_actual < (rpm_target - rpm_re)) {
-				if (duty == 100) {
-					status = FAN_DUTY_OV;
-				} else {
-					if (duty == 0)
-						fan_init_start(ch);
-
-					pwm_duty_inc(ch);
-					status = FAN_DUTY_I;
-				}
-			} else if (rpm_actual > (rpm_target + rpm_re)) {
-				if (duty == 0) {
-					status = FAN_DUTY_OV;
-				} else {
-					pwm_duty_reduce(ch);
-					status = FAN_DUTY_R;
-				}
-			} else {
-				status = FAN_DUTY_DONE;
-			}
-		} else {
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_LOCKED;
-		}
-
-		if (status == FAN_DUTY_DONE) {
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_LOCKED;
-		} else if ((status == FAN_DUTY_I) || (status == FAN_DUTY_R)) {
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_CHANGING;
-		} else if (status == FAN_DUTY_OV) {
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_FRUSTRATED;
-
-			if (!fan_info_data[tach_ch].rpm_actual && duty)
-				fan_info_data[tach_ch].fan_sts =
-					FAN_STATUS_STOPPED;
-		}
-	}
-}
-
-static int tach_ch_valid(enum tach_ch_sel tach_ch)
-{
-	int valid = 0;
-
-	switch (tach_ch) {
-	case TACH_CH_TACH0A:
-		if ((IT83XX_PWM_TSWCTRL & 0x0C) == 0x08)
-			valid = 1;
-		break;
-	case TACH_CH_TACH1A:
-		if ((IT83XX_PWM_TSWCTRL & 0x03) == 0x02)
-			valid = 1;
-		break;
-	case TACH_CH_TACH0B:
-		if ((IT83XX_PWM_TSWCTRL & 0x0C) == 0x0C)
-			valid = 1;
-		break;
-	case TACH_CH_TACH1B:
-		if ((IT83XX_PWM_TSWCTRL & 0x03) == 0x03)
-			valid = 1;
-		break;
-	default:
-		break;
-	}
-
-	return valid;
-}
-
-static int get_tach0_rpm(int fan_p)
-{
-	uint16_t rpm;
-
-	/* TACH0A / TACH0B data is valid */
-	if (IT83XX_PWM_TSWCTRL & 0x08) {
-		rpm = (IT83XX_PWM_F1TMRR << 8) | IT83XX_PWM_F1TLRR;
-
-		if (rpm)
-			rpm = TACH0_TO_RPM(fan_p, rpm);
-
-		/* W/C */
-		IT83XX_PWM_TSWCTRL |= 0x08;
-		return rpm;
-	}
-	return -1;
-}
-
-static int get_tach1_rpm(int fan_p)
-{
-	uint16_t rpm;
-
-	/* TACH1A / TACH1B data is valid */
-	if (IT83XX_PWM_TSWCTRL & 0x02) {
-		rpm = (IT83XX_PWM_F2TMRR << 8) | IT83XX_PWM_F2TLRR;
-
-		if (rpm)
-			rpm = TACH1_TO_RPM(fan_p, rpm);
-
-		/* W/C */
-		IT83XX_PWM_TSWCTRL |= 0x02;
-		return rpm;
-	}
-	return -1;
-}
-
-static void proc_tach(int ch)
-{
-	int t_rpm;
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	/* tachometer data valid */
-	if (tach_ch_valid(tach_ch)) {
-		if ((tach_ch == TACH_CH_TACH0A) || (tach_ch == TACH_CH_TACH0B))
-			t_rpm = get_tach0_rpm(fan_info_data[tach_ch].fan_p);
-		else
-			t_rpm = get_tach1_rpm(fan_info_data[tach_ch].fan_p);
-
-		fan_info_data[tach_ch].rpm_actual = t_rpm;
-		fan_set_interval(ch);
-		fan_info_data[tach_ch].tach_valid_ms = 0;
-	} else {
-		fan_info_data[tach_ch].tach_valid_ms += FAN_CTRL_BASED_MS;
-		if (fan_info_data[tach_ch].tach_valid_ms >
-			TACH_DATA_VALID_TIMEOUT_MS)
-			fan_info_data[tach_ch].rpm_actual = 0;
-	}
-}
-
-void fan_ext_timer_interrupt(void)
-{
-	int fan;
-
-	task_clear_pending_irq(et_ctrl_regs[FAN_CTRL_EXT_TIMER].irq);
-
-	for (fan = 0; fan < fan_get_count(); fan++) {
-		if (fan_get_enabled(FAN_CH(fan))) {
-			proc_tach(FAN_CH(fan));
-			fan_ctrl(FAN_CH(fan));
-		}
-	}
-}
-
-static void fan_init(void)
-{
-	int ch, rpm_re, fan_p, s_duty;
-	enum tach_ch_sel tach_ch;
-
-	for (ch = 0; ch < fan_get_count(); ch++) {
-
-		rpm_re = fan_tach[pwm_channels[FAN_CH(ch)].channel].rpm_re;
-		fan_p = fan_tach[pwm_channels[FAN_CH(ch)].channel].fan_p;
-		s_duty = fan_tach[pwm_channels[FAN_CH(ch)].channel].s_duty;
-		tach_ch = tach_bind(FAN_CH(ch));
-
-		if (tach_ch < TACH_CH_COUNT) {
-
-			if (tach_ch == TACH_CH_TACH0B) {
-				/* GPJ2 will select TACH0B as its alt. */
-				IT83XX_GPIO_GRC5 |= 0x01;
-				/* bit2, to select TACH0B */
-				IT83XX_PWM_TSWCTRL |= 0x04;
-			} else if (tach_ch == TACH_CH_TACH1B) {
-				/* GPJ3 will select TACH1B as its alt. */
-				IT83XX_GPIO_GRC5 |= 0x02;
-				/* bit0, to select TACH1B */
-				IT83XX_PWM_TSWCTRL |= 0x01;
-			}
-
-			fan_info_data[tach_ch].flags = 0;
-			fan_info_data[tach_ch].fan_mode = 0;
-			fan_info_data[tach_ch].rpm_target = 0;
-			fan_info_data[tach_ch].rpm_actual = 0;
-			fan_info_data[tach_ch].tach_valid_ms = 0;
-			fan_info_data[tach_ch].fan_ms_idx = 0;
-			fan_info_data[tach_ch].enabled = 0;
-			fan_info_data[tach_ch].fan_p = fan_p;
-			fan_info_data[tach_ch].rpm_re = rpm_re;
-			fan_info_data[tach_ch].fan_ms = FAN_CTRL_BASED_MS;
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_STOPPED;
-			fan_info_data[tach_ch].startup_duty = s_duty;
-		}
-	}
-
-	/* init external timer for fan control */
-	ext_timer_ms(FAN_CTRL_EXT_TIMER, EXT_PSR_32P768K_HZ, 0, 0,
-			FAN_CTRL_BASED_MS, 1, 0);
-}
-DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN);
diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c
deleted file mode 100644
index ed02aa882f..0000000000
--- a/chip/it83xx/flash.c
+++ /dev/null
@@ -1,808 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "flash_chip.h"
-#include "host_command.h"
-#include "intc.h"
-#include "system.h"
-#include "util.h"
-#include "watchdog.h"
-#include "registers.h"
-#include "task.h"
-#include "shared_mem.h"
-#include "uart.h"
-
-#define FLASH_DMA_START ((uint32_t) &__flash_dma_start)
-#define FLASH_DMA_CODE __attribute__((section(".flash_direct_map")))
-#define FLASH_ILM0_ADDR ((uint32_t) &__ilm0_ram_code)
-
-/* erase size of sector is 1KB or 4KB */
-#define FLASH_SECTOR_ERASE_SIZE CONFIG_FLASH_ERASE_SIZE
-
-#ifdef IT83XX_CHIP_FLASH_IS_KGD
-/* page program command  */
-#define FLASH_CMD_PAGE_WRITE    0x2
-/* ector erase command (erase size is 4KB) */
-#define FLASH_CMD_SECTOR_ERASE  0x20
-/* command for flash write */
-#define FLASH_CMD_WRITE         FLASH_CMD_PAGE_WRITE
-#else
-/* Auto address increment programming */
-#define FLASH_CMD_AAI_WORD      0xAD
-/* Flash sector erase (1K bytes) command */
-#define FLASH_CMD_SECTOR_ERASE  0xD7
-/* command for flash write */
-#define FLASH_CMD_WRITE         FLASH_CMD_AAI_WORD
-#endif
-/* Write status register */
-#define FLASH_CMD_WRSR         0x01
-/* Write disable */
-#define FLASH_CMD_WRDI         0x04
-/* Write enable */
-#define FLASH_CMD_WREN         0x06
-/* Read status register */
-#define FLASH_CMD_RS           0x05
-
-#if (CONFIG_FLASH_SIZE_BYTES == 0x80000) && defined(CHIP_CORE_NDS32)
-#define FLASH_TEXT_START ((uint32_t) &__flash_text_start)
-/* Apply workaround of the issue (b:111808417) */
-#define IMMU_CACHE_TAG_INVALID
-/* The default tag index of immu. */
-#define IMMU_TAG_INDEX_BY_DEFAULT 0x7E000
-/* immu cache size is 8K bytes. */
-#define IMMU_SIZE                 0x2000
-#endif
-
-static int stuck_locked;
-static int inconsistent_locked;
-static int all_protected;
-static int flash_dma_code_enabled;
-
-#define FWP_REG(bank) (bank / 8)
-#define FWP_MASK(bank) (1 << (bank % 8))
-
-enum flash_wp_interface {
-	FLASH_WP_HOST = 0x01,
-	FLASH_WP_DBGR = 0x02,
-	FLASH_WP_EC = 0x04,
-};
-
-enum flash_wp_status {
-	FLASH_WP_STATUS_PROTECT_RO = EC_FLASH_PROTECT_RO_NOW,
-	FLASH_WP_STATUS_PROTECT_ALL = EC_FLASH_PROTECT_ALL_NOW,
-};
-
-enum flash_status_mask {
-	FLASH_SR_NO_BUSY = 0,
-	/* Internal write operation is in progress */
-	FLASH_SR_BUSY = 0x01,
-	/* Device is memory Write enabled */
-	FLASH_SR_WEL = 0x02,
-
-	FLASH_SR_ALL = (FLASH_SR_BUSY | FLASH_SR_WEL),
-};
-
-enum dlm_address_view {
-	SCAR0_ILM0_DLM13   = 0x8D000, /* DLM ~ 0x8DFFF H2RAM map LPC I/O */
-	SCAR1_ILM1_DLM11   = 0x8B000, /* DLM ~ 0x8BFFF ram 44K ~ 48K */
-	SCAR2_ILM2_DLM14   = 0x8E000, /* DLM ~ 0x8EFFF RO/RW flash code DMA */
-	SCAR3_ILM3_DLM6    = 0x86000, /* DLM ~ 0x86FFF ram 24K ~ 28K */
-	SCAR4_ILM4_DLM7    = 0x87000, /* DLM ~ 0x87FFF ram 28K ~ 32K */
-	SCAR5_ILM5_DLM8    = 0x88000, /* DLM ~ 0x88FFF ram 32K ~ 36K */
-	SCAR6_ILM6_DLM9    = 0x89000, /* DLM ~ 0x89FFF ram 36K ~ 40K */
-	SCAR7_ILM7_DLM10   = 0x8A000, /* DLM ~ 0x8AFFF ram 40K ~ 44K */
-	SCAR8_ILM8_DLM4    = 0x84000, /* DLM ~ 0x84FFF ram 16K ~ 20K */
-	SCAR9_ILM9_DLM5    = 0x85000, /* DLM ~ 0x85FFF ram 20K ~ 24K */
-	SCAR10_ILM10_DLM2  = 0x82000, /* DLM ~ 0x82FFF ram 8K ~ 12K */
-	SCAR11_ILM11_DLM3  = 0x83000, /* DLM ~ 0x83FFF ram 12K ~ 16K */
-	SCAR12_ILM12_DLM12 = 0x8C000, /* DLM ~ 0x8CFFF immu cache */
-};
-
-void FLASH_DMA_CODE dma_reset_immu(int fill_immu)
-{
-	/* Immu tag sram reset */
-	IT83XX_GCTRL_MCCR |= 0x10;
-	/* Make sure the immu(dynamic cache) is reset */
-	data_serialization_barrier();
-
-	IT83XX_GCTRL_MCCR &= ~0x10;
-	data_serialization_barrier();
-
-#ifdef IMMU_CACHE_TAG_INVALID
-	/*
-	 * Workaround for (b:111808417):
-	 * After immu reset, we will fill the immu cache with 8KB data
-	 * that are outside address 0x7e000 ~ 0x7ffff.
-	 * When CPU tries to fetch contents from address 0x7e000 ~ 0x7ffff,
-	 * immu will re-fetch the missing contents inside 0x7e000 ~ 0x7ffff.
-	 */
-	if (fill_immu) {
-		volatile int immu __unused;
-		const uint32_t *ptr = (uint32_t *)FLASH_TEXT_START;
-		int i = 0;
-
-		while (i < IMMU_SIZE) {
-			immu = *ptr++;
-			i += sizeof(*ptr);
-		}
-	}
-#endif
-}
-
-void FLASH_DMA_CODE dma_flash_follow_mode(void)
-{
-	/*
-	 * ECINDAR3-0 are EC-indirect memory address registers.
-	 *
-	 * Enter follow mode by writing 0xf to low nibble of ECINDAR3 register,
-	 * and set high nibble as 0x4 to select internal flash.
-	 */
-	IT83XX_SMFI_ECINDAR3 = (EC_INDIRECT_READ_INTERNAL_FLASH | 0xf);
-	/* Set FSCE# as high level by writing 0 to address xfff_fe00h */
-	IT83XX_SMFI_ECINDAR2 = 0xFF;
-	IT83XX_SMFI_ECINDAR1 = 0xFE;
-	IT83XX_SMFI_ECINDAR0 = 0x00;
-	/* EC-indirect memory data register */
-	IT83XX_SMFI_ECINDDR = 0x00;
-}
-
-void FLASH_DMA_CODE dma_flash_follow_mode_exit(void)
-{
-	/* Exit follow mode, and keep the setting of selecting internal flash */
-	IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
-	IT83XX_SMFI_ECINDAR2 = 0x00;
-}
-
-void FLASH_DMA_CODE dma_flash_fsce_high(void)
-{
-	/* FSCE# high level */
-	IT83XX_SMFI_ECINDAR1 = 0xFE;
-	IT83XX_SMFI_ECINDDR = 0x00;
-}
-
-uint8_t FLASH_DMA_CODE dma_flash_read_dat(void)
-{
-	/* Read data from FMISO */
-	return IT83XX_SMFI_ECINDDR;
-}
-
-void FLASH_DMA_CODE dma_flash_write_dat(uint8_t wdata)
-{
-	/* Write data to FMOSI */
-	IT83XX_SMFI_ECINDDR = wdata;
-}
-
-void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf,
-					int rlen, uint8_t *rbuf, int cmd_end)
-{
-	int i;
-
-	/*  FSCE# with low level */
-	IT83XX_SMFI_ECINDAR1 = 0xFD;
-	/* Write data to FMOSI */
-	for (i = 0; i < wlen; i++)
-		IT83XX_SMFI_ECINDDR = wbuf[i];
-	/* Read data from FMISO */
-	for (i = 0; i < rlen; i++)
-		rbuf[i] = IT83XX_SMFI_ECINDDR;
-
-	/* FSCE# high level if transaction done */
-	if (cmd_end)
-		dma_flash_fsce_high();
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_read_status(enum flash_status_mask mask,
-						enum flash_status_mask target)
-{
-	uint8_t status[1];
-	uint8_t cmd_rs[] = {FLASH_CMD_RS};
-
-	/*
-	 * We prefer no timeout here. We can always get the status
-	 * we want, or wait for watchdog triggered to check
-	 * e-flash's status instead of breaking loop.
-	 * This will avoid fetching unknown instruction from e-flash
-	 * and causing exception.
-	 */
-	while (1) {
-		/* read status */
-		dma_flash_transaction(sizeof(cmd_rs), cmd_rs, 1, status, 1);
-		/* only bit[1:0] valid */
-		if ((status[0] & mask) == target)
-			break;
-	}
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_write_enable(void)
-{
-	uint8_t cmd_we[] = {FLASH_CMD_WREN};
-
-	/* enter EC-indirect follow mode */
-	dma_flash_follow_mode();
-	/* send write enable command */
-	dma_flash_transaction(sizeof(cmd_we), cmd_we, 0, NULL, 1);
-	/* read status and make sure busy bit cleared and write enabled. */
-	dma_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_WEL);
-	/* exit EC-indirect follow mode */
-	dma_flash_follow_mode_exit();
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_write_disable(void)
-{
-	uint8_t cmd_wd[] = {FLASH_CMD_WRDI};
-
-	/* enter EC-indirect follow mode */
-	dma_flash_follow_mode();
-	/* send write disable command */
-	dma_flash_transaction(sizeof(cmd_wd), cmd_wd, 0, NULL, 1);
-	/* make sure busy bit cleared. */
-	dma_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_NO_BUSY);
-	/* exit EC-indirect follow mode */
-	dma_flash_follow_mode_exit();
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_erase(int addr, int cmd)
-{
-	uint8_t cmd_erase[] = {cmd, ((addr >> 16) & 0xFF),
-				((addr >> 8) & 0xFF), (addr & 0xFF)};
-
-	/* enter EC-indirect follow mode */
-	dma_flash_follow_mode();
-	/* send erase command */
-	dma_flash_transaction(sizeof(cmd_erase), cmd_erase, 0, NULL, 1);
-	/* make sure busy bit cleared. */
-	dma_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY);
-	/* exit EC-indirect follow mode */
-	dma_flash_follow_mode_exit();
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf)
-{
-	int i;
-	uint8_t flash_write[] = {FLASH_CMD_WRITE, ((addr >> 16) & 0xFF),
-				((addr >> 8) & 0xFF), (addr & 0xFF)};
-
-	/* enter EC-indirect follow mode */
-	dma_flash_follow_mode();
-	/* send flash write command (aai word or page program) */
-	dma_flash_transaction(sizeof(flash_write), flash_write, 0, NULL, 0);
-#ifdef IT83XX_CHIP_FLASH_IS_KGD
-	for (i = 0; i < wlen; i++) {
-		/* send data byte */
-		dma_flash_write_dat(wbuf[i]);
-
-		/*
-		 * we want to restart the write sequence every IDEAL_SIZE
-		 * chunk worth of data.
-		 */
-		if (!(++addr % CONFIG_FLASH_WRITE_IDEAL_SIZE)) {
-			uint8_t w_en[] = {FLASH_CMD_WREN};
-
-			dma_flash_fsce_high();
-			/* make sure busy bit cleared. */
-			dma_flash_cmd_read_status(FLASH_SR_BUSY,
-							FLASH_SR_NO_BUSY);
-			/* send write enable command */
-			dma_flash_transaction(sizeof(w_en), w_en, 0, NULL, 1);
-			/* make sure busy bit cleared and write enabled. */
-			dma_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_WEL);
-			/* re-send write command */
-			flash_write[1] = (addr >> 16) & 0xff;
-			flash_write[2] = (addr >> 8) & 0xff;
-			flash_write[3] = addr & 0xff;
-			dma_flash_transaction(sizeof(flash_write), flash_write,
-				0, NULL, 0);
-		}
-	}
-	dma_flash_fsce_high();
-	/* make sure busy bit cleared. */
-	dma_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY);
-#else
-	for (i = 0; i < wlen; i += 2) {
-		dma_flash_write_dat(wbuf[i]);
-		dma_flash_write_dat(wbuf[i + 1]);
-		dma_flash_fsce_high();
-		/* make sure busy bit cleared. */
-		dma_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY);
-		/* resend aai word command without address field */
-		if ((i + 2) < wlen)
-			dma_flash_transaction(1, flash_write, 0, NULL, 0);
-	}
-#endif
-	/* exit EC-indirect follow mode */
-	dma_flash_follow_mode_exit();
-}
-
-uint8_t FLASH_DMA_CODE dma_flash_indirect_fast_read(int addr)
-{
-	IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
-	IT83XX_SMFI_ECINDAR2 = (addr >> 16) & 0xFF;
-	IT83XX_SMFI_ECINDAR1 = (addr >> 8) & 0xFF;
-	IT83XX_SMFI_ECINDAR0 = (addr & 0xFF);
-
-	return IT83XX_SMFI_ECINDDR;
-}
-
-int FLASH_DMA_CODE dma_flash_verify(int addr, int size, const char *data)
-{
-	int i;
-	uint8_t *wbuf = (uint8_t *)data;
-	uint8_t *flash = (uint8_t *)addr;
-
-	/* verify for erase */
-	if (data == NULL) {
-		for (i = 0; i < size; i++) {
-			if (flash[i] != 0xFF)
-				return EC_ERROR_UNKNOWN;
-		}
-	/* verify for write */
-	} else {
-		for (i = 0; i < size; i++) {
-			if (flash[i] != wbuf[i])
-				return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-void FLASH_DMA_CODE dma_flash_write(int addr, int wlen, const char *wbuf)
-{
-	dma_flash_cmd_write_enable();
-	dma_flash_cmd_write(addr, wlen, (uint8_t *)wbuf);
-	dma_flash_cmd_write_disable();
-}
-
-void FLASH_DMA_CODE dma_flash_erase(int addr, int cmd)
-{
-	dma_flash_cmd_write_enable();
-	dma_flash_cmd_erase(addr, cmd);
-	dma_flash_cmd_write_disable();
-}
-
-static enum flash_wp_status flash_check_wp(void)
-{
-	enum flash_wp_status wp_status;
-	int all_bank_count, bank;
-
-	all_bank_count = CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE;
-
-	for (bank = 0; bank < all_bank_count; bank++) {
-		if (!(IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank)))
-			break;
-	}
-
-	if (bank == WP_BANK_COUNT)
-		wp_status = FLASH_WP_STATUS_PROTECT_RO;
-	else if (bank == (WP_BANK_COUNT + PSTATE_BANK_COUNT))
-		wp_status = FLASH_WP_STATUS_PROTECT_RO;
-	else if (bank == all_bank_count)
-		wp_status = FLASH_WP_STATUS_PROTECT_ALL;
-	else
-		wp_status = 0;
-
-	return wp_status;
-}
-
-/**
- * Protect flash banks until reboot.
- *
- * @param start_bank    Start bank to protect
- * @param bank_count    Number of banks to protect
- */
-static void flash_protect_banks(int start_bank,
-				int bank_count,
-				enum flash_wp_interface wp_if)
-{
-	int bank;
-
-	for (bank = start_bank; bank < start_bank + bank_count; bank++) {
-		if (wp_if & FLASH_WP_EC)
-			IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) |= FWP_MASK(bank);
-		if (wp_if & FLASH_WP_HOST)
-			IT83XX_GCTRL_EWPR0PFH(FWP_REG(bank)) |= FWP_MASK(bank);
-		if (wp_if & FLASH_WP_DBGR)
-			IT83XX_GCTRL_EWPR0PFD(FWP_REG(bank)) |= FWP_MASK(bank);
-	}
-}
-
-int FLASH_DMA_CODE crec_flash_physical_read(int offset, int size, char *data)
-{
-	int i;
-
-	for (i = 0; i < size; i++) {
-		data[i] = dma_flash_indirect_fast_read(offset);
-		offset++;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Write to physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Data to write to flash.  Must be 32-bit aligned.
- */
-int FLASH_DMA_CODE crec_flash_physical_write(int offset, int size,
-					     const char *data)
-{
-	int ret = EC_ERROR_UNKNOWN;
-
-	if (flash_dma_code_enabled == 0)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	watchdog_reload();
-
-	/*
-	 * CPU can't fetch instruction from flash while use
-	 * EC-indirect follow mode to access flash, interrupts need to be
-	 * disabled.
-	 */
-	interrupt_disable();
-
-	dma_flash_write(offset, size, data);
-#ifdef IMMU_CACHE_TAG_INVALID
-	dma_reset_immu((offset + size) >= IMMU_TAG_INDEX_BY_DEFAULT);
-#else
-	dma_reset_immu(0);
-#endif
-	/*
-	 * Internal flash of N8 or RISC-V core is ILM(Instruction Local Memory)
-	 * mapped, but RISC-V's ILM base address is 0x80000000.
-	 *
-	 * Ensure that we will get the ILM address of a flash offset.
-	 */
-	offset |= CONFIG_MAPPED_STORAGE_BASE;
-	ret = dma_flash_verify(offset, size, data);
-
-	interrupt_enable();
-
-	return ret;
-}
-
-/**
- * Erase physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE.
- *
- * @param offset        Flash offset to erase.
- * @param size          Number of bytes to erase.
- */
-int FLASH_DMA_CODE crec_flash_physical_erase(int offset, int size)
-{
-	int v_size = size, v_addr = offset, ret = EC_ERROR_UNKNOWN;
-
-	if (flash_dma_code_enabled == 0)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/*
-	 * CPU can't fetch instruction from flash while use
-	 * EC-indirect follow mode to access flash, interrupts need to be
-	 * disabled.
-	 */
-	interrupt_disable();
-
-	/* Always use sector erase command (1K or 4K bytes) */
-	for (; size > 0; size -= FLASH_SECTOR_ERASE_SIZE) {
-		dma_flash_erase(offset, FLASH_CMD_SECTOR_ERASE);
-		offset += FLASH_SECTOR_ERASE_SIZE;
-		/*
-		 * If requested erase size is too large at one time on KGD
-		 * flash, we need to reload watchdog to prevent the reset.
-		 */
-		if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD) && (size > 0x10000))
-			watchdog_reload();
-		/*
-		 * EC still need to handle AP's EC_CMD_GET_COMMS_STATUS command
-		 * during erasing.
-		 */
-#ifdef IT83XX_IRQ_SPI_PERIPHERAL
-		if (IS_ENABLED(CONFIG_SPI) &&
-		    IS_ENABLED(HAS_TASK_HOSTCMD) &&
-		    IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) {
-			if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI)
-				task_trigger_irq(IT83XX_IRQ_SPI_PERIPHERAL);
-		}
-#endif
-	}
-#ifdef IMMU_CACHE_TAG_INVALID
-	dma_reset_immu((v_addr + v_size) >= IMMU_TAG_INDEX_BY_DEFAULT);
-#else
-	dma_reset_immu(0);
-#endif
-	/* get the ILM address of a flash offset. */
-	v_addr |= CONFIG_MAPPED_STORAGE_BASE;
-	ret = dma_flash_verify(v_addr, v_size, NULL);
-
-	interrupt_enable();
-
-	return ret;
-}
-
-/**
- * Read physical write protect setting for a flash bank.
- *
- * @param bank    Bank index to check.
- * @return        non-zero if bank is protected until reboot.
- */
-int crec_flash_physical_get_protect(int bank)
-{
-	return IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank);
-}
-
-/**
- * Protect flash now.
- *
- * @param all      Protect all (=1) or just read-only and pstate (=0).
- * @return         non-zero if error.
- */
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		/* Protect the entire flash */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-			FLASH_WP_EC);
-		all_protected = 1;
-	} else {
-		/* Protect the read-only section and persistent state */
-		flash_protect_banks(WP_BANK_OFFSET,
-			WP_BANK_COUNT, FLASH_WP_EC);
-#ifdef PSTATE_BANK
-		flash_protect_banks(PSTATE_BANK,
-			PSTATE_BANK_COUNT, FLASH_WP_EC);
-#endif
-	}
-
-	/*
-	 * bit[0], eflash protect lock register which can only be write 1 and
-	 * only be cleared by power-on reset.
-	 */
-	IT83XX_GCTRL_EPLR |= 0x01;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Return flash protect state flags from the physical layer.
- *
- * This should only be called by flash_get_protect().
- *
- * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	flags |= flash_check_wp();
-
-	if (all_protected)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	/* Check if blocks were stuck locked at pre-init */
-	if (stuck_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_STUCK;
-
-	/* Check if flash protection is in inconsistent state at pre-init */
-	if (inconsistent_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	return flags;
-}
-
-/**
- * Return the valid flash protect flags.
- *
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-/**
- * Return the writable flash protect flags.
- *
- * @param    cur_flags The current flash protect flags.
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-static void flash_enable_second_ilm(void)
-{
-#ifdef CHIP_CORE_RISCV
-	/* Make sure no interrupt while enable static cache */
-	interrupt_disable();
-
-	/* Invalid ILM0 */
-	IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM0_ENABLE;
-	IT83XX_SMFI_SCAR0H = BIT(3);
-	/* copy code to ram */
-	memcpy((void *)CHIP_RAMCODE_ILM0,
-		(const void *)FLASH_ILM0_ADDR,
-		IT83XX_ILM_BLOCK_SIZE);
-	/*
-	 * Set the logic memory address(flash code of RO/RW) in flash
-	 * by programming the register SCAR0x bit19-bit0.
-	 */
-	IT83XX_SMFI_SCAR0L = FLASH_ILM0_ADDR & GENMASK(7, 0);
-	IT83XX_SMFI_SCAR0M = (FLASH_ILM0_ADDR >> 8) & GENMASK(7, 0);
-	IT83XX_SMFI_SCAR0H = (FLASH_ILM0_ADDR >> 16) & GENMASK(2, 0);
-	if (FLASH_ILM0_ADDR & BIT(19))
-		IT83XX_SMFI_SCAR0H |= BIT(7);
-	else
-		IT83XX_SMFI_SCAR0H &= ~BIT(7);
-	/* Enable ILM 0 */
-	IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM0_ENABLE;
-
-	interrupt_enable();
-#endif
-}
-
-static void flash_code_static_dma(void)
-{
-
-	/* Make sure no interrupt while enable static DMA */
-	interrupt_disable();
-
-	/* invalid static DMA first */
-	if (IS_ENABLED(CHIP_CORE_RISCV))
-		IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM2_ENABLE;
-	IT83XX_SMFI_SCAR2H = 0x08;
-
-	/* Enable DLM 56k~60k region and than copy data into it */
-	if (IS_ENABLED(CHIP_CORE_NDS32))
-		IT83XX_GCTRL_MCCR2 |= IT83XX_DLM14_ENABLE;
-	memcpy((void *)CHIP_RAMCODE_BASE, (const void *)FLASH_DMA_START,
-		IT83XX_ILM_BLOCK_SIZE);
-	if (IS_ENABLED(CHIP_CORE_RISCV))
-		IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM2_ENABLE;
-	/* Disable DLM 56k~60k region and be the ram code section */
-	if (IS_ENABLED(CHIP_CORE_NDS32))
-		IT83XX_GCTRL_MCCR2 &= ~IT83XX_DLM14_ENABLE;
-
-	/*
-	 * Enable ILM
-	 * Set the logic memory address(flash code of RO/RW) in eflash
-	 * by programming the register SCARx bit19-bit0.
-	 */
-	IT83XX_SMFI_SCAR2L = FLASH_DMA_START & 0xFF;
-	IT83XX_SMFI_SCAR2M = (FLASH_DMA_START >> 8) & 0xFF;
-#ifdef IT83XX_DAM_ADDR_BIT19_AT_REG_SCARXH_BIT7
-	IT83XX_SMFI_SCAR2H = (FLASH_DMA_START >> 16) & 0x7;
-	if (FLASH_DMA_START & BIT(19))
-		IT83XX_SMFI_SCAR2H |= BIT(7);
-	else
-		IT83XX_SMFI_SCAR2H &= ~BIT(7);
-#else
-	IT83XX_SMFI_SCAR2H = (FLASH_DMA_START >> 16) & 0x0F;
-#endif
-	/*
-	 * Validate Direct-map SRAM function by programming
-	 * register SCARx bit20=0
-	 */
-	IT83XX_SMFI_SCAR2H &= ~0x10;
-
-	flash_dma_code_enabled = 0x01;
-
-	interrupt_enable();
-}
-
-/**
- * Initialize the module.
- *
- * Applies at-boot protection settings if necessary.
- */
-int crec_flash_pre_init(void)
-{
-	int32_t reset_flags, prot_flags, unwanted_prot_flags;
-
-	/* By default, select internal flash for indirect fast read. */
-	IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
-	if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD))
-		IT83XX_SMFI_FLHCTRL6R |= IT83XX_SMFI_MASK_ECINDPP;
-	flash_code_static_dma();
-	/*
-	 * Enable second ilm (ILM0 of it8xxx2 series), so we can pull more code
-	 * (4kB) into static cache to save latency of fetching code from flash.
-	 */
-	flash_enable_second_ilm();
-
-	reset_flags = system_get_reset_flags();
-	prot_flags = crec_flash_get_protect();
-	unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection.  Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/* Protect the entire flash of host interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-			FLASH_WP_HOST);
-		/* Protect the entire flash of DBGR interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-			FLASH_WP_DBGR);
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = crec_flash_get_protect();
-		}
-	} else {
-		/* Don't want RO flash protected */
-		unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	/* If there are no unwanted flags, done */
-	if (!(prot_flags & unwanted_prot_flags))
-		return EC_SUCCESS;
-
-	/*
-	 * If the last reboot was a power-on reset, it should have cleared
-	 * write-protect.  If it didn't, then the flash write protect registers
-	 * have been permanently committed and we can't fix that.
-	 */
-	if (reset_flags & EC_RESET_FLAG_POWER_ON) {
-		stuck_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	} else {
-		/*
-		 * Set inconsistent flag, because there is no software
-		 * reset can clear write-protect.
-		 */
-		inconsistent_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* That doesn't return, so if we're still here that's an error */
-	return EC_ERROR_UNKNOWN;
-}
diff --git a/chip/it83xx/flash_chip.h b/chip/it83xx/flash_chip.h
deleted file mode 100644
index c1262da116..0000000000
--- a/chip/it83xx/flash_chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FLASH_CHIP_H
-#define __CROS_EC_FLASH_CHIP_H
-
-/*
- * This symbol is defined in linker script and used to provide the begin
- * address of the ram code section. With this address, we can enable a ILM
- * (4K bytes static code cache) for ram code section.
- */
-extern const char __flash_dma_start;
-
-/* This symbol is the begin address of the __ilm0_ram_code section. */
-extern const char __ilm0_ram_code;
-
-/* This symbol is the begin address of the text section. */
-extern const char __flash_text_start;
-
-#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
deleted file mode 100644
index c0e2367720..0000000000
--- a/chip/it83xx/gpio.c
+++ /dev/null
@@ -1,906 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "it83xx_pd.h"
-#include "kmsc_chip.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Data structure to define KSI/KSO GPIO mode control registers. */
-struct kbs_gpio_ctrl_t {
-	/* GPIO mode control register. */
-	volatile uint8_t *gpio_mode;
-	/* GPIO output enable register. */
-	volatile uint8_t *gpio_out;
-};
-
-static const struct kbs_gpio_ctrl_t kbs_gpio_ctrl_regs[] = {
-	/* KSI pins 7:0 */
-	{&IT83XX_KBS_KSIGCTRL, &IT83XX_KBS_KSIGOEN},
-	/* KSO pins 15:8 */
-	{&IT83XX_KBS_KSOHGCTRL, &IT83XX_KBS_KSOHGOEN},
-	/* KSO pins 7:0 */
-	{&IT83XX_KBS_KSOLGCTRL, &IT83XX_KBS_KSOLGOEN},
-};
-
-/**
- * Convert wake-up controller (WUC) group to the corresponding wake-up edge
- * sense register (WUESR). Return pointer to the register.
- *
- * @param grp  WUC group.
- *
- * @return Pointer to corresponding WUESR register.
- */
-static volatile uint8_t *wuesr(uint8_t grp)
-{
-	/*
-	 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on
-	 * the address increases by fours.
-	 */
-	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUESR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUESR5 + 4*(grp-5));
-}
-
-/**
- * Convert wake-up controller (WUC) group to the corresponding wake-up edge
- * mode register (WUEMR). Return pointer to the register.
- *
- * @param grp  WUC group.
- *
- * @return Pointer to corresponding WUEMR register.
- */
-static volatile uint8_t *wuemr(uint8_t grp)
-{
-	/*
-	 * From WUEMR1-WUEMR4, the address increases by ones. From WUEMR5 on
-	 * the address increases by fours.
-	 */
-	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUEMR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4*(grp-5));
-}
-
-/**
- * Convert wake-up controller (WUC) group to the corresponding wake-up both edge
- * mode register (WUBEMR). Return pointer to the register.
- *
- * @param grp  WUC group.
- *
- * @return Pointer to corresponding WUBEMR register.
- */
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-static volatile uint8_t *wubemr(uint8_t grp)
-{
-	/*
-	 * From WUBEMR1-WUBEMR4, the address increases by ones. From WUBEMR5 on
-	 * the address increases by fours.
-	 */
-	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4*(grp-5));
-}
-#endif
-
-/*
- * Array to store the corresponding GPIO port and mask, and WUC group and mask
- * for each WKO interrupt. This allows GPIO interrupts coming in through WKO
- * to easily identify which pin caused the interrupt.
- * Note: Using designated initializers here in addition to using the array size
- * assert because many rows are purposely skipped. Not all IRQs are WKO IRQs,
- * so the IRQ index skips around. But, we still want the entire array to take
- * up the size of the total number of IRQs because the index to the array could
- * be any IRQ number.
- */
-static const struct {
-	uint8_t gpio_port;
-	uint8_t gpio_mask;
-	uint8_t wuc_group;
-	uint8_t wuc_mask;
-} gpio_irqs[] = {
-	/*     irq           gpio_port,gpio_mask,wuc_group,wuc_mask */
-	[IT83XX_IRQ_WKO20] =    {GPIO_D, BIT(0),        2, BIT(0)},
-	[IT83XX_IRQ_WKO21] =    {GPIO_D, BIT(1),        2, BIT(1)},
-	[IT83XX_IRQ_WKO22] =    {GPIO_C, BIT(4),        2, BIT(2)},
-	[IT83XX_IRQ_WKO23] =    {GPIO_C, BIT(6),        2, BIT(3)},
-	[IT83XX_IRQ_WKO24] =    {GPIO_D, BIT(2),        2, BIT(4)},
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO40] =    {GPIO_E, BIT(5),        4, BIT(0)},
-	[IT83XX_IRQ_WKO45] =    {GPIO_E, BIT(6),        4, BIT(5)},
-	[IT83XX_IRQ_WKO46] =    {GPIO_E, BIT(7),        4, BIT(6)},
-#endif
-	[IT83XX_IRQ_WKO50] =    {GPIO_K, BIT(0),        5, BIT(0)},
-	[IT83XX_IRQ_WKO51] =    {GPIO_K, BIT(1),        5, BIT(1)},
-	[IT83XX_IRQ_WKO52] =    {GPIO_K, BIT(2),        5, BIT(2)},
-	[IT83XX_IRQ_WKO53] =    {GPIO_K, BIT(3),        5, BIT(3)},
-	[IT83XX_IRQ_WKO54] =    {GPIO_K, BIT(4),        5, BIT(4)},
-	[IT83XX_IRQ_WKO55] =    {GPIO_K, BIT(5),        5, BIT(5)},
-	[IT83XX_IRQ_WKO56] =    {GPIO_K, BIT(6),        5, BIT(6)},
-	[IT83XX_IRQ_WKO57] =    {GPIO_K, BIT(7),        5, BIT(7)},
-	[IT83XX_IRQ_WKO60] =    {GPIO_H, BIT(0),        6, BIT(0)},
-	[IT83XX_IRQ_WKO61] =    {GPIO_H, BIT(1),        6, BIT(1)},
-	[IT83XX_IRQ_WKO62] =    {GPIO_H, BIT(2),        6, BIT(2)},
-	[IT83XX_IRQ_WKO63] =    {GPIO_H, BIT(3),        6, BIT(3)},
-	[IT83XX_IRQ_WKO64] =    {GPIO_F, BIT(4),        6, BIT(4)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(5),        6, BIT(5)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(6),        6, BIT(6)},
-	[IT83XX_IRQ_WKO67] =    {GPIO_F, BIT(7),        6, BIT(7)},
-	[IT83XX_IRQ_WKO70] =    {GPIO_E, BIT(0),        7, BIT(0)},
-	[IT83XX_IRQ_WKO71] =    {GPIO_E, BIT(1),        7, BIT(1)},
-	[IT83XX_IRQ_WKO72] =    {GPIO_E, BIT(2),        7, BIT(2)},
-	[IT83XX_IRQ_WKO73] =    {GPIO_E, BIT(3),        7, BIT(3)},
-	[IT83XX_IRQ_WKO74] =    {GPIO_I, BIT(4),        7, BIT(4)},
-	[IT83XX_IRQ_WKO75] =    {GPIO_I, BIT(5),        7, BIT(5)},
-	[IT83XX_IRQ_WKO76] =    {GPIO_I, BIT(6),        7, BIT(6)},
-	[IT83XX_IRQ_WKO77] =    {GPIO_I, BIT(7),        7, BIT(7)},
-	[IT83XX_IRQ_WKO80] =    {GPIO_A, BIT(3),        8, BIT(0)},
-	[IT83XX_IRQ_WKO81] =    {GPIO_A, BIT(4),        8, BIT(1)},
-	[IT83XX_IRQ_WKO82] =    {GPIO_A, BIT(5),        8, BIT(2)},
-	[IT83XX_IRQ_WKO83] =    {GPIO_A, BIT(6),        8, BIT(3)},
-	[IT83XX_IRQ_WKO84] =    {GPIO_B, BIT(2),        8, BIT(4)},
-	[IT83XX_IRQ_WKO85] =    {GPIO_C, BIT(0),        8, BIT(5)},
-	[IT83XX_IRQ_WKO86] =    {GPIO_C, BIT(7),        8, BIT(6)},
-	[IT83XX_IRQ_WKO87] =    {GPIO_D, BIT(7),        8, BIT(7)},
-	[IT83XX_IRQ_WKO88] =    {GPIO_H, BIT(4),        9, BIT(0)},
-	[IT83XX_IRQ_WKO89] =    {GPIO_H, BIT(5),        9, BIT(1)},
-	[IT83XX_IRQ_WKO90] =    {GPIO_H, BIT(6),        9, BIT(2)},
-	[IT83XX_IRQ_WKO91] =    {GPIO_A, BIT(0),        9, BIT(3)},
-	[IT83XX_IRQ_WKO92] =    {GPIO_A, BIT(1),        9, BIT(4)},
-	[IT83XX_IRQ_WKO93] =    {GPIO_A, BIT(2),        9, BIT(5)},
-	[IT83XX_IRQ_WKO94] =    {GPIO_B, BIT(4),        9, BIT(6)},
-	[IT83XX_IRQ_WKO95] =    {GPIO_C, BIT(2),        9, BIT(7)},
-	[IT83XX_IRQ_WKO96] =    {GPIO_F, BIT(0),        10, BIT(0)},
-	[IT83XX_IRQ_WKO97] =    {GPIO_F, BIT(1),        10, BIT(1)},
-	[IT83XX_IRQ_WKO98] =    {GPIO_F, BIT(2),        10, BIT(2)},
-	[IT83XX_IRQ_WKO99] =    {GPIO_F, BIT(3),        10, BIT(3)},
-	[IT83XX_IRQ_WKO100] =   {GPIO_A, BIT(7),        10, BIT(4)},
-	[IT83XX_IRQ_WKO101] =   {GPIO_B, BIT(0),        10, BIT(5)},
-	[IT83XX_IRQ_WKO102] =   {GPIO_B, BIT(1),        10, BIT(6)},
-	[IT83XX_IRQ_WKO103] =   {GPIO_B, BIT(3),        10, BIT(7)},
-	[IT83XX_IRQ_WKO104] =   {GPIO_B, BIT(5),        11, BIT(0)},
-	[IT83XX_IRQ_WKO105] =   {GPIO_B, BIT(6),        11, BIT(1)},
-	[IT83XX_IRQ_WKO106] =   {GPIO_B, BIT(7),        11, BIT(2)},
-	[IT83XX_IRQ_WKO107] =   {GPIO_C, BIT(1),        11, BIT(3)},
-	[IT83XX_IRQ_WKO108] =   {GPIO_C, BIT(3),        11, BIT(4)},
-	[IT83XX_IRQ_WKO109] =   {GPIO_C, BIT(5),        11, BIT(5)},
-	[IT83XX_IRQ_WKO110] =   {GPIO_D, BIT(3),        11, BIT(6)},
-	[IT83XX_IRQ_WKO111] =   {GPIO_D, BIT(4),        11, BIT(7)},
-	[IT83XX_IRQ_WKO112] =   {GPIO_D, BIT(5),        12, BIT(0)},
-	[IT83XX_IRQ_WKO113] =   {GPIO_D, BIT(6),        12, BIT(1)},
-	[IT83XX_IRQ_WKO114] =   {GPIO_E, BIT(4),        12, BIT(2)},
-	[IT83XX_IRQ_WKO115] =   {GPIO_G, BIT(0),        12, BIT(3)},
-	[IT83XX_IRQ_WKO116] =   {GPIO_G, BIT(1),        12, BIT(4)},
-	[IT83XX_IRQ_WKO117] =   {GPIO_G, BIT(2),        12, BIT(5)},
-	[IT83XX_IRQ_WKO118] =   {GPIO_G, BIT(6),        12, BIT(6)},
-	[IT83XX_IRQ_WKO119] =   {GPIO_I, BIT(0),        12, BIT(7)},
-	[IT83XX_IRQ_WKO120] =   {GPIO_I, BIT(1),        13, BIT(0)},
-	[IT83XX_IRQ_WKO121] =   {GPIO_I, BIT(2),        13, BIT(1)},
-	[IT83XX_IRQ_WKO122] =   {GPIO_I, BIT(3),        13, BIT(2)},
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO123] =   {GPIO_G, BIT(3),        13, BIT(3)},
-	[IT83XX_IRQ_WKO124] =   {GPIO_G, BIT(4),        13, BIT(4)},
-	[IT83XX_IRQ_WKO125] =   {GPIO_G, BIT(5),        13, BIT(5)},
-	[IT83XX_IRQ_WKO126] =   {GPIO_G, BIT(7),        13, BIT(6)},
-#endif
-	[IT83XX_IRQ_WKO128] =   {GPIO_J, BIT(0),        14, BIT(0)},
-	[IT83XX_IRQ_WKO129] =   {GPIO_J, BIT(1),        14, BIT(1)},
-	[IT83XX_IRQ_WKO130] =   {GPIO_J, BIT(2),        14, BIT(2)},
-	[IT83XX_IRQ_WKO131] =   {GPIO_J, BIT(3),        14, BIT(3)},
-	[IT83XX_IRQ_WKO132] =   {GPIO_J, BIT(4),        14, BIT(4)},
-	[IT83XX_IRQ_WKO133] =   {GPIO_J, BIT(5),        14, BIT(5)},
-	[IT83XX_IRQ_WKO134] =   {GPIO_J, BIT(6),        14, BIT(6)},
-	[IT83XX_IRQ_WKO135] =   {GPIO_J, BIT(7),        14, BIT(7)},
-	[IT83XX_IRQ_WKO136] =   {GPIO_L, BIT(0),        15, BIT(0)},
-	[IT83XX_IRQ_WKO137] =   {GPIO_L, BIT(1),        15, BIT(1)},
-	[IT83XX_IRQ_WKO138] =   {GPIO_L, BIT(2),        15, BIT(2)},
-	[IT83XX_IRQ_WKO139] =   {GPIO_L, BIT(3),        15, BIT(3)},
-	[IT83XX_IRQ_WKO140] =   {GPIO_L, BIT(4),        15, BIT(4)},
-	[IT83XX_IRQ_WKO141] =   {GPIO_L, BIT(5),        15, BIT(5)},
-	[IT83XX_IRQ_WKO142] =   {GPIO_L, BIT(6),        15, BIT(6)},
-	[IT83XX_IRQ_WKO143] =   {GPIO_L, BIT(7),        15, BIT(7)},
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO144] =   {GPIO_M, BIT(0),        16, BIT(0)},
-	[IT83XX_IRQ_WKO145] =   {GPIO_M, BIT(1),        16, BIT(1)},
-	[IT83XX_IRQ_WKO146] =   {GPIO_M, BIT(2),        16, BIT(2)},
-	[IT83XX_IRQ_WKO147] =   {GPIO_M, BIT(3),        16, BIT(3)},
-	[IT83XX_IRQ_WKO148] =   {GPIO_M, BIT(4),        16, BIT(4)},
-	[IT83XX_IRQ_WKO149] =   {GPIO_M, BIT(5),        16, BIT(5)},
-	[IT83XX_IRQ_WKO150] =   {GPIO_M, BIT(6),        16, BIT(6)},
-#endif
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[IT83XX_IRQ_GPO0]   =   {GPIO_O, BIT(0),        19, BIT(0)},
-	[IT83XX_IRQ_GPO1]   =   {GPIO_O, BIT(1),        19, BIT(1)},
-	[IT83XX_IRQ_GPO2]   =   {GPIO_O, BIT(2),        19, BIT(2)},
-	[IT83XX_IRQ_GPO3]   =   {GPIO_O, BIT(3),        19, BIT(3)},
-	[IT83XX_IRQ_GPP0]   =   {GPIO_P, BIT(0),        20, BIT(0)},
-	[IT83XX_IRQ_GPP1]   =   {GPIO_P, BIT(1),        20, BIT(1)},
-	[IT83XX_IRQ_GPP2]   =   {GPIO_P, BIT(2),        20, BIT(2)},
-	[IT83XX_IRQ_GPP3]   =   {GPIO_P, BIT(3),        20, BIT(3)},
-	[IT83XX_IRQ_GPP4]   =   {GPIO_P, BIT(4),        20, BIT(4)},
-	[IT83XX_IRQ_GPP5]   =   {GPIO_P, BIT(5),        20, BIT(5)},
-	[IT83XX_IRQ_GPP6]   =   {GPIO_P, BIT(6),        20, BIT(6)},
-	[IT83XX_IRQ_GPQ0]   =   {GPIO_Q, BIT(0),        21, BIT(0)},
-	[IT83XX_IRQ_GPQ1]   =   {GPIO_Q, BIT(1),        21, BIT(1)},
-	[IT83XX_IRQ_GPQ2]   =   {GPIO_Q, BIT(2),        21, BIT(2)},
-	[IT83XX_IRQ_GPQ3]   =   {GPIO_Q, BIT(3),        21, BIT(3)},
-	[IT83XX_IRQ_GPQ4]   =   {GPIO_Q, BIT(4),        21, BIT(4)},
-	[IT83XX_IRQ_GPQ5]   =   {GPIO_Q, BIT(5),        21, BIT(5)},
-	[IT83XX_IRQ_GPR0]   =   {GPIO_R, BIT(0),        22, BIT(0)},
-	[IT83XX_IRQ_GPR1]   =   {GPIO_R, BIT(1),        22, BIT(1)},
-	[IT83XX_IRQ_GPR2]   =   {GPIO_R, BIT(2),        22, BIT(2)},
-	[IT83XX_IRQ_GPR3]   =   {GPIO_R, BIT(3),        22, BIT(3)},
-	[IT83XX_IRQ_GPR4]   =   {GPIO_R, BIT(4),        22, BIT(4)},
-	[IT83XX_IRQ_GPR5]   =   {GPIO_R, BIT(5),        22, BIT(5)},
-#endif
-	[IT83XX_IRQ_COUNT]  =   {     0,      0,         0,      0},
-};
-BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT83XX_IRQ_COUNT + 1);
-
-/**
- * Given a GPIO port and mask, find the corresponding WKO interrupt number.
- *
- * @param port  GPIO port
- * @param mask  GPIO mask
- *
- * @return IRQ for the WKO interrupt on the corresponding input pin.
- */
-static int gpio_to_irq(uint8_t port, uint8_t mask)
-{
-	int i;
-
-	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
-		if (gpio_irqs[i].gpio_port == port &&
-				gpio_irqs[i].gpio_mask == mask)
-			return i;
-	}
-
-	return -1;
-}
-
-struct gpio_1p8v_t {
-	volatile uint8_t *reg;
-	uint8_t sel;
-};
-
-static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = {
-#ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)},
-		     [6] = {&IT83XX_GPIO_GRC24, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GRC24, BIT(6)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC24, BIT(4)} },
-	[GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
-		     [4] = {&IT83XX_GPIO_GRC24, BIT(2)},
-		     [6] = {&IT83XX_GPIO_GRC24, BIT(3)},
-		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)},
-		     [5] = {&IT83XX_GPIO_GRC22, BIT(4)},
-		     [6] = {&IT83XX_GPIO_GRC22, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GRC22, BIT(6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
-		     [1] = {&IT83XX_GPIO_GCR28, BIT(6)},
-		     [2] = {&IT83XX_GPIO_GCR28, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(2)},
-		     [5] = {&IT83XX_GPIO_GRC22, BIT(3)},
-		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
-	[GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)},
-		     [1] = {&IT83XX_GPIO_GCR28, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
-	[GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GCR28, BIT(3)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(3)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GCR28, BIT(0)} },
-	[GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
-		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(4)},
-		     [6] = {&IT83XX_GPIO_GCR27, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GCR27, BIT(6)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR27, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(1)},
-		     [6] = {&IT83XX_GPIO_GCR27, BIT(2)},
-		     [7] = {&IT83XX_GPIO_GCR33, BIT(2)} },
-	[GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR26, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR26, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR26, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR26, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR26, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR26, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GCR26, BIT(7)} },
-	[GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR25, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR25, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR25, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR25, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR25, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR25, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GCR25, BIT(7)} },
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[GPIO_O] = { [0] = {&IT83XX_GPIO_GCR31, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR31, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR31, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR31, BIT(3)} },
-	[GPIO_P] = { [0] = {&IT83XX_GPIO_GCR32, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR32, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR32, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR32, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR32, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR32, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR32, BIT(6)} },
-#endif
-#else
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)} },
-	[GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
-	[GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)} },
-	[GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
-		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)} },
-#endif
-};
-
-static void gpio_1p8v_3p3v_sel_by_pin(uint8_t port, uint8_t pin, int sel_1p8v)
-{
-	volatile uint8_t *reg_1p8v = gpio_1p8v_sel[port][pin].reg;
-	uint8_t sel = gpio_1p8v_sel[port][pin].sel;
-
-	if (reg_1p8v == NULL)
-		return;
-
-	if (sel_1p8v)
-		*reg_1p8v |= sel;
-	else
-		*reg_1p8v &= ~sel;
-}
-
-static inline void it83xx_set_alt_func(uint32_t port, uint32_t pin,
-				enum gpio_alternate_func func)
-{
-	/*
-	 * If func is not ALT_FUNC_NONE, set for alternate function.
-	 * Otherwise, turn the pin into an input as it's default.
-	 */
-	if (func != GPIO_ALT_FUNC_NONE)
-		IT83XX_GPIO_CTRL(port, pin) &= ~(GPCR_PORT_PIN_MODE_OUTPUT |
-			GPCR_PORT_PIN_MODE_INPUT);
-	else
-		IT83XX_GPIO_CTRL(port, pin) =
-			(IT83XX_GPIO_CTRL(port, pin) | GPCR_PORT_PIN_MODE_INPUT)
-			& ~GPCR_PORT_PIN_MODE_OUTPUT;
-}
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	uint32_t pin = 0;
-
-	/* Alternate function configuration for KSI/KSO pins */
-	if (port > GPIO_PORT_COUNT) {
-		port -= GPIO_KSI;
-		/*
-		 * If func is non-negative, set for keyboard scan function.
-		 * Otherwise, turn the pin into a GPIO input.
-		 */
-		if (func >= GPIO_ALT_FUNC_DEFAULT) {
-			/* KBS mode */
-			*kbs_gpio_ctrl_regs[port].gpio_mode &= ~mask;
-		} else {
-			/* input */
-			*kbs_gpio_ctrl_regs[port].gpio_out &= ~mask;
-			/* GPIO mode */
-			*kbs_gpio_ctrl_regs[port].gpio_mode |= mask;
-		}
-		return;
-	}
-
-	/* For each bit high in the mask, set that pin to use alt. func. */
-	while (mask > 0) {
-		if (mask & 1)
-			it83xx_set_alt_func(port, pin, func);
-		pin++;
-		mask >>= 1;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return (IT83XX_GPIO_DATA_MIRROR(gpio_list[signal].port) &
-			gpio_list[signal].mask) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	/* critical section with interrupts off */
-	uint32_t int_mask = read_clear_int_mask();
-
-	if (value)
-		IT83XX_GPIO_DATA(gpio_list[signal].port) |=
-				 gpio_list[signal].mask;
-	else
-		IT83XX_GPIO_DATA(gpio_list[signal].port) &=
-				~gpio_list[signal].mask;
-	/* restore interrupts */
-	set_int_mask(int_mask);
-}
-
-void gpio_kbs_pin_gpio_mode(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	uint32_t idx = port - GPIO_KSI;
-
-	/* Set GPIO mode */
-	*kbs_gpio_ctrl_regs[idx].gpio_mode |= mask;
-
-	/* Set input or output */
-	if (flags & GPIO_OUTPUT) {
-		/*
-		 * Select open drain first, so that we don't glitch the signal
-		 * when changing the line to an output.
-		 */
-		if (flags & GPIO_OPEN_DRAIN)
-			/*
-			 * it83xx: need external pullup for output data high
-			 * it8xxx2: this pin is always internal pullup
-			 */
-			IT83XX_GPIO_GPOT(port) |= mask;
-		else
-			/*
-			 * it8xxx2: this pin is not internal pullup
-			 */
-			IT83XX_GPIO_GPOT(port) &= ~mask;
-
-		/* Set level before change to output. */
-		if (flags & GPIO_HIGH)
-			IT83XX_GPIO_DATA(port) |= mask;
-		else if (flags & GPIO_LOW)
-			IT83XX_GPIO_DATA(port) &= ~mask;
-		*kbs_gpio_ctrl_regs[idx].gpio_out |= mask;
-	} else {
-		*kbs_gpio_ctrl_regs[idx].gpio_out &= ~mask;
-		if (flags & GPIO_PULL_UP)
-			IT83XX_GPIO_GPOT(port) |= mask;
-		else
-			/* No internal pullup and pulldown */
-			IT83XX_GPIO_GPOT(port) &= ~mask;
-	}
-}
-
-#ifndef IT83XX_GPIO_INT_FLEXIBLE
-/* Returns true when the falling trigger bit actually mean both trigger. */
-static int group_falling_is_both(const int group)
-{
-	return group == 7 || group == 10 || group == 12;
-}
-
-static const char *get_gpio_string(const int port, const int mask)
-{
-	static char buffer[3];
-	int i;
-
-	buffer[0] = port - GPIO_A + 'A';
-	buffer[1] = '!';
-
-	for (i = 0; i < 8; ++i) {
-		if (mask & BIT(i)) {
-			buffer[1] = i + '0';
-			break;
-		}
-	}
-	return buffer;
-}
-#endif /* IT83XX_GPIO_INT_FLEXIBLE */
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	uint32_t pin = 0;
-	uint32_t mask_copy = mask;
-
-	/* Set GPIO mode for KSI/KSO pins */
-	if (port > GPIO_PORT_COUNT) {
-		gpio_kbs_pin_gpio_mode(port, mask, flags);
-		return;
-	}
-
-	/*
-	 * Select open drain first, so that we don't glitch the signal
-	 * when changing the line to an output.
-	 */
-	if (flags & GPIO_OPEN_DRAIN)
-		IT83XX_GPIO_GPOT(port) |= mask;
-	else
-		IT83XX_GPIO_GPOT(port) &= ~mask;
-
-	/* If output, set level before changing type to an output. */
-	if (flags & GPIO_OUTPUT) {
-		if (flags & GPIO_HIGH)
-			IT83XX_GPIO_DATA(port) |= mask;
-		else if (flags & GPIO_LOW)
-			IT83XX_GPIO_DATA(port) &= ~mask;
-	}
-
-	/* For each bit high in the mask, set input/output and pullup/down. */
-	while (mask_copy > 0) {
-		if (mask_copy & 1) {
-			/* Set input or output. */
-			if (flags & GPIO_OUTPUT)
-				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_OUTPUT) &
-				~GPCR_PORT_PIN_MODE_INPUT;
-			else
-				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_INPUT) &
-				~GPCR_PORT_PIN_MODE_OUTPUT;
-
-			/* Handle pullup / pulldown */
-			if (flags & GPIO_PULL_UP) {
-				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_PULLUP) &
-				~GPCR_PORT_PIN_MODE_PULLDOWN;
-			} else if (flags & GPIO_PULL_DOWN) {
-				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_PULLDOWN) &
-				~GPCR_PORT_PIN_MODE_PULLUP;
-			} else {
-				/* No pull up/down */
-				IT83XX_GPIO_CTRL(port, pin) &=
-					~(GPCR_PORT_PIN_MODE_PULLUP |
-					  GPCR_PORT_PIN_MODE_PULLDOWN);
-			}
-
-			/* To select 1.8v or 3.3v support. */
-			gpio_1p8v_3p3v_sel_by_pin(port, pin,
-						(flags & GPIO_SEL_1P8V));
-		}
-
-		pin++;
-		mask_copy >>= 1;
-	}
-
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) {
-		int irq, wuc_group, wuc_mask;
-		irq = gpio_to_irq(port, mask);
-		wuc_group = gpio_irqs[irq].wuc_group;
-		wuc_mask = gpio_irqs[irq].wuc_mask;
-
-		/*
-		 * Set both edges interrupt.
-		 * The WUBEMR register is valid on IT8320 DX version.
-		 * And the setting (falling or rising edge) of WUEMR register is
-		 * invalid if this mode is set.
-		 */
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-		if ((flags & GPIO_INT_BOTH) == GPIO_INT_BOTH)
-			*(wubemr(wuc_group)) |= wuc_mask;
-		else
-			*(wubemr(wuc_group)) &= ~wuc_mask;
-#endif
-
-		if (flags & GPIO_INT_F_FALLING) {
-#ifndef IT83XX_GPIO_INT_FLEXIBLE
-			if (!!(flags & GPIO_INT_F_RISING) !=
-			    group_falling_is_both(wuc_group)) {
-				ccprintf("!!Fix GPIO %s interrupt config!!\n",
-					 get_gpio_string(port, mask));
-			}
-#endif
-			*(wuemr(wuc_group)) |= wuc_mask;
-		} else {
-			*(wuemr(wuc_group)) &= ~wuc_mask;
-		}
-		/*
-		 * Always write 1 to clear the WUC status register after
-		 * modifying edge mode selection register (WUBEMR and WUEMR).
-		 */
-		*(wuesr(wuc_group)) = wuc_mask;
-	}
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask);
-
-	if (irq == -1)
-		return EC_ERROR_UNKNOWN;
-	else
-		task_enable_irq(irq);
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask);
-
-	if (irq == -1)
-		return EC_ERROR_UNKNOWN;
-	else
-		task_disable_irq(irq);
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask);
-
-	if (irq == -1)
-		return EC_ERROR_UNKNOWN;
-
-	*(wuesr(gpio_irqs[irq].wuc_group)) = gpio_irqs[irq].wuc_mask;
-	task_clear_pending_irq(irq);
-	return EC_SUCCESS;
-}
-
-/* To prevent cc pins leakage, disables integrated cc module. */
-void it83xx_disable_cc_module(int port)
-{
-	/* Power down all CC, and disable CC voltage detector */
-	IT83XX_USBPD_CCGCR(port) |= USBPD_REG_MASK_DISABLE_CC;
-#if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
-	IT83XX_USBPD_CCCSR(port) |= USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR;
-#elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
-	IT83XX_USBPD_CCGCR(port) |= USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR;
-#endif
-	/*
-	 * Disconnect CC analog module (ex.UP/RD/DET/TX/RX), and
-	 * disconnect CC 5.1K to GND
-	 */
-	IT83XX_USBPD_CCCSR(port) |= (USBPD_REG_MASK_CC2_DISCONNECT |
-				     USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND |
-				     USBPD_REG_MASK_CC1_DISCONNECT |
-				     USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND);
-	/* Disconnect CC 5V tolerant */
-	IT83XX_USBPD_CCPSR(port) |= (USBPD_REG_MASK_DISCONNECT_POWER_CC2 |
-				     USBPD_REG_MASK_DISCONNECT_POWER_CC1);
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int is_warm = system_is_reboot_warm();
-	int flags;
-	int i;
-
-	IT83XX_GPIO_GCR = 0x06;
-
-#if !defined(CONFIG_IT83XX_VCC_1P8V) && !defined(CONFIG_IT83XX_VCC_3P3V)
-#error Please select voltage level of VCC for EC.
-#endif
-
-#if defined(CONFIG_IT83XX_VCC_1P8V) && defined(CONFIG_IT83XX_VCC_3P3V)
-#error Must select only one voltage level of VCC for EC.
-#endif
-	/* The power level of GPM6 follows VCC */
-	IT83XX_GPIO_GCR29 |= BIT(0);
-
-	/* The power level (VCC) of GPM0~6 is 1.8V */
-	if (IS_ENABLED(CONFIG_IT83XX_VCC_1P8V))
-		IT83XX_GPIO_GCR30 |= BIT(4);
-
-	/* The power level (VCC) of GPM0~6 is 3.3V */
-	if (IS_ENABLED(CONFIG_IT83XX_VCC_3P3V))
-		IT83XX_GPIO_GCR30 &= ~BIT(4);
-
-#if IT83XX_USBPD_PHY_PORT_COUNT < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT
-#error "ITE pd active port count should be less than physical port count !"
-#endif
-	/*
-	 * To prevent cc pins leakage and cc pins can be used as gpio,
-	 * disable board not active ITE TCPC port cc modules.
-	 */
-	for (i = CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT;
-	     i < IT83XX_USBPD_PHY_PORT_COUNT; i++) {
-		it83xx_disable_cc_module(i);
-		/* Dis-connect 5.1K dead battery resistor to CC */
-		IT83XX_USBPD_CCPSR(i) |=
-			(USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB |
-			 USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB);
-	}
-
-#ifndef CONFIG_USB
-	/*
-	 * We need to enable USB's clock so we can config USB control register.
-	 * This is important for a software reset as the hardware clock may
-	 * already be disabled from the previous run.
-	 * We will disable clock to USB module in clock_module_disable() later.
-	 */
-	clock_enable_peripheral(CGC_OFFSET_USB, 0, 0);
-	/*
-	 * Disable default pull-down of USB controller (GPH5 and GPH6) if we
-	 * don't use this module.
-	 */
-	IT83XX_USB_P0MCR &= ~USB_DP_DM_PULL_DOWN_EN;
-#endif
-
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	/* Q group pins are default GPI mode, clear alternate setting. */
-	IT83XX_VBATPC_XLPIER = 0x0;
-	/*
-	 * R group pins are default alternate output low, we clear alternate
-	 * setting (sink power switch from VBAT to VSTBY) to become GPO output
-	 * low.
-	 * NOTE: GPR0~5 pins are output low by default. It should consider
-	 *       that if output low signal effect external circuit or not,
-	 *       until we reconfig these pins in gpio.inc.
-	 */
-	IT83XX_VBATPC_BGPOPSCR = 0x0;
-#endif
-
-	/*
-	 * On IT81202 (128-pins package), the pins of GPIO group K and L aren't
-	 * bonding with pad. So we configure these pins as internal pull-down
-	 * at default to prevent leakage current due to floating.
-	 */
-	if (IS_ENABLED(IT83XX_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN)) {
-		for (i = 0; i < 8; i++) {
-			IT83XX_GPIO_CTRL(GPIO_K, i) = (GPCR_PORT_PIN_MODE_INPUT
-				| GPCR_PORT_PIN_MODE_PULLDOWN);
-			IT83XX_GPIO_CTRL(GPIO_L, i) = (GPCR_PORT_PIN_MODE_INPUT
-				| GPCR_PORT_PIN_MODE_PULLDOWN);
-		}
-	}
-
-	/*
-	 * On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
-	 * floating internally. We need to enable internal pull-down for the pin
-	 * to prevent leakage current, but IT81202/IT81302 doesn't have the
-	 * capability to pull it down. We can only set it as output low,
-	 * so we enable output low for it at initialization to prevent leakage.
-	 */
-	if (IS_ENABLED(IT83XX_GPIO_H7_DEFAULT_OUTPUT_LOW)) {
-		IT83XX_GPIO_CTRL(GPIO_H, 7) = GPCR_PORT_PIN_MODE_OUTPUT;
-		IT83XX_GPIO_DATA(GPIO_H) &= ~BIT(7);
-	}
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-/**
- * Handle a GPIO interrupt by calling the pins corresponding handler if
- * one exists.
- *
- * @param port		GPIO port (GPIO_*)
- * @param mask		GPIO mask
- */
-static void gpio_interrupt(int port, uint8_t mask)
-{
-	int i = 0;
-	const struct gpio_info *g = gpio_list;
-
-	for (i = 0; i < GPIO_IH_COUNT; i++, g++) {
-		if (port == g->port && (mask & g->mask)) {
-			gpio_irq_handlers[i](i);
-			return;
-		}
-	}
-}
-
-/**
- * Define one IRQ function to handle all GPIO interrupts. The IRQ determines
- * the interrupt number which was triggered, calls the master handler above,
- * and clears status registers.
- */
-static void __gpio_irq(void)
-{
-	/* Determine interrupt number. */
-	int irq = intc_get_ec_int();
-
-	/* assert failure if interrupt number is zero */
-	ASSERT(irq);
-
-#if defined(HAS_TASK_KEYSCAN) && !defined(CONFIG_KEYBOARD_NOT_RAW)
-	if (irq == IT83XX_IRQ_WKINTC) {
-		keyboard_raw_interrupt();
-		return;
-	}
-#endif
-
-#ifdef CONFIG_HOSTCMD_X86
-	if (irq == IT83XX_IRQ_WKINTAD)
-		return;
-#endif
-
-	/*
-	 * Clear the WUC status register. Note the external pin first goes
-	 * to the WUC module and is always edge triggered.
-	 */
-	*(wuesr(gpio_irqs[irq].wuc_group)) = gpio_irqs[irq].wuc_mask;
-
-	/*
-	 * Clear the interrupt controller  status register. Note the interrupt
-	 * controller is level triggered from the WUC status.
-	 */
-	task_clear_pending_irq(irq);
-
-	/* Run the GPIO master handler above with corresponding port/mask. */
-	gpio_interrupt(gpio_irqs[irq].gpio_port, gpio_irqs[irq].gpio_mask);
-}
-
-/* Route all WKO interrupts coming from INT#2 into __gpio_irq. */
-DECLARE_IRQ(CPU_INT_2_ALL_GPIOS, __gpio_irq, 1);
diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c
deleted file mode 100644
index 291751a1cb..0000000000
--- a/chip/it83xx/hwtimer.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "cpu.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "intc.h"
-#include "irq_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * The IT839X series support combinational mode for combining specific pairs of
- * timers: 3(24-bit) and 4(32-bit) / timer 5(24-bit) and 6(32-bit) /
- * timer 7(24-bit) and 8(32-bit).
- *
- * 32-bit MHz free-running counter: We combine (bit3@IT83XX_ETWD_ETXCTRL)
- * timer 3(TIMER_L) and 4(TIMER_H) and set clock source register to 8MHz.
- * In combinational mode, the counter register(IT83XX_ETWD_ETXCNTLR) of timer 3
- * is a fixed value = 7, and observation register(IT83XX_ETWD_ETXCNTOR)
- * of timer 4 will increase one per-us.
- *
- * For example, if
- * __hw_clock_source_set() set 0 us, the counter setting registers are
- * timer 3(TIMER_L) = 0x000007 (fixed, will not change)
- * timer 4(TIMER_H) = 0xffffffff
- *
- * Note:
- * In combinational mode, the counter observation value of
- * timer 4(TIMER_H), 6, 8 will in incrementing order.
- * For the above example, the counter observation value registers will be
- * timer 3(TIMER_L) 0x0000007
- * timer 4(TIMER_H) ~0xffffffff = 0x00000000
- *
- * The following will describe timer 3 and 4's operation in combinational mode:
- * 1. When timer 3(TIMER_L) has completed each counting (per-us),
-      timer 4(TIMER_H) observation value++.
- * 2. When timer 4(TIMER_H) observation value overflows:
- *    timer 4(TIMER_H) observation value = ~counter setting register.
- * 3. Timer 4(TIMER_H) interrupt occurs.
- *
- * IT839X only supports terminal count interrupt. We need a separate
- * 8 MHz 32-bit timer to handle events.
- */
-
-#define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
-
-const struct ext_timer_ctrl_t et_ctrl_regs[] = {
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x08,
-		IT83XX_IRQ_EXT_TIMER3},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x10,
-		IT83XX_IRQ_EXT_TIMER4},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x20,
-		IT83XX_IRQ_EXT_TIMER5},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x40,
-		IT83XX_IRQ_EXT_TIMER6},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x80,
-		IT83XX_IRQ_EXT_TIMER7},
-	{&IT83XX_INTC_IELMR10, &IT83XX_INTC_IPOLR10, &IT83XX_INTC_ISR10, 0x01,
-		IT83XX_IRQ_EXT_TMR8},
-};
-BUILD_ASSERT(ARRAY_SIZE(et_ctrl_regs) == EXT_TIMER_COUNT);
-
-static void free_run_timer_overflow(void)
-{
-	/*
-	 * If timer 4 (TIMER_H) counter register != 0xffffffff.
-	 * This usually happens once after sysjump, force time, and etc.
-	 * (when __hw_clock_source_set is called and param 'ts' != 0)
-	 */
-	if (IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) != 0xffffffff) {
-		/* set timer counter register */
-		IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff;
-		/* bit[1], timer reset */
-		IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1);
-	}
-	/* w/c interrupt status */
-	task_clear_pending_irq(et_ctrl_regs[FREE_EXT_TIMER_H].irq);
-	/* timer overflow */
-	process_timers(1);
-	update_exc_start_time();
-}
-
-static void event_timer_clear_pending_isr(void)
-{
-	/* w/c interrupt status */
-	task_clear_pending_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
-}
-
-uint32_t __ram_code __hw_clock_source_read(void)
-{
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-	/*
-	 * In combinational mode, the counter observation register of
-	 * timer 4(TIMER_H) will increment.
-	 */
-	return ext_observation_reg_read(FREE_EXT_TIMER_H);
-#else
-	return IT83XX_ETWD_ETXCNTOR(FREE_EXT_TIMER_H);
-#endif
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	/* counting down timer, microseconds to timer counter register */
-	IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff - ts;
-	/* bit[1], timer reset */
-	IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1);
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint32_t wait;
-	/* bit0, disable event timer */
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
-	/* w/c interrupt status */
-	event_timer_clear_pending_isr();
-	/* microseconds to timer counter */
-	wait = deadline - __hw_clock_source_read();
-	IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) =
-		wait < EVENT_TIMER_COUNT_TO_US(0xffffffff) ?
-		EVENT_TIMER_US_TO_COUNT(wait) : 0xffffffff;
-	/* enable and re-start timer */
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x03;
-	task_enable_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	uint32_t next_event_us = __hw_clock_source_read();
-
-	/* bit0, event timer is enabled */
-	if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)) {
-		/* timer counter observation value to microseconds */
-		next_event_us += EVENT_TIMER_COUNT_TO_US(
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-			ext_observation_reg_read(EVENT_EXT_TIMER));
-#else
-			IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER));
-#endif
-	}
-	return next_event_us;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* stop event timer */
-	ext_timer_stop(EVENT_EXT_TIMER, 1);
-	event_timer_clear_pending_isr();
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/* bit3, timer 3 and timer 4 combinational mode */
-	IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(3);
-	/* init free running timer (timer 4, TIMER_H), clock source is 8mhz */
-	ext_timer_ms(FREE_EXT_TIMER_H, EXT_PSR_8M_HZ, 0, 1, 0xffffffff, 1, 1);
-	/* 1us counter setting (timer 3, TIMER_L) */
-	ext_timer_ms(FREE_EXT_TIMER_L, EXT_PSR_8M_HZ, 1, 0, 7, 1, 1);
-	__hw_clock_source_set(start_t);
-	/* init event timer */
-	ext_timer_ms(EVENT_EXT_TIMER, EXT_PSR_8M_HZ, 0, 0, 0xffffffff, 1, 1);
-	/* returns the IRQ number of event timer */
-	return et_ctrl_regs[EVENT_EXT_TIMER].irq;
-}
-
-static void __hw_clock_source_irq(void)
-{
-	/* Determine interrupt number. */
-	int irq = intc_get_ec_int();
-
-	/* SW/HW interrupt of event timer. */
-	if (irq == et_ctrl_regs[EVENT_EXT_TIMER].irq) {
-		IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = 0xffffffff;
-		IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= BIT(1);
-		event_timer_clear_pending_isr();
-		process_timers(0);
-		return;
-	}
-
-#ifdef CONFIG_WATCHDOG
-	/*
-	 * Both the external timer for the watchdog warning and the HW timer
-	 * go through this irq. So, if this interrupt was caused by watchdog
-	 * warning timer, then call that function.
-	 */
-	if (irq == et_ctrl_regs[WDT_EXT_TIMER].irq) {
-		watchdog_warning_irq();
-		return;
-	}
-#endif
-
-#ifdef CONFIG_FANS
-	if (irq == et_ctrl_regs[FAN_CTRL_EXT_TIMER].irq) {
-		fan_ext_timer_interrupt();
-		return;
-	}
-#endif
-
-	/* Interrupt of free running timer TIMER_H. */
-	if (irq == et_ctrl_regs[FREE_EXT_TIMER_H].irq) {
-		free_run_timer_overflow();
-		return;
-	}
-
-	/*
-	 * This interrupt is used to wakeup EC from sleep mode
-	 * to complete PLL frequency change.
-	 */
-	if (irq == et_ctrl_regs[LOW_POWER_EXT_TIMER].irq) {
-		ext_timer_stop(LOW_POWER_EXT_TIMER, 1);
-		return;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_3, __hw_clock_source_irq, 1);
-
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-/* Number of CPU cycles in 125 us */
-#define CYCLES_125NS (125*(PLL_CLOCK/SECOND) / 1000)
-uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer)
-{
-	uint32_t prev_mask = read_clear_int_mask();
-	uint32_t val;
-
-	asm volatile(
-		/* read observation register for the first time */
-		"lwi %0,[%1]\n\t"
-		/*
-		 * the delay time between reading the first and second
-		 * observation registers need to be greater than 0.125us and
-		 * smaller than 0.250us.
-		 */
-		".rept %2\n\t"
-		"nop\n\t"
-		".endr\n\t"
-		/* read for the second time */
-		"lwi %0,[%1]\n\t"
-		: "=&r"(val)
-		: "r"((uintptr_t) &IT83XX_ETWD_ETXCNTOR(ext_timer)),
-			"i"(CYCLES_125NS));
-	/* restore interrupts */
-	set_int_mask(prev_mask);
-
-	return val;
-}
-#endif
-
-void ext_timer_start(enum ext_timer_sel ext_timer, int en_irq)
-{
-	/* enable external timer n */
-	IT83XX_ETWD_ETXCTRL(ext_timer) |= 0x03;
-
-	if (en_irq) {
-		task_clear_pending_irq(et_ctrl_regs[ext_timer].irq);
-		task_enable_irq(et_ctrl_regs[ext_timer].irq);
-	}
-}
-
-void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq)
-{
-	/* disable external timer n */
-	IT83XX_ETWD_ETXCTRL(ext_timer) &= ~0x01;
-
-	if (dis_irq)
-		task_disable_irq(et_ctrl_regs[ext_timer].irq);
-}
-
-static void ext_timer_ctrl(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int with_int,
-		int32_t count)
-{
-	uint8_t intc_mask;
-
-	/* rising-edge-triggered */
-	intc_mask = et_ctrl_regs[ext_timer].mask;
-	*et_ctrl_regs[ext_timer].mode |= intc_mask;
-	*et_ctrl_regs[ext_timer].polarity &= ~intc_mask;
-
-	/* clear interrupt status */
-	task_clear_pending_irq(et_ctrl_regs[ext_timer].irq);
-
-	/* These bits control the clock input source to the exttimer 3 - 8 */
-	IT83XX_ETWD_ETXPSR(ext_timer) = ext_timer_clock;
-
-	/* The count number of external timer n. */
-	IT83XX_ETWD_ETXCNTLR(ext_timer) = count;
-
-	ext_timer_stop(ext_timer, 0);
-	if (start)
-		ext_timer_start(ext_timer, 0);
-
-	if (with_int)
-		task_enable_irq(et_ctrl_regs[ext_timer].irq);
-	else
-		task_disable_irq(et_ctrl_regs[ext_timer].irq);
-}
-
-int ext_timer_ms(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int with_int,
-		int32_t ms,
-		int first_time_enable,
-		int raw)
-{
-	uint32_t count;
-
-	if (raw) {
-		count = ms;
-	} else {
-		if (ext_timer_clock == EXT_PSR_32P768K_HZ)
-			count = MS_TO_COUNT(32768, ms);
-		else if (ext_timer_clock == EXT_PSR_1P024K_HZ)
-			count = MS_TO_COUNT(1024, ms);
-		else if (ext_timer_clock == EXT_PSR_32_HZ)
-			count = MS_TO_COUNT(32, ms);
-		else if (ext_timer_clock == EXT_PSR_8M_HZ)
-			count = 8000 * ms;
-		else
-			return -1;
-	}
-
-	if (count == 0)
-		return -3;
-
-	if (first_time_enable) {
-		ext_timer_start(ext_timer, 0);
-		ext_timer_stop(ext_timer, 0);
-	}
-
-	ext_timer_ctrl(ext_timer, ext_timer_clock, start, with_int, count);
-
-	return 0;
-}
diff --git a/chip/it83xx/hwtimer_chip.h b/chip/it83xx/hwtimer_chip.h
deleted file mode 100644
index 2ccdce1d96..0000000000
--- a/chip/it83xx/hwtimer_chip.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* External timers control module for IT83xx. */
-
-#ifndef __CROS_EC_HWTIMER_CHIP_H
-#define __CROS_EC_HWTIMER_CHIP_H
-
-#define TIMER_COUNT_1US_SHIFT      3
-
-/* Microseconds to event timer counter setting register */
-#define EVENT_TIMER_US_TO_COUNT(us)  ((us) << TIMER_COUNT_1US_SHIFT)
-/* Event timer counter observation value to microseconds */
-#define EVENT_TIMER_COUNT_TO_US(cnt) ((cnt) >> TIMER_COUNT_1US_SHIFT)
-
-#define FREE_EXT_TIMER_L     EXT_TIMER_3
-#define FREE_EXT_TIMER_H     EXT_TIMER_4
-#define FAN_CTRL_EXT_TIMER   EXT_TIMER_5
-#define EVENT_EXT_TIMER      EXT_TIMER_6
-/*
- * The low power timer is used to continue system time when EC goes into low
- * power in idle task. Timer 7 is 24bit timer and configured at 32.768khz.
- * The configuration is enough for continuing system time, because periodic
- * tick event (interval is 500ms on it8xxx2) will wake EC up.
- *
- * IMPORTANT:
- * If you change low power timer to a non-24bit timer, you also have to change
- * mask of observation register in clock_sleep_mode_wakeup_isr() or EC will get
- * wrong system time after resume.
- */
-#define LOW_POWER_EXT_TIMER  EXT_TIMER_7
-#define LOW_POWER_TIMER_MASK (BIT(24) - 1)
-#define WDT_EXT_TIMER        EXT_TIMER_8
-
-enum ext_timer_clock_source {
-	EXT_PSR_32P768K_HZ = 0,
-	EXT_PSR_1P024K_HZ  = 1,
-	EXT_PSR_32_HZ      = 2,
-	EXT_PSR_8M_HZ      = 3
-};
-
-/*
- * 24-bit timers: external timer 3, 5, and 7
- * 32-bit timers: external timer 4, 6, and 8
- */
-enum ext_timer_sel {
-	/* timer 3 and 4 combine mode for free running timer */
-	EXT_TIMER_3 = 0,
-	EXT_TIMER_4,
-	/* For fan control */
-	EXT_TIMER_5,
-	/* timer 6 for event timer */
-	EXT_TIMER_6,
-	/* For WDT capture important state information before being reset */
-	EXT_TIMER_7,
-	/* HW timer for low power mode */
-	EXT_TIMER_8,
-	EXT_TIMER_COUNT,
-};
-
-struct ext_timer_ctrl_t {
-	volatile uint8_t *mode;
-	volatile uint8_t *polarity;
-	volatile uint8_t *isr;
-	uint8_t mask;
-	uint8_t irq;
-};
-
-extern const struct ext_timer_ctrl_t et_ctrl_regs[];
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer);
-#endif
-void ext_timer_start(enum ext_timer_sel ext_timer, int en_irq);
-void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq);
-void fan_ext_timer_interrupt(void);
-void update_exc_start_time(void);
-
-/**
- * Config a external timer.
- *
- * @param raw	(!=0) timer count equal to param "ms" no conversion.
- */
-int ext_timer_ms(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int et_int,
-		int32_t ms,
-		int first_time_enable,
-		int raw);
-
-#endif /* __CROS_EC_HWTIMER_CHIP_H */
diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c
deleted file mode 100644
index 5aa8f8a460..0000000000
--- a/chip/it83xx/i2c.c
+++ /dev/null
@@ -1,946 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Default maximum time we allow for an I2C transfer */
-#define I2C_TIMEOUT_DEFAULT_US (100 * MSEC)
-
-enum enhanced_i2c_transfer_direct {
-	TX_DIRECT,
-	RX_DIRECT,
-};
-
-enum i2c_host_status {
-	/* Host busy */
-	HOSTA_HOBY = 0x01,
-	/* Finish Interrupt */
-	HOSTA_FINTR = 0x02,
-	/* Device error */
-	HOSTA_DVER = 0x04,
-	/* Bus error */
-	HOSTA_BSER = 0x08,
-	/* Fail */
-	HOSTA_FAIL = 0x10,
-	/* Not response ACK */
-	HOSTA_NACK = 0x20,
-	/* Time-out error */
-	HOSTA_TMOE = 0x40,
-	/* Byte done status */
-	HOSTA_BDS = 0x80,
-	/* Error bit is set */
-	HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER |
-				HOSTA_FAIL | HOSTA_NACK | HOSTA_TMOE),
-	/* W/C for next byte */
-	HOSTA_NEXT_BYTE = HOSTA_BDS,
-	/* W/C host status register */
-	HOSTA_ALL_WC_BIT = (HOSTA_FINTR | HOSTA_ANY_ERROR | HOSTA_BDS),
-};
-
-enum enhanced_i2c_host_status {
-	/* ACK receive */
-	E_HOSTA_ACK = 0x01,
-	/* Interrupt pending */
-	E_HOSTA_INTP = 0x02,
-	/* Read/Write */
-	E_HOSTA_RW = 0x04,
-	/* Time out error */
-	E_HOSTA_TMOE = 0x08,
-	/* Arbitration lost */
-	E_HOSTA_ARB = 0x10,
-	/* Bus busy */
-	E_HOSTA_BB = 0x20,
-	/* Address match */
-	E_HOSTA_AM = 0x40,
-	/* Byte done status */
-	E_HOSTA_BDS = 0x80,
-	/* time out or lost arbitration */
-	E_HOSTA_ANY_ERROR = (E_HOSTA_TMOE | E_HOSTA_ARB),
-	/* Byte transfer done and ACK receive */
-	E_HOSTA_BDS_AND_ACK = (E_HOSTA_BDS | E_HOSTA_ACK),
-};
-
-enum enhanced_i2c_ctl {
-	/* Hardware reset */
-	E_HW_RST = 0x01,
-	/* Stop */
-	E_STOP = 0x02,
-	/* Start & Repeat start */
-	E_START = 0x04,
-	/* Acknowledge */
-	E_ACK = 0x08,
-	/* State reset */
-	E_STS_RST = 0x10,
-	/* Mode select */
-	E_MODE_SEL = 0x20,
-	/* I2C interrupt enable */
-	E_INT_EN = 0x40,
-	/* 0 : Standard mode , 1 : Receive mode */
-	E_RX_MODE = 0x80,
-	/* State reset and hardware reset */
-	E_STS_AND_HW_RST = (E_STS_RST | E_HW_RST),
-	/* Generate start condition and transmit peripheral address */
-	E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST),
-	/* Generate stop condition */
-	E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST),
-};
-
-enum i2c_reset_cause {
-	I2C_RC_NO_IDLE_FOR_START = 1,
-	I2C_RC_TIMEOUT,
-};
-
-struct i2c_ch_freq {
-	int kbps;
-	uint8_t freq_set;
-};
-
-static const struct i2c_ch_freq i2c_freq_select[] = {
-	{ 50,   1},
-	{ 100,  2},
-	{ 400,  3},
-	{ 1000, 4},
-};
-
-struct i2c_pin {
-	volatile uint8_t *pin_clk;
-	volatile uint8_t *pin_data;
-	volatile uint8_t *pin_clk_ctrl;
-	volatile uint8_t *pin_data_ctrl;
-	volatile uint8_t *mirror_clk;
-	volatile uint8_t *mirror_data;
-	uint8_t clk_mask;
-	uint8_t data_mask;
-};
-
-static const struct i2c_pin i2c_pin_regs[] = {
-	{ &IT83XX_GPIO_GPCRB3, &IT83XX_GPIO_GPCRB4,
-		&IT83XX_GPIO_GPDRB, &IT83XX_GPIO_GPDRB,
-		&IT83XX_GPIO_GPDMRB, &IT83XX_GPIO_GPDMRB,
-		0x08, 0x10},
-	{ &IT83XX_GPIO_GPCRC1, &IT83XX_GPIO_GPCRC2,
-		&IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRC,
-		&IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRC,
-		0x02, 0x04},
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-	{ &IT83XX_GPIO_GPCRC7, &IT83XX_GPIO_GPCRF7,
-		&IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRF,
-		&IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRF,
-		0x80, 0x80},
-#else
-	{ &IT83XX_GPIO_GPCRF6, &IT83XX_GPIO_GPCRF7,
-		&IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDRF,
-		&IT83XX_GPIO_GPDMRF, &IT83XX_GPIO_GPDMRF,
-		0x40, 0x80},
-#endif
-	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2,
-		&IT83XX_GPIO_GPDRH, &IT83XX_GPIO_GPDRH,
-		&IT83XX_GPIO_GPDMRH, &IT83XX_GPIO_GPDMRH,
-		0x02, 0x04},
-	{ &IT83XX_GPIO_GPCRE0, &IT83XX_GPIO_GPCRE7,
-		&IT83XX_GPIO_GPDRE, &IT83XX_GPIO_GPDRE,
-		&IT83XX_GPIO_GPDMRE, &IT83XX_GPIO_GPDMRE,
-		0x01, 0x80},
-	{ &IT83XX_GPIO_GPCRA4, &IT83XX_GPIO_GPCRA5,
-		&IT83XX_GPIO_GPDRA, &IT83XX_GPIO_GPDRA,
-		&IT83XX_GPIO_GPDMRA, &IT83XX_GPIO_GPDMRA,
-		0x10, 0x20},
-};
-
-struct i2c_ctrl_t {
-	uint8_t irq;
-	enum clock_gate_offsets clock_gate;
-	int reg_shift;
-};
-
-const struct i2c_ctrl_t i2c_ctrl_regs[] = {
-	{IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA, -1},
-	{IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB, -1},
-	{IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC, -1},
-	{IT83XX_IRQ_SMB_D, CGC_OFFSET_SMBD, 3},
-	{IT83XX_IRQ_SMB_E, CGC_OFFSET_SMBE, 0},
-	{IT83XX_IRQ_SMB_F, CGC_OFFSET_SMBF, 1},
-};
-
-enum i2c_ch_status {
-	I2C_CH_NORMAL = 0,
-	I2C_CH_REPEAT_START,
-	I2C_CH_WAIT_READ,
-	I2C_CH_WAIT_NEXT_XFER,
-};
-
-/* I2C port state data */
-struct i2c_port_data {
-	const uint8_t *out;  /* Output data pointer */
-	int out_size;        /* Output data to transfer, in bytes */
-	uint8_t *in;         /* Input data pointer */
-	int in_size;         /* Input data to transfer, in bytes */
-	int flags;           /* Flags (I2C_XFER_*) */
-	int widx;            /* Index into output data */
-	int ridx;            /* Index into input data */
-	int err;             /* Error code, if any */
-	uint8_t addr_8bit;   /* address of device */
-	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
-	uint8_t freq;        /* Frequency setting */
-
-	enum i2c_ch_status i2ccs;
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	volatile int task_waiting;
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-static int i2c_ch_reg_shift(int p)
-{
-	/*
-	 * only enhanced port needs to be changed the parameter of registers
-	 */
-	ASSERT(p >= I2C_STANDARD_PORT_COUNT && p < I2C_PORT_COUNT);
-
-	/*
-	 * The registers of i2c enhanced ports are not sequential.
-	 * This routine transfers the i2c port number to related
-	 * parameter of registers.
-	 *
-	 * IT83xx chip : i2c enhanced ports - channel D,E,F
-	 * channel D registers : 0x3680 ~ 0x36FF
-	 * channel E registers : 0x3500 ~ 0x357F
-	 * channel F registers : 0x3580 ~ 0x35FF
-	 */
-	return i2c_ctrl_regs[p].reg_shift;
-}
-
-static void i2c_reset(int p, int cause)
-{
-	int p_ch;
-
-	if (p < I2C_STANDARD_PORT_COUNT) {
-		/* bit1, kill current transaction. */
-		IT83XX_SMB_HOCTL(p) = 0x2;
-		IT83XX_SMB_HOCTL(p) = 0;
-		/* W/C host status register */
-		IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT;
-	} else {
-		/* Shift register */
-		p_ch = i2c_ch_reg_shift(p);
-		/* State reset and hardware reset */
-		IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
-	}
-	CPRINTS("I2C ch%d reset cause %d", p, cause);
-}
-
-static void i2c_r_last_byte(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-
-	/*
-	 * bit5, The firmware shall write 1 to this bit
-	 * when the next byte will be the last byte for i2c read.
-	 */
-	if ((pd->flags & I2C_XFER_STOP) && (pd->ridx == pd->in_size - 1))
-		IT83XX_SMB_HOCTL(p) |= 0x20;
-}
-
-static void i2c_w2r_change_direction(int p)
-{
-	/* I2C switch direction */
-	if (IT83XX_SMB_HOCTL2(p) & 0x08) {
-		i2c_r_last_byte(p);
-		IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-	} else {
-		/*
-		 * bit2, I2C switch direction wait.
-		 * bit3, I2C switch direction enable.
-		 */
-		IT83XX_SMB_HOCTL2(p) |= 0x0C;
-		IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-		i2c_r_last_byte(p);
-		IT83XX_SMB_HOCTL2(p) &= ~0x04;
-	}
-}
-
-static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct,
-			       uint8_t data, int first_byte)
-{
-	struct i2c_port_data *pd = pdata + p;
-	int p_ch;
-	int nack = 0;
-
-	/* Shift register */
-	p_ch = i2c_ch_reg_shift(p);
-
-	if (first_byte) {
-		/* First byte must be peripheral address. */
-		IT83XX_I2C_DTR(p_ch) =
-			data | (direct == RX_DIRECT ? BIT(0) : 0);
-		/* start or repeat start signal. */
-		IT83XX_I2C_CTR(p_ch) = E_START_ID;
-	} else {
-		if (direct == TX_DIRECT)
-			/* Transmit data */
-			IT83XX_I2C_DTR(p_ch) = data;
-		else {
-			/*
-			 * Receive data.
-			 * Last byte should be NACK in the end of read cycle
-			 */
-			if (((pd->ridx + 1) == pd->in_size) &&
-				(pd->flags & I2C_XFER_STOP))
-				nack = 1;
-		}
-		/* Set hardware reset to start next transmission */
-		IT83XX_I2C_CTR(p_ch) =
-			E_INT_EN | E_MODE_SEL | E_HW_RST | (nack ? 0 : E_ACK);
-	}
-}
-
-static int i2c_tran_write(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-
-	if (pd->flags & I2C_XFER_START) {
-		/* i2c enable */
-		IT83XX_SMB_HOCTL2(p) = 0x13;
-		/*
-		 * bit0, Direction of the host transfer.
-		 * bit[1:7}, Address of the targeted peripheral.
-		 */
-		IT83XX_SMB_TRASLA(p) = pd->addr_8bit;
-		/* Send first byte */
-		IT83XX_SMB_HOBDB(p) = *(pd->out++);
-		pd->widx++;
-		/* clear start flag */
-		pd->flags &= ~I2C_XFER_START;
-		/*
-		 * bit0, Host interrupt enable.
-		 * bit[2:4}, Extend command.
-		 * bit6, start.
-		 */
-		IT83XX_SMB_HOCTL(p) = 0x5D;
-	} else {
-		/* Host has completed the transmission of a byte */
-		if (IT83XX_SMB_HOSTA(p) & HOSTA_BDS) {
-			if (pd->widx < pd->out_size) {
-				/* Send next byte */
-				IT83XX_SMB_HOBDB(p) = *(pd->out++);
-				pd->widx++;
-				/* W/C byte done for next byte */
-				IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-				if (pd->i2ccs == I2C_CH_REPEAT_START) {
-					pd->i2ccs = I2C_CH_NORMAL;
-					task_enable_irq(i2c_ctrl_regs[p].irq);
-				}
-			} else {
-				/* done */
-				pd->out_size = 0;
-				if (pd->in_size > 0) {
-					/* write to read */
-					i2c_w2r_change_direction(p);
-				} else {
-					if (pd->flags & I2C_XFER_STOP) {
-						/* set I2C_EN = 0 */
-						IT83XX_SMB_HOCTL2(p) = 0x11;
-						/* W/C byte done for finish */
-						IT83XX_SMB_HOSTA(p) =
-							HOSTA_NEXT_BYTE;
-					} else {
-						pd->i2ccs = I2C_CH_REPEAT_START;
-						return 0;
-					}
-				}
-			}
-		}
-	}
-	return 1;
-}
-
-static int i2c_tran_read(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-
-	if (pd->flags & I2C_XFER_START) {
-		/* i2c enable */
-		IT83XX_SMB_HOCTL2(p) = 0x13;
-		/*
-		 * bit0, Direction of the host transfer.
-		 * bit[1:7}, Address of the targeted peripheral.
-		 */
-		IT83XX_SMB_TRASLA(p) = pd->addr_8bit | 0x01;
-		/* clear start flag */
-		pd->flags &= ~I2C_XFER_START;
-		/*
-		 * bit0, Host interrupt enable.
-		 * bit[2:4}, Extend command.
-		 * bit5, The firmware shall write 1 to this bit
-		 *       when the next byte will be the last byte.
-		 * bit6, start.
-		 */
-		if ((1 == pd->in_size) && (pd->flags & I2C_XFER_STOP))
-			IT83XX_SMB_HOCTL(p) = 0x7D;
-		else
-			IT83XX_SMB_HOCTL(p) = 0x5D;
-	} else {
-		if ((pd->i2ccs == I2C_CH_REPEAT_START) ||
-			(pd->i2ccs == I2C_CH_WAIT_READ)) {
-			if (pd->i2ccs == I2C_CH_REPEAT_START) {
-				/* write to read */
-				i2c_w2r_change_direction(p);
-			} else {
-				/* For last byte */
-				i2c_r_last_byte(p);
-				/* W/C for next byte */
-				IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-			}
-			pd->i2ccs = I2C_CH_NORMAL;
-			task_enable_irq(i2c_ctrl_regs[p].irq);
-		} else if (IT83XX_SMB_HOSTA(p) & HOSTA_BDS) {
-			if (pd->ridx < pd->in_size) {
-				/* To get received data. */
-				*(pd->in++) = IT83XX_SMB_HOBDB(p);
-				pd->ridx++;
-				/* For last byte */
-				i2c_r_last_byte(p);
-				/* done */
-				if (pd->ridx == pd->in_size) {
-					pd->in_size = 0;
-					if (pd->flags & I2C_XFER_STOP) {
-						/* W/C for finish */
-						IT83XX_SMB_HOSTA(p) =
-							HOSTA_NEXT_BYTE;
-					} else {
-						pd->i2ccs = I2C_CH_WAIT_READ;
-						return 0;
-					}
-				} else {
-					/* W/C for next byte */
-					IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-				}
-			}
-		}
-	}
-	return 1;
-}
-
-static void enhanced_i2c_start(int p)
-{
-	/* Shift register */
-	int p_ch = i2c_ch_reg_shift(p);
-
-	/* State reset and hardware reset */
-	IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
-	/* Set i2c frequency */
-	IT83XX_I2C_PSR(p_ch) = pdata[p].freq;
-	IT83XX_I2C_HSPR(p_ch) = pdata[p].freq;
-	/*
-	 * Set time out register.
-	 * I2C D/E/F clock/data low timeout.
-	 */
-	IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT;
-	/* bit1: Enable enhanced i2c module */
-	IT83XX_I2C_CTR1(p_ch) = BIT(1);
-}
-
-static int enhanced_i2c_tran_write(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-	uint8_t out_data;
-	int p_ch;
-
-	/* Shift register */
-	p_ch = i2c_ch_reg_shift(p);
-
-	if (pd->flags & I2C_XFER_START) {
-		/* Clear start bit */
-		pd->flags &= ~I2C_XFER_START;
-		enhanced_i2c_start(p);
-		/* Send ID */
-		i2c_pio_trans_data(p, TX_DIRECT, pd->addr_8bit, 1);
-	} else {
-		/* Host has completed the transmission of a byte */
-		if (pd->widx < pd->out_size) {
-			out_data = *(pd->out++);
-			pd->widx++;
-
-			/* Send Byte */
-			i2c_pio_trans_data(p, TX_DIRECT, out_data, 0);
-			if (pd->i2ccs == I2C_CH_WAIT_NEXT_XFER) {
-				pd->i2ccs = I2C_CH_NORMAL;
-				task_enable_irq(i2c_ctrl_regs[p].irq);
-			}
-		} else {
-			/* done */
-			pd->out_size = 0;
-			if (pd->in_size > 0) {
-				/* Write to read protocol */
-				pd->i2ccs = I2C_CH_REPEAT_START;
-				/* Repeat Start */
-				i2c_pio_trans_data(p, RX_DIRECT,
-						   pd->addr_8bit, 1);
-			} else {
-				if (pd->flags & I2C_XFER_STOP) {
-					IT83XX_I2C_CTR(p_ch) = E_FINISH;
-					/* wait for stop bit interrupt*/
-					return 1;
-				}
-				/* Direct write with direct read */
-				pd->i2ccs = I2C_CH_WAIT_NEXT_XFER;
-				return 0;
-			}
-		}
-	}
-	return 1;
-}
-
-static int enhanced_i2c_tran_read(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-	uint8_t in_data = 0;
-	int p_ch;
-
-	/* Shift register */
-	p_ch = i2c_ch_reg_shift(p);
-
-	if (pd->flags & I2C_XFER_START) {
-		/* clear start flag */
-		pd->flags &= ~I2C_XFER_START;
-		enhanced_i2c_start(p);
-		/* Direct read  */
-		pd->i2ccs = I2C_CH_WAIT_READ;
-		/* Send ID */
-		i2c_pio_trans_data(p, RX_DIRECT, pd->addr_8bit, 1);
-	} else {
-		if (pd->i2ccs) {
-			if (pd->i2ccs == I2C_CH_REPEAT_START) {
-				pd->i2ccs = I2C_CH_NORMAL;
-				/* Receive data */
-				i2c_pio_trans_data(p, RX_DIRECT, in_data, 0);
-			} else if (pd->i2ccs == I2C_CH_WAIT_READ) {
-				pd->i2ccs = I2C_CH_NORMAL;
-				/* Receive data */
-				i2c_pio_trans_data(p, RX_DIRECT, in_data, 0);
-				/* Turn on irq before next direct read */
-				task_enable_irq(i2c_ctrl_regs[p].irq);
-			} else {
-				/* Write to read */
-				pd->i2ccs = I2C_CH_WAIT_READ;
-				/* Send ID */
-				i2c_pio_trans_data(p, RX_DIRECT,
-						   pd->addr_8bit, 1);
-				task_enable_irq(i2c_ctrl_regs[p].irq);
-			}
-		} else {
-			if (pd->ridx < pd->in_size) {
-				/* read data */
-				*(pd->in++) = IT83XX_I2C_DRR(p_ch);
-				pd->ridx++;
-
-				/* done */
-				if (pd->ridx == pd->in_size) {
-					pd->in_size = 0;
-					if (pd->flags & I2C_XFER_STOP) {
-						pd->i2ccs = I2C_CH_NORMAL;
-						IT83XX_I2C_CTR(p_ch) = E_FINISH;
-						/* wait for stop bit interrupt*/
-						return 1;
-					}
-					/* End the transaction */
-					pd->i2ccs = I2C_CH_WAIT_READ;
-					return 0;
-				}
-				/* read next byte */
-				i2c_pio_trans_data(p, RX_DIRECT, in_data, 0);
-			}
-		}
-	}
-	return 1;
-}
-
-static int enhanced_i2c_error(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-	/* Shift register */
-	int p_ch = i2c_ch_reg_shift(p);
-	int i2c_str = IT83XX_I2C_STR(p_ch);
-
-	if (i2c_str & E_HOSTA_ANY_ERROR) {
-		pd->err = i2c_str & E_HOSTA_ANY_ERROR;
-	/* device does not respond ACK */
-	} else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) {
-		if (IT83XX_I2C_CTR(p_ch) & E_ACK)
-			pd->err = E_HOSTA_ACK;
-	}
-
-	return pd->err;
-}
-
-static int i2c_transaction(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-	int p_ch;
-
-	if (p < I2C_STANDARD_PORT_COUNT) {
-		/* any error */
-		if (IT83XX_SMB_HOSTA(p) & HOSTA_ANY_ERROR) {
-			pd->err = (IT83XX_SMB_HOSTA(p) & HOSTA_ANY_ERROR);
-		} else {
-			/* i2c write */
-			if (pd->out_size)
-				return i2c_tran_write(p);
-			/* i2c read */
-			else if (pd->in_size)
-				return i2c_tran_read(p);
-			/* wait finish */
-			if (!(IT83XX_SMB_HOSTA(p) & HOSTA_FINTR))
-				return 1;
-		}
-		/* W/C */
-		IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT;
-		/* disable the SMBus host interface */
-		IT83XX_SMB_HOCTL2(p) = 0x00;
-	} else {
-		/* no error */
-		if (!(enhanced_i2c_error(p))) {
-			/* i2c write */
-			if (pd->out_size)
-				return enhanced_i2c_tran_write(p);
-			/* i2c read */
-			else if (pd->in_size)
-				return enhanced_i2c_tran_read(p);
-		}
-		p_ch = i2c_ch_reg_shift(p);
-		IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
-		IT83XX_I2C_CTR1(p_ch) = 0;
-	}
-	/* done doing work */
-	return 0;
-}
-
-int i2c_is_busy(int port)
-{
-	int p_ch;
-
-	if (port < I2C_STANDARD_PORT_COUNT)
-		return (IT83XX_SMB_HOSTA(port) &
-			(HOSTA_HOBY | HOSTA_ALL_WC_BIT));
-
-	p_ch = i2c_ch_reg_shift(port);
-	return (IT83XX_I2C_STR(p_ch) & E_HOSTA_BB);
-}
-
-int chip_i2c_xfer(int port, uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	struct i2c_port_data *pd = pdata + port;
-	uint32_t events = 0;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	/*
-	 * Make the below i2c transaction work:
-	 * - i2c_xfer with I2C_XFER_START flag
-	 * - i2c_xfer with I2C_XFER_START flag
-	 * - xxx
-	 * - i2c_xfer with I2C_XFER_STOP flag
-	 */
-	if (pd->i2ccs)
-		flags &= ~I2C_XFER_START;
-
-	/* Copy data to port struct */
-	pd->out = out;
-	pd->out_size = out_size;
-	pd->in = in;
-	pd->in_size = in_size;
-	pd->flags = flags;
-	pd->widx = 0;
-	pd->ridx = 0;
-	pd->err = 0;
-	pd->addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
-
-	/* Make sure we're in a good state to start */
-	if ((flags & I2C_XFER_START) && (i2c_is_busy(port)
-		|| (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
-
-		/* Attempt to unwedge the port. */
-		pd->err = i2c_unwedge(port);
-
-		/* reset i2c port */
-		i2c_reset(port, I2C_RC_NO_IDLE_FOR_START);
-
-		/* Return if port is still wedged */
-		if (pd->err)
-			return pd->err;
-	}
-
-	pd->task_waiting = task_get_current();
-	if (pd->flags & I2C_XFER_START) {
-		pd->i2ccs = I2C_CH_NORMAL;
-		/* enable i2c interrupt */
-		task_clear_pending_irq(i2c_ctrl_regs[port].irq);
-		task_enable_irq(i2c_ctrl_regs[port].irq);
-	}
-	/* Start transaction */
-	i2c_transaction(port);
-	/* Wait for transfer complete or timeout */
-	events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, pd->timeout_us);
-	/* disable i2c interrupt */
-	task_disable_irq(i2c_ctrl_regs[port].irq);
-	pd->task_waiting = TASK_ID_INVALID;
-
-	/* Handle timeout */
-	if (!(events & TASK_EVENT_I2C_IDLE)) {
-		pd->err = EC_ERROR_TIMEOUT;
-		/* reset i2c port */
-		i2c_reset(port, I2C_RC_TIMEOUT);
-	}
-
-	/* reset i2c channel status */
-	if (pd->err)
-		pd->i2ccs = I2C_CH_NORMAL;
-
-	return pd->err;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return !!(*i2c_pin_regs[port].mirror_clk &
-			i2c_pin_regs[port].clk_mask);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return !!(*i2c_pin_regs[port].mirror_data &
-			i2c_pin_regs[port].data_mask);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	int pin_sts = 0;
-
-	if (port < I2C_STANDARD_PORT_COUNT)
-		return IT83XX_SMB_SMBPCTL(port) & 0x03;
-
-	if (*i2c_pin_regs[port].mirror_clk & i2c_pin_regs[port].clk_mask)
-		pin_sts |= I2C_LINE_SCL_HIGH;
-	if (*i2c_pin_regs[port].mirror_data & i2c_pin_regs[port].data_mask)
-		pin_sts |= I2C_LINE_SDA_HIGH;
-
-	return pin_sts;
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-void i2c_interrupt(int port)
-{
-	int id = pdata[port].task_waiting;
-
-	/* Clear the interrupt status */
-	task_clear_pending_irq(i2c_ctrl_regs[port].irq);
-
-	/* If no task is waiting, just return */
-	if (id == TASK_ID_INVALID)
-		return;
-
-	/* If done doing work, wake up the task waiting for the transfer */
-	if (!i2c_transaction(port)) {
-		task_disable_irq(i2c_ctrl_regs[port].irq);
-		task_set_event(id, TASK_EVENT_I2C_IDLE);
-	}
-}
-
-/*
- * Set i2c standard port (A, B, or C) runs at 400kHz by using timing registers
- * (offset 0h ~ 7h).
- */
-static void i2c_standard_port_timing_regs_400khz(int port)
-{
-	/* Port clock frequency depends on setting of timing registers. */
-	IT83XX_SMB_SCLKTS(port) = 0;
-	/* Suggested setting of timing registers of 400kHz. */
-	IT83XX_SMB_4P7USL = 0x6;
-	IT83XX_SMB_4P0USL = 0;
-	IT83XX_SMB_300NS = 0x1;
-	IT83XX_SMB_250NS = 0x2;
-	IT83XX_SMB_45P3USL = 0x6a;
-	IT83XX_SMB_45P3USH = 0x1;
-	IT83XX_SMB_4P7A4P0H = 0;
-}
-
-/* Set clock frequency for i2c port A, B , or C */
-static void i2c_standard_port_set_frequency(int port, int freq_khz)
-{
-	/*
-	 * If port's clock frequency is 400kHz, we use timing registers
-	 * for setting. So we can adjust tlow to meet timing.
-	 * The others use basic 50/100/1000 KHz setting.
-	 */
-	if (freq_khz == 400) {
-		i2c_standard_port_timing_regs_400khz(port);
-	} else {
-		for (int f = ARRAY_SIZE(i2c_freq_select) - 1; f >= 0; f--) {
-			if (freq_khz >= i2c_freq_select[f].kbps) {
-				IT83XX_SMB_SCLKTS(port) =
-						i2c_freq_select[f].freq_set;
-				break;
-			}
-		}
-	}
-
-	/* This field defines the SMCLK0/1/2 clock/data low timeout. */
-	IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
-}
-
-/* Set clock frequency for i2c port D, E , or F */
-static void i2c_enhanced_port_set_frequency(int port, int freq_khz)
-{
-	int port_reg_shift, clk_div, psr;
-
-	/* Get base address of i2c enhanced port's registers. */
-	port_reg_shift = i2c_ch_reg_shift(port);
-	/*
-	 * Let psr(Prescale) = IT83XX_I2C_PSR(port_reg_shift)
-	 * Then, 1 SCL cycle = 2 x (psr + 2) x SMBus clock cycle
-	 * SMBus clock = PLL_CLOCK / clk_div
-	 * SMBus clock cycle = 1 / SMBus clock
-	 * 1 SCL cycle = 1 / (1000 x freq)
-	 * 1 / (1000 x freq) = 2 x (psr + 2) x (1 / (PLL_CLOCK / clk_div))
-	 * psr = ((PLL_CLOCK / clk_div) x (1 / (1000 x freq)) x (1 / 2)) - 2
-	 */
-	if (freq_khz) {
-		/* Get SMBus clock divide value */
-		clk_div = (IT83XX_ECPM_SCDCR2 & 0x0F) + 1;
-		/* Calculate PSR value */
-		psr = (PLL_CLOCK / (clk_div * (2 * 1000 * freq_khz))) - 2;
-		/* Set psr value under 0xFD */
-		if (psr > 0xFD)
-			psr = 0xFD;
-
-		/* Set I2C Speed */
-		IT83XX_I2C_PSR(port_reg_shift) = (psr & 0xFF);
-		IT83XX_I2C_HSPR(port_reg_shift) = (psr & 0xFF);
-		/* Backup */
-		pdata[port].freq = (psr & 0xFF);
-	}
-}
-
-static void i2c_freq_changed(void)
-{
-	int i, freq, port;
-
-	/* Set clock frequency for I2C ports */
-	for (i = 0; i < i2c_ports_used; i++) {
-		freq = i2c_ports[i].kbps;
-		port = i2c_ports[i].port;
-		if (port < I2C_STANDARD_PORT_COUNT)
-			i2c_standard_port_set_frequency(port, freq);
-		else
-			i2c_enhanced_port_set_frequency(port, freq);
-	}
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT);
-
-void i2c_init(void)
-{
-	int i, p, p_ch;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-	/* bit7, 0: SMCLK2 is located on GPF6, 1: SMCLK2 is located on GPC7 */
-	IT83XX_GPIO_GRC7 |= 0x80;
-#endif
-
-	/* Enable I2C function. */
-	for (i = 0; i < i2c_ports_used; i++) {
-		/* I2c port mapping. */
-		p = i2c_ports[i].port;
-
-		clock_enable_peripheral(i2c_ctrl_regs[p].clock_gate, 0, 0);
-
-		if (p < I2C_STANDARD_PORT_COUNT) {
-			/*
-			 * bit0, The SMBus host interface is enabled.
-			 * bit1, Enable to communicate with I2C device
-			 *        and support I2C-compatible cycles.
-			 * bit4, This bit controls the reset mechanism
-			 *        of SMBus master to handle the SMDAT
-			 *        line low if 25ms reg timeout.
-			 */
-			IT83XX_SMB_HOCTL2(p) = 0x11;
-			/*
-			 * bit1, Kill SMBus host transaction.
-			 * bit0, Enable the interrupt for the master interface.
-			 */
-			IT83XX_SMB_HOCTL(p) = 0x03;
-			IT83XX_SMB_HOCTL(p) = 0x01;
-			/* W/C host status register */
-			IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT;
-			IT83XX_SMB_HOCTL2(p) = 0x00;
-		} else {
-			/* Shift register */
-			p_ch = i2c_ch_reg_shift(p);
-			switch (p) {
-			case IT83XX_I2C_CH_D:
-				#ifndef CONFIG_UART_HOST
-				/* Enable SMBus D channel */
-				IT83XX_GPIO_GRC2 |= 0x20;
-				#endif
-				break;
-			case IT83XX_I2C_CH_E:
-				/* Enable SMBus E channel */
-				IT83XX_GCTRL_PMER1 |= 0x01;
-				break;
-			case IT83XX_I2C_CH_F:
-				/* Enable SMBus F channel */
-				IT83XX_GCTRL_PMER1 |= 0x02;
-				break;
-			}
-			/* Software reset */
-			IT83XX_I2C_DHTR(p_ch) |= 0x80;
-			IT83XX_I2C_DHTR(p_ch) &= 0x7F;
-			/* State reset and hardware reset */
-			IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
-			/* bit1, Module enable */
-			IT83XX_I2C_CTR1(p_ch) = 0;
-		}
-		pdata[i].task_waiting = TASK_ID_INVALID;
-	}
-
-	i2c_freq_changed();
-
-	for (i = 0; i < I2C_PORT_COUNT; i++) {
-		/* Use default timeout */
-		i2c_set_timeout(i, 0);
-	}
-}
diff --git a/chip/it83xx/i2c_peripheral.c b/chip/it83xx/i2c_peripheral.c
deleted file mode 100644
index 91eb2c1dfb..0000000000
--- a/chip/it83xx/i2c_peripheral.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C module for Chrome EC */
-#include "clock.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c_peripheral.h"
-#include "registers.h"
-#include <stddef.h>
-#include <string.h>
-#include "task.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* The size must be a power of 2 */
-#define I2C_MAX_BUFFER_SIZE 0x100
-#define I2C_SIZE_MASK (I2C_MAX_BUFFER_SIZE - 1)
-
-#define I2C_READ_MAXFIFO_DATA 16
-#define I2C_ENHANCED_CH_INTERVAL 0x80
-
-/* Store controller to peripheral data of channel D, E, F by DMA */
-static uint8_t in_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
-			__attribute__((section(".h2ram.pool.i2cslv")));
-/* Store peripheral to controller data of channel D, E, F by DMA */
-static uint8_t out_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
-			__attribute__((section(".h2ram.pool.i2cslv")));
-/* Store read and write data of channel A by FIFO mode */
-static uint8_t pbuffer[I2C_MAX_BUFFER_SIZE];
-
-static uint32_t w_index;
-static uint32_t r_index;
-static int wr_done[I2C_ENHANCED_PORT_COUNT];
-
-void buffer_index_reset(void)
-{
-	/* Reset write buffer index */
-	w_index = 0;
-	/* Reset read buffer index */
-	r_index = 0;
-}
-
-/* Data structure to define I2C peripheral control configuration. */
-struct i2c_periph_ctrl_t {
-	int irq;              /* peripheral irq */
-	/* offset from base 0x00F03500 register; -1 means unused. */
-	int offset;
-	enum clock_gate_offsets clock_gate;
-	int dma_index;
-};
-
-/* I2C peripheral control */
-const struct i2c_periph_ctrl_t i2c_periph_ctrl[] = {
-	[IT83XX_I2C_CH_A] = {.irq = IT83XX_IRQ_SMB_A, .offset = -1,
-		.clock_gate = CGC_OFFSET_SMBA, .dma_index = -1},
-	[IT83XX_I2C_CH_D] = {.irq = IT83XX_IRQ_SMB_D, .offset = 0x180,
-		.clock_gate = CGC_OFFSET_SMBD, .dma_index = 0},
-	[IT83XX_I2C_CH_E] = {.irq = IT83XX_IRQ_SMB_E, .offset = 0x0,
-		.clock_gate = CGC_OFFSET_SMBE, .dma_index = 1},
-	[IT83XX_I2C_CH_F] = {.irq = IT83XX_IRQ_SMB_F, .offset = 0x80,
-		.clock_gate = CGC_OFFSET_SMBF, .dma_index = 2},
-};
-
-void i2c_peripheral_read_write_data(int port)
-{
-	int periph_status, i;
-
-	/* I2C peripheral channel A FIFO mode */
-	if (port < I2C_STANDARD_PORT_COUNT) {
-		int count;
-
-		periph_status = IT83XX_SMB_SLSTA;
-
-		/* bit0-4 : FIFO byte count */
-		count = IT83XX_SMB_SFFSTA & 0x1F;
-
-		/* Peripheral data register is waiting for read or write. */
-		if (periph_status & IT83XX_SMB_SDS) {
-			/* Controller to read data */
-			if (periph_status & IT83XX_SMB_RCS) {
-				for (i = 0; i < I2C_READ_MAXFIFO_DATA; i++)
-					/* Return buffer data to controller */
-					IT83XX_SMB_SLDA =
-					pbuffer[(i + r_index) & I2C_SIZE_MASK];
-
-				/* Index to next 16 bytes of read buffer */
-				r_index += I2C_READ_MAXFIFO_DATA;
-			}
-			/* Controller to write data */
-			else {
-				/* FIFO Full */
-				if (IT83XX_SMB_SFFSTA & IT83XX_SMB_SFFFULL) {
-					for (i = 0; i < count; i++)
-				/* Get data from controller to buffer */
-						pbuffer[(w_index + i) &
-					I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
-				}
-
-				/* Index to next byte of write buffer */
-				w_index += count;
-			}
-		}
-		/* Stop condition, indicate stop condition detected. */
-		if (periph_status & IT83XX_SMB_SPDS) {
-			/* Read data less 16 bytes status */
-			if (periph_status & IT83XX_SMB_RCS) {
-				/* Disable FIFO mode to clear left count */
-				IT83XX_SMB_SFFCTL &= ~IT83XX_SMB_SAFE;
-
-				/* Peripheral A FIFO Enable */
-				IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
-			}
-			/* Controller to write data */
-			else {
-				for (i = 0; i < count; i++)
-					/* Get data from controller to buffer */
-					pbuffer[(i + w_index) &
-					I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
-			}
-
-			/* Reset read and write buffer index */
-			buffer_index_reset();
-		}
-		/* Peripheral time status, timeout status occurs. */
-		if (periph_status & IT83XX_SMB_STS) {
-			/* Reset read and write buffer index */
-			buffer_index_reset();
-		}
-
-		/* Write clear the peripheral status */
-		IT83XX_SMB_SLSTA = periph_status;
-	}
-	/* Enhanced I2C peripheral channel D, E, F DMA mode */
-	else {
-		int ch, idx;
-
-		/* Get enhanced i2c channel */
-		ch = i2c_periph_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
-
-		idx = i2c_periph_ctrl[port].dma_index;
-
-		/* Interrupt pending */
-		if (IT83XX_I2C_STR(ch) & IT83XX_I2C_INTPEND) {
-
-			periph_status = IT83XX_I2C_IRQ_ST(ch);
-
-			/* Controller to read data */
-			if (periph_status & IT83XX_I2C_IDR_CLR) {
-			/*
-			 * TODO(b:129360157): Return buffer data by
-			 * "out_data" array.
-			 * Ex: Write data to buffer from 0x00 to 0xFF
-			 */
-				for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++)
-					out_data[idx][i] = i;
-			}
-			/* Controller to write data */
-			if (periph_status & IT83XX_I2C_IDW_CLR) {
-				/* Controller to write data finish flag */
-				wr_done[idx] = 1;
-			}
-			/* Peripheral finish */
-			if (periph_status & IT83XX_I2C_P_CLR) {
-				if (wr_done[idx]) {
-			/*
-			 * TODO(b:129360157): Handle controller write
-			 * data by "in_data" array.
-			 */
-					CPRINTS("WData: %ph",
-						HEX_BUF(in_data[idx],
-							I2C_MAX_BUFFER_SIZE));
-					wr_done[idx] = 0;
-				}
-			}
-
-			/* Write clear the peripheral status */
-			IT83XX_I2C_IRQ_ST(ch) = periph_status;
-		}
-
-		/* Hardware reset */
-		IT83XX_I2C_CTR(ch) |= IT83XX_I2C_HALT;
-	}
-}
-
-void i2c_periph_interrupt(int port)
-{
-	/* Peripheral to read and write fifo data */
-	i2c_peripheral_read_write_data(port);
-
-	/* Clear the interrupt status */
-	task_clear_pending_irq(i2c_periph_ctrl[port].irq);
-}
-
-void i2c_peripheral_enable(int port, uint8_t periph_addr)
-{
-
-	clock_enable_peripheral(i2c_periph_ctrl[port].clock_gate, 0, 0);
-
-	/* I2C peripheral channel A FIFO mode */
-	if (port < I2C_STANDARD_PORT_COUNT) {
-
-		/* This field defines the SMCLK0/1/2 clock/data low timeout. */
-		IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
-
-		/* bit0 : Peripheral A FIFO Enable */
-		IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
-
-		/*
-		 * bit1 : Peripheral interrupt enable.
-		 * bit2 : SMCLK/SMDAT will be released if timeout.
-		 * bit3 : Peripheral detect STOP condition interrupt enable.
-		 */
-		IT83XX_SMB_SICR = 0x0E;
-
-		/* Peripheral address 1 */
-		IT83XX_SMB_RESLADR = periph_addr;
-
-		/* Write clear all peripheral status */
-		IT83XX_SMB_SLSTA = 0xE7;
-
-		/* bit5 : Enable the SMBus peripheral device */
-		IT83XX_SMB_HOCTL2(port) |= IT83XX_SMB_SLVEN;
-	}
-	/* Enhanced I2C peripheral channel D, E, F DMA mode */
-	else {
-		int ch, idx;
-		uint32_t in_data_addr, out_data_addr;
-
-		/* Get enhanced i2c channel */
-		ch = i2c_periph_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
-
-		idx = i2c_periph_ctrl[port].dma_index;
-
-		switch (port) {
-		case IT83XX_I2C_CH_D:
-			/* Enable I2C D channel */
-			IT83XX_GPIO_GRC2 |= (1 << 5);
-			break;
-		case IT83XX_I2C_CH_E:
-			/* Enable I2C E channel */
-			IT83XX_GCTRL_PMER1 |= (1 << 0);
-			break;
-		case IT83XX_I2C_CH_F:
-			/* Enable I2C F channel */
-			IT83XX_GCTRL_PMER1 |= (1 << 1);
-			break;
-		}
-
-		/* Software reset */
-		IT83XX_I2C_DHTR(ch) |= (1 << 7);
-		IT83XX_I2C_DHTR(ch) &= ~(1 << 7);
-
-		/* This field defines the SMCLK3/4/5 clock/data low timeout. */
-		IT83XX_I2C_TOR(ch) = I2C_CLK_LOW_TIMEOUT;
-
-		/* Bit stretching */
-		IT83XX_I2C_TOS(ch) |= IT83XX_I2C_CLK_STR;
-
-		/* Peripheral address(8-bit)*/
-		IT83XX_I2C_IDR(ch) = periph_addr << 1;
-
-		/* I2C interrupt enable and set acknowledge */
-		IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT |
-			IT83XX_I2C_INTEN | IT83XX_I2C_ACK;
-
-		/*
-		 * bit3 : Peripheral ID write flag
-		 * bit2 : Peripheral ID read flag
-		 * bit1 : Peripheral received data flag
-		 * bit0 : Peripheral finish
-		 */
-		IT83XX_I2C_IRQ_ST(ch) = 0xFF;
-
-		/* Clear read and write data buffer of DMA */
-		memset(in_data[idx], 0, I2C_MAX_BUFFER_SIZE);
-		memset(out_data[idx], 0, I2C_MAX_BUFFER_SIZE);
-
-		if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
-			in_data_addr = (uint32_t)in_data[idx] & 0xffffff;
-			out_data_addr = (uint32_t)out_data[idx] & 0xffffff;
-		} else {
-			in_data_addr = (uint32_t)in_data[idx] & 0xfff;
-			out_data_addr = (uint32_t)out_data[idx] & 0xfff;
-		}
-
-		/* DMA write target address register */
-		IT83XX_I2C_RAMHA(ch) = in_data_addr >> 8;
-		IT83XX_I2C_RAMLA(ch) = in_data_addr;
-
-		if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
-			/*
-			 * DMA write target address register
-			 * for high order byte
-			 */
-			IT83XX_I2C_RAMH2A(ch) = in_data_addr >> 16;
-			/*
-			 * DMA read target address register
-			 * for high order byte
-			 */
-			IT83XX_I2C_CMD_ADDH2(ch) = out_data_addr >> 16;
-			IT83XX_I2C_CMD_ADDH(ch) = out_data_addr >> 8;
-			IT83XX_I2C_CMD_ADDL(ch) = out_data_addr;
-		} else {
-			/* DMA read target address register */
-			IT83XX_I2C_RAMHA2(ch) = out_data_addr >> 8;
-			IT83XX_I2C_RAMLA2(ch) = out_data_addr;
-		}
-
-		/* I2C module enable and command queue mode */
-		IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN |
-			IT83XX_I2C_MDL_EN;
-	}
-}
-
-static void i2c_peripheral_init(void)
-{
-	int  i, p;
-
-	/* DLM 52k~56k size select enable */
-	IT83XX_GCTRL_MCCR2 |= (1 << 4);
-
-	/* Enable I2C Peripheral function */
-	for (i = 0; i < i2c_periphs_used; i++) {
-
-		/* I2c peripheral port mapping. */
-		p = i2c_periph_ports[i].port;
-
-		/* To enable peripheral ch[x] */
-		i2c_peripheral_enable(p, i2c_periph_ports[i].addr);
-
-		/* Clear the interrupt status */
-		task_clear_pending_irq(i2c_periph_ctrl[p].irq);
-
-		/* enable i2c interrupt */
-		task_enable_irq(i2c_periph_ctrl[p].irq);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, i2c_peripheral_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c
deleted file mode 100644
index 80abfaad63..0000000000
--- a/chip/it83xx/intc.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "intc.h"
-#include "it83xx_pd.h"
-#include "ite_pd_intc.h"
-#include "kmsc_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "usb_pd.h"
-
-int __ram_code intc_get_ec_int(void)
-{
-	extern volatile int ec_int;
-	return ec_int;
-}
-
-void intc_cpu_int_group_5(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_5 = intc_get_ec_int();
-
-	switch (intc_group_5) {
-#if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO)
-	case IT83XX_IRQ_KBC_OUT:
-		lpc_kbc_obe_interrupt();
-		break;
-
-	case IT83XX_IRQ_KBC_IN:
-		lpc_kbc_ibf_interrupt();
-		break;
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_5, intc_cpu_int_group_5, 2);
-
-void intc_cpu_int_group_4(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_4 = intc_get_ec_int();
-
-	switch (intc_group_4) {
-#ifdef CONFIG_HOSTCMD_X86
-	case IT83XX_IRQ_PMC_IN:
-		pm1_ibf_interrupt();
-		break;
-
-	case IT83XX_IRQ_PMC2_IN:
-		pm2_ibf_interrupt();
-		break;
-
-	case IT83XX_IRQ_PMC3_IN:
-		pm3_ibf_interrupt();
-		break;
-
-	case IT83XX_IRQ_PMC4_IN:
-		pm4_ibf_interrupt();
-		break;
-
-	case IT83XX_IRQ_PMC5_IN:
-		pm5_ibf_interrupt();
-		break;
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_4, intc_cpu_int_group_4, 2);
-
-void intc_cpu_int_group_12(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_12 = intc_get_ec_int();
-
-	switch (intc_group_12) {
-#ifdef CONFIG_PECI
-	case IT83XX_IRQ_PECI:
-		peci_interrupt();
-		break;
-#endif
-#ifdef CONFIG_HOSTCMD_ESPI
-	case IT83XX_IRQ_ESPI:
-		espi_interrupt();
-		break;
-
-	case IT83XX_IRQ_ESPI_VW:
-		espi_vw_interrupt();
-		break;
-#endif
-#ifdef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-	case IT83XX_IRQ_USBPD0:
-		chip_pd_irq(USBPD_PORT_A);
-		break;
-
-	case IT83XX_IRQ_USBPD1:
-		chip_pd_irq(USBPD_PORT_B);
-		break;
-#ifdef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
-	case IT83XX_IRQ_USBPD2:
-		chip_pd_irq(USBPD_PORT_C);
-		break;
-#endif
-#endif
-#ifdef CONFIG_SPI
-	case IT83XX_IRQ_SPI_PERIPHERAL:
-		spi_peripheral_int_handler();
-		break;
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_12, intc_cpu_int_group_12, 2);
-
-void intc_cpu_int_group_7(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_7 = intc_get_ec_int();
-
-	switch (intc_group_7) {
-#ifdef CONFIG_ADC
-	case IT83XX_IRQ_ADC:
-		adc_interrupt();
-		break;
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-	case IT83XX_IRQ_V_COMP:
-		voltage_comparator_interrupt();
-		break;
-#endif
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_7, intc_cpu_int_group_7, 2);
-
-void intc_cpu_int_group_6(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_6 = intc_get_ec_int();
-
-	switch (intc_group_6) {
-#if defined(CONFIG_I2C_CONTROLLER) || defined(CONFIG_I2C_PERIPHERAL)
-	case IT83XX_IRQ_SMB_A:
-#ifdef CONFIG_I2C_PERIPHERAL
-		if (IT83XX_SMB_SFFCTL & IT83XX_SMB_SAFE)
-			i2c_periph_interrupt(IT83XX_I2C_CH_A);
-		else
-#endif
-			i2c_interrupt(IT83XX_I2C_CH_A);
-		break;
-
-	case IT83XX_IRQ_SMB_B:
-		i2c_interrupt(IT83XX_I2C_CH_B);
-		break;
-
-	case IT83XX_IRQ_SMB_C:
-		i2c_interrupt(IT83XX_I2C_CH_C);
-		break;
-
-	case IT83XX_IRQ_SMB_D:
-#ifdef CONFIG_I2C_PERIPHERAL
-		if (!(IT83XX_I2C_CTR(3) & IT83XX_I2C_MODE))
-			i2c_periph_interrupt(IT83XX_I2C_CH_D);
-		else
-#endif
-			i2c_interrupt(IT83XX_I2C_CH_D);
-		break;
-
-	case IT83XX_IRQ_SMB_E:
-#ifdef CONFIG_I2C_PERIPHERAL
-		if (!(IT83XX_I2C_CTR(0) & IT83XX_I2C_MODE))
-			i2c_periph_interrupt(IT83XX_I2C_CH_E);
-		else
-#endif
-			i2c_interrupt(IT83XX_I2C_CH_E);
-		break;
-
-	case IT83XX_IRQ_SMB_F:
-#ifdef CONFIG_I2C_PERIPHERAL
-		if (!(IT83XX_I2C_CTR(1) & IT83XX_I2C_MODE))
-			i2c_periph_interrupt(IT83XX_I2C_CH_F);
-		else
-#endif
-			i2c_interrupt(IT83XX_I2C_CH_F);
-		break;
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_6, intc_cpu_int_group_6, 2);
diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h
deleted file mode 100644
index 62ceb34576..0000000000
--- a/chip/it83xx/intc.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* INTC control module for IT83xx. */
-
-#ifndef __CROS_EC_INTC_H
-#define __CROS_EC_INTC_H
-
-/*
- * The DSB instruction guarantees a modified architecture or hardware state
- * can be seen by any following dependent data operations.
- */
-static inline void data_serialization_barrier(void)
-{
-	if (IS_ENABLED(CHIP_CORE_NDS32))
-		asm volatile ("dsb");
-}
-
-int intc_get_ec_int(void);
-void pm1_ibf_interrupt(void);
-void pm2_ibf_interrupt(void);
-void pm3_ibf_interrupt(void);
-void pm4_ibf_interrupt(void);
-void pm5_ibf_interrupt(void);
-void lpcrst_interrupt(enum gpio_signal signal);
-void peci_interrupt(void);
-void adc_interrupt(void);
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-void voltage_comparator_interrupt(void);
-#endif
-void i2c_interrupt(int port);
-#ifdef CONFIG_I2C_PERIPHERAL
-void i2c_periph_interrupt(int port);
-#endif
-void clock_sleep_mode_wakeup_isr(void);
-int clock_ec_wake_from_sleep(void);
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds);
-void espi_reset_pin_asserted_interrupt(enum gpio_signal signal);
-void espi_fw_reset_module(void);
-void espi_interrupt(void);
-void espi_vw_interrupt(void);
-void espi_enable_pad(int enable);
-void espi_init(void);
-void clock_cpu_standby(void);
-void spi_emmc_cmd0_isr(uint32_t *cmd0_payload);
-void spi_peripheral_int_handler(void);
-#if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO)
-void lpc_kbc_ibf_interrupt(void);
-void lpc_kbc_obe_interrupt(void);
-#endif
-
-#endif /* __CROS_EC_INTC_H */
diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c
deleted file mode 100644
index fb01309721..0000000000
--- a/chip/it83xx/irq.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IT83xx chip-specific part of the IRQ handling.
- */
-
-#include "common.h"
-#include "irq_chip.h"
-#include "registers.h"
-#include "util.h"
-
-#define IRQ_GROUP(n, cpu_ints...) \
-	{(uint32_t)&CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \
-	 (uint32_t)&CONCAT2(IT83XX_INTC_IER, n) - IT83XX_INTC_BASE, \
-	 ##cpu_ints}
-
-static const struct {
-	uint8_t isr_off;
-	uint8_t ier_off;
-	uint8_t cpu_int[8];
-} irq_groups[] = {
-	IRQ_GROUP(0,  {-1,  2,  5,  4,  6,  2,  2,  4}),
-	IRQ_GROUP(1,  { 7,  6,  6,  5,  2,  2,  2,  8}),
-	IRQ_GROUP(2,  { 6,  2,  8,  8,  8,  2, 12, 12}),
-	IRQ_GROUP(3,  { 5,  4,  4,  4, 11, 11,  3,  2}),
-	IRQ_GROUP(4,  {11, 11, 11, 11,  8,  9,  9,  9}),
-	IRQ_GROUP(5,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(6,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(7,  {10, 10,  3, 12,  3,  3,  3,  3}),
-	IRQ_GROUP(8,  { 4,  4,  4,  4,  4,  4, -1, 12}),
-	IRQ_GROUP(9,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(10, { 3,  6, 12, 12,  5,  2,  2,  2}),
-	IRQ_GROUP(11, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(12, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(13, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(14, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(15, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(16, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(17, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(18, { 2,  2,  2,  2, -1,  4,  4,  7}),
-	IRQ_GROUP(19, { 6,  6, 12,  3,  3,  3,  3,  3}),
-	IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, -1}),
-#if defined(IT83XX_INTC_GROUP_21_22_SUPPORT)
-	IRQ_GROUP(21, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(22, { 2,  2, -1, -1, -1, -1, -1, -1}),
-#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	IRQ_GROUP(21, {-1, -1, 12, 12, 12, 12, 12, 12}),
-	IRQ_GROUP(22, { 2,  2,  2,  2,  2,  2,  2,  2}),
-#else
-	IRQ_GROUP(21, {-1, -1, -1, -1, -1, -1, -1, -1}),
-	IRQ_GROUP(22, {-1, -1, -1, -1, -1, -1, -1, -1}),
-#endif
-	IRQ_GROUP(23, { 2,  2, -1, -1, -1, -1, -1,  2}),
-	IRQ_GROUP(24, { 2,  2,  2,  2,  2,  2, -1,  2}),
-	IRQ_GROUP(25, { 2,  2,  2,  2, -1, -1, -1, -1}),
-	IRQ_GROUP(26, { 2,  2,  2,  2,  2,  2,  2, -1}),
-	IRQ_GROUP(27, { 2,  2,  2,  2,  2,  2, -1, -1}),
-	IRQ_GROUP(28, { 2,  2,  2,  2,  2,  2, -1, -1}),
-};
-
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
-/* Number of CPU hardware interrupts (HW0 ~ HW15) */
-int cpu_int_entry_number;
-#endif
-
-int chip_get_ec_int(void)
-{
-	extern volatile int ec_int;
-
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
-	int i;
-
-	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
-		ec_int = IT83XX_INTC_IVCT(cpu_int_entry_number);
-		/*
-		 * WORKAROUND: when the interrupt vector register isn't
-		 * latched in a load operation,
-		 * we read it again to make sure the value we got
-		 * is the correct value.
-		 */
-		if (ec_int == IT83XX_INTC_IVCT(cpu_int_entry_number))
-			break;
-	}
-	/* Determine interrupt number */
-	ec_int -= 16;
-#else /* defined(CHIP_FAMILY_IT8XXX2) RISCV core */
-	/* wait until two equal interrupt values are read */
-	do {
-		ec_int = IT83XX_INTC_AIVCT;
-	} while (ec_int != IT83XX_INTC_AIVCT);
-	ec_int -= 0x10;
-	/* Unsupported EC INT number. */
-	if (chip_get_intc_group(ec_int) >= 16)
-		return -1;
-#endif
-	return ec_int;
-}
-
-int chip_get_intc_group(int irq)
-{
-	return irq_groups[irq / 8].cpu_int[irq % 8];
-}
-
-void chip_enable_irq(int irq)
-{
-	int group = irq / 8;
-	int bit = irq % 8;
-
-	/* SOC's interrupts share CPU machine-mode external interrupt */
-	if (IS_ENABLED(CHIP_CORE_RISCV))
-		IT83XX_INTC_REG(irq_groups[group].ier_off) |= BIT(bit);
-
-	/* SOC's interrupts use CPU HW interrupt 2 ~ 15 */
-	if (IS_ENABLED(CHIP_CORE_NDS32))
-		IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) |= BIT(bit);
-}
-
-void chip_disable_irq(int irq)
-{
-	int group = irq / 8;
-	int bit = irq % 8;
-
-	/* SOC's interrupts share CPU machine-mode external interrupt */
-	if (IS_ENABLED(CHIP_CORE_RISCV)) {
-		volatile uint8_t _ier __unused;
-
-		IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit);
-		/*
-		 * This load operation will guarantee the above modification of
-		 * EC's register can be seen by any following instructions.
-		 */
-		_ier = IT83XX_INTC_REG(irq_groups[group].ier_off);
-	}
-
-	/* SOC's interrupts use CPU HW interrupt 2 ~ 15 */
-	if (IS_ENABLED(CHIP_CORE_NDS32)) {
-		volatile uint8_t _ext_ier __unused;
-
-		IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) &= ~BIT(bit);
-		/*
-		 * This load operation will guarantee the above modification of
-		 * EC's register can be seen by any following instructions.
-		 */
-		_ext_ier = IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group));
-	}
-}
-
-void chip_clear_pending_irq(int irq)
-{
-	int group = irq / 8;
-	int bit = irq % 8;
-
-	/* always write 1 clear, no | */
-	IT83XX_INTC_REG(irq_groups[group].isr_off) = BIT(bit);
-}
-
-int chip_trigger_irq(int irq)
-{
-	int group = irq / 8;
-	int bit = irq % 8;
-
-	return irq_groups[group].cpu_int[bit];
-}
-
-void chip_init_irqs(void)
-{
-	int i;
-
-	/* Clear all IERx and EXT_IERx */
-	for (i = 0; i < ARRAY_SIZE(irq_groups); i++) {
-		IT83XX_INTC_REG(irq_groups[i].ier_off) = 0;
-		if (IS_ENABLED(CHIP_CORE_NDS32))
-			IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(i)) = 0;
-	}
-}
diff --git a/chip/it83xx/it83xx_fpu.S b/chip/it83xx/it83xx_fpu.S
deleted file mode 100644
index 5265eb7253..0000000000
--- a/chip/it83xx/it83xx_fpu.S
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config_chip.h"
-
-/*
- * DLMB register = 0x80189:
- * Disable all interrupts and switching CPU's
- * ALU (Arithmetic Logic Unit) to floating point operation mode.
- * (IEEE standard 754 floating point)
- *
- * DLMB register = 0x80009:
- * Restore interrupts and ALU.
- */
-	.text
-	.align	2
-	.global	__addsf3
-	.type	__addsf3, @function
-__addsf3:
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	/* Floating-point addition single-precision */
-	add45  $r0, $r1
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-	ret5   $lp
-	.size	__addsf3, .-__addsf3
-
-	.text
-	.align	2
-	.global	__subsf3
-	.type	__subsf3, @function
-__subsf3:
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	/* Floating-point subtraction single-precision */
-	sub45  $r0, $r1
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-	ret5   $lp
-	.size	__subsf3, .-__subsf3
-
-	.text
-	.align	2
-	.global	__mulsf3
-	.type	__mulsf3, @function
-__mulsf3:
-#ifdef IT83XX_FPU_MUL_BY_DIV
-#define SIGN	$r2
-#define EXPOA	$r3
-#define MANTA	$r4
-#define VALUA	$r5
-#define EXPOB	$r6
-#define MANTB	$r7
-#define VALUB	$r8
-#define SPROD	$r15
-        /* save r6-r8 */
-	smw.adm	$r6, [$sp], $r8, #0x0
-	xor    SPROD, $r1, $r0  /* sign(A xor B) */
-	move   SIGN, #0x80000000
-	and    SPROD, SPROD, SIGN /* store sign bit */
-	slli   VALUA, $r0, 1    /* A<<1, (exponent and mantissa) */
-	slli   VALUB, $r1, 1    /* B<<1, (exponent and mantissa) */
-	srli   EXPOA, VALUA, 24 /* exponent(A) */
-	srli   EXPOB, VALUB, 24 /* exponent(B) */
-	slli   MANTA, VALUA, 7  /* A<<8, mantissa(A) with exponent's LSB */
-	slli   MANTB, VALUB, 7  /* A<<8, mantissa(B) with exponent's LSB */
-	beqz   VALUA, .LFzeroA  /* exponent(A) and mantissa (A) are zero */
-	beqc   EXPOA, 0xff, .LFinfnanA /* A is inf or NaN */
-	beqz   VALUB, .LFzeroB  /* exponent(B) and mantissa (B) are zero */
-	beqc   EXPOB, 0xff, .LFinfnanB /* B is inf or NaN */
-        /* A*B = A/(1/B) */
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	sethi  $r5, #0x3f800    /* r5 = 1.0f */
-	divsr  $r1,$r1,$r5,$r1  /* r1 = 1.0f / r1 */
-	divsr  $r0,$r0,$r0,$r1  /* r0 = r0 / r1 */
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-.LFret:
-	/* restore r6-r8  */
-	lmw.bim	$r6, [$sp], $r8, #0x0
-	ret5	$lp
-
-.LFzeroA:                       /* A is zero */
-	beqc EXPOB, 0xff, .LFnan/*zero * inf = zero * NaN = NaN */
-.LFzero:
-	move $r0, SPROD         /* return 0.0f or -0.0f */
-	b    .LFret
-.LFinfnanA:                     /* exponent(A) is 0xff */
-	bne  MANTA, SIGN, .LFnan/* A is NaN: NaN * B = NaN */
-	beqz VALUB, .LFnan      /* A is inf and B is zero: inf * zero = NaN */
-	bnec EXPOB, 0xff, .LFinf/* B is finite: inf * B = inf */
-.LFinfnanB:                     /* exponent(B) is 0xff */
-	bne  MANTB, SIGN, .LFnan/* B is NaN: A * NaN = NaN */
-.LFinf:
-	move $r0, #0x7f800000
-	or   $r0, $r0, SPROD    /* return inf or -inf */
-	b   .LFret
-.LFzeroB:                       /* B is zero and A is finit */
-	b   .LFzero	        /* B is zero */
-.LFnan:
-	move $r0, #0xffc00000   /* return NaN */
-	b    .LFret
-#else  /* !IT83XX_FPU_MUL_BY_DIV */
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	/* Floating-point multiplication single-precision */
-	mul33  $r0, $r1
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-	ret5   $lp
-#endif /* IT83XX_FPU_MUL_BY_DIV */
-	.size	__mulsf3, .-__mulsf3
-
-	.text
-	.align	2
-	.global	__divsf3
-	.type	__divsf3, @function
-__divsf3:
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	/* Floating-point division single-precision */
-	divsr  $r0,$r0,$r0,$r1
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-	ret5   $lp
-	.size	__divsf3, .-__divsf3
diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c
deleted file mode 100644
index 6c7a10c463..0000000000
--- a/chip/it83xx/keyboard_raw.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "irq_chip.h"
-
-#define KSOH_PIN_MASK (((1 << (KEYBOARD_COLS_MAX - 8)) - 1) & 0xff)
-
-/*
- * Initialize the raw keyboard interface.
- */
-void keyboard_raw_init(void)
-{
-	uint32_t int_mask;
-
-	/* Ensure top-level interrupt is disabled */
-	keyboard_raw_enable_interrupt(0);
-
-	/*
-	 * bit2, Setting 1 enables the internal pull-up of the KSO[15:0] pins.
-	 * To pull up KSO[17:16], set the GPCR registers of their
-	 * corresponding GPIO ports.
-	 * bit0, Setting 1 enables the open-drain mode of the KSO[17:0] pins.
-	 */
-	IT83XX_KBS_KSOCTRL = 0x05;
-
-	/* bit2, 1 enables the internal pull-up of the KSI[7:0] pins. */
-	IT83XX_KBS_KSICTRL = 0x04;
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/* KSO[2] is high, others are low. */
-	IT83XX_KBS_KSOL = BIT(2);
-	/* Enable KSO2's push-pull */
-	IT83XX_KBS_KSOLGCTRL |= BIT(2);
-	IT83XX_KBS_KSOLGOEN |= BIT(2);
-#else
-	/* KSO[7:0] pins low. */
-	IT83XX_KBS_KSOL = 0x00;
-#endif
-
-	/* critical section with interrupts off */
-	int_mask = read_clear_int_mask();
-	/*
-	 * KSO[COLS_MAX:8] pins low.
-	 * NOTE: KSO[15:8] pins can part be enabled for keyboard function and
-	 *       rest be configured as GPIO output mode. In this case that we
-	 *       disable the ISR in critical section to avoid race condition.
-	 */
-	IT83XX_KBS_KSOH1 &= ~KSOH_PIN_MASK;
-	/* restore interrupts */
-	set_int_mask(int_mask);
-
-	/* KSI[0-7] falling-edge triggered is selected */
-	IT83XX_WUC_WUEMR3 = 0xFF;
-
-	/* W/C */
-	IT83XX_WUC_WUESR3 = 0xFF;
-
-	task_clear_pending_irq(IT83XX_IRQ_WKINTC);
-
-	/* Enable WUC for KSI[0-7] */
-	IT83XX_WUC_WUENR3 = 0xFF;
-}
-
-/*
- * Finish initialization after task scheduling has started.
- */
-void keyboard_raw_task_start(void)
-{
-	IT83XX_WUC_WUESR3 = 0xFF;
-	task_clear_pending_irq(IT83XX_IRQ_WKINTC);
-	task_enable_irq(IT83XX_IRQ_WKINTC);
-}
-
-/*
- * Drive the specified column low.
- */
-test_mockable void keyboard_raw_drive_column(int col)
-{
-	int mask;
-	uint32_t int_mask;
-
-	/* Tri-state all outputs */
-	if (col == KEYBOARD_COLUMN_NONE)
-		mask = 0xffff;
-	/* Assert all outputs */
-	else if (col == KEYBOARD_COLUMN_ALL)
-		mask = 0;
-	/* Assert a single output */
-	else
-		mask = 0xffff ^ BIT(col);
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/* KSO[2] is inverted. */
-	mask ^= BIT(2);
-#endif
-	IT83XX_KBS_KSOL = mask & 0xff;
-
-	/* critical section with interrupts off */
-	int_mask = read_clear_int_mask();
-	/*
-	 * Because IT83XX_KBS_KSOH1 register is shared by keyboard scan
-	 * out and GPIO output mode, so we don't drive all KSOH pins
-	 * here (this depends on how many keyboard matrix output pin
-	 * we are using).
-	 */
-	IT83XX_KBS_KSOH1 = (IT83XX_KBS_KSOH1 & ~KSOH_PIN_MASK) |
-		((mask >> 8) & KSOH_PIN_MASK);
-	/* restore interrupts */
-	set_int_mask(int_mask);
-}
-
-/*
- * Read raw row state.
- * Bits are 1 if signal is present, 0 if not present.
- */
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Bits are active-low, so invert returned levels */
-	return IT83XX_KBS_KSI ^ 0xff;
-}
-
-/*
- * Enable or disable keyboard matrix scan interrupts.
- */
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		IT83XX_WUC_WUESR3 = 0xFF;
-		task_clear_pending_irq(IT83XX_IRQ_WKINTC);
-		task_enable_irq(IT83XX_IRQ_WKINTC);
-	} else {
-		task_disable_irq(IT83XX_IRQ_WKINTC);
-	}
-}
-
-/*
- * Interrupt handler for keyboard matrix scan interrupt.
- */
-void keyboard_raw_interrupt(void)
-{
-	IT83XX_WUC_WUESR3 = 0xFF;
-	task_clear_pending_irq(IT83XX_IRQ_WKINTC);
-
-	/* Wake the scan task */
-	task_wake(TASK_ID_KEYSCAN);
-}
-
-int keyboard_raw_is_input_low(int port, int id)
-{
-	return !(IT83XX_GPIO_DATA_MIRROR(port) & BIT(id));
-}
diff --git a/chip/it83xx/kmsc_chip.h b/chip/it83xx/kmsc_chip.h
deleted file mode 100644
index cf4169a1c4..0000000000
--- a/chip/it83xx/kmsc_chip.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Keyboard matrix scan control module for IT83xx. */
-
-#ifndef __CROS_EC_KMSC_CHIP_H
-#define __CROS_EC_KMSC_CHIP_H
-
-void keyboard_raw_interrupt(void);
-
-#endif /* __CROS_EC_KMSC_CHIP_H */
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
deleted file mode 100644
index 867d9e024f..0000000000
--- a/chip/it83xx/lpc.c
+++ /dev/null
@@ -1,770 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for Chrome EC */
-
-#include "acpi.h"
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "ec2i_chip.h"
-#include "espi.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "intc.h"
-#include "irq_chip.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "port80.h"
-#include "pwm.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-/* LPC PM channels */
-enum lpc_pm_ch {
-	LPC_PM1 = 0,
-	LPC_PM2,
-	LPC_PM3,
-	LPC_PM4,
-	LPC_PM5,
-};
-
-enum pm_ctrl_mask {
-	/* Input Buffer Full Interrupt Enable. */
-	PM_CTRL_IBFIE = 0x01,
-	/* Output Buffer Empty Interrupt Enable. */
-	PM_CTRL_OBEIE = 0x02,
-};
-
-#define LPC_ACPI_CMD      LPC_PM1   /* ACPI commands 62h/66h port */
-#define LPC_HOST_CMD      LPC_PM2   /* Host commands 200h/204h port */
-#define LPC_HOST_PORT_80H LPC_PM3   /* Host 80h port */
-
-static uint8_t acpi_ec_memmap[EC_MEMMAP_SIZE]
-			__attribute__((section(".h2ram.pool.acpiec")));
-static uint8_t host_cmd_memmap[256]
-			__attribute__((section(".h2ram.pool.hostcmd")));
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-/* Params must be 32-bit aligned */
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-static int p80l_index;
-
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)host_cmd_memmap;
-
-static void pm_set_ctrl(enum lpc_pm_ch ch, enum pm_ctrl_mask ctrl, int set)
-{
-	if (set)
-		IT83XX_PMC_PMCTL(ch) |= ctrl;
-	else
-		IT83XX_PMC_PMCTL(ch) &= ~ctrl;
-}
-
-static void pm_set_status(enum lpc_pm_ch ch, uint8_t status, int set)
-{
-	if (set)
-		IT83XX_PMC_PMSTS(ch) |= status;
-	else
-		IT83XX_PMC_PMSTS(ch) &= ~status;
-}
-
-static uint8_t pm_get_status(enum lpc_pm_ch ch)
-{
-	return IT83XX_PMC_PMSTS(ch);
-}
-
-static uint8_t pm_get_data_in(enum lpc_pm_ch ch)
-{
-	return IT83XX_PMC_PMDI(ch);
-}
-
-static void pm_put_data_out(enum lpc_pm_ch ch, uint8_t out)
-{
-	IT83XX_PMC_PMDO(ch) = out;
-}
-
-static void pm_clear_ibf(enum lpc_pm_ch ch)
-{
-	/* bit7, write-1 clear IBF */
-	IT83XX_PMC_PMIE(ch) |= BIT(7);
-}
-
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-static void keyboard_irq_assert(void)
-{
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	udelay(4);
-
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-}
-#endif
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_vw_set_wire(VW_SMI_L, 0);
-	udelay(65);
-	espi_vw_set_wire(VW_SMI_L, 1);
-#else
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#endif
-}
-
-static void lpc_generate_sci(void)
-{
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_vw_set_wire(VW_SCI_L, 0);
-	udelay(65);
-	espi_vw_set_wire(VW_SCI_L, 1);
-#else
-	gpio_set_level(GPIO_PCH_SCI_L, 0);
-	udelay(65);
-	gpio_set_level(GPIO_PCH_SCI_L, 1);
-#endif
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-static void lpc_send_response(struct host_cmd_handler_args *args)
-{
-	uint8_t *out;
-	int size = args->response_size;
-	int csum;
-	int i;
-
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (args->result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Handle negative size */
-	if (size < 0) {
-		args->result = EC_RES_INVALID_RESPONSE;
-		size = 0;
-	}
-
-	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-		EC_HOST_ARGS_FLAG_TO_HOST;
-
-	lpc_host_args->data_size = size;
-
-	csum = args->command + lpc_host_args->flags +
-		lpc_host_args->command_version +
-		lpc_host_args->data_size;
-
-	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
-		csum += *out;
-
-	lpc_host_args->checksum = (uint8_t)csum;
-
-	/* Fail if response doesn't fit in the param buffer */
-	if (size > EC_PROTO2_MAX_PARAM_SIZE)
-		args->result = EC_RES_INVALID_RESPONSE;
-
-	/* Write result to the data byte.  This sets the OBF status bit. */
-	pm_put_data_out(LPC_HOST_CMD, args->result);
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 0);
-}
-
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable PMC1 interrupt while updating status register */
-	task_disable_irq(IT83XX_IRQ_PMC_IN);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_SMI_PENDING))
-			need_smi = 1;
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SMI_PENDING, 1);
-	} else {
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SMI_PENDING, 0);
-	}
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SCI_PENDING, 1);
-	} else {
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SCI_PENDING, 0);
-	}
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	task_enable_irq(IT83XX_IRQ_PMC_IN);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte. */
-	pm_put_data_out(LPC_HOST_CMD, pkt->driver_result);
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 0);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return (uint8_t *)acpi_ec_memmap;
-}
-
-int lpc_keyboard_has_char(void)
-{
-	/* OBE or OBF */
-	return IT83XX_KBC_KBHISR & 0x01;
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	/* IBE or IBF */
-	return IT83XX_KBC_KBHISR & 0x02;
-}
-
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	/* Clear programming data bit 7-4 */
-	IT83XX_KBC_KBHISR &= 0x0F;
-
-	/* keyboard */
-	IT83XX_KBC_KBHISR |= 0x10;
-
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-	task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-	/* The data output to the KBC Data Output Register. */
-	IT83XX_KBC_KBHIKDOR = chr;
-	task_enable_irq(IT83XX_IRQ_KBC_OUT);
-	if (send_irq)
-		keyboard_irq_assert();
-#else
-	/*
-	 * bit0 = 0, The IRQ1 is controlled by the IRQ1B bit in KBIRQR.
-	 * bit1 = 0, The IRQ12 is controlled by the IRQ12B bit in KBIRQR.
-	 */
-	IT83XX_KBC_KBHICR &= 0x3C;
-
-	/*
-	 * Enable the interrupt to keyboard driver in the host processor
-	 * via SERIRQ when the output buffer is full.
-	 */
-	if (send_irq)
-		IT83XX_KBC_KBHICR |= 0x01;
-
-	udelay(16);
-
-	task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-	/* The data output to the KBC Data Output Register. */
-	IT83XX_KBC_KBHIKDOR = chr;
-	task_enable_irq(IT83XX_IRQ_KBC_OUT);
-#endif
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	uint32_t int_mask = read_clear_int_mask();
-
-	/* bit6, write-1 clear OBF */
-	IT83XX_KBC_KBHICR |= BIT(6);
-	IT83XX_KBC_KBHICR &= ~BIT(6);
-	set_int_mask(int_mask);
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char()) {
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-		keyboard_irq_assert();
-#else
-		/* The IRQ1 is controlled by the IRQ1B bit in KBIRQR. */
-		IT83XX_KBC_KBHICR &= ~0x01;
-
-		/*
-		 * When the OBFKIE bit in KBC Host Interface Control Register
-		 * (KBHICR) is 0, the bit directly controls the IRQ1 signal.
-		 */
-		IT83XX_KBC_KBIRQR |= 0x01;
-#endif
-
-		task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-
-		task_enable_irq(IT83XX_IRQ_KBC_OUT);
-	}
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	pm_set_status(LPC_ACPI_CMD, mask, 1);
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	pm_set_status(LPC_ACPI_CMD, mask, 0);
-}
-
-#ifndef CONFIG_HOSTCMD_ESPI
-int lpc_get_pltrst_asserted(void)
-{
-	return !gpio_get_level(GPIO_PCH_PLTRST_L);
-}
-#endif
-
-#ifdef HAS_TASK_KEYPROTO
-/* KBC and PMC control modules */
-void lpc_kbc_ibf_interrupt(void)
-{
-	if (lpc_keyboard_input_pending()) {
-		keyboard_host_write(IT83XX_KBC_KBHIDIR,
-			(IT83XX_KBC_KBHISR & 0x08) ? 1 : 0);
-		/* bit7, write-1 clear IBF */
-		IT83XX_KBC_KBHICR |= BIT(7);
-		IT83XX_KBC_KBHICR &= ~BIT(7);
-	}
-
-	task_clear_pending_irq(IT83XX_IRQ_KBC_IN);
-
-	task_wake(TASK_ID_KEYPROTO);
-}
-
-void lpc_kbc_obe_interrupt(void)
-{
-	task_disable_irq(IT83XX_IRQ_KBC_OUT);
-
-	task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-
-#ifndef CONFIG_KEYBOARD_IRQ_GPIO
-	if (!(IT83XX_KBC_KBHICR & 0x01)) {
-		IT83XX_KBC_KBIRQR &= ~0x01;
-
-		IT83XX_KBC_KBHICR |= 0x01;
-	}
-#endif
-
-	task_wake(TASK_ID_KEYPROTO);
-}
-#endif /* HAS_TASK_KEYPROTO */
-
-void pm1_ibf_interrupt(void)
-{
-	int is_cmd;
-	uint8_t value, result;
-
-	if (pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_FROM_HOST) {
-		/* Set the busy bit */
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_PROCESSING, 1);
-
-		/* data from command port or data port */
-		is_cmd = pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_LAST_CMD;
-
-		/* Get command or data */
-		value = pm_get_data_in(LPC_ACPI_CMD);
-
-		/* Handle whatever this was. */
-		if (acpi_ap_to_ec(is_cmd, value, &result))
-			pm_put_data_out(LPC_ACPI_CMD, result);
-
-		pm_clear_ibf(LPC_ACPI_CMD);
-
-		/* Clear the busy bit */
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_PROCESSING, 0);
-
-		/*
-		 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty
-		 * Output Buffer Full condition on the kernel channel.
-		 */
-		lpc_generate_sci();
-	}
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC_IN);
-}
-
-void pm2_ibf_interrupt(void)
-{
-	uint8_t value __attribute__((unused)) = 0;
-	uint8_t status;
-
-	status = pm_get_status(LPC_HOST_CMD);
-	/* IBE */
-	if (!(status & EC_LPC_STATUS_FROM_HOST)) {
-		task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-		return;
-	}
-
-	/* IBF and data port */
-	if (!(status & EC_LPC_STATUS_LAST_CMD)) {
-		/* R/C IBF*/
-		value = pm_get_data_in(LPC_HOST_CMD);
-		pm_clear_ibf(LPC_HOST_CMD);
-		task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-		return;
-	}
-
-	/* Set the busy bit */
-	pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 1);
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = pm_get_data_in(LPC_HOST_CMD);
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	if (host_cmd_args.command != EC_COMMAND_PROTOCOL_3)
-		host_cmd_args.send_response = lpc_send_response;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* We only support new style command (v3) now */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)host_cmd_memmap;
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)host_cmd_memmap;
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-		host_packet_receive(&lpc_packet);
-
-		pm_clear_ibf(LPC_HOST_CMD);
-		task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-		return;
-	} else {
-		/* Old style command, now unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-
-	pm_clear_ibf(LPC_HOST_CMD);
-	task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-}
-
-void pm3_ibf_interrupt(void)
-{
-	int new_p80_idx, i;
-	enum ec2i_message ec2i_r;
-
-	/* set LDN */
-	if (ec2i_write(HOST_INDEX_LDN, LDN_RTCT) == EC2I_WRITE_SUCCESS) {
-		/* get P80L current index */
-		ec2i_r = ec2i_read(HOST_INDEX_DSLDC6);
-		/* clear IBF */
-		pm_clear_ibf(LPC_HOST_PORT_80H);
-		/* read OK */
-		if ((ec2i_r & 0xff00) == EC2I_READ_SUCCESS) {
-			new_p80_idx = ec2i_r & P80L_BRAM_BANK1_SIZE_MASK;
-			for (i = 0; i < (P80L_P80LE - P80L_P80LB + 1); i++) {
-				if (++p80l_index > P80L_P80LE)
-					p80l_index = P80L_P80LB;
-				port_80_write(IT83XX_BRAM_BANK1(p80l_index));
-				if (p80l_index == new_p80_idx)
-					break;
-			}
-		}
-	} else {
-		pm_clear_ibf(LPC_HOST_PORT_80H);
-	}
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
-}
-
-void pm4_ibf_interrupt(void)
-{
-	pm_clear_ibf(LPC_PM4);
-	task_clear_pending_irq(IT83XX_IRQ_PMC4_IN);
-}
-
-void pm5_ibf_interrupt(void)
-{
-	pm_clear_ibf(LPC_PM5);
-	task_clear_pending_irq(IT83XX_IRQ_PMC5_IN);
-}
-
-static void lpc_init(void)
-{
-	enum ec2i_message ec2i_r;
-
-	/* SPI peripheral interface is disabled */
-	IT83XX_GCTRL_SSCR = 0;
-	/*
-	 * DLM 52k~56k size select enable.
-	 * For mapping LPC I/O cycle 800h ~ 9FFh to DLM 8D800 ~ 8D9FF.
-	 */
-	IT83XX_GCTRL_MCCR2 |= 0x10;
-
-	/* The register pair to access PNPCFG is 004Eh and 004Fh */
-	IT83XX_GCTRL_BADRSEL = 0x01;
-
-	/* Disable KBC IRQ */
-	IT83XX_KBC_KBIRQR = 0x00;
-
-	/*
-	 * bit2, Output Buffer Empty CPU Interrupt Enable.
-	 * bit3, Input Buffer Full CPU Interrupt Enable.
-	 * bit5, IBF/OBF EC clear mode.
-	 *   0b: IBF cleared if EC read data register, EC reset, or host reset.
-	 *       OBF cleared if host read data register, or EC reset.
-	 *   1b: IBF cleared if EC write-1 to bit7 at related registers,
-	 *       EC reset, or host reset.
-	 *       OBF cleared if host read data register, EC write-1 to bit6 at
-	 *       related registers, or EC reset.
-	 */
-	IT83XX_KBC_KBHICR |= 0x2C;
-
-	/* PM1 Input Buffer Full Interrupt Enable for 62h/66 port */
-	pm_set_ctrl(LPC_ACPI_CMD, PM_CTRL_IBFIE, 1);
-
-	/* PM2 Input Buffer Full Interrupt Enable for 200h/204 port */
-	pm_set_ctrl(LPC_HOST_CMD, PM_CTRL_IBFIE, 1);
-
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-
-	/* Host LPC I/O cycle mapping to RAM */
-#ifdef IT83XX_H2RAM_REMAPPING
-	/*
-	 * On it8xxx2 series, host I/O cycles are mapped to the first block
-	 * (0x80080000~0x80080fff) at default, and it is adjustable.
-	 * We should set the correct offset depends on the base address of
-	 * H2RAM section, so EC will be able to receive/handle commands from
-	 * host.
-	 */
-	IT83XX_GCTRL_H2ROFSR =
-		(CONFIG_H2RAM_BASE - CONFIG_RAM_BASE) / CONFIG_H2RAM_SIZE;
-#endif
-	/*
-	 * bit[4], H2RAM through LPC IO cycle.
-	 * bit[1], H2RAM window 1 enabled.
-	 * bit[0], H2RAM window 0 enabled.
-	 */
-	IT83XX_SMFI_HRAMWC |= 0x13;
-
-	/*
-	 * bit[7:6]
-	 * Host RAM Window[x] Read Protect Enable
-	 * 00b: Disabled
-	 * 01b: Lower half of RAM window protected
-	 * 10b: Upper half of RAM window protected
-	 * 11b: All protected
-	 *
-	 * bit[5:4]
-	 * Host RAM Window[x] Write Protect Enable
-	 * 00b: Disabled
-	 * 01b: Lower half of RAM window protected
-	 * 10b: Upper half of RAM window protected
-	 * 11b: All protected
-	 *
-	 * bit[2:0]
-	 * Host RAM Window 1 Size (HRAMW1S)
-	 * 0h: 16 bytes
-	 * 1h: 32 bytes
-	 * 2h: 64 bytes
-	 * 3h: 128 bytes
-	 * 4h: 256 bytes
-	 * 5h: 512 bytes
-	 * 6h: 1024 bytes
-	 * 7h: 2048 bytes
-	 */
-
-	/* H2RAM Win 0 Base Address 800h allow r/w for host_cmd_memmap */
-	IT83XX_SMFI_HRAMW0BA = 0x80;
-	IT83XX_SMFI_HRAMW0AAS = 0x04;
-
-	/* H2RAM Win 1 Base Address 900h allow r for acpi_ec_memmap */
-	IT83XX_SMFI_HRAMW1BA = 0x90;
-	IT83XX_SMFI_HRAMW1AAS = 0x34;
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-
-	/*
-	 * bit[5], Dedicated interrupt
-	 * INT3: PMC1 Output Buffer Empty Int
-	 * INT25: PMC1 Input Buffer Full Int
-	 * INT26: PMC2 Output Buffer Empty Int
-	 * INT27: PMC2 Input Buffer Full Int
-	 */
-	IT83XX_PMC_MBXCTRL |= 0x20;
-
-	/* PM3 Input Buffer Full Interrupt Enable for 80h port */
-	pm_set_ctrl(LPC_HOST_PORT_80H, PM_CTRL_IBFIE, 1);
-
-	p80l_index = P80L_P80LC;
-	if (ec2i_write(HOST_INDEX_LDN, LDN_RTCT) == EC2I_WRITE_SUCCESS) {
-		/* get P80L current index */
-		ec2i_r = ec2i_read(HOST_INDEX_DSLDC6);
-		/* read OK */
-		if ((ec2i_r & 0xff00) == EC2I_READ_SUCCESS)
-			p80l_index = ec2i_r & P80L_BRAM_BANK1_SIZE_MASK;
-	}
-
-	/*
-	 * bit[7], enable P80L function.
-	 * bit[6], accept port 80h cycle.
-	 * bit[1-0], 10b: I2EC is read-only.
-	 */
-	IT83XX_GCTRL_SPCTRL1 |= 0xC2;
-
-#ifndef CONFIG_HOSTCMD_ESPI
-	gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
-#endif
-
-#ifdef HAS_TASK_KEYPROTO
-	task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-	task_disable_irq(IT83XX_IRQ_KBC_OUT);
-
-	task_clear_pending_irq(IT83XX_IRQ_KBC_IN);
-	task_enable_irq(IT83XX_IRQ_KBC_IN);
-#endif
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC_IN);
-	pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_PROCESSING, 0);
-	task_enable_irq(IT83XX_IRQ_PMC_IN);
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-	pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 0);
-	task_enable_irq(IT83XX_IRQ_PMC2_IN);
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
-	task_enable_irq(IT83XX_IRQ_PMC3_IN);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_init();
-#endif
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-#ifndef CONFIG_HOSTCMD_ESPI
-void lpcrst_interrupt(enum gpio_signal signal)
-{
-	if (lpc_get_pltrst_asserted())
-		/* Store port 80 reset event */
-		port_80_write(PORT_80_EVENT_RESET);
-
-	CPRINTS("LPC RESET# %sasserted",
-		lpc_get_pltrst_asserted() ? "" : "de");
-}
-#endif
-
-/* Enable LPC ACPI-EC interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	task_enable_irq(IT83XX_IRQ_PMC_IN);
-}
-
-/* Disable LPC ACPI-EC interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	task_disable_irq(IT83XX_IRQ_PMC_IN);
-}
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
diff --git a/chip/it83xx/peci.c b/chip/it83xx/peci.c
deleted file mode 100644
index 07336eaaf6..0000000000
--- a/chip/it83xx/peci.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PECI interface for Chrome EC */
-
-#include "clock.h"
-#include "hooks.h"
-#include "peci.h"
-#include "registers.h"
-#include "util.h"
-#include "timer.h"
-#include "task.h"
-
-enum peci_status {
-	PECI_STATUS_NO_ERR        = 0x00,
-	PECI_STATUS_HOBY          = 0x01,
-	PECI_STATUS_FINISH        = 0x02,
-	PECI_STATUS_RD_FCS_ERR    = 0x04,
-	PECI_STATUS_WR_FCS_ERR    = 0x08,
-	PECI_STATUS_EXTERR        = 0x20,
-	PECI_STATUS_BUSERR        = 0x40,
-	PECI_STATUS_RCV_ERRCODE   = 0x80,
-	PECI_STATUS_ERR_NEED_RST  = (PECI_STATUS_BUSERR | PECI_STATUS_EXTERR),
-	PECI_STATUS_ANY_ERR       = (PECI_STATUS_RCV_ERRCODE |
-					PECI_STATUS_BUSERR |
-					PECI_STATUS_EXTERR |
-					PECI_STATUS_WR_FCS_ERR |
-					PECI_STATUS_RD_FCS_ERR),
-	PECI_STATUS_ANY_BIT       = 0xFE,
-	PECI_STATUS_TIMEOUT       = 0xFF,
-};
-
-static task_id_t peci_current_task;
-
-static void peci_init_vtt_freq(void)
-{
-	/*
-	 * bit2, enable the PECI interrupt generated by data valid event
-	 * from PECI.
-	 *
-	 * bit[1-0], these bits are used to set PECI VTT level.
-	 * 00b: 1.10v
-	 * 01b: 1.05v
-	 * 10b: 1.00v
-	 */
-	IT83XX_PECI_PADCTLR = 0x06;
-
-	/*
-	 * bit[2-0], these bits are used to set PECI host's optimal
-	 * transfer rate.
-	 * 000b: 2.0 MHz
-	 * 001b: 1.0 MHz
-	 * 100b: 1.6 MHz
-	 */
-	IT83XX_PECI_HOCTL2R = 0x01;
-}
-
-static void peci_reset(void)
-{
-	/* Reset PECI */
-	IT83XX_GCTRL_RSTC4 |= 0x10;
-
-	/* short delay */
-	udelay(15);
-
-	peci_init_vtt_freq();
-}
-
-/**
- * Start a PECI transaction
- *
- * @param  peci transaction data
- *
- * @return zero if successful, non-zero if error
- */
-int peci_transaction(struct peci_data *peci)
-{
-	uint8_t status;
-	int index;
-
-	/* To enable PECI function pin */
-	IT83XX_GPIO_GPCRF6 = 0x00;
-
-	/*
-	 * bit5, Both write and read data FIFO pointers will be cleared.
-	 *
-	 * bit4, This bit enables the PECI host to abort the transaction
-	 *       when FCS error occurs.
-	 *
-	 * bit2, This bit enables the contention mechanism of the PECI bus.
-	 *       When this bit is set, the host will abort the transaction
-	 *       if the PECI bus is contentious.
-	 */
-	IT83XX_PECI_HOCTLR |= 0x34;
-
-	/* This register is the target address field of the PECI protocol. */
-	IT83XX_PECI_HOTRADDR = peci->addr;
-
-	/* This register is the write length field of the PECI protocol. */
-	ASSERT(peci->w_len <= PECI_WRITE_DATA_FIFO_SIZE);
-
-	if (peci->cmd_code == PECI_CMD_PING) {
-		/* write length is 0 */
-		IT83XX_PECI_HOWRLR = 0x00;
-	} else {
-		if ((peci->cmd_code == PECI_CMD_WR_PKG_CFG) ||
-			(peci->cmd_code == PECI_CMD_WR_IAMSR) ||
-			(peci->cmd_code == PECI_CMD_WR_PCI_CFG) ||
-			(peci->cmd_code == PECI_CMD_WR_PCI_CFG_LOCAL)) {
-
-			/* write length include Cmd Code + AW FCS */
-			IT83XX_PECI_HOWRLR = peci->w_len + 2;
-
-			/* bit1, The bit enables the AW_FCS hardwired mechanism
-			 * based on the PECI command. This bit is functional
-			 * only when the AW_FCS supported command of
-			 * PECI 2.0/3.0/3.1 is issued.
-			 * When this bit is set, the hardware will handle the
-			 * calculation of AW_FCS.
-			 */
-			IT83XX_PECI_HOCTLR |= 0x02;
-		} else {
-			/* write length include Cmd Code */
-			IT83XX_PECI_HOWRLR = peci->w_len + 1;
-
-			IT83XX_PECI_HOCTLR &= ~0x02;
-		}
-	}
-
-	/* This register is the read length field of the PECI protocol. */
-	ASSERT(peci->r_len <= PECI_READ_DATA_FIFO_SIZE);
-	IT83XX_PECI_HORDLR = peci->r_len;
-
-	/* This register is the command field of the PECI protocol. */
-	IT83XX_PECI_HOCMDR = peci->cmd_code;
-
-	/* The write data field of the PECI protocol. */
-	for (index = 0x00; index < peci->w_len; index++)
-		IT83XX_PECI_HOWRDR = peci->w_buf[index];
-
-	peci_current_task = task_get_current();
-	task_clear_pending_irq(IT83XX_IRQ_PECI);
-	task_enable_irq(IT83XX_IRQ_PECI);
-
-	/* start */
-	IT83XX_PECI_HOCTLR |= 0x01;
-
-	/* pre-set timeout */
-	index = peci->timeout_us;
-	if (task_wait_event(peci->timeout_us) != TASK_EVENT_TIMER)
-		index = 0;
-
-	task_disable_irq(IT83XX_IRQ_PECI);
-
-	peci_current_task = TASK_ID_INVALID;
-
-	if (index < peci->timeout_us) {
-
-		status = IT83XX_PECI_HOSTAR;
-
-		/* any error */
-		if (IT83XX_PECI_HOSTAR & PECI_STATUS_ANY_ERR) {
-
-			if (IT83XX_PECI_HOSTAR & PECI_STATUS_ERR_NEED_RST)
-				peci_reset();
-
-		} else if (IT83XX_PECI_HOSTAR & PECI_STATUS_FINISH) {
-
-			/* The read data field of the PECI protocol. */
-			for (index = 0x00; index < peci->r_len; index++)
-				peci->r_buf[index] = IT83XX_PECI_HORDDR;
-
-			/* W/C */
-			IT83XX_PECI_HOSTAR = PECI_STATUS_FINISH;
-			status = IT83XX_PECI_HOSTAR;
-		}
-	} else {
-		/* transaction timeout */
-		status = PECI_STATUS_TIMEOUT;
-	}
-
-	/* Don't disable PECI host controller if controller already enable. */
-	IT83XX_PECI_HOCTLR = 0x08;
-
-	/* W/C */
-	IT83XX_PECI_HOSTAR = PECI_STATUS_ANY_BIT;
-
-	/* Disable PECI function pin */
-	IT83XX_GPIO_GPCRF6 = 0x80;
-
-	return status;
-}
-
-void peci_interrupt(void)
-{
-	task_clear_pending_irq(IT83XX_IRQ_PECI);
-	task_disable_irq(IT83XX_IRQ_PECI);
-
-	if (peci_current_task != TASK_ID_INVALID)
-		task_wake(peci_current_task);
-}
-
-static void peci_init(void)
-{
-	clock_enable_peripheral(CGC_OFFSET_PECI, 0, 0);
-	peci_init_vtt_freq();
-
-	/* bit3,this bit enables the PECI host controller. */
-	IT83XX_PECI_HOCTLR |= 0x08;
-
-	/* bit4, PECI enable */
-	IT83XX_GPIO_GRC2 |= 0x10;
-}
-DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/it83xx/pwm.c b/chip/it83xx/pwm.c
deleted file mode 100644
index fda8dd23d6..0000000000
--- a/chip/it83xx/pwm.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for IT83xx. */
-
-#include "clock.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-#include "math_util.h"
-
-#define PWM_CTRX_MIN 100
-#define PWM_EC_FREQ  8000000
-
-const struct pwm_ctrl_t pwm_ctrl_regs[] = {
-	{ &IT83XX_PWM_DCR0, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA0},
-	{ &IT83XX_PWM_DCR1, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA1},
-	{ &IT83XX_PWM_DCR2, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA2},
-	{ &IT83XX_PWM_DCR3, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA3},
-	{ &IT83XX_PWM_DCR4, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA4},
-	{ &IT83XX_PWM_DCR5, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA5},
-	{ &IT83XX_PWM_DCR6, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA6},
-	{ &IT83XX_PWM_DCR7, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA7},
-};
-
-const struct pwm_ctrl_t2 pwm_clock_ctrl_regs[] = {
-	{ &IT83XX_PWM_CTR, &IT83XX_PWM_C0CPRS, &IT83XX_PWM_C0CPRS,
-		&IT83XX_PWM_PCFSR, 0x01},
-	{ &IT83XX_PWM_CTR1, &IT83XX_PWM_C4CPRS, &IT83XX_PWM_C4MCPRS,
-		&IT83XX_PWM_PCFSR, 0x02},
-	{ &IT83XX_PWM_CTR2, &IT83XX_PWM_C6CPRS, &IT83XX_PWM_C6MCPRS,
-		&IT83XX_PWM_PCFSR, 0x04},
-	{ &IT83XX_PWM_CTR3, &IT83XX_PWM_C7CPRS, &IT83XX_PWM_C7MCPRS,
-		&IT83XX_PWM_PCFSR, 0x08},
-};
-
-static int pwm_get_cycle_time(enum pwm_channel ch)
-{
-	int pcs_shift;
-	int pcs_mask;
-	int pcs_reg;
-	int cycle_time_setting;
-
-	/* pwm channel mapping */
-	ch = pwm_channels[ch].channel;
-
-	/* bit shift for "Prescaler Clock Source Select Group" register. */
-	pcs_shift = (ch % 4) * 2;
-
-	/* setting of "Prescaler Clock Source Select Group" register. */
-	pcs_reg = *pwm_ctrl_regs[ch].pwm_clock_source;
-
-	/* only bit0 bit1 information. */
-	pcs_mask = (pcs_reg >> pcs_shift) & 0x03;
-
-	/* get cycle time setting of PWM channel x. */
-	cycle_time_setting = *pwm_clock_ctrl_regs[pcs_mask].pwm_cycle_time;
-
-	return cycle_time_setting;
-}
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	/* pwm channel mapping */
-	int pwm_reg_index = pwm_channels[ch].channel;
-
-	/*
-	 * enabled : pin to PWM function.
-	 * disabled : pin to GPIO input function.
-	 */
-	if (enabled)
-		*pwm_ctrl_regs[pwm_reg_index].pwm_pin = 0x00;
-	else
-		*pwm_ctrl_regs[pwm_reg_index].pwm_pin = 0x80 |
-			((pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) ?
-			4 : 2);
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	/* pwm channel mapping */
-	ch = pwm_channels[ch].channel;
-
-	/* pin is PWM function and PWMs clock counter was enabled */
-	return ((*pwm_ctrl_regs[ch].pwm_pin & ~0x04) == 0x00 &&
-		IT83XX_PWM_ZTIER & 0x02) ? 1 : 0;
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	int pcs_shift;
-	int pcs_mask;
-	int pcs_reg;
-	int cycle_time_setting;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	/* pwm channel mapping */
-	ch = pwm_channels[ch].channel;
-
-	/* bit shift for "Prescaler Clock Source Select Group" register. */
-	pcs_shift = (ch % 4) * 2;
-
-	/* setting of "Prescaler Clock Source Select Group" register.*/
-	pcs_reg = *pwm_ctrl_regs[ch].pwm_clock_source;
-
-	/* only bit0 bit1 information. */
-	pcs_mask = (pcs_reg >> pcs_shift) & 0x03;
-
-	/* get cycle time setting of PWM channel x. */
-	cycle_time_setting = *pwm_clock_ctrl_regs[pcs_mask].pwm_cycle_time;
-
-	/* to update PWM DCRx depend on CTRx setting. */
-	if (percent == 100) {
-		*pwm_ctrl_regs[ch].pwm_duty = cycle_time_setting;
-	} else {
-		*pwm_ctrl_regs[ch].pwm_duty =
-			((cycle_time_setting + 1) * percent) / 100;
-	}
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	int pcs_mask;
-	int pcs_reg;
-	int cycle_time_setting;
-	int percent;
-	int ch_idx;
-
-	ch_idx = ch;
-
-	/* pwm channel mapping */
-	ch = pwm_channels[ch].channel;
-
-	/* setting of "Prescaler Clock Source Select Group" register.*/
-	pcs_reg = *pwm_ctrl_regs[ch].pwm_clock_source;
-
-	/* only bit0 bit1 information. */
-	pcs_mask = (pcs_reg >> ((ch % 4) * 2)) & 0x03;
-
-	/* get cycle time setting of PWM channel x. */
-	cycle_time_setting = *pwm_clock_ctrl_regs[pcs_mask].pwm_cycle_time;
-
-	percent = *pwm_ctrl_regs[ch].pwm_duty * 100 / cycle_time_setting;
-
-	if (pwm_channels[ch_idx].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	/* output signal duty cycle. */
-	return percent;
-}
-
-void pwm_duty_inc(enum pwm_channel ch)
-{
-	int cycle_time, pwm_ch;
-
-	/* pwm channel mapping */
-	pwm_ch = pwm_channels[ch].channel;
-
-	cycle_time = pwm_get_cycle_time(ch);
-
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) {
-		if (*pwm_ctrl_regs[pwm_ch].pwm_duty > 0)
-			*pwm_ctrl_regs[pwm_ch].pwm_duty -= 1;
-	} else {
-		if (*pwm_ctrl_regs[pwm_ch].pwm_duty < cycle_time)
-			*pwm_ctrl_regs[pwm_ch].pwm_duty += 1;
-	}
-}
-
-void pwm_duty_reduce(enum pwm_channel ch)
-{
-	int cycle_time, pwm_ch;
-
-	/* pwm channel mapping */
-	pwm_ch = pwm_channels[ch].channel;
-
-	cycle_time = pwm_get_cycle_time(ch);
-
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) {
-		if (*pwm_ctrl_regs[pwm_ch].pwm_duty < cycle_time)
-			*pwm_ctrl_regs[pwm_ch].pwm_duty += 1;
-	} else {
-		if (*pwm_ctrl_regs[pwm_ch].pwm_duty > 0)
-			*pwm_ctrl_regs[pwm_ch].pwm_duty -= 1;
-	}
-}
-
-static int pwm_ch_freq(enum pwm_channel ch)
-{
-	int actual_freq = -1, targe_freq, deviation;
-	int pcfsr, ctr, pcfsr_sel, pcs_shift, pcs_mask;
-	int pwm_clk_src = (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) ?
-							32768 : PWM_EC_FREQ;
-
-	targe_freq = pwm_channels[ch].freq_hz;
-	deviation = (targe_freq / 100) + 1;
-
-	for (ctr = 0xFF; ctr >= PWM_CTRX_MIN; ctr--) {
-		pcfsr = (pwm_clk_src / (ctr + 1) / targe_freq) - 1;
-		if (pcfsr >= 0) {
-			actual_freq = pwm_clk_src / (ctr + 1) / (pcfsr + 1);
-			if (ABS(actual_freq - targe_freq) < deviation)
-				break;
-		}
-	}
-
-	if (ctr < PWM_CTRX_MIN) {
-		actual_freq = -1;
-	} else {
-		pcfsr_sel = pwm_channels[ch].pcfsr_sel;
-		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cycle_time = ctr;
-
-		if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-			/*
-			 * Select 32.768KHz as PWM clock source.
-]			 *
-			 * NOTE:
-			 * For pwm_channels[], the maximum supported pwm output
-			 * signal frequency is 324 Hz (32768/(PWM_CTRX_MIN+1)).
-			 */
-			*pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_reg &=
-				~pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_ctrl;
-		else
-			/* ec clock 8MHz */
-			*pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_reg |=
-				pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_ctrl;
-
-		/* pwm channel mapping */
-		ch = pwm_channels[ch].channel;
-
-		/*
-		 * bit shift for "Prescaler Clock Source Select Group"
-		 * register.
-		 */
-		pcs_shift = (ch % 4) * 2;
-		pcs_mask = pcfsr_sel << pcs_shift;
-
-		*pwm_ctrl_regs[ch].pwm_clock_source &= ~(0x3 << pcs_shift);
-		*pwm_ctrl_regs[ch].pwm_clock_source |= pcs_mask;
-
-		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_lsb = pcfsr & 0xFF;
-		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_msb =
-			(pcfsr >> 8) & 0xFF;
-	}
-
-	return actual_freq;
-}
-
-static void pwm_init(void)
-{
-	int ch;
-
-	for (ch = 0; ch < PWM_CH_COUNT; ch++)
-		pwm_ch_freq(ch);
-
-	/*
-	 * The cycle timer1 of chip 8320 later series was enhanced from
-	 * 8bits to 10bits resolution, and others are still 8bit resolution.
-	 * Because the cycle timer1 high byte default value is not zero,
-	 * we clear cycle timer1 high byte at init and use it as 8-bit
-	 * resolution like others.
-	 */
-	IT83XX_PWM_CTR1M = 0;
-	/* enable PWMs clock counter. */
-	IT83XX_PWM_ZTIER |= 0x02;
-}
-
-/* The chip PWM module initialization. */
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/it83xx/pwm_chip.h b/chip/it83xx/pwm_chip.h
deleted file mode 100644
index 4e8aba1c62..0000000000
--- a/chip/it83xx/pwm_chip.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for IT83xx. */
-
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-enum pwm_pcfsr_sel {
-	PWM_PRESCALER_C4 = 1,
-	PWM_PRESCALER_C6 = 2,
-	PWM_PRESCALER_C7 = 3,
-};
-
-enum pwm_hw_channel {
-	PWM_HW_CH_DCR0 = 0,
-	PWM_HW_CH_DCR1,
-	PWM_HW_CH_DCR2,
-	PWM_HW_CH_DCR3,
-	PWM_HW_CH_DCR4,
-	PWM_HW_CH_DCR5,
-	PWM_HW_CH_DCR6,
-	PWM_HW_CH_DCR7,
-
-	PWM_HW_CH_TOTAL,
-};
-
-enum tach_ch_sel {
-	/* Pin GPIOD.6 */
-	TACH_CH_TACH0A = 0,
-	/* Pin GPIOD.7 */
-	TACH_CH_TACH1A,
-	/* Pin GPIOJ.2 */
-	TACH_CH_TACH0B,
-	/* Pin GPIOJ.3 */
-	TACH_CH_TACH1B,
-	/* Number of TACH channels */
-	TACH_CH_COUNT,
-
-	TACH_CH_NULL = 0xFF,
-};
-
-/* Data structure to define PWM channel control registers. */
-struct pwm_ctrl_t {
-	/* PWM channel output duty register. */
-	volatile uint8_t *pwm_duty;
-	/* PWM channel clock source selection register. */
-	volatile uint8_t *pwm_clock_source;
-	/* PWM channel pin control register. */
-	volatile uint8_t *pwm_pin;
-};
-
-/* Data structure to define PWM channel control registers part 2. */
-struct pwm_ctrl_t2 {
-	/* PWM cycle time register. */
-	volatile uint8_t *pwm_cycle_time;
-	/* PWM channel clock prescaler register (LSB). */
-	volatile uint8_t *pwm_cpr_lsb;
-	/* PWM channel clock prescaler register (MSB). */
-	volatile uint8_t *pwm_cpr_msb;
-	/* PWM prescaler clock frequency select register. */
-	volatile uint8_t *pwm_pcfsr_reg;
-	/* PWM prescaler clock frequency select register setting. */
-	uint8_t pwm_pcfsr_ctrl;
-};
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM channel ID */
-	int channel;
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-	int freq_hz;
-	enum pwm_pcfsr_sel pcfsr_sel;
-};
-
-/* Tachometer channel of each physical fan */
-struct fan_tach_t {
-	enum tach_ch_sel ch_tach;
-	/* the numbers of square pulses per revolution of fan. */
-	int fan_p;
-	/* allow actual rpm ~= targe rpm +- rpm_re */
-	int rpm_re;
-	/* startup duty of fan */
-	int s_duty;
-};
-
-extern const struct pwm_t pwm_channels[];
-/* The list of tachometer channel of fans is instantiated in board.c. */
-extern const struct fan_tach_t fan_tach[];
-
-void pwm_duty_inc(enum pwm_channel ch);
-void pwm_duty_reduce(enum pwm_channel ch);
-
-#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
deleted file mode 100644
index 34a2ddd6ae..0000000000
--- a/chip/it83xx/registers.h
+++ /dev/null
@@ -1,1678 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for IT83xx processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#define __ram_code __attribute__((section(__RAM_CODE_SECTION_NAME)))
-
-/* IRQ numbers */
-/* Group 0 */
-#define IT83XX_IRQ_WKO20           1
-#define IT83XX_IRQ_KBC_OUT         2
-#define IT83XX_IRQ_PMC_OUT         3
-#define IT83XX_IRQ_SMB_D           4
-#define IT83XX_IRQ_WKINTAD         5
-#define IT83XX_IRQ_WKO23           6
-#define IT83XX_IRQ_PWM             7
-/* Group 1 */
-#define IT83XX_IRQ_ADC             8
-#define IT83XX_IRQ_SMB_A           9
-#define IT83XX_IRQ_SMB_B          10
-#define IT83XX_IRQ_KB_MATRIX      11
-#define IT83XX_IRQ_WKO26          12
-#define IT83XX_IRQ_WKINTC         13
-#define IT83XX_IRQ_WKO25          14
-#define IT83XX_IRQ_CIR            15
-/* Group 2 */
-#define IT83XX_IRQ_SMB_C          16
-#define IT83XX_IRQ_WKO24          17
-#define IT83XX_IRQ_PS2_2          18
-#define IT83XX_IRQ_PS2_1          19
-#define IT83XX_IRQ_PS2_0          20
-#define IT83XX_IRQ_WKO22          21
-#define IT83XX_IRQ_SMFI           22
-#define IT83XX_IRQ_USB            23
-/* Group 3 */
-#define IT83XX_IRQ_KBC_IN         24
-#define IT83XX_IRQ_PMC_IN         25
-#define IT83XX_IRQ_PMC2_OUT       26
-#define IT83XX_IRQ_PMC2_IN        27
-#define IT83XX_IRQ_GINT           28
-#define IT83XX_IRQ_EGPC           29
-#define IT83XX_IRQ_EXT_TIMER1     30
-#define IT83XX_IRQ_WKO21          31
-/* Group 4 */
-#define IT83XX_IRQ_GPINT0         32
-#define IT83XX_IRQ_GPINT1         33
-#define IT83XX_IRQ_GPINT2         34
-#define IT83XX_IRQ_GPINT3         35
-#define IT83XX_IRQ_CIR_GPINT      36
-#define IT83XX_IRQ_SSPI           37
-#define IT83XX_IRQ_UART1          38
-#define IT83XX_IRQ_UART2          39
-/* Group 5 */
-#define IT83XX_IRQ_WKO50          40
-#define IT83XX_IRQ_WKO51          41
-#define IT83XX_IRQ_WKO52          42
-#define IT83XX_IRQ_WKO53          43
-#define IT83XX_IRQ_WKO54          44
-#define IT83XX_IRQ_WKO55          45
-#define IT83XX_IRQ_WKO56          46
-#define IT83XX_IRQ_WKO57          47
-/* Group 6 */
-#define IT83XX_IRQ_WKO60          48
-#define IT83XX_IRQ_WKO61          49
-#define IT83XX_IRQ_WKO62          50
-#define IT83XX_IRQ_WKO63          51
-#define IT83XX_IRQ_WKO64          52
-#define IT83XX_IRQ_WKO65          53
-#define IT83XX_IRQ_WKO66          54
-#define IT83XX_IRQ_WKO67          55
-/* Group 7 */
-#define IT83XX_IRQ_RTCT_ALARM1    56
-#define IT83XX_IRQ_RTCT_ALARM2    57
-#define IT83XX_IRQ_EXT_TIMER2     58
-#define IT83XX_IRQ_DEFERRED_SPI   59
-#define IT83XX_IRQ_TMR_A0         60
-#define IT83XX_IRQ_TMR_A1         61
-#define IT83XX_IRQ_TMR_B0         62
-#define IT83XX_IRQ_TMR_B1         63
-/* Group 8 */
-#define IT83XX_IRQ_PMC2EX_OUT     64
-#define IT83XX_IRQ_PMC2EX_IN      65
-#define IT83XX_IRQ_PMC3_OUT       66
-#define IT83XX_IRQ_PMC3_IN        67
-#define IT83XX_IRQ_PMC4_OUT       68
-#define IT83XX_IRQ_PMC4_IN        69
-#define IT83XX_IRQ_I2BRAM         71
-/* Group 9 */
-#define IT83XX_IRQ_WKO70          72
-#define IT83XX_IRQ_WKO71          73
-#define IT83XX_IRQ_WKO72          74
-#define IT83XX_IRQ_WKO73          75
-#define IT83XX_IRQ_WKO74          76
-#define IT83XX_IRQ_WKO75          77
-#define IT83XX_IRQ_WKO76          78
-#define IT83XX_IRQ_WKO77          79
-/* Group 10 */
-#define IT83XX_IRQ_EXT_TMR8       80
-#define IT83XX_IRQ_SMB_CLOCK_HELD 81
-#define IT83XX_IRQ_CEC            82
-#define IT83XX_IRQ_H2RAM_LPC      83
-#define IT83XX_IRQ_HW_KB_SCAN     84
-#define IT83XX_IRQ_WKO88          85
-#define IT83XX_IRQ_WKO89          86
-#define IT83XX_IRQ_WKO90          87
-/* Group 11 */
-#define IT83XX_IRQ_WKO80          88
-#define IT83XX_IRQ_WKO81          89
-#define IT83XX_IRQ_WKO82          90
-#define IT83XX_IRQ_WKO83          91
-#define IT83XX_IRQ_WKO84          92
-#define IT83XX_IRQ_WKO85          93
-#define IT83XX_IRQ_WKO86          94
-#define IT83XX_IRQ_WKO87          95
-/* Group 12 */
-#define IT83XX_IRQ_WKO91          96
-#define IT83XX_IRQ_WKO92          97
-#define IT83XX_IRQ_WKO93          98
-#define IT83XX_IRQ_WKO94          99
-#define IT83XX_IRQ_WKO95          100
-#define IT83XX_IRQ_WKO96          101
-#define IT83XX_IRQ_WKO97          102
-#define IT83XX_IRQ_WKO98          103
-/* Group 13 */
-#define IT83XX_IRQ_WKO99          104
-#define IT83XX_IRQ_WKO100         105
-#define IT83XX_IRQ_WKO101         106
-#define IT83XX_IRQ_WKO102         107
-#define IT83XX_IRQ_WKO103         108
-#define IT83XX_IRQ_WKO104         109
-#define IT83XX_IRQ_WKO105         110
-#define IT83XX_IRQ_WKO106         111
-/* Group 14 */
-#define IT83XX_IRQ_WKO107         112
-#define IT83XX_IRQ_WKO108         113
-#define IT83XX_IRQ_WKO109         114
-#define IT83XX_IRQ_WKO110         115
-#define IT83XX_IRQ_WKO111         116
-#define IT83XX_IRQ_WKO112         117
-#define IT83XX_IRQ_WKO113         118
-#define IT83XX_IRQ_WKO114         119
-/* Group 15 */
-#define IT83XX_IRQ_WKO115         120
-#define IT83XX_IRQ_WKO116         121
-#define IT83XX_IRQ_WKO117         122
-#define IT83XX_IRQ_WKO118         123
-#define IT83XX_IRQ_WKO119         124
-#define IT83XX_IRQ_WKO120         125
-#define IT83XX_IRQ_WKO121         126
-#define IT83XX_IRQ_WKO122         127
-/* Group 16 */
-#define IT83XX_IRQ_WKO128         128
-#define IT83XX_IRQ_WKO129         129
-#define IT83XX_IRQ_WKO130         130
-#define IT83XX_IRQ_WKO131         131
-#define IT83XX_IRQ_WKO132         132
-#define IT83XX_IRQ_WKO133         133
-#define IT83XX_IRQ_WKO134         134
-#define IT83XX_IRQ_WKO135         135
-/* Group 17 */
-#define IT83XX_IRQ_WKO136         136
-#define IT83XX_IRQ_WKO137         137
-#define IT83XX_IRQ_WKO138         138
-#define IT83XX_IRQ_WKO139         139
-#define IT83XX_IRQ_WKO140         140
-#define IT83XX_IRQ_WKO141         141
-#define IT83XX_IRQ_WKO142         142
-#define IT83XX_IRQ_WKO143         143
-/* Group 18 */
-#define IT83XX_IRQ_WKO123         144
-#define IT83XX_IRQ_WKO124         145
-#define IT83XX_IRQ_WKO125         146
-#define IT83XX_IRQ_WKO126         147
-#define IT83XX_IRQ_PMC5_OUT       149
-#define IT83XX_IRQ_PMC5_IN        150
-#define IT83XX_IRQ_V_COMP         151
-/* Group 19 */
-#define IT83XX_IRQ_SMB_E          152
-#define IT83XX_IRQ_SMB_F          153
-#define IT83XX_IRQ_OSC_DMA        154
-#define IT83XX_IRQ_EXT_TIMER3     155
-#define IT83XX_IRQ_EXT_TIMER4     156
-#define IT83XX_IRQ_EXT_TIMER5     157
-#define IT83XX_IRQ_EXT_TIMER6     158
-#define IT83XX_IRQ_EXT_TIMER7     159
-/* Group 20 */
-#define IT83XX_IRQ_PECI           160
-#define IT83XX_IRQ_SOFTWARE       161
-#define IT83XX_IRQ_ESPI           162
-#define IT83XX_IRQ_ESPI_VW        163
-#define IT83XX_IRQ_PCH_P80        164
-#define IT83XX_IRQ_USBPD0         165
-#define IT83XX_IRQ_USBPD1         166
-/* Group 21 */
-#if defined(CHIP_FAMILY_IT8320)
-#define IT83XX_IRQ_WKO40          168
-#define IT83XX_IRQ_WKO45          169
-#define IT83XX_IRQ_WKO46          170
-#define IT83XX_IRQ_WKO144         171
-#define IT83XX_IRQ_WKO145         172
-#define IT83XX_IRQ_WKO146         173
-#define IT83XX_IRQ_WKO147         174
-#define IT83XX_IRQ_WKO148         175
-/* Group 22 */
-#define IT83XX_IRQ_WKO149         176
-#define IT83XX_IRQ_WKO150         177
-
-#define IT83XX_IRQ_COUNT          178
-#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-/* Group 21 */
-#define IT83XX_IRQ_AUDIO_IF       170
-#define IT83XX_IRQ_SPI_PERIPHERAL 171
-#define IT83XX_IRQ_DSP_ENGINE     172
-#define IT83XX_IRQ_NN_ENGINE      173
-#define IT83XX_IRQ_USBPD2         174
-#define IT83XX_IRQ_CRYPTO         175
-/* Group 22 */
-#define IT83XX_IRQ_WKO40          176
-#define IT83XX_IRQ_WKO45          177
-#define IT83XX_IRQ_WKO46          178
-#define IT83XX_IRQ_WKO144         179
-#define IT83XX_IRQ_WKO145         180
-#define IT83XX_IRQ_WKO146         181
-#define IT83XX_IRQ_WKO147         182
-#define IT83XX_IRQ_WKO148         183
-/* Group 23 */
-#define IT83XX_IRQ_WKO149         184
-#define IT83XX_IRQ_WKO150         185
-#define IT83XX_IRQ_SSPI1          191
-/* Group 24 */
-#define IT83XX_IRQ_XLPIN0         192
-#define IT83XX_IRQ_XLPIN1         193
-#define IT83XX_IRQ_XLPIN2         194
-#define IT83XX_IRQ_XLPIN3         195
-#define IT83XX_IRQ_XLPIN4         196
-#define IT83XX_IRQ_XLPIN5         197
-#define IT83XX_IRQ_WEEK_ALARM     199
-/* Group 25 */
-#define IT83XX_IRQ_GPO0           200
-#define IT83XX_IRQ_GPO1           201
-#define IT83XX_IRQ_GPO2           202
-#define IT83XX_IRQ_GPO3           203
-/* Group 26 */
-#define IT83XX_IRQ_GPP0           208
-#define IT83XX_IRQ_GPP1           209
-#define IT83XX_IRQ_GPP2           210
-#define IT83XX_IRQ_GPP3           211
-#define IT83XX_IRQ_GPP4           212
-#define IT83XX_IRQ_GPP5           213
-#define IT83XX_IRQ_GPP6           214
-/* Group 27 */
-#define IT83XX_IRQ_GPQ0           216
-#define IT83XX_IRQ_GPQ1           217
-#define IT83XX_IRQ_GPQ2           218
-#define IT83XX_IRQ_GPQ3           219
-#define IT83XX_IRQ_GPQ4           220
-#define IT83XX_IRQ_GPQ5           221
-/* Group 28 */
-#define IT83XX_IRQ_GPR0           224
-#define IT83XX_IRQ_GPR1           225
-#define IT83XX_IRQ_GPR2           226
-#define IT83XX_IRQ_GPR3           227
-#define IT83XX_IRQ_GPR4           228
-#define IT83XX_IRQ_GPR5           229
-
-#define IT83XX_IRQ_COUNT          230
-#endif /* !defined(CHIP_FAMILY_IT8320) */
-
-/* IRQ dispatching to CPU INT vectors */
-#define IT83XX_CPU_INT_IRQ_1       2
-#define IT83XX_CPU_INT_IRQ_2       5
-#define IT83XX_CPU_INT_IRQ_3       4
-#define IT83XX_CPU_INT_IRQ_4       6
-#define IT83XX_CPU_INT_IRQ_5       2
-#define IT83XX_CPU_INT_IRQ_6       2
-#define IT83XX_CPU_INT_IRQ_7       4
-#define IT83XX_CPU_INT_IRQ_8       7
-#define IT83XX_CPU_INT_IRQ_9       6
-#define IT83XX_CPU_INT_IRQ_10      6
-#define IT83XX_CPU_INT_IRQ_11      5
-#define IT83XX_CPU_INT_IRQ_12      2
-#define IT83XX_CPU_INT_IRQ_13      2
-#define IT83XX_CPU_INT_IRQ_14      2
-#define IT83XX_CPU_INT_IRQ_15      8
-#define IT83XX_CPU_INT_IRQ_16      6
-#define IT83XX_CPU_INT_IRQ_17      2
-#define IT83XX_CPU_INT_IRQ_18      8
-#define IT83XX_CPU_INT_IRQ_19      8
-#define IT83XX_CPU_INT_IRQ_20      8
-#define IT83XX_CPU_INT_IRQ_21      2
-#define IT83XX_CPU_INT_IRQ_22     12
-#define IT83XX_CPU_INT_IRQ_23     12
-#define IT83XX_CPU_INT_IRQ_24      5
-#define IT83XX_CPU_INT_IRQ_25      4
-#define IT83XX_CPU_INT_IRQ_26      4
-#define IT83XX_CPU_INT_IRQ_27      4
-#define IT83XX_CPU_INT_IRQ_28     11
-#define IT83XX_CPU_INT_IRQ_29     11
-#define IT83XX_CPU_INT_IRQ_30      3
-#define IT83XX_CPU_INT_IRQ_31      2
-#define IT83XX_CPU_INT_IRQ_32     11
-#define IT83XX_CPU_INT_IRQ_33     11
-#define IT83XX_CPU_INT_IRQ_34     11
-#define IT83XX_CPU_INT_IRQ_35     11
-#define IT83XX_CPU_INT_IRQ_36      8
-#define IT83XX_CPU_INT_IRQ_37      9
-#define IT83XX_CPU_INT_IRQ_38      9
-#define IT83XX_CPU_INT_IRQ_39      9
-#define IT83XX_CPU_INT_IRQ_40      2
-#define IT83XX_CPU_INT_IRQ_41      2
-#define IT83XX_CPU_INT_IRQ_42      2
-#define IT83XX_CPU_INT_IRQ_43      2
-#define IT83XX_CPU_INT_IRQ_44      2
-#define IT83XX_CPU_INT_IRQ_45      2
-#define IT83XX_CPU_INT_IRQ_46      2
-#define IT83XX_CPU_INT_IRQ_47      2
-#define IT83XX_CPU_INT_IRQ_48      2
-#define IT83XX_CPU_INT_IRQ_49      2
-#define IT83XX_CPU_INT_IRQ_50      2
-#define IT83XX_CPU_INT_IRQ_51      2
-#define IT83XX_CPU_INT_IRQ_52      2
-#define IT83XX_CPU_INT_IRQ_53      2
-#define IT83XX_CPU_INT_IRQ_54      2
-#define IT83XX_CPU_INT_IRQ_55      2
-#define IT83XX_CPU_INT_IRQ_56     10
-#define IT83XX_CPU_INT_IRQ_57     10
-#define IT83XX_CPU_INT_IRQ_58      3
-#define IT83XX_CPU_INT_IRQ_59     12
-#define IT83XX_CPU_INT_IRQ_60      3
-#define IT83XX_CPU_INT_IRQ_61      3
-#define IT83XX_CPU_INT_IRQ_62      3
-#define IT83XX_CPU_INT_IRQ_63      3
-#define IT83XX_CPU_INT_IRQ_64      4
-#define IT83XX_CPU_INT_IRQ_65      4
-#define IT83XX_CPU_INT_IRQ_66      4
-#define IT83XX_CPU_INT_IRQ_67      4
-#define IT83XX_CPU_INT_IRQ_68      4
-#define IT83XX_CPU_INT_IRQ_69      4
-#define IT83XX_CPU_INT_IRQ_71     12
-#define IT83XX_CPU_INT_IRQ_72      2
-#define IT83XX_CPU_INT_IRQ_73      2
-#define IT83XX_CPU_INT_IRQ_74      2
-#define IT83XX_CPU_INT_IRQ_75      2
-#define IT83XX_CPU_INT_IRQ_76      2
-#define IT83XX_CPU_INT_IRQ_77      2
-#define IT83XX_CPU_INT_IRQ_78      2
-#define IT83XX_CPU_INT_IRQ_79      2
-#define IT83XX_CPU_INT_IRQ_80      3
-#define IT83XX_CPU_INT_IRQ_81      6
-#define IT83XX_CPU_INT_IRQ_82     12
-#define IT83XX_CPU_INT_IRQ_83     12
-#define IT83XX_CPU_INT_IRQ_84      5
-#define IT83XX_CPU_INT_IRQ_85      2
-#define IT83XX_CPU_INT_IRQ_86      2
-#define IT83XX_CPU_INT_IRQ_87      2
-#define IT83XX_CPU_INT_IRQ_88      2
-#define IT83XX_CPU_INT_IRQ_89      2
-#define IT83XX_CPU_INT_IRQ_90      2
-#define IT83XX_CPU_INT_IRQ_91      2
-#define IT83XX_CPU_INT_IRQ_92      2
-#define IT83XX_CPU_INT_IRQ_93      2
-#define IT83XX_CPU_INT_IRQ_94      2
-#define IT83XX_CPU_INT_IRQ_95      2
-#define IT83XX_CPU_INT_IRQ_96      2
-#define IT83XX_CPU_INT_IRQ_97      2
-#define IT83XX_CPU_INT_IRQ_98      2
-#define IT83XX_CPU_INT_IRQ_99      2
-#define IT83XX_CPU_INT_IRQ_100     2
-#define IT83XX_CPU_INT_IRQ_101     2
-#define IT83XX_CPU_INT_IRQ_102     2
-#define IT83XX_CPU_INT_IRQ_103     2
-#define IT83XX_CPU_INT_IRQ_104     2
-#define IT83XX_CPU_INT_IRQ_105     2
-#define IT83XX_CPU_INT_IRQ_106     2
-#define IT83XX_CPU_INT_IRQ_107     2
-#define IT83XX_CPU_INT_IRQ_108     2
-#define IT83XX_CPU_INT_IRQ_109     2
-#define IT83XX_CPU_INT_IRQ_110     2
-#define IT83XX_CPU_INT_IRQ_111     2
-#define IT83XX_CPU_INT_IRQ_112     2
-#define IT83XX_CPU_INT_IRQ_113     2
-#define IT83XX_CPU_INT_IRQ_114     2
-#define IT83XX_CPU_INT_IRQ_115     2
-#define IT83XX_CPU_INT_IRQ_116     2
-#define IT83XX_CPU_INT_IRQ_117     2
-#define IT83XX_CPU_INT_IRQ_118     2
-#define IT83XX_CPU_INT_IRQ_119     2
-#define IT83XX_CPU_INT_IRQ_120     2
-#define IT83XX_CPU_INT_IRQ_121     2
-#define IT83XX_CPU_INT_IRQ_122     2
-#define IT83XX_CPU_INT_IRQ_123     2
-#define IT83XX_CPU_INT_IRQ_124     2
-#define IT83XX_CPU_INT_IRQ_125     2
-#define IT83XX_CPU_INT_IRQ_126     2
-#define IT83XX_CPU_INT_IRQ_127     2
-#define IT83XX_CPU_INT_IRQ_128     2
-#define IT83XX_CPU_INT_IRQ_129     2
-#define IT83XX_CPU_INT_IRQ_130     2
-#define IT83XX_CPU_INT_IRQ_131     2
-#define IT83XX_CPU_INT_IRQ_132     2
-#define IT83XX_CPU_INT_IRQ_133     2
-#define IT83XX_CPU_INT_IRQ_134     2
-#define IT83XX_CPU_INT_IRQ_135     2
-#define IT83XX_CPU_INT_IRQ_136     2
-#define IT83XX_CPU_INT_IRQ_137     2
-#define IT83XX_CPU_INT_IRQ_138     2
-#define IT83XX_CPU_INT_IRQ_139     2
-#define IT83XX_CPU_INT_IRQ_140     2
-#define IT83XX_CPU_INT_IRQ_141     2
-#define IT83XX_CPU_INT_IRQ_142     2
-#define IT83XX_CPU_INT_IRQ_143     2
-#define IT83XX_CPU_INT_IRQ_144     2
-#define IT83XX_CPU_INT_IRQ_145     2
-#define IT83XX_CPU_INT_IRQ_146     2
-#define IT83XX_CPU_INT_IRQ_147     2
-#define IT83XX_CPU_INT_IRQ_149     4
-#define IT83XX_CPU_INT_IRQ_150     4
-#define IT83XX_CPU_INT_IRQ_151     7
-#define IT83XX_CPU_INT_IRQ_152     6
-#define IT83XX_CPU_INT_IRQ_153     6
-#define IT83XX_CPU_INT_IRQ_154    12
-#define IT83XX_CPU_INT_IRQ_155     3
-#define IT83XX_CPU_INT_IRQ_156     3
-#define IT83XX_CPU_INT_IRQ_157     3
-#define IT83XX_CPU_INT_IRQ_158     3
-#define IT83XX_CPU_INT_IRQ_159     3
-#define IT83XX_CPU_INT_IRQ_160    12
-#define IT83XX_CPU_INT_IRQ_161    12
-#define IT83XX_CPU_INT_IRQ_162    12
-#define IT83XX_CPU_INT_IRQ_163    12
-#define IT83XX_CPU_INT_IRQ_164    12
-#define IT83XX_CPU_INT_IRQ_165    12
-#define IT83XX_CPU_INT_IRQ_166    12
-#define IT83XX_CPU_INT_IRQ_167    12
-#define IT83XX_CPU_INT_IRQ_168     2
-#define IT83XX_CPU_INT_IRQ_169     2
-#if defined(CHIP_FAMILY_IT8320)
-#define IT83XX_CPU_INT_IRQ_170     2
-#define IT83XX_CPU_INT_IRQ_171     2
-#define IT83XX_CPU_INT_IRQ_172     2
-#define IT83XX_CPU_INT_IRQ_173     2
-#define IT83XX_CPU_INT_IRQ_174     2
-#define IT83XX_CPU_INT_IRQ_175     2
-#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-#define IT83XX_CPU_INT_IRQ_170    12
-#define IT83XX_CPU_INT_IRQ_171    12
-#define IT83XX_CPU_INT_IRQ_172    12
-#define IT83XX_CPU_INT_IRQ_173    12
-#define IT83XX_CPU_INT_IRQ_174    12
-#define IT83XX_CPU_INT_IRQ_175    12
-#endif
-#define IT83XX_CPU_INT_IRQ_176     2
-#define IT83XX_CPU_INT_IRQ_177     2
-#define IT83XX_CPU_INT_IRQ_178     2
-#define IT83XX_CPU_INT_IRQ_179     2
-#define IT83XX_CPU_INT_IRQ_180     2
-#define IT83XX_CPU_INT_IRQ_181     2
-#define IT83XX_CPU_INT_IRQ_182     2
-#define IT83XX_CPU_INT_IRQ_183     2
-#define IT83XX_CPU_INT_IRQ_184     2
-#define IT83XX_CPU_INT_IRQ_185     2
-#define IT83XX_CPU_INT_IRQ_191     2
-#define IT83XX_CPU_INT_IRQ_192     2
-#define IT83XX_CPU_INT_IRQ_193     2
-#define IT83XX_CPU_INT_IRQ_194     2
-#define IT83XX_CPU_INT_IRQ_195     2
-#define IT83XX_CPU_INT_IRQ_196     2
-#define IT83XX_CPU_INT_IRQ_197     2
-#define IT83XX_CPU_INT_IRQ_199     2
-#define IT83XX_CPU_INT_IRQ_200     2
-#define IT83XX_CPU_INT_IRQ_201     2
-#define IT83XX_CPU_INT_IRQ_202     2
-#define IT83XX_CPU_INT_IRQ_203     2
-#define IT83XX_CPU_INT_IRQ_208     2
-#define IT83XX_CPU_INT_IRQ_209     2
-#define IT83XX_CPU_INT_IRQ_210     2
-#define IT83XX_CPU_INT_IRQ_211     2
-#define IT83XX_CPU_INT_IRQ_212     2
-#define IT83XX_CPU_INT_IRQ_213     2
-#define IT83XX_CPU_INT_IRQ_214     2
-#define IT83XX_CPU_INT_IRQ_216     2
-#define IT83XX_CPU_INT_IRQ_217     2
-#define IT83XX_CPU_INT_IRQ_218     2
-#define IT83XX_CPU_INT_IRQ_219     2
-#define IT83XX_CPU_INT_IRQ_220     2
-#define IT83XX_CPU_INT_IRQ_221     2
-#define IT83XX_CPU_INT_IRQ_224     2
-#define IT83XX_CPU_INT_IRQ_225     2
-#define IT83XX_CPU_INT_IRQ_226     2
-#define IT83XX_CPU_INT_IRQ_227     2
-#define IT83XX_CPU_INT_IRQ_228     2
-#define IT83XX_CPU_INT_IRQ_229     2
-
-/* "Fake" IRQ to declare in readable fashion all WKO IRQ routed to INT#2 */
-#define CPU_INT_2_ALL_GPIOS      255
-#define IT83XX_CPU_INT_IRQ_255     2
-
-#define CPU_INT_GROUP_5          254
-#define IT83XX_CPU_INT_IRQ_254     5
-
-#define CPU_INT_GROUP_4          252
-#define IT83XX_CPU_INT_IRQ_252     4
-
-#define CPU_INT_GROUP_12         253
-#define IT83XX_CPU_INT_IRQ_253    12
-
-#define CPU_INT_GROUP_3          251
-#define IT83XX_CPU_INT_IRQ_251     3
-
-#define CPU_INT_GROUP_6          250
-#define IT83XX_CPU_INT_IRQ_250     6
-
-#define CPU_INT_GROUP_9          249
-#define IT83XX_CPU_INT_IRQ_249     9
-
-#define CPU_INT_GROUP_7          248
-#define IT83XX_CPU_INT_IRQ_248     7
-
-#define CPU_INT(irq) CONCAT2(IT83XX_CPU_INT_IRQ_, irq)
-
-/* --- INTC --- */
-#define IT83XX_INTC_BASE    CHIP_EC_INTC_BASE
-
-#define IT83XX_INTC_REG(n)  REG8(IT83XX_INTC_BASE+(n))
-
-#define IT83XX_INTC_AIVCT   REG8(IT83XX_INTC_BASE+0x10)
-
-#define IT83XX_INTC_IER0    REG8(IT83XX_INTC_BASE+0x04)
-#define IT83XX_INTC_IER1    REG8(IT83XX_INTC_BASE+0x05)
-#define IT83XX_INTC_IER2    REG8(IT83XX_INTC_BASE+0x06)
-#define IT83XX_INTC_IER3    REG8(IT83XX_INTC_BASE+0x07)
-#define IT83XX_INTC_IER4    REG8(IT83XX_INTC_BASE+0x15)
-#define IT83XX_INTC_IER5    REG8(IT83XX_INTC_BASE+0x19)
-#define IT83XX_INTC_IER6    REG8(IT83XX_INTC_BASE+0x1d)
-#define IT83XX_INTC_IER7    REG8(IT83XX_INTC_BASE+0x21)
-#define IT83XX_INTC_IER8    REG8(IT83XX_INTC_BASE+0x25)
-#define IT83XX_INTC_IER9    REG8(IT83XX_INTC_BASE+0x29)
-#define IT83XX_INTC_IER10   REG8(IT83XX_INTC_BASE+0x2d)
-#define IT83XX_INTC_IER11   REG8(IT83XX_INTC_BASE+0x31)
-#define IT83XX_INTC_IER12   REG8(IT83XX_INTC_BASE+0x35)
-#define IT83XX_INTC_IER13   REG8(IT83XX_INTC_BASE+0x39)
-#define IT83XX_INTC_IER14   REG8(IT83XX_INTC_BASE+0x3d)
-#define IT83XX_INTC_IER15   REG8(IT83XX_INTC_BASE+0x41)
-#define IT83XX_INTC_IER16   REG8(IT83XX_INTC_BASE+0x45)
-#define IT83XX_INTC_IER17   REG8(IT83XX_INTC_BASE+0x49)
-#define IT83XX_INTC_IER18   REG8(IT83XX_INTC_BASE+0x4d)
-#define IT83XX_INTC_IER19   REG8(IT83XX_INTC_BASE+0x51)
-#define IT83XX_INTC_IER20   REG8(IT83XX_INTC_BASE+0x55)
-#define IT83XX_INTC_IER21   REG8(IT83XX_INTC_BASE+0x59)
-#define IT83XX_INTC_IER22   REG8(IT83XX_INTC_BASE+0x5d)
-#define IT83XX_INTC_IER23   REG8(IT83XX_INTC_BASE+0x91)
-#define IT83XX_INTC_IER24   REG8(IT83XX_INTC_BASE+0x95)
-#define IT83XX_INTC_IER25   REG8(IT83XX_INTC_BASE+0x99)
-#define IT83XX_INTC_IER26   REG8(IT83XX_INTC_BASE+0x9d)
-#define IT83XX_INTC_IER27   REG8(IT83XX_INTC_BASE+0xa1)
-#define IT83XX_INTC_IER28   REG8(IT83XX_INTC_BASE+0xa5)
-
-#define IT83XX_INTC_ISR0    REG8(IT83XX_INTC_BASE+0x00)
-#define IT83XX_INTC_ISR1    REG8(IT83XX_INTC_BASE+0x01)
-#define IT83XX_INTC_ISR2    REG8(IT83XX_INTC_BASE+0x02)
-#define IT83XX_INTC_ISR3    REG8(IT83XX_INTC_BASE+0x03)
-#define IT83XX_INTC_ISR4    REG8(IT83XX_INTC_BASE+0x14)
-#define IT83XX_INTC_ISR5    REG8(IT83XX_INTC_BASE+0x18)
-#define IT83XX_INTC_ISR6    REG8(IT83XX_INTC_BASE+0x1c)
-#define IT83XX_INTC_ISR7    REG8(IT83XX_INTC_BASE+0x20)
-#define IT83XX_INTC_ISR8    REG8(IT83XX_INTC_BASE+0x24)
-#define IT83XX_INTC_ISR9    REG8(IT83XX_INTC_BASE+0x28)
-#define IT83XX_INTC_ISR10   REG8(IT83XX_INTC_BASE+0x2c)
-#define IT83XX_INTC_ISR11   REG8(IT83XX_INTC_BASE+0x30)
-#define IT83XX_INTC_ISR12   REG8(IT83XX_INTC_BASE+0x34)
-#define IT83XX_INTC_ISR13   REG8(IT83XX_INTC_BASE+0x38)
-#define IT83XX_INTC_ISR14   REG8(IT83XX_INTC_BASE+0x3c)
-#define IT83XX_INTC_ISR15   REG8(IT83XX_INTC_BASE+0x40)
-#define IT83XX_INTC_ISR16   REG8(IT83XX_INTC_BASE+0x44)
-#define IT83XX_INTC_ISR17   REG8(IT83XX_INTC_BASE+0x48)
-#define IT83XX_INTC_ISR18   REG8(IT83XX_INTC_BASE+0x4c)
-#define IT83XX_INTC_ISR19   REG8(IT83XX_INTC_BASE+0x50)
-#define IT83XX_INTC_ISR20   REG8(IT83XX_INTC_BASE+0x54)
-#define IT83XX_INTC_ISR21   REG8(IT83XX_INTC_BASE+0x58)
-#define IT83XX_INTC_ISR22   REG8(IT83XX_INTC_BASE+0x5c)
-#define IT83XX_INTC_ISR23   REG8(IT83XX_INTC_BASE+0x90)
-#define IT83XX_INTC_ISR24   REG8(IT83XX_INTC_BASE+0x94)
-#define IT83XX_INTC_ISR25   REG8(IT83XX_INTC_BASE+0x98)
-#define IT83XX_INTC_ISR26   REG8(IT83XX_INTC_BASE+0x9c)
-#define IT83XX_INTC_ISR27   REG8(IT83XX_INTC_BASE+0xa0)
-#define IT83XX_INTC_ISR28   REG8(IT83XX_INTC_BASE+0xa4)
-
-#define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE+0x2E)
-#define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE+0x2F)
-#define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE+0x52)
-#define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE+0x53)
-
-#define IT83XX_INTC_EXT_IER_OFF(n) (0x60 + (n))
-#define IT83XX_INTC_IVCT(i)     REG8(IT83XX_INTC_BASE+0x80+(i))
-
-/* --- EC Access to the Host Controlled Modules (EC2I Bridge) --- */
-#define IT83XX_EC2I_BASE  0x00F01200
-
-#define IT83XX_EC2I_IHIOA       REG8(IT83XX_EC2I_BASE+0x00)
-#define IT83XX_EC2I_IHD         REG8(IT83XX_EC2I_BASE+0x01)
-#define IT83XX_EC2I_LSIOHA      REG8(IT83XX_EC2I_BASE+0x02)
-#define IT83XX_EC2I_SIOLV       REG8(IT83XX_EC2I_BASE+0x03)
-#define IT83XX_EC2I_IBMAE       REG8(IT83XX_EC2I_BASE+0x04)
-#define IT83XX_EC2I_IBCTL       REG8(IT83XX_EC2I_BASE+0x05)
-
-/* --- System Wake-UP Control (SWUC) --- */
-#define IT83XX_SWUC_BASE  0x00F01400
-#define IT83XX_SWUC_SWCTL1      REG8(IT83XX_SWUC_BASE+0x00)
-
-/* --- Wake-Up Control (WUC) --- */
-#define IT83XX_WUC_BASE   0x00F01B00
-
-#define IT83XX_WUC_WUEMR1 (IT83XX_WUC_BASE+0x00)
-#define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE+0x0c)
-#define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE+0x04)
-#define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE+0x0d)
-#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE+0x3c)
-#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE+0x0f)
-
-#define IT83XX_WUC_WUESR10    REG8(IT83XX_WUC_BASE+0x21)
-#define IT83XX_WUC_WUESR11    REG8(IT83XX_WUC_BASE+0x25)
-
-#define IT83XX_WUC_WUEMR3     REG8(IT83XX_WUC_BASE+0x02)
-#define IT83XX_WUC_WUESR3     REG8(IT83XX_WUC_BASE+0x06)
-#define IT83XX_WUC_WUENR3     REG8(IT83XX_WUC_BASE+0x0A)
-
-#define IT83XX_WUC_WUEMR4     REG8(IT83XX_WUC_BASE+0x03)
-#define IT83XX_WUC_WUESR4     REG8(IT83XX_WUC_BASE+0x07)
-#define IT83XX_WUC_WUENR4     REG8(IT83XX_WUC_BASE+0x0B)
-
-/* --- UART --- */
-#define IT83XX_UART0_BASE 0x00F02700
-#define IT83XX_UART1_BASE 0x00F02800
-
-#define IT83XX_UART_BASE(n)        CONCAT3(IT83XX_UART, n, _BASE)
-#define IT83XX_UART_REG(n, offset) REG8(IT83XX_UART_BASE(n) + (offset))
-
-#define IT83XX_UART_DLL(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_DLM(n)         IT83XX_UART_REG(n, 0x01)
-#define IT83XX_UART_RBR(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_THR(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_IER(n)         IT83XX_UART_REG(n, 0x01)
-#define IT83XX_UART_IIR(n)         IT83XX_UART_REG(n, 0x02)
-#define IT83XX_UART_FCR(n)         IT83XX_UART_REG(n, 0x02)
-#define IT83XX_UART_LCR(n)         IT83XX_UART_REG(n, 0x03)
-#define IT83XX_UART_MCR(n)         IT83XX_UART_REG(n, 0x04)
-#define IT83XX_UART_LSR(n)         IT83XX_UART_REG(n, 0x05)
-#define IT83XX_UART_MSR(n)         IT83XX_UART_REG(n, 0x06)
-#define IT83XX_UART_SCR(n)         IT83XX_UART_REG(n, 0x07)
-#define IT83XX_UART_ECSMPR(n)      IT83XX_UART_REG(n, 0x08)
-#define IT83XX_UART_CSSR(n)        IT83XX_UART_REG(n, 0x09)
-
-/* --- GPIO --- */
-
-#define IT83XX_GPIO_BASE  0x00F01600
-#define IT83XX_GPIO2_BASE 0x00F03E00
-
-#define IT83XX_GPIO_GCR         REG8(IT83XX_GPIO_BASE+0x00)
-#define IT83XX_GPIO_GCR_LPC_RST_B7      0x1
-#define IT83XX_GPIO_GCR_LPC_RST_D2      0x2
-#define IT83XX_GPIO_GCR_LPC_RST_DISABLE 0x3
-#define IT83XX_GPIO_GCR_LPC_RST_POS     1
-
-#define IT83XX_GPIO_GPDRA       REG8(IT83XX_GPIO_BASE+0x01)
-#define IT83XX_GPIO_GPDRB       REG8(IT83XX_GPIO_BASE+0x02)
-#define IT83XX_GPIO_GPDRC       REG8(IT83XX_GPIO_BASE+0x03)
-#define IT83XX_GPIO_GPDRE       REG8(IT83XX_GPIO_BASE+0x05)
-#define IT83XX_GPIO_GPDRF       REG8(IT83XX_GPIO_BASE+0x06)
-#define IT83XX_GPIO_GPDRH       REG8(IT83XX_GPIO_BASE+0x08)
-
-#define IT83XX_GPIO_GPCRA0      REG8(IT83XX_GPIO_BASE+0x10)
-#define IT83XX_GPIO_GPCRA1      REG8(IT83XX_GPIO_BASE+0x11)
-#define IT83XX_GPIO_GPCRA2      REG8(IT83XX_GPIO_BASE+0x12)
-#define IT83XX_GPIO_GPCRA3      REG8(IT83XX_GPIO_BASE+0x13)
-#define IT83XX_GPIO_GPCRA4      REG8(IT83XX_GPIO_BASE+0x14)
-#define IT83XX_GPIO_GPCRA5      REG8(IT83XX_GPIO_BASE+0x15)
-#define IT83XX_GPIO_GPCRA6      REG8(IT83XX_GPIO_BASE+0x16)
-#define IT83XX_GPIO_GPCRA7      REG8(IT83XX_GPIO_BASE+0x17)
-
-#define IT83XX_GPIO_GPCRB0      REG8(IT83XX_GPIO_BASE+0x18)
-#define IT83XX_GPIO_GPCRB1      REG8(IT83XX_GPIO_BASE+0x19)
-#define IT83XX_GPIO_GPCRB2      REG8(IT83XX_GPIO_BASE+0x1A)
-#define IT83XX_GPIO_GPCRB3      REG8(IT83XX_GPIO_BASE+0x1B)
-#define IT83XX_GPIO_GPCRB4      REG8(IT83XX_GPIO_BASE+0x1C)
-#define IT83XX_GPIO_GPCRB5      REG8(IT83XX_GPIO_BASE+0x1D)
-#define IT83XX_GPIO_GPCRB6      REG8(IT83XX_GPIO_BASE+0x1E)
-#define IT83XX_GPIO_GPCRB7      REG8(IT83XX_GPIO_BASE+0x1F)
-
-#define IT83XX_GPIO_GPCRC0      REG8(IT83XX_GPIO_BASE+0x20)
-#define IT83XX_GPIO_GPCRC1      REG8(IT83XX_GPIO_BASE+0x21)
-#define IT83XX_GPIO_GPCRC2      REG8(IT83XX_GPIO_BASE+0x22)
-#define IT83XX_GPIO_GPCRC3      REG8(IT83XX_GPIO_BASE+0x23)
-#define IT83XX_GPIO_GPCRC4      REG8(IT83XX_GPIO_BASE+0x24)
-#define IT83XX_GPIO_GPCRC5      REG8(IT83XX_GPIO_BASE+0x25)
-#define IT83XX_GPIO_GPCRC6      REG8(IT83XX_GPIO_BASE+0x26)
-#define IT83XX_GPIO_GPCRC7      REG8(IT83XX_GPIO_BASE+0x27)
-
-#define IT83XX_GPIO_GPCRE0      REG8(IT83XX_GPIO_BASE+0x30)
-#define IT83XX_GPIO_GPCRE1      REG8(IT83XX_GPIO_BASE+0x31)
-#define IT83XX_GPIO_GPCRE2      REG8(IT83XX_GPIO_BASE+0x32)
-#define IT83XX_GPIO_GPCRE3      REG8(IT83XX_GPIO_BASE+0x33)
-#define IT83XX_GPIO_GPCRE4      REG8(IT83XX_GPIO_BASE+0x34)
-#define IT83XX_GPIO_GPCRE5      REG8(IT83XX_GPIO_BASE+0x35)
-#define IT83XX_GPIO_GPCRE6      REG8(IT83XX_GPIO_BASE+0x36)
-#define IT83XX_GPIO_GPCRE7      REG8(IT83XX_GPIO_BASE+0x37)
-
-#define IT83XX_GPIO_GPCRF0      REG8(IT83XX_GPIO_BASE+0x38)
-#define IT83XX_GPIO_GPCRF1      REG8(IT83XX_GPIO_BASE+0x39)
-#define IT83XX_GPIO_GPCRF2      REG8(IT83XX_GPIO_BASE+0x3A)
-#define IT83XX_GPIO_GPCRF3      REG8(IT83XX_GPIO_BASE+0x3B)
-#define IT83XX_GPIO_GPCRF4      REG8(IT83XX_GPIO_BASE+0x3C)
-#define IT83XX_GPIO_GPCRF5      REG8(IT83XX_GPIO_BASE+0x3D)
-#define IT83XX_GPIO_GPCRF6      REG8(IT83XX_GPIO_BASE+0x3E)
-#define IT83XX_GPIO_GPCRF7      REG8(IT83XX_GPIO_BASE+0x3F)
-
-#define IT83XX_GPIO_GPCRH0      REG8(IT83XX_GPIO_BASE+0x48)
-#define IT83XX_GPIO_GPCRH1      REG8(IT83XX_GPIO_BASE+0x49)
-#define IT83XX_GPIO_GPCRH2      REG8(IT83XX_GPIO_BASE+0x4A)
-#define IT83XX_GPIO_GPCRH3      REG8(IT83XX_GPIO_BASE+0x4B)
-#define IT83XX_GPIO_GPCRH4      REG8(IT83XX_GPIO_BASE+0x4C)
-#define IT83XX_GPIO_GPCRH5      REG8(IT83XX_GPIO_BASE+0x4D)
-#define IT83XX_GPIO_GPCRH6      REG8(IT83XX_GPIO_BASE+0x4E)
-#define IT83XX_GPIO_GPCRH7      REG8(IT83XX_GPIO_BASE+0x4F)
-
-#define IT83XX_GPIO_GPCRI0      REG8(IT83XX_GPIO_BASE+0x50)
-#define IT83XX_GPIO_GPCRI1      REG8(IT83XX_GPIO_BASE+0x51)
-#define IT83XX_GPIO_GPCRI2      REG8(IT83XX_GPIO_BASE+0x52)
-#define IT83XX_GPIO_GPCRI3      REG8(IT83XX_GPIO_BASE+0x53)
-#define IT83XX_GPIO_GPCRI4      REG8(IT83XX_GPIO_BASE+0x54)
-#define IT83XX_GPIO_GPCRI5      REG8(IT83XX_GPIO_BASE+0x55)
-#define IT83XX_GPIO_GPCRI6      REG8(IT83XX_GPIO_BASE+0x56)
-#define IT83XX_GPIO_GPCRI7      REG8(IT83XX_GPIO_BASE+0x57)
-
-#define IT83XX_GPIO_GPCRM5      REG8(IT83XX_GPIO_BASE+0xA5)
-
-#define IT83XX_GPIO_GPDMRA      REG8(IT83XX_GPIO_BASE+0x61)
-#define IT83XX_GPIO_GPDMRB      REG8(IT83XX_GPIO_BASE+0x62)
-#define IT83XX_GPIO_GPDMRC      REG8(IT83XX_GPIO_BASE+0x63)
-#define IT83XX_GPIO_GPDMRE      REG8(IT83XX_GPIO_BASE+0x65)
-#define IT83XX_GPIO_GPDMRF      REG8(IT83XX_GPIO_BASE+0x66)
-#define IT83XX_GPIO_GPDMRH      REG8(IT83XX_GPIO_BASE+0x68)
-
-#define IT83XX_GPIO_GPCRL0      REG8(IT83XX_GPIO_BASE+0x98)
-#define IT83XX_GPIO_GPCRL1      REG8(IT83XX_GPIO_BASE+0x99)
-#define IT83XX_GPIO_GPCRL2      REG8(IT83XX_GPIO_BASE+0x9A)
-#define IT83XX_GPIO_GPCRL3      REG8(IT83XX_GPIO_BASE+0x9B)
-#define IT83XX_GPIO_GPCRP0      REG8(IT83XX_GPIO2_BASE+0x18)
-#define IT83XX_GPIO_GPCRP1      REG8(IT83XX_GPIO2_BASE+0x19)
-
-#define IT83XX_GPIO_GRC1        REG8(IT83XX_GPIO_BASE+0xF0)
-#define IT83XX_GPIO_GRC2        REG8(IT83XX_GPIO_BASE+0xF1)
-#define IT83XX_GPIO_GRC3        REG8(IT83XX_GPIO_BASE+0xF2)
-#define IT83XX_GPIO_GRC4        REG8(IT83XX_GPIO_BASE+0xF3)
-#define IT83XX_GPIO_GRC5        REG8(IT83XX_GPIO_BASE+0xF4)
-#define IT83XX_GPIO_GRC6        REG8(IT83XX_GPIO_BASE+0xF5)
-#define IT83XX_GPIO_GRC7        REG8(IT83XX_GPIO_BASE+0xF6)
-#define IT83XX_GPIO_GRC8        REG8(IT83XX_GPIO_BASE+0xF7)
-#define IT83XX_GPIO_GRC19       REG8(IT83XX_GPIO_BASE+0xE4)
-#define IT83XX_GPIO_GRC20       REG8(IT83XX_GPIO_BASE+0xE5)
-#define IT83XX_GPIO_GRC21       REG8(IT83XX_GPIO_BASE+0xE6)
-#define IT83XX_GPIO_GRC22       REG8(IT83XX_GPIO_BASE+0xE7)
-#define IT83XX_GPIO_GRC23       REG8(IT83XX_GPIO_BASE+0xE8)
-#define IT83XX_GPIO_GRC24       REG8(IT83XX_GPIO_BASE+0xE9)
-#define IT83XX_GPIO_GCR25       REG8(IT83XX_GPIO_BASE+0xD1)
-#define IT83XX_GPIO_GCR26       REG8(IT83XX_GPIO_BASE+0xD2)
-#define IT83XX_GPIO_GCR27       REG8(IT83XX_GPIO_BASE+0xD3)
-#define IT83XX_GPIO_GCR28       REG8(IT83XX_GPIO_BASE+0xD4)
-#define IT83XX_GPIO_GCR29       REG8(IT83XX_GPIO_BASE+0xEE)
-#define IT83XX_GPIO_GCR30       REG8(IT83XX_GPIO_BASE+0xED)
-#define IT83XX_GPIO_GCR31       REG8(IT83XX_GPIO_BASE+0xD5)
-#define IT83XX_GPIO_GCR32       REG8(IT83XX_GPIO_BASE+0xD6)
-#define IT83XX_GPIO_GCR33       REG8(IT83XX_GPIO_BASE+0xD7)
-
-#define IT83XX_VBATPC_BGPOPSCR  REG8(IT83XX_GPIO2_BASE+0xF0)
-#define IT83XX_VBATPC_XLPIER    REG8(IT83XX_GPIO2_BASE+0xF5)
-
-enum {
-	/* GPIO group index */
-	GPIO_A = 0x1,
-	GPIO_B = 0x2,
-	GPIO_C = 0x3,
-	GPIO_D = 0x4,
-	GPIO_E = 0x5,
-	GPIO_F = 0x6,
-	GPIO_G = 0x7,
-	GPIO_H = 0x8,
-	GPIO_I = 0x9,
-	GPIO_J = 0xa,
-	GPIO_K = 0xb,
-	GPIO_L = 0xc,
-	GPIO_M = 0xd,
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	GPIO_O = 0xe,
-	GPIO_P = 0xf,
-	GPIO_Q = 0x10,
-	GPIO_R = 0x11,
-#endif
-	GPIO_PORT_COUNT,
-
-	/*
-	 * NOTE: support flags when KSI/KSO are configured as GPIO
-	 * 1) it8320bx:
-	 * output: GPIO_OUTPUT, GPIO_OPEN_DRAIN, GPIO_HIGH, GPIO_LOW
-	 * input: GPIO_INPUT
-	 * 2) it8320dx, it8xxx1, and it8xxx2:
-	 * output: GPIO_OUTPUT, GPIO_OPEN_DRAIN(always internal pullup),
-	 *         GPIO_HIGH, GPIO_LOW
-	 * input: GPIO_INPUT, GPIO_PULL_UP
-	 */
-	/* KSI[7-0]  GPIO data mirror register. */
-	GPIO_KSI,
-	/* KSO[15-8] GPIO data mirror register. */
-	GPIO_KSO_H,
-	/* KSO[7-0]  GPIO data mirror register. */
-	GPIO_KSO_L,
-	/* Compiler check COUNT and gpio_group_to_reg member cnt match or not */
-	COUNT,
-};
-
-struct gpio_reg_t {
-	/* GPIO and KSI/KSO port data register (bit mapping to pin) */
-	uint32_t reg_gpdr;
-	/* GPIO and KSI/KSO port data mirror register (bit mapping to pin) */
-	uint32_t reg_gpdmr;
-	/* GPIO and KSI/KSO port output type register (bit mapping to pin) */
-	uint32_t reg_gpotr;
-	/* GPIO port control register (byte mapping to pin) */
-	uint32_t reg_gpcr;
-};
-
-/* GPIO group index convert to GPIO data/output type/ctrl group address */
-static const struct gpio_reg_t gpio_group_to_reg[] = {
-	/*               GPDR(set),  GPDMR(get), GPOTR,      GPCR      */
-	[GPIO_A]     = { 0x00F01601, 0x00F01661, 0x00F01671, 0x00F01610 },
-	[GPIO_B]     = { 0x00F01602, 0x00F01662, 0x00F01672, 0x00F01618 },
-	[GPIO_C]     = { 0x00F01603, 0x00F01663, 0x00F01673, 0x00F01620 },
-	[GPIO_D]     = { 0x00F01604, 0x00F01664, 0x00F01674, 0x00F01628 },
-	[GPIO_E]     = { 0x00F01605, 0x00F01665, 0x00F01675, 0x00F01630 },
-	[GPIO_F]     = { 0x00F01606, 0x00F01666, 0x00F01676, 0x00F01638 },
-	[GPIO_G]     = { 0x00F01607, 0x00F01667, 0x00F01677, 0x00F01640 },
-	[GPIO_H]     = { 0x00F01608, 0x00F01668, 0x00F01678, 0x00F01648 },
-	[GPIO_I]     = { 0x00F01609, 0x00F01669, 0x00F01679, 0x00F01650 },
-	[GPIO_J]     = { 0x00F0160A, 0x00F0166A, 0x00F0167A, 0x00F01658 },
-	[GPIO_K]     = { 0x00F0160B, 0x00F0166B, 0x00F0167B, 0x00F01690 },
-	[GPIO_L]     = { 0x00F0160C, 0x00F0166C, 0x00F0167C, 0x00F01698 },
-	[GPIO_M]     = { 0x00F0160D, 0x00F0166D, 0x00F0167D, 0x00F016a0 },
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[GPIO_O]     = { 0x00F03E01, 0x00F03E61, 0x00F03E71, 0x00F03E10 },
-	[GPIO_P]     = { 0x00F03E02, 0x00F03E62, 0x00F03E72, 0x00F03E18 },
-	[GPIO_Q]     = { 0x00F03E03, 0x00F03E63, 0x00F03E73, 0x00F03E20 },
-	[GPIO_R]     = { 0x00F03E04, 0x00F03E64, 0x00F03E74, 0x00F03E28 },
-#endif
-	[GPIO_KSI]   = { 0x00F01D08, 0x00F01D09, 0x00F01D26, 0xFFFFFFFF },
-	[GPIO_KSO_H] = { 0x00F01D01, 0x00F01D0C, 0x00F01D27, 0xFFFFFFFF },
-	[GPIO_KSO_L] = { 0x00F01D00, 0x00F01D0F, 0x00F01D28, 0xFFFFFFFF },
-};
-BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT));
-
-#define UNIMPLEMENTED_GPIO_BANK GPIO_A
-
-#define IT83XX_GPIO_DATA(port)                 \
-	REG8(gpio_group_to_reg[port].reg_gpdr)
-#define IT83XX_GPIO_DATA_MIRROR(port)          \
-	REG8(gpio_group_to_reg[port].reg_gpdmr)
-#define IT83XX_GPIO_GPOT(port)                 \
-	REG8(gpio_group_to_reg[port].reg_gpotr)
-#define IT83XX_GPIO_CTRL(port, pin_offset)     \
-	REG8(gpio_group_to_reg[port].reg_gpcr + pin_offset)
-#define GPCR_PORT_PIN_MODE_INPUT          BIT(7)
-#define GPCR_PORT_PIN_MODE_OUTPUT         BIT(6)
-#define GPCR_PORT_PIN_MODE_PULLUP         BIT(2)
-#define GPCR_PORT_PIN_MODE_PULLDOWN       BIT(1)
-
-/* --- Clock and Power Management (ECPM) --- */
-
-#define IT83XX_ECPM_BASE  0x00F01E00
-
-#define IT83XX_ECPM_CGCTRL1R_OFF 0x01
-#define IT83XX_ECPM_CGCTRL2R_OFF 0x02
-#define IT83XX_ECPM_CGCTRL3R_OFF 0x05
-#define IT83XX_ECPM_CGCTRL4R_OFF 0x09
-
-#define IT83XX_ECPM_PLLCTRL	REG8(IT83XX_ECPM_BASE+0x03)
-enum ec_pll_ctrl {
-	EC_PLL_DOZE = 0,
-	EC_PLL_SLEEP = 1,
-	EC_PLL_DEEP_DOZE = 3,
-};
-
-#define IT83XX_ECPM_AUTOCG	REG8(IT83XX_ECPM_BASE+0x04)
-#define IT83XX_ECPM_PLLFREQR	REG8(IT83XX_ECPM_BASE+0x06)
-#define IT83XX_ECPM_PLLCSS	REG8(IT83XX_ECPM_BASE+0x08)
-#define IT83XX_ECPM_SCDCR0	REG8(IT83XX_ECPM_BASE+0x0c)
-#define IT83XX_ECPM_SCDCR1	REG8(IT83XX_ECPM_BASE+0x0d)
-#define IT83XX_ECPM_SCDCR2	REG8(IT83XX_ECPM_BASE+0x0e)
-#define IT83XX_ECPM_SCDCR3	REG8(IT83XX_ECPM_BASE+0x0f)
-#define IT83XX_ECPM_SCDCR4	REG8(IT83XX_ECPM_BASE+0x10)
-
-/*
- * The clock gate offsets combine the register offset from ECPM_BASE and the
- * mask within that register into one value. These are used for
- * clock_enable_peripheral() and clock_disable_peripheral()
- */
-enum clock_gate_offsets {
-	CGC_OFFSET_EGPC  = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x40),
-	CGC_OFFSET_CIR   = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x20),
-	CGC_OFFSET_SWUC  = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x10),
-	CGC_OFFSET_USB   = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x20),
-	CGC_OFFSET_PECI  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x08),
-	CGC_OFFSET_UART  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04),
-	CGC_OFFSET_SSPI  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02),
-	CGC_OFFSET_DBGR  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01),
-	CGC_OFFSET_SMBF  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80),
-	CGC_OFFSET_SMBE  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40),
-	CGC_OFFSET_SMBD  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20),
-	CGC_OFFSET_SMBC  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10),
-	CGC_OFFSET_SMBB  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08),
-	CGC_OFFSET_SMBA  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04),
-	CGC_OFFSET_SMB   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02),
-	CGC_OFFSET_CEC   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01)
-};
-
-/* --- Timer (TMR) --- */
-#define IT83XX_TMR_BASE         0x00F02900
-
-#define IT83XX_TMR_PRSC         REG8(IT83XX_TMR_BASE+0x00)
-#define IT83XX_TMR_GCSMS        REG8(IT83XX_TMR_BASE+0x01)
-#define IT83XX_TMR_CTR_A0       REG8(IT83XX_TMR_BASE+0x02)
-#define IT83XX_TMR_CTR_A1       REG8(IT83XX_TMR_BASE+0x03)
-#define IT83XX_TMR_CTR_B0       REG8(IT83XX_TMR_BASE+0x04)
-#define IT83XX_TMR_CTR_B1       REG8(IT83XX_TMR_BASE+0x05)
-#define IT83XX_TMR_DCR_A0       REG8(IT83XX_TMR_BASE+0x06)
-#define IT83XX_TMR_DCR_A1       REG8(IT83XX_TMR_BASE+0x07)
-#define IT83XX_TMR_DCR_B0       REG8(IT83XX_TMR_BASE+0x08)
-#define IT83XX_TMR_DCR_B1       REG8(IT83XX_TMR_BASE+0x09)
-#define IT83XX_TMR_CCGSR        REG8(IT83XX_TMR_BASE+0x0A)
-#define IT83XX_TMR_TMRCE        REG8(IT83XX_TMR_BASE+0x0B)
-#define IT83XX_TMR_TMRIE        REG8(IT83XX_TMR_BASE+0x0C)
-
-/* --- External Timer and Watchdog (ETWD) --- */
-#define IT83XX_ETWD_BASE  0x00F01F00
-
-#define IT83XX_ETWD_ETWCFG        REG8(IT83XX_ETWD_BASE+0x01)
-#define IT83XX_ETWD_ET1PSR        REG8(IT83XX_ETWD_BASE+0x02)
-#define IT83XX_ETWD_ET1CNTLHR     REG8(IT83XX_ETWD_BASE+0x03)
-#define IT83XX_ETWD_ET1CNTLLR     REG8(IT83XX_ETWD_BASE+0x04)
-#define IT83XX_ETWD_ETWCTRL       REG8(IT83XX_ETWD_BASE+0x05)
-#define IT83XX_ETWD_EWDCNTLLR     REG8(IT83XX_ETWD_BASE+0x06)
-#define IT83XX_ETWD_EWDKEYR       REG8(IT83XX_ETWD_BASE+0x07)
-#define IT83XX_ETWD_EWDCNTLHR     REG8(IT83XX_ETWD_BASE+0x09)
-#define IT83XX_ETWD_ETXCTRL(n)    REG8(IT83XX_ETWD_BASE + 0x10 + (n << 3))
-#define IT83XX_ETWD_ETXPSR(n)     REG8(IT83XX_ETWD_BASE + 0x11 + (n << 3))
-#define IT83XX_ETWD_ETXCNTLR(n)   REG32(IT83XX_ETWD_BASE + 0x14 + (n << 3))
-#define IT83XX_ETWD_ETXCNTOR(n)   REG32(IT83XX_ETWD_BASE + 0x48 + (n << 2))
-
-/* --- General Control (GCTRL) --- */
-#define IT83XX_GCTRL_BASE 0x00F02000
-
-#ifdef IT83XX_CHIP_ID_3BYTES
-#define IT83XX_GCTRL_CHIPID1      REG8(IT83XX_GCTRL_BASE+0x85)
-#define IT83XX_GCTRL_CHIPID2      REG8(IT83XX_GCTRL_BASE+0x86)
-#define IT83XX_GCTRL_CHIPID3      REG8(IT83XX_GCTRL_BASE+0x87)
-#else
-#define IT83XX_GCTRL_CHIPID1      REG8(IT83XX_GCTRL_BASE+0x00)
-#define IT83XX_GCTRL_CHIPID2      REG8(IT83XX_GCTRL_BASE+0x01)
-#endif
-#define IT83XX_GCTRL_CHIPVER      REG8(IT83XX_GCTRL_BASE+0x02)
-#define IT83XX_GCTRL_DBGROS       REG8(IT83XX_GCTRL_BASE+0x03)
-#define IT83XX_SMB_DBGR           BIT(0)
-#define IT83XX_GCTRL_WNCKR        REG8(IT83XX_GCTRL_BASE+0x0B)
-#define IT83XX_GCTRL_RSTS         REG8(IT83XX_GCTRL_BASE+0x06)
-#define IT83XX_GCTRL_BADRSEL      REG8(IT83XX_GCTRL_BASE+0x0A)
-#define IT83XX_GCTRL_SPCTRL1      REG8(IT83XX_GCTRL_BASE+0x0D)
-#define IT83XX_GCTRL_RSTDMMC      REG8(IT83XX_GCTRL_BASE+0x10)
-#define IT83XX_GCTRL_RSTC4        REG8(IT83XX_GCTRL_BASE+0x11)
-#define IT83XX_GCTRL_SPCTRL4      REG8(IT83XX_GCTRL_BASE+0x1C)
-#define IT83XX_GCTRL_MCCR3        REG8(IT83XX_GCTRL_BASE+0x20)
-#define IT83XX_GCTRL_SPISLVPFE    BIT(6)
-#define IT83XX_GCTRL_RSTC5        REG8(IT83XX_GCTRL_BASE+0x21)
-#define IT83XX_GCTRL_MCCR         REG8(IT83XX_GCTRL_BASE+0x30)
-#define IT83XX_GCTRL_PMER1        REG8(IT83XX_GCTRL_BASE+0x32)
-#define IT83XX_GCTRL_PMER2        REG8(IT83XX_GCTRL_BASE+0x33)
-#define IT83XX_GCTRL_EPLR         REG8(IT83XX_GCTRL_BASE+0x37)
-#define IT83XX_GCTRL_IVTBAR       REG8(IT83XX_GCTRL_BASE+0x41)
-#define IT83XX_GCTRL_MCCR2        REG8(IT83XX_GCTRL_BASE+0x44)
-#define IT83XX_GCTRL_PIN_MUX0     REG8(IT83XX_GCTRL_BASE+0x46)
-#define IT83XX_DLM14_ENABLE       BIT(5)
-#define IT83XX_GCTRL_SSCR         REG8(IT83XX_GCTRL_BASE+0x4A)
-#define IT83XX_GCTRL_ETWDUARTCR   REG8(IT83XX_GCTRL_BASE+0x4B)
-#define IT83XX_GCTRL_WMCR         REG8(IT83XX_GCTRL_BASE+0x4C)
-#define IT83XX_GCTRL_H2ROFSR      REG8(IT83XX_GCTRL_BASE+0x53)
-/* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */
-#define ETWD_HW_RST_EN            BIT(0)
-#define IT83XX_GCTRL_RVILMCR0     REG8(IT83XX_GCTRL_BASE+0x5D)
-#define ILMCR_ILM0_ENABLE         BIT(0)
-#define ILMCR_ILM2_ENABLE         BIT(2)
-#define IT83XX_GCTRL_EWPR0PFH(i)  REG8(IT83XX_GCTRL_BASE+0x60+i)
-#define IT83XX_GCTRL_EWPR0PFD(i)  REG8(IT83XX_GCTRL_BASE+0xA0+i)
-#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i)
-
-/* --- Pulse Width Modulation (PWM) --- */
-#define IT83XX_PWM_BASE   0x00F01800
-
-#define IT83XX_PWM_C0CPRS       REG8(IT83XX_PWM_BASE+0x00)
-#define IT83XX_PWM_CTR          REG8(IT83XX_PWM_BASE+0x01)
-#define IT83XX_PWM_DCR0         REG8(IT83XX_PWM_BASE+0x02)
-#define IT83XX_PWM_DCR1         REG8(IT83XX_PWM_BASE+0x03)
-#define IT83XX_PWM_DCR2         REG8(IT83XX_PWM_BASE+0x04)
-#define IT83XX_PWM_DCR3         REG8(IT83XX_PWM_BASE+0x05)
-#define IT83XX_PWM_DCR4         REG8(IT83XX_PWM_BASE+0x06)
-#define IT83XX_PWM_DCR5         REG8(IT83XX_PWM_BASE+0x07)
-#define IT83XX_PWM_DCR6         REG8(IT83XX_PWM_BASE+0x08)
-#define IT83XX_PWM_DCR7         REG8(IT83XX_PWM_BASE+0x09)
-#define IT83XX_PWM_PWMPOL       REG8(IT83XX_PWM_BASE+0x0A)
-#define IT83XX_PWM_PCFSR        REG8(IT83XX_PWM_BASE+0x0B)
-#define IT83XX_PWM_PCSSGL       REG8(IT83XX_PWM_BASE+0x0C)
-#define IT83XX_PWM_PCSSGH       REG8(IT83XX_PWM_BASE+0x0D)
-#define IT83XX_PWM_CR256PCSSG   REG8(IT83XX_PWM_BASE+0x0E)
-#define IT83XX_PWM_PCSGR        REG8(IT83XX_PWM_BASE+0x0F)
-#define IT83XX_PWM_CTR1M        REG8(IT83XX_PWM_BASE+0x10)
-#define IT83XX_PWM_F1TLRR       REG8(IT83XX_PWM_BASE+0x1E)
-#define IT83XX_PWM_F1TMRR       REG8(IT83XX_PWM_BASE+0x1F)
-#define IT83XX_PWM_F2TLRR       REG8(IT83XX_PWM_BASE+0x20)
-#define IT83XX_PWM_F2TMRR       REG8(IT83XX_PWM_BASE+0x21)
-#define IT83XX_PWM_ZINTSCR      REG8(IT83XX_PWM_BASE+0x22)
-#define IT83XX_PWM_ZTIER        REG8(IT83XX_PWM_BASE+0x23)
-#define IT83XX_PWM_TSWCTLR      REG8(IT83XX_PWM_BASE+0x24)
-#define IT83XX_PWM_C4CPRS       REG8(IT83XX_PWM_BASE+0x27)
-#define IT83XX_PWM_C4MCPRS      REG8(IT83XX_PWM_BASE+0x28)
-#define IT83XX_PWM_C6CPRS       REG8(IT83XX_PWM_BASE+0x2B)
-#define IT83XX_PWM_C6MCPRS      REG8(IT83XX_PWM_BASE+0x2C)
-#define IT83XX_PWM_C7CPRS       REG8(IT83XX_PWM_BASE+0x2D)
-#define IT83XX_PWM_C7MCPRS      REG8(IT83XX_PWM_BASE+0x2E)
-#define IT83XX_PWM_CLK6MSEL     REG8(IT83XX_PWM_BASE+0x40)
-#define IT83XX_PWM_CTR1         REG8(IT83XX_PWM_BASE+0x41)
-#define IT83XX_PWM_CTR2         REG8(IT83XX_PWM_BASE+0x42)
-#define IT83XX_PWM_CTR3         REG8(IT83XX_PWM_BASE+0x43)
-#define IT83XX_PWM_PWM5TOCTRL   REG8(IT83XX_PWM_BASE+0x44)
-#define IT83XX_PWM_CFLRR        REG8(IT83XX_PWM_BASE+0x45)
-#define IT83XX_PWM_CFMRR        REG8(IT83XX_PWM_BASE+0x46)
-#define IT83XX_PWM_CFINTCTRL    REG8(IT83XX_PWM_BASE+0x47)
-#define IT83XX_PWM_TSWCTRL      REG8(IT83XX_PWM_BASE+0x48)
-#define IT83XX_PWM_PWMODENR     REG8(IT83XX_PWM_BASE+0x49)
-
-/* Analog to Digital Converter (ADC) */
-#define IT83XX_ADC_BASE   0x00F01900
-
-#define IT83XX_ADC_ADCSTS       REG8(IT83XX_ADC_BASE+0x00)
-#define IT83XX_ADC_ADCCFG       REG8(IT83XX_ADC_BASE+0x01)
-#define IT83XX_ADC_ADCCTL       REG8(IT83XX_ADC_BASE+0x02)
-#define IT83XX_ADC_ADCGCR       REG8(IT83XX_ADC_BASE+0x03)
-#define IT83XX_ADC_DBKEN            BIT(7) /* ADC data buffer keep enable. */
-#define IT83XX_ADC_VCH0CTL      REG8(IT83XX_ADC_BASE+0x04)
-#define IT83XX_ADC_KDCTL        REG8(IT83XX_ADC_BASE+0x05)
-#define IT83XX_ADC_AHCE             BIT(7)
-#define IT83XX_ADC_VCH1CTL      REG8(IT83XX_ADC_BASE+0x06)
-#define IT83XX_ADC_VCH1DATL     REG8(IT83XX_ADC_BASE+0x07)
-#define IT83XX_ADC_VCH1DATM     REG8(IT83XX_ADC_BASE+0x08)
-#define IT83XX_ADC_VCH2CTL      REG8(IT83XX_ADC_BASE+0x09)
-#define IT83XX_ADC_VCH2DATL     REG8(IT83XX_ADC_BASE+0x0A)
-#define IT83XX_ADC_VCH2DATM     REG8(IT83XX_ADC_BASE+0x0B)
-#define IT83XX_ADC_VCH3CTL      REG8(IT83XX_ADC_BASE+0x0C)
-#define IT83XX_ADC_VCH3DATL     REG8(IT83XX_ADC_BASE+0x0D)
-#define IT83XX_ADC_VCH3DATM     REG8(IT83XX_ADC_BASE+0x0E)
-#define IT83XX_ADC_VHSCDBL      REG8(IT83XX_ADC_BASE+0x14)
-#define IT83XX_ADC_VHSCDBM      REG8(IT83XX_ADC_BASE+0x15)
-#define IT83XX_ADC_VCH0DATL     REG8(IT83XX_ADC_BASE+0x18)
-#define IT83XX_ADC_VCH0DATM     REG8(IT83XX_ADC_BASE+0x19)
-#define IT83XX_ADC_VHSGCDBL     REG8(IT83XX_ADC_BASE+0x1C)
-#define IT83XX_ADC_VHSGCDBM     REG8(IT83XX_ADC_BASE+0x1D)
-#define IT83XX_ADC_ADCSAR       REG8(IT83XX_ADC_BASE+0x32)
-#define IT83XX_ADC_VCMPSCP      REG8(IT83XX_ADC_BASE+0x37)
-#define IT83XX_ADC_VCH4CTL      REG8(IT83XX_ADC_BASE+0x38)
-#define IT83XX_ADC_VCH4DATM     REG8(IT83XX_ADC_BASE+0x39)
-#define IT83XX_ADC_VCH4DATL     REG8(IT83XX_ADC_BASE+0x3A)
-#define IT83XX_ADC_VCH5CTL      REG8(IT83XX_ADC_BASE+0x3B)
-#define IT83XX_ADC_VCH5DATM     REG8(IT83XX_ADC_BASE+0x3C)
-#define IT83XX_ADC_VCH5DATL     REG8(IT83XX_ADC_BASE+0x3D)
-#define IT83XX_ADC_VCH6CTL      REG8(IT83XX_ADC_BASE+0x3E)
-#define IT83XX_ADC_VCH6DATM     REG8(IT83XX_ADC_BASE+0x3F)
-#define IT83XX_ADC_VCH6DATL     REG8(IT83XX_ADC_BASE+0x40)
-#define IT83XX_ADC_VCH7CTL      REG8(IT83XX_ADC_BASE+0x41)
-#define IT83XX_ADC_VCH7DATM     REG8(IT83XX_ADC_BASE+0x42)
-#define IT83XX_ADC_VCH7DATL     REG8(IT83XX_ADC_BASE+0x43)
-#define IT83XX_ADC_ADCDVSTS     REG8(IT83XX_ADC_BASE+0x44)
-#define IT83XX_ADC_VCMPSTS      REG8(IT83XX_ADC_BASE+0x45)
-#define IT83XX_ADC_VCMP0CTL     REG8(IT83XX_ADC_BASE+0x46)
-#define ADC_VCMP_CMPEN              BIT(7)
-#define ADC_VCMP_CMPINTEN           BIT(6)
-#define ADC_VCMP_GREATER_THRESHOLD  BIT(5)
-#define ADC_VCMP_EDGE_TRIGGER       BIT(4)
-#define ADC_VCMP_GPIO_ACTIVE_LOW    BIT(3)
-#define IT83XX_ADC_CMP0THRDATM  REG8(IT83XX_ADC_BASE+0x47)
-#define IT83XX_ADC_CMP0THRDATL  REG8(IT83XX_ADC_BASE+0x48)
-#define IT83XX_ADC_VCMP1CTL     REG8(IT83XX_ADC_BASE+0x49)
-#define IT83XX_ADC_CMP1THRDATM  REG8(IT83XX_ADC_BASE+0x4A)
-#define IT83XX_ADC_CMP1THRDATL  REG8(IT83XX_ADC_BASE+0x4B)
-#define IT83XX_ADC_VCMP2CTL     REG8(IT83XX_ADC_BASE+0x4C)
-#define IT83XX_ADC_CMP2THRDATM  REG8(IT83XX_ADC_BASE+0x4D)
-#define IT83XX_ADC_CMP2THRDATL  REG8(IT83XX_ADC_BASE+0x4E)
-#define IT83XX_ADC_VCH13CTL     REG8(IT83XX_ADC_BASE+0x60)
-#define IT83XX_ADC_VCH13DATM    REG8(IT83XX_ADC_BASE+0x61)
-#define IT83XX_ADC_VCH13DATL    REG8(IT83XX_ADC_BASE+0x62)
-#define IT83XX_ADC_VCH14CTL     REG8(IT83XX_ADC_BASE+0x63)
-#define IT83XX_ADC_VCH14DATM    REG8(IT83XX_ADC_BASE+0x64)
-#define IT83XX_ADC_VCH14DATL    REG8(IT83XX_ADC_BASE+0x65)
-#define IT83XX_ADC_VCH15CTL     REG8(IT83XX_ADC_BASE+0x66)
-#define IT83XX_ADC_VCH15DATM    REG8(IT83XX_ADC_BASE+0x67)
-#define IT83XX_ADC_VCH15DATL    REG8(IT83XX_ADC_BASE+0x68)
-#define IT83XX_ADC_VCH16CTL     REG8(IT83XX_ADC_BASE+0x69)
-#define IT83XX_ADC_VCH16DATM    REG8(IT83XX_ADC_BASE+0x6A)
-#define IT83XX_ADC_VCH16DATL    REG8(IT83XX_ADC_BASE+0x6B)
-#define IT83XX_ADC_ADCDVSTS2    REG8(IT83XX_ADC_BASE+0x6C)
-#define IT83XX_ADC_VCMPSTS2     REG8(IT83XX_ADC_BASE+0x6D)
-#define IT83XX_ADC_VCMP3CTL     REG8(IT83XX_ADC_BASE+0x6E)
-#define IT83XX_ADC_CMP3THRDATM  REG8(IT83XX_ADC_BASE+0x6F)
-#define IT83XX_ADC_CMP3THRDATL  REG8(IT83XX_ADC_BASE+0x70)
-#define IT83XX_ADC_VCMP4CTL     REG8(IT83XX_ADC_BASE+0x71)
-#define IT83XX_ADC_CMP4THRDATM  REG8(IT83XX_ADC_BASE+0x72)
-#define IT83XX_ADC_CMP4THRDATL  REG8(IT83XX_ADC_BASE+0x73)
-#define IT83XX_ADC_VCMP5CTL     REG8(IT83XX_ADC_BASE+0x74)
-#define IT83XX_ADC_CMP5THRDATM  REG8(IT83XX_ADC_BASE+0x75)
-#define IT83XX_ADC_CMP5THRDATL  REG8(IT83XX_ADC_BASE+0x76)
-#define IT83XX_ADC_VCMP0CSELM   REG8(IT83XX_ADC_BASE+0x77)
-#define ADC_VCMP_VCMPCSELM          BIT(0)
-#define IT83XX_ADC_VCMP1CSELM   REG8(IT83XX_ADC_BASE+0x78)
-#define IT83XX_ADC_VCMP2CSELM   REG8(IT83XX_ADC_BASE+0x79)
-#define IT83XX_ADC_VCMP3CSELM   REG8(IT83XX_ADC_BASE+0x7A)
-#define IT83XX_ADC_VCMP4CSELM   REG8(IT83XX_ADC_BASE+0x7B)
-#define IT83XX_ADC_VCMP5CSELM   REG8(IT83XX_ADC_BASE+0x7C)
-
-/* Digital to Analog Converter (DAC) */
-#define IT83XX_DAC_BASE   0x00F01A00
-
-#define IT83XX_DAC_DACPDREG     REG8(IT83XX_DAC_BASE+0x01)
-#define IT83XX_DAC_POWDN(ch)    BIT(ch)
-#define IT83XX_DAC_DACDAT(ch)   REG8(IT83XX_DAC_BASE+0x02+ch)
-
-/* Keyboard Controller (KBC) */
-#define IT83XX_KBC_BASE   0x00F01300
-
-#define IT83XX_KBC_KBHICR       REG8(IT83XX_KBC_BASE+0x00)
-#define IT83XX_KBC_KBIRQR       REG8(IT83XX_KBC_BASE+0x02)
-#define IT83XX_KBC_KBHISR       REG8(IT83XX_KBC_BASE+0x04)
-#define IT83XX_KBC_KBHIKDOR     REG8(IT83XX_KBC_BASE+0x06)
-#define IT83XX_KBC_KBHIMDOR     REG8(IT83XX_KBC_BASE+0x08)
-#define IT83XX_KBC_KBHIDIR      REG8(IT83XX_KBC_BASE+0x0A)
-
-/* Power Management Channel (PMC) */
-#define IT83XX_PMC_BASE   0x00F01500
-
-#define IT83XX_PMC_PM1STS       REG8(IT83XX_PMC_BASE+0x00)
-#define IT83XX_PMC_PM1DO        REG8(IT83XX_PMC_BASE+0x01)
-#define IT83XX_PMC_PM1DOSCI     REG8(IT83XX_PMC_BASE+0x02)
-#define IT83XX_PMC_PM1DOSMI     REG8(IT83XX_PMC_BASE+0x03)
-#define IT83XX_PMC_PM1DI        REG8(IT83XX_PMC_BASE+0x04)
-#define IT83XX_PMC_PM1DISCI     REG8(IT83XX_PMC_BASE+0x05)
-#define IT83XX_PMC_PM1CTL       REG8(IT83XX_PMC_BASE+0x06)
-#define IT83XX_PMC_PM1IC        REG8(IT83XX_PMC_BASE+0x07)
-#define IT83XX_PMC_PM1IE        REG8(IT83XX_PMC_BASE+0x08)
-#define IT83XX_PMC_PM2STS       REG8(IT83XX_PMC_BASE+0x10)
-#define IT83XX_PMC_PM2DO        REG8(IT83XX_PMC_BASE+0x11)
-#define IT83XX_PMC_PM2DOSCI     REG8(IT83XX_PMC_BASE+0x12)
-#define IT83XX_PMC_PM2DOSMI     REG8(IT83XX_PMC_BASE+0x13)
-#define IT83XX_PMC_PM2DI        REG8(IT83XX_PMC_BASE+0x14)
-#define IT83XX_PMC_PM2DISCI     REG8(IT83XX_PMC_BASE+0x15)
-#define IT83XX_PMC_PM2CTL       REG8(IT83XX_PMC_BASE+0x16)
-#define IT83XX_PMC_PM2IC        REG8(IT83XX_PMC_BASE+0x17)
-#define IT83XX_PMC_PM2IE        REG8(IT83XX_PMC_BASE+0x18)
-#define IT83XX_PMC_PM3STS       REG8(IT83XX_PMC_BASE+0x20)
-#define IT83XX_PMC_PM3DO        REG8(IT83XX_PMC_BASE+0x21)
-#define IT83XX_PMC_PM3DI        REG8(IT83XX_PMC_BASE+0x22)
-#define IT83XX_PMC_PM3CTL       REG8(IT83XX_PMC_BASE+0x23)
-#define IT83XX_PMC_PM3IC        REG8(IT83XX_PMC_BASE+0x24)
-#define IT83XX_PMC_PM3IE        REG8(IT83XX_PMC_BASE+0x25)
-#define IT83XX_PMC_PM4STS       REG8(IT83XX_PMC_BASE+0x30)
-#define IT83XX_PMC_PM4DO        REG8(IT83XX_PMC_BASE+0x31)
-#define IT83XX_PMC_PM4DI        REG8(IT83XX_PMC_BASE+0x32)
-#define IT83XX_PMC_PM4CTL       REG8(IT83XX_PMC_BASE+0x33)
-#define IT83XX_PMC_PM4IC        REG8(IT83XX_PMC_BASE+0x34)
-#define IT83XX_PMC_PM4IE        REG8(IT83XX_PMC_BASE+0x35)
-#define IT83XX_PMC_PM5STS       REG8(IT83XX_PMC_BASE+0x40)
-#define IT83XX_PMC_PM5DO        REG8(IT83XX_PMC_BASE+0x41)
-#define IT83XX_PMC_PM5DI        REG8(IT83XX_PMC_BASE+0x42)
-#define IT83XX_PMC_PM5CTL       REG8(IT83XX_PMC_BASE+0x43)
-#define IT83XX_PMC_PM5IC        REG8(IT83XX_PMC_BASE+0x44)
-#define IT83XX_PMC_PM5IE        REG8(IT83XX_PMC_BASE+0x45)
-#define IT83XX_PMC_MBXCTRL      REG8(IT83XX_PMC_BASE+0x19)
-#define IT83XX_PMC_MBXEC_00     REG8(IT83XX_PMC_BASE+0xF0)
-#define IT83XX_PMC_MBXEC_01     REG8(IT83XX_PMC_BASE+0xF1)
-#define IT83XX_PMC_MBXEC_02     REG8(IT83XX_PMC_BASE+0xF2)
-#define IT83XX_PMC_MBXEC_03     REG8(IT83XX_PMC_BASE+0xF3)
-#define IT83XX_PMC_MBXEC_04     REG8(IT83XX_PMC_BASE+0xF4)
-#define IT83XX_PMC_MBXEC_05     REG8(IT83XX_PMC_BASE+0xF5)
-#define IT83XX_PMC_MBXEC_06     REG8(IT83XX_PMC_BASE+0xF6)
-#define IT83XX_PMC_MBXEC_07     REG8(IT83XX_PMC_BASE+0xF7)
-#define IT83XX_PMC_MBXEC_08     REG8(IT83XX_PMC_BASE+0xF8)
-#define IT83XX_PMC_MBXEC_09     REG8(IT83XX_PMC_BASE+0xF9)
-#define IT83XX_PMC_MBXEC_10     REG8(IT83XX_PMC_BASE+0xFA)
-#define IT83XX_PMC_MBXEC_11     REG8(IT83XX_PMC_BASE+0xFB)
-#define IT83XX_PMC_MBXEC_12     REG8(IT83XX_PMC_BASE+0xFC)
-#define IT83XX_PMC_MBXEC_13     REG8(IT83XX_PMC_BASE+0xFD)
-#define IT83XX_PMC_MBXEC_14     REG8(IT83XX_PMC_BASE+0xFE)
-#define IT83XX_PMC_MBXEC_15     REG8(IT83XX_PMC_BASE+0xFF)
-#define IT83XX_PMC_PMSTS(ch)    REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4))
-#define IT83XX_PMC_PMDO(ch)     REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4))
-#define IT83XX_PMC_PMDI(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4))
-#define IT83XX_PMC_PMCTL(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4))
-#define IT83XX_PMC_PMIE(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
-
-/* Keyboard Matrix Scan control (KBS) */
-#define IT83XX_KBS_BASE   0x00F01D00
-
-#define IT83XX_KBS_KSOL         REG8(IT83XX_KBS_BASE+0x00)
-#define IT83XX_KBS_KSOH1        REG8(IT83XX_KBS_BASE+0x01)
-#define IT83XX_KBS_KSOCTRL      REG8(IT83XX_KBS_BASE+0x02)
-#define IT83XX_KBS_KSOH2        REG8(IT83XX_KBS_BASE+0x03)
-#define IT83XX_KBS_KSI          REG8(IT83XX_KBS_BASE+0x04)
-#define IT83XX_KBS_KSICTRL      REG8(IT83XX_KBS_BASE+0x05)
-#define IT83XX_KBS_KSIGCTRL     REG8(IT83XX_KBS_BASE+0x06)
-#define IT83XX_KBS_KSIGOEN      REG8(IT83XX_KBS_BASE+0x07)
-#define IT83XX_KBS_KSIGDAT      REG8(IT83XX_KBS_BASE+0x08)
-#define IT83XX_KBS_KSIGDMRR     REG8(IT83XX_KBS_BASE+0x09)
-#define IT83XX_KBS_KSOHGCTRL    REG8(IT83XX_KBS_BASE+0x0A)
-#define IT83XX_KBS_KSOHGOEN     REG8(IT83XX_KBS_BASE+0x0B)
-#define IT83XX_KBS_KSOHGDMRR    REG8(IT83XX_KBS_BASE+0x0C)
-#define IT83XX_KBS_KSOLGCTRL    REG8(IT83XX_KBS_BASE+0x0D)
-#define IT83XX_KBS_KSOLGOEN     REG8(IT83XX_KBS_BASE+0x0E)
-#define IT83XX_KBS_KSOLGDMRR    REG8(IT83XX_KBS_BASE+0x0F)
-#define IT83XX_KBS_KSO0LSDR     REG8(IT83XX_KBS_BASE+0x10)
-#define IT83XX_KBS_KSO1LSDR     REG8(IT83XX_KBS_BASE+0x11)
-#define IT83XX_KBS_KSO2LSDR     REG8(IT83XX_KBS_BASE+0x12)
-#define IT83XX_KBS_KSO3LSDR     REG8(IT83XX_KBS_BASE+0x13)
-#define IT83XX_KBS_KSO4LSDR     REG8(IT83XX_KBS_BASE+0x14)
-#define IT83XX_KBS_KSO5LSDR     REG8(IT83XX_KBS_BASE+0x15)
-#define IT83XX_KBS_KSO6LSDR     REG8(IT83XX_KBS_BASE+0x16)
-#define IT83XX_KBS_KSO7LSDR     REG8(IT83XX_KBS_BASE+0x17)
-#define IT83XX_KBS_KSO8LSDR     REG8(IT83XX_KBS_BASE+0x18)
-#define IT83XX_KBS_KSO9LSDR     REG8(IT83XX_KBS_BASE+0x19)
-#define IT83XX_KBS_KSO10LSDR    REG8(IT83XX_KBS_BASE+0x1A)
-#define IT83XX_KBS_KSO11LSDR    REG8(IT83XX_KBS_BASE+0x1B)
-#define IT83XX_KBS_KSO12LSDR    REG8(IT83XX_KBS_BASE+0x1C)
-#define IT83XX_KBS_KSO13LSDR    REG8(IT83XX_KBS_BASE+0x1D)
-#define IT83XX_KBS_KSO14LSDR    REG8(IT83XX_KBS_BASE+0x1E)
-#define IT83XX_KBS_KSO15LSDR    REG8(IT83XX_KBS_BASE+0x1F)
-#define IT83XX_KBS_KSO16LSDR    REG8(IT83XX_KBS_BASE+0x20)
-#define IT83XX_KBS_KSO17LSDR    REG8(IT83XX_KBS_BASE+0x21)
-#define IT83XX_KBS_SDC1R        REG8(IT83XX_KBS_BASE+0x22)
-#define IT83XX_KBS_SDC2R        REG8(IT83XX_KBS_BASE+0x23)
-#define IT83XX_KBS_SDC3R        REG8(IT83XX_KBS_BASE+0x24)
-#define IT83XX_KBS_SDSR         REG8(IT83XX_KBS_BASE+0x25)
-#define IT83XX_KBS_KSIGPODR     REG8(IT83XX_KBS_BASE+0x26)
-#define IT83XX_KBS_KSOHGPODR    REG8(IT83XX_KBS_BASE+0x27)
-#define IT83XX_KBS_KSOLGPODR    REG8(IT83XX_KBS_BASE+0x28)
-
-/* Shared Memory Flash Interface Bridge (SMFI) */
-#define IT83XX_SMFI_BASE  0x00F01000
-
-#define IT83XX_SMFI_SMECCS      REG8(IT83XX_SMFI_BASE+0x20)
-#define IT83XX_SMFI_MASK_HOSTWA 	BIT(5)
-#define IT83XX_SMFI_HRAMWC      REG8(IT83XX_SMFI_BASE+0x5A)
-#define IT83XX_SMFI_HRAMW0BA    REG8(IT83XX_SMFI_BASE+0x5B)
-#define IT83XX_SMFI_HRAMW1BA    REG8(IT83XX_SMFI_BASE+0x5C)
-#define IT83XX_SMFI_HRAMW0AAS   REG8(IT83XX_SMFI_BASE+0x5D)
-#define IT83XX_SMFI_HRAMW1AAS   REG8(IT83XX_SMFI_BASE+0x5E)
-#define IT83XX_SMFI_HRAMW2BA    REG8(IT83XX_SMFI_BASE+0x76)
-#define IT83XX_SMFI_HRAMW3BA    REG8(IT83XX_SMFI_BASE+0x77)
-#define IT83XX_SMFI_HRAMW2AAS   REG8(IT83XX_SMFI_BASE+0x78)
-#define IT83XX_SMFI_HRAMW3AAS   REG8(IT83XX_SMFI_BASE+0x79)
-#define IT83XX_SMFI_H2RAMECSIE  REG8(IT83XX_SMFI_BASE+0x7A)
-#define IT83XX_SMFI_H2RAMECSA   REG8(IT83XX_SMFI_BASE+0x7B)
-#define IT83XX_SMFI_H2RAMHSS    REG8(IT83XX_SMFI_BASE+0x7C)
-#define IT83XX_SMFI_ECINDAR0    REG8(IT83XX_SMFI_BASE+0x3B)
-#define IT83XX_SMFI_ECINDAR1    REG8(IT83XX_SMFI_BASE+0x3C)
-#define IT83XX_SMFI_ECINDAR2    REG8(IT83XX_SMFI_BASE+0x3D)
-#define IT83XX_SMFI_ECINDAR3    REG8(IT83XX_SMFI_BASE+0x3E)
-#define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
-#define IT83XX_SMFI_ECINDDR     REG8(IT83XX_SMFI_BASE+0x3F)
-#define IT83XX_SMFI_SCAR0L      REG8(IT83XX_SMFI_BASE+0x40)
-#define IT83XX_SMFI_SCAR0M      REG8(IT83XX_SMFI_BASE+0x41)
-#define IT83XX_SMFI_SCAR0H      REG8(IT83XX_SMFI_BASE+0x42)
-#define IT83XX_SMFI_SCAR2L      REG8(IT83XX_SMFI_BASE+0x46)
-#define IT83XX_SMFI_SCAR2M      REG8(IT83XX_SMFI_BASE+0x47)
-#define IT83XX_SMFI_SCAR2H      REG8(IT83XX_SMFI_BASE+0x48)
-#define IT83XX_SMFI_FLHCTRL3R   REG8(IT83XX_SMFI_BASE+0x63)
-#define IT83XX_SMFI_STCDMACR    REG8(IT83XX_SMFI_BASE+0x80)
-#define IT83XX_SMFI_FLHCTRL6R   REG8(IT83XX_SMFI_BASE+0xA2)
-/* Enable EC-indirect page program command */
-#define IT83XX_SMFI_MASK_ECINDPP BIT(3)
-
-/* Serial Peripheral Interface (SSPI) */
-#define IT83XX_SSPI_BASE  0x00F02600
-
-#define IT83XX_SSPI_SPIDATA     REG8(IT83XX_SSPI_BASE+0x00)
-#define IT83XX_SSPI_SPICTRL1    REG8(IT83XX_SSPI_BASE+0x01)
-#define IT83XX_SSPI_SPICTRL2    REG8(IT83XX_SSPI_BASE+0x02)
-#define IT83XX_SSPI_SPISTS      REG8(IT83XX_SSPI_BASE+0x03)
-#define IT83XX_SSPI_SPICTRL3    REG8(IT83XX_SSPI_BASE+0x04)
-
-/* Serial Peripheral Interface (SPI) */
-#define IT83XX_SPI_BASE  0x00F03A00
-
-#define IT83XX_SPI_SPISGCR      REG8(IT83XX_SPI_BASE+0x00)
-#define IT83XX_SPI_SPISCEN         BIT(0)
-#define IT83XX_SPI_TXRXFAR      REG8(IT83XX_SPI_BASE+0x01)
-#define IT83XX_SPI_CPURXF2A        BIT(4)
-#define IT83XX_SPI_CPURXF1A        BIT(3)
-#define IT83XX_SPI_CPUTFA          BIT(1)
-#define IT83XX_SPI_TXFCR        REG8(IT83XX_SPI_BASE+0x02)
-#define IT83XX_SPI_TXFCMR          BIT(2)
-#define IT83XX_SPI_TXFR            BIT(1)
-#define IT83XX_SPI_TXFS            BIT(0)
-#define IT83XX_SPI_GCR2         REG8(IT83XX_SPI_BASE+0x03)
-#define IT83XX_SPI_RXF2OC          BIT(4)
-#define IT83XX_SPI_RXF1OC          BIT(3)
-#define IT83XX_SPI_RXFAR           BIT(0)
-#define IT83XX_SPI_IMR          REG8(IT83XX_SPI_BASE+0x04)
-#define IT83XX_SPI_RX_FIFO_FULL    BIT(7)
-#define IT83XX_SPI_RX_REACH        BIT(5)
-#define IT83XX_SPI_EDIM            BIT(2)
-#define IT83XX_SPI_ISR          REG8(IT83XX_SPI_BASE+0x05)
-#define IT83XX_SPI_TXFSR        REG8(IT83XX_SPI_BASE+0x06)
-#define IT83XX_SPI_ENDDETECTINT    BIT(2)
-#define IT83XX_SPI_RXFSR        REG8(IT83XX_SPI_BASE+0x07)
-#define IT83XX_SPI_RXFFSM          (BIT(4) | BIT(3))
-#define IT83XX_SPI_RXF2FS          BIT(2)
-#define IT83XX_SPI_RXF1FS          BIT(1)
-#ifdef CHIP_VARIANT_IT83202BX
-#define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x08)
-#else
-#define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x0b)
-#endif
-#define IT83XX_SPI_CPUWTFDB0    REG32(IT83XX_SPI_BASE+0x08)
-#define IT83XX_SPI_FCR          REG8(IT83XX_SPI_BASE+0x09)
-#define IT83XX_SPI_SPISRTXF        BIT(2)
-#define IT83XX_SPI_RXFR            BIT(1)
-#define IT83XX_SPI_RXFCMR          BIT(0)
-#define IT83XX_SPI_RXFRDRB0     REG32(IT83XX_SPI_BASE+0x0C)
-#define IT83XX_SPI_FTCB0R       REG8(IT83XX_SPI_BASE+0x18)
-#define IT83XX_SPI_FTCB1R       REG8(IT83XX_SPI_BASE+0x19)
-#define IT83XX_SPI_TCCB0        REG8(IT83XX_SPI_BASE+0x1A)
-#define IT83XX_SPI_TCCB1        REG8(IT83XX_SPI_BASE+0x1B)
-#define IT83XX_SPI_HPR2         REG8(IT83XX_SPI_BASE+0x1E)
-#define IT83XX_SPI_EMMCBMR      REG8(IT83XX_SPI_BASE+0x21)
-#define IT83XX_SPI_EMMCABM         BIT(1) /* eMMC Alternative Boot Mode */
-#define IT83XX_SPI_RX_VLISMR    REG8(IT83XX_SPI_BASE+0x26)
-#define IT83XX_SPI_RVLIM           BIT(0)
-#define IT83XX_SPI_RX_VLISR     REG8(IT83XX_SPI_BASE+0x27)
-#define IT83XX_SPI_RVLI            BIT(0)
-
-/* Platform Environment Control Interface (PECI) */
-#define IT83XX_PECI_BASE  0x00F02C00
-
-#define IT83XX_PECI_HOSTAR      REG8(IT83XX_PECI_BASE+0x00)
-#define IT83XX_PECI_HOCTLR      REG8(IT83XX_PECI_BASE+0x01)
-#define IT83XX_PECI_HOCMDR      REG8(IT83XX_PECI_BASE+0x02)
-#define IT83XX_PECI_HOTRADDR    REG8(IT83XX_PECI_BASE+0x03)
-#define IT83XX_PECI_HOWRLR      REG8(IT83XX_PECI_BASE+0x04)
-#define IT83XX_PECI_HORDLR      REG8(IT83XX_PECI_BASE+0x05)
-#define IT83XX_PECI_HOWRDR      REG8(IT83XX_PECI_BASE+0x06)
-#define IT83XX_PECI_HORDDR      REG8(IT83XX_PECI_BASE+0x07)
-#define IT83XX_PECI_HOCTL2R     REG8(IT83XX_PECI_BASE+0x08)
-#define IT83XX_PECI_RWFCSV      REG8(IT83XX_PECI_BASE+0x09)
-#define IT83XX_PECI_RRFCSV      REG8(IT83XX_PECI_BASE+0x0A)
-#define IT83XX_PECI_WFCSV       REG8(IT83XX_PECI_BASE+0x0B)
-#define IT83XX_PECI_RFCSV       REG8(IT83XX_PECI_BASE+0x0C)
-#define IT83XX_PECI_AWFCSV      REG8(IT83XX_PECI_BASE+0x0D)
-#define IT83XX_PECI_PADCTLR     REG8(IT83XX_PECI_BASE+0x0E)
-
-/*
- * The count number of the counter for 25 ms register.
- * The 25 ms register is calculated by (count number *1.024 kHz).
- */
-#define I2C_CLK_LOW_TIMEOUT  255 /* ~=249 ms */
-
-/* SMBus/I2C Interface (SMB/I2C) */
-#define IT83XX_SMB_BASE   0x00F01C00
-
-#define IT83XX_SMB_4P7USL       REG8(IT83XX_SMB_BASE+0x00)
-#define IT83XX_SMB_4P0USL       REG8(IT83XX_SMB_BASE+0x01)
-#define IT83XX_SMB_300NS        REG8(IT83XX_SMB_BASE+0x02)
-#define IT83XX_SMB_250NS        REG8(IT83XX_SMB_BASE+0x03)
-#define IT83XX_SMB_25MS         REG8(IT83XX_SMB_BASE+0x04)
-#define IT83XX_SMB_45P3USL      REG8(IT83XX_SMB_BASE+0x05)
-#define IT83XX_SMB_45P3USH      REG8(IT83XX_SMB_BASE+0x06)
-#define IT83XX_SMB_4P7A4P0H     REG8(IT83XX_SMB_BASE+0x07)
-#define IT83XX_SMB_SLVISELR     REG8(IT83XX_SMB_BASE+0x08)
-#define IT83XX_SMB_SCLKTS(ch)   REG8(IT83XX_SMB_BASE+0x09+ch)
-#define IT83XX_SMB_CHSEF        REG8(IT83XX_SMB_BASE+0x11)
-#define IT83XX_SMB_CHSAB        REG8(IT83XX_SMB_BASE+0x20)
-#define IT83XX_SMB_CHSCD        REG8(IT83XX_SMB_BASE+0x21)
-#define IT83XX_SMB_HOSTA(ch)    REG8(IT83XX_SMB_BASE+0x40+(ch << 6))
-#define IT83XX_SMB_HOCTL(ch)    REG8(IT83XX_SMB_BASE+0x41+(ch << 6))
-#define IT83XX_SMB_HOCMD(ch)    REG8(IT83XX_SMB_BASE+0x42+(ch << 6))
-#define IT83XX_SMB_TRASLA(ch)   REG8(IT83XX_SMB_BASE+0x43+(ch << 6))
-#define IT83XX_SMB_D0REG(ch)    REG8(IT83XX_SMB_BASE+0x44+(ch << 6))
-#define IT83XX_SMB_D1REG(ch)    REG8(IT83XX_SMB_BASE+0x45+(ch << 6))
-#define IT83XX_SMB_HOBDB(ch)    REG8(IT83XX_SMB_BASE+0x46+(ch << 6))
-#define IT83XX_SMB_PECERC(ch)   REG8(IT83XX_SMB_BASE+0x47+(ch << 6))
-#define IT83XX_SMB_SMBPCTL(ch)  REG8(IT83XX_SMB_BASE+0x4A+(ch << 6))
-#define IT83XX_SMB_HOCTL2(ch)   REG8(IT83XX_SMB_BASE+0x50+(ch << 6))
-#define IT83XX_SMB_SLVEN        (1 << 5)
-#define IT83XX_SMB_RESLADR      REG8(IT83XX_SMB_BASE+0x48)
-#define IT83XX_SMB_SLDA         REG8(IT83XX_SMB_BASE+0x49)
-#define IT83XX_SMB_SLSTA        REG8(IT83XX_SMB_BASE+0x4B)
-#define IT83XX_SMB_SPDS         (1 << 5)
-#define IT83XX_SMB_RCS          (1 << 3)
-#define IT83XX_SMB_STS          (1 << 2)
-#define IT83XX_SMB_SDS          (1 << 1)
-#define IT83XX_SMB_SICR         REG8(IT83XX_SMB_BASE+0x4C)
-#define IT83XX_SMB_RESLADR2     REG8(IT83XX_SMB_BASE+0x51)
-#define IT83XX_SMB_ENADDR2      (1 << 7)
-#define IT83XX_SMB_SFFCTL       REG8(IT83XX_SMB_BASE+0x55)
-#define IT83XX_SMB_HSAPE        BIT(1)
-#define IT83XX_SMB_SAFE         (1 << 0)
-#define IT83XX_SMB_SFFSTA       REG8(IT83XX_SMB_BASE+0x56)
-#define IT83XX_SMB_SFFFULL      (1 << 6)
-
-/* BRAM */
-#define IT83XX_BRAM_BASE  0x00F02200
-
-/* offset 0 ~ 0x7f */
-#define IT83XX_BRAM_BANK0(i)    REG8(IT83XX_BRAM_BASE + i)
-/* Battery backed RAM indices. */
-enum bram_indices {
-	/* reset flags uses 4 bytes */
-	BRAM_IDX_RESET_FLAGS0 = 0,
-	BRAM_IDX_RESET_FLAGS1 = 1,
-	BRAM_IDX_RESET_FLAGS2 = 2,
-	BRAM_IDX_RESET_FLAGS3 = 3,
-
-	/* PD state data for CONFIG_USB_PD_DUAL_ROLE uses 1 byte per port */
-	BRAM_IDX_PD0 =           4,
-	BRAM_IDX_PD1 =           5,
-	BRAM_IDX_PD2 =           6,
-
-	/* index 7 is reserved */
-
-	BRAM_IDX_SCRATCHPAD0  = 8,
-	BRAM_IDX_SCRATCHPAD1  = 9,
-	BRAM_IDX_SCRATCHPAD2  = 0xa,
-	BRAM_IDX_SCRATCHPAD3  = 0xb,
-
-	/* EC logs status */
-	BRAM_IDX_EC_LOG_STATUS = 0xc,
-
-	/* offset 0x0d ~ 0x1f are reserved for future use. */
-#if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI)
-	/*
-	 * offset 0x20 ~ 0x7b are reserved for future use.
-	 * (apply to x86 platform)
-	 */
-
-	/* This field is used to indicate BRAM is valid or not. */
-	BRAM_IDX_VALID_FLAGS0  = 0x7c,
-	BRAM_IDX_VALID_FLAGS1  = 0x7d,
-	BRAM_IDX_VALID_FLAGS2  = 0x7e,
-	BRAM_IDX_VALID_FLAGS3  = 0x7f
-	/* offset 0x7f is the end of BRAM bank 0. */
-#else
-
-	/* panic data uses 144 bytes (offset 0x20 ~ 0xaf) */
-	BRAM_PANIC_DATA_START  = 0x20,
-	BRAM_PANIC_DATA_END    = 0xaf,
-
-	/* This field is used to indicate BRAM is valid or not. */
-	BRAM_IDX_VALID_FLAGS0  = 0xbc,
-	BRAM_IDX_VALID_FLAGS1  = 0xbd,
-	BRAM_IDX_VALID_FLAGS2  = 0xbe,
-	BRAM_IDX_VALID_FLAGS3  = 0xbf
-	/* offset 0xbf is the end of BRAM bank 1. */
-#endif
-};
-#define BRAM_RESET_FLAGS0       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS0)
-#define BRAM_RESET_FLAGS1       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1)
-#define BRAM_RESET_FLAGS2       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS2)
-#define BRAM_RESET_FLAGS3       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS3)
-
-#define BRAM_SCRATCHPAD0        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD0)
-#define BRAM_SCRATCHPAD1        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1)
-#define BRAM_SCRATCHPAD2        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2)
-#define BRAM_SCRATCHPAD3        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3)
-
-#define BRAM_EC_LOG_STATUS      IT83XX_BRAM_BANK0(BRAM_IDX_EC_LOG_STATUS)
-enum bram_ec_logs_status {
-	EC_LOG_SAVED_IN_FLASH = 1,
-	EC_LOG_SAVED_IN_MEMORY
-};
-
-#define BRAM_VALID_FLAGS0       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS0)
-#define BRAM_VALID_FLAGS1       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS1)
-#define BRAM_VALID_FLAGS2       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS2)
-#define BRAM_VALID_FLAGS3       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS3)
-
-/*
- * These 128 bytes are use to latch port 80h data on x86 platform.
- * And they will be used to save panic data if the GPG1 reset mechanism
- * is enabled.
- */
-#if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI)
-/* offset 0x80 ~ 0xbf */
-#define IT83XX_BRAM_BANK1(i)    REG8(IT83XX_BRAM_BASE + 0x80 + i)
-#else
-/* Length of bram panic data */
-#define BRAM_PANIC_LEN (BRAM_PANIC_DATA_END - BRAM_PANIC_DATA_START + 1)
-#endif
-
-/*
- * Enhanced SMBus/I2C Interface
- * Ch_D: 0x00F03680 , Ch_E: 0x00F03500 , Ch_F: 0x00F03580
- * Ch_D: ch = 0x03  , Ch_E: ch = 0x00  , Ch_F: ch = 0x01
- */
-#define IT83XX_I2C_BASE   0x00F03500
-
-#define IT83XX_I2C_DRR(ch)           REG8(IT83XX_I2C_BASE+0x00+(ch << 7))
-#define IT83XX_I2C_PSR(ch)           REG8(IT83XX_I2C_BASE+0x01+(ch << 7))
-#define IT83XX_I2C_HSPR(ch)          REG8(IT83XX_I2C_BASE+0x02+(ch << 7))
-#define IT83XX_I2C_STR(ch)           REG8(IT83XX_I2C_BASE+0x03+(ch << 7))
-#define IT83XX_I2C_BB                (1 << 5)
-#define IT83XX_I2C_TIME_OUT          (1 << 3)
-#define IT83XX_I2C_RW                (1 << 2)
-#define IT83XX_I2C_INTPEND           (1 << 1)
-#define IT83XX_I2C_DHTR(ch)          REG8(IT83XX_I2C_BASE+0x04+(ch << 7))
-#define IT83XX_I2C_TOR(ch)           REG8(IT83XX_I2C_BASE+0x05+(ch << 7))
-#define IT83XX_I2C_DTR(ch)           REG8(IT83XX_I2C_BASE+0x08+(ch << 7))
-#define IT83XX_I2C_CTR(ch)           REG8(IT83XX_I2C_BASE+0x09+(ch << 7))
-#define IT83XX_I2C_INTEN             (1 << 6)
-#define IT83XX_I2C_MODE              (1 << 5)
-#define IT83XX_I2C_STARST            (1 << 4)
-#define IT83XX_I2C_ACK               (1 << 3)
-#define IT83XX_I2C_HALT              (1 << 0)
-#define IT83XX_I2C_CTR1(ch)          REG8(IT83XX_I2C_BASE+0x0A+(ch << 7))
-#define IT83XX_I2C_COMQ_EN           (1 << 7)
-#define IT83XX_I2C_MDL_EN            (1 << 1)
-#define IT83XX_I2C_BYTE_CNT_L(ch)    REG8(IT83XX_I2C_BASE+0x0C+(ch << 7))
-#define IT83XX_I2C_IRQ_ST(ch)        REG8(IT83XX_I2C_BASE+0x0D+(ch << 7))
-#define IT83XX_I2C_IDW_CLR           (1 << 3)
-#define IT83XX_I2C_IDR_CLR           (1 << 2)
-#define IT83XX_I2C_SLVDATAFLG        (1 << 1)
-#define IT83XX_I2C_P_CLR             (1 << 0)
-#define IT83XX_I2C_IDR(ch)           REG8(IT83XX_I2C_BASE+0x06+(ch << 7))
-#define IT83XX_I2C_TOS(ch)           REG8(IT83XX_I2C_BASE+0x07+(ch << 7))
-#define IT83XX_I2C_CLK_STR           (1 << 7)
-#define IT83XX_I2C_IDR2(ch)          REG8(IT83XX_I2C_BASE+0x1F+(ch << 7))
-#define IT83XX_I2C_RAMHA(ch)         REG8(IT83XX_I2C_BASE+0x23+(ch << 7))
-#define IT83XX_I2C_RAMLA(ch)         REG8(IT83XX_I2C_BASE+0x24+(ch << 7))
-#define IT83XX_I2C_RAMHA2(ch)        REG8(IT83XX_I2C_BASE+0x2B+(ch << 7))
-#define IT83XX_I2C_RAMLA2(ch)        REG8(IT83XX_I2C_BASE+0x2C+(ch << 7))
-#define IT83XX_I2C_CMD_ADDH(ch)      REG8(IT83XX_I2C_BASE+0x25+(ch << 7))
-#define IT83XX_I2C_CMD_ADDL(ch)      REG8(IT83XX_I2C_BASE+0x26+(ch << 7))
-#define IT83XX_I2C_RAMH2A(ch)        REG8(IT83XX_I2C_BASE+0x50+(ch << 7))
-#define IT83XX_I2C_CMD_ADDH2(ch)     REG8(IT83XX_I2C_BASE+0x52+(ch << 7))
-
-enum i2c_channels {
-	IT83XX_I2C_CH_A,  /* GPIO.B3/B4 */
-	IT83XX_I2C_CH_B,  /* GPIO.C1/C2 */
-	IT83XX_I2C_CH_C,  /* GPIO.F6/F7 or GPIO.C7/F7 */
-	IT83XX_I2C_CH_D,  /* GPIO.H1/H2 */
-	IT83XX_I2C_CH_E,  /* GPIO.E0/E7 */
-	IT83XX_I2C_CH_F,  /* GPIO.A4/A5 (for util/iteflash) */
-	IT83XX_I2C_PORT_COUNT,
-};
-
-#define USB_VID_ITE 0x048d
-
-#define IT83XX_ESPI_BASE  0x00F03100
-
-#define IT83XX_ESPI_GCAC1      REG8(IT83XX_ESPI_BASE+0x05)
-#define IT83XX_ESPI_ESPCTRL0   REG8(IT83XX_ESPI_BASE+0x90)
-#define IT83XX_ESPI_ESGCTRL0   REG8(IT83XX_ESPI_BASE+0xA0)
-#define IT83XX_ESPI_ESGCTRL1   REG8(IT83XX_ESPI_BASE+0xA1)
-#define IT83XX_ESPI_ESGCTRL2   REG8(IT83XX_ESPI_BASE+0xA2)
-
-/* eSPI VW */
-#define IT83XX_ESPI_VW_BASE  0x00F03200
-#define IT83XX_ESPI_VWIDX(i)   REG8(IT83XX_ESPI_VW_BASE+(i))
-
-#define VW_LEVEL_FIELD(f)          ((f) << 0)
-#define VW_VALID_FIELD(f)          ((f) << 4)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2
-#define VW_IDX_2_SLP_S3            BIT(0)
-#define VW_IDX_2_SLP_S4            BIT(1)
-#define VW_IDX_2_SLP_S5            BIT(2)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3
-#define VW_IDX_3_SUS_STAT          BIT(0)
-#define VW_IDX_3_PLTRST            BIT(1)
-#define VW_IDX_3_OOB_RST_WARN      BIT(2)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4
-#define VW_IDX_4_OOB_RST_ACK       BIT(0)
-#define VW_IDX_4_WAKE              BIT(2)
-#define VW_IDX_4_PME               BIT(3)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5
-#define VW_IDX_5_SLAVE_BTLD_DONE   BIT(0)
-#define VW_IDX_5_FATAL             BIT(1)
-#define VW_IDX_5_NON_FATAL         BIT(2)
-#define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3)
-#define VW_IDX_5_BTLD_STATUS_DONE  (VW_IDX_5_SLAVE_BTLD_DONE | \
-					VW_IDX_5_SLAVE_BTLD_STATUS)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6
-#define VW_IDX_6_SCI               BIT(0)
-#define VW_IDX_6_SMI               BIT(1)
-#define VW_IDX_6_RCIN              BIT(2)
-#define VW_IDX_6_HOST_RST_ACK      BIT(3)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7
-#define VW_IDX_7_HOST_RST_WARN     BIT(0)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40
-#define VW_IDX_40_SUS_ACK           BIT(0)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41
-#define VW_IDX_41_SUS_WARN          BIT(0)
-#define VW_IDX_41_SUS_PWRDN_ACK     BIT(1)
-#define VW_IDX_41_SLP_A             BIT(3)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42
-#define VW_IDX_42_SLP_LAN           BIT(0)
-#define VW_IDX_42_SLP_WLAN          BIT(1)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43
-#define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44
-#define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47
-
-#define IT83XX_ESPI_VWCTRL0    REG8(IT83XX_ESPI_VW_BASE+0x90)
-#define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7)
-
-#define IT83XX_ESPI_VWCTRL1    REG8(IT83XX_ESPI_VW_BASE+0x91)
-#define IT83XX_ESPI_VWCTRL2    REG8(IT83XX_ESPI_VW_BASE+0x92)
-#define IT83XX_ESPI_VWCTRL3    REG8(IT83XX_ESPI_VW_BASE+0x93)
-
-/* eSPI Queue 0 */
-#define IT83XX_ESPI_QUEUE_BASE  0x00F03300
-/* PUT_PC data byte 0 - 63 */
-#define IT83XX_ESPI_QUEUE_PUT_PC(i)  REG8(IT83XX_ESPI_QUEUE_BASE+(i))
-/* PUT_OOB data byte 0 - 79 */
-#define IT83XX_ESPI_QUEUE_PUT_OOB(i) REG8(IT83XX_ESPI_QUEUE_BASE+0x80+(i))
-
-/* USB Controller */
-#define IT83XX_USB_BASE   0x00F02F00
-
-#define IT83XX_USB_P0MCR  REG8(IT83XX_USB_BASE+0xE4)
-#define USB_DP_DM_PULL_DOWN_EN BIT(4)
-
-/* Wake pin definitions, defined at board-level */
-#ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-extern const enum gpio_signal hibernate_wake_pins[];
-extern const int hibernate_wake_pins_used;
-#else
-extern enum gpio_signal hibernate_wake_pins[];
-extern int hibernate_wake_pins_used;
-#endif
-
-/* --- MISC (not implemented yet) --- */
-
-#define IT83XX_PS2_BASE   0x00F01700
-#define IT83XX_EGPIO_BASE 0x00F02100
-#define IT83XX_CIR_BASE   0x00F02300
-#define IT83XX_DBGR_BASE  0x00F02500
-#define IT83XX_OW_BASE    0x00F02A00
-#define IT83XX_CEC_BASE   0x00F02E00
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c
deleted file mode 100644
index 63f8e4247c..0000000000
--- a/chip/it83xx/spi.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI driver for Chrome EC.
- *
- * This uses FIFO mode to handle transmission and reception.
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "intc.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-
-#define SPI_RX_MAX_FIFO_SIZE 256
-#define SPI_TX_MAX_FIFO_SIZE 256
-
-#define EC_SPI_PREAMBLE_LENGTH 4
-#define EC_SPI_PAST_END_LENGTH 4
-
-/* Max data size for a version 3 request/response packet. */
-#define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE
-#define SPI_MAX_RESPONSE_SIZE (SPI_TX_MAX_FIFO_SIZE - \
-	EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
-
-static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = {
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	/* This is the byte which matters */
-	EC_SPI_FRAME_START,
-};
-
-/* Store read and write data buffer */
-static uint8_t in_msg[SPI_RX_MAX_FIFO_SIZE] __aligned(4);
-static uint8_t out_msg[SPI_TX_MAX_FIFO_SIZE] __aligned(4);
-
-/* Parameters used by host protocols */
-static struct host_packet spi_packet;
-
-enum spi_peripheral_state_machine {
-	/* Ready to receive next request */
-	SPI_STATE_READY_TO_RECV,
-	/* Receiving request */
-	SPI_STATE_RECEIVING,
-	/* Processing request */
-	SPI_STATE_PROCESSING,
-	/* Received bad data */
-	SPI_STATE_RX_BAD,
-
-	SPI_STATE_COUNT,
-} spi_peripheral_state;
-
-static const int spi_response_state[] = {
-	[SPI_STATE_READY_TO_RECV] = EC_SPI_OLD_READY,
-	[SPI_STATE_RECEIVING]     = EC_SPI_RECEIVING,
-	[SPI_STATE_PROCESSING]    = EC_SPI_PROCESSING,
-	[SPI_STATE_RX_BAD]        = EC_SPI_RX_BAD_DATA,
-};
-BUILD_ASSERT(ARRAY_SIZE(spi_response_state) == SPI_STATE_COUNT);
-
-static void spi_set_state(int state)
-{
-	/* SPI peripheral state machine */
-	spi_peripheral_state = state;
-	/* Response spi peripheral state */
-	IT83XX_SPI_SPISRDR = spi_response_state[state];
-}
-
-static void reset_rx_fifo(void)
-{
-	/* End Rx FIFO access */
-	IT83XX_SPI_TXRXFAR = 0x00;
-	/* Rx FIFO reset and count monitor reset */
-	IT83XX_SPI_FCR = IT83XX_SPI_RXFR | IT83XX_SPI_RXFCMR;
-}
-
-/* This routine handles spi received unexcepted data */
-static void spi_bad_received_data(int count)
-{
-	int i;
-
-	/* State machine mismatch, timeout, or protocol we can't handle. */
-	spi_set_state(SPI_STATE_RX_BAD);
-	/* End CPU access Rx FIFO, so it can clock in bytes from AP again. */
-	IT83XX_SPI_TXRXFAR = 0;
-
-	CPRINTS("SPI rx bad data");
-	CPRINTF("in_msg=[");
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", in_msg[i]);
-	CPRINTF("]\n");
-}
-
-static void spi_response_host_data(uint8_t *out_msg_addr, int tx_size)
-{
-	int i;
-
-	/* Tx FIFO reset and count monitor reset */
-	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
-	/* CPU Tx FIFO1 and FIFO2 access */
-	IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPUTFA;
-
-	for (i = 0; i < tx_size; i += 4)
-		/* Write response data from out_msg buffer to Tx FIFO */
-		IT83XX_SPI_CPUWTFDB0 = *(uint32_t *)(out_msg_addr + i);
-
-	/*
-	 * After writing data to Tx FIFO is finished, this bit will
-	 * be to indicate the SPI peripheral.
-	 */
-	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS;
-	/* End Tx FIFO access */
-	IT83XX_SPI_TXRXFAR = 0;
-	/* SPI peripheral read Tx FIFO */
-	IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF;
-}
-
-/*
- * Called to send a response back to the host.
- *
- * Some commands can continue for a while. This function is called by
- * host_command when it completes.
- *
- */
-static void spi_send_response_packet(struct host_packet *pkt)
-{
-	int i, tx_size;
-
-	if (spi_peripheral_state != SPI_STATE_PROCESSING) {
-		CPRINTS("The request data is not processing.");
-		return;
-	}
-
-	/* Append our past-end byte, which we reserved space for. */
-	for (i = 0; i < EC_SPI_PAST_END_LENGTH; i++)
-		((uint8_t *)pkt->response)[pkt->response_size + i]
-			= EC_SPI_PAST_END;
-
-	tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH +
-			EC_SPI_PAST_END_LENGTH;
-
-	/* Transmit the reply */
-	spi_response_host_data(out_msg, tx_size);
-}
-
-/* Store request data from Rx FIFO to in_msg buffer */
-static void spi_host_request_data(uint8_t *in_msg_addr, int count)
-{
-	int i;
-
-	/* CPU Rx FIFO1 access */
-	IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPURXF1A;
-	/*
-	 * In spi_parse_header, the request data will separate to
-	 * write in_msg buffer so we cannot set CPU to end accessing
-	 * Rx FIFO in this function. We will set IT83XX_SPI_TXRXFAR = 0
-	 * in reset_rx_fifo.
-	 */
-
-	for (i = 0; i < count; i += 4)
-		/* Get data from controller to buffer */
-		*(uint32_t *)(in_msg_addr + i) = IT83XX_SPI_RXFRDRB0;
-}
-
-/* Parse header for version of spi-protocol */
-static void spi_parse_header(void)
-{
-	struct ec_host_request *r = (struct ec_host_request *)in_msg;
-
-	/* Store request data from Rx FIFO to in_msg buffer */
-	spi_host_request_data(in_msg, sizeof(*r));
-
-	/* Protocol version 3 */
-	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
-		int pkt_size;
-
-		/* Check how big the packet should be */
-		pkt_size = host_request_expected_size(r);
-
-		if (pkt_size == 0 || pkt_size > sizeof(in_msg))
-			return spi_bad_received_data(pkt_size);
-
-		/* Store request data from Rx FIFO to in_msg buffer */
-		spi_host_request_data(in_msg + sizeof(*r),
-			pkt_size - sizeof(*r));
-
-		/* Set up parameters for host request */
-		spi_packet.send_response = spi_send_response_packet;
-		spi_packet.request = in_msg;
-		spi_packet.request_temp = NULL;
-		spi_packet.request_max = sizeof(in_msg);
-		spi_packet.request_size = pkt_size;
-
-		/* Response must start with the preamble */
-		memcpy(out_msg, out_preamble, EC_SPI_PREAMBLE_LENGTH);
-
-		spi_packet.response = out_msg + EC_SPI_PREAMBLE_LENGTH;
-		/* Reserve space for frame start and trailing past-end byte */
-		spi_packet.response_max = SPI_MAX_RESPONSE_SIZE;
-		spi_packet.response_size = 0;
-		spi_packet.driver_result = EC_RES_SUCCESS;
-
-		/* Move to processing state */
-		spi_set_state(SPI_STATE_PROCESSING);
-
-		/* Go to common-layer to handle request */
-		host_packet_receive(&spi_packet);
-	} else {
-		/* Invalid version number */
-		CPRINTS("Invalid version number");
-		return spi_bad_received_data(1);
-	}
-}
-
-void spi_event(enum gpio_signal signal)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		/* EC has started receiving the request from the AP */
-		spi_set_state(SPI_STATE_RECEIVING);
-		/* Disable idle task deep sleep bit of SPI in S0. */
-		disable_sleep(SLEEP_MASK_SPI);
-	}
-}
-
-void spi_peripheral_int_handler(void)
-{
-	if (IS_ENABLED(CONFIG_BOOTBLOCK) &&
-	    (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL) &&
-	    (IT83XX_SPI_EMMCBMR & IT83XX_SPI_EMMCABM)) {
-		spi_host_request_data(in_msg, 128);
-		/* End CPU access RX FIFO */
-		IT83XX_SPI_TXRXFAR = 0;
-		/* Write to clear interrupt status */
-		IT83XX_SPI_ISR = 0xff;
-		/*
-		 * Handle eMMC CMD0:
-		 * GO_IDLE_STATE, GO_PRE_IDLE_STATE, and BOOT_INITIATION
-		 */
-		spi_emmc_cmd0_isr((uint32_t *)in_msg);
-		return;
-	}
-
-	/*
-	 * The status of SPI end detection interrupt bit is set, it
-	 * means that host command parse has been completed and AP
-	 * has received the last byte which is EC_SPI_PAST_END from
-	 * EC responded data, then AP ended the transaction.
-	 */
-	if (IT83XX_SPI_ISR & IT83XX_SPI_ENDDETECTINT) {
-		/* Ready to receive */
-		spi_set_state(SPI_STATE_READY_TO_RECV);
-		/*
-		 * Once there is no SPI active, enable idle task deep
-		 * sleep bit of SPI in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_SPI);
-		/* CS# is deasserted, so write clear all peripheral status */
-		IT83XX_SPI_ISR = 0xff;
-	}
-	/*
-	 * The status of Rx valid length interrupt bit is set that
-	 * indicates reached target count(IT83XX_SPI_FTCB1R,
-	 * IT83XX_SPI_FTCB0R) and the length field of the host
-	 * requested data.
-	 */
-	if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) {
-		/* write clear peripheral status */
-		IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
-		/* Parse header for version of spi-protocol */
-		spi_parse_header();
-	}
-
-	/* Clear the interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_SPI_PERIPHERAL);
-}
-
-static void spi_init(void)
-{
-	/* Set FIFO data target count */
-	struct ec_host_request cmd_head;
-
-	/*
-	 * Target count means the size of host request.
-	 * And plus extra 4 bytes because the CPU accesses FIFO base on
-	 * word. If host requested data length is one byte, we need to
-	 * align the data length to 4 bytes.
-	 */
-	int target_count = sizeof(cmd_head) + 4;
-	/* Offset of data_len member of host request. */
-	int offset = (char *)&cmd_head.data_len - (char *)&cmd_head;
-
-	IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff;
-	IT83XX_SPI_FTCB0R = target_count & 0xff;
-	/*
-	 * The register setting can capture the length field of host
-	 * request.
-	 */
-	IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff;
-	IT83XX_SPI_TCCB0 = offset & 0xff;
-
-	/* Set SPI pins to alternate function */
-	gpio_config_module(MODULE_SPI, 1);
-	/*
-	 * Memory controller configuration register 3.
-	 * bit6 : SPI pin function select (0b:Enable, 1b:Mask)
-	 */
-	IT83XX_GCTRL_MCCR3 |= IT83XX_GCTRL_SPISLVPFE;
-	/* Set unused blocked byte */
-	IT83XX_SPI_HPR2 = 0x00;
-	/* Rx valid length interrupt enabled */
-	IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM;
-	/*
-	 * General control register2
-	 * bit4 : Rx FIFO2 will not be overwrited once it's full.
-	 * bit3 : Rx FIFO1 will not be overwrited once it's full.
-	 * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high.
-	 */
-	IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC
-				| IT83XX_SPI_RXFAR;
-	/*
-	 * Interrupt mask register (0b:Enable, 1b:Mask)
-	 * bit5 : Rx byte reach interrupt mask
-	 * bit2 : SPI end detection interrupt mask
-	 */
-	IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM;
-	/* Reset fifo and prepare to for next transaction */
-	reset_rx_fifo();
-	/* Ready to receive */
-	spi_set_state(SPI_STATE_READY_TO_RECV);
-	/* Interrupt status register(write one to clear) */
-	IT83XX_SPI_ISR = 0xff;
-	/* SPI peripheral enable (after settings are ready) */
-	IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN;
-	/* Enable SPI peripheral interrupt */
-	task_clear_pending_irq(IT83XX_IRQ_SPI_PERIPHERAL);
-	task_enable_irq(IT83XX_IRQ_SPI_PERIPHERAL);
-	/* Enable SPI chip select pin interrupt */
-	gpio_clear_pending_interrupt(GPIO_SPI0_CS);
-	gpio_enable_interrupt(GPIO_SPI0_CS);
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
-
-/* reset peripheral SPI module */
-static void spi_reset(void)
-{
-	/*
-	 * Reset SPI module before sysjump. New FW images (RO/RW) will
-	 * re-configure it.
-	 */
-	IT83XX_GCTRL_RSTC5 |= BIT(1);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, spi_reset, HOOK_PRIO_DEFAULT);
-
-#if defined(SECTION_IS_RO) && defined(CONFIG_BOOTBLOCK)
-/* AP has booted */
-void emmc_ap_jump_to_bl(enum gpio_signal signal)
-{
-	/* Transmission completed. Set SPI pin mux to AP communication mode */
-	IT83XX_GCTRL_PIN_MUX0 &= ~BIT(7);
-	/* Reset and re-initialize SPI module to communication mode */
-	spi_reset();
-	spi_init();
-	/* Disable interrupt of detection of AP's BOOTBLOCK_EN_L */
-	gpio_disable_interrupt(GPIO_BOOTBLOCK_EN_L);
-	enable_sleep(SLEEP_MASK_EMMC);
-
-	CPRINTS("eMMC emulation disabled. AP Jumped to BL");
-}
-#endif
-
-/* Get protocol information */
-enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = SPI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		spi_get_protocol_info,
-		EC_VER_MASK(0));
diff --git a/chip/it83xx/spi_master.c b/chip/it83xx/spi_master.c
deleted file mode 100644
index d3898deef6..0000000000
--- a/chip/it83xx/spi_master.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-enum sspi_clk_sel {
-	sspi_clk_24mhz = 0,
-	sspi_clk_12mhz,
-	sspi_clk_8mhz,
-	sspi_clk_6mhz,
-	sspi_clk_4p8mhz,
-	sspi_clk_4mhz,
-	sspi_clk_3p428mhz,
-	sspi_clk_3mhz,
-};
-
-enum sspi_ch_sel {
-	SSPI_CH_CS0 = 0,
-	SSPI_CH_CS1,
-};
-
-static void sspi_frequency(enum sspi_clk_sel freq)
-{
-	/*
-	 * bit[6:5]
-	 * Bit 6:Clock Polarity (CLPOL)
-	 * 0: SSCK is low in the idle mode.
-	 * 1: SSCK is high in the idle mode.
-	 * Bit 5:Clock Phase (CLPHS)
-	 * 0: Latch data on the first SSCK edge.
-	 * 1: Latch data on the second SSCK edge.
-	 *
-	 * bit[4:2]
-	 * 000b: 1/2 clk_sspi
-	 * 001b: 1/4 clk_sspi
-	 * 010b: 1/6 clk_sspi
-	 * 011b: 1/8 clk_sspi
-	 * 100b: 1/10 clk_sspi
-	 * 101b: 1/12 clk_sspi
-	 * 110b: 1/14 clk_sspi
-	 * 111b: 1/16 clk_sspi
-	 *
-	 * SSCK frequency is [freq] MHz and mode 3.
-	 * note, clk_sspi need equal to 48MHz above.
-	 */
-	IT83XX_SSPI_SPICTRL1 |= (0x60 | (freq << 2));
-}
-
-static void sspi_transmission_end(void)
-{
-	/* Write 1 to end the SPI transmission. */
-	IT83XX_SSPI_SPISTS = 0x20;
-
-	/* Short delay for "Transfer End Flag" */
-	IT83XX_GCTRL_WNCKR = 0;
-
-	/* Write 1 to clear this bit and terminate data transmission. */
-	IT83XX_SSPI_SPISTS = 0x02;
-}
-
-/* We assume only one SPI port in the chip, one SPI device */
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	int port = spi_device->port;
-
-	if (enable) {
-		/*
-		 * bit[5:4]
-		 * 00b: SPI channel 0 and channel 1 are disabled.
-		 * 10b: SSCK/SMOSI/SMISO/SSCE1# are enabled.
-		 * 01b: SSCK/SMOSI/SMISO/SSCE0# are enabled.
-		 * 11b: SSCK/SMOSI/SMISO/SSCE1#/SSCE0# are enabled.
-		 */
-		if (port == SSPI_CH_CS1)
-			IT83XX_GPIO_GRC1 |= 0x20;
-		else
-			IT83XX_GPIO_GRC1 |= 0x10;
-
-		gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-	} else {
-		if (port == SSPI_CH_CS1)
-			IT83XX_GPIO_GRC1 &= ~0x20;
-		else
-			IT83XX_GPIO_GRC1 &= ~0x10;
-
-		gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		const uint8_t *txdata, int txlen,
-		uint8_t *rxdata, int rxlen)
-{
-	int idx;
-	uint8_t port = spi_device->port;
-	static struct mutex spi_mutex;
-
-	mutex_lock(&spi_mutex);
-	/* bit[0]: Write cycle */
-	IT83XX_SSPI_SPICTRL2 &= ~0x04;
-	for (idx = 0x00; idx < txlen; idx++) {
-		IT83XX_SSPI_SPIDATA = txdata[idx];
-		if (port == SSPI_CH_CS1)
-			/* Write 1 to start the data transmission of CS1 */
-			IT83XX_SSPI_SPISTS |= 0x08;
-		else
-			/* Write 1 to start the data transmission of CS0 */
-			IT83XX_SSPI_SPISTS |= 0x10;
-	}
-
-	/* bit[1]: Read cycle */
-	IT83XX_SSPI_SPICTRL2 |= 0x04;
-	for (idx = 0x00; idx < rxlen; idx++) {
-		if (port == SSPI_CH_CS1)
-			/* Write 1 to start the data transmission of CS1 */
-			IT83XX_SSPI_SPISTS |= 0x08;
-		else
-			/* Write 1 to start the data transmission of CS0 */
-			IT83XX_SSPI_SPISTS |= 0x10;
-		rxdata[idx] = IT83XX_SSPI_SPIDATA;
-	}
-
-	sspi_transmission_end();
-	mutex_unlock(&spi_mutex);
-
-	return EC_SUCCESS;
-}
-
-static void sspi_init(void)
-{
-	int i;
-
-	clock_enable_peripheral(CGC_OFFSET_SSPI, 0, 0);
-	sspi_frequency(sspi_clk_8mhz);
-
-	/*
-	 * bit[5:3] Byte Width (BYTEWIDTH)
-	 * 000b: 8-bit transmission
-	 * 001b: 1-bit transmission
-	 * 010b: 2-bit transmission
-	 * 011b: 3-bit transmission
-	 * 100b: 4-bit transmission
-	 * 101b: 5-bit transmission
-	 * 110b: 6-bit transmission
-	 * 111b: 7-bit transmission
-	 *
-	 * bit[1] Blocking selection
-	 */
-	IT83XX_SSPI_SPICTRL2 |= 0x02;
-
-	for (i = 0; i < spi_devices_used; i++)
-		/* Disabling spi module */
-		spi_enable(&spi_devices[i], 0);
-}
-DECLARE_HOOK(HOOK_INIT, sspi_init, HOOK_PRIO_INIT_SPI);
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
deleted file mode 100644
index 16871e5826..0000000000
--- a/chip/it83xx/system.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : hardware specific implementation */
-
-#include "console.h"
-#include "cpu.h"
-#include "cros_version.h"
-#include "ec2i_chip.h"
-#include "flash.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "intc.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-#ifdef CONFIG_HOSTCMD_PD
-	/* Inform the PD MCU that we are going to hibernate. */
-	host_command_pd_request_hibernate();
-	/* Wait to ensure exchange with PD before hibernating. */
-	msleep(100);
-#endif
-
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* chip specific standby mode */
-	__enter_hibernate(seconds, microseconds);
-}
-
-/* Clear reset flags if it's not cleared in check_reset_cause() */
-static int delayed_clear_reset_flags;
-static void clear_reset_flags(void)
-{
-	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-			delayed_clear_reset_flags) {
-		chip_save_reset_flags(0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, clear_reset_flags, HOOK_PRIO_LAST);
-
-#if !defined(CONFIG_HOSTCMD_LPC) && !defined(CONFIG_HOSTCMD_ESPI)
-static void system_save_panic_data_to_bram(void)
-{
-	uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR;
-
-	for (int i = 0; i < CONFIG_PANIC_DATA_SIZE; i++)
-		IT83XX_BRAM_BANK0(i + BRAM_PANIC_DATA_START) = ptr[i];
-}
-
-static void system_restore_panic_data_from_bram(void)
-{
-	uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR;
-
-	for (int i = 0; i < CONFIG_PANIC_DATA_SIZE; i++)
-		ptr[i] = IT83XX_BRAM_BANK0(i + BRAM_PANIC_DATA_START);
-}
-BUILD_ASSERT(BRAM_PANIC_LEN >= CONFIG_PANIC_DATA_SIZE);
-#else
-static void system_save_panic_data_to_bram(void) {}
-static void system_restore_panic_data_from_bram(void) {}
-#endif
-
-static void system_reset_ec_by_gpg1(void)
-{
-	system_save_panic_data_to_bram();
-	/* Set GPG1 as output high and wait until EC reset. */
-	IT83XX_GPIO_CTRL(GPIO_G, 1) = GPCR_PORT_PIN_MODE_OUTPUT;
-	IT83XX_GPIO_DATA(GPIO_G) |= BIT(1);
-	while (1)
-		;
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t flags;
-	uint8_t raw_reset_cause = IT83XX_GCTRL_RSTS & 0x03;
-	uint8_t raw_reset_cause2 = IT83XX_GCTRL_SPCTRL4 & 0x07;
-
-	/* Restore saved reset flags. */
-	flags = chip_read_reset_flags();
-
-	/* Clear reset cause. */
-	IT83XX_GCTRL_RSTS |= 0x03;
-	IT83XX_GCTRL_SPCTRL4 |= 0x07;
-
-	/* Determine if watchdog reset or power on reset. */
-	if (raw_reset_cause & 0x02) {
-		flags |= EC_RESET_FLAG_WATCHDOG;
-		if (IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1)) {
-			/*
-			 * Save watchdog reset flag to BRAM so we can restore
-			 * the flag on next reboot.
-			 */
-			chip_save_reset_flags(EC_RESET_FLAG_WATCHDOG);
-			/*
-			 * Assert GPG1 to reset EC and then EC_RST_ODL will be
-			 * toggled.
-			 */
-			system_reset_ec_by_gpg1();
-		}
-	} else if (raw_reset_cause & 0x01) {
-		flags |= EC_RESET_FLAG_POWER_ON;
-	} else {
-		if ((IT83XX_GCTRL_RSTS & 0xC0) == 0x80)
-			flags |= EC_RESET_FLAG_POWER_ON;
-	}
-
-	if (raw_reset_cause2 & 0x04)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-	/* watchdog module triggers these reset */
-	if (flags & (EC_RESET_FLAG_HARD | EC_RESET_FLAG_SOFT))
-		flags &= ~EC_RESET_FLAG_WATCHDOG;
-
-	/*
-	 * On power-on of some boards, H1 releases the EC from reset but then
-	 * quickly asserts and releases the reset a second time. This means the
-	 * EC sees 2 resets. In order to carry over some important flags (e.g.
-	 * HIBERNATE) to the second resets, the reset flag will not be wiped if
-	 * we know this is the first reset.
-	 */
-	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-			(flags & EC_RESET_FLAG_POWER_ON)) {
-		if (flags & EC_RESET_FLAG_INITIAL_PWR) {
-			/* Second boot, clear the flag immediately */
-			chip_save_reset_flags(0);
-		} else {
-			/*
-			 * First boot, Keep current flags and set INITIAL_PWR
-			 * flag. EC reset should happen soon.
-			 *
-			 * It's possible that H1 never trigger EC reset, or
-			 * reset happens before this line. Both cases should be
-			 * fine because we will have the correct flag anyway.
-			 */
-			chip_save_reset_flags(chip_read_reset_flags() |
-						EC_RESET_FLAG_INITIAL_PWR);
-
-			/*
-			 * Schedule chip_save_reset_flags(0) later.
-			 * Wait until end of HOOK_INIT should be long enough.
-			 */
-			delayed_clear_reset_flags = 1;
-		}
-	} else {
-		/* Clear saved reset flags. */
-		chip_save_reset_flags(0);
-	}
-
-	system_set_reset_flags(flags);
-
-	/* Clear PD contract recorded in bram if this is a power-on reset. */
-	if (IS_ENABLED(CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM) &&
-	   (flags == (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) {
-		for (int i = 0; i < MAX_SYSTEM_BBRAM_IDX_PD_PORTS; i++)
-			system_set_bbram((SYSTEM_BBRAM_IDX_PD0 + i), 0);
-	}
-
-	if ((IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1)) &&
-		(flags & ~(EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN)))
-		system_restore_panic_data_from_bram();
-}
-
-static void system_reset_cause_is_unknown(void)
-{
-	/* No reset cause and not sysjump. */
-	if (!system_get_reset_flags() && !system_jumped_to_this_image())
-		/*
-		 * We decrease 4 or 2 for "ec_reset_lp" here, that depend on
-		 * which jump and link instruction has executed.
-		 * eg: Andes core (jral5: LP=PC+2, jal: LP=PC+4)
-		 */
-		ccprintf("===Unknown reset! jump from %x or %x===\n",
-				ec_reset_lp - 4, ec_reset_lp - 2);
-}
-DECLARE_HOOK(HOOK_INIT, system_reset_cause_is_unknown, HOOK_PRIO_FIRST);
-
-int system_is_reboot_warm(void)
-{
-	uint32_t reset_flags;
-	/*
-	 * Check reset cause here,
-	 * gpio_pre_init is executed faster than system_pre_init
-	 */
-	check_reset_cause();
-	reset_flags = system_get_reset_flags();
-
-	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-	    (reset_flags & EC_RESET_FLAG_POWER_ON) ||
-	    (reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-	    (reset_flags & EC_RESET_FLAG_HARD) ||
-	    (reset_flags & EC_RESET_FLAG_SOFT) ||
-	    (reset_flags & EC_RESET_FLAG_HIBERNATE))
-		return 0;
-	else
-		return 1;
-}
-
-void chip_pre_init(void)
-{
-	/* bit1=0: disable pre-defined command */
-	IT83XX_SMB_SFFCTL &= ~IT83XX_SMB_HSAPE;
-
-	/* bit0, EC received the special waveform from iteflash */
-	if (IT83XX_GCTRL_DBGROS & IT83XX_SMB_DBGR) {
-		/*
-		 * Wait ~200ms, so iteflash will have enough time to let
-		 * EC enter follow mode. And once EC goes into follow mode, EC
-		 * will be stayed here (no following sequences, eg:
-		 * enable watchdog/write protect/power-on sequence...) until
-		 * we reset it.
-		 */
-		for (int i = 0; i < (200 * MSEC / 15); i++)
-			/* delay ~15.25us */
-			IT83XX_GCTRL_WNCKR = 0;
-	}
-
-	if (IS_ENABLED(IT83XX_ETWD_HW_RESET_SUPPORT))
-		/* System triggers a soft reset by default (command: reboot). */
-		IT83XX_GCTRL_ETWDUARTCR &= ~ETWD_HW_RST_EN;
-
-	if (IS_ENABLED(IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED))
-		/*
-		 * bit7: wake up CPU if it is in low power mode and
-		 * an interrupt is pending.
-		 */
-		IT83XX_GCTRL_WMCR |= BIT(7);
-}
-
-#define BRAM_VALID_MAGIC        0x4252414D  /* "BRAM" */
-#define BRAM_VALID_MAGIC_FIELD0 (BRAM_VALID_MAGIC & 0xff)
-#define BRAM_VALID_MAGIC_FIELD1 ((BRAM_VALID_MAGIC >> 8) & 0xff)
-#define BRAM_VALID_MAGIC_FIELD2 ((BRAM_VALID_MAGIC >> 16) & 0xff)
-#define BRAM_VALID_MAGIC_FIELD3 ((BRAM_VALID_MAGIC >> 24) & 0xff)
-void chip_bram_valid(void)
-{
-	int i;
-
-	if ((BRAM_VALID_FLAGS0 != BRAM_VALID_MAGIC_FIELD0) ||
-	    (BRAM_VALID_FLAGS1 != BRAM_VALID_MAGIC_FIELD1) ||
-	    (BRAM_VALID_FLAGS2 != BRAM_VALID_MAGIC_FIELD2) ||
-	    (BRAM_VALID_FLAGS3 != BRAM_VALID_MAGIC_FIELD3)) {
-		/*
-		 * Magic does not match, so BRAM must be uninitialized. Clear
-		 * entire Bank0 BRAM, and set magic value.
-		 */
-		for (i = 0; i < BRAM_IDX_VALID_FLAGS0; i++)
-			IT83XX_BRAM_BANK0(i) = 0;
-
-		BRAM_VALID_FLAGS0 = BRAM_VALID_MAGIC_FIELD0;
-		BRAM_VALID_FLAGS1 = BRAM_VALID_MAGIC_FIELD1;
-		BRAM_VALID_FLAGS2 = BRAM_VALID_MAGIC_FIELD2;
-		BRAM_VALID_FLAGS3 = BRAM_VALID_MAGIC_FIELD3;
-	}
-
-#if defined(CONFIG_PRESERVE_LOGS) && defined(CONFIG_IT83XX_HARD_RESET_BY_GPG1)
-	if (BRAM_EC_LOG_STATUS == EC_LOG_SAVED_IN_FLASH) {
-		/* Restore EC logs from flash. */
-		memcpy((void *)__preserved_logs_start,
-			(const void *)CHIP_FLASH_PRESERVE_LOGS_BASE,
-			(uintptr_t)__preserved_logs_size);
-	}
-	BRAM_EC_LOG_STATUS = 0;
-#endif
-}
-
-void system_pre_init(void)
-{
-	/* No initialization required */
-
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	uint32_t flags = 0;
-	flags |= BRAM_RESET_FLAGS0 << 24;
-	flags |= BRAM_RESET_FLAGS1 << 16;
-	flags |= BRAM_RESET_FLAGS2 << 8;
-	flags |= BRAM_RESET_FLAGS3;
-	return flags;
-}
-
-void chip_save_reset_flags(uint32_t save_flags)
-{
-	BRAM_RESET_FLAGS0 = save_flags >> 24;
-	BRAM_RESET_FLAGS1 = (save_flags >> 16) & 0xff;
-	BRAM_RESET_FLAGS2 = (save_flags >> 8) & 0xff;
-	BRAM_RESET_FLAGS3 = save_flags & 0xff;
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* We never get this warning message in normal case. */
-	if (IT83XX_GCTRL_DBGROS & IT83XX_SMB_DBGR) {
-		ccprintf("!Reset will be failed due to EC is in debug mode!\n");
-		cflush();
-	}
-
-#if defined(CONFIG_PRESERVE_LOGS) && defined(CONFIG_IT83XX_HARD_RESET_BY_GPG1)
-	/* Saving EC logs into flash before reset. */
-	crec_flash_physical_erase(CHIP_FLASH_PRESERVE_LOGS_BASE,
-		CHIP_FLASH_PRESERVE_LOGS_SIZE);
-	crec_flash_physical_write(CHIP_FLASH_PRESERVE_LOGS_BASE,
-		(uintptr_t)__preserved_logs_size, __preserved_logs_start);
-	BRAM_EC_LOG_STATUS = EC_LOG_SAVED_IN_FLASH;
-#endif
-
-	/* Disable interrupts to avoid task swaps during reboot. */
-	interrupt_disable();
-
-	/* Handle saving common reset flags. */
-	system_encode_save_flags(flags, &save_flags);
-
-	if (clock_ec_wake_from_sleep())
-		save_flags |= EC_RESET_FLAG_HIBERNATE;
-
-	/* Store flags to battery backed RAM. */
-	chip_save_reset_flags(save_flags);
-
-	/* If WAIT_EXT is set, then allow 10 seconds for external reset */
-	if (flags & SYSTEM_RESET_WAIT_EXT) {
-		int i;
-
-		/* Wait 10 seconds for external reset */
-		for (i = 0; i < 1000; i++) {
-			watchdog_reload();
-			udelay(10000);
-		}
-	}
-
-	/* bit0: enable watchdog hardware reset. */
-#ifdef IT83XX_ETWD_HW_RESET_SUPPORT
-	if (flags & SYSTEM_RESET_HARD)
-		IT83XX_GCTRL_ETWDUARTCR |= ETWD_HW_RST_EN;
-#endif
-	/* Set GPG1 as output high and wait until EC reset. */
-	if (IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1))
-		system_reset_ec_by_gpg1();
-
-	/*
-	 * Writing invalid key to watchdog module triggers a soft or hardware
-	 * reset. It depends on the setting of bit0 at ETWDUARTCR register.
-	 */
-	IT83XX_ETWD_ETWCFG |= 0x20;
-	IT83XX_ETWD_EWDKEYR = 0x00;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	BRAM_SCRATCHPAD3 = (value >> 24) & 0xff;
-	BRAM_SCRATCHPAD2 = (value >> 16) & 0xff;
-	BRAM_SCRATCHPAD1 = (value >> 8) & 0xff;
-	BRAM_SCRATCHPAD0 = value & 0xff;
-
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = (BRAM_SCRATCHPAD3 << 24) | (BRAM_SCRATCHPAD2 << 16) |
-		 (BRAM_SCRATCHPAD1 << 8) | (BRAM_SCRATCHPAD0);
-	return EC_SUCCESS;
-}
-
-static uint32_t system_get_chip_id(void)
-{
-#ifdef IT83XX_CHIP_ID_3BYTES
-	return (IT83XX_GCTRL_CHIPID1 << 16) | (IT83XX_GCTRL_CHIPID2 << 8) |
-		IT83XX_GCTRL_CHIPID3;
-#else
-	return (IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2;
-#endif
-}
-
-static uint8_t system_get_chip_version(void)
-{
-	/* bit[3-0], chip version */
-	return IT83XX_GCTRL_CHIPVER & 0x0F;
-}
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "ite";
-}
-
-const char *system_get_chip_name(void)
-{
-	static char buf[8] = {'i', 't'};
-	int num = (IS_ENABLED(IT83XX_CHIP_ID_3BYTES) ? 4 : 3);
-	uint32_t chip_id = system_get_chip_id();
-
-	for (int n = 2; num >= 0; n++, num--)
-		buf[n] = to_hex(chip_id >> (num * 4) & 0xF);
-
-	return buf;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char buf[3];
-	uint8_t rev = system_get_chip_version();
-
-	buf[0] = to_hex(rev + 0xa);
-	buf[1] = 'x';
-	buf[2] = '\0';
-	return buf;
-}
-
-static int bram_idx_lookup(enum system_bbram_idx idx)
-{
-	if (idx == SYSTEM_BBRAM_IDX_PD0)
-		return BRAM_IDX_PD0;
-	if (idx == SYSTEM_BBRAM_IDX_PD1)
-		return BRAM_IDX_PD1;
-	if (idx == SYSTEM_BBRAM_IDX_PD2)
-		return BRAM_IDX_PD2;
-	return -1;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int bram_idx = bram_idx_lookup(idx);
-
-	if (bram_idx < 0)
-		return EC_ERROR_INVAL;
-
-	*value = IT83XX_BRAM_BANK0(bram_idx);
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	int bram_idx = bram_idx_lookup(idx);
-
-	if (bram_idx < 0)
-		return EC_ERROR_INVAL;
-
-	IT83XX_BRAM_BANK0(bram_idx) = value;
-	return EC_SUCCESS;
-}
-
-uintptr_t system_get_fw_reset_vector(uintptr_t base)
-{
-	/*
-	 * Because our reset vector is at the beginning of image copy
-	 * (see init.S). So I just need to return 'base' here and EC will jump
-	 * to the reset vector.
-	 */
-	return base;
-}
diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c
deleted file mode 100644
index d0b645e68c..0000000000
--- a/chip/it83xx/uart.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "intc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-/* Traces on UART1 */
-#define UART_PORT      0
-#define UART_PORT_HOST 1
-
-static int init_done;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (IT83XX_UART_IER(UART_PORT) & 0x02)
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/* Re-enable the transmit interrupt. */
-	IT83XX_UART_IER(UART_PORT) |= 0x02;
-}
-
-void uart_tx_stop(void)
-{
-	IT83XX_UART_IER(UART_PORT) &= ~0x02;
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/*
-	 * Wait for transmit FIFO empty (TEMT) and transmitter holder
-	 * register and transmitter shift registers to be empty (THRE).
-	 */
-	while ((IT83XX_UART_LSR(UART_PORT) & 0x60) != 0x60)
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/* Transmit is ready when FIFO is empty (THRE). */
-	return IT83XX_UART_LSR(UART_PORT) & 0x20;
-}
-
-int uart_tx_in_progress(void)
-{
-	/*
-	 * Transmit is in progress if transmit holding register or transmitter
-	 * shift register are not empty (TEMT).
-	 */
-	return !(IT83XX_UART_LSR(UART_PORT) & 0x40);
-}
-
-int uart_rx_available(void)
-{
-	return IT83XX_UART_LSR(UART_PORT) & 0x01;
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	IT83XX_UART_THR(UART_PORT) = c;
-}
-
-int uart_read_char(void)
-{
-	return IT83XX_UART_RBR(UART_PORT);
-}
-
-static void uart_ec_interrupt(void)
-{
-	uint8_t uart_ier;
-
-	/* clear interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_UART1);
-
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-
-	uart_ier = IT83XX_UART_IER(UART_PORT);
-	IT83XX_UART_IER(UART_PORT) = 0;
-	IT83XX_UART_IER(UART_PORT) = uart_ier;
-}
-
-static void intc_cpu_int_group_9(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_9 = intc_get_ec_int();
-
-	switch (intc_group_9) {
-	case IT83XX_IRQ_UART1:
-		uart_ec_interrupt();
-		break;
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_9, intc_cpu_int_group_9, 1);
-
-static void uart_config(void)
-{
-	/*
-	 * Specify clock source of the UART is 24MHz,
-	 * must match CLK_UART_DIV_SEL.
-	 */
-	IT83XX_UART_CSSR(UART_PORT) = 0x01;
-
-	/* 8-N-1 and DLAB set to allow access to DLL and DLM registers. */
-	IT83XX_UART_LCR(UART_PORT) = 0x83;
-
-	/* Set divisor to set baud rate to 115200 */
-	IT83XX_UART_DLM(UART_PORT) = 0x00;
-	IT83XX_UART_DLL(UART_PORT) = 0x01;
-
-	/*
-	 * Clear DLAB bit to exclude access to DLL and DLM and give access to
-	 * RBR and THR.
-	 */
-	IT83XX_UART_LCR(UART_PORT) = 0x03;
-
-	/*
-	 * Enable TX and RX FIFOs and set RX FIFO interrupt level to the
-	 * minimum 1 byte.
-	 */
-	IT83XX_UART_FCR(UART_PORT) = 0x07;
-
-	/*
-	 * set OUT2 bit to enable interrupt logic.
-	 */
-	IT83XX_UART_MCR(UART_PORT) = 0x08;
-}
-
-#ifdef CONFIG_UART_HOST
-static void host_uart_config(void)
-{
-	/*
-	 * Specify clock source of the UART is 24MHz,
-	 * must match CLK_UART_DIV_SEL.
-	 */
-	IT83XX_UART_CSSR(UART_PORT_HOST) = 0x01;
-	/* 8-N-1 and DLAB set to allow access to DLL and DLM registers. */
-	IT83XX_UART_LCR(UART_PORT_HOST) = 0x83;
-	/* Set divisor to set baud rate to 115200 */
-	IT83XX_UART_DLM(UART_PORT_HOST) = 0x00;
-	IT83XX_UART_DLL(UART_PORT_HOST) = 0x01;
-	/*
-	 * Clear DLAB bit to exclude access to DLL and DLM and give access to
-	 * RBR and THR.
-	 */
-	IT83XX_UART_LCR(UART_PORT_HOST) = 0x03;
-	/*
-	 * Enable TX and RX FIFOs and set RX FIFO interrupt level to the
-	 * minimum 1 byte.
-	 */
-	IT83XX_UART_FCR(UART_PORT_HOST) = 0x07;
-}
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	gpio_clear_pending_interrupt(GPIO_UART1_RX);
-	gpio_enable_interrupt(GPIO_UART1_RX);
-}
-
-void uart_exit_dsleep(void)
-{
-	gpio_disable_interrupt(GPIO_UART1_RX);
-	gpio_clear_pending_interrupt(GPIO_UART1_RX);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	clock_refresh_console_in_use();
-	/* Disable interrupts on UART1 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART1_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-void uart_init(void)
-{
-	/*
-	 * bit3: uart1 belongs to the EC side.
-	 * This is necessary for enabling eSPI module.
-	 */
-	IT83XX_GCTRL_RSTDMMC |= BIT(3);
-
-	/* reset uart before config it */
-	IT83XX_GCTRL_RSTC4 |= BIT(1);
-
-	/* Waiting for when we can use the GPIO module to set pin muxing */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* switch UART1 on without hardware flow control */
-	IT83XX_GPIO_GRC1 |= 0x01;
-	IT83XX_GPIO_GRC6 |= 0x03;
-
-	/* Enable clocks to UART 1 and 2. */
-	clock_enable_peripheral(CGC_OFFSET_UART, 0, 0);
-
-	/* Config UART 1 */
-	uart_config();
-
-#ifdef CONFIG_UART_HOST
-	/* bit2, reset UART2 */
-	IT83XX_GCTRL_RSTC4 |= BIT(2);
-	/* SIN1/SOUT1 of UART 2 is enabled. */
-	IT83XX_GPIO_GRC1 |= BIT(2);
-	/* Config UART 2 */
-	host_uart_config();
-#endif
-
-	/* clear interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_UART1);
-
-	/* Enable interrupts */
-	IT83XX_UART_IER(UART_PORT) = 0x03;
-	task_enable_irq(IT83XX_IRQ_UART1);
-
-	init_done = 1;
-}
diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c
deleted file mode 100644
index f0e200c4ac..0000000000
--- a/chip/it83xx/watchdog.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer_chip.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "watchdog.h"
-
-/* Enter critical period or not. */
-static int wdt_warning_fired;
-
-/*
- * We use WDT_EXT_TIMER to trigger an interrupt just before the watchdog timer
- * will fire so that we can capture important state information before
- * being reset.
- */
-
-/* Magic value to tickle the watchdog register. */
-#define ITE83XX_WATCHDOG_MAGIC_WORD  0x5C
-/* Start to print warning message. */
-#define ITE83XX_WATCHDOG_WARNING_MS  CONFIG_AUX_TIMER_PERIOD_MS
-/* The interval to print warning message at critical period. */
-#define ITE83XX_WATCHDOG_CRITICAL_MS 30
-
-/* set warning timer */
-static void watchdog_set_warning_timer(int32_t ms, int init)
-{
-	ext_timer_ms(WDT_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 1, ms, init, 0);
-}
-
-void watchdog_warning_irq(void)
-{
-#ifdef CONFIG_SOFTWARE_PANIC
-	struct panic_data * const pdata_ptr = get_panic_data_write();
-
-#if defined(CHIP_CORE_NDS32)
-	pdata_ptr->nds_n8.ipc = get_ipc();
-#elif defined(CHIP_CORE_RISCV)
-	pdata_ptr->riscv.mepc = get_mepc();
-#endif
-#endif
-	/* clear interrupt status */
-	task_clear_pending_irq(et_ctrl_regs[WDT_EXT_TIMER].irq);
-
-	/* Reset warning timer. */
-	IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03;
-
-#if defined(CHIP_CORE_NDS32)
-	/*
-	 * The IPC (Interruption Program Counter) is the shadow stack register
-	 * of the PC (Program Counter). It stores the return address of program
-	 * (PC->IPC) when the ISR was called.
-	 *
-	 * The LP (Link Pointer) stores the program address of the next
-	 * sequential instruction for function call return purposes.
-	 * LP = PC+4 after a jump and link instruction (jal).
-	 */
-	panic_printf("Pre-WDT warning! IPC:%08x LP:%08x TASK_ID:%d\n",
-		get_ipc(), ilp, task_get_current());
-#elif defined(CHIP_CORE_RISCV)
-	panic_printf("Pre-WDT warning! MEPC:%08x RA:%08x TASK_ID:%d\n",
-		get_mepc(), ira, task_get_current());
-#endif
-
-	if (!wdt_warning_fired++)
-		/*
-		 * Reduce interval of warning timer, so we can print more
-		 * warning messages during critical period.
-		 */
-		watchdog_set_warning_timer(ITE83XX_WATCHDOG_CRITICAL_MS, 0);
-}
-
-void watchdog_reload(void)
-{
-	/* Reset warning timer. */
-	IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03;
-
-	/* Restart (tickle) watchdog timer. */
-	IT83XX_ETWD_EWDKEYR = ITE83XX_WATCHDOG_MAGIC_WORD;
-
-	if (wdt_warning_fired) {
-		wdt_warning_fired = 0;
-		/* Reset warning timer to default if watchdog is touched. */
-		watchdog_set_warning_timer(ITE83XX_WATCHDOG_WARNING_MS, 0);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	uint16_t wdt_count = CONFIG_WATCHDOG_PERIOD_MS * 1024 / 1000;
-
-	/* Unlock access to watchdog registers. */
-	IT83XX_ETWD_ETWCFG = 0x00;
-
-	/* Set WD timer to use 1.024kHz clock. */
-	IT83XX_ETWD_ET1PSR = 0x01;
-
-	/* Set WDT key match enabled and WDT clock to use ET1PSR. */
-	IT83XX_ETWD_ETWCFG = 0x30;
-
-#ifdef CONFIG_HIBERNATE
-	/* bit4: watchdog can be stopped. */
-	IT83XX_ETWD_ETWCTRL |= BIT(4);
-#else
-	/* Specify that watchdog cannot be stopped. */
-	IT83XX_ETWD_ETWCTRL = 0x00;
-#endif
-
-	/* Start WDT_EXT_TIMER (CONFIG_AUX_TIMER_PERIOD_MS ms). */
-	watchdog_set_warning_timer(ITE83XX_WATCHDOG_WARNING_MS, 1);
-
-	/* Start timer 1 (must be started for watchdog timer to run). */
-	IT83XX_ETWD_ET1CNTLLR = 0x00;
-
-	/*
-	 * Set watchdog timer to CONFIG_WATCHDOG_PERIOD_MS ms.
-	 * Writing CNTLL starts timer.
-	 */
-	IT83XX_ETWD_EWDCNTLHR = (wdt_count >> 8) & 0xff;
-	IT83XX_ETWD_EWDCNTLLR = wdt_count & 0xff;
-
-	/* Lock access to watchdog registers. */
-	IT83XX_ETWD_ETWCFG = 0x3f;
-
-	return EC_SUCCESS;
-}
diff --git a/chip/lm4/adc.c b/chip/lm4/adc.c
deleted file mode 100644
index 13b5ebdebd..0000000000
--- a/chip/lm4/adc.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4-specific ADC module for Chrome EC */
-
-#include "adc.h"
-#include "atomic.h"
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Maximum time we allow for an ADC conversion */
-#define ADC_TIMEOUT_US SECOND
-
-static volatile task_id_t task_waiting_on_ss[LM4_ADC_SEQ_COUNT];
-
-static void configure_gpio(void)
-{
-	int i, port, mask;
-
-	/* Use analog function for AIN */
-	for (i = 0; i < ADC_CH_COUNT; ++i) {
-		if (adc_channels[i].gpio_mask) {
-			mask = adc_channels[i].gpio_mask;
-			port = adc_channels[i].gpio_port;
-			LM4_GPIO_DEN(port) &= ~mask;
-			LM4_GPIO_AMSEL(port) |= mask;
-		}
-	}
-}
-
-/**
- * Flush an ADC sequencer and initiate a read.
- *
- * @param seq		Sequencer to read
- * @return Raw ADC value.
- */
-static int flush_and_read(enum lm4_adc_sequencer seq)
-{
-	/*
-	 * This is currently simple because we can dedicate a sequencer to each
-	 * ADC channel.  If we have enough channels that's no longer possible,
-	 * this code will need to become more complex.  For example, we could:
-	 *
-	 * 1) Read them all using a timer interrupt, and then return the most
-	 * recent value?  This is lowest-latency for the caller, but won't
-	 * return accurate data if read frequently.
-	 *
-	 * 2) Reserve SS3 for reading a single value, and configure it on each
-	 * read?  Needs mutex if we could have multiple callers; doesn't matter
-	 * if just used for debugging.
-	 *
-	 * 3) Both?
-	 */
-	volatile uint32_t scratch  __attribute__((unused));
-	int event;
-
-	/* Empty the FIFO of any previous results */
-	while (!(LM4_ADC_SSFSTAT(seq) & 0x100))
-		scratch = LM4_ADC_SSFIFO(seq);
-
-	/*
-	 * This assumes we don't have multiple tasks accessing the same
-	 * sequencer. Add mutex lock if needed.
-	 */
-	task_waiting_on_ss[seq] = task_get_current();
-
-	/* Clear the interrupt status */
-	LM4_ADC_ADCISC |= 0x01 << seq;
-
-	/* Enable interrupt */
-	LM4_ADC_ADCIM |= 0x01 << seq;
-
-	/* Initiate sample sequence */
-	LM4_ADC_ADCPSSI |= 0x01 << seq;
-
-	/* Wait for interrupt */
-	event = task_wait_event_mask(TASK_EVENT_ADC_DONE, ADC_TIMEOUT_US);
-
-	/* Disable interrupt */
-	LM4_ADC_ADCIM &= ~(0x01 << seq);
-
-	task_waiting_on_ss[seq] = TASK_ID_INVALID;
-
-	if (!(event & TASK_EVENT_ADC_DONE))
-		return ADC_READ_ERROR;
-
-	/* Read the FIFO and convert to temperature */
-	return LM4_ADC_SSFIFO(seq);
-}
-
-/**
- * Configure an ADC sequencer to be dedicated for an ADC input.
- *
- * @param seq		Sequencer to configure
- * @param ain_id	ADC input to use
- * @param ssctl		Value for sampler sequencer control register
- *
- */
-static void adc_configure(const struct adc_t *adc)
-{
-	const enum lm4_adc_sequencer seq = adc->sequencer;
-
-	/* Configure sample sequencer */
-	LM4_ADC_ADCACTSS &= ~(0x01 << seq);
-
-	/* Trigger sequencer by processor request */
-	LM4_ADC_ADCEMUX = (LM4_ADC_ADCEMUX & ~(0xf << (seq * 4))) | 0x00;
-
-	/* Sample internal temp sensor */
-	if (adc->channel == LM4_AIN_NONE) {
-		LM4_ADC_SSMUX(seq) = 0x00;
-		LM4_ADC_SSEMUX(seq) = 0x00;
-	} else {
-		LM4_ADC_SSMUX(seq) = adc->channel & 0xf;
-		LM4_ADC_SSEMUX(seq) = adc->channel >> 4;
-	}
-	LM4_ADC_SSCTL(seq) = adc->flag;
-
-	/* Enable sample sequencer */
-	LM4_ADC_ADCACTSS |= 0x01 << seq;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	static uint32_t ch_busy_mask;
-	static struct mutex adc_clock;
-	int rv;
-
-	/*
-	 * TODO(crbug.com/314121): Generalize ADC reads such that any task can
-	 * trigger a read of any channel.
-	 */
-
-	/*
-	 * Enable ADC clock and set a bit in ch_busy_mask to signify that this
-	 * channel is busy. Note, this function may be called from multiple
-	 * tasks, but each channel may be read by only one task. If assert
-	 * fails, then it means multiple tasks are trying to read same channel.
-	 */
-	mutex_lock(&adc_clock);
-	ASSERT(!(ch_busy_mask & (1UL << ch)));
-	clock_enable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	ch_busy_mask |= (1UL << ch);
-	mutex_unlock(&adc_clock);
-
-	rv = flush_and_read(adc->sequencer);
-
-	/*
-	 * If no ADC channels are busy, then disable ADC clock to conserve
-	 * power.
-	 */
-	mutex_lock(&adc_clock);
-	ch_busy_mask &= ~(1UL << ch);
-	if (!ch_busy_mask)
-		clock_disable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	mutex_unlock(&adc_clock);
-
-	if (rv == ADC_READ_ERROR)
-		return ADC_READ_ERROR;
-
-	return rv * adc->factor_mul / adc->factor_div + adc->shift;
-}
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle an interrupt on the specified sample sequencer.
- */
-static void handle_interrupt(int ss)
-{
-	int id = task_waiting_on_ss[ss];
-
-	/* Clear the interrupt status */
-	LM4_ADC_ADCISC = (0x1 << ss);
-
-	/* Wake up the task which was waiting on the interrupt, if any */
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_ADC_DONE);
-}
-
-void ss0_interrupt(void) { handle_interrupt(0); }
-void ss1_interrupt(void) { handle_interrupt(1); }
-void ss2_interrupt(void) { handle_interrupt(2); }
-void ss3_interrupt(void) { handle_interrupt(3); }
-
-DECLARE_IRQ(LM4_IRQ_ADC0_SS0, ss0_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_ADC0_SS1, ss1_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_ADC0_SS2, ss2_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_ADC0_SS3, ss3_interrupt, 2);
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_ECTEMP
-static int command_ectemp(int argc, char **argv)
-{
-	int t = adc_read_channel(ADC_CH_EC_TEMP);
-	ccprintf("EC temperature is %d K = %d C\n", t, K_TO_C(t));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ectemp, command_ectemp,
-			NULL,
-			"Print EC temperature");
-#endif
-
-/*****************************************************************************/
-/* Initialization */
-
-static void adc_init(void)
-{
-	int i;
-
-	/* Configure GPIOs */
-	configure_gpio();
-
-	/*
-	 * Temporarily enable the PLL when turning on the clock to the ADC
-	 * module, to work around chip errata (10.4).  No need to notify
-	 * other modules; the PLL isn't enabled long enough to matter.
-	 */
-	clock_enable_pll(1, 0);
-
-	/* Enable ADC0 module in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/*
-	 * Use external voltage references (VREFA+, VREFA-) instead of
-	 * VDDA and GNDA.
-	 */
-	LM4_ADC_ADCCTL = 0x01;
-
-	/* Use internal oscillator */
-	LM4_ADC_ADCCC = 0x1;
-
-	/* Disable the PLL now that the ADC is using the internal oscillator */
-	clock_enable_pll(0, 0);
-
-	/* No tasks waiting yet */
-	for (i = 0; i < LM4_ADC_SEQ_COUNT; i++)
-		task_waiting_on_ss[i] = TASK_ID_INVALID;
-
-	/* Enable IRQs */
-	task_enable_irq(LM4_IRQ_ADC0_SS0);
-	task_enable_irq(LM4_IRQ_ADC0_SS1);
-	task_enable_irq(LM4_IRQ_ADC0_SS2);
-	task_enable_irq(LM4_IRQ_ADC0_SS3);
-
-	/* 2**6 = 64x oversampling */
-	LM4_ADC_ADCSAC = 6;
-
-	/* Initialize ADC sequencer */
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		adc_configure(adc_channels + i);
-
-	/* Disable ADC0 module until it is needed to conserve power. */
-	clock_disable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/lm4/adc_chip.h b/chip/lm4/adc_chip.h
deleted file mode 100644
index a402c845a1..0000000000
--- a/chip/lm4/adc_chip.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-#include <stdint.h>
-
-enum lm4_adc_sequencer {
-	LM4_ADC_SEQ0 = 0,
-	LM4_ADC_SEQ1,
-	LM4_ADC_SEQ2,
-	LM4_ADC_SEQ3,
-	LM4_ADC_SEQ_COUNT
-};
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	enum lm4_adc_sequencer sequencer;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-	int flag;
-	uint32_t gpio_port;
-	uint8_t gpio_mask;
-};
-
-/* Minimum and maximum values returned by raw ADC read. */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 4095
-
-/* Just plain id mapping for code readability */
-#define LM4_AIN(x) (x)
-
-/* Mock value for "channel" in adc_t if we don't have an external channel. */
-#define LM4_AIN_NONE (-1)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/lm4/build.mk b/chip/lm4/build.mk
deleted file mode 100644
index 26419d3a04..0000000000
--- a/chip/lm4/build.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# LM4 chip specific files build
-#
-
-# LM4 SoC has a Cortex-M4F ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# Required chip modules
-chip-y=clock.o gpio.o hwtimer.o system.o uart.o
-
-# Optional chip modules
-chip-$(CONFIG_ADC)+=adc.o chip_temp_sensor.o
-chip-$(CONFIG_EEPROM)+=eeprom.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o
-chip-$(CONFIG_PECI)+=peci.o
-# pwm functions are implemented with the fan functions
-chip-$(CONFIG_PWM)+=pwm.o fan.o
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
diff --git a/chip/lm4/chip_temp_sensor.c b/chip/lm4/chip_temp_sensor.c
deleted file mode 100644
index 93b66f5f3f..0000000000
--- a/chip/lm4/chip_temp_sensor.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Temperature sensor module for Chrome EC */
-
-#include "adc.h"
-#include "common.h"
-#include "hooks.h"
-
-/* Initialize temperature reading to a valid value (27 C) */
-static int last_val = C_TO_K(27);
-
-static void chip_temp_sensor_poll(void)
-{
-	last_val = adc_read_channel(ADC_CH_EC_TEMP);
-}
-DECLARE_HOOK(HOOK_SECOND, chip_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-int chip_temp_sensor_get_val(int idx, int *temp_ptr)
-{
-	if (last_val == ADC_READ_ERROR)
-		return EC_ERROR_UNKNOWN;
-
-	*temp_ptr = last_val;
-
-	return EC_SUCCESS;
-}
diff --git a/chip/lm4/clock.c b/chip/lm4/clock.c
deleted file mode 100644
index 39800c9034..0000000000
--- a/chip/lm4/clock.c
+++ /dev/null
@@ -1,754 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#define PLL_CLOCK 66666667  /* System clock = 200MHz PLL/3 = 66.667MHz */
-
-#ifdef CONFIG_LOW_POWER_USE_LFIOSC
-/*
- * Length of time for the processor to wake up from deep sleep. Actual
- * measurement gives anywhere up to 780us, depending on the mode it is coming
- * out of. The datasheet gives a maximum of 846us, for coming out of deep
- * sleep in our worst case deep sleep mode.
- */
-#define DEEP_SLEEP_RECOVER_TIME_USEC 850
-#else
-/*
- * Length of time for the processor to wake up from deep sleep. Datasheet
- * maximum is 145us, but in practice have seen as much as 336us.
- */
-#define DEEP_SLEEP_RECOVER_TIME_USEC 400
-#endif
-
-/* Low power idle statistics */
-#ifdef CONFIG_LOW_POWER_IDLE
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the low speed clock is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-
-static int console_in_use_timeout_sec = 60;
-static timestamp_t console_expire_time;
-#endif
-
-static int freq;
-
-/**
- * Disable the PLL; run off internal oscillator.
- */
-static void disable_pll(void)
-{
-	/* Switch to 16MHz internal oscillator and power down the PLL */
-	LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(0) |
-		LM4_SYSTEM_RCC_BYPASS |
-		LM4_SYSTEM_RCC_PWRDN |
-		LM4_SYSTEM_RCC_OSCSRC(1) |
-		LM4_SYSTEM_RCC_MOSCDIS;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * If using the low power idle, then set the ACG bit, which specifies
-	 * that the sleep and deep sleep modes are using their own clock gating
-	 * registers SCGC and DCGS respectively instead of using the run mode
-	 * clock gating registers RCGC.
-	 */
-	LM4_SYSTEM_RCC |= LM4_SYSTEM_RCC_ACG;
-#endif
-
-	LM4_SYSTEM_RCC2 &= ~LM4_SYSTEM_RCC2_USERCC2;
-
-	freq = INTERNAL_CLOCK;
-}
-
-/**
- * Enable the PLL to run at full clock speed.
- */
-static void enable_pll(void)
-{
-	/* Disable the PLL so we can reconfigure it */
-	disable_pll();
-
-	/*
-	 * Enable the PLL (PWRDN is no longer set) and set divider.  PLL is
-	 * still bypassed, since it hasn't locked yet.
-	 */
-	LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(2) |
-		LM4_SYSTEM_RCC_USESYSDIV |
-		LM4_SYSTEM_RCC_BYPASS |
-		LM4_SYSTEM_RCC_OSCSRC(1) |
-		LM4_SYSTEM_RCC_MOSCDIS;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * If using the low power idle, then set the ACG bit, which specifies
-	 * that the sleep and deep sleep modes are using their own clock gating
-	 * registers SCGC and DCGS respectively instead of using the run mode
-	 * clock gating registers RCGC.
-	 */
-	LM4_SYSTEM_RCC |= LM4_SYSTEM_RCC_ACG;
-#endif
-
-	/* Wait for the PLL to lock */
-	clock_wait_cycles(1024);
-	while (!(LM4_SYSTEM_PLLSTAT & 1))
-		;
-
-	/* Remove bypass on PLL */
-	LM4_SYSTEM_RCC &= ~LM4_SYSTEM_RCC_BYPASS;
-	freq = PLL_CLOCK;
-}
-
-void clock_enable_pll(int enable, int notify)
-{
-	if (enable)
-		enable_pll();
-	else
-		disable_pll();
-
-	/* Notify modules of frequency change */
-	if (notify)
-		hook_notify(HOOK_FREQ_CHANGE);
-}
-
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-void clock_init(void)
-{
-#ifdef BOARD_BDS
-	/*
-	 * Perform an auto calibration of the internal oscillator using the
-	 * 32.768KHz hibernate clock, unless we've already done so.  This is
-	 * only necessary on A2 silicon as on BDS; A3 silicon is all
-	 * factory-trimmed.
-	 */
-	if ((LM4_SYSTEM_PIOSCSTAT & 0x300) != 0x100) {
-		/* Start calibration */
-		LM4_SYSTEM_PIOSCCAL = 0x80000000;
-		LM4_SYSTEM_PIOSCCAL = 0x80000200;
-		/* Wait for result */
-		clock_wait_cycles(16);
-		while (!(LM4_SYSTEM_PIOSCSTAT & 0x300))
-			;
-	}
-#else
-	/*
-	 * Only BDS has an external crystal; other boards don't have one, and
-	 * can disable main oscillator control to reduce power consumption.
-	 */
-	LM4_SYSTEM_MOSCCTL = 0x04;
-#endif
-
-	/* Make sure PLL is disabled */
-	disable_pll();
-}
-
-void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	if (mode & CGC_MODE_RUN)
-		*(LM4_SYSTEM_RCGC_BASE + offset) |= mask;
-
-	if (mode & CGC_MODE_SLEEP)
-		*(LM4_SYSTEM_SCGC_BASE + offset) |= mask;
-
-	if (mode & CGC_MODE_DSLEEP)
-		*(LM4_SYSTEM_DCGC_BASE + offset) |= mask;
-
-	/* Wait for clock change to take affect. */
-	clock_wait_cycles(3);
-}
-
-void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	if (mode & CGC_MODE_RUN)
-		*(LM4_SYSTEM_RCGC_BASE + offset) &= ~mask;
-
-	if (mode & CGC_MODE_SLEEP)
-		*(LM4_SYSTEM_SCGC_BASE + offset) &= ~mask;
-
-	if (mode & CGC_MODE_DSLEEP)
-		*(LM4_SYSTEM_DCGC_BASE + offset) &= ~mask;
-}
-
-/*
- * The low power idle task does not support using the EEPROM,
- * because it is dangerous to go to deep sleep while EEPROM
- * transaction is in progress. To fix, LM4_EEPROM_EEDONE, should
- * be checked before going in to deep sleep.
- */
-#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_EEPROM)
-#error "Low power idle mode does not support use of EEPROM"
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-
-void clock_refresh_console_in_use(void)
-{
-	disable_sleep(SLEEP_MASK_CONSOLE);
-
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-
-}
-
-/* Low power idle task.  Executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	timestamp_t t0, t1, rtc_t0, rtc_t1;
-	int next_delay = 0;
-	int time_for_dsleep, margin_us;
-	int use_low_speed_clock;
-
-	/* Enable the hibernate IRQ used to wake up from deep sleep */
-	system_enable_hib_interrupt();
-
-	/* Set SRAM and flash power management to 'low power' in deep sleep. */
-	LM4_SYSTEM_DSLPPWRCFG = 0x23;
-
-	/* Enable JTAG interrupt which will notify us when JTAG is in use. */
-	gpio_enable_interrupt(GPIO_JTAG_TCK);
-
-	/*
-	 * Initialize console in use to true and specify the console expire
-	 * time in order to give a fixed window on boot in which the low speed
-	 * clock will not be used in idle.
-	 */
-	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	CPRINTS("low power idle task started");
-
-	while (1) {
-		/*
-		 * Disable interrupts before going to deep sleep in order to
-		 * calculate the appropriate time to wake up. Note: the wfi
-		 * instruction waits until an interrupt is pending, so it
-		 * will still wake up even with interrupts disabled.
-		 */
-		interrupt_disable();
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		/* Do we have enough time before next event to deep sleep. */
-		time_for_dsleep = next_delay > (DEEP_SLEEP_RECOVER_TIME_USEC +
-						HIB_SET_RTC_MATCH_DELAY_USEC);
-
-		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-			/* Deep-sleep in STOP mode. */
-			idle_dsleep_cnt++;
-
-			/* Check if the console use has expired. */
-			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-					t0.val > console_expire_time.val) {
-				/* Enable low speed deep sleep. */
-				enable_sleep(SLEEP_MASK_CONSOLE);
-
-				/*
-				 * Wait one clock before checking if low speed
-				 * deep sleep is allowed to give time for
-				 * sleep mask to update.
-				 */
-				clock_wait_cycles(1);
-
-				if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
-					CPRINTS("Disabling console in "
-						"deep sleep");
-			}
-
-			/*
-			 * Determine if we should use a lower clock speed or
-			 * keep the same (16MHz) clock in deep sleep. Use the
-			 * lower speed only if the sleep mask specifies that low
-			 * speed sleep is allowed, the console UART TX is not
-			 * busy, and the console UART buffer is empty.
-			 */
-			use_low_speed_clock = LOW_SPEED_DEEP_SLEEP_ALLOWED &&
-				!uart_tx_in_progress() && uart_buffer_empty();
-
-#ifdef CONFIG_LOW_POWER_USE_LFIOSC
-			/* Set the deep sleep clock register. Use either the
-			 *  normal PIOSC (16MHz) or the LFIOSC (32kHz). */
-			LM4_SYSTEM_DSLPCLKCFG = use_low_speed_clock ?
-					0x32 : 0x10;
-#else
-			/*
-			 * Set the deep sleep clock register. Use either the
-			 * PIOSC with no divider (16MHz) or the PIOSC with
-			 * a /64 divider (250kHz).
-			 */
-			LM4_SYSTEM_DSLPCLKCFG = use_low_speed_clock ?
-					0x1f800010 : 0x10;
-#endif
-
-			/*
-			 * If using low speed clock, disable console.
-			 * This will also convert the console RX pin to a GPIO
-			 * and set an edge interrupt to wake us from deep sleep
-			 * if any action occurs on console.
-			 */
-			if (use_low_speed_clock)
-				uart_enter_dsleep();
-
-			/* Set deep sleep bit. */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			/* Record real time before sleeping. */
-			rtc_t0 = system_get_rtc();
-
-			/*
-			 * Set RTC interrupt in time to wake up before
-			 * next event.
-			 */
-			system_set_rtc_alarm(0, next_delay -
-						DEEP_SLEEP_RECOVER_TIME_USEC);
-
-			/* Wait for interrupt: goes into deep sleep. */
-			asm("wfi");
-
-			/* Clear deep sleep bit. */
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			/* Disable and clear RTC interrupt. */
-			system_reset_rtc_alarm();
-
-			/* Fast forward timer according to RTC counter. */
-			rtc_t1 = system_get_rtc();
-			t1.val = t0.val + (rtc_t1.val - rtc_t0.val);
-			force_time(t1);
-
-			/* If using low speed clock, re-enable the console. */
-			if (use_low_speed_clock)
-				uart_exit_dsleep();
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += (rtc_t1.val - rtc_t0.val);
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - (int)(rtc_t1.val - rtc_t0.val);
-			if (margin_us < 0)
-				CPRINTS("overslept by %dus", -margin_us);
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* Normal idle : only CPU clock stopped. */
-			asm("wfi");
-		}
-		interrupt_enable();
-	}
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_SLEEP
-/**
- * Measure baseline for power consumption.
- *
- * Levels :
- *   0 : CPU running in tight loop
- *   1 : CPU running in tight loop but peripherals gated
- *   2 : CPU in sleep mode
- *   3 : CPU in sleep mode and peripherals gated
- *   4 : CPU in deep sleep mode
- *   5 : CPU in deep sleep mode and peripherals gated
- *
- * Clocks :
- *   0 : No change
- *   1 : 16MHz
- *   2 : 1 MHz
- *   3 : 30kHz
- *
- * SRAM Power Management:
- *   0 : Active
- *   1 : Standby
- *   3 : Low Power
- *
- * Flash Power Management:
- *   0 : Active
- *   2 : Low Power
- */
-static int command_sleep(int argc, char **argv)
-{
-	int level = 0;
-	int clock = 0;
-	int sram_pm = 0;
-	int flash_pm = 0;
-	uint32_t uartibrd = 0;
-	uint32_t uartfbrd = 0;
-
-	if (argc >= 2)
-		level = strtoi(argv[1], NULL, 10);
-	if (argc >= 3)
-		clock = strtoi(argv[2], NULL, 10);
-	if (argc >= 4)
-		sram_pm = strtoi(argv[3], NULL, 10);
-	if (argc >= 5)
-		flash_pm = strtoi(argv[4], NULL, 10);
-
-#ifdef BOARD_BDS
-	/* Remove LED current sink. */
-	gpio_set_level(GPIO_DEBUG_LED, 0);
-#endif
-
-	ccprintf("Sleep : level %d, clock %d, sram pm %d, flash_pm %d...\n",
-			level, clock, sram_pm, flash_pm);
-	cflush();
-
-	/* Set clock speed. */
-	if (clock) {
-		/* Use ROM code function to set the clock */
-		void **func_table = (void **)*(uint32_t *)0x01000044;
-		void (*rom_clock_set)(uint32_t rcc) = func_table[23];
-
-		/* Disable interrupts. */
-		asm volatile("cpsid i");
-
-		switch (clock) {
-		case 1: /* 16MHz IOSC */
-			uartibrd = 17;
-			uartfbrd = 23;
-			rom_clock_set(0x00000d51);
-			break;
-		case 2: /* 1MHz IOSC */
-			uartibrd = 1;
-			uartfbrd = 5;
-			rom_clock_set(0x07C00d51);
-			break;
-		case 3: /* 30 kHz */
-			uartibrd = 0;
-			uartfbrd = 0;
-			rom_clock_set(0x00000d71);
-			break;
-		}
-
-		/*
-		 * TODO(crosbug.com/p/23795): move this to the UART module;
-		 * ugly to have UARTisms here.  Also note this only fixes
-		 * UART0, not UART1.  Should just be able to trigger
-		 * HOOK_FREQ_CHANGE and have that take care of it.
-		 */
-		if (uartfbrd) {
-			/* Disable the port via UARTCTL and add HSE. */
-			LM4_UART_CTL(0) = 0x0320;
-			/* Set the baud rate divisor. */
-			LM4_UART_IBRD(0) = uartibrd;
-			LM4_UART_FBRD(0) = uartfbrd;
-			/* Poke UARTLCRH to make the new divisor take effect. */
-			LM4_UART_LCRH(0) = LM4_UART_LCRH(0);
-			/* Enable the port. */
-			LM4_UART_CTL(0) |= 0x0001;
-		}
-		asm volatile("cpsie i");
-	}
-
-	if (uartfbrd) {
-		ccprintf("We are still alive. RCC=%08x\n", LM4_SYSTEM_RCC);
-		cflush();
-	}
-
-	/* Enable interrupts. */
-	asm volatile("cpsid i");
-
-	/* gate peripheral clocks */
-	if (level & 1) {
-		clock_disable_peripheral(CGC_OFFSET_WD,     0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_TIMER,  0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_GPIO,   0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_DMA,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_HIB,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_UART,   0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_SSI,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_I2C,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_ADC,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_LPC,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_PECI,   0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_FAN,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_EEPROM, 0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_WTIMER, 0xffffffff,
-				CGC_MODE_ALL);
-	}
-
-	/* Set deep sleep bit. */
-	if (level >= 4)
-		CPU_SCB_SYSCTRL |= 0x4;
-
-	/* Set SRAM and flash PM for sleep and deep sleep. */
-	LM4_SYSTEM_SLPPWRCFG = (flash_pm << 4) | sram_pm;
-	LM4_SYSTEM_DSLPPWRCFG = (flash_pm << 4) | sram_pm;
-
-	/* Go to low power mode (forever ...) */
-	if (level > 1)
-		while (1) {
-			asm("wfi");
-			watchdog_reload();
-		}
-	else
-		while (1)
-			watchdog_reload();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(sleep, command_sleep,
-			"[level [clock] [sram pm] [flash pm]]",
-			"Drop into sleep");
-#endif /* CONFIG_CMD_SLEEP */
-
-#ifdef CONFIG_CMD_PLL
-
-static int command_pll(int argc, char **argv)
-{
-	int v;
-
-	/* Toggle the PLL */
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			clock_enable_pll(v, 1);
-		} else {
-			/* Disable PLL and set extra divider */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(v - 1) |
-				LM4_SYSTEM_RCC_BYPASS |
-				LM4_SYSTEM_RCC_PWRDN |
-				LM4_SYSTEM_RCC_OSCSRC(1) |
-				LM4_SYSTEM_RCC_MOSCDIS;
-
-			freq = INTERNAL_CLOCK / v;
-
-			/* Notify modules of frequency change */
-			hook_notify(HOOK_FREQ_CHANGE);
-		}
-	}
-
-	/* Print current PLL state */
-	ccprintf("RCC:     0x%08x\n", LM4_SYSTEM_RCC);
-	ccprintf("RCC2:    0x%08x\n", LM4_SYSTEM_RCC2);
-	ccprintf("PLLSTAT: 0x%08x\n", LM4_SYSTEM_PLLSTAT);
-	ccprintf("Clock:   %d Hz\n", clock_get_freq());
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pll, command_pll,
-			"[ on | off | <div> ]",
-			"Get/set PLL state");
-
-#endif /* CONFIG_CMD_PLL */
-
-#ifdef CONFIG_CMD_CLOCKGATES
-/**
- * Print all clock gating registers
- */
-static int command_clock_gating(int argc, char **argv)
-{
-	ccprintf("         Run       , Sleep     , Deep Sleep\n");
-
-	ccprintf("WD:      0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_WD));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_WD));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_WD));
-
-	ccprintf("TIMER:   0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_TIMER));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_TIMER));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_TIMER));
-
-	ccprintf("GPIO:    0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_GPIO));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_GPIO));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_GPIO));
-
-	ccprintf("DMA:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_DMA));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_DMA));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_DMA));
-
-	ccprintf("HIB:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_HIB));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_HIB));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_HIB));
-
-	ccprintf("UART:    0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_UART));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_UART));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_UART));
-
-	ccprintf("SSI:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_SSI));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_SSI));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_SSI));
-
-	ccprintf("I2C:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_I2C));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_I2C));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_I2C));
-
-	ccprintf("ADC:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_ADC));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_ADC));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_ADC));
-
-	ccprintf("LPC:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_LPC));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_LPC));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_LPC));
-
-	ccprintf("PECI:    0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_PECI));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_PECI));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_PECI));
-
-	ccprintf("FAN:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_FAN));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_FAN));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_FAN));
-
-	ccprintf("EEPROM:  0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_EEPROM));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_EEPROM));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_EEPROM));
-
-	ccprintf("WTIMER:  0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_WTIMER));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_WTIMER));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_WTIMER));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(clockgates, command_clock_gating,
-			"",
-			"Get state of the clock gating controls regs");
-#endif /* CONFIG_CMD_CLOCKGATES */
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use low speed clock or
-			 * allow it to use the low speed clock.
-			 */
-			if (v)
-				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else
-				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-	ccprintf("DSLPCLKCFG register:      0x%08x\n", LM4_SYSTEM_DSLPCLKCFG);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-			"[ on | off | <timeout> sec]",
-			"Deep sleep clock settings:\nUse 'on' to force deep "
-			"sleep not to use low speed clock.\nUse 'off' to "
-			"allow deep sleep to auto-select using the low speed "
-			"clock.\n"
-			"Give a timeout value for the console in use timeout.\n"
-			"See also 'sleepmask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
-
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
deleted file mode 100644
index 4e442004c9..0000000000
--- a/chip/lm4/config_chip.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* 16.000 MHz internal oscillator frequency (PIOSC) */
-#define INTERNAL_CLOCK 16000000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 132
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 8192
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 250
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 6
-
-/*
- * Time it takes to set the RTC match register. This value is conservatively
- * set based on measurements around 200us.
- */
-#define HIB_SET_RTC_MATCH_DELAY_USEC 300
-
-/****************************************************************************/
-/* Memory mapping */
-
-#define CONFIG_RAM_BASE             0x20000000
-#define CONFIG_RAM_SIZE             0x00008000
-
-/* System stack size */
-#define CONFIG_STACK_SIZE           4096
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE        512
-#define LARGER_TASK_STACK_SIZE      768
-#define SMALLER_TASK_STACK_SIZE     384
-
-/* Default task stack size */
-#define TASK_STACK_SIZE             512
-
-#define CONFIG_PROGRAM_MEMORY_BASE  0x00000000
-#define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
-
-/* Ideal flash write size fills the 32-entry flash write buffer */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE (32 * 4)
-
-/* This is the physical size of the flash on the chip. We'll reserve one bank
- * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
- * doesn't support a write-protect pin, and if we make the write-protection
- * permanent, it can't be undone easily enough to support RMA. */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/****************************************************************************/
-/* Lock the boot configuration to prevent brickage. */
-
-/*
- * No GPIO trigger for ROM bootloader.
- * Keep JTAG debugging enabled.
- * Use 0xA442 flash write key.
- * Lock it this way.
- */
-#define CONFIG_BOOTCFG_VALUE 0x7ffffffe
-
-/****************************************************************************/
-/* Customize the build */
-
-/* Optional features present on this chip */
-#define CONFIG_ADC
-#define CONFIG_HOSTCMD_ALIGNED
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_PECI
-#define CONFIG_RTC
-#define CONFIG_SWITCH
-#define CONFIG_MPU
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/lm4/eeprom.c b/chip/lm4/eeprom.c
deleted file mode 100644
index 97fd3bdc24..0000000000
--- a/chip/lm4/eeprom.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* EEPROM module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "eeprom.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Size of EEPROM block in bytes */
-#define EEPROM_BLOCK_SIZE 64
-
-/* Count of EEPROM blocks */
-static int block_count;
-
-/*
- * Wait for the current EEPROM operation to finish; all operations but write
- * should normally finish in 4 system clocks, but worst case is up to
- * 1800ms if the EEPROM needs to do an internal page erase/copy.  We must
- * spin-wait for this delay, because EEPROM operations will fail if the chip
- * drops to sleep mode.
- */
-static int wait_for_done(void)
-{
-	int j;
-
-	for (j = 0; j < 20; j++) {  /* 20 * 100 ms = 2000 ms */
-		uint64_t tstop = get_time().val + 100 * MSEC;
-		while (get_time().val < tstop) {
-			if (!(LM4_EEPROM_EEDONE & 0x01))
-				return EC_SUCCESS;
-		}
-		watchdog_reload();
-	}
-
-	return EC_ERROR_UNKNOWN;
-}
-
-
-int eeprom_get_block_count(void)
-{
-	return block_count;
-}
-
-
-int eeprom_get_block_size(void)
-{
-	return EEPROM_BLOCK_SIZE;
-}
-
-
-int eeprom_read(int block, int offset, int size, char *data)
-{
-	uint32_t *d = (uint32_t *)data;
-	int rv;
-
-	if (block < 0 || block >= block_count ||
-	    offset < 0 || offset > EEPROM_BLOCK_SIZE || offset & 3 ||
-	    size < 0 || offset + size > EEPROM_BLOCK_SIZE || size & 3)
-		return EC_ERROR_UNKNOWN;
-
-	rv = wait_for_done();
-	if (rv)
-		return rv;
-
-	LM4_EEPROM_EEBLOCK = block;
-	if (LM4_EEPROM_EEBLOCK != block)
-		return EC_ERROR_UNKNOWN;  /* Error setting block */
-
-	LM4_EEPROM_EEOFFSET = offset >> 2;
-
-	for (; size; size -= sizeof(uint32_t))
-		*(d++) = LM4_EEPROM_EERDWRINC;
-
-	return EC_SUCCESS;
-}
-
-
-int eeprom_write(int block, int offset, int size, const char *data)
-{
-	uint32_t *d = (uint32_t *)data;
-	int rv;
-
-	if (block < 0 || block >= block_count ||
-	    offset < 0 || offset > EEPROM_BLOCK_SIZE || offset & 3 ||
-	    size < 0 || offset + size > EEPROM_BLOCK_SIZE || size & 3)
-		return EC_ERROR_UNKNOWN;
-
-	rv = wait_for_done();
-	if (rv)
-		return rv;
-
-	LM4_EEPROM_EEBLOCK = block;
-	if (LM4_EEPROM_EEBLOCK != block)
-		return EC_ERROR_UNKNOWN;  /* Error setting block */
-
-	LM4_EEPROM_EEOFFSET = offset >> 2;
-
-	/* Write 32 bits at a time; wait for each write to complete */
-	for (; size; size -= sizeof(uint32_t)) {
-		LM4_EEPROM_EERDWRINC = *(d++);
-
-		rv = wait_for_done();
-		if (rv)
-			return rv;
-
-		if (LM4_EEPROM_EEDONE & 0x10) {
-			/* Failed due to write protect */
-			return EC_ERROR_ACCESS_DENIED;
-		} else if (LM4_EEPROM_EEDONE & 0x100) {
-			/* Failed due to program voltage level */
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-
-int eeprom_hide(int block)
-{
-	/* Block 0 can't be hidden */
-	if (block <= 0 || block >= block_count)
-		return EC_ERROR_UNKNOWN;
-
-	LM4_EEPROM_EEHIDE |= 1 << block;
-	return EC_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_eeprom_info(int argc, char **argv)
-{
-	ccprintf("%d blocks @ %d bytes, hide=0x%08x\n",
-		 eeprom_get_block_count(), eeprom_get_block_size(),
-		 LM4_EEPROM_EEHIDE);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(eeinfo, command_eeprom_info,
-			NULL,
-			"Print EEPROM info");
-
-
-static int command_eeprom_read(int argc, char **argv)
-{
-	int block = 0;
-	int offset = 0;
-	char *e;
-	int rv;
-	uint32_t d;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	block = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	if (argc > 2) {
-		offset = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-	}
-
-	rv = eeprom_read(block, offset, sizeof(d), (char *)&d);
-	if (rv == EC_SUCCESS)
-		ccprintf("%d:%d = 0x%08x\n", block, offset, d);
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(eeread, command_eeprom_read,
-			"block [offset]",
-			"Read a word of EEPROM");
-
-
-static int command_eeprom_write(int argc, char **argv)
-{
-	int block = 0;
-	int offset = 0;
-	char *e;
-	uint32_t d;
-
-	if (argc < 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	block = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-	offset = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	d = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	ccprintf("Writing 0x%08x to %d:%d...\n", d, block, offset);
-	return eeprom_write(block, offset, sizeof(d), (char *)&d);
-}
-DECLARE_CONSOLE_COMMAND(eewrite, command_eeprom_write,
-			"block offset value",
-			"Write a word of EEPROM");
-
-
-#ifdef CONSOLE_COMMAND_EEHIDE
-static int command_eeprom_hide(int argc, char **argv)
-{
-	int block = 0;
-	char *e;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	block = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	ccprintf("Hiding block %d\n", block);
-	return eeprom_hide(block);
-}
-DECLARE_CONSOLE_COMMAND(eehide, command_eeprom_hide,
-			"block",
-			"Hide a block of EEPROM");
-#endif
-
-
-/*****************************************************************************/
-/* Initialization */
-
-
-int eeprom_init(void)
-{
-	/* Enable the EEPROM module in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_EEPROM, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Wait for internal EEPROM init to finish */
-	wait_for_done();
-
-	/* Store block count */
-	block_count = LM4_EEPROM_EESIZE >> 16;
-
-	/*
-	 * Handle resetting the EEPROM module to clear state from a previous
-	 * error condition.
-	 */
-	if (LM4_EEPROM_EESUPP & 0xc0) {
-		LM4_SYSTEM_SREEPROM = 1;
-		clock_wait_cycles(200);
-		LM4_SYSTEM_SREEPROM = 0;
-
-		/* Wait again for internal init to finish */
-		clock_wait_cycles(6);
-		wait_for_done();
-
-		/* Fail if error condition didn't clear */
-		if (LM4_EEPROM_EESUPP & 0xc0)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/chip/lm4/fan.c b/chip/lm4/fan.c
deleted file mode 100644
index b09323a37b..0000000000
--- a/chip/lm4/fan.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4 fan control module. */
-
-#include "clock.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "util.h"
-
-/* Maximum RPM for fan controller */
-#define MAX_RPM 0x1fff
-
-/* Maximum PWM for PWM controller */
-#define MAX_PWM 0x1ff
-
-/*
- * Scaling factor for requested/actual RPM for CPU fan.  We need this because
- * the fan controller on Blizzard filters tach pulses that are less than 64
- * 15625Hz ticks apart, which works out to ~7000rpm on an unscaled fan.  By
- * telling the controller we actually have twice as many edges per revolution,
- * the controller can handle fans that actually go twice as fast.  See
- * crosbug.com/p/7718.
- */
-#define RPM_SCALE 2
-
-
-void fan_set_enabled(int ch, int enabled)
-{
-	if (enabled)
-		LM4_FAN_FANCTL |= BIT(ch);
-	else
-		LM4_FAN_FANCTL &= ~BIT(ch);
-}
-
-int fan_get_enabled(int ch)
-{
-	return (LM4_FAN_FANCTL & BIT(ch)) ? 1 : 0;
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	int duty;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	duty = (MAX_PWM * percent + 50) / 100;
-
-	/* Always enable the channel */
-	fan_set_enabled(ch, 1);
-
-	/* Set the duty cycle */
-	LM4_FAN_FANCMD(ch) = duty << 16;
-}
-
-int fan_get_duty(int ch)
-{
-	return ((LM4_FAN_FANCMD(ch) >> 16) * 100 + MAX_PWM / 2) / MAX_PWM;
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	return (LM4_FAN_FANCH(ch) & 0x0001) ? 0 : 1;
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	int was_enabled = fan_get_enabled(ch);
-	int was_rpm = fan_get_rpm_mode(ch);
-
-	if (!was_rpm && rpm_mode) {
-		/* Enable RPM control */
-		fan_set_enabled(ch, 0);
-		LM4_FAN_FANCH(ch) &= ~0x0001;
-		fan_set_enabled(ch, was_enabled);
-	} else if (was_rpm && !rpm_mode) {
-		/* Disable RPM mode */
-		fan_set_enabled(ch, 0);
-		LM4_FAN_FANCH(ch) |= 0x0001;
-		fan_set_enabled(ch, was_enabled);
-	}
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	return (LM4_FAN_FANCST(ch) & MAX_RPM) * RPM_SCALE;
-}
-
-int fan_get_rpm_target(int ch)
-{
-	return (LM4_FAN_FANCMD(ch) & MAX_RPM) * RPM_SCALE;
-}
-
-test_mockable void fan_set_rpm_target(int ch, int rpm)
-{
-	/* Apply fan scaling */
-	if (rpm > 0)
-		rpm /= RPM_SCALE;
-
-	/* Treat out-of-range requests as requests for maximum fan speed */
-	if (rpm < 0 || rpm > MAX_RPM)
-		rpm = MAX_RPM;
-
-	LM4_FAN_FANCMD(ch) = rpm;
-}
-
-/* The LM4 status is the original definition of enum fan_status */
-enum fan_status fan_get_status(int ch)
-{
-	return (LM4_FAN_FANSTS >> (2 * ch)) & 0x03;
-}
-
-/**
- * Return non-zero if fan is enabled but stalled.
- */
-int fan_is_stalled(int ch)
-{
-	/* Must be enabled with non-zero target to stall */
-	if (!fan_get_enabled(ch) || fan_get_rpm_target(ch) == 0)
-		return 0;
-
-	/* Check for stall condition */
-	return fan_get_status(ch) == FAN_STATUS_STOPPED;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	uint32_t init;
-
-	if (flags & FAN_USE_RPM_MODE)
-		/*
-		 * Configure automatic/feedback mode:
-		 * 0x8000 = bit 15     = auto-restart
-		 * 0x0000 = bit 14     = slow acceleration
-		 * 0x0000 = bits 13:11 = no hysteresis
-		 * 0x0000 = bits 10:8  = start period (2<<0) edges
-		 * 0x0000 = bits 7:6   = no fast start
-		 * 0x0020 = bits 5:4   = average 4 edges when
-		 *                       calculating RPM
-		 * 0x000c = bits 3:2   = 8 pulses per revolution
-		 *                       (see note at top of file)
-		 * 0x0000 = bit 0      = automatic control
-		 */
-		init = 0x802c;
-	else
-		/*
-		 * Configure drive-only mode:
-		 * 0x0000 = bit 15     = no auto-restart
-		 * 0x0000 = bit 14     = slow acceleration
-		 * 0x0000 = bits 13:11 = no hysteresis
-		 * 0x0000 = bits 10:8  = start period (2<<0) edges
-		 * 0x0000 = bits 7:6   = no fast start
-		 * 0x0000 = bits 5:4   = no RPM averaging
-		 * 0x0000 = bits 3:2   = 1 pulses per revolution
-		 * 0x0001 = bit 0      = manual control
-		 */
-		init = 0x0001;
-
-	if (flags & FAN_USE_FAST_START)
-		/*
-		 * Configure fast-start mode
-		 * 0x0000 = bits 10:8  = start period (2<<0) edges
-		 * 0x0040 = bits 7:6   = fast start at 50% duty
-		 */
-		init |= 0x0040;
-
-	LM4_FAN_FANCH(ch) = init;
-}
-
-static void fan_init(void)
-{
-
-#ifdef CONFIG_FAN_DSLEEP
-	/* Enable the fan module and delay a few clocks */
-	clock_enable_peripheral(CGC_OFFSET_FAN, 0x1, CGC_MODE_ALL);
-#else
-	/* Enable the fan module and delay a few clocks */
-	clock_enable_peripheral(CGC_OFFSET_FAN, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-#endif
-	/* Disable all fans */
-	LM4_FAN_FANCTL = 0;
-}
-/* Init before PWM */
-DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN);
diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c
deleted file mode 100644
index 5b61874984..0000000000
--- a/chip/lm4/flash.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC */
-
-#include "flash.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-#define FLASH_FWB_WORDS 32
-#define FLASH_FWB_BYTES (FLASH_FWB_WORDS * 4)
-
-#define BANK_SHIFT 5 /* bank registers have 32bits each, 2^32 */
-#define BANK_MASK (BIT(BANK_SHIFT) - 1) /* 5 bits */
-#define F_BANK(b) ((b) >> BANK_SHIFT)
-#define F_BIT(b) (1 << ((b) & BANK_MASK))
-
-/* Flash timeouts.  These are 2x the spec sheet max. */
-#define ERASE_TIMEOUT_MS 200
-#define WRITE_TIMEOUT_US 300
-
-int stuck_locked;  /* Is physical flash stuck protected? */
-int all_protected; /* Has all-flash protection been requested? */
-
-/**
- * Protect flash banks until reboot.
- *
- * @param start_bank    Start bank to protect
- * @param bank_count    Number of banks to protect
- */
-static void protect_banks(int start_bank, int bank_count)
-{
-	int bank;
-	for (bank = start_bank; bank < start_bank + bank_count; bank++)
-		LM4_FLASH_FMPPE[F_BANK(bank)] &= ~F_BIT(bank);
-}
-
-/**
- * Perform a write-buffer operation.  Buffer (FWB) and address (FMA) must be
- * pre-loaded.
- *
- * @return EC_SUCCESS, or nonzero if error.
- */
-static int write_buffer(void)
-{
-	int t;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (!LM4_FLASH_FWBVAL)
-		return EC_SUCCESS;  /* Nothing to do */
-
-	/* Clear previous error status */
-	LM4_FLASH_FCMISC = LM4_FLASH_FCRIS;
-
-	/* Start write operation at page boundary */
-	LM4_FLASH_FMC2 = 0xa4420001;
-
-	/*
-	 * Reload the watchdog timer, so that writing a large amount of flash
-	 * doesn't cause a watchdog reset.
-	 */
-	watchdog_reload();
-
-	/* Wait for write to complete */
-	for (t = 0; LM4_FLASH_FMC2 & 0x01; t += 10) {
-		if (t > WRITE_TIMEOUT_US)
-			return EC_ERROR_TIMEOUT;
-		udelay(10);
-	}
-
-	/* Check for error conditions - program failed, erase needed,
-	 * voltage error. */
-	if (LM4_FLASH_FCRIS & 0x2e01)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	const uint32_t *data32 = (const uint32_t *)data;
-	int rv;
-	int i;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	/* Get initial write buffer index and page */
-	LM4_FLASH_FMA = offset & ~(FLASH_FWB_BYTES - 1);
-	i = (offset >> 2) & (FLASH_FWB_WORDS - 1);
-
-	/* Copy words into buffer */
-	for (; size > 0; size -= 4) {
-		LM4_FLASH_FWB[i++] = *data32++;
-		if (i == FLASH_FWB_WORDS) {
-			rv = write_buffer();
-			if (rv != EC_SUCCESS)
-				return rv;
-
-			/* Advance to next page */
-			i = 0;
-			LM4_FLASH_FMA += FLASH_FWB_BYTES;
-		}
-	}
-
-	/* Handle final partial page, if any */
-	if (i > 0)
-		return write_buffer();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	LM4_FLASH_FCMISC = LM4_FLASH_FCRIS;  /* Clear previous error status */
-
-	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-		     offset += CONFIG_FLASH_ERASE_SIZE) {
-		int t;
-
-		/* Do nothing if already erased */
-		if (crec_flash_is_erased(offset, CONFIG_FLASH_ERASE_SIZE))
-			continue;
-
-		LM4_FLASH_FMA = offset;
-
-		/*
-		 * Reload the watchdog timer, so that erasing many flash pages
-		 * doesn't cause a watchdog reset.  May not need this now that
-		 * we're using msleep() below.
-		 */
-		watchdog_reload();
-
-		/* Start erase */
-		LM4_FLASH_FMC = 0xa4420002;
-
-		/* Wait for erase to complete */
-		for (t = 0; LM4_FLASH_FMC & 0x02; t++) {
-			if (t > ERASE_TIMEOUT_MS)
-				return EC_ERROR_TIMEOUT;
-			msleep(1);
-		}
-
-		/* Check for error conditions - erase failed, voltage error,
-		 * protection error */
-		if (LM4_FLASH_FCRIS & 0x0a01)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_get_protect(int bank)
-{
-	return (LM4_FLASH_FMPPE[F_BANK(bank)] & F_BIT(bank)) ? 0 : 1;
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	/* Read all-protected state from our shadow copy */
-	if (all_protected)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	/* Check if blocks were stuck locked at pre-init */
-	if (stuck_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_STUCK;
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		/* Protect the entire flash */
-		all_protected = 1;
-		protect_banks(0, CONFIG_FLASH_SIZE_BYTES /
-			      CONFIG_FLASH_BANK_SIZE);
-	} else
-		/* Protect the WP region (read-only section and pstate) */
-		protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT);
-
-	return EC_SUCCESS;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-
-/*****************************************************************************/
-/* High-level APIs */
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection.  Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = crec_flash_get_protect();
-		}
-
-		/* Update all-now flag if all flash is protected */
-		if (prot_flags & EC_FLASH_PROTECT_ALL_NOW)
-			all_protected = 1;
-
-	} else {
-		/* Don't want RO flash protected */
-		unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	/* If there are no unwanted flags, done */
-	if (!(prot_flags & unwanted_prot_flags))
-		return EC_SUCCESS;
-
-	/*
-	 * If the last reboot was a power-on reset, it should have cleared
-	 * write-protect.  If it didn't, then the flash write protect registers
-	 * have been permanently committed and we can't fix that.
-	 */
-	if (reset_flags & EC_RESET_FLAG_POWER_ON) {
-		stuck_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* Otherwise, do a hard boot to clear the flash protection registers */
-	system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	/* That doesn't return, so if we're still here that's an error */
-	return EC_ERROR_UNKNOWN;
-}
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c
deleted file mode 100644
index 841bfdb214..0000000000
--- a/chip/lm4/gpio.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "switch.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* 0-terminated list of GPIO base addresses */
-static const uint32_t gpio_bases[] = {
-	LM4_GPIO_A, LM4_GPIO_B, LM4_GPIO_C, LM4_GPIO_D,
-	LM4_GPIO_E, LM4_GPIO_F, LM4_GPIO_G, LM4_GPIO_H,
-	LM4_GPIO_J, LM4_GPIO_K, LM4_GPIO_L, LM4_GPIO_M,
-	LM4_GPIO_N, LM4_GPIO_P, LM4_GPIO_Q, 0
-};
-
-/**
- * Find the index of a GPIO port base address
- *
- * This is used by the clock gating registers.
- *
- * @param port_base	Base address to find (LM4_GPIO_[A-Q])
- *
- * @return The index, or -1 if no match.
- */
-static int find_gpio_port_index(uint32_t port_base)
-{
-	int i;
-	for (i = 0; gpio_bases[i]; i++) {
-		if (gpio_bases[i] == port_base)
-			return i;
-	}
-	return -1;
-}
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int port_index = find_gpio_port_index(port);
-	int cgmask;
-
-	/* Ignore (do nothing for) invalid port values */
-	if (port_index < 0)
-		return;
-
-	/* Enable the GPIO port in run and sleep. */
-	cgmask = 1 << port_index;
-	clock_enable_peripheral(CGC_OFFSET_GPIO, cgmask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	if (func != GPIO_ALT_FUNC_NONE) {
-		int pctlmask = 0;
-		int i;
-		/* Expand mask from bits to nibbles */
-		for (i = 0; i < 8; i++) {
-			if (mask & BIT(i))
-				pctlmask |= 1 << (4 * i);
-		}
-
-		LM4_GPIO_PCTL(port) =
-			(LM4_GPIO_PCTL(port) & ~(pctlmask * 0xf)) |
-			(pctlmask * func);
-		LM4_GPIO_AFSEL(port) |= mask;
-	} else {
-		LM4_GPIO_AFSEL(port) &= ~mask;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return LM4_GPIO_DATA(gpio_list[signal].port,
-			     gpio_list[signal].mask) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	/*
-	 * Ok to write 0xff because LM4_GPIO_DATA bit-masks only the bit
-	 * we care about.
-	 */
-	LM4_GPIO_DATA(gpio_list[signal].port,
-		      gpio_list[signal].mask) = (value ? 0xff : 0);
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/*
-	 * Select open drain first, so that we don't glitch the signal
-	 * when changing the line to an output.
-	 */
-	if (flags & GPIO_OPEN_DRAIN)
-		LM4_GPIO_ODR(port) |= mask;
-	else
-		LM4_GPIO_ODR(port) &= ~mask;
-
-	if (flags & GPIO_OUTPUT)
-		LM4_GPIO_DIR(port) |= mask;
-	else
-		LM4_GPIO_DIR(port) &= ~mask;
-
-	/* Handle pullup / pulldown */
-	if (flags & GPIO_PULL_UP) {
-		LM4_GPIO_PUR(port) |= mask;
-	} else if (flags & GPIO_PULL_DOWN) {
-		LM4_GPIO_PDR(port) |= mask;
-	} else {
-		/* No pull up/down */
-		LM4_GPIO_PUR(port) &= ~mask;
-		LM4_GPIO_PDR(port) &= ~mask;
-	}
-
-	/* Set up interrupt type */
-	if (flags & (GPIO_INT_F_LOW | GPIO_INT_F_HIGH))
-		LM4_GPIO_IS(port) |= mask;
-	else
-		LM4_GPIO_IS(port) &= ~mask;
-
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH))
-		LM4_GPIO_IEV(port) |= mask;
-	else
-		LM4_GPIO_IEV(port) &= ~mask;
-
-	/* Handle interrupting on both edges */
-	if ((flags & GPIO_INT_F_RISING) &&
-	    (flags & GPIO_INT_F_FALLING))
-		LM4_GPIO_IBE(port) |= mask;
-	else
-		LM4_GPIO_IBE(port) &= ~mask;
-
-	if (flags & GPIO_ANALOG)
-		LM4_GPIO_DEN(port) &= ~mask;
-	else
-		LM4_GPIO_DEN(port) |= mask;
-
-	/* Set level */
-	if (flags & GPIO_HIGH)
-		LM4_GPIO_DATA(port, mask) = 0xff;
-	else if (flags & GPIO_LOW)
-		LM4_GPIO_DATA(port, mask) = 0;
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	/* Fail if no interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_UNKNOWN;
-
-	LM4_GPIO_IM(g->port) |= g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if no interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_UNKNOWN;
-
-	LM4_GPIO_IM(g->port) &= ~g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if no interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	LM4_GPIO_ICR(g->port) |= g->mask;
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * Convert GPIO port to a mask that can be used to set the
- * clock gate control register for GPIOs.
- */
-static int gpio_port_to_clock_gate_mask(uint32_t gpio_port)
-{
-	int index = find_gpio_port_index(gpio_port);
-
-	return index >= 0 ? BIT(index) : 0;
-}
-#endif
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int is_warm = 0;
-	int i;
-
-	if (LM4_SYSTEM_RCGCGPIO == 0x7fff) {
-		/* This is a warm reboot */
-		is_warm = 1;
-	} else {
-		/*
-		 * Enable clocks to all the GPIO blocks since we use all of
-		 * them as GPIOs in run and sleep modes.
-		 */
-		clock_enable_peripheral(CGC_OFFSET_GPIO, 0x7fff,
-				CGC_MODE_RUN | CGC_MODE_SLEEP);
-	}
-
-	/*
-	 * Disable GPIO commit control for PD7 and PF0, since we don't use the
-	 * NMI pin function.
-	 */
-	LM4_GPIO_LOCK(LM4_GPIO_D) = LM4_GPIO_LOCK_UNLOCK;
-	LM4_GPIO_CR(LM4_GPIO_D) |= 0x80;
-	LM4_GPIO_LOCK(LM4_GPIO_D) = 0;
-	LM4_GPIO_LOCK(LM4_GPIO_F) = LM4_GPIO_LOCK_UNLOCK;
-	LM4_GPIO_CR(LM4_GPIO_F) |= 0x01;
-	LM4_GPIO_LOCK(LM4_GPIO_F) = 0;
-
-	/* Clear SSI0 alternate function on PA2:5 */
-	LM4_GPIO_AFSEL(LM4_GPIO_A) &= ~0x3c;
-
-	/* Mask all GPIO interrupts */
-	for (i = 0; gpio_bases[i]; i++)
-		LM4_GPIO_IM(gpio_bases[i]) = 0;
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-		/*
-		 * Enable board specific GPIO ports to interrupt deep sleep by
-		 * providing a clock to that port in deep sleep mode.
-		 */
-		if (flags & GPIO_INT_DSLEEP) {
-			clock_enable_peripheral(CGC_OFFSET_GPIO,
-				gpio_port_to_clock_gate_mask(g->port),
-				CGC_MODE_ALL);
-		}
-#endif
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the main chipset.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * Enable KB scan row to interrupt deep sleep by providing a clock
-	 * signal to that port in deep sleep mode.
-	 */
-	clock_enable_peripheral(CGC_OFFSET_GPIO,
-				gpio_port_to_clock_gate_mask(KB_SCAN_ROW_GPIO),
-				CGC_MODE_ALL);
-#endif
-}
-
-/* List of GPIO IRQs to enable. Don't automatically enable interrupts for
- * the keyboard input GPIO bank - that's handled separately. Of course the
- * bank is different for different systems. */
-static const uint8_t gpio_irqs[] = {
-	LM4_IRQ_GPIOA, LM4_IRQ_GPIOB, LM4_IRQ_GPIOC, LM4_IRQ_GPIOD,
-	LM4_IRQ_GPIOE, LM4_IRQ_GPIOF, LM4_IRQ_GPIOG, LM4_IRQ_GPIOH,
-	LM4_IRQ_GPIOJ,
-#if defined(KB_SCAN_ROW_IRQ) && (KB_SCAN_ROW_IRQ != LM4_IRQ_GPIOK)
-	LM4_IRQ_GPIOK,
-#endif
-	LM4_IRQ_GPIOL, LM4_IRQ_GPIOM,
-#if defined(KB_SCAN_ROW_IRQ) && (KB_SCAN_ROW_IRQ != LM4_IRQ_GPION)
-	LM4_IRQ_GPION,
-#endif
-	LM4_IRQ_GPIOP, LM4_IRQ_GPIOQ
-};
-
-static void gpio_init(void)
-{
-	int i;
-
-	/* Enable IRQs now that pins are set up */
-	for (i = 0; i < ARRAY_SIZE(gpio_irqs); i++)
-		task_enable_irq(gpio_irqs[i]);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle a GPIO interrupt.
- *
- * @param port		GPIO port (LM4_GPIO_*)
- * @param mis		Masked interrupt status value for that port
- */
-static void gpio_interrupt(int port, uint32_t mis)
-{
-	int i = 0;
-	const struct gpio_info *g = gpio_list;
-
-	for (i = 0; i < GPIO_IH_COUNT && mis; i++, g++) {
-		if (port == g->port && (mis & g->mask)) {
-			gpio_irq_handlers[i](i);
-			mis &= ~g->mask;
-		}
-	}
-}
-
-/**
- * Handlers for each GPIO port.  These read and clear the interrupt bits for
- * the port, then call the main handler above.
- */
-#define GPIO_IRQ_FUNC(irqfunc, gpiobase)		\
-	void irqfunc(void)				\
-	{						\
-		uint32_t mis = LM4_GPIO_MIS(gpiobase);	\
-		LM4_GPIO_ICR(gpiobase) = mis;		\
-		gpio_interrupt(gpiobase, mis);		\
-	}
-
-GPIO_IRQ_FUNC(__gpio_a_interrupt, LM4_GPIO_A);
-GPIO_IRQ_FUNC(__gpio_b_interrupt, LM4_GPIO_B);
-GPIO_IRQ_FUNC(__gpio_c_interrupt, LM4_GPIO_C);
-GPIO_IRQ_FUNC(__gpio_d_interrupt, LM4_GPIO_D);
-GPIO_IRQ_FUNC(__gpio_e_interrupt, LM4_GPIO_E);
-GPIO_IRQ_FUNC(__gpio_f_interrupt, LM4_GPIO_F);
-GPIO_IRQ_FUNC(__gpio_g_interrupt, LM4_GPIO_G);
-GPIO_IRQ_FUNC(__gpio_h_interrupt, LM4_GPIO_H);
-GPIO_IRQ_FUNC(__gpio_j_interrupt, LM4_GPIO_J);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_K)
-GPIO_IRQ_FUNC(__gpio_k_interrupt, LM4_GPIO_K);
-#endif
-GPIO_IRQ_FUNC(__gpio_l_interrupt, LM4_GPIO_L);
-GPIO_IRQ_FUNC(__gpio_m_interrupt, LM4_GPIO_M);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_N)
-GPIO_IRQ_FUNC(__gpio_n_interrupt, LM4_GPIO_N);
-#endif
-GPIO_IRQ_FUNC(__gpio_p_interrupt, LM4_GPIO_P);
-GPIO_IRQ_FUNC(__gpio_q_interrupt, LM4_GPIO_Q);
-
-#undef GPIO_IRQ_FUNC
-
-/*
- * Declare IRQs.  Nesting this macro inside the GPIO_IRQ_FUNC macro works
- * poorly because DECLARE_IRQ() stringizes its inputs.
- */
-DECLARE_IRQ(LM4_IRQ_GPIOA, __gpio_a_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOB, __gpio_b_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOC, __gpio_c_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOD, __gpio_d_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOE, __gpio_e_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOF, __gpio_f_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOG, __gpio_g_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOH, __gpio_h_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOJ, __gpio_j_interrupt, 1);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_K)
-DECLARE_IRQ(LM4_IRQ_GPIOK, __gpio_k_interrupt, 1);
-#endif
-DECLARE_IRQ(LM4_IRQ_GPIOL, __gpio_l_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOM, __gpio_m_interrupt, 1);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_N)
-DECLARE_IRQ(LM4_IRQ_GPION, __gpio_n_interrupt, 1);
-#endif
-DECLARE_IRQ(LM4_IRQ_GPIOP, __gpio_p_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOQ, __gpio_q_interrupt, 1);
diff --git a/chip/lm4/hwtimer.c b/chip/lm4/hwtimer.c
deleted file mode 100644
index 44e1c2fb27..0000000000
--- a/chip/lm4/hwtimer.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	/* set the match on the deadline */
-	LM4_TIMER_TAMATCHR(6) = 0xffffffff - deadline;
-	/* Set the match interrupt */
-	LM4_TIMER_IMR(6) |= 0x10;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return 0xffffffff - LM4_TIMER_TAMATCHR(6);
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* Disable the match interrupt */
-	LM4_TIMER_IMR(6) &= ~0x10;
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return 0xffffffff - LM4_TIMER_TAV(6);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	LM4_TIMER_TAV(6) = 0xffffffff - ts;
-}
-
-void __hw_clock_source_irq(void)
-{
-	uint32_t status = LM4_TIMER_RIS(6);
-
-	/* Clear interrupt */
-	LM4_TIMER_ICR(6) = status;
-
-	/*
-	 * Find expired timers and set the new timer deadline; check the IRQ
-	 * status to determine if the free-running counter overflowed.
-	 */
-	process_timers(status & 0x01);
-}
-DECLARE_IRQ(LM4_IRQ_TIMERW0A, __hw_clock_source_irq, 1);
-
-static void update_prescaler(void)
-{
-	/*
-	 * Set the prescaler to increment every microsecond.  This takes
-	 * effect immediately, because the TAILD bit in TAMR is clear.
-	 */
-	LM4_TIMER_TAPR(6) = clock_get_freq() / SECOND;
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * Use WTIMER0 (timer 6) configured as a free running counter with 1 us
-	 * period.
-	 */
-
-	/* Enable WTIMER0 clock in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_WTIMER, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Ensure timer is disabled : TAEN = TBEN = 0 */
-	LM4_TIMER_CTL(6) &= ~0x101;
-	/* Set overflow interrupt */
-	LM4_TIMER_IMR(6) = 0x1;
-	/* 32-bit timer mode */
-	LM4_TIMER_CFG(6) = 4;
-
-	/* Set initial prescaler */
-	update_prescaler();
-
-	/* Periodic mode, counting down */
-	LM4_TIMER_TAMR(6) = 0x22;
-	/* Use the full 32-bits of the timer */
-	LM4_TIMER_TAILR(6) = 0xffffffff;
-	/* Starts counting in timer A */
-	LM4_TIMER_CTL(6) |= 0x1;
-
-	/*
-	 * Override the count with the start value now that counting has
-	 * started.
-	 */
-	__hw_clock_source_set(start_t);
-
-	/* Enable interrupt */
-	task_enable_irq(LM4_IRQ_TIMERW0A);
-
-	return LM4_IRQ_TIMERW0A;
-}
diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c
deleted file mode 100644
index 56084c38e6..0000000000
--- a/chip/lm4/i2c.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for Chrome EC */
-
-#include "atomic.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Flags for writes to MCS */
-#define LM4_I2C_MCS_RUN   BIT(0)
-#define LM4_I2C_MCS_START BIT(1)
-#define LM4_I2C_MCS_STOP  BIT(2)
-#define LM4_I2C_MCS_ACK   BIT(3)
-#define LM4_I2C_MCS_HS    BIT(4)
-#define LM4_I2C_MCS_QCMD  BIT(5)
-
-/* Flags for reads from MCS */
-#define LM4_I2C_MCS_BUSY   BIT(0)
-#define LM4_I2C_MCS_ERROR  BIT(1)
-#define LM4_I2C_MCS_ADRACK BIT(2)
-#define LM4_I2C_MCS_DATACK BIT(3)
-#define LM4_I2C_MCS_ARBLST BIT(4)
-#define LM4_I2C_MCS_IDLE   BIT(5)
-#define LM4_I2C_MCS_BUSBSY BIT(6)
-#define LM4_I2C_MCS_CLKTO  BIT(7)
-
-/*
- * Minimum delay between resetting the port or sending a stop condition,
- * and when the port can be expected to be back in an idle state (and
- * the peripheral has had long enough to see the start/stop condition
- * edges).
- *
- * 500 us = 50 clocks at 100 KHz bus speed.  This has been experimentally
- * determined to be enough.
- */
-#define I2C_IDLE_US 500
-
-/* IRQ for each port */
-static const uint32_t i2c_irqs[] = {LM4_IRQ_I2C0, LM4_IRQ_I2C1, LM4_IRQ_I2C2,
-				    LM4_IRQ_I2C3, LM4_IRQ_I2C4, LM4_IRQ_I2C5};
-BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_PORT_COUNT);
-
-/* I2C port state data */
-struct i2c_port_data {
-	const uint8_t *out;	/* Output data pointer */
-	int out_size;		/* Output data to transfer, in bytes */
-	uint8_t *in;		/* Input data pointer */
-	int in_size;		/* Input data to transfer, in bytes */
-	int flags;		/* Flags (I2C_XFER_*) */
-	int idx;		/* Index into input/output data */
-	int err;		/* Error code, if any */
-	uint32_t timeout_us;	/* Transaction timeout, or 0 to use default */
-
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	volatile int task_waiting;
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-int i2c_is_busy(int port)
-{
-	return LM4_I2C_MCS(port) & LM4_I2C_MCS_BUSBSY;
-}
-
-/**
- * I2C transfer engine.
- *
- * @return Zero when done with transfer (ready to wake task).
- *
- * MCS sequence on multi-byte write:
- *     0x3 0x1 0x1 ... 0x1 0x5
- * Single byte write:
- *     0x7
- *
- * MCS receive sequence on multi-byte read:
- *     0xb 0x9 0x9 ... 0x9 0x5
- * Single byte read:
- *     0x7
- */
-int i2c_do_work(int port)
-{
-	struct i2c_port_data *pd = pdata + port;
-	uint32_t reg_mcs = LM4_I2C_MCS_RUN;
-
-	if (pd->flags & I2C_XFER_START) {
-		/* Set start bit on first byte */
-		reg_mcs |= LM4_I2C_MCS_START;
-		pd->flags &= ~I2C_XFER_START;
-	} else if (LM4_I2C_MCS(port) & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST |
-					LM4_I2C_MCS_ERROR)) {
-		/*
-		 * Error after starting; abort transfer.  Ignore errors at
-		 * start because arbitration and timeout errors are taken care
-		 * of in chip_i2c_xfer(), and peripheral ack failures will
-		 * automatically clear once we send a start condition.
-		 */
-		pd->err = EC_ERROR_UNKNOWN;
-		return 0;
-	}
-
-	if (pd->out_size) {
-		/* Send next byte of output */
-		LM4_I2C_MDR(port) = *(pd->out++);
-		pd->idx++;
-
-		/* Handle starting to send last byte */
-		if (pd->idx == pd->out_size) {
-
-			/* Done with output after this */
-			pd->out_size = 0;
-			pd->idx = 0;
-
-			/* Resend start bit when changing direction */
-			pd->flags |= I2C_XFER_START;
-
-			/*
-			 * Send stop bit after last byte if the stop flag is
-			 * on, and caller doesn't expect to receive data.
-			 */
-			if ((pd->flags & I2C_XFER_STOP) && pd->in_size == 0)
-				reg_mcs |= LM4_I2C_MCS_STOP;
-		}
-
-		LM4_I2C_MCS(port) = reg_mcs;
-		return 1;
-
-	} else if (pd->in_size) {
-		if (pd->idx) {
-			/* Copy the byte we just read */
-			*(pd->in++) = LM4_I2C_MDR(port) & 0xff;
-		} else {
-			/* Starting receive; switch to receive address */
-			LM4_I2C_MSA(port) |= 0x01;
-		}
-
-		if (pd->idx < pd->in_size) {
-			/* More data to read */
-			pd->idx++;
-
-			/* ACK all bytes except the last one */
-			if ((pd->flags & I2C_XFER_STOP) &&
-			    pd->idx == pd->in_size)
-				reg_mcs |= LM4_I2C_MCS_STOP;
-			else
-				reg_mcs |= LM4_I2C_MCS_ACK;
-
-			LM4_I2C_MCS(port) = reg_mcs;
-			return 1;
-		}
-	}
-
-	/* If we're still here, done with transfer */
-	return 0;
-}
-
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	struct i2c_port_data *pd = pdata + port;
-	uint32_t reg_mcs = LM4_I2C_MCS(port);
-	int events = 0;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	/* Copy data to port struct */
-	pd->out = out;
-	pd->out_size = out_size;
-	pd->in = in;
-	pd->in_size = in_size;
-	pd->flags = flags;
-	pd->idx = 0;
-	pd->err = 0;
-
-	/* Make sure we're in a good state to start */
-	if ((flags & I2C_XFER_START) &&
-	    ((reg_mcs & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST)) ||
-			    (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
-		uint32_t tpr = LM4_I2C_MTPR(port);
-
-		CPRINTS("I2C%d Addr:%02X bad status 0x%02x, SCL=%d, SDA=%d",
-			port,
-			I2C_STRIP_FLAGS(addr_flags),
-			reg_mcs,
-			i2c_get_line_levels(port) & I2C_LINE_SCL_HIGH,
-			i2c_get_line_levels(port) & I2C_LINE_SDA_HIGH);
-
-		/* Attempt to unwedge the port. */
-		i2c_unwedge(port);
-
-		/* Clock timeout or arbitration lost.  Reset port to clear. */
-		atomic_or(LM4_SYSTEM_SRI2C_ADDR, BIT(port));
-		clock_wait_cycles(3);
-		atomic_clear_bits(LM4_SYSTEM_SRI2C_ADDR, BIT(port));
-		clock_wait_cycles(3);
-
-		/* Restore settings */
-		LM4_I2C_MCR(port) = 0x10;
-		LM4_I2C_MTPR(port) = tpr;
-
-		/*
-		 * We don't know what edges the peripheral saw, so sleep
-		 * long enough that the peripheral will see the new
-		 * start condition below.
-		 */
-		usleep(I2C_IDLE_US);
-	}
-
-	/* Set peripheral address for transmit */
-	LM4_I2C_MSA(port) = (I2C_STRIP_FLAGS(addr_flags) << 1) & 0xff;
-
-	/* Enable interrupts */
-	pd->task_waiting = task_get_current();
-	LM4_I2C_MICR(port) = 0x03;
-	LM4_I2C_MIMR(port) = 0x03;
-
-	/* Kick the port interrupt handler to start the transfer */
-	task_trigger_irq(i2c_irqs[port]);
-
-	/* Wait for transfer complete or timeout */
-	events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, pd->timeout_us);
-
-	/* Disable interrupts */
-	LM4_I2C_MIMR(port) = 0x00;
-	pd->task_waiting = TASK_ID_INVALID;
-
-	/* Handle timeout */
-	if (events & TASK_EVENT_TIMER)
-		pd->err = EC_ERROR_TIMEOUT;
-
-	if (pd->err) {
-		/* Force port back idle */
-		LM4_I2C_MCS(port) = LM4_I2C_MCS_STOP;
-		usleep(I2C_IDLE_US);
-	}
-
-	return pd->err;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-	int ret;
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	/* If we are driving the pin low, it must be low. */
-	if (gpio_get_level(g) == 0)
-		return 0;
-
-	/*
-	 * Otherwise, we need to toggle it to an input to read the true pin
-	 * state.
-	 */
-	gpio_set_flags(g, GPIO_INPUT);
-	ret = gpio_get_level(g);
-	gpio_set_flags(g, GPIO_ODR_HIGH);
-
-	return ret;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-	int ret;
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	/* If we are driving the pin low, it must be low. */
-	if (gpio_get_level(g) == 0)
-		return 0;
-
-	/*
-	 * Otherwise, we need to toggle it to an input to read the true pin
-	 * state.
-	 */
-	gpio_set_flags(g, GPIO_INPUT);
-	ret = gpio_get_level(g);
-	gpio_set_flags(g, GPIO_ODR_HIGH);
-
-	return ret;
-}
-
-int i2c_get_line_levels(int port)
-{
-	/* Conveniently, MBMON bit BIT(1) is SDA and BIT(0) is SCL. */
-	return LM4_I2C_MBMON(port) & 0x03;
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void i2c_freq_changed(void)
-{
-	int freq = clock_get_freq();
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		/*
-		 * From datasheet:
-		 *     SCL_PRD = 2 * (1 + TPR) * (SCL_LP + SCL_HP) * CLK_PRD
-		 *
-		 * so:
-		 *     TPR = SCL_PRD / (2 * (SCL_LP + SCL_HP) * CLK_PRD) - 1
-		 *
-		 * converting from period to frequency:
-		 *     TPR = CLK_FREQ / (SCL_FREQ * 2 * (SCL_LP + SCL_HP)) - 1
-		 */
-		const int d = 2 * (6 + 4) * (i2c_ports[i].kbps * 1000);
-
-		/* Round TPR up, so desired kbps is an upper bound */
-		const int tpr = (freq + d - 1) / d - 1;
-
-#ifdef PRINT_I2C_SPEEDS
-		const int f = freq / (2 * (1 + tpr) * (6 + 4));
-		CPRINTS("I2C%d clk=%d tpr=%d freq=%d",
-			i2c_ports[i].port, freq, tpr, f);
-#endif
-
-		LM4_I2C_MTPR(i2c_ports[i].port) = tpr;
-	}
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT);
-
-void i2c_init(void)
-{
-	uint32_t mask = 0;
-	int i;
-
-	/* Enable I2C modules in run and sleep modes. */
-	for (i = 0; i < i2c_ports_used; i++)
-		mask |= 1 << i2c_ports[i].port;
-
-	clock_enable_peripheral(CGC_OFFSET_I2C, mask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Initialize ports as controller, with interrupts enabled */
-	for (i = 0; i < i2c_ports_used; i++)
-		LM4_I2C_MCR(i2c_ports[i].port) = 0x10;
-
-	/* Set initial clock frequency */
-	i2c_freq_changed();
-
-	/* Enable IRQs; no tasks are waiting on ports */
-	for (i = 0; i < I2C_PORT_COUNT; i++) {
-		pdata[i].task_waiting = TASK_ID_INVALID;
-		task_enable_irq(i2c_irqs[i]);
-
-		/* Use default timeout */
-		i2c_set_timeout(i, 0);
-	}
-}
-
-/**
- * Handle an interrupt on the specified port.
- *
- * @param port		I2C port generating interrupt
- */
-static void handle_interrupt(int port)
-{
-	int id = pdata[port].task_waiting;
-
-	/* Clear the interrupt status */
-	LM4_I2C_MICR(port) = LM4_I2C_MMIS(port);
-
-	/* If no task is waiting, just return */
-	if (id == TASK_ID_INVALID)
-		return;
-
-	/* If done doing work, wake up the task waiting for the transfer */
-	if (!i2c_do_work(port))
-		task_set_event(id, TASK_EVENT_I2C_IDLE);
-}
-
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
-void i2c4_interrupt(void) { handle_interrupt(4); }
-void i2c5_interrupt(void) { handle_interrupt(5); }
-
-DECLARE_IRQ(LM4_IRQ_I2C0, i2c0_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C1, i2c1_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C2, i2c2_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C3, i2c3_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C4, i2c4_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C5, i2c5_interrupt, 2);
diff --git a/chip/lm4/keyboard_raw.c b/chip/lm4/keyboard_raw.c
deleted file mode 100644
index 81af0efdde..0000000000
--- a/chip/lm4/keyboard_raw.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions needed by keyboard scanner module for Chrome EC */
-
-#include "common.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-
-void keyboard_raw_init(void)
-{
-	/* Ensure top-level interrupt is disabled */
-	keyboard_raw_enable_interrupt(0);
-
-	/*
-	 * Set column outputs as open-drain; we either pull them low or let
-	 * them float high.
-	 */
-	LM4_GPIO_AFSEL(LM4_GPIO_P) = 0;  /* KSO[7:0] */
-	LM4_GPIO_AFSEL(LM4_GPIO_Q) &= ~0x1f;  /* KSO[12:8] */
-	LM4_GPIO_DEN(LM4_GPIO_P) = 0xff;
-	LM4_GPIO_DEN(LM4_GPIO_Q) |= 0x1f;
-	LM4_GPIO_DIR(LM4_GPIO_P) = 0xff;
-	LM4_GPIO_DIR(LM4_GPIO_Q) |= 0x1f;
-	LM4_GPIO_ODR(LM4_GPIO_P) = 0xff;
-	LM4_GPIO_ODR(LM4_GPIO_Q) |= 0x1f;
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/*
-	 * When column 2 is inverted, the Silego has a pulldown instead of a
-	 * pullup.  So drive it push-pull instead of open-drain.
-	 */
-	LM4_GPIO_ODR(LM4_GPIO_P) &= ~BIT(2);
-#endif
-
-	/* Set row inputs with pull-up */
-	LM4_GPIO_AFSEL(KB_SCAN_ROW_GPIO) &= 0xff;
-	LM4_GPIO_DEN(KB_SCAN_ROW_GPIO) |= 0xff;
-	LM4_GPIO_DIR(KB_SCAN_ROW_GPIO) = 0;
-	LM4_GPIO_PUR(KB_SCAN_ROW_GPIO) = 0xff;
-
-	/* Edge-sensitive on both edges. */
-	LM4_GPIO_IS(KB_SCAN_ROW_GPIO) = 0;
-	LM4_GPIO_IBE(KB_SCAN_ROW_GPIO) = 0xff;
-
-	/*
-	 * Enable interrupts for the inputs.  The top-level interrupt is still
-	 * masked off, so this won't trigger interrupts yet.
-	 */
-	LM4_GPIO_IM(KB_SCAN_ROW_GPIO) = 0xff;
-}
-
-void keyboard_raw_task_start(void)
-{
-	task_enable_irq(KB_SCAN_ROW_IRQ);
-}
-
-test_mockable void keyboard_raw_drive_column(int col)
-{
-	int mask;
-
-	if (col == KEYBOARD_COLUMN_NONE)
-		mask = 0x1fff;			/* Tri-state all outputs */
-	else if (col == KEYBOARD_COLUMN_ALL)
-		mask = 0;			/* Assert all outputs */
-	else
-		mask = 0x1fff ^ BIT(col);	/* Assert a single output */
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/* Invert column 2 output */
-	mask ^= BIT(2);
-#endif
-
-	LM4_GPIO_DATA(LM4_GPIO_P, 0xff) = mask & 0xff;
-	LM4_GPIO_DATA(LM4_GPIO_Q, 0x1f) = (mask >> 8) & 0x1f;
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Bits are active-low, so invert returned levels */
-	return LM4_GPIO_DATA(KB_SCAN_ROW_GPIO, 0xff) ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/*
-		 * Clear pending interrupts before enabling them, because the
-		 * raw interrupt status may have been tripped by keyboard
-		 * scanning or, if a key is already pressed, by driving all the
-		 * outputs.
-		 *
-		 * We won't lose keyboard events because the scanning task will
-		 * explicitly check the raw row state before waiting for an
-		 * interrupt.  If a key is pressed, the task won't wait.
-		 */
-		LM4_GPIO_ICR(KB_SCAN_ROW_GPIO) = 0xff;
-		LM4_GPIO_IM(KB_SCAN_ROW_GPIO) = 0xff;
-	} else {
-		LM4_GPIO_IM(KB_SCAN_ROW_GPIO) = 0;
-	}
-}
-
-/**
- * Interrupt handler for the entire GPIO bank of keyboard rows.
- */
-void keyboard_raw_interrupt(void)
-{
-	/* Clear all pending keyboard interrupts */
-	LM4_GPIO_ICR(KB_SCAN_ROW_GPIO) = 0xff;
-
-	/* Wake the scan task */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(KB_SCAN_ROW_IRQ, keyboard_raw_interrupt, 3);
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
deleted file mode 100644
index 6e3c39220d..0000000000
--- a/chip/lm4/lpc.c
+++ /dev/null
@@ -1,835 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for Chrome EC */
-
-#include "acpi.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "port80.h"
-#include "pwm.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* LPC channels */
-#define LPC_CH_ACPI     0  /* ACPI commands */
-#define LPC_CH_PORT80   1  /* Port 80 debug output */
-#define LPC_CH_CMD_DATA 2  /* Data for host commands (args/params/response) */
-#define LPC_CH_KEYBOARD 3  /* 8042 keyboard emulation */
-#define LPC_CH_CMD      4  /* Host commands */
-#define LPC_CH_MEMMAP   5  /* Memory-mapped data */
-#define LPC_CH_COMX     7  /* UART emulation */
-/* LPC pool offsets */
-#define LPC_POOL_OFFS_ACPI       0  /* ACPI commands - 0=in, 1=out */
-#define LPC_POOL_OFFS_PORT80     4  /* Port 80 - 4=in, 5=out */
-#define LPC_POOL_OFFS_COMX       8  /* UART emulation range - 8-15 */
-#define LPC_POOL_OFFS_KEYBOARD  16  /* Keyboard - 16=in, 17=out */
-#define LPC_POOL_OFFS_CMD       20  /* Host commands - 20=in, 21=out */
-#define LPC_POOL_OFFS_CMD_DATA 512  /* Data range for host commands - 512-767 */
-#define LPC_POOL_OFFS_MEMMAP   768  /* Memory-mapped data - 768-1023 */
-/* LPC pool data pointers */
-#define LPC_POOL_ACPI     (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_ACPI)
-#define LPC_POOL_PORT80   (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_PORT80)
-#define LPC_POOL_COMX     (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_COMX)
-#define LPC_POOL_KEYBOARD (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_KEYBOARD)
-#define LPC_POOL_CMD      (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_CMD)
-#define LPC_POOL_CMD_DATA (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_CMD_DATA)
-#define LPC_POOL_MEMMAP   (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_MEMMAP)
-/* LPC COMx I/O address (in x86 I/O address space) */
-#define LPC_COMX_ADDR 0x3f8  /* COM1 */
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-/* Params must be 32-bit aligned */
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static uint8_t * const cmd_params = (uint8_t *)LPC_POOL_CMD_DATA +
-	EC_LPC_ADDR_HOST_PARAM - EC_LPC_ADDR_HOST_ARGS;
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)LPC_POOL_CMD_DATA;
-
-static void wait_irq_sent(void)
-{
-	/*
-	 * A hard-coded delay here isn't very elegant, but it's the best we can
-	 * manage (and it's a short delay, so it's not that horrible).  We need
-	 * this because SIRQRIS isn't cleared in continuous mode, and the EC
-	 * has trouble sending more than 1 frame in quiet mode.  Waiting 4 us =
-	 * 2 SERIRQ frames ensures the IRQ has been sent out.
-	 */
-	udelay(4);
-}
-
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-static void keyboard_irq_assert(void)
-{
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	uint64_t tstop = get_time().val + MSEC;
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	/* Wait for host senses the interrupt and gets the char. */
-	do {
-		if (get_time().val > tstop)
-			break;
-	} while (lpc_keyboard_has_char());
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-}
-#else
-static void wait_send_serirq(uint32_t lpcirqctl)
-{
-	LM4_LPC_LPCIRQCTL = lpcirqctl;
-	wait_irq_sent();
-}
-
-/**
- * Manually generate an IRQ to host (edge-trigger).
- *
- * @param irq_num	IRQ number to generate.  Pass 0 to set the AH
- *			(active high) bit.
- *
- * For SERIRQ quite mode, we need to set LM4_LPC_LPCIRQCTL twice.
- * The first one is to assert IRQ (pull low), and then the second one is
- * to de-assert it. This generates a pulse (high-low-high) for an IRQ.
- */
-static void lpc_manual_irq(int irq_num)
-{
-	uint32_t common_bits =
-	    0x00000004 |  /* PULSE */
-	    0x00000002 |  /* ONCHG - for quiet mode */
-	    0x00000001;   /* SND - send immediately */
-
-	/* Send out the IRQ first. */
-	wait_send_serirq((1 << (irq_num + 16)) | common_bits);
-
-	/* Generate a all-high frame to simulate a rising edge. */
-	wait_send_serirq(common_bits);
-}
-
-static inline void keyboard_irq_assert(void)
-{
-	/* Use serirq method. */
-	lpc_manual_irq(1);  /* IRQ#1 */
-}
-#endif
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-	host_event_t smi;
-
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-
-	smi = lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI);
-	if (smi)
-		HOST_EVENT_CPRINTS("smi", smi);
-}
-
-/**
- * Generate SCI pulse to the host chipset via LPC0SCI.
- */
-static void lpc_generate_sci(void)
-{
-	host_event_t sci;
-
-#ifdef CONFIG_SCI_GPIO
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#else
-	LM4_LPC_LPCCTL |= LM4_LPC_SCI_START;
-#endif
-
-	sci = lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI);
-	if (sci)
-		HOST_EVENT_CPRINTS("sci", sci);
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(uint64_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return (uint8_t *)LPC_POOL_MEMMAP;
-}
-
-static void lpc_send_response(struct host_cmd_handler_args *args)
-{
-	uint8_t *out;
-	int size = args->response_size;
-	int csum;
-	int i;
-
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (args->result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Handle negative size */
-	if (size < 0) {
-		args->result = EC_RES_INVALID_RESPONSE;
-		size = 0;
-	}
-
-	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-		EC_HOST_ARGS_FLAG_TO_HOST;
-
-	lpc_host_args->data_size = size;
-
-	csum = args->command + lpc_host_args->flags +
-		lpc_host_args->command_version +
-		lpc_host_args->data_size;
-
-	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
-		csum += *out;
-
-	lpc_host_args->checksum = (uint8_t)csum;
-
-	/* Fail if response doesn't fit in the param buffer */
-	if (size > EC_PROTO2_MAX_PARAM_SIZE)
-		args->result = EC_RES_INVALID_RESPONSE;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	LPC_POOL_CMD[1] = args->result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	task_disable_irq(LM4_IRQ_LPC);
-	LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
-	task_enable_irq(LM4_IRQ_LPC);
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	LPC_POOL_CMD[1] = pkt->driver_result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	task_disable_irq(LM4_IRQ_LPC);
-	LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
-	task_enable_irq(LM4_IRQ_LPC);
-}
-
-int lpc_keyboard_has_char(void)
-{
-	return (LM4_LPC_ST(LPC_CH_KEYBOARD) & LM4_LPC_ST_TOH) ? 1 : 0;
-}
-
-/* Return true if the FRMH is set */
-int lpc_keyboard_input_pending(void)
-{
-	return (LM4_LPC_ST(LPC_CH_KEYBOARD) & LM4_LPC_ST_FRMH) ? 1 : 0;
-}
-
-/* Put a char to host buffer and send IRQ if specified. */
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	LPC_POOL_KEYBOARD[1] = chr;
-	if (send_irq)
-		keyboard_irq_assert();
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	/* Make sure the previous TOH and IRQ has been sent out. */
-	wait_irq_sent();
-
-	LM4_LPC_ST(LPC_CH_KEYBOARD) &= ~LM4_LPC_ST_TOH;
-
-	/* Ensure there is no TOH set in this period. */
-	wait_irq_sent();
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-#ifdef CONFIG_UART_HOST
-
-int lpc_comx_has_char(void)
-{
-	return LM4_LPC_ST(LPC_CH_COMX) & LM4_LPC_ST_FRMH;
-}
-
-int lpc_comx_get_char(void)
-{
-	return LPC_POOL_COMX[0];
-}
-
-void lpc_comx_put_char(int c)
-{
-	LPC_POOL_COMX[1] = c;
-
-	/*
-	 * We could in theory manually trigger an IRQ, like we do for the 8042
-	 * keyboard interface, but neither the kernel nor BIOS seems to require
-	 * this.
-	 */
-}
-
-#endif /* CONFIG_UART_HOST */
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via EC_SMI_L GPIO
- *   - SCI pulse via LPC0SCI
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	task_disable_irq(LM4_IRQ_LPC);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(LM4_LPC_ST(LPC_CH_ACPI) & LM4_LPC_ST_SMI))
-			need_smi = 1;
-		LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_SMI;
-	} else
-		LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_SMI;
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_SCI;
-	} else
-		LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_SCI;
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	task_enable_irq(LM4_IRQ_LPC);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	uint32_t set_mask = 0;
-	if (mask & EC_LPC_STATUS_BURST_MODE)
-		set_mask |= LM4_LPC_ST_BURST;
-
-	LM4_LPC_ST(LPC_CH_ACPI) |= set_mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	uint32_t clear_mask = 0;
-	if (mask & EC_LPC_STATUS_BURST_MODE)
-		clear_mask |= LM4_LPC_ST_BURST;
-
-	LM4_LPC_ST(LPC_CH_ACPI) &= ~clear_mask;
-}
-
-int lpc_get_pltrst_asserted(void)
-{
-	return (LM4_LPC_LPCSTS & BIT(10)) ? 1 : 0;
-}
-
-/**
- * Handle write to ACPI I/O port
- *
- * @param is_cmd	Is write command (is_cmd=1) or data (is_cmd=0)
- */
-static void handle_acpi_write(int is_cmd)
-{
-	uint8_t value, result;
-
-	/* Set the busy bit */
-	LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_BUSY;
-
-	/* Read command/data; this clears the FRMH status bit. */
-	value = LPC_POOL_ACPI[0];
-
-	/* Handle whatever this was. */
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		LPC_POOL_ACPI[1] = result;
-
-	/* Clear the busy bit */
-	LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_BUSY;
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
-	 * Full condition on the kernel channel.
-	 */
-	lpc_generate_sci();
-}
-
-/**
- * Handle write to host command I/O ports.
- *
- * @param is_cmd	Is write command (1) or data (0)?
- */
-static void handle_host_write(int is_cmd)
-{
-	/* Ignore data writes or overlapping commands from host */
-	uint32_t is_overlapping = LM4_LPC_ST(LPC_CH_CMD) & LM4_LPC_ST_BUSY;
-	if (!is_cmd || is_overlapping) {
-		if (is_overlapping)
-			CPRINTS("LPC Ignoring overlapping HC");
-		LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_FRMH;
-		return;
-	}
-
-	/* Set the busy bit */
-	LM4_LPC_ST(LPC_CH_CMD) |= LM4_LPC_ST_BUSY;
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = LPC_POOL_CMD[0];
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_args.send_response = lpc_send_response;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* See if we have an old or new style command */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)LPC_POOL_CMD_DATA;
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)LPC_POOL_CMD_DATA;
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-		host_packet_receive(&lpc_packet);
-		return;
-
-	} else if (host_cmd_flags & EC_HOST_ARGS_FLAG_FROM_HOST) {
-		/* Version 2 (link) style command */
-		int size = lpc_host_args->data_size;
-		int csum, i;
-
-		host_cmd_args.version = lpc_host_args->command_version;
-		host_cmd_args.params = params_copy;
-		host_cmd_args.params_size = size;
-		host_cmd_args.response = cmd_params;
-		host_cmd_args.response_max = EC_PROTO2_MAX_PARAM_SIZE;
-		host_cmd_args.response_size = 0;
-
-		/* Verify params size */
-		if (size > EC_PROTO2_MAX_PARAM_SIZE) {
-			host_cmd_args.result = EC_RES_INVALID_PARAM;
-		} else {
-			const uint8_t *src = cmd_params;
-			uint8_t *copy = params_copy;
-
-			/*
-			 * Verify checksum and copy params out of LPC space.
-			 * This ensures the data acted on by the host command
-			 * handler can't be changed by host writes after the
-			 * checksum is verified.
-			 */
-			csum = host_cmd_args.command +
-				host_cmd_flags +
-				host_cmd_args.version +
-				host_cmd_args.params_size;
-
-			for (i = 0; i < size; i++) {
-				csum += *src;
-				*(copy++) = *(src++);
-			}
-
-			if ((uint8_t)csum != lpc_host_args->checksum)
-				host_cmd_args.result = EC_RES_INVALID_CHECKSUM;
-		}
-	} else {
-		/* Old style command, now unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-}
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-/**
- * LPC interrupt handler
- */
-void lpc_interrupt(void)
-{
-	uint32_t mis = LM4_LPC_LPCMIS;
-	uint32_t st;
-
-	/* Clear the interrupt bits we're handling */
-	LM4_LPC_LPCIC = mis;
-
-#ifdef HAS_TASK_HOSTCMD
-	/* Handle ACPI command and data writes */
-	st = LM4_LPC_ST(LPC_CH_ACPI);
-	if (st & LM4_LPC_ST_FRMH)
-		handle_acpi_write(st & LM4_LPC_ST_CMD);
-
-	/* Handle user command writes */
-	st = LM4_LPC_ST(LPC_CH_CMD);
-	if (st & LM4_LPC_ST_FRMH)
-		handle_host_write(st & LM4_LPC_ST_CMD);
-#endif
-
-	/*
-	 * Handle port 80 writes (CH0MIS1).  Due to crosbug.com/p/12349 the
-	 * interrupt status (mis & LM4_LPC_INT_MASK(LPC_CH_PORT80, 2))
-	 * apparently gets lost on back-to-back writes to port 80, so check the
-	 * FRMH bit in the channel status register to see if a write is
-	 * pending.  Loop to handle bursts of back-to-back writes.
-	 */
-	while (LM4_LPC_ST(LPC_CH_PORT80) & LM4_LPC_ST_FRMH)
-		port_80_write(LPC_POOL_PORT80[0]);
-
-#ifdef HAS_TASK_KEYPROTO
-	/* Handle keyboard interface writes */
-	st = LM4_LPC_ST(LPC_CH_KEYBOARD);
-	if (st & LM4_LPC_ST_FRMH)
-		keyboard_host_write(LPC_POOL_KEYBOARD[0], st & LM4_LPC_ST_CMD);
-
-	if (mis & LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 1)) {
-		/* Host read data; wake up task to send remaining bytes */
-		task_wake(TASK_ID_KEYPROTO);
-	}
-#endif
-
-#ifdef CONFIG_UART_HOST
-	/* Handle COMx */
-	if (lpc_comx_has_char()) {
-		/* Copy a character to the UART if there's space */
-		if (uart_comx_putc_ok())
-			uart_comx_putc(lpc_comx_get_char());
-	}
-#endif
-
-	/* Debugging: print changes to LPC0RESET */
-	if (mis & BIT(31)) {
-		if (LM4_LPC_LPCSTS & BIT(10)) {
-			int i;
-
-			/* Store port 80 reset event */
-			port_80_write(PORT_80_EVENT_RESET);
-
-			/*
-			 * Workaround for crosbug.com/p/12349; clear all FRMH
-			 * bits so host writes will trigger interrupts.
-			 */
-			for (i = 0; i < 8; i++)
-				LM4_LPC_ST(i) &= ~LM4_LPC_ST_FRMH;
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-			/* Notify HOOK_CHIPSET_RESET */
-			hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-		}
-
-		CPRINTS("LPC RESET# %sasserted",
-			lpc_get_pltrst_asserted() ? "" : "de");
-	}
-}
-DECLARE_IRQ(LM4_IRQ_LPC, lpc_interrupt, 2);
-
-/* Enable LPC ACPI-EC interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_ACPI, 6);
-}
-
-/* Disable LPC ACPI-EC interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	LM4_LPC_LPCIM &= ~(LM4_LPC_INT_MASK(LPC_CH_ACPI, 6));
-}
-
-static void lpc_init(void)
-{
-	/* Enable LPC clock in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_LPC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	LM4_LPC_LPCIM = 0;
-	LM4_LPC_LPCCTL = 0;
-	LM4_LPC_LPCIRQCTL = 0;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_LPC, 1);
-
-	/*
-	 * Set LPC channel 0 to I/O address 0x62 (data) / 0x66 (command),
-	 * single endpoint, offset 0 for host command/writes and 1 for EC
-	 * data writes, pool bytes 0(data)/1(cmd)
-	 */
-	LM4_LPC_ADR(LPC_CH_ACPI) = EC_LPC_ADDR_ACPI_DATA;
-	LM4_LPC_CTL(LPC_CH_ACPI) = (LPC_POOL_OFFS_ACPI << (5 - 1));
-	LM4_LPC_ST(LPC_CH_ACPI) = 0;
-	/* Unmask interrupt for host command and data writes */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_ACPI, 6);
-
-	/*
-	 * Set LPC channel 1 to I/O address 0x80 (data), single endpoint,
-	 * pool bytes 4(data)/5(cmd).
-	 */
-	LM4_LPC_ADR(LPC_CH_PORT80) = 0x80;
-	LM4_LPC_CTL(LPC_CH_PORT80) = (LPC_POOL_OFFS_PORT80 << (5 - 1));
-	/* Unmask interrupt for host data writes */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_PORT80, 2);
-
-	/*
-	 * Set LPC channel 2 to I/O address 0x880, range endpoint,
-	 * arbitration disabled, pool bytes 512-639.  To access this from
-	 * x86, use the following command to set GEN_LPC2:
-	 *
-	 *   pci_write32 0 0x1f 0 0x88 0x007c0801
-	 */
-	LM4_LPC_ADR(LPC_CH_CMD_DATA) = EC_LPC_ADDR_HOST_ARGS;
-	LM4_LPC_CTL(LPC_CH_CMD_DATA) = 0x8019 |
-		(LPC_POOL_OFFS_CMD_DATA << (5 - 1));
-
-	/*
-	 * Set LPC channel 3 to I/O address 0x60 (data) / 0x64 (command),
-	 * single endpoint, offset 0 for host command/writes and 1 for EC
-	 * data writes, pool bytes 0(data)/1(cmd)
-	 */
-	LM4_LPC_ADR(LPC_CH_KEYBOARD) = 0x60;
-	LM4_LPC_CTL(LPC_CH_KEYBOARD) = (BIT(24)/* IRQSEL1 */) |
-		(0 << 18/* IRQEN1 */) | (LPC_POOL_OFFS_KEYBOARD << (5 - 1));
-	LM4_LPC_ST(LPC_CH_KEYBOARD) = 0;
-	/* Unmask interrupt for host command/data writes and data reads */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 7);
-
-	/*
-	 * Set LPC channel 4 to I/O address 0x200 (data) / 0x204 (command),
-	 * single endpoint, offset 0 for host command/writes and 1 for EC
-	 * data writes, pool bytes 0(data)/1(cmd)
-	 */
-	LM4_LPC_ADR(LPC_CH_CMD) = EC_LPC_ADDR_HOST_DATA;
-	LM4_LPC_CTL(LPC_CH_CMD) = (LPC_POOL_OFFS_CMD << (5 - 1));
-	/*
-	 * Initialize status bits to 0.  We never set the ACPI burst status bit,
-	 * so this guarantees that at least one status bit will always be 0.
-	 * This is used by comm_lpc.c to detect that the EC is present on the
-	 * LPC bus.  See crosbug.com/p/10963.
-	 */
-	LM4_LPC_ST(LPC_CH_CMD) = 0;
-	/* Unmask interrupt for host command writes */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_CMD, 4);
-
-	/*
-	 * Set LPC channel 5 to I/O address 0x900, range endpoint,
-	 * arbitration enabled, pool bytes 768-1023.  To access this from
-	 * x86, use the following command to set GEN_LPC3:
-	 *
-	 *   pci_write32 0 0x1f 0 0x8c 0x007c0901
-	 */
-	LM4_LPC_ADR(LPC_CH_MEMMAP) = EC_LPC_ADDR_MEMMAP;
-	LM4_LPC_CTL(LPC_CH_MEMMAP) = 0x0019 | (LPC_POOL_OFFS_MEMMAP << (5 - 1));
-
-#ifdef CONFIG_UART_HOST
-	/*
-	 * Set LPC channel 7 to COM port I/O address.  Note that channel 7
-	 * ignores the TYPE bit and is always an 8-byte range.
-	 */
-	LM4_LPC_ADR(LPC_CH_COMX) = LPC_COMX_ADDR;
-	/*
-	 * In theory we could configure IRQSELs and set IRQEN2/CX, and then the
-	 * host could enable IRQs on its own.  So far that hasn't been
-	 * necessary, and due to the issues with IRQs (see wait_irq_sent()
-	 * above) it might not work anyway.
-	 */
-	LM4_LPC_CTL(LPC_CH_COMX) = 0x0004 | (LPC_POOL_OFFS_COMX << (5 - 1));
-	/* Enable COMx emulation for reads and writes. */
-	LM4_LPC_LPCDMACX = 0x00310000;
-	/*
-	 * Unmask interrupt for host data writes.  We don't need interrupts for
-	 * reads, because there's no flow control in that direction; LPC is
-	 * much faster than the UART, and the UART doesn't have anywhere
-	 * sensible to buffer input anyway.
-	 */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_COMX, 2);
-#endif /* CONFIG_UART_HOST */
-
-	/*
-	 * Unmask LPC bus reset interrupt.  This lets us monitor the PCH
-	 * PLTRST# signal for debugging.
-	 */
-	LM4_LPC_LPCIM |= BIT(31);
-
-	/* Enable LPC channels */
-	LM4_LPC_LPCCTL = LM4_LPC_SCI_CLK_1 |
-		BIT(LPC_CH_ACPI) |
-		BIT(LPC_CH_PORT80) |
-		BIT(LPC_CH_CMD_DATA) |
-		BIT(LPC_CH_KEYBOARD) |
-		BIT(LPC_CH_CMD) |
-		BIT(LPC_CH_MEMMAP);
-
-#ifdef CONFIG_UART_HOST
-	LM4_LPC_LPCCTL |= 1 << LPC_CH_COMX;
-#endif
-
-	/*
-	 * Ensure the EC (peripheral) has control of the memory-mapped
-	 * I/O space.  Once the EC has won arbitration for the
-	 * memory-mapped space, it will keep control of it until it
-	 * writes the last byte in the space.  (That never happens; we
-	 * can't use the last byte in the space because ACPI can't see
-	 * it anyway.)
-	 */
-	while (!(LM4_LPC_ST(LPC_CH_MEMMAP) & 0x10)) {
-		/* Clear HW1ST */
-		LM4_LPC_ST(LPC_CH_MEMMAP) &= ~0x40;
-		/* Do a peripheral write; this should cause SW1ST to be set */
-		*LPC_POOL_MEMMAP = *LPC_POOL_MEMMAP;
-	}
-
-	/* Initialize host args and memory map to all zero */
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-
-	/* Enable LPC interrupt */
-	task_enable_irq(LM4_IRQ_LPC);
-
-#ifdef CONFIG_UART_HOST
-	/* Enable COMx UART */
-	uart_comx_enable();
-#endif
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-static void lpc_tick(void)
-{
-	/*
-	 * Make sure pending LPC interrupts have been processed.
-	 * This works around a LM4 bug where host writes sometimes
-	 * don't trigger interrupts.  See crosbug.com/p/13965.
-	 */
-	task_trigger_irq(LM4_IRQ_LPC);
-}
-DECLARE_HOOK(HOOK_TICK, lpc_tick, HOOK_PRIO_DEFAULT);
-
-/**
- * Get protocol information
- */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(2) | BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     lpc_get_protocol_info,
-		     EC_VER_MASK(0));
diff --git a/chip/lm4/peci.c b/chip/lm4/peci.c
deleted file mode 100644
index b3b54a64bc..0000000000
--- a/chip/lm4/peci.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PECI interface for Chrome EC */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "peci.h"
-#include "registers.h"
-#include "temp_sensor.h"
-#include "util.h"
-
-/* Initial PECI baud rate */
-#define PECI_BAUD_RATE 100000
-
-/* Polling interval for PECI, in ms */
-#define PECI_POLL_INTERVAL_MS 250
-
-/*
- * Internal and external path delays, in ns.  The external delay is a
- * best-guess measurement, but we're fairly tolerant of a bad guess because
- * PECI_BAUD_RATE is slow compared to PECI's actual maximum baud rate.
- */
-#define PECI_TD_FET_NS 60
-#define PECI_TD_INT_NS 80
-
-/* Number of controller retries. Should be between 0 and 7. */
-#define PECI_RETRY_COUNT 4
-
-/* Timing negotiation error bypass. 1 = on. 0 = off. */
-#define PECI_ERROR_BYPASS 1
-
-#define TEMP_AVG_LENGTH 4  /* Should be power of 2 */
-static int temp_vals[TEMP_AVG_LENGTH];
-static int temp_idx;
-
-int peci_get_cpu_temp(void)
-{
-	int v = LM4_PECI_M0D0 & 0xffff;
-
-	if (v >= 0x8000 && v <= 0x8fff)
-		return -1;
-
-	return v >> 6;
-}
-
-int peci_temp_sensor_get_val(int idx, int *temp_ptr)
-{
-	int sum = 0;
-	int success_cnt = 0;
-	int i;
-
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return EC_ERROR_NOT_POWERED;
-
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i) {
-		if (temp_vals[i] >= 0) {
-			success_cnt++;
-			sum += temp_vals[i];
-		}
-	}
-
-	/*
-	 * Require at least two valid samples. When the AP transitions into S0,
-	 * it is possible, depending on the timing of the PECI sample, to read
-	 * an invalid temperature. This is very rare, but when it does happen
-	 * the temperature returned is CONFIG_PECI_TJMAX. Requiring two valid
-	 * samples here assures us that one bad maximum temperature reading
-	 * when entering S0 won't cause us to trigger an over temperature.
-	 */
-	if (success_cnt < 2)
-		return EC_ERROR_UNKNOWN;
-
-	*temp_ptr = sum / success_cnt;
-	return EC_SUCCESS;
-}
-
-static void peci_temp_sensor_poll(void)
-{
-	temp_vals[temp_idx] = peci_get_cpu_temp();
-	temp_idx = (temp_idx + 1) & (TEMP_AVG_LENGTH - 1);
-}
-DECLARE_HOOK(HOOK_TICK, peci_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-static void peci_freq_changed(void)
-{
-	int freq = clock_get_freq();
-	int baud;
-
-	/* Disable polling while reconfiguring */
-	LM4_PECI_CTL = 0;
-
-	/*
-	 * Calculate baud setting from desired rate, compensating for internal
-	 * and external delays.
-	 */
-	baud = freq / (4 * PECI_BAUD_RATE) - 2;
-	baud -= (freq / 1000000) * (PECI_TD_FET_NS + PECI_TD_INT_NS) / 1000;
-
-	/* Set baud rate and polling rate */
-	LM4_PECI_DIV = (baud << 16) |
-		(PECI_POLL_INTERVAL_MS * (freq / 1000 / 4096));
-
-	/* Set up temperature monitoring to report in degrees K */
-	LM4_PECI_CTL = ((CONFIG_PECI_TJMAX + 273) << 22) | 0x0001 |
-		       (PECI_RETRY_COUNT << 12) |
-		       (PECI_ERROR_BYPASS << 11);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, peci_freq_changed, HOOK_PRIO_DEFAULT);
-
-static void peci_init(void)
-{
-	int i;
-
-	/* Enable the PECI module in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_PECI, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_PECI, 1);
-
-	/* Set initial clock frequency */
-	peci_freq_changed();
-
-	/* Initialize temperature reading buffer to a valid value. */
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i)
-		temp_vals[i] = 300; /* 27 C */
-}
-DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_peci_temp(int argc, char **argv)
-{
-	int t = peci_get_cpu_temp();
-	if (t == -1) {
-		ccprintf("PECI error 0x%04x\n", LM4_PECI_M0D0 & 0xffff);
-		return EC_ERROR_UNKNOWN;
-	}
-	ccprintf("CPU temp = %d K = %d C\n", t, K_TO_C(t));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-			NULL,
-			"Print CPU temperature");
diff --git a/chip/lm4/pwm.c b/chip/lm4/pwm.c
deleted file mode 100644
index 38ce61714d..0000000000
--- a/chip/lm4/pwm.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for LM4.
- *
- * On this chip, the PWM logic is implemented by the hardware FAN modules.
- */
-
-#include "clock.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	fan_set_enabled(pwm_channels[ch].channel, enabled);
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return fan_get_enabled(pwm_channels[ch].channel);
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	/* Assume the fan control is active high and invert it ourselves */
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	/* Always enable the channel */
-	pwm_enable(ch, 1);
-
-	/* Set the duty cycle */
-	fan_set_duty(pwm_channels[ch].channel, percent);
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	int percent = fan_get_duty(pwm_channels[ch].channel);
-
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	return percent;
-}
-
-static void pwm_init(void)
-{
-	int i;
-
-	for (i = 0; i < PWM_CH_COUNT; ++i)
-		fan_channel_setup(pwm_channels[i].channel,
-				       (pwm_channels[i].flags &
-					PWM_CONFIG_HAS_RPM_MODE)
-				       ? FAN_USE_RPM_MODE : 0);
-}
-
-/* The chip-specific fan module initializes before this. */
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/lm4/pwm_chip.h b/chip/lm4/pwm_chip.h
deleted file mode 100644
index ada5785495..0000000000
--- a/chip/lm4/pwm_chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4-specific PWM module for Chrome EC */
-
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM channel ID */
-	int channel;
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h
deleted file mode 100644
index 0c59da19f6..0000000000
--- a/chip/lm4/registers.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for LM4x processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-#define LM4_UART_CH0_BASE      0x4000c000
-#define LM4_UART_CH1_BASE      0x4000d000
-#define LM4_UART_CH_SEP        0x00001000
-static inline int lm4_uart_addr(int ch, int offset)
-{
-	return offset + LM4_UART_CH0_BASE + LM4_UART_CH_SEP * ch;
-}
-#define LM4UARTREG(ch, offset) REG32(lm4_uart_addr(ch, offset))
-#define LM4_UART_DR(ch)        LM4UARTREG(ch, 0x000)
-#define LM4_UART_FR(ch)        LM4UARTREG(ch, 0x018)
-#define LM4_UART_IBRD(ch)      LM4UARTREG(ch, 0x024)
-#define LM4_UART_FBRD(ch)      LM4UARTREG(ch, 0x028)
-#define LM4_UART_LCRH(ch)      LM4UARTREG(ch, 0x02c)
-#define LM4_UART_CTL(ch)       LM4UARTREG(ch, 0x030)
-#define LM4_UART_IFLS(ch)      LM4UARTREG(ch, 0x034)
-#define LM4_UART_IM(ch)        LM4UARTREG(ch, 0x038)
-#define LM4_UART_ICR(ch)       LM4UARTREG(ch, 0x044)
-#define LM4_UART_DMACTL(ch)    LM4UARTREG(ch, 0x048)
-#define LM4_UART_CC(ch)        LM4UARTREG(ch, 0xfc8)
-
-#define LM4_SSI_BASE           0x40008000
-#define LM4_SSI_CH_SEP         0x40001000
-static inline int lm4_spi_addr(int ch, int offset)
-{
-	return offset + LM4_SSI_BASE + LM4_SSI_CH_SEP * ch;
-}
-#define LM4SSIREG(ch, offset)  REG32(lm4_spi_addr(ch, offset))
-#define LM4_SSI_CR0(ch)        LM4SSIREG(ch, 0x000)
-#define LM4_SSI_CR1(ch)        LM4SSIREG(ch, 0x004)
-#define LM4_SSI_DR(ch)         LM4SSIREG(ch, 0x008)
-#define LM4_SSI_SR(ch)         LM4SSIREG(ch, 0x00c)
-#define LM4_SSI_SR_TFE         BIT(0)  /* Transmit FIFO empty */
-#define LM4_SSI_SR_TNF         BIT(1)  /* Transmit FIFO not full */
-#define LM4_SSI_SR_RNE         BIT(2)  /* Receive FIFO not empty */
-#define LM4_SSI_SR_RFF         BIT(3)  /* Receive FIFO full */
-#define LM4_SSI_SR_BSY         BIT(4)  /* Busy */
-#define LM4_SSI_CPSR(ch)       LM4SSIREG(ch, 0x010)
-#define LM4_SSI_IM(ch)         LM4SSIREG(ch, 0x014)
-#define LM4_SSI_RIS(ch)        LM4SSIREG(ch, 0x018)
-#define LM4_SSI_MIS(ch)        LM4SSIREG(ch, 0x01c)
-#define LM4_SSI_ICR(ch)        LM4SSIREG(ch, 0x020)
-#define LM4_SSI_DMACTL(ch)     LM4SSIREG(ch, 0x024)
-#define LM4_SSI_CC(ch)         LM4SSIREG(ch, 0xfc8)
-
-#define LM4_ADC_ADCACTSS       REG32(0x40038000)
-#define LM4_ADC_ADCRIS         REG32(0x40038004)
-#define LM4_ADC_ADCIM          REG32(0x40038008)
-#define LM4_ADC_ADCISC         REG32(0x4003800c)
-#define LM4_ADC_ADCOSTAT       REG32(0x40038010)
-#define LM4_ADC_ADCEMUX        REG32(0x40038014)
-#define LM4_ADC_ADCUSTAT       REG32(0x40038018)
-#define LM4_ADC_ADCSSPRI       REG32(0x40038020)
-#define LM4_ADC_ADCSPC         REG32(0x40038024)
-#define LM4_ADC_ADCPSSI        REG32(0x40038028)
-#define LM4_ADC_ADCSAC         REG32(0x40038030)
-#define LM4_ADC_ADCCTL         REG32(0x40038038)
-#define LM4_ADC_ADCCC          REG32(0x40038fc8)
-#define LM4_ADC_SS0_BASE       0x40038040
-#define LM4_ADC_SS1_BASE       0x40038060
-#define LM4_ADC_SS2_BASE       0x40038080
-#define LM4_ADC_SS3_BASE       0x400380a0
-#define LM4_ADC_SS_SEP         0x00000020
-static inline int lm4_adc_addr(int ss, int offset)
-{
-	return offset + LM4_ADC_SS0_BASE + LM4_ADC_SS_SEP * ss;
-}
-#define LM4ADCREG(ss, offset)  REG32(lm4_adc_addr(ss, offset))
-#define LM4_ADC_SSMUX(ss)      LM4ADCREG(ss, 0x000)
-#define LM4_ADC_SSCTL(ss)      LM4ADCREG(ss, 0x004)
-#define LM4_ADC_SSFIFO(ss)     LM4ADCREG(ss, 0x008)
-#define LM4_ADC_SSFSTAT(ss)    LM4ADCREG(ss, 0x00c)
-#define LM4_ADC_SSOP(ss)       LM4ADCREG(ss, 0x010)
-#define LM4_ADC_SSEMUX(ss)     LM4ADCREG(ss, 0x018)
-
-#define LM4_LPC_LPCCTL         REG32(0x40080000)
-#define LM4_LPC_SCI_START      BIT(9)  /* Start a pulse on LPC0SCI signal */
-#define LM4_LPC_SCI_CLK_1      (0 << 10) /* SCI asserted for 1 clock period */
-#define LM4_LPC_SCI_CLK_2      (1 << 10) /* SCI asserted for 2 clock periods */
-#define LM4_LPC_SCI_CLK_4      (2 << 10) /* SCI asserted for 4 clock periods */
-#define LM4_LPC_SCI_CLK_8      (3 << 10) /* SCI asserted for 8 clock periods */
-#define LM4_LPC_LPCSTS         REG32(0x40080004)
-#define LM4_LPC_LPCIRQCTL      REG32(0x40080008)
-#define LM4_LPC_LPCIRQST       REG32(0x4008000c)
-#define LM4_LPC_LPCIM          REG32(0x40080100)
-#define LM4_LPC_LPCRIS         REG32(0x40080104)
-#define LM4_LPC_LPCMIS         REG32(0x40080108)
-#define LM4_LPC_LPCIC          REG32(0x4008010c)
-#define LM4_LPC_INT_MASK(ch, bits) ((bits) << (4 * (ch)))
-#define LM4_LPC_LPCDMACX       REG32(0x40080120)
-#define LM4_LPC_CH0_BASE       0x40080010
-#define LM4_LPC_CH1_BASE       0x40080020
-#define LM4_LPC_CH2_BASE       0x40080030
-#define LM4_LPC_CH3_BASE       0x40080040
-#define LM4_LPC_CH4_BASE       0x40080050
-#define LM4_LPC_CH5_BASE       0x40080060
-#define LM4_LPC_CH6_BASE       0x40080070
-#define LM4_LPC_CH7_BASE       0x40080080
-#define LM4_LPC_CH_SEP         0x00000010
-static inline int lm4_lpc_addr(int ch, int offset)
-{
-	return offset + LM4_LPC_CH0_BASE + LM4_LPC_CH_SEP * ch;
-}
-#define LM4LPCREG(ch, offset)  REG32(lm4_lpc_addr(ch, offset))
-#define LM4_LPC_CTL(ch)        LM4LPCREG(ch, 0x000)
-#define LM4_LPC_ST(ch)         LM4LPCREG(ch, 0x004)
-#define LM4_LPC_ST_TOH         BIT(0)  /* TO Host bit */
-#define LM4_LPC_ST_FRMH        BIT(1)  /* FRoM Host bit */
-#define LM4_LPC_ST_CMD         BIT(3)  /* Last from-host byte was command */
-#define LM4_LPC_ST_BURST       BIT(8)
-#define LM4_LPC_ST_SCI         BIT(9)
-#define LM4_LPC_ST_SMI         BIT(10)
-#define LM4_LPC_ST_BUSY        BIT(12)
-#define LM4_LPC_ADR(ch)        LM4LPCREG(ch, 0x008)
-#define LM4_LPC_POOL_BYTES     1024   /* Size of LPCPOOL in bytes */
-#define LM4_LPC_LPCPOOL        ((volatile unsigned char *)0x40080400)
-
-#define LM4_FAN_FANSTS         REG32(0x40084000)
-#define LM4_FAN_FANCTL         REG32(0x40084004)
-#define LM4_FAN_CH0_BASE       0x40084010
-#define LM4_FAN_CH1_BASE       0x40084020
-#define LM4_FAN_CH2_BASE       0x40084030
-#define LM4_FAN_CH3_BASE       0x40084040
-#define LM4_FAN_CH4_BASE       0x40084050
-#define LM4_FAN_CH5_BASE       0x40084060
-#define LM4_FAN_CH_SEP         0x00000010
-static inline int lm4_fan_addr(int ch, int offset)
-{
-	return offset + LM4_FAN_CH0_BASE + LM4_FAN_CH_SEP * ch;
-}
-#define LM4FANREG(ch, offset)  REG32(lm4_fan_addr(ch, offset))
-#define LM4_FAN_FANCH(ch)      LM4FANREG(ch, 0x000)
-#define LM4_FAN_FANCMD(ch)     LM4FANREG(ch, 0x004)
-#define LM4_FAN_FANCST(ch)     LM4FANREG(ch, 0x008)
-
-#define LM4_EEPROM_EESIZE      REG32(0x400af000)
-#define LM4_EEPROM_EEBLOCK     REG32(0x400af004)
-#define LM4_EEPROM_EEOFFSET    REG32(0x400af008)
-#define LM4_EEPROM_EERDWR      REG32(0x400af010)
-#define LM4_EEPROM_EERDWRINC   REG32(0x400af014)
-#define LM4_EEPROM_EEDONE      REG32(0x400af018)
-#define LM4_EEPROM_EESUPP      REG32(0x400af01c)
-#define LM4_EEPROM_EEUNLOCK    REG32(0x400af020)
-#define LM4_EEPROM_EEPROT      REG32(0x400af030)
-#define LM4_EEPROM_EEPASS0     REG32(0x400af034)
-#define LM4_EEPROM_EEPASS1     REG32(0x400af038)
-#define LM4_EEPROM_EEPASS2     REG32(0x400af03c)
-#define LM4_EEPROM_EEINT       REG32(0x400af040)
-#define LM4_EEPROM_EEHIDE      REG32(0x400af050)
-
-#define LM4_PECI_CTL           REG32(0x400b0000)
-#define LM4_PECI_DIV           REG32(0x400b0004)
-#define LM4_PECI_CMP           REG32(0x400b0008)
-#define LM4_PECI_M0D0C         REG32(0x400b0010)
-#define LM4_PECI_M0D1C         REG32(0x400b0014)
-#define LM4_PECI_M1D0C         REG32(0x400b0018)
-#define LM4_PECI_M1D1C         REG32(0x400b001c)
-#define LM4_PECI_M0D0          REG32(0x400b0040)
-#define LM4_PECI_M0D1          REG32(0x400b0044)
-#define LM4_PECI_M1D0          REG32(0x400b0048)
-#define LM4_PECI_M1D1          REG32(0x400b004c)
-#define LM4_PECI_IM            REG32(0x400b0080)
-#define LM4_PECI_RIS           REG32(0x400b0084)
-#define LM4_PECI_MIS           REG32(0x400b0088)
-#define LM4_PECI_IC            REG32(0x400b008c)
-#define LM4_PECI_ACADDR        REG32(0x400b0100)
-#define LM4_PECI_ACARG         REG32(0x400b0104)
-#define LM4_PECI_ACRDWR0       REG32(0x400b0108)
-#define LM4_PECI_ACRDWR1       REG32(0x400b010c)
-#define LM4_PECI_ACCMD         REG32(0x400b0110)
-#define LM4_PECI_ACCODE        REG32(0x400b0114)
-
-
-#define LM4_HIBERNATE_HIBRTCC  REG32(0x400fc000)
-#define LM4_HIBERNATE_HIBRTCM0 REG32(0x400fc004)
-#define LM4_HIBERNATE_HIBRTCLD REG32(0x400fc00c)
-#define LM4_HIBERNATE_HIBCTL   REG32(0x400fc010)
-#define LM4_HIBCTL_WRC         BIT(31)
-#define LM4_HIBCTL_CLK32EN     BIT(6)
-#define LM4_HIBCTL_PINWEN      BIT(4)
-#define LM4_HIBCTL_RTCWEN      BIT(3)
-#define LM4_HIBCTL_HIBREQ      BIT(1)
-#define LM4_HIBCTL_RTCEN       BIT(0)
-#define LM4_HIBERNATE_HIBIM    REG32(0x400fc014)
-#define LM4_HIBERNATE_HIBRIS   REG32(0x400fc018)
-#define LM4_HIBERNATE_HIBMIS   REG32(0x400fc01c)
-#define LM4_HIBERNATE_HIBIC    REG32(0x400fc020)
-#define LM4_HIBERNATE_HIBRTCT  REG32(0x400fc024)
-#define LM4_HIBERNATE_HIBRTCSS REG32(0x400fc028)
-#define LM4_HIBERNATE_HIBDATA_ENTRIES 16  /* Number of entries in HIBDATA[] */
-#define LM4_HIBERNATE_HIBDATA  ((volatile uint32_t *)0x400fc030)
-
-#define LM4_FLASH_FMA          REG32(0x400fd000)
-#define LM4_FLASH_FMD          REG32(0x400fd004)
-#define LM4_FLASH_FMC          REG32(0x400fd008)
-#define LM4_FLASH_FCRIS        REG32(0x400fd00c)
-#define LM4_FLASH_FCMISC       REG32(0x400fd014)
-#define LM4_FLASH_FMC2         REG32(0x400fd020)
-#define LM4_FLASH_FWBVAL       REG32(0x400fd030)
-/* FWB size is 32 words = 128 bytes */
-#define LM4_FLASH_FWB          ((volatile uint32_t*)0x400fd100)
-#define LM4_FLASH_FSIZE        REG32(0x400fdfc0)
-#define LM4_FLASH_FMPRE0       REG32(0x400fe200)
-#define LM4_FLASH_FMPRE1       REG32(0x400fe204)
-#define LM4_FLASH_FMPRE2       REG32(0x400fe208)
-#define LM4_FLASH_FMPRE3       REG32(0x400fe20c)
-#define LM4_FLASH_FMPPE        ((volatile uint32_t*)0x400fe400)
-#define LM4_FLASH_FMPPE0       REG32(0x400fe400)
-#define LM4_FLASH_FMPPE1       REG32(0x400fe404)
-#define LM4_FLASH_FMPPE2       REG32(0x400fe408)
-#define LM4_FLASH_FMPPE3       REG32(0x400fe40c)
-
-#define LM4_SYSTEM_DID0        REG32(0x400fe000)
-#define LM4_SYSTEM_DID1        REG32(0x400fe004)
-#define LM4_SYSTEM_PBORCTL     REG32(0x400fe030)
-#define LM4_SYSTEM_RIS         REG32(0x400fe050)
-#define LM4_SYSTEM_MISC        REG32(0x400fe058)
-#define LM4_SYSTEM_RESC        REG32(0x400fe05c)
-#define LM4_SYSTEM_RCC         REG32(0x400fe060)
-#define LM4_SYSTEM_RCC_ACG        BIT(27)
-#define LM4_SYSTEM_RCC_SYSDIV(x)  (((x) & 0xf) << 23)
-#define LM4_SYSTEM_RCC_USESYSDIV  BIT(22)
-#define LM4_SYSTEM_RCC_PWRDN      BIT(13)
-#define LM4_SYSTEM_RCC_BYPASS     BIT(11)
-#define LM4_SYSTEM_RCC_XTAL(x)    (((x) & 0x1f) << 6)
-#define LM4_SYSTEM_RCC_OSCSRC(x)  (((x) & 0x3) << 4)
-#define LM4_SYSTEM_RCC_IOSCDIS    BIT(1)
-#define LM4_SYSTEM_RCC_MOSCDIS    BIT(0)
-#define LM4_SYSTEM_RCC2        REG32(0x400fe070)
-#define LM4_SYSTEM_RCC2_USERCC2     BIT(31)
-#define LM4_SYSTEM_RCC2_DIV400      BIT(30)
-#define LM4_SYSTEM_RCC2_SYSDIV2(x)  (((x) & 0x3f) << 23)
-#define LM4_SYSTEM_RCC2_SYSDIV2LSB  BIT(22)
-#define LM4_SYSTEM_RCC2_PWRDN2      BIT(13)
-#define LM4_SYSTEM_RCC2_BYPASS2     BIT(11)
-#define LM4_SYSTEM_RCC2_OSCSRC2(x)  (((x) & 0x7) << 4)
-#define LM4_SYSTEM_MOSCCTL     REG32(0x400fe07c)
-#define LM4_SYSTEM_DSLPCLKCFG  REG32(0x400fe144)
-#define LM4_SYSTEM_PIOSCCAL    REG32(0x400fe150)
-#define LM4_SYSTEM_PIOSCSTAT   REG32(0x400fe154)
-#define LM4_SYSTEM_PLLSTAT     REG32(0x400fe168)
-#define LM4_SYSTEM_SLPPWRCFG   REG32(0x400fe188)
-#define LM4_SYSTEM_DSLPPWRCFG  REG32(0x400fe18c)
-#define LM4_SYSTEM_LDOSPCTL    REG32(0x400fe1b4)
-#define LM4_SYSTEM_LDOSPCAL    REG32(0x400fe1b8)
-#define LM4_SYSTEM_LDODPCTL    REG32(0x400fe1bc)
-#define LM4_SYSTEM_LDODPCAL    REG32(0x400fe1c0)
-#define LM4_SYSTEM_SPDMST      REG32(0x400fe1cc)
-#define LM4_SYSTEM_BOOTCFG     REG32(0x400fe1d0)
-#define LM4_SYSTEM_BOOTCFG_MASK 0x7fff00ec /* Reserved bits of BOOTCFG reg */
-/* Note: USER_REG3 is used to hold pre-programming process data and should not
- * be modified by EC code.  See crosbug.com/p/8889. */
-#define LM4_SYSTEM_USER_REG3   REG32(0x400fe1ec)
-#define LM4_SYSTEM_SRI2C       REG32(0x400fe520)
-#define LM4_SYSTEM_SREEPROM    REG32(0x400fe558)
-
-#define LM4_SYSTEM_SRI2C_ADDR  ((uint32_t *)0x400fe520)
-
-#define LM4_SYSTEM_RCGC_BASE   ((volatile uint32_t *)0x400fe600)
-#define LM4_SYSTEM_RCGCGPIO    REG32(0x400fe608)
-#define LM4_SYSTEM_SCGC_BASE   ((volatile uint32_t *)0x400fe700)
-#define LM4_SYSTEM_DCGC_BASE   ((volatile uint32_t *)0x400fe800)
-
-/*
- * Offsets from CGC_BASE registers for each peripheral.
- * Note: these are in units of 32-bit words offset from
- * the base address.
- */
-enum clock_gate_offsets {
-	CGC_OFFSET_WD =        0,
-	CGC_OFFSET_TIMER =     1,
-	CGC_OFFSET_GPIO =      2,
-	CGC_OFFSET_DMA =       3,
-	CGC_OFFSET_HIB =       5,
-	CGC_OFFSET_UART =      6,
-	CGC_OFFSET_SSI =       7,
-	CGC_OFFSET_I2C =       8,
-	CGC_OFFSET_ADC =       14,
-	CGC_OFFSET_LPC =       18,
-	CGC_OFFSET_PECI =      20,
-	CGC_OFFSET_FAN =       21,
-	CGC_OFFSET_EEPROM =    22,
-	CGC_OFFSET_WTIMER =    23,
-};
-
-#define LM4_SYSTEM_PREEPROM    REG32(0x400fea58)
-
-#define LM4_DMA_DMACFG         REG32(0x400ff004)
-#define LM4_DMA_DMACTLBASE     REG32(0x400ff008)
-#define LM4_DMA_DMACHMAP0      REG32(0x400ff510)
-#define LM4_DMA_DMACHMAP1      REG32(0x400ff514)
-#define LM4_DMA_DMACHMAP2      REG32(0x400ff518)
-#define LM4_DMA_DMACHMAP3      REG32(0x400ff51c)
-
-/* IRQ numbers */
-#define LM4_IRQ_GPIOA            0
-#define LM4_IRQ_GPIOB            1
-#define LM4_IRQ_GPIOC            2
-#define LM4_IRQ_GPIOD            3
-#define LM4_IRQ_GPIOE            4
-#define LM4_IRQ_UART0            5
-#define LM4_IRQ_UART1            6
-#define LM4_IRQ_SSI0             7
-#define LM4_IRQ_I2C0             8
-/* 9 - 13 reserved */
-#define LM4_IRQ_ADC0_SS0        14
-#define LM4_IRQ_ADC0_SS1        15
-#define LM4_IRQ_ADC0_SS2        16
-#define LM4_IRQ_ADC0_SS3        17
-#define LM4_IRQ_WATCHDOG        18
-#define LM4_IRQ_TIMER0A         19
-#define LM4_IRQ_TIMER0B         20
-#define LM4_IRQ_TIMER1A         21
-#define LM4_IRQ_TIMER1B         22
-#define LM4_IRQ_TIMER2A         23
-#define LM4_IRQ_TIMER2B         24
-#define LM4_IRQ_ACMP0           25
-#define LM4_IRQ_ACMP1           26
-#define LM4_IRQ_ACMP2           27
-#define LM4_IRQ_SYSCTRL         28
-#define LM4_IRQ_EEPROM          29
-#define LM4_IRQ_GPIOF           30
-#define LM4_IRQ_GPIOG           31
-#define LM4_IRQ_GPIOH           32
-#define LM4_IRQ_UART2           33
-#define LM4_IRQ_SSI1            34
-#define LM4_IRQ_TIMER3A         35
-#define LM4_IRQ_TIMER3B         36
-#define LM4_IRQ_I2C1            37
-/* 38 - 42 reserved */
-#define LM4_IRQ_HIBERNATE       43
-/* 44 - 45 reserved */
-#define LM4_IRQ_UDMA_SOFTWARE   46
-#define LM4_IRQ_UDMA_ERROR      47
-#define LM4_IRQ_ADC1_SS0        48
-#define LM4_IRQ_ADC1_SS1        49
-#define LM4_IRQ_ADC1_SS2        50
-#define LM4_IRQ_ADC1_SS3        51
-/* 52 - 53 reserved */
-#define LM4_IRQ_GPIOJ           54
-#define LM4_IRQ_GPIOK           55
-#define LM4_IRQ_GPIOL           56
-#define LM4_IRQ_SSI2            57
-#define LM4_IRQ_SSI3            58
-#define LM4_IRQ_UART3           59
-#define LM4_IRQ_UART4           60
-#define LM4_IRQ_UART5           61
-#define LM4_IRQ_UART6           62
-#define LM4_IRQ_UART7           63
-/* 64 - 67 reserved */
-#define LM4_IRQ_I2C2            68
-#define LM4_IRQ_I2C3            69
-#define LM4_IRQ_TIMER4A         70
-#define LM4_IRQ_TIMER4B         71
-/* 72 - 91 reserved */
-#define LM4_IRQ_TIMER5A         92
-#define LM4_IRQ_TIMER5B         93
-#define LM4_IRQ_TIMERW0A        94
-#define LM4_IRQ_TIMERW0B        95
-#define LM4_IRQ_TIMERW1A        96
-#define LM4_IRQ_TIMERW1B        97
-#define LM4_IRQ_TIMERW2A        98
-#define LM4_IRQ_TIMERW2B        99
-#define LM4_IRQ_TIMERW3A       100
-#define LM4_IRQ_TIMERW3B       101
-#define LM4_IRQ_TIMERW4A       102
-#define LM4_IRQ_TIMERW4B       103
-#define LM4_IRQ_TIMERW5A       104
-#define LM4_IRQ_TIMERW5B       105
-#define LM4_IRQ_SYS_EXCEPTION  106
-#define LM4_IRQ_SYS_PECI       107
-#define LM4_IRQ_LPC            108
-#define LM4_IRQ_I2C4           109
-#define LM4_IRQ_I2C5           110
-#define LM4_IRQ_GPIOM          111
-#define LM4_IRQ_GPION          112
-/* 113 reserved */
-#define LM4_IRQ_FAN            114
-/* 115 reserved */
-#define LM4_IRQ_GPIOP          116
-#define LM4_IRQ_GPIOP1         117
-#define LM4_IRQ_GPIOP2         118
-#define LM4_IRQ_GPIOP3         119
-#define LM4_IRQ_GPIOP4         120
-#define LM4_IRQ_GPIOP5         121
-#define LM4_IRQ_GPIOP6         122
-#define LM4_IRQ_GPIOP7         123
-#define LM4_IRQ_GPIOQ          124
-#define LM4_IRQ_GPIOQ1         125
-#define LM4_IRQ_GPIOQ2         126
-#define LM4_IRQ_GPIOQ3         127
-#define LM4_IRQ_GPIOQ4         128
-#define LM4_IRQ_GPIOQ5         129
-#define LM4_IRQ_GPIOQ6         130
-#define LM4_IRQ_GPIOQ7         131
-/* 132 - 138 reserved */
-
-/* GPIO */
-#define LM4_GPIO_PORTA_BASE         0x40004000
-#define LM4_GPIO_PORTB_BASE         0x40005000
-#define LM4_GPIO_PORTC_BASE         0x40006000
-#define LM4_GPIO_PORTD_BASE         0x40007000
-#define LM4_GPIO_PORTE_BASE         0x40024000
-#define LM4_GPIO_PORTF_BASE         0x40025000
-#define LM4_GPIO_PORTG_BASE         0x40026000
-#define LM4_GPIO_PORTH_BASE         0x40027000
-#define LM4_GPIO_PORTJ_BASE         0x4003d000
-#define LM4_GPIO_PORTK_BASE         0x40061000
-#define LM4_GPIO_PORTL_BASE         0x40062000
-#define LM4_GPIO_PORTM_BASE         0x40063000
-#define LM4_GPIO_PORTN_BASE         0x40064000
-#define LM4_GPIO_PORTP_BASE         0x40065000
-#define LM4_GPIO_PORTQ_BASE         0x40066000
-#define LM4_GPIO_PORTA_AHB_BASE     0x40058000
-#define LM4_GPIO_PORTB_AHB_BASE     0x40059000
-#define LM4_GPIO_PORTC_AHB_BASE     0x4005a000
-#define LM4_GPIO_PORTD_AHB_BASE     0x4005b000
-#define LM4_GPIO_PORTE_AHB_BASE     0x4005c000
-#define LM4_GPIO_PORTF_AHB_BASE     0x4005d000
-#define LM4_GPIO_PORTG_AHB_BASE     0x4005e000
-#define LM4_GPIO_PORTH_AHB_BASE     0x4005f000
-#define LM4_GPIO_PORTJ_AHB_BASE     0x40060000
-/* Ports for passing to LM4GPIOREG(); abstracted from base addresses above so
- * that we can switch to/from AHB. */
-#define LM4_GPIO_A LM4_GPIO_PORTA_BASE
-#define LM4_GPIO_B LM4_GPIO_PORTB_BASE
-#define LM4_GPIO_C LM4_GPIO_PORTC_BASE
-#define LM4_GPIO_D LM4_GPIO_PORTD_BASE
-#define LM4_GPIO_E LM4_GPIO_PORTE_BASE
-#define LM4_GPIO_F LM4_GPIO_PORTF_BASE
-#define LM4_GPIO_G LM4_GPIO_PORTG_BASE
-#define LM4_GPIO_H LM4_GPIO_PORTH_BASE
-#define LM4_GPIO_J LM4_GPIO_PORTJ_BASE
-#define LM4_GPIO_K LM4_GPIO_PORTK_BASE
-#define LM4_GPIO_L LM4_GPIO_PORTL_BASE
-#define LM4_GPIO_M LM4_GPIO_PORTM_BASE
-#define LM4_GPIO_N LM4_GPIO_PORTN_BASE
-#define LM4_GPIO_P LM4_GPIO_PORTP_BASE
-#define LM4_GPIO_Q LM4_GPIO_PORTQ_BASE
-#define LM4GPIOREG(port, offset)      REG32((port) + (offset))
-#define LM4_GPIO_DATA(port, mask)     LM4GPIOREG(port, ((mask) << 2))
-#define LM4_GPIO_DIR(port)            LM4GPIOREG(port, 0x400)
-#define LM4_GPIO_IS(port)             LM4GPIOREG(port, 0x404)
-#define LM4_GPIO_IBE(port)            LM4GPIOREG(port, 0x408)
-#define LM4_GPIO_IEV(port)            LM4GPIOREG(port, 0x40c)
-#define LM4_GPIO_IM(port)             LM4GPIOREG(port, 0x410)
-#define LM4_GPIO_RIS(port)            LM4GPIOREG(port, 0x414)
-#define LM4_GPIO_MIS(port)            LM4GPIOREG(port, 0x418)
-#define LM4_GPIO_ICR(port)            LM4GPIOREG(port, 0x41c)
-#define LM4_GPIO_AFSEL(port)          LM4GPIOREG(port, 0x420)
-#define LM4_GPIO_DR2R(port)           LM4GPIOREG(port, 0x500)
-#define LM4_GPIO_DR4R(port)           LM4GPIOREG(port, 0x504)
-#define LM4_GPIO_DR8R(port)           LM4GPIOREG(port, 0x508)
-#define LM4_GPIO_ODR(port)            LM4GPIOREG(port, 0x50c)
-#define LM4_GPIO_PUR(port)            LM4GPIOREG(port, 0x510)
-#define LM4_GPIO_PDR(port)            LM4GPIOREG(port, 0x514)
-#define LM4_GPIO_SLR(port)            LM4GPIOREG(port, 0x518)
-#define LM4_GPIO_DEN(port)            LM4GPIOREG(port, 0x51c)
-#define LM4_GPIO_LOCK(port)           LM4GPIOREG(port, 0x520)
-#define LM4_GPIO_CR(port)             LM4GPIOREG(port, 0x524)
-#define LM4_GPIO_AMSEL(port)          LM4GPIOREG(port, 0x528)
-#define LM4_GPIO_PCTL(port)           LM4GPIOREG(port, 0x52c)
-
-/* Chip-independent aliases for port base addresses */
-#define GPIO_A LM4_GPIO_A
-#define GPIO_B LM4_GPIO_B
-#define GPIO_C LM4_GPIO_C
-#define GPIO_D LM4_GPIO_D
-#define GPIO_E LM4_GPIO_E
-#define GPIO_F LM4_GPIO_F
-#define GPIO_G LM4_GPIO_G
-#define GPIO_H LM4_GPIO_H
-#define GPIO_J LM4_GPIO_J
-#define GPIO_K LM4_GPIO_K
-#define GPIO_L LM4_GPIO_L
-#define GPIO_M LM4_GPIO_M
-#define GPIO_N LM4_GPIO_N
-#define GPIO_P LM4_GPIO_P
-#define GPIO_Q LM4_GPIO_Q
-
-#define UNIMPLEMENTED_GPIO_BANK GPIO_A
-
-/* Value to write to LM4_GPIO_LOCK to unlock writes */
-#define LM4_GPIO_LOCK_UNLOCK          0x4c4f434b
-
-/* I2C */
-#define LM4_I2C0_BASE                 0x40020000
-#define LM4_I2C1_BASE                 0x40021000
-#define LM4_I2C2_BASE                 0x40022000
-#define LM4_I2C3_BASE                 0x40023000
-#define LM4_I2C4_BASE                 0x400c0000
-#define LM4_I2C5_BASE                 0x400c1000
-#define LM4_I2C_BASESEP               0x00001000
-/* I2C base address by port.  Compiles to a constant in gcc if port
-   and offset are constant. */
-static inline int lm4_i2c_addr(int port, int offset)
-{
-	return offset + (port < 4 ?
-			 LM4_I2C0_BASE + LM4_I2C_BASESEP * port :
-			 LM4_I2C4_BASE + LM4_I2C_BASESEP * (port - 4));
-}
-#define LM4I2CREG(port, offset)       REG32(lm4_i2c_addr(port, offset))
-#define LM4_I2C_MSA(port)             LM4I2CREG(port, 0x000)
-#define LM4_I2C_MCS(port)             LM4I2CREG(port, 0x004)
-#define LM4_I2C_MDR(port)             LM4I2CREG(port, 0x008)
-#define LM4_I2C_MTPR(port)            LM4I2CREG(port, 0x00c)
-#define LM4_I2C_MIMR(port)            LM4I2CREG(port, 0x010)
-#define LM4_I2C_MRIS(port)            LM4I2CREG(port, 0x014)
-#define LM4_I2C_MMIS(port)            LM4I2CREG(port, 0x018)
-#define LM4_I2C_MICR(port)            LM4I2CREG(port, 0x01c)
-#define LM4_I2C_MCR(port)             LM4I2CREG(port, 0x020)
-#define LM4_I2C_MCLKOCNT(port)        LM4I2CREG(port, 0x024)
-#define LM4_I2C_MBMON(port)           LM4I2CREG(port, 0x02c)
-
-
-/* Timers */
-/* Timers 0-5 are 16/32 bit */
-#define LM4_TIMER0_BASE                 0x40030000
-#define LM4_TIMER1_BASE                 0x40031000
-#define LM4_TIMER2_BASE                 0x40032000
-#define LM4_TIMER3_BASE                 0x40033000
-#define LM4_TIMER4_BASE                 0x40034000
-#define LM4_TIMER5_BASE                 0x40035000
-/* Timers 6-11 are 32/64 bit */
-#define LM4_TIMERW0_BASE                0x40036000
-#define LM4_TIMERW1_BASE                0x40037000
-#define LM4_TIMERW2_BASE                0x4004c000
-#define LM4_TIMERW3_BASE                0x4004d000
-#define LM4_TIMERW4_BASE                0x4004e000
-#define LM4_TIMERW5_BASE                0x4004f000
-#define LM4_TIMER_SEP                   0x00001000
-static inline int lm4_timer_addr(int timer, int offset)
-{
-	if (timer < 8)
-		return offset + LM4_TIMER0_BASE + LM4_TIMER_SEP * timer;
-	else
-		return offset + LM4_TIMERW2_BASE + LM4_TIMER_SEP * (timer - 8);
-}
-#define LM4TIMERREG(timer, offset)      REG32(lm4_timer_addr(timer, offset))
-#define LM4_TIMER_CFG(tmr)              LM4TIMERREG(tmr, 0x00)
-#define LM4_TIMER_TAMR(tmr)             LM4TIMERREG(tmr, 0x04)
-#define LM4_TIMER_TBMR(tmr)             LM4TIMERREG(tmr, 0x08)
-#define LM4_TIMER_CTL(tmr)              LM4TIMERREG(tmr, 0x0c)
-#define LM4_TIMER_SYNC(tmr)             LM4TIMERREG(tmr, 0x10)
-#define LM4_TIMER_IMR(tmr)              LM4TIMERREG(tmr, 0x18)
-#define LM4_TIMER_RIS(tmr)              LM4TIMERREG(tmr, 0x1c)
-#define LM4_TIMER_MIS(tmr)              LM4TIMERREG(tmr, 0x20)
-#define LM4_TIMER_ICR(tmr)              LM4TIMERREG(tmr, 0x24)
-#define LM4_TIMER_TAILR(tmr)            LM4TIMERREG(tmr, 0x28)
-#define LM4_TIMER_TBILR(tmr)            LM4TIMERREG(tmr, 0x2c)
-#define LM4_TIMER_TAMATCHR(tmr)         LM4TIMERREG(tmr, 0x30)
-#define LM4_TIMER_TBMATCHR(tmr)         LM4TIMERREG(tmr, 0x34)
-#define LM4_TIMER_TAPR(tmr)             LM4TIMERREG(tmr, 0x38)
-#define LM4_TIMER_TBPR(tmr)             LM4TIMERREG(tmr, 0x3c)
-#define LM4_TIMER_TAPMR(tmr)            LM4TIMERREG(tmr, 0x40)
-#define LM4_TIMER_TBPMR(tmr)            LM4TIMERREG(tmr, 0x44)
-#define LM4_TIMER_TAR(tmr)              LM4TIMERREG(tmr, 0x48)
-#define LM4_TIMER_TBR(tmr)              LM4TIMERREG(tmr, 0x4c)
-#define LM4_TIMER_TAV(tmr)              LM4TIMERREG(tmr, 0x50)
-#define LM4_TIMER_TBV(tmr)              LM4TIMERREG(tmr, 0x54)
-#define LM4_TIMER_RTCPD(tmr)            LM4TIMERREG(tmr, 0x58)
-#define LM4_TIMER_TAPS(tmr)             LM4TIMERREG(tmr, 0x5c)
-#define LM4_TIMER_TBPS(tmr)             LM4TIMERREG(tmr, 0x60)
-#define LM4_TIMER_TAPV(tmr)             LM4TIMERREG(tmr, 0x64)
-#define LM4_TIMER_TBPV(tmr)             LM4TIMERREG(tmr, 0x68)
-
-#define LM4_SYSTICK_CTRL                REG32(0xe000e010)
-#define LM4_SYSTICK_RELOAD              REG32(0xe000e014)
-#define LM4_SYSTICK_CURRENT             REG32(0xe000e018)
-
-/* Watchdogs */
-#define LM4_WATCHDOG0_BASE              0x40000000
-#define LM4_WATCHDOG1_BASE              0x40001000
-static inline int lm4_watchdog_addr(int num, int offset)
-{
-	return offset + (num ? LM4_WATCHDOG1_BASE : LM4_WATCHDOG0_BASE);
-}
-#define LM4WDTREG(num, offset)		REG32(lm4_watchdog_addr(num, offset))
-#define LM4_WATCHDOG_LOAD(n)            LM4WDTREG(n, 0x000)
-#define LM4_WATCHDOG_VALUE(n)           LM4WDTREG(n, 0x004)
-#define LM4_WATCHDOG_CTL(n)             LM4WDTREG(n, 0x008)
-#define LM4_WATCHDOG_ICR(n)             LM4WDTREG(n, 0x00c)
-#define LM4_WATCHDOG_RIS(n)             LM4WDTREG(n, 0x010)
-#define LM4_WATCHDOG_TEST(n)            LM4WDTREG(n, 0x418)
-#define LM4_WATCHDOG_LOCK(n)            LM4WDTREG(n, 0xc00)
-
-#define LM4_TEST_MODE_ENABLED		REG32(0x400fdff0)
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/lm4/spi.c b/chip/lm4/spi.c
deleted file mode 100644
index 629e306af7..0000000000
--- a/chip/lm4/spi.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI module for Chrome EC */
-
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	if (enable) {
-		gpio_config_module(MODULE_SPI, 1);
-		/*
-		 * Don't use the SSI0 frame output.
-		 * CS# is a GPIO so we can keep it low during an entire
-		 * transaction.
-		 */
-		gpio_set_flags(spi_device->gpio_cs, GPIO_OUTPUT);
-		gpio_set_level(spi_device->gpio_cs, 1);
-
-		/* Enable SSI port */
-		LM4_SSI_CR1(0) |= 0x02;
-	} else {
-		/* Disable SSI port */
-		LM4_SSI_CR1(0) &= ~0x02;
-
-		/* Make sure CS# is deselected */
-		gpio_set_level(spi_device->gpio_cs, 1);
-		gpio_set_flags(spi_device->gpio_cs[i], GPIO_ODR_HIGH);
-
-		gpio_config_module(MODULE_SPI, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int totallen = txlen + rxlen;
-	int txcount = 0, rxcount = 0;
-	static struct mutex spi_mutex;
-	volatile uint32_t unused  __attribute__((unused));
-
-	mutex_lock(&spi_mutex);
-	/* Empty the receive FIFO */
-	while (LM4_SSI_SR(0) & LM4_SSI_SR_RNE)
-		unused = LM4_SSI_DR(0);
-
-	/* Start transaction.  Need to do this explicitly because the LM4
-	 * SSI controller pulses its frame select every byte, and the EEPROM
-	 * wants the chip select held low during the entire transaction. */
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	while (rxcount < totallen) {
-		/* Handle received bytes if any.  We just checked rxcount <
-		 * totallen, so we don't need to worry about overflowing the
-		 * receive buffer. */
-		if (LM4_SSI_SR(0) & LM4_SSI_SR_RNE) {
-			if (rxcount < txlen) {
-				/* Throw away bytes received while we were
-				   transmitting */
-				unused = LM4_SSI_DR(0);
-			} else
-				*(rxdata++) = LM4_SSI_DR(0);
-			rxcount++;
-		}
-
-		/* Transmit another byte if needed */
-		if ((LM4_SSI_SR(0) & LM4_SSI_SR_TNF) && txcount < totallen) {
-			if (txcount < txlen)
-				LM4_SSI_DR(0) = *(txdata++);
-			else {
-				/* Clock out unused byte so we can clock in the
-				 * response byte */
-				LM4_SSI_DR(0) = 0;
-			}
-			txcount++;
-		}
-	}
-
-	/* End transaction */
-	gpio_set_level(spi_device->gpio_cs, 1);
-	mutex_unlock(&spi_mutex);
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static int spi_init(void)
-{
-	/* Enable the SPI module in run and sleep modes */
-	clock_enable_peripheral(CGC_OFFSET_SSI, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	LM4_SSI_CR1(0) = 0;       /* Disable SSI */
-	LM4_SSI_CR0(0) = 0x0007;  /* SCR=0, SPH=0, SPO=0, FRF=SPI, 8-bit */
-
-	/* Use PIOSC for clock.  This limits us to 8MHz (PIOSC/2), but is
-	 * simpler to configure and we don't need to worry about clock
-	 * frequency changing when the PLL is disabled.  If we really start
-	 * using this, might be worth using the system clock and handling
-	 * frequency change (like we do with PECI) so we can go faster. */
-	LM4_SSI_CC(0) = 1;
-	/* SSICLK = PIOSC / (CPSDVSR * (1 + SCR)
-	 *        = 16 MHz / (2 * (1 + 0))
-	 *        = 8 MHz */
-	LM4_SSI_CPSR(0) = 2;
-
-	/* Ensure the SPI port is disabled.  This keeps us from interfering
-	 * with the main chipset when we're not explicitly using the SPI
-	 * bus. */
-	spi_enable(SPI_FLASH_DEVICE, 0);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int printrx(const char *desc, const uint8_t *txdata, int txlen,
-		   int rxlen)
-{
-	uint8_t rxdata[32];
-	int rv;
-	int i;
-
-	rv = spi_transaction(SPI_FLASH_DEVICE, txdata, txlen, rxdata, rxlen);
-	if (rv)
-		return rv;
-
-	ccprintf("%-12s:", desc);
-	for (i = 0; i < rxlen; i++)
-		ccprintf(" 0x%02x", rxdata[i]);
-	ccputs("\n");
-	return EC_SUCCESS;
-}
-
-
-static int command_spirom(int argc, char **argv)
-{
-	uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00};
-	uint8_t txjedec[] = {0x9f};
-	uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00};
-	uint8_t txsr1[] = {0x05};
-	uint8_t txsr2[] = {0x35};
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	printrx("Man/Dev ID", txmandev, sizeof(txmandev), 2);
-	printrx("JEDEC ID", txjedec, sizeof(txjedec), 3);
-	printrx("Unique ID", txunique, sizeof(txunique), 8);
-	printrx("Status reg 1", txsr1, sizeof(txsr1), 1);
-	printrx("Status reg 2", txsr2, sizeof(txsr2), 1);
-
-	spi_enable(SPI_FLASH_DEVICE, 0);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(spirom, command_spirom,
-			NULL,
-			"Test reading SPI EEPROM");
diff --git a/chip/lm4/system.c b/chip/lm4/system.c
deleted file mode 100644
index 56bd1a82fd..0000000000
--- a/chip/lm4/system.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : LM4 hardware specific implementation */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "host_command.h"
-#include "panic.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Indices for hibernate data registers */
-enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD,           /* General-purpose scratchpad */
-	HIBDATA_INDEX_WAKE,                 /* Wake reasons for hibernate */
-	HIBDATA_INDEX_SAVED_RESET_FLAGS,    /* Saved reset flags */
-#ifdef CONFIG_SOFTWARE_PANIC
-	HIBDATA_INDEX_SAVED_PANIC_REASON,   /* Saved panic reason */
-	HIBDATA_INDEX_SAVED_PANIC_INFO,     /* Saved panic data */
-	HIBDATA_INDEX_SAVED_PANIC_EXCEPTION,/* Saved panic exception code */
-	HIBDATA_INDEX_SAVED_PANIC_FLAGS,    /* Saved panic flags */
-#endif
-};
-
-/* Flags for HIBDATA_INDEX_WAKE */
-#define HIBDATA_WAKE_RTC        BIT(0)  /* RTC alarm */
-#define HIBDATA_WAKE_HARD_RESET BIT(1)  /* Hard reset via short RTC alarm */
-#define HIBDATA_WAKE_PIN        BIT(2)  /* Wake pin */
-
-/*
- * Time to hibernate to trigger a power-on reset.  50 ms is sufficient for the
- * EC itself, but we need a longer delay to ensure the rest of the components
- * on the same power rail are reset and 5VALW has dropped.
- */
-#define HIB_RESET_USEC 1000000
-
-/*
- * Convert between microseconds and the hibernation module RTC subsecond
- * register which has 15-bit resolution. Divide down both numerator and
- * denominator to avoid integer overflow while keeping the math accurate.
- */
-#define HIB_RTC_USEC_TO_SUBSEC(us) ((us) * (32768/64) / (1000000/64))
-#define HIB_RTC_SUBSEC_TO_USEC(ss) ((ss) * (1000000/64) / (32768/64))
-
-/**
- * Wait for a write to commit to a hibernate register.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-static int wait_for_hibctl_wc(void)
-{
-	int i;
-
-	/* Wait for write-capable */
-	for (i = 0; i < 1000000; i++) {
-		if (LM4_HIBERNATE_HIBCTL & LM4_HIBCTL_WRC)
-			return EC_SUCCESS;
-	}
-	return EC_ERROR_TIMEOUT;
-}
-
-/**
- * Read hibernate register at specified index.
- *
- * @return The value of the register or 0 if invalid index.
- */
-static uint32_t hibdata_read(enum hibdata_index index)
-{
-	if (index < 0 || index >= LM4_HIBERNATE_HIBDATA_ENTRIES)
-		return 0;
-
-	return LM4_HIBERNATE_HIBDATA[index];
-}
-
-/**
- * Write hibernate register at specified index.
- *
- * @return nonzero if error.
- */
-static int hibdata_write(enum hibdata_index index, uint32_t value)
-{
-	int rv;
-
-	if (index < 0 || index >= LM4_HIBERNATE_HIBDATA_ENTRIES)
-		return EC_ERROR_INVAL;
-
-	/* Wait for ok-to-write */
-	rv = wait_for_hibctl_wc();
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Write register */
-	LM4_HIBERNATE_HIBDATA[index] = value;
-
-	/* Wait for write-complete */
-	return wait_for_hibctl_wc();
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return hibdata_read(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	hibdata_write(HIBDATA_INDEX_SAVED_RESET_FLAGS, flags);
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t hib_status = LM4_HIBERNATE_HIBRIS;
-	uint32_t raw_reset_cause = LM4_SYSTEM_RESC;
-	uint32_t hib_wake_flags = hibdata_read(HIBDATA_INDEX_WAKE);
-	uint32_t flags = 0;
-
-	/* Clear the reset causes now that we've read them */
-	LM4_SYSTEM_RESC = 0;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = hib_status;
-	hibdata_write(HIBDATA_INDEX_WAKE, 0);
-
-	if (raw_reset_cause & 0x02) {
-		/*
-		 * Full power-on reset of chip.  This resets the flash
-		 * protection registers to their permanently-stored values.
-		 * Note that this is also triggered by hibernation, because
-		 * that de-powers the chip.
-		 */
-		flags |= EC_RESET_FLAG_POWER_ON;
-	} else if (!flags && (raw_reset_cause & 0x01)) {
-		/*
-		 * LM4 signals the reset pin in RESC for all power-on resets,
-		 * even though the external pin wasn't asserted.  Make setting
-		 * this flag mutually-exclusive with power on flag, so we can
-		 * use it to indicate a keyboard-triggered reset.
-		 */
-		flags |= EC_RESET_FLAG_RESET_PIN;
-	}
-
-	if (raw_reset_cause & 0x04)
-		flags |= EC_RESET_FLAG_BROWNOUT;
-
-	if (raw_reset_cause & 0x10)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (raw_reset_cause & 0x28) {
-		/* Watchdog timer 0 or 1 */
-		flags |= EC_RESET_FLAG_WATCHDOG;
-	}
-
-	/* Handle other raw reset causes */
-	if (raw_reset_cause && !flags)
-		flags |= EC_RESET_FLAG_OTHER;
-
-
-	if ((hib_status & 0x09) &&
-	    (hib_wake_flags & HIBDATA_WAKE_HARD_RESET)) {
-		/* Hibernation caused by software-triggered hard reset */
-		flags |= EC_RESET_FLAG_HARD;
-
-		/* Consume the hibernate reasons so we don't see them below */
-		hib_status &= ~0x09;
-	}
-
-	if ((hib_status & 0x01) && (hib_wake_flags & HIBDATA_WAKE_RTC))
-		flags |= EC_RESET_FLAG_RTC_ALARM;
-
-	if ((hib_status & 0x08) && (hib_wake_flags & HIBDATA_WAKE_PIN))
-		flags |= EC_RESET_FLAG_WAKE_PIN;
-
-	if (hib_status & 0x04)
-		flags |= EC_RESET_FLAG_LOW_BATTERY;
-
-	/* Restore then clear saved reset flags */
-	flags |= chip_read_reset_flags();
-	chip_save_reset_flags(0);
-
-	system_set_reset_flags(flags);
-}
-
-/*
- * A3 and earlier chip stepping has a problem accessing flash during shutdown.
- * To work around that, we jump to RAM before hibernating.  This function must
- * live in RAM.  It must be called with interrupts disabled, cannot call other
- * functions, and can't be declared static (or else the compiler optimizes it
- * into the main hibernate function.
- */
-void  __attribute__((noinline)) __attribute__((section(".iram.text")))
-__enter_hibernate(int hibctl)
-{
-	LM4_HIBERNATE_HIBCTL = hibctl;
-	while (1)
-		;
-}
-
-/**
- * Read the real-time clock.
- *
- * @param ss_ptr       Destination for sub-seconds value, if not null.
- *
- * @return the real-time clock seconds value.
- */
-uint32_t system_get_rtc_sec_subsec(uint32_t *ss_ptr)
-{
-	uint32_t rtc, rtc2;
-	uint32_t rtcss, rtcss2;
-
-	/*
-	 * The hibernate module isn't synchronized, so need to read repeatedly
-	 * to guarantee a valid read.
-	 */
-	do {
-		rtc = LM4_HIBERNATE_HIBRTCC;
-		rtcss = LM4_HIBERNATE_HIBRTCSS & 0x7fff;
-		rtcss2 = LM4_HIBERNATE_HIBRTCSS & 0x7fff;
-		rtc2 = LM4_HIBERNATE_HIBRTCC;
-	} while (rtc != rtc2 || rtcss != rtcss2);
-
-	if (ss_ptr)
-		*ss_ptr = rtcss;
-
-	return rtc;
-}
-
-timestamp_t system_get_rtc(void)
-{
-	uint32_t rtc, rtc_ss;
-	timestamp_t time;
-
-	rtc = system_get_rtc_sec_subsec(&rtc_ss);
-
-	time.val = ((uint64_t)rtc) * SECOND + HIB_RTC_SUBSEC_TO_USEC(rtc_ss);
-	return time;
-}
-
-/**
- * Set the real-time clock.
- *
- * @param seconds	New clock value.
- */
-void system_set_rtc(uint32_t seconds)
-{
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCLD = seconds;
-	wait_for_hibctl_wc();
-}
-
-/**
- * Set the hibernate RTC match time at a given time from now
- *
- * @param seconds      Number of seconds from now for RTC match
- * @param microseconds Number of microseconds from now for RTC match
- */
-static void set_hibernate_rtc_match_time(uint32_t seconds,
-					uint32_t microseconds)
-{
-	uint32_t rtc, rtcss;
-
-	/*
-	 * Make sure that the requested delay is not less then the
-	 * amount of time it takes to set the RTC match registers,
-	 * otherwise, the match event could be missed.
-	 */
-	if (seconds == 0 && microseconds < HIB_SET_RTC_MATCH_DELAY_USEC)
-		microseconds = HIB_SET_RTC_MATCH_DELAY_USEC;
-
-	/* Calculate the wake match */
-	rtc = system_get_rtc_sec_subsec(&rtcss) + seconds;
-	rtcss += HIB_RTC_USEC_TO_SUBSEC(microseconds);
-	if (rtcss > 0x7fff) {
-		rtc += rtcss >> 15;
-		rtcss &= 0x7fff;
-	}
-
-	/* Set RTC alarm match */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCM0 = rtc;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCSS = rtcss << 16;
-	wait_for_hibctl_wc();
-}
-
-/**
- * Use hibernate module to set up an RTC interrupt at a given
- * time from now
- *
- * @param seconds      Number of seconds before RTC interrupt
- * @param microseconds Number of microseconds before RTC interrupt
- */
-void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	/* Clear pending interrupt */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = LM4_HIBERNATE_HIBRIS;
-
-	/* Set match time */
-	set_hibernate_rtc_match_time(seconds, microseconds);
-
-	/* Enable RTC interrupt on match */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIM = 1;
-
-	/*
-	 * Wait for the write to commit.  This ensures that the RTC interrupt
-	 * actually gets enabled.  This is important if we're about to switch
-	 * the system to the 30 kHz oscillator, which might prevent the write
-	 * from committing.
-	 */
-	wait_for_hibctl_wc();
-}
-
-/**
- * Disable and clear the RTC interrupt.
- */
-void system_reset_rtc_alarm(void)
-{
-	/* Disable hibernate interrupts */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIM = 0;
-
-	/* Clear interrupts */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = LM4_HIBERNATE_HIBRIS;
-}
-
-/**
- * Hibernate module interrupt
- */
-void __hibernate_irq(void)
-{
-	system_reset_rtc_alarm();
-}
-DECLARE_IRQ(LM4_IRQ_HIBERNATE, __hibernate_irq, 1);
-
-/**
- * Enable hibernate interrupt
- */
-void system_enable_hib_interrupt(void)
-{
-	task_enable_irq(LM4_IRQ_HIBERNATE);
-}
-
-/**
- * Internal hibernate function.
- *
- * @param seconds      Number of seconds to sleep before RTC alarm
- * @param microseconds Number of microseconds to sleep before RTC alarm
- * @param flags        Additional hibernate wake flags
- */
-static void hibernate(uint32_t seconds, uint32_t microseconds, uint32_t flags)
-{
-	uint32_t hibctl;
-
-	/* Set up wake reasons and hibernate flags */
-	hibctl = LM4_HIBERNATE_HIBCTL | LM4_HIBCTL_PINWEN;
-
-	if (flags & HIBDATA_WAKE_PIN)
-		hibctl |= LM4_HIBCTL_PINWEN;
-	else
-		hibctl &= ~LM4_HIBCTL_PINWEN;
-
-	if (seconds || microseconds) {
-		hibctl |= LM4_HIBCTL_RTCWEN;
-		flags |= HIBDATA_WAKE_RTC;
-
-		set_hibernate_rtc_match_time(seconds, microseconds);
-
-		/* Enable RTC interrupt on match */
-		wait_for_hibctl_wc();
-		LM4_HIBERNATE_HIBIM = 1;
-	} else {
-		hibctl &= ~LM4_HIBCTL_RTCWEN;
-	}
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBCTL = hibctl;
-
-	/* Clear pending interrupt */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = LM4_HIBERNATE_HIBRIS;
-
-	/* Store hibernate flags */
-	hibdata_write(HIBDATA_INDEX_WAKE, flags);
-
-	__enter_hibernate(hibctl | LM4_HIBCTL_HIBREQ);
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* Flush console before hibernating */
-	cflush();
-	hibernate(seconds, microseconds, HIBDATA_WAKE_PIN);
-}
-
-void chip_pre_init(void)
-{
-	/* Enable clocks to GPIO block C in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_GPIO, 0x0004, CGC_MODE_ALL);
-
-	/*
-	 * Ensure PC0:3 are set to JTAG function.  They should be set this way
-	 * on a cold boot, but on a warm reboot a previous misbehaving image
-	 * could have set them differently.
-	 */
-	if (((LM4_GPIO_PCTL(LM4_GPIO_C) & 0x0000ffff) == 0x00001111) &&
-	    ((LM4_GPIO_AFSEL(LM4_GPIO_C) & 0x0f) == 0x0f) &&
-	    ((LM4_GPIO_DEN(LM4_GPIO_C) & 0x0f) == 0x0f) &&
-	    ((LM4_GPIO_PUR(LM4_GPIO_C) & 0x0f) == 0x0f))
-		return;  /* Already properly configured */
-
-	/* Unlock commit register for JTAG pins */
-	LM4_GPIO_LOCK(LM4_GPIO_C) = LM4_GPIO_LOCK_UNLOCK;
-	LM4_GPIO_CR(LM4_GPIO_C) |= 0x0f;
-
-	/* Reset JTAG pins */
-	LM4_GPIO_PCTL(LM4_GPIO_C) =
-		(LM4_GPIO_PCTL(LM4_GPIO_C) & 0xffff0000) | 0x00001111;
-	LM4_GPIO_AFSEL(LM4_GPIO_C) |= 0x0f;
-	LM4_GPIO_DEN(LM4_GPIO_C) |= 0x0f;
-	LM4_GPIO_PUR(LM4_GPIO_C) |= 0x0f;
-
-	/* Set interrupt on either edge of the JTAG signals */
-	LM4_GPIO_IS(LM4_GPIO_C) &= ~0x0f;
-	LM4_GPIO_IBE(LM4_GPIO_C) |= 0x0f;
-
-	/* Re-lock commit register */
-	LM4_GPIO_CR(LM4_GPIO_C) &= ~0x0f;
-	LM4_GPIO_LOCK(LM4_GPIO_C) = 0;
-}
-
-void system_pre_init(void)
-{
-	uint32_t hibctl;
-#ifdef CONFIG_SOFTWARE_PANIC
-	uint32_t reason, info;
-	uint8_t exception, panic_flags;
-#endif
-
-	/*
-	 * Enable clocks to the hibernation module in run, sleep,
-	 * and deep sleep modes.
-	 */
-	clock_enable_peripheral(CGC_OFFSET_HIB, 0x1, CGC_MODE_ALL);
-
-	/*
-	 * Enable the hibernation oscillator, if it's not already enabled.
-	 * This should only need setting if the EC completely lost power (for
-	 * example, the battery was pulled).
-	 */
-	if (!(LM4_HIBERNATE_HIBCTL & LM4_HIBCTL_CLK32EN)) {
-		int i;
-
-		/* Enable clock to hibernate module */
-		wait_for_hibctl_wc();
-		LM4_HIBERNATE_HIBCTL |= LM4_HIBCTL_CLK32EN;
-
-		/* Wait for write-complete */
-		for (i = 0; i < 1000000; i++) {
-			if (LM4_HIBERNATE_HIBRIS & 0x10)
-				break;
-		}
-
-		/* Enable and reset RTC */
-		wait_for_hibctl_wc();
-		LM4_HIBERNATE_HIBCTL |= LM4_HIBCTL_RTCEN;
-		system_set_rtc(0);
-
-		/* Clear all hibernate data entries */
-		for (i = 0; i < LM4_HIBERNATE_HIBDATA_ENTRIES; i++)
-			hibdata_write(i, 0);
-	}
-
-	/*
-	 * Set wake reasons to RTC match and WAKE pin by default.
-	 * Before going in to hibernate, these may change.
-	 */
-	hibctl = LM4_HIBERNATE_HIBCTL;
-	hibctl |= LM4_HIBCTL_RTCWEN;
-	hibctl |= LM4_HIBCTL_PINWEN;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBCTL = hibctl;
-
-	/*
-	 * Initialize registers after reset to work around LM4 chip errata
-	 * (still present in A3 chip stepping).
-	 */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCT = 0x7fff;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIM = 0;
-
-	check_reset_cause();
-
-#ifdef CONFIG_SOFTWARE_PANIC
-	/* Restore then clear saved panic reason */
-	reason = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_REASON);
-	info = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_INFO);
-	exception = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_EXCEPTION);
-	panic_flags = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_FLAGS);
-
-	if (reason || info || exception) {
-		panic_set_reason(reason, info, exception);
-		panic_get_data()->flags = panic_flags;
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_REASON, 0);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_INFO, 0);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_EXCEPTION, 0);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_FLAGS, 0);
-	}
-#endif
-
-	/* Initialize bootcfg if needed */
-	if (LM4_SYSTEM_BOOTCFG != CONFIG_BOOTCFG_VALUE) {
-		/* read-modify-write */
-		LM4_FLASH_FMD = (LM4_SYSTEM_BOOTCFG_MASK & LM4_SYSTEM_BOOTCFG)
-			| (~LM4_SYSTEM_BOOTCFG_MASK & CONFIG_BOOTCFG_VALUE);
-		LM4_FLASH_FMA = 0x75100000;
-		LM4_FLASH_FMC = 0xa4420008;  /* WRKEY | COMT */
-		while (LM4_FLASH_FMC & 0x08)
-			;
-	}
-
-	/* Brown-outs should trigger a reset */
-	LM4_SYSTEM_PBORCTL |= 0x02;
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	chip_save_reset_flags(save_flags);
-
-	if (flags & SYSTEM_RESET_HARD) {
-#ifdef CONFIG_SOFTWARE_PANIC
-		uint32_t reason, info;
-		uint8_t exception, panic_flags;
-
-		panic_flags = panic_get_data()->flags;
-
-		/* Panic data will be wiped by hard reset, so save it */
-		panic_get_reason(&reason, &info, &exception);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_REASON, reason);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_INFO, info);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_EXCEPTION, exception);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_FLAGS, panic_flags);
-#endif
-
-		/*
-		 * Bounce through hibernate to trigger a hard reboot.  Do
-		 * not wake on wake pin, since we need the full duration.
-		 */
-		hibernate(0, HIB_RESET_USEC, HIBDATA_WAKE_HARD_RESET);
-	} else
-		CPU_NVIC_APINT = 0x05fa0004;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	return hibdata_write(HIBDATA_INDEX_SCRATCHPAD, value);
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = hibdata_read(HIBDATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "ti";
-}
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_id_string(void)
-{
-	static char str[15] = "Unknown-";
-	char *p = str + 8;
-	uint32_t did = LM4_SYSTEM_DID1 >> 16;
-
-	if (*p)
-		return (const char *)str;
-
-	*p = to_hex(did >> 12);
-	*(p + 1) = to_hex((did >> 8) & 0xf);
-	*(p + 2) = to_hex((did >> 4) & 0xf);
-	*(p + 3) = to_hex(did & 0xf);
-	*(p + 4) = '\0';
-
-	return (const char *)str;
-}
-
-const char *system_get_raw_chip_name(void)
-{
-	switch ((LM4_SYSTEM_DID1 & 0xffff0000) >> 16) {
-	case 0x10de:
-		return "tm4e1g31h6zrb";
-	case 0x10e2:
-		return "lm4fsxhh5bb";
-	case 0x10e3:
-		return "lm4fs232h5bb";
-	case 0x10e4:
-		return "lm4fs99h5bb";
-	case 0x10e6:
-		return "lm4fs1ah5bb";
-	case 0x10ea:
-		return "lm4fs1gh5bb";
-	default:
-		return system_get_chip_id_string();
-	}
-}
-
-const char *system_get_chip_name(void)
-{
-	const char *postfix = "-tm"; /* test mode */
-	static char str[20];
-	const char *raw_chip_name = system_get_raw_chip_name();
-	char *p = str;
-
-	if (LM4_TEST_MODE_ENABLED) {
-		/* Debug mode is enabled. Postfix chip name. */
-		while (*raw_chip_name)
-			*(p++) = *(raw_chip_name++);
-		while (*postfix)
-			*(p++) = *(postfix++);
-		*p = '\0';
-		return (const char *)str;
-	} else {
-		return raw_chip_name;
-	}
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char rev[3];
-
-	/* Extract the major[15:8] and minor[7:0] revisions. */
-	rev[0] = 'A' + ((LM4_SYSTEM_DID0 >> 8) & 0xff);
-	rev[1] = '0' + (LM4_SYSTEM_DID0 & 0xff);
-	rev[2] = 0;
-
-	return rev;
-}
-
-/*****************************************************************************/
-/* Console commands */
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t rtc;
-	uint32_t rtcss;
-
-	rtc = system_get_rtc_sec_subsec(&rtcss);
-	cprintf(ch, "RTC: 0x%08x.%04x (%d.%06d s)\n",
-		 rtc, rtcss, rtc, HIB_RTC_SUBSEC_TO_USEC(rtcss));
-}
-
-#ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
-{
-	if (argc == 3 && !strcasecmp(argv[1], "set")) {
-		char *e;
-		uint32_t t = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		system_set_rtc(t);
-	} else if (argc > 1) {
-		return EC_ERROR_INVAL;
-	}
-
-	print_system_rtc(CC_COMMAND);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-			"[set <seconds>]",
-			"Get/set real-time clock");
-
-#ifdef CONFIG_CMD_RTC_ALARM
-/**
- * Test the RTC alarm by setting an interrupt on RTC match.
- */
-static int command_rtc_alarm_test(int argc, char **argv)
-{
-	int s = 1, us = 0;
-	char *e;
-
-	ccprintf("Setting RTC alarm\n");
-	system_enable_hib_interrupt();
-
-	if (argc > 1) {
-		s = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-	}
-	if (argc > 2) {
-		us = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-	}
-
-	system_set_rtc_alarm(s, us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-			"[seconds [microseconds]]",
-			"Test alarm");
-#endif /* CONFIG_CMD_RTC_ALARM */
-#endif /* CONFIG_CMD_RTC */
-
-/*****************************************************************************/
-/* Host commands */
-
-#ifdef CONFIG_HOSTCMD_RTC
-static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = system_get_rtc_sec_subsec(NULL);
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		     system_rtc_get_value,
-		     EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	system_set_rtc(p->time);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		     system_rtc_set_value,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_RTC */
diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c
deleted file mode 100644
index 7ccea9eb75..0000000000
--- a/chip/lm4/uart.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "lpc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#ifdef CONFIG_UART_HOST
-#define IRQ_UART_HOST CONCAT2(LM4_IRQ_UART, CONFIG_UART_HOST)
-#endif
-
-static int init_done;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (LM4_UART_IM(0) & 0x20)
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	LM4_UART_IM(0) |= 0x20;
-	task_trigger_irq(LM4_IRQ_UART0);
-}
-
-void uart_tx_stop(void)
-{
-	LM4_UART_IM(0) &= ~0x20;
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/* Wait for transmit FIFO empty */
-	while (!(LM4_UART_FR(0) & 0x80))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	return !(LM4_UART_FR(0) & 0x20);
-}
-
-int uart_tx_in_progress(void)
-{
-	/* Transmit is in progress if the TX busy bit is set. */
-	return LM4_UART_FR(0) & 0x08;
-}
-
-int uart_rx_available(void)
-{
-	return !(LM4_UART_FR(0) & 0x10);
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	LM4_UART_DR(0) = c;
-}
-
-int uart_read_char(void)
-{
-	return LM4_UART_DR(0);
-}
-
-static void uart_clear_rx_fifo(int channel)
-{
-	int scratch __attribute__ ((unused));
-	while (!(LM4_UART_FR(channel) & 0x10))
-		scratch = LM4_UART_DR(channel);
-}
-
-/**
- * Interrupt handler for UART0
- */
-void uart_ec_interrupt(void)
-{
-	/* Clear transmit and receive interrupt status */
-	LM4_UART_ICR(0) = 0x70;
-
-
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-}
-DECLARE_IRQ(LM4_IRQ_UART0, uart_ec_interrupt, 1);
-
-#ifdef CONFIG_UART_HOST
-
-/**
- * Interrupt handler for Host UART
- */
-void uart_host_interrupt(void)
-{
-	/* Clear transmit and receive interrupt status */
-	LM4_UART_ICR(CONFIG_UART_HOST) = 0x70;
-
-#ifdef CONFIG_HOSTCMD_LPC
-	/*
-	 * If we have space in our FIFO and a character is pending in LPC,
-	 * handle that character.
-	 */
-	if (!(LM4_UART_FR(CONFIG_UART_HOST) & 0x20) && lpc_comx_has_char()) {
-		/* Copy the next byte then disable transmit interrupt */
-		LM4_UART_DR(CONFIG_UART_HOST) = lpc_comx_get_char();
-		LM4_UART_IM(CONFIG_UART_HOST) &= ~0x20;
-	}
-
-	/*
-	 * Handle received character.  There is no flow control on input;
-	 * received characters are blindly forwarded to LPC.  This is ok
-	 * because LPC is much faster than UART, and we don't have flow control
-	 * on the UART receive-side either.
-	 */
-	if (!(LM4_UART_FR(CONFIG_UART_HOST) & 0x10))
-		lpc_comx_put_char(LM4_UART_DR(CONFIG_UART_HOST));
-#endif
-}
-/* Must be same prio as LPC interrupt handler so they don't preempt */
-DECLARE_IRQ(IRQ_UART_HOST, uart_host_interrupt, 2);
-
-#endif /* CONFIG_UART_HOST */
-
-static void uart_config(int port)
-{
-	/* Disable the port */
-	LM4_UART_CTL(port) = 0x0300;
-	/* Use the internal oscillator */
-	LM4_UART_CC(port) = 0x1;
-	/* Set the baud rate divisor */
-	LM4_UART_IBRD(port) = (INTERNAL_CLOCK / 16) / CONFIG_UART_BAUD_RATE;
-	LM4_UART_FBRD(port) =
-		(((INTERNAL_CLOCK / 16) % CONFIG_UART_BAUD_RATE) * 64
-		 + CONFIG_UART_BAUD_RATE / 2) / CONFIG_UART_BAUD_RATE;
-	/*
-	 * 8-N-1, FIFO enabled.  Must be done after setting
-	 * the divisor for the new divisor to take effect.
-	 */
-	LM4_UART_LCRH(port) = 0x70;
-	/*
-	 * Interrupt when RX fifo at minimum (>= 1/8 full), and TX fifo
-	 * when <= 1/4 full
-	 */
-	LM4_UART_IFLS(port) = 0x01;
-	/*
-	 * Unmask receive-FIFO, receive-timeout.  We need
-	 * receive-timeout because the minimum RX FIFO depth is 1/8 = 2
-	 * bytes; without the receive-timeout we'd never be notified
-	 * about single received characters.
-	 */
-	LM4_UART_IM(port) = 0x50;
-	/* Enable the port */
-	LM4_UART_CTL(port) |= 0x0001;
-}
-
-void uart_init(void)
-{
-	uint32_t mask = 0;
-
-	/*
-	 * Enable UART0 in run, sleep, and deep sleep modes. Enable the Host
-	 * UART in run and sleep modes.
-	 */
-	mask |= 1;
-	clock_enable_peripheral(CGC_OFFSET_UART, mask, CGC_MODE_ALL);
-
-#ifdef CONFIG_UART_HOST
-	mask |= BIT(CONFIG_UART_HOST);
-#endif
-
-	clock_enable_peripheral(CGC_OFFSET_UART, mask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Configure UARTs (identically) */
-	uart_config(0);
-
-#ifdef CONFIG_UART_HOST
-	uart_config(CONFIG_UART_HOST);
-#endif
-
-	/*
-	 * Enable interrupts for UART0 only. Host UART will have to wait
-	 * until the LPC bus is initialized.
-	 */
-	uart_clear_rx_fifo(0);
-	task_enable_irq(LM4_IRQ_UART0);
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	const struct gpio_info g = gpio_list[GPIO_UART0_RX];
-
-	/* Disable the UART0 module interrupt. */
-	task_disable_irq(LM4_IRQ_UART0);
-
-	/* Disable UART0 peripheral in deep sleep. */
-	clock_disable_peripheral(CGC_OFFSET_UART, 0x1, CGC_MODE_DSLEEP);
-
-	/*
-	 * Set the UART0 RX pin to be a generic GPIO with the flags defined
-	 * in the board.c file.
-	 */
-	gpio_reset(GPIO_UART0_RX);
-
-	/* Clear any pending GPIO interrupts on the UART0 RX pin. */
-	LM4_GPIO_ICR(g.port) = g.mask;
-
-	/* Enable GPIO interrupts on the UART0 RX pin. */
-	gpio_enable_interrupt(GPIO_UART0_RX);
-}
-
-void uart_exit_dsleep(void)
-{
-	const struct gpio_info g = gpio_list[GPIO_UART0_RX];
-
-	/*
-	 * If the UART0 RX GPIO interrupt has not fired, then no edge has been
-	 * detected. Disable the GPIO interrupt so that switching the pin over
-	 * to a UART pin doesn't inadvertently cause a GPIO edge interrupt.
-	 * Note: we can't disable this interrupt if it has already fired
-	 * because then the IRQ will not get called.
-	 */
-	if (!(LM4_GPIO_MIS(g.port) & g.mask))
-		gpio_disable_interrupt(GPIO_UART0_RX);
-
-	/* Configure UART0 pins for use in UART peripheral. */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Clear pending interrupts on UART peripheral and enable interrupts. */
-	uart_clear_rx_fifo(0);
-	task_enable_irq(LM4_IRQ_UART0);
-
-	/* Enable UART0 peripheral in deep sleep */
-	clock_enable_peripheral(CGC_OFFSET_UART, 0x1, CGC_MODE_DSLEEP);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Activity seen on UART RX pin while UART was disabled for deep sleep.
-	 * The console won't see that character because the UART is disabled,
-	 * so we need to inform the clock module of UART activity ourselves.
-	 */
-	clock_refresh_console_in_use();
-
-	/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART0_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-
-/*****************************************************************************/
-/* COMx functions */
-
-#ifdef CONFIG_UART_HOST
-
-void uart_comx_enable(void)
-{
-	uart_clear_rx_fifo(CONFIG_UART_HOST);
-	task_enable_irq(IRQ_UART_HOST);
-}
-
-int uart_comx_putc_ok(void)
-{
-	if (LM4_UART_FR(CONFIG_UART_HOST) & 0x20) {
-		/*
-		 * FIFO is full, so enable transmit interrupt to let us know
-		 * when it empties.
-		 */
-		LM4_UART_IM(CONFIG_UART_HOST) |= 0x20;
-		return 0;
-	} else {
-		return 1;
-	}
-}
-
-void uart_comx_putc(int c)
-{
-	LM4_UART_DR(CONFIG_UART_HOST) = c;
-}
-
-#endif /* CONFIG_UART_HOST */
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_COMXTEST
-
-/**
- * Write a character to COMx, waiting for space in the output buffer if
- * necessary.
- */
-static void uart_comx_putc_wait(int c)
-{
-		while (!uart_comx_putc_ok())
-			;
-		uart_comx_putc(c);
-}
-
-static int command_comxtest(int argc, char **argv)
-{
-	/* Put characters to COMX port */
-	const char *c = argc > 1 ? argv[1] : "testing comx output!";
-
-	ccprintf("Writing \"%s\\r\\n\" to COMx UART...\n", c);
-
-	while (*c)
-		uart_comx_putc_wait(*c++);
-
-	uart_comx_putc_wait('\r');
-	uart_comx_putc_wait('\n');
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(comxtest, command_comxtest,
-			"[string]",
-			"Write test data to COMx uart");
-
-#endif /* CONFIG_CMD_COMXTEST */
diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c
deleted file mode 100644
index 50f122bf02..0000000000
--- a/chip/lm4/watchdog.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "clock.h"
-#include "common.h"
-#include "registers.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * We use watchdog 0 which is clocked on the system clock
- * to avoid the penalty cycles on each write access
- */
-
-/* magic value to unlock the watchdog registers */
-#define LM4_WATCHDOG_MAGIC_WORD  0x1ACCE551
-
-static uint32_t watchdog_period;     /* Watchdog counter initial value */
-
-void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void) __attribute__((naked));
-void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveniently saves
-		      * R0=LR so we can pass it to task_resched_if_needed. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_trace\n"
-		      /* Do NOT reset the watchdog interrupt here; it will
-		       * be done in watchdog_reload(), or reset will be
-		       * triggered if we don't call that by the next watchdog
-		       * period.  Instead, de-activate the interrupt in the
-		       * NVIC, so the watchdog trace will only be printed
-		       * once.
-		       */
-		     "mov r0, %[irq]\n"
-		     "bl task_disable_irq\n"
-		     "pop {r0, lr}\n"
-		     "b task_resched_if_needed\n"
-			: : [irq] "i" (LM4_IRQ_WATCHDOG));
-}
-const struct irq_priority __keep IRQ_PRIORITY(LM4_IRQ_WATCHDOG)
-	__attribute__((section(".rodata.irqprio")))
-		= {LM4_IRQ_WATCHDOG, 0}; /* put the watchdog at the highest
-					    priority */
-
-void watchdog_reload(void)
-{
-	uint32_t status = LM4_WATCHDOG_RIS(0);
-
-	/* Unlock watchdog registers */
-	LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD;
-
-	/* As we reboot only on the second timeout, if we have already reached
-	 * the first timeout we need to reset the interrupt bit. */
-	if (status) {
-		LM4_WATCHDOG_ICR(0) = status;
-		/* That doesn't seem to unpend the watchdog interrupt (even if
-		 * we do writes to force the write to be committed), so
-		 * explicitly unpend the interrupt before re-enabling it. */
-		task_clear_pending_irq(LM4_IRQ_WATCHDOG);
-		task_enable_irq(LM4_IRQ_WATCHDOG);
-	}
-
-	/* Reload the watchdog counter */
-	LM4_WATCHDOG_LOAD(0) = watchdog_period;
-
-	/* Re-lock watchdog registers */
-	LM4_WATCHDOG_LOCK(0) = 0xdeaddead;
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-static void watchdog_freq_changed(void)
-{
-	/* Set the timeout period */
-	watchdog_period = CONFIG_WATCHDOG_PERIOD_MS * (clock_get_freq() / 1000);
-
-	/* Reload the watchdog timer now */
-	watchdog_reload();
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, watchdog_freq_changed, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	/* Enable watchdog 0 clock in run, sleep, and deep sleep modes */
-	clock_enable_peripheral(CGC_OFFSET_WD, 0x1, CGC_MODE_ALL);
-
-	/* Set initial timeout period */
-	watchdog_freq_changed();
-
-	/* Unlock watchdog registers */
-	LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD;
-
-	/* De-activate the watchdog when the JTAG stops the CPU */
-	LM4_WATCHDOG_TEST(0) |= BIT(8);
-
-	/* Reset after 2 time-out, activate the watchdog and lock the control
-	 * register. */
-	LM4_WATCHDOG_CTL(0) = 0x3;
-
-	/* Reset watchdog interrupt bits */
-	LM4_WATCHDOG_ICR(0) = LM4_WATCHDOG_RIS(0);
-
-	/* Lock watchdog registers against unintended accesses */
-	LM4_WATCHDOG_LOCK(0) = 0xdeaddead;
-
-	/* Enable watchdog interrupt */
-	task_enable_irq(LM4_IRQ_WATCHDOG);
-
-	return EC_SUCCESS;
-}
diff --git a/chip/max32660/build.mk b/chip/max32660/build.mk
deleted file mode 100644
index e0f5636b2e..0000000000
--- a/chip/max32660/build.mk
+++ /dev/null
@@ -1,21 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# MAX32660 chip specific files build
-#
-
-# MAX32660 SoC has a Cortex-M4F ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# Required chip modules
-chip-y=clock_chip.o gpio_chip.o system_chip.o hwtimer_chip.o uart_chip.o
-chip-$(CONFIG_I2C)+=i2c_chip.o
-
-# Optional chip modules
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash_chip.o
-chip-$(CONFIG_WATCHDOG)+=wdt_chip.o
-
diff --git a/chip/max32660/clock_chip.c b/chip/max32660/clock_chip.c
deleted file mode 100644
index 901c5d559c..0000000000
--- a/chip/max32660/clock_chip.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Clocks and Power Management Module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-#include "tmr_regs.h"
-#include "gcr_regs.h"
-#include "pwrseq_regs.h"
-
-#define MAX32660_SYSTEMCLOCK SYS_CLOCK_HIRC
-
-/** Clock source */
-typedef enum {
-	SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring
-								 on MAX32660 */
-	SYS_CLOCK_HFXIN =
-		MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
-	SYS_CLOCK_HFXIN_DIGITAL = 0x9,	/**< External Clock Input*/
-	SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency
-							 Internal Oscillator */
-} sys_system_clock_t;
-
-/***** Functions ******/
-static void clock_wait_ready(uint32_t ready)
-{
-	// Start timeout, wait for ready
-	do {
-		if (MXC_GCR->clkcn & ready) {
-			return;
-		}
-	} while (1);
-}
-
-extern void (*const __isr_vector[])(void);
-uint32_t SystemCoreClock = HIRC96_FREQ;
-
-static void clock_update(void)
-{
-	uint32_t base_freq, divide, ovr;
-
-	// Get the clock source and frequency
-	ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
-	if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
-		base_freq = HIRC96_FREQ / 4;
-	} else {
-		if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
-			base_freq = HIRC96_FREQ / 2;
-		} else {
-			base_freq = HIRC96_FREQ;
-		}
-	}
-
-	// Get the clock divider
-	divide = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >>
-		 MXC_F_GCR_CLKCN_PSC_POS;
-
-	SystemCoreClock = base_freq >> divide;
-}
-
-void clock_init(void)
-{
-	/* Switch system clock to HIRC */
-	uint32_t ovr, divide;
-
-	// Set FWS higher than what the minimum for the fastest clock is
-	MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-			   (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-
-	// Enable 96MHz Clock
-	MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC_EN;
-
-	// Wait for the 96MHz clock
-	clock_wait_ready(MXC_F_GCR_CLKCN_HIRC_RDY);
-
-	// Set 96MHz clock as System Clock
-	MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL,
-		     MXC_S_GCR_CLKCN_CLKSEL_HIRC);
-
-	// Wait for system clock to be ready
-	clock_wait_ready(MXC_F_GCR_CLKCN_CKRDY);
-
-	// Update the system core clock
-	clock_update();
-
-	// Get the clock divider
-	divide = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >>
-		 MXC_F_GCR_CLKCN_PSC_POS;
-
-	// get ovr setting
-	ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
-
-	// Set flash wait settings
-	if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
-		if (divide == 0) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		}
-	} else if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
-		if (divide == 0) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		}
-	} else {
-		if (divide == 0) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else if (divide == 1) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		}
-	}
-}
diff --git a/chip/max32660/config_chip.h b/chip/max32660/config_chip.h
deleted file mode 100644
index c97c246bb7..0000000000
--- a/chip/max32660/config_chip.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* 96.000 MHz internal oscillator frequency */
-#define INTERNAL_CLOCK 96000000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 132
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 8192
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 250
-#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 2
-
-/*
- * Time it takes to set the RTC match register. This value is conservatively
- * set based on measurements around 200us.
- */
-#define HIB_SET_RTC_MATCH_DELAY_USEC 300
-
-/****************************************************************************/
-/* Memory mapping */
-
-#define CONFIG_RAM_BASE 0x20000000
-#define CONFIG_RAM_SIZE 0x00018000 /* 96k MAX32660 SRAM Size*/
-
-/* System stack size */
-#define CONFIG_STACK_SIZE 4096
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE 512
-#define LARGER_TASK_STACK_SIZE 768
-#define SMALLER_TASK_STACK_SIZE 384
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
-#define CONFIG_FLASH_BANK_SIZE 0x00002000  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE 0x00002000 /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
-
-/* Ideal flash write size fills the 32-entry flash write buffer */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE (32 * 4)
-
-/* This is the physical size of the flash on the chip. We'll reserve one bank
- * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
- * doesn't support a write-protect pin, and if we make the write-protection
- * permanent, it can't be undone easily enough to support RMA. */
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256K MAX32660 FLASH Size */
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/****************************************************************************/
-/* Lock the boot configuration to prevent brickage. */
-
-/*
- * No GPIO trigger for ROM bootloader.
- * Keep JTAG debugging enabled.
- * Use 0xA442 flash write key.
- * Lock it this way.
- */
-#define CONFIG_BOOTCFG_VALUE 0x7ffffffe
-
-/****************************************************************************/
-/* Customize the build */
-
-/* Optional features present on this chip */
-#define CONFIG_HOSTCMD_ALIGNED
-#define CONFIG_RTC
-#define CONFIG_SWITCH
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(port, index) GPIO_##port, (1 << index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/max32660/flash_chip.c b/chip/max32660/flash_chip.c
deleted file mode 100644
index 747d7dcc58..0000000000
--- a/chip/max32660/flash_chip.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Flash Memory Module for Chrome EC */
-
-#include "flash.h"
-#include "switch.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-#include "registers.h"
-#include "common.h"
-#include "icc_regs.h"
-#include "flc_regs.h"
-
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/***** Definitions *****/
-
-/// Bit mask that can be used to find the starting address of a page in flash
-#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
-
-/// Calculate the address of a page in flash from the page number
-#define MXC_FLASH_PAGE_ADDR(page)                                              \
-	(MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
-
-void flash_operation(void)
-{
-	volatile uint32_t *line_addr;
-	volatile uint32_t __attribute__((unused)) line;
-
-	// Clear the cache
-	MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
-	MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
-
-	// Clear the line fill buffer
-	line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE);
-	line = *line_addr;
-
-	line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE);
-	line = *line_addr;
-}
-
-static int flash_busy(void)
-{
-	return (MXC_FLC->cn &
-		(MXC_F_FLC_CN_WR | MXC_F_FLC_CN_ME | MXC_F_FLC_CN_PGE));
-}
-
-static int flash_init_controller(void)
-{
-	// Set flash clock divider to generate a 1MHz clock from the APB clock
-	MXC_FLC->clkdiv = SystemCoreClock / 1000000;
-
-	/* Check if the flash controller is busy */
-	if (flash_busy()) {
-		return EC_ERROR_BUSY;
-	}
-
-	/* Clear stale errors */
-	if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
-		MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
-	}
-
-	/* Unlock flash */
-	MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_UNLOCK) |
-		      MXC_S_FLC_CN_UNLOCK_UNLOCKED;
-
-	return EC_SUCCESS;
-}
-
-static int flash_device_page_erase(uint32_t address)
-{
-	int err;
-
-	if ((err = flash_init_controller()) != EC_SUCCESS)
-		return err;
-
-	// Align address on page boundary
-	address = address - (address % MXC_FLASH_PAGE_SIZE);
-
-	/* Write paflash_init_controllerde */
-	MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_ERASE_CODE) |
-		      MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE;
-	/* Issue page erase command */
-	MXC_FLC->addr = address;
-	MXC_FLC->cn |= MXC_F_FLC_CN_PGE;
-
-	/* Wait until flash operation is complete */
-	while (flash_busy())
-		;
-
-	/* Lock flash */
-	MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
-
-	/* Check access violations */
-	if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
-		MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
-		return EC_ERROR_UNKNOWN;
-	}
-
-	flash_operation();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int err;
-	uint32_t bytes_written;
-	uint8_t current_data[4];
-
-	if ((err = flash_init_controller()) != EC_SUCCESS)
-		return err;
-
-	// write in 32-bit units until we are 128-bit aligned
-	MXC_FLC->cn &= ~MXC_F_FLC_CN_BRST;
-	MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
-
-	// Align the address and read/write if we have to
-	if (offset & 0x3) {
-
-		// Figure out how many bytes we have to write to round up the
-		// address
-		bytes_written = 4 - (offset & 0x3);
-
-		// Save the data currently in the flash
-		memcpy(current_data, (void *)(offset & (~0x3)), 4);
-
-		// Modify current_data to insert the data from buffer
-		memcpy(&current_data[4 - bytes_written], data, bytes_written);
-
-		// Write the modified data
-		MXC_FLC->addr = offset - (offset % 4);
-		memcpy((void *)&MXC_FLC->data[0], &current_data, 4);
-		MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-		/* Wait until flash operation is complete */
-		while (flash_busy())
-			;
-
-		offset += bytes_written;
-		size -= bytes_written;
-		data += bytes_written;
-	}
-
-	while ((size >= 4) && ((offset & 0x1F) != 0)) {
-		MXC_FLC->addr = offset;
-		memcpy((void *)&MXC_FLC->data[0], data, 4);
-		MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-		/* Wait until flash operation is complete */
-		while (flash_busy())
-			;
-
-		offset += 4;
-		size -= 4;
-		data += 4;
-	}
-
-	if (size >= 16) {
-
-		// write in 128-bit bursts while we can
-		MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
-
-		while (size >= 16) {
-			MXC_FLC->addr = offset;
-			memcpy((void *)&MXC_FLC->data[0], data, 16);
-			MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-			/* Wait until flash operation is complete */
-			while (flash_busy())
-				;
-
-			offset += 16;
-			size -= 16;
-			data += 16;
-		}
-
-		// Return to 32-bit writes.
-		MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
-	}
-
-	while (size >= 4) {
-		MXC_FLC->addr = offset;
-		memcpy((void *)&MXC_FLC->data[0], data, 4);
-		MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-		/* Wait until flash operation is complete */
-		while (flash_busy())
-			;
-
-		offset += 4;
-		size -= 4;
-		data += 4;
-	}
-
-	if (size > 0) {
-		// Save the data currently in the flash
-		memcpy(current_data, (void *)(offset), 4);
-
-		// Modify current_data to insert the data from data
-		memcpy(current_data, data, size);
-
-		MXC_FLC->addr = offset;
-		memcpy((void *)&MXC_FLC->data[0], current_data, 4);
-		MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-		/* Wait until flash operation is complete */
-		while (flash_busy())
-			;
-	}
-
-	/* Lock flash */
-	MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
-
-	/* Check access violations */
-	if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
-		MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
-		return EC_ERROR_UNKNOWN;
-	}
-
-	flash_operation();
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int i;
-	int pages;
-	int error_status;
-
-	/*
-	 * erase 'size' number of bytes starting at address 'offset'
-	 */
-	/* calculate the number of pages */
-	pages = size / CONFIG_FLASH_ERASE_SIZE;
-	/* iterate over the number of pages */
-	for (i = 0; i < pages; i++) {
-		/* erase the page after calculating the start address */
-		error_status = flash_device_page_erase(
-			offset + (i * CONFIG_FLASH_ERASE_SIZE));
-		if (error_status != EC_SUCCESS) {
-			return error_status;
-		}
-	}
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_get_protect(int bank)
-{
-	/* Not protected */
-	return 0;
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	/* no flags set */
-	return 0;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	/* These are the flags we're going to pay attention to */
-	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	/* no flags writable */
-	return 0;
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	/* nothing to do here */
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	/* nothing to do here */
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* High-level APIs */
-
-int crec_flash_pre_init(void)
-{
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Test Commands */
-
-/*
- * Read, Write, and Erase a page of flash memory using chip routines
- * NOTE: This is a DESTRUCTIVE test for the range of flash pages tested
- *       make sure that PAGE_START is beyond your flash code.
- */
-static int command_flash_test1(int argc, char **argv)
-{
-	int i;
-	uint8_t *ptr;
-	const uint32_t PAGE_START = 9;
-	const uint32_t PAGE_END = 32;
-	uint32_t page;
-	int error_status;
-	uint32_t flash_address;
-	const int BUFFER_SIZE = 32;
-	uint8_t buffer[BUFFER_SIZE];
-
-	/*
-	 * As a test, write unique data to each page in this for loop, later
-	 * verify data in pages
-	 */
-	for (page = PAGE_START; page < PAGE_END; page++) {
-		flash_address = page * CONFIG_FLASH_ERASE_SIZE;
-
-		/*
-		 * erase page
-		 */
-		error_status = crec_flash_physical_erase(flash_address,
-						    CONFIG_FLASH_ERASE_SIZE);
-		if (error_status != EC_SUCCESS) {
-			CPRINTS("Error with crec_flash_physical_erase\n");
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/*
-		 * verify page was erased
-		 */
-		// CPRINTS("read flash page %d, address %x, ", page,
-		// flash_address);
-		ptr = (uint8_t *)flash_address;
-		for (i = 0; i < CONFIG_FLASH_ERASE_SIZE; i++) {
-			if (*ptr++ != 0xff) {
-				CPRINTS("Error with verifying page erase\n");
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-
-		/*
-		 * write pattern to page, just write BUFFER_SIZE worth of data
-		 */
-		for (i = 0; i < BUFFER_SIZE; i++) {
-			buffer[i] = i + page;
-		}
-		error_status = crec_flash_physical_write(flash_address,
-							 BUFFER_SIZE, buffer);
-		if (error_status != EC_SUCCESS) {
-			CPRINTS("Error with crec_flash_physical_write\n");
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	/*
-	 * Verify data in pages
-	 */
-	for (page = PAGE_START; page < PAGE_END; page++) {
-		flash_address = page * CONFIG_FLASH_ERASE_SIZE;
-
-		/*
-		 * read a portion of flash memory
-		 */
-		ptr = (uint8_t *)flash_address;
-		for (i = 0; i < BUFFER_SIZE; i++) {
-			if (*ptr++ != (i + page)) {
-				CPRINTS("Error with verifing written test "
-					"data\n");
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		CPRINTS("Verified Erase, Write, Read page %d", page);
-	}
-
-	/*
-	 * Clean up after tests
-	 */
-	for (page = PAGE_START; page <= PAGE_END; page++) {
-		flash_address = page * CONFIG_FLASH_ERASE_SIZE;
-		error_status = crec_flash_physical_erase(flash_address,
-						    CONFIG_FLASH_ERASE_SIZE);
-		if (error_status != EC_SUCCESS) {
-			CPRINTS("Error with crec_flash_physical_erase\n");
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	CPRINTS("done command_flash_test1.");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(flashtest1, command_flash_test1, "flashtest1",
-			"Flash chip routine tests");
diff --git a/chip/max32660/flc_regs.h b/chip/max32660/flc_regs.h
deleted file mode 100644
index a484763c0b..0000000000
--- a/chip/max32660/flc_regs.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the FLC Peripheral Module
- */
-
-#ifndef _FLC_REGS_H_
-#define _FLC_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * Registers, Bit Masks and Bit Positions for the FLC Peripheral
- * Module.
- */
-
-/**
- * Structure type to access the FLC Registers.
- */
-typedef struct {
-	__IO uint32_t addr;   /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
-	__IO uint32_t clkdiv; /**< <tt>\b 0x04:<\tt> FLC CLKDIV Register */
-	__IO uint32_t cn;     /**< <tt>\b 0x08:<\tt> FLC CN Register */
-	__R uint32_t rsv_0xc_0x23[6];
-	__IO uint32_t intr; /**< <tt>\b 0x024:<\tt> FLC INTR Register */
-	__R uint32_t rsv_0x28_0x2f[2];
-	__IO uint32_t data[4]; /**< <tt>\b 0x30:<\tt> FLC DATA Register */
-	__O uint32_t acntl;    /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
-} mxc_flc_regs_t;
-
-/* Register offsets for module FLC */
-/**
- * FLC Peripheral Register Offsets from the FLC Base Peripheral
- * Address.
- */
-#define MXC_R_FLC_ADDR                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_FLC_CLKDIV                                                       \
-	((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x004 */
-#define MXC_R_FLC_CN                                                           \
-	((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x008 */
-#define MXC_R_FLC_INTR                                                         \
-	((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x024 */
-#define MXC_R_FLC_DATA                                                         \
-	((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x030 */
-#define MXC_R_FLC_ACNTL                                                        \
-	((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x040 */
-
-/**
- * Flash Write Address.
- */
-#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
-#define MXC_F_FLC_ADDR_ADDR                                                    \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
-
-/**
- * Flash Clock Divide. The clock (PLL0) is divided by this value to
- * generate a 1 MHz clock for Flash controller.
- */
-#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
-#define MXC_F_FLC_CLKDIV_CLKDIV                                                \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
-
-/**
- * Flash Control Register.
- */
-#define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */
-#define MXC_F_FLC_CN_WR                                                        \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */
-#define MXC_V_FLC_CN_WR_COMPLETE                                               \
-	((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value                            \
-			   */
-#define MXC_S_FLC_CN_WR_COMPLETE                                               \
-	(MXC_V_FLC_CN_WR_COMPLETE                                              \
-	 << MXC_F_FLC_CN_WR_POS)		/**< CN_WR_COMPLETE Setting */
-#define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */
-#define MXC_S_FLC_CN_WR_START                                                  \
-	(MXC_V_FLC_CN_WR_START                                                 \
-	 << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */
-
-#define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */
-#define MXC_F_FLC_CN_ME                                                        \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
-
-#define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */
-#define MXC_F_FLC_CN_PGE                                                       \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
-
-#define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */
-#define MXC_F_FLC_CN_WDTH                                                      \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */
-#define MXC_V_FLC_CN_WDTH_SIZE128                                              \
-	((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */
-#define MXC_S_FLC_CN_WDTH_SIZE128                                              \
-	(MXC_V_FLC_CN_WDTH_SIZE128                                             \
-	 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
-#define MXC_V_FLC_CN_WDTH_SIZE32                                               \
-	((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value                            \
-			   */
-#define MXC_S_FLC_CN_WDTH_SIZE32                                               \
-	(MXC_V_FLC_CN_WDTH_SIZE32                                              \
-	 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */
-
-#define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */
-#define MXC_F_FLC_CN_ERASE_CODE                                                \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
-#define MXC_V_FLC_CN_ERASE_CODE_NOP                                            \
-	((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */
-#define MXC_S_FLC_CN_ERASE_CODE_NOP                                            \
-	(MXC_V_FLC_CN_ERASE_CODE_NOP                                           \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
-#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                      \
-	((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */
-#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE                                      \
-	(MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                     \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting  \
-					  */
-#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                       \
-	((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */
-#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL                                       \
-	(MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                      \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting   \
-					  */
-
-#define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */
-#define MXC_F_FLC_CN_PEND                                                      \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */
-#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL)     /**< CN_PEND_IDLE Value */
-#define MXC_S_FLC_CN_PEND_IDLE                                                 \
-	(MXC_V_FLC_CN_PEND_IDLE                                                \
-	 << MXC_F_FLC_CN_PEND_POS)		 /**< CN_PEND_IDLE Setting */
-#define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */
-#define MXC_S_FLC_CN_PEND_BUSY                                                 \
-	(MXC_V_FLC_CN_PEND_BUSY                                                \
-	 << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
-
-#define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */
-#define MXC_F_FLC_CN_LVE                                                       \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
-#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL)      /**< CN_LVE_DIS Value */
-#define MXC_S_FLC_CN_LVE_DIS                                                   \
-	(MXC_V_FLC_CN_LVE_DIS                                                  \
-	 << MXC_F_FLC_CN_LVE_POS)	     /**< CN_LVE_DIS Setting */
-#define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */
-#define MXC_S_FLC_CN_LVE_EN                                                    \
-	(MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting   \
-						       */
-
-#define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */
-#define MXC_F_FLC_CN_BRST                                                      \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
-#define MXC_V_FLC_CN_BRST_DISABLE                                              \
-	((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */
-#define MXC_S_FLC_CN_BRST_DISABLE                                              \
-	(MXC_V_FLC_CN_BRST_DISABLE                                             \
-	 << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
-#define MXC_V_FLC_CN_BRST_ENABLE                                               \
-	((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value                            \
-			   */
-#define MXC_S_FLC_CN_BRST_ENABLE                                               \
-	(MXC_V_FLC_CN_BRST_ENABLE                                              \
-	 << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */
-
-#define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */
-#define MXC_F_FLC_CN_UNLOCK                                                    \
-	((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
-#define MXC_V_FLC_CN_UNLOCK_UNLOCKED                                           \
-	((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
-#define MXC_S_FLC_CN_UNLOCK_UNLOCKED                                           \
-	(MXC_V_FLC_CN_UNLOCK_UNLOCKED                                          \
-	 << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
-
-/**
- * Flash Interrupt Register.
- */
-#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
-#define MXC_F_FLC_INTR_DONE                                                    \
-	((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
-#define MXC_V_FLC_INTR_DONE_INACTIVE                                           \
-	((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */
-#define MXC_S_FLC_INTR_DONE_INACTIVE                                           \
-	(MXC_V_FLC_INTR_DONE_INACTIVE                                          \
-	 << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
-#define MXC_V_FLC_INTR_DONE_PENDING                                            \
-	((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */
-#define MXC_S_FLC_INTR_DONE_PENDING                                            \
-	(MXC_V_FLC_INTR_DONE_PENDING                                           \
-	 << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
-
-#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */
-#define MXC_F_FLC_INTR_AF                                                      \
-	((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
-#define MXC_V_FLC_INTR_AF_NOERROR                                              \
-	((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */
-#define MXC_S_FLC_INTR_AF_NOERROR                                              \
-	(MXC_V_FLC_INTR_AF_NOERROR                                             \
-	 << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
-#define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */
-#define MXC_S_FLC_INTR_AF_ERROR                                                \
-	(MXC_V_FLC_INTR_AF_ERROR                                               \
-	 << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */
-
-#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
-#define MXC_F_FLC_INTR_DONEIE                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
-#define MXC_V_FLC_INTR_DONEIE_DISABLE                                          \
-	((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */
-#define MXC_S_FLC_INTR_DONEIE_DISABLE                                          \
-	(MXC_V_FLC_INTR_DONEIE_DISABLE                                         \
-	 << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
-#define MXC_V_FLC_INTR_DONEIE_ENABLE                                           \
-	((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */
-#define MXC_S_FLC_INTR_DONEIE_ENABLE                                           \
-	(MXC_V_FLC_INTR_DONEIE_ENABLE                                          \
-	 << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
-
-#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
-#define MXC_F_FLC_INTR_AFIE                                                    \
-	((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
-
-/**
- * Flash Write Data.
- */
-#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
-#define MXC_F_FLC_DATA_DATA                                                    \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
-
-/**
- * Access Control Register. Writing the ACNTL register with the
- * following values in the order shown, allows read and write access to the
- * system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl =
- * 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will
- * disable access to system and user information block. Readback of this
- * register is always zero.
- */
-#define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */
-#define MXC_F_FLC_ACNTL_ACNTL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FLC_REGS_H_ */
diff --git a/chip/max32660/gcr_regs.h b/chip/max32660/gcr_regs.h
deleted file mode 100644
index c9de13812c..0000000000
--- a/chip/max32660/gcr_regs.h
+++ /dev/null
@@ -1,1365 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the GCR Peripheral Module
- */
-
-#ifndef _GCR_REGS_H_
-#define _GCR_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * Registers, Bit Masks and Bit Positions for the GCR Peripheral
- * Module.
- */
-
-/**
- * Structure type to access the GCR Registers.
- */
-typedef struct {
-	__IO uint32_t scon;  /**< <tt>\b 0x00:<\tt> GCR SCON Register */
-	__IO uint32_t rstr0; /**< <tt>\b 0x04:<\tt> GCR RSTR0 Register */
-	__IO uint32_t clkcn; /**< <tt>\b 0x08:<\tt> GCR CLKCN Register */
-	__IO uint32_t pm;    /**< <tt>\b 0x0C:<\tt> GCR PM Register */
-	__R uint32_t rsv_0x10_0x17[2];
-	__IO uint32_t pckdiv; /**< <tt>\b 0x18:<\tt> GCR PCKDIV Register */
-	__R uint32_t rsv_0x1c_0x23[2];
-	__IO uint32_t perckcn0; /**< <tt>\b 0x24:<\tt> GCR PERCKCN0 Register */
-	__IO uint32_t memckcn;  /**< <tt>\b 0x28:<\tt> GCR MEMCKCN Register */
-	__IO uint32_t memzcn;   /**< <tt>\b 0x2C:<\tt> GCR MEMZCN Register */
-	__R uint32_t rsv_0x30;
-	__IO uint32_t scck;     /**< <tt>\b 0x34:<\tt> GCR SCCK Register */
-	__IO uint32_t mpri0;    /**< <tt>\b 0x38:<\tt> GCR MPRI0 Register */
-	__IO uint32_t mpri1;    /**< <tt>\b 0x3C:<\tt> GCR MPRI1 Register */
-	__IO uint32_t sysst;    /**< <tt>\b 0x40:<\tt> GCR SYSST Register */
-	__IO uint32_t rstr1;    /**< <tt>\b 0x44:<\tt> GCR RSTR1 Register */
-	__IO uint32_t perckcn1; /**< <tt>\b 0x48:<\tt> GCR PERCKCN1 Register */
-	__IO uint32_t evten;    /**< <tt>\b 0x4C:<\tt> GCR EVTEN Register */
-	__I uint32_t revision;  /**< <tt>\b 0x50:<\tt> GCR REVISION Register */
-	__IO uint32_t syssie;   /**< <tt>\b 0x54:<\tt> GCR SYSSIE Register */
-} mxc_gcr_regs_t;
-
-/**
- * GCR Peripheral Register Offsets from the GCR Base Peripheral
- * Address.
- */
-#define MXC_R_GCR_SCON                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_GCR_RSTR0                                                        \
-	((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x004 */
-#define MXC_R_GCR_CLKCN                                                        \
-	((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x008 */
-#define MXC_R_GCR_PM                                                           \
-	((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x00C */
-#define MXC_R_GCR_PCKDIV                                                       \
-	((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x018 */
-#define MXC_R_GCR_PERCKCN0                                                     \
-	((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x024 */
-#define MXC_R_GCR_MEMCKCN                                                      \
-	((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x028 */
-#define MXC_R_GCR_MEMZCN                                                       \
-	((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x02C */
-#define MXC_R_GCR_SCCK                                                         \
-	((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x034 */
-#define MXC_R_GCR_MPRI0                                                        \
-	((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x038 */
-#define MXC_R_GCR_MPRI1                                                        \
-	((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x03C */
-#define MXC_R_GCR_SYSST                                                        \
-	((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x040 */
-#define MXC_R_GCR_RSTR1                                                        \
-	((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x044 */
-#define MXC_R_GCR_PERCKCN1                                                     \
-	((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x048 */
-#define MXC_R_GCR_EVTEN                                                        \
-	((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x04C */
-#define MXC_R_GCR_REVISION                                                     \
-	((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x050 */
-#define MXC_R_GCR_SYSSIE                                                       \
-	((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x054 */
-
-/**
- * System Control.
- */
-#define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */
-#define MXC_F_GCR_SCON_SBUSARB                                                 \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
-#define MXC_V_GCR_SCON_SBUSARB_FIX                                             \
-	((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */
-#define MXC_S_GCR_SCON_SBUSARB_FIX                                             \
-	(MXC_V_GCR_SCON_SBUSARB_FIX                                            \
-	 << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
-#define MXC_V_GCR_SCON_SBUSARB_ROUND                                           \
-	((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */
-#define MXC_S_GCR_SCON_SBUSARB_ROUND                                           \
-	(MXC_V_GCR_SCON_SBUSARB_ROUND                                          \
-	 << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
-
-#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS                                     \
-	4 /**< SCON_FLASH_PAGE_FLIP Position */
-#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                                          \
-	((uint32_t)(                                                            \
-		0x1UL                                                           \
-		<< MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**<                    \
-							   SCON_FLASH_PAGE_FLIP \
-							   Mask */
-#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                  \
-	((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
-#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                  \
-	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                 \
-	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**<                           \
-						   SCON_FLASH_PAGE_FLIP_NORMAL \
-						   Setting */
-#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                 \
-	((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
-#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                  \
-	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                 \
-	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**<                            \
-						   SCON_FLASH_PAGE_FLIP_SWAPPED \
-						   Setting */
-
-#define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */
-#define MXC_F_GCR_SCON_FPU_DIS                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
-#define MXC_V_GCR_SCON_FPU_DIS_ENABLE                                          \
-	((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */
-#define MXC_S_GCR_SCON_FPU_DIS_ENABLE                                          \
-	(MXC_V_GCR_SCON_FPU_DIS_ENABLE                                         \
-	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */
-#define MXC_V_GCR_SCON_FPU_DIS_DISABLE                                         \
-	((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */
-#define MXC_S_GCR_SCON_FPU_DIS_DISABLE                                         \
-	(MXC_V_GCR_SCON_FPU_DIS_DISABLE                                        \
-	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */
-
-#define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */
-#define MXC_F_GCR_SCON_CCACHE_FLUSH                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH    \
-							Mask */
-#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                     \
-	((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
-#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL                                     \
-	(MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                    \
-	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL     \
-						Setting */
-#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                      \
-	((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */
-#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH                                      \
-	(MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                     \
-	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH      \
-						Setting */
-
-#define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */
-#define MXC_F_GCR_SCON_SWD_DIS                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
-#define MXC_V_GCR_SCON_SWD_DIS_ENABLE                                          \
-	((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */
-#define MXC_S_GCR_SCON_SWD_DIS_ENABLE                                          \
-	(MXC_V_GCR_SCON_SWD_DIS_ENABLE                                         \
-	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */
-#define MXC_V_GCR_SCON_SWD_DIS_DISABLE                                         \
-	((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */
-#define MXC_S_GCR_SCON_SWD_DIS_DISABLE                                         \
-	(MXC_V_GCR_SCON_SWD_DIS_DISABLE                                        \
-	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */
-
-/**
- * Reset Register 0.
- */
-#define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */
-#define MXC_F_GCR_RSTR0_DMA                                                    \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
-#define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */
-#define MXC_S_GCR_RSTR0_DMA_RFU                                                \
-	(MXC_V_GCR_RSTR0_DMA_RFU                                               \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */
-#define MXC_V_GCR_RSTR0_DMA_RESET                                              \
-	((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */
-#define MXC_S_GCR_RSTR0_DMA_RESET                                              \
-	(MXC_V_GCR_RSTR0_DMA_RESET                                             \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */
-#define MXC_V_GCR_RSTR0_DMA_RESET_DONE                                         \
-	((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_DMA_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_DMA_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_DMA_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_DMA_BUSY                                               \
-	(MXC_V_GCR_RSTR0_DMA_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */
-#define MXC_F_GCR_RSTR0_WDT                                                    \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
-#define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */
-#define MXC_S_GCR_RSTR0_WDT_RFU                                                \
-	(MXC_V_GCR_RSTR0_WDT_RFU                                               \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */
-#define MXC_V_GCR_RSTR0_WDT_RESET                                              \
-	((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */
-#define MXC_S_GCR_RSTR0_WDT_RESET                                              \
-	(MXC_V_GCR_RSTR0_WDT_RESET                                             \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */
-#define MXC_V_GCR_RSTR0_WDT_RESET_DONE                                         \
-	((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_WDT_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_WDT_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_WDT_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_WDT_BUSY                                               \
-	(MXC_V_GCR_RSTR0_WDT_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */
-#define MXC_F_GCR_RSTR0_GPIO0                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
-#define MXC_V_GCR_RSTR0_GPIO0_RFU                                              \
-	((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RFU                                              \
-	(MXC_V_GCR_RSTR0_GPIO0_RFU                                             \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_RESET                                            \
-	((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RESET                                            \
-	(MXC_V_GCR_RSTR0_GPIO0_RESET                                           \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                                       \
-	((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_BUSY                                             \
-	((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */
-#define MXC_S_GCR_RSTR0_GPIO0_BUSY                                             \
-	(MXC_V_GCR_RSTR0_GPIO0_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */
-#define MXC_F_GCR_RSTR0_TIMER0                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
-#define MXC_V_GCR_RSTR0_TIMER0_RFU                                             \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER0_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER0_RESET                                           \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER0_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                      \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting   \
-					 */
-#define MXC_V_GCR_RSTR0_TIMER0_BUSY                                            \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER0_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER0_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */
-#define MXC_F_GCR_RSTR0_TIMER1                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
-#define MXC_V_GCR_RSTR0_TIMER1_RFU                                             \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER1_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER1_RESET                                           \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER1_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                      \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting   \
-					 */
-#define MXC_V_GCR_RSTR0_TIMER1_BUSY                                            \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER1_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER1_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */
-#define MXC_F_GCR_RSTR0_TIMER2                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
-#define MXC_V_GCR_RSTR0_TIMER2_RFU                                             \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER2_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER2_RESET                                           \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER2_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                      \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting   \
-					 */
-#define MXC_V_GCR_RSTR0_TIMER2_BUSY                                            \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER2_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER2_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */
-#define MXC_F_GCR_RSTR0_UART0                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
-#define MXC_V_GCR_RSTR0_UART0_RFU                                              \
-	((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */
-#define MXC_S_GCR_RSTR0_UART0_RFU                                              \
-	(MXC_V_GCR_RSTR0_UART0_RFU                                             \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */
-#define MXC_V_GCR_RSTR0_UART0_RESET                                            \
-	((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */
-#define MXC_S_GCR_RSTR0_UART0_RESET                                            \
-	(MXC_V_GCR_RSTR0_UART0_RESET                                           \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */
-#define MXC_V_GCR_RSTR0_UART0_RESET_DONE                                       \
-	((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_UART0_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_UART0_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_UART0_BUSY                                             \
-	((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */
-#define MXC_S_GCR_RSTR0_UART0_BUSY                                             \
-	(MXC_V_GCR_RSTR0_UART0_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */
-#define MXC_F_GCR_RSTR0_UART1                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */
-#define MXC_V_GCR_RSTR0_UART1_RFU                                              \
-	((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */
-#define MXC_S_GCR_RSTR0_UART1_RFU                                              \
-	(MXC_V_GCR_RSTR0_UART1_RFU                                             \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */
-#define MXC_V_GCR_RSTR0_UART1_RESET                                            \
-	((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */
-#define MXC_S_GCR_RSTR0_UART1_RESET                                            \
-	(MXC_V_GCR_RSTR0_UART1_RESET                                           \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */
-#define MXC_V_GCR_RSTR0_UART1_RESET_DONE                                       \
-	((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_UART1_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_UART1_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_UART1_BUSY                                             \
-	((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */
-#define MXC_S_GCR_RSTR0_UART1_BUSY                                             \
-	(MXC_V_GCR_RSTR0_UART1_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */
-#define MXC_F_GCR_RSTR0_SPI0                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_SPI0_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_SPI0_RFU                                               \
-	(MXC_V_GCR_RSTR0_SPI0_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */
-#define MXC_V_GCR_RSTR0_SPI0_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */
-#define MXC_S_GCR_RSTR0_SPI0_RESET                                             \
-	(MXC_V_GCR_RSTR0_SPI0_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */
-#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SPI0_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SPI0_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */
-#define MXC_S_GCR_RSTR0_SPI0_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SPI0_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */
-#define MXC_F_GCR_RSTR0_SPI1                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_SPI1_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_SPI1_RFU                                               \
-	(MXC_V_GCR_RSTR0_SPI1_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */
-#define MXC_V_GCR_RSTR0_SPI1_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */
-#define MXC_S_GCR_RSTR0_SPI1_RESET                                             \
-	(MXC_V_GCR_RSTR0_SPI1_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */
-#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SPI1_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SPI1_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */
-#define MXC_S_GCR_RSTR0_SPI1_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SPI1_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */
-#define MXC_F_GCR_RSTR0_I2C0                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_I2C0_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_I2C0_RFU                                               \
-	(MXC_V_GCR_RSTR0_I2C0_RFU                                              \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */
-#define MXC_V_GCR_RSTR0_I2C0_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */
-#define MXC_S_GCR_RSTR0_I2C0_RESET                                             \
-	(MXC_V_GCR_RSTR0_I2C0_RESET                                            \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */
-#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_I2C0_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_I2C0_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */
-#define MXC_S_GCR_RSTR0_I2C0_BUSY                                              \
-	(MXC_V_GCR_RSTR0_I2C0_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */
-#define MXC_F_GCR_RSTR0_RTC                                                    \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */
-#define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */
-#define MXC_S_GCR_RSTR0_RTC_RFU                                                \
-	(MXC_V_GCR_RSTR0_RTC_RFU                                               \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */
-#define MXC_V_GCR_RSTR0_RTC_RESET                                              \
-	((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */
-#define MXC_S_GCR_RSTR0_RTC_RESET                                              \
-	(MXC_V_GCR_RSTR0_RTC_RESET                                             \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */
-#define MXC_V_GCR_RSTR0_RTC_RESET_DONE                                         \
-	((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_RTC_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_RTC_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_RTC_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_RTC_BUSY                                               \
-	(MXC_V_GCR_RSTR0_RTC_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */
-#define MXC_F_GCR_RSTR0_SRST                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_SRST_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_SRST_RFU                                               \
-	(MXC_V_GCR_RSTR0_SRST_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */
-#define MXC_V_GCR_RSTR0_SRST_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */
-#define MXC_S_GCR_RSTR0_SRST_RESET                                             \
-	(MXC_V_GCR_RSTR0_SRST_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */
-#define MXC_V_GCR_RSTR0_SRST_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SRST_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SRST_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SRST_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */
-#define MXC_S_GCR_RSTR0_SRST_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SRST_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */
-#define MXC_F_GCR_RSTR0_PRST                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_PRST_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_PRST_RFU                                               \
-	(MXC_V_GCR_RSTR0_PRST_RFU                                              \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */
-#define MXC_V_GCR_RSTR0_PRST_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */
-#define MXC_S_GCR_RSTR0_PRST_RESET                                             \
-	(MXC_V_GCR_RSTR0_PRST_RESET                                            \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */
-#define MXC_V_GCR_RSTR0_PRST_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_PRST_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_PRST_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_PRST_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */
-#define MXC_S_GCR_RSTR0_PRST_BUSY                                              \
-	(MXC_V_GCR_RSTR0_PRST_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */
-#define MXC_F_GCR_RSTR0_SYSTEM                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
-#define MXC_V_GCR_RSTR0_SYSTEM_RFU                                             \
-	((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RFU                                             \
-	(MXC_V_GCR_RSTR0_SYSTEM_RFU                                            \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */
-#define MXC_V_GCR_RSTR0_SYSTEM_RESET                                           \
-	((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RESET                                           \
-	(MXC_V_GCR_RSTR0_SYSTEM_RESET                                          \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */
-#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                      \
-	((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting   \
-					 */
-#define MXC_V_GCR_RSTR0_SYSTEM_BUSY                                            \
-	((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_BUSY                                            \
-	(MXC_V_GCR_RSTR0_SYSTEM_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */
-
-/**
- * Clock Control.
- */
-#define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */
-#define MXC_F_GCR_CLKCN_PSC                                                    \
-	((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */
-#define MXC_V_GCR_CLKCN_PSC_DIV1                                               \
-	((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value                            \
-			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV1                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV1                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV2                                               \
-	((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value                            \
-			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV2                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV2                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV4                                               \
-	((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value                            \
-			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV4                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV4                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV8                                               \
-	((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value                            \
-			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV8                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV8                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV16                                              \
-	((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV16                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV16                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV32                                              \
-	((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV32                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV32                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV64                                              \
-	((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV64                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV64                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV128                                             \
-	((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV128                                             \
-	(MXC_V_GCR_CLKCN_PSC_DIV128                                            \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
-
-#define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */
-#define MXC_F_GCR_CLKCN_CLKSEL                                                 \
-	((uint32_t)(0x7UL                                                      \
-		    << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
-#define MXC_V_GCR_CLKCN_CLKSEL_HIRC                                            \
-	((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_HIRC                                            \
-	(MXC_V_GCR_CLKCN_CLKSEL_HIRC                                           \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
-#define MXC_V_GCR_CLKCN_CLKSEL_NANORING                                        \
-	((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_NANORING                                        \
-	(MXC_V_GCR_CLKCN_CLKSEL_NANORING                                       \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */
-#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN                                           \
-	((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN                                           \
-	(MXC_V_GCR_CLKCN_CLKSEL_HFXIN                                          \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */
-
-#define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */
-#define MXC_F_GCR_CLKCN_CKRDY                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
-#define MXC_V_GCR_CLKCN_CKRDY_BUSY                                             \
-	((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */
-#define MXC_S_GCR_CLKCN_CKRDY_BUSY                                             \
-	(MXC_V_GCR_CLKCN_CKRDY_BUSY                                            \
-	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
-#define MXC_V_GCR_CLKCN_CKRDY_READY                                            \
-	((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */
-#define MXC_S_GCR_CLKCN_CKRDY_READY                                            \
-	(MXC_V_GCR_CLKCN_CKRDY_READY                                           \
-	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
-
-#define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */
-#define MXC_F_GCR_CLKCN_X32K_EN                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */
-#define MXC_V_GCR_CLKCN_X32K_EN_DIS                                            \
-	((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */
-#define MXC_S_GCR_CLKCN_X32K_EN_DIS                                            \
-	(MXC_V_GCR_CLKCN_X32K_EN_DIS                                           \
-	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */
-#define MXC_V_GCR_CLKCN_X32K_EN_EN                                             \
-	((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */
-#define MXC_S_GCR_CLKCN_X32K_EN_EN                                             \
-	(MXC_V_GCR_CLKCN_X32K_EN_EN                                            \
-	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */
-
-#define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */
-#define MXC_F_GCR_CLKCN_HIRC_EN                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
-#define MXC_V_GCR_CLKCN_HIRC_EN_DIS                                            \
-	((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */
-#define MXC_S_GCR_CLKCN_HIRC_EN_DIS                                            \
-	(MXC_V_GCR_CLKCN_HIRC_EN_DIS                                           \
-	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
-#define MXC_V_GCR_CLKCN_HIRC_EN_EN                                             \
-	((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */
-#define MXC_S_GCR_CLKCN_HIRC_EN_EN                                             \
-	(MXC_V_GCR_CLKCN_HIRC_EN_EN                                            \
-	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
-
-#define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */
-#define MXC_F_GCR_CLKCN_X32K_RDY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */
-#define MXC_V_GCR_CLKCN_X32K_RDY_NOT                                           \
-	((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_X32K_RDY_NOT                                           \
-	(MXC_V_GCR_CLKCN_X32K_RDY_NOT                                          \
-	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */
-#define MXC_V_GCR_CLKCN_X32K_RDY_READY                                         \
-	((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_X32K_RDY_READY                                         \
-	(MXC_V_GCR_CLKCN_X32K_RDY_READY                                        \
-	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */
-
-#define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */
-#define MXC_F_GCR_CLKCN_HIRC_RDY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
-#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT                                           \
-	((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT                                           \
-	(MXC_V_GCR_CLKCN_HIRC_RDY_NOT                                          \
-	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
-#define MXC_V_GCR_CLKCN_HIRC_RDY_READY                                         \
-	((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_HIRC_RDY_READY                                         \
-	(MXC_V_GCR_CLKCN_HIRC_RDY_READY                                        \
-	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
-
-#define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */
-#define MXC_F_GCR_CLKCN_LIRC8K_RDY                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY  \
-							   Mask */
-#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                         \
-	((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT                                         \
-	(MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                        \
-	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting  \
-					     */
-#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                                       \
-	((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY                                       \
-	(MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                                      \
-	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY        \
-					       Setting */
-
-/**
- * Power Management.
- */
-#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
-#define MXC_F_GCR_PM_MODE                                                      \
-	((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
-#define MXC_V_GCR_PM_MODE_ACTIVE                                               \
-	((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value                            \
-			   */
-#define MXC_S_GCR_PM_MODE_ACTIVE                                               \
-	(MXC_V_GCR_PM_MODE_ACTIVE                                              \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
-#define MXC_V_GCR_PM_MODE_SHUTDOWN                                             \
-	((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
-#define MXC_S_GCR_PM_MODE_SHUTDOWN                                             \
-	(MXC_V_GCR_PM_MODE_SHUTDOWN                                            \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
-#define MXC_V_GCR_PM_MODE_BACKUP                                               \
-	((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value                            \
-			   */
-#define MXC_S_GCR_PM_MODE_BACKUP                                               \
-	(MXC_V_GCR_PM_MODE_BACKUP                                              \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
-
-#define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */
-#define MXC_F_GCR_PM_GPIOWKEN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
-#define MXC_V_GCR_PM_GPIOWKEN_DIS                                              \
-	((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */
-#define MXC_S_GCR_PM_GPIOWKEN_DIS                                              \
-	(MXC_V_GCR_PM_GPIOWKEN_DIS                                             \
-	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */
-#define MXC_V_GCR_PM_GPIOWKEN_EN                                               \
-	((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value                            \
-			   */
-#define MXC_S_GCR_PM_GPIOWKEN_EN                                               \
-	(MXC_V_GCR_PM_GPIOWKEN_EN                                              \
-	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */
-
-#define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */
-#define MXC_F_GCR_PM_RTCWKEN                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask   \
-							 */
-#define MXC_V_GCR_PM_RTCWKEN_DIS                                               \
-	((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value                            \
-			   */
-#define MXC_S_GCR_PM_RTCWKEN_DIS                                               \
-	(MXC_V_GCR_PM_RTCWKEN_DIS                                              \
-	 << MXC_F_GCR_PM_RTCWKEN_POS)		  /**< PM_RTCWKEN_DIS Setting */
-#define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */
-#define MXC_S_GCR_PM_RTCWKEN_EN                                                \
-	(MXC_V_GCR_PM_RTCWKEN_EN                                               \
-	 << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */
-
-#define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */
-#define MXC_F_GCR_PM_HIRCPD                                                    \
-	((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
-#define MXC_V_GCR_PM_HIRCPD_ACTIVE                                             \
-	((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */
-#define MXC_S_GCR_PM_HIRCPD_ACTIVE                                             \
-	(MXC_V_GCR_PM_HIRCPD_ACTIVE                                            \
-	 << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
-#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                                          \
-	((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */
-#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP                                          \
-	(MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                                         \
-	 << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
-
-/**
- * Peripheral Clock Divider.
- */
-#define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */
-#define MXC_F_GCR_PCKDIV_AONCD                                                 \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_4                                           \
-	((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_4                                           \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_4                                          \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_8                                           \
-	((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_8                                           \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_8                                          \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_16                                          \
-	((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_16                                          \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_16                                         \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_32                                          \
-	((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_32                                          \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_32                                         \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
-
-/**
- * Peripheral Clock Disable.
- */
-#define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */
-#define MXC_F_GCR_PERCKCN0_GPIO0D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_GPIO0D_EN                                           \
-	((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_GPIO0D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_GPIO0D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS                                          \
-	((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_GPIO0D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */
-#define MXC_F_GCR_PERCKCN0_DMAD                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
-#define MXC_V_GCR_PERCKCN0_DMAD_EN                                             \
-	((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */
-#define MXC_S_GCR_PERCKCN0_DMAD_EN                                             \
-	(MXC_V_GCR_PERCKCN0_DMAD_EN                                            \
-	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */
-#define MXC_V_GCR_PERCKCN0_DMAD_DIS                                            \
-	((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */
-#define MXC_S_GCR_PERCKCN0_DMAD_DIS                                            \
-	(MXC_V_GCR_PERCKCN0_DMAD_DIS                                           \
-	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */
-#define MXC_F_GCR_PERCKCN0_SPI0D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
-#define MXC_V_GCR_PERCKCN0_SPI0D_EN                                            \
-	((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_SPI0D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_SPI0D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_SPI0D_DIS                                           \
-	((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_SPI0D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_SPI0D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */
-#define MXC_F_GCR_PERCKCN0_SPI1D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
-#define MXC_V_GCR_PERCKCN0_SPI1D_EN                                            \
-	((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_SPI1D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_SPI1D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_SPI1D_DIS                                           \
-	((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_SPI1D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_SPI1D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */
-#define MXC_F_GCR_PERCKCN0_UART0D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_UART0D_EN                                           \
-	((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_UART0D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_UART0D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_UART0D_DIS                                          \
-	((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_UART0D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_UART0D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */
-#define MXC_F_GCR_PERCKCN0_UART1D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_UART1D_EN                                           \
-	((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_UART1D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_UART1D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_UART1D_DIS                                          \
-	((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_UART1D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_UART1D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */
-#define MXC_F_GCR_PERCKCN0_I2C0D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
-#define MXC_V_GCR_PERCKCN0_I2C0D_EN                                            \
-	((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_I2C0D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_I2C0D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_I2C0D_DIS                                           \
-	((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_I2C0D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_I2C0D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */
-#define MXC_F_GCR_PERCKCN0_T0D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
-#define MXC_V_GCR_PERCKCN0_T0D_EN                                              \
-	((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T0D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T0D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T0D_DIS                                             \
-	((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T0D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T0D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */
-#define MXC_F_GCR_PERCKCN0_T1D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
-#define MXC_V_GCR_PERCKCN0_T1D_EN                                              \
-	((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T1D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T1D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T1D_DIS                                             \
-	((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T1D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T1D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */
-#define MXC_F_GCR_PERCKCN0_T2D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
-#define MXC_V_GCR_PERCKCN0_T2D_EN                                              \
-	((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T2D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T2D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T2D_DIS                                             \
-	((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T2D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T2D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */
-#define MXC_F_GCR_PERCKCN0_I2C1D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */
-#define MXC_V_GCR_PERCKCN0_I2C1D_EN                                            \
-	((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_I2C1D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_I2C1D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_I2C1D_DIS                                           \
-	((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_I2C1D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_I2C1D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */
-
-/**
- * Memory Clock Control Register.
- */
-#define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */
-#define MXC_F_GCR_MEMCKCN_FWS                                                  \
-	((uint32_t)(                                                           \
-		0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
-
-#define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM0LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                     \
-	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE     \
-						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                \
-	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**<                              \
-						MEMCKCN_SYSRAM0LS_LIGHT_SLEEP  \
-						Setting */
-
-#define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM1LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                     \
-	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE     \
-						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                                \
-	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**<                              \
-						MEMCKCN_SYSRAM1LS_LIGHT_SLEEP  \
-						Setting */
-
-#define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM2LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                     \
-	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE     \
-						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                                \
-	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**<                              \
-						MEMCKCN_SYSRAM2LS_LIGHT_SLEEP  \
-						Setting */
-
-#define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM3LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                     \
-	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE     \
-						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                                \
-	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**<                              \
-						MEMCKCN_SYSRAM3LS_LIGHT_SLEEP  \
-						Setting */
-
-#define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */
-#define MXC_F_GCR_MEMCKCN_ICACHELS                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS  \
-							   Mask */
-#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                                      \
-	((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE                                      \
-	(MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                                     \
-	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE       \
-					       Setting */
-#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                 \
-	((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                 \
-	(MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                \
-	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP  \
-					       Setting */
-
-/**
- * Memory Zeroize Control.
- */
-#define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */
-#define MXC_F_GCR_MEMZCN_SRAM0Z                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
-#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP                                            \
-	((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */
-#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP                                            \
-	(MXC_V_GCR_MEMZCN_SRAM0Z_NOP                                           \
-	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
-#define MXC_V_GCR_MEMZCN_SRAM0Z_START                                          \
-	((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */
-#define MXC_S_GCR_MEMZCN_SRAM0Z_START                                          \
-	(MXC_V_GCR_MEMZCN_SRAM0Z_START                                         \
-	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
-
-#define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */
-#define MXC_F_GCR_MEMZCN_ICACHEZ                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
-#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP                                           \
-	((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */
-#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP                                           \
-	(MXC_V_GCR_MEMZCN_ICACHEZ_NOP                                          \
-	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */
-#define MXC_V_GCR_MEMZCN_ICACHEZ_START                                         \
-	((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */
-#define MXC_S_GCR_MEMZCN_ICACHEZ_START                                         \
-	(MXC_V_GCR_MEMZCN_ICACHEZ_START                                        \
-	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */
-
-/**
- * System Status Register.
- */
-#define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */
-#define MXC_F_GCR_SYSST_ICECLOCK                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
-#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED                                      \
-	((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
-#define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED                                      \
-	(MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED                                     \
-	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting \
-					   */
-#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                        \
-	((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */
-#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED                                        \
-	(MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                       \
-	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting   \
-					   */
-
-#define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */
-#define MXC_F_GCR_SYSST_CODEINTERR                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR  \
-							   Mask */
-#define MXC_V_GCR_SYSST_CODEINTERR_NORM                                        \
-	((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */
-#define MXC_S_GCR_SYSST_CODEINTERR_NORM                                        \
-	(MXC_V_GCR_SYSST_CODEINTERR_NORM                                       \
-	 << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting \
-					     */
-#define MXC_V_GCR_SYSST_CODEINTERR_CODE                                        \
-	((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */
-#define MXC_S_GCR_SYSST_CODEINTERR_CODE                                        \
-	(MXC_V_GCR_SYSST_CODEINTERR_CODE                                       \
-	 << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_CODE Setting \
-					     */
-
-#define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */
-#define MXC_F_GCR_SYSST_SCMEMF                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */
-#define MXC_V_GCR_SYSST_SCMEMF_NORM                                            \
-	((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */
-#define MXC_S_GCR_SYSST_SCMEMF_NORM                                            \
-	(MXC_V_GCR_SYSST_SCMEMF_NORM                                           \
-	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */
-#define MXC_V_GCR_SYSST_SCMEMF_MEMORY                                          \
-	((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */
-#define MXC_S_GCR_SYSST_SCMEMF_MEMORY                                          \
-	(MXC_V_GCR_SYSST_SCMEMF_MEMORY                                         \
-	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */
-
-/**
- * Reset Register.
- */
-#define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */
-#define MXC_F_GCR_RSTR1_I2C1                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask   \
-							 */
-#define MXC_V_GCR_RSTR1_I2C1_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */
-#define MXC_S_GCR_RSTR1_I2C1_RESET                                             \
-	(MXC_V_GCR_RSTR1_I2C1_RESET                                            \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */
-#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR1_I2C1_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR1_I2C1_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */
-#define MXC_S_GCR_RSTR1_I2C1_BUSY                                              \
-	(MXC_V_GCR_RSTR1_I2C1_BUSY                                             \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */
-
-/**
- * Peripheral Clock Disable.
- */
-#define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */
-#define MXC_F_GCR_PERCKCN1_FLCD                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */
-#define MXC_V_GCR_PERCKCN1_FLCD_EN                                             \
-	((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */
-#define MXC_S_GCR_PERCKCN1_FLCD_EN                                             \
-	(MXC_V_GCR_PERCKCN1_FLCD_EN                                            \
-	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */
-#define MXC_V_GCR_PERCKCN1_FLCD_DIS                                            \
-	((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */
-#define MXC_S_GCR_PERCKCN1_FLCD_DIS                                            \
-	(MXC_V_GCR_PERCKCN1_FLCD_DIS                                           \
-	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */
-#define MXC_F_GCR_PERCKCN1_ICACHED                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED  \
-							   Mask */
-#define MXC_V_GCR_PERCKCN1_ICACHED_EN                                          \
-	((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */
-#define MXC_S_GCR_PERCKCN1_ICACHED_EN                                          \
-	(MXC_V_GCR_PERCKCN1_ICACHED_EN                                         \
-	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting   \
-					     */
-#define MXC_V_GCR_PERCKCN1_ICACHED_DIS                                         \
-	((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */
-#define MXC_S_GCR_PERCKCN1_ICACHED_DIS                                         \
-	(MXC_V_GCR_PERCKCN1_ICACHED_DIS                                        \
-	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting  \
-					     */
-
-/**
- * Event Enable Register.
- */
-#define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */
-#define MXC_F_GCR_EVTEN_DMAEVENT                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
-
-#define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */
-#define MXC_F_GCR_EVTEN_RXEVENT                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */
-
-/**
- * Revision Register.
- */
-#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */
-#define MXC_F_GCR_REVISION_REVISION                                            \
-	((uint32_t)(                                                           \
-		0xFFFFUL                                                       \
-		<< MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION    \
-							Mask */
-
-/**
- * System Status Interrupt Enable Register.
- */
-#define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */
-#define MXC_F_GCR_SYSSIE_ICEULIE                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */
-#define MXC_V_GCR_SYSSIE_ICEULIE_DIS                                           \
-	((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_ICEULIE_DIS                                           \
-	(MXC_V_GCR_SYSSIE_ICEULIE_DIS                                          \
-	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_ICEULIE_EN                                            \
-	((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */
-#define MXC_S_GCR_SYSSIE_ICEULIE_EN                                            \
-	(MXC_V_GCR_SYSSIE_ICEULIE_EN                                           \
-	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */
-
-#define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */
-#define MXC_F_GCR_SYSSIE_CIEIE                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */
-#define MXC_V_GCR_SYSSIE_CIEIE_DIS                                             \
-	((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_CIEIE_DIS                                             \
-	(MXC_V_GCR_SYSSIE_CIEIE_DIS                                            \
-	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_CIEIE_EN                                              \
-	((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */
-#define MXC_S_GCR_SYSSIE_CIEIE_EN                                              \
-	(MXC_V_GCR_SYSSIE_CIEIE_EN                                             \
-	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */
-
-#define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */
-#define MXC_F_GCR_SYSSIE_SCMFIE                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */
-#define MXC_V_GCR_SYSSIE_SCMFIE_DIS                                            \
-	((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_SCMFIE_DIS                                            \
-	(MXC_V_GCR_SYSSIE_SCMFIE_DIS                                           \
-	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_SCMFIE_EN                                             \
-	((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */
-#define MXC_S_GCR_SYSSIE_SCMFIE_EN                                             \
-	(MXC_V_GCR_SYSSIE_SCMFIE_EN                                            \
-	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */
-
-#endif /* _GCR_REGS_H_ */
diff --git a/chip/max32660/gpio_chip.c b/chip/max32660/gpio_chip.c
deleted file mode 100644
index 5fe38cd657..0000000000
--- a/chip/max32660/gpio_chip.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "switch.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "registers.h"
-#include "gpio_regs.h"
-
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
-
-/* 0-terminated list of GPIO base addresses */
-static mxc_gpio_regs_t *gpio_bases[] = {MXC_GPIO0, 0};
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-			enum gpio_alternate_func func)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port);
-
-	switch (func) {
-	case GPIO_ALT_FUNC_1:
-		gpio->en_clr = mask;
-		gpio->en1_clr = mask;
-		break;
-	case GPIO_ALT_FUNC_2:
-		gpio->en_clr = mask;
-		gpio->en1_set = mask;
-		break;
-	case GPIO_ALT_FUNC_3:
-		gpio->en_set = mask;
-		gpio->en1_set = mask;
-		break;
-	default:
-	    /* Default as input */
-		gpio->out_en_clr = mask;
-		gpio->en_set = mask;
-		gpio->en1_clr = mask;
-		break;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	return (gpio->in & gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	if (value) {
-		gpio->out_set = gpio_list[signal].mask;
-	} else {
-		gpio->out_clr = gpio_list[signal].mask;
-	}
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port);
-
-	/* Setup for either an output or input. */
-	if (flags & GPIO_OUTPUT) {
-		gpio->out_en_set = mask;
-		gpio->en_set = mask;
-		gpio->en1_clr = mask;
-	} else {
-		gpio->out_en_clr = mask;
-		gpio->en_set = mask;
-		gpio->en1_clr = mask;
-	}
-
-	/* Handle pull up, pull down or neither. */
-	if (flags & GPIO_PULL_UP) {
-		gpio->pad_cfg1 |= mask;
-		gpio->pad_cfg2 &= ~mask;
-		gpio->ps |= mask;
-	} else if (flags & GPIO_PULL_DOWN) {
-		gpio->pad_cfg1 &= ~mask;
-		gpio->pad_cfg2 |= mask;
-		gpio->ps &= ~mask;
-	} else {
-		/* No pull up/down */
-		gpio->pad_cfg1 &= ~mask;
-		gpio->pad_cfg2 &= ~mask;
-		gpio->ps &= ~mask;
-	}
-
-	/* Handle setting up level interrupts. */
-	if (flags & GPIO_INT_F_HIGH) {
-		/* Level triggered mode. */
-		gpio->int_mod &= ~mask;
-		/* Level high generates interrupt. */
-		gpio->int_pol |= mask;
-	} else if (flags & GPIO_INT_F_LOW) {
-		/* Level triggered mode. */
-		gpio->int_mod &= ~mask;
-		/* Level low generates interrupt. */
-		gpio->int_pol &= ~mask;
-	}
-
-	/* Handle setting up edge interrupts. */
-	if (flags & GPIO_INT_F_RISING) {
-		/* Edge triggered mode. */
-		gpio->int_mod |= mask;
-		/* Rising edge generates interrupt. */
-		gpio->int_pol |= mask;
-	} else if (flags & GPIO_INT_F_FALLING) {
-		/* Edge triggered mode. */
-		gpio->int_mod |= mask;
-		/* Falling edge generates interrupt. */
-		gpio->int_pol &= ~mask;
-	}
-
-	/* Handle interrupting on both edges. */
-	if ((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) {
-		/* Dual edge triggered mode. */
-		gpio->int_dual_edge |= mask;
-	} else {
-		/* Not dual edge triggered mode. */
-		gpio->int_dual_edge &= ~mask;
-	}
-
-	/* Set the gpio pin high or low. */
-	if (flags & GPIO_HIGH) {
-		gpio->out_set = mask;
-	} else if (flags & GPIO_LOW) {
-		gpio->out_clr = mask;
-	}
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	gpio->int_en_set = gpio_list[signal].mask;
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	gpio->int_en_clr = gpio_list[signal].mask;
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	gpio->int_clr = gpio_list[signal].mask;
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int i;
-
-	/* Mask all GPIO interrupts */
-	for (i = 0; gpio_bases[i]; i++)
-		gpio_bases[i]->int_en = 0;
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-static void gpio_init(void)
-{
-	/*
-	 * Enable global GPIO0 Port interrupt. Note that interrupts still need to be
-	 * enabled at the per pin level.
-	 */
-	task_enable_irq(EC_GPIO0_IRQn);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle a GPIO interrupt.
- *
- * port		GPIO port
- * mis		Masked interrupt status value for that port
- */
-static void gpio_interrupt(int port, uint32_t mis)
-{
-	int i = 0;
-	const struct gpio_info *g = gpio_list;
-
-	for (i = 0; i < GPIO_IH_COUNT && mis; i++, g++) {
-		if (port == g->port && (mis & g->mask)) {
-			gpio_irq_handlers[i](i);
-			mis &= ~g->mask;
-		}
-	}
-}
-
-/**
- * Handlers for each GPIO port. Read the interrupt status, call the common GPIO
- * interrupt handler and clear the GPIO hardware interrupt status.
- */
-#define GPIO_IRQ_FUNC(irqfunc, gpiobase)                                       \
-	void irqfunc(void)                                                     \
-	{                                                                      \
-		mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpiobase);           \
-		uint32_t mis = gpio->int_stat;                                 \
-		gpio_interrupt(gpiobase, mis);                                 \
-		gpio->int_clr = mis;                                           \
-	}
-
-GPIO_IRQ_FUNC(__gpio_0_interrupt, PORT_0);
-#undef GPIO_IRQ_FUNC
-DECLARE_IRQ(EC_GPIO0_IRQn, __gpio_0_interrupt, 1);
diff --git a/chip/max32660/gpio_regs.h b/chip/max32660/gpio_regs.h
deleted file mode 100644
index 1c6fcf7a71..0000000000
--- a/chip/max32660/gpio_regs.h
+++ /dev/null
@@ -1,866 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the GPIO Peripheral
- * Module */
-
-#ifndef _GPIO_REGS_H_
-#define _GPIO_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * gpio
- * Individual I/O for each GPIO
- */
-
-/**
- * gpio_registers
- * Structure type to access the GPIO Registers.
- */
-typedef struct {
-	__IO uint32_t en;     /**< <tt>\b 0x00:<\tt> GPIO EN Register */
-	__IO uint32_t en_set; /**< <tt>\b 0x04:<\tt> GPIO EN_SET Register */
-	__IO uint32_t en_clr; /**< <tt>\b 0x08:<\tt> GPIO EN_CLR Register */
-	__IO uint32_t out_en; /**< <tt>\b 0x0C:<\tt> GPIO OUT_EN Register */
-	__IO uint32_t
-		out_en_set; /**< <tt>\b 0x10:<\tt> GPIO OUT_EN_SET Register */
-	__IO uint32_t
-		out_en_clr;   /**< <tt>\b 0x14:<\tt> GPIO OUT_EN_CLR Register */
-	__IO uint32_t out;    /**< <tt>\b 0x18:<\tt> GPIO OUT Register */
-	__O uint32_t out_set; /**< <tt>\b 0x1C:<\tt> GPIO OUT_SET Register */
-	__O uint32_t out_clr; /**< <tt>\b 0x20:<\tt> GPIO OUT_CLR Register */
-	__I uint32_t in;      /**< <tt>\b 0x24:<\tt> GPIO IN Register */
-	__IO uint32_t int_mod; /**< <tt>\b 0x28:<\tt> GPIO INT_MOD Register */
-	__IO uint32_t int_pol; /**< <tt>\b 0x2C:<\tt> GPIO INT_POL Register */
-	__R uint32_t rsv_0x30;
-	__IO uint32_t int_en; /**< <tt>\b 0x34:<\tt> GPIO INT_EN Register */
-	__IO uint32_t
-		int_en_set; /**< <tt>\b 0x38:<\tt> GPIO INT_EN_SET Register */
-	__IO uint32_t
-		int_en_clr; /**< <tt>\b 0x3C:<\tt> GPIO INT_EN_CLR Register */
-	__I uint32_t int_stat; /**< <tt>\b 0x40:<\tt> GPIO INT_STAT Register */
-	__R uint32_t rsv_0x44;
-	__IO uint32_t int_clr; /**< <tt>\b 0x48:<\tt> GPIO INT_CLR Register */
-	__IO uint32_t wake_en; /**< <tt>\b 0x4C:<\tt> GPIO WAKE_EN Register */
-	__IO uint32_t
-		wake_en_set; /**< <tt>\b 0x50:<\tt> GPIO WAKE_EN_SET Register */
-	__IO uint32_t
-		wake_en_clr; /**< <tt>\b 0x54:<\tt> GPIO WAKE_EN_CLR Register */
-	__R uint32_t rsv_0x58;
-	__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:<\tt> GPIO INT_DUAL_EDGE
-					Register */
-	__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:<\tt> GPIO PAD_CFG1 Register */
-	__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:<\tt> GPIO PAD_CFG2 Register */
-	__IO uint32_t en1;      /**< <tt>\b 0x68:<\tt> GPIO EN1 Register */
-	__IO uint32_t en1_set;  /**< <tt>\b 0x6C:<\tt> GPIO EN1_SET Register */
-	__IO uint32_t en1_clr;  /**< <tt>\b 0x70:<\tt> GPIO EN1_CLR Register */
-	__IO uint32_t en2;      /**< <tt>\b 0x74:<\tt> GPIO EN2 Register */
-	__IO uint32_t en2_set;  /**< <tt>\b 0x78:<\tt> GPIO EN2_SET Register */
-	__IO uint32_t en2_clr;  /**< <tt>\b 0x7C:<\tt> GPIO EN2_CLR Register */
-	__R uint32_t rsv_0x80_0xa7[10];
-	__IO uint32_t is;  /**< <tt>\b 0xA8:<\tt> GPIO IS Register */
-	__IO uint32_t sr;  /**< <tt>\b 0xAC:<\tt> GPIO SR Register */
-	__IO uint32_t ds;  /**< <tt>\b 0xB0:<\tt> GPIO DS Register */
-	__IO uint32_t ds1; /**< <tt>\b 0xB4:<\tt> GPIO DS1 Register */
-	__IO uint32_t ps;  /**< <tt>\b 0xB8:<\tt> GPIO PS Register */
-	__R uint32_t rsv_0xbc;
-	__IO uint32_t vssel; /**< <tt>\b 0xC0:<\tt> GPIO VSSEL Register */
-} mxc_gpio_regs_t;
-
-#define PIN_0 ((uint32_t)(1UL << 0))   /**< Pin 0 Define */
-#define PIN_1 ((uint32_t)(1UL << 1))   /**< Pin 1 Define */
-#define PIN_2 ((uint32_t)(1UL << 2))   /**< Pin 2 Define */
-#define PIN_3 ((uint32_t)(1UL << 3))   /**< Pin 3 Define */
-#define PIN_4 ((uint32_t)(1UL << 4))   /**< Pin 4 Define */
-#define PIN_5 ((uint32_t)(1UL << 5))   /**< Pin 5 Define */
-#define PIN_6 ((uint32_t)(1UL << 6))   /**< Pin 6 Define */
-#define PIN_7 ((uint32_t)(1UL << 7))   /**< Pin 7 Define */
-#define PIN_8 ((uint32_t)(1UL << 8))   /**< Pin 8 Define */
-#define PIN_9 ((uint32_t)(1UL << 9))   /**< Pin 9 Define */
-#define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */
-#define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */
-#define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */
-#define PIN_13 ((uint32_t)(1UL << 13)) /**< Pin 13 Define */
-#define PIN_14 ((uint32_t)(1UL << 14)) /**< Pin 14 Define */
-#define PIN_15 ((uint32_t)(1UL << 15)) /**< Pin 15 Define */
-#define PIN_16 ((uint32_t)(1UL << 16)) /**< Pin 16 Define */
-#define PIN_17 ((uint32_t)(1UL << 17)) /**< Pin 17 Define */
-#define PIN_18 ((uint32_t)(1UL << 18)) /**< Pin 18 Define */
-#define PIN_19 ((uint32_t)(1UL << 19)) /**< Pin 19 Define */
-#define PIN_20 ((uint32_t)(1UL << 20)) /**< Pin 20 Define */
-#define PIN_21 ((uint32_t)(1UL << 21)) /**< Pin 21 Define */
-#define PIN_22 ((uint32_t)(1UL << 22)) /**< Pin 22 Define */
-#define PIN_23 ((uint32_t)(1UL << 23)) /**< Pin 23 Define */
-#define PIN_24 ((uint32_t)(1UL << 24)) /**< Pin 24 Define */
-#define PIN_25 ((uint32_t)(1UL << 25)) /**< Pin 25 Define */
-#define PIN_26 ((uint32_t)(1UL << 26)) /**< Pin 26 Define */
-#define PIN_27 ((uint32_t)(1UL << 27)) /**< Pin 27 Define */
-#define PIN_28 ((uint32_t)(1UL << 28)) /**< Pin 28 Define */
-#define PIN_29 ((uint32_t)(1UL << 29)) /**< Pin 29 Define */
-#define PIN_30 ((uint32_t)(1UL << 30)) /**< Pin 30 Define */
-#define PIN_31 ((uint32_t)(1UL << 31)) /**< Pin 31 Define */
-
-/**
- * Enumeration type for the GPIO Function Type
- */
-typedef enum {
-	GPIO_FUNC_IN,   /**< GPIO Input */
-	GPIO_FUNC_OUT,  /**< GPIO Output */
-	GPIO_FUNC_ALT1, /**< Alternate Function Selection */
-	GPIO_FUNC_ALT2, /**< Alternate Function Selection */
-	GPIO_FUNC_ALT3, /**< Alternate Function Selection */
-	GPIO_FUNC_ALT4, /**< Alternate Function Selection */
-} gpio_func_t;
-
-/**
- * Enumeration type for the type of GPIO pad on a given pin.
- */
-typedef enum {
-	GPIO_PAD_NONE,      /**< No pull-up or pull-down */
-	GPIO_PAD_PULL_UP,   /**< Set pad to weak pull-up */
-	GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */
-} gpio_pad_t;
-
-/**
- * Structure type for configuring a GPIO port.
- */
-typedef struct {
-	uint32_t port;    /**< Index of GPIO port */
-	uint32_t mask;    /**< Pin mask (multiple pins may be set) */
-	gpio_func_t func; /**< Function type */
-	gpio_pad_t pad;   /**< Pad type */
-} gpio_cfg_t;
-
-typedef enum { GPIO_INTERRUPT_LEVEL, GPIO_INTERRUPT_EDGE } gpio_int_mode_t;
-
-typedef enum {
-	GPIO_INTERRUPT_FALLING = 0, /**< Interrupt triggers on falling edge */
-	GPIO_INTERRUPT_HIGH = GPIO_INTERRUPT_FALLING, /**< Interrupt triggers
-							 when level is high */
-	GPIO_INTERRUPT_RISING, /**< Interrupt triggers on rising edge */
-	GPIO_INTERRUPT_LOW = GPIO_INTERRUPT_RISING, /**< Interrupt triggers when
-						       level is low */
-	GPIO_INTERRUPT_BOTH /**< Interrupt triggers on either edge */
-} gpio_int_pol_t;
-
-/* Register offsets for module GPIO */
-#define MXC_R_GPIO_EN                                                          \
-	((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x000 */
-#define MXC_R_GPIO_EN_SET                                                      \
-	((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x004 */
-#define MXC_R_GPIO_EN_CLR                                                      \
-	((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x008 */
-#define MXC_R_GPIO_OUT_EN                                                      \
-	((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x00C */
-#define MXC_R_GPIO_OUT_EN_SET                                                  \
-	((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x010 */
-#define MXC_R_GPIO_OUT_EN_CLR                                                  \
-	((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x014 */
-#define MXC_R_GPIO_OUT                                                         \
-	((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x018 */
-#define MXC_R_GPIO_OUT_SET                                                     \
-	((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x01C */
-#define MXC_R_GPIO_OUT_CLR                                                     \
-	((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x020 */
-#define MXC_R_GPIO_IN                                                          \
-	((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x024 */
-#define MXC_R_GPIO_INT_MOD                                                     \
-	((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x028 */
-#define MXC_R_GPIO_INT_POL                                                     \
-	((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x02C */
-#define MXC_R_GPIO_INT_EN                                                      \
-	((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x034 */
-#define MXC_R_GPIO_INT_EN_SET                                                  \
-	((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x038 */
-#define MXC_R_GPIO_INT_EN_CLR                                                  \
-	((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x03C */
-#define MXC_R_GPIO_INT_STAT                                                    \
-	((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x040 */
-#define MXC_R_GPIO_INT_CLR                                                     \
-	((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x048 */
-#define MXC_R_GPIO_WAKE_EN                                                     \
-	((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x04C */
-#define MXC_R_GPIO_WAKE_EN_SET                                                 \
-	((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x050 */
-#define MXC_R_GPIO_WAKE_EN_CLR                                                 \
-	((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x054 */
-#define MXC_R_GPIO_INT_DUAL_EDGE                                               \
-	((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x05C */
-#define MXC_R_GPIO_PAD_CFG1                                                    \
-	((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x060 */
-#define MXC_R_GPIO_PAD_CFG2                                                    \
-	((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x064 */
-#define MXC_R_GPIO_EN1                                                         \
-	((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x068 */
-#define MXC_R_GPIO_EN1_SET                                                     \
-	((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x06C */
-#define MXC_R_GPIO_EN1_CLR                                                     \
-	((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x070 */
-#define MXC_R_GPIO_EN2                                                         \
-	((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x074 */
-#define MXC_R_GPIO_EN2_SET                                                     \
-	((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x078 */
-#define MXC_R_GPIO_EN2_CLR                                                     \
-	((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x07C */
-#define MXC_R_GPIO_IS                                                          \
-	((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0A8 */
-#define MXC_R_GPIO_SR                                                          \
-	((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0AC */
-#define MXC_R_GPIO_DS                                                          \
-	((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0B0 */
-#define MXC_R_GPIO_DS1                                                         \
-	((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0B4 */
-#define MXC_R_GPIO_PS                                                          \
-	((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0B8 */
-#define MXC_R_GPIO_VSSEL                                                       \
-	((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0C0 */
-
-/**
- * GPIO Function Enable Register. Each bit controls the GPIO_EN
- * setting for one GPIO pin on the associated port.
- */
-#define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */
-#define MXC_F_GPIO_EN_GPIO_EN                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */
-#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                                        \
-	((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */
-#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE                                        \
-	(MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                                       \
-	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */
-#define MXC_V_GPIO_EN_GPIO_EN_GPIO                                             \
-	((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */
-#define MXC_S_GPIO_EN_GPIO_EN_GPIO                                             \
-	(MXC_V_GPIO_EN_GPIO_EN_GPIO                                            \
-	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */
-
-/**
- * GPIO Set Function Enable Register. Writing a 1 to one or more bits
- * in this register sets the bits in the same positions in GPIO_EN to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */
-#define MXC_F_GPIO_EN_SET_ALL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */
-
-/**
- * GPIO Clear Function Enable Register. Writing a 1 to one or more
- * bits in this register clears the bits in the same positions in GPIO_EN to 0,
- * without affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */
-#define MXC_F_GPIO_EN_CLR_ALL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */
-
-/**
- * GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN
- * setting for one GPIO pin in the associated port.
- */
-#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS                                      \
-	0 /**< OUT_EN_GPIO_OUT_EN Position                                     \
-	   */
-#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN                                          \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN \
-							  Mask */
-#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                      \
-	((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
-#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                      \
-	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                     \
-	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS     \
-						  Setting */
-#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                       \
-	((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
-#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN                                       \
-	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                      \
-	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN      \
-						  Setting */
-
-/**
- * GPIO Output Enable Set Function Enable Register. Writing a 1 to one
- * or more bits in this register sets the bits in the same positions in
- * GPIO_OUT_EN to 1, without affecting other bits in that register.
- */
-#define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */
-#define MXC_F_GPIO_OUT_EN_SET_ALL                                              \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
-
-/**
- * GPIO Output Enable Clear Function Enable Register. Writing a 1 to
- * one or more bits in this register clears the bits in the same positions in
- * GPIO_OUT_EN to 0, without affecting other bits in that register.
- */
-#define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */
-#define MXC_F_GPIO_OUT_EN_CLR_ALL                                              \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
-
-/**
- * GPIO Output Register. Each bit controls the GPIO_OUT setting for
- * one pin in the associated port.  This register can be written either
- * directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
- */
-#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
-#define MXC_F_GPIO_OUT_GPIO_OUT                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
-#define MXC_V_GPIO_OUT_GPIO_OUT_LOW                                            \
-	((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
-#define MXC_S_GPIO_OUT_GPIO_OUT_LOW                                            \
-	(MXC_V_GPIO_OUT_GPIO_OUT_LOW                                           \
-	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
-#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH                                           \
-	((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
-#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                                           \
-	(MXC_V_GPIO_OUT_GPIO_OUT_HIGH                                          \
-	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
-
-/**
- * GPIO Output Set. Writing a 1 to one or more bits in this register
- * sets the bits in the same positions in GPIO_OUT to 1, without affecting other
- * bits in that register.
- */
-#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS                                    \
-	0 /**< OUT_SET_GPIO_OUT_SET Position */
-#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**<                    \
-							    OUT_SET_GPIO_OUT_SET \
-							    Mask */
-#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                     \
-	((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
-#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO                                     \
-	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                    \
-	 << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO  \
-						    Setting */
-#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET                                    \
-	((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
-#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET                                    \
-	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET                                   \
-	 << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET \
-						    Setting */
-/**
- * GPIO Output Clear. Writing a 1 to one or more bits in this register
- * clears the bits in the same positions in GPIO_OUT to 0, without affecting
- * other bits in that register.
- */
-#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS                                    \
-	0 /**< OUT_CLR_GPIO_OUT_CLR Position */
-#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**<                    \
-							    OUT_CLR_GPIO_OUT_CLR \
-							    Mask */
-
-/**
- * GPIO Input Register. Read-only register to read from the logic
- * states of the GPIO pins on this port.
- */
-#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
-#define MXC_F_GPIO_IN_GPIO_IN                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
-
-/**
- * GPIO Interrupt Mode Register. Each bit in this register controls
- * the interrupt mode setting for the associated GPIO pin on this port.
- */
-#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS                                    \
-	0 /**< INT_MOD_GPIO_INT_MOD Position */
-#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**<                    \
-							    INT_MOD_GPIO_INT_MOD \
-							    Mask */
-#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                  \
-	((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
-#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                  \
-	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                 \
-	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                          \
-						    INT_MOD_GPIO_INT_MOD_LEVEL \
-						    Setting */
-#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                   \
-	((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
-#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                   \
-	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                  \
-	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                          \
-						    INT_MOD_GPIO_INT_MOD_EDGE  \
-						    Setting */
-
-/**
- * GPIO Interrupt Polarity Register. Each bit in this register
- * controls the interrupt polarity setting for one GPIO pin in the associated
- * port.
- */
-#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS                                    \
-	0 /**< INT_POL_GPIO_INT_POL Position */
-#define MXC_F_GPIO_INT_POL_GPIO_INT_POL                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**<                    \
-							    INT_POL_GPIO_INT_POL \
-							    Mask */
-#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING                                \
-	((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
-#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING                                  \
-	(MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING                                 \
-	 << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**<                            \
-						    INT_POL_GPIO_INT_POL_FALLING \
-						    Setting */
-#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING                                 \
-	((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
-#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING                                  \
-	(MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING                                 \
-	 << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**<                           \
-						    INT_POL_GPIO_INT_POL_RISING \
-						    Setting */
-
-/**
- * GPIO Interrupt Enable Register. Each bit in this register controls
- * the GPIO interrupt enable for the associated pin on the GPIO port.
- */
-#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS                                      \
-	0 /**< INT_EN_GPIO_INT_EN Position                                     \
-	   */
-#define MXC_F_GPIO_INT_EN_GPIO_INT_EN                                          \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN \
-							  Mask */
-#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                      \
-	((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
-#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS                                      \
-	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                     \
-	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS     \
-						  Setting */
-#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                       \
-	((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
-#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN                                       \
-	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                      \
-	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN      \
-						  Setting */
-
-/**
- * GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this
- * register sets the bits in the same positions in GPIO_INT_EN to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS                              \
-	0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
-#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET                                                \
-	((uint32_t)(                                                                         \
-		0xFFFFFFFFUL                                                                 \
-		<< MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**<                          \
-								  INT_EN_SET_GPIO_INT_EN_SET \
-								  Mask */
-#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                               \
-	((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
-#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                                        \
-	(MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                                       \
-	 << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**<                             \
-							  INT_EN_SET_GPIO_INT_EN_SET_NO \
-							  Setting */
-#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                              \
-	((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
-#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                                        \
-	(MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                                       \
-	 << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**<                              \
-							  INT_EN_SET_GPIO_INT_EN_SET_SET \
-							  Setting */
-/**
- * GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in
- * this register clears the bits in the same positions in GPIO_INT_EN to 0,
- * without affecting other bits in that register.
- */
-#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS                              \
-	0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
-#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR                                                \
-	((uint32_t)(                                                                         \
-		0xFFFFFFFFUL                                                                 \
-		<< MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**<                          \
-								  INT_EN_CLR_GPIO_INT_EN_CLR \
-								  Mask */
-#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                               \
-	((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
-#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                                        \
-	(MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                                       \
-	 << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**<                             \
-							  INT_EN_CLR_GPIO_INT_EN_CLR_NO \
-							  Setting */
-#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                            \
-	((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
-#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                                        \
-	(MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                                       \
-	 << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**<                                \
-							  INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \
-							  Setting */
-/**
- * GPIO Interrupt Status Register. Each bit in this register contains
- * the pending interrupt status for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS                                  \
-	0 /**< INT_STAT_GPIO_INT_STAT Position */
-#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**<                      \
-							      INT_STAT_GPIO_INT_STAT \
-							      Mask */
-#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO                                   \
-	((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
-#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO                                    \
-	(MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO                                   \
-	 << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**<                         \
-						      INT_STAT_GPIO_INT_STAT_NO \
-						      Setting */
-#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                              \
-	((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
-#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                                    \
-	(MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                                   \
-	 << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**<                              \
-						      INT_STAT_GPIO_INT_STAT_PENDING \
-						      Setting */
-
-/**
- * GPIO Status Clear. Writing a 1 to one or more bits in this register
- * clears the bits in the same positions in GPIO_INT_STAT to 0, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */
-#define MXC_F_GPIO_INT_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
-
-/**
- * GPIO Wake Enable Register. Each bit in this register controls the
- * PMU wakeup enable for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS                                    \
-	0 /**< WAKE_EN_GPIO_WAKE_EN Position */
-#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**<                    \
-							    WAKE_EN_GPIO_WAKE_EN \
-							    Mask */
-#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                    \
-	((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
-#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                    \
-	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                   \
-	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS \
-						    Setting */
-#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                     \
-	((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
-#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                     \
-	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                    \
-	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN  \
-						    Setting */
-
-/**
- * GPIO Wake Enable Set. Writing a 1 to one or more bits in this
- * register sets the bits in the same positions in GPIO_WAKE_EN to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */
-#define MXC_F_GPIO_WAKE_EN_SET_ALL                                             \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL   \
-							   Mask */
-
-/**
- * GPIO Wake Enable Clear. Writing a 1 to one or more bits in this
- * register clears the bits in the same positions in GPIO_WAKE_EN to 0, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */
-#define MXC_F_GPIO_WAKE_EN_CLR_ALL                                             \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL   \
-							   Mask */
-
-/**
- * GPIO Interrupt Dual Edge Mode Register. Each bit in this register
- * selects dual edge mode for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS                        \
-	0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
-#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE                                                      \
-	((uint32_t)(                                                                                     \
-		0xFFFFFFFFUL                                                                             \
-		<< MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**<                                \
-									INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \
-									Mask                             \
-								      */
-#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                         \
-	((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
-#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                                              \
-	(MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                                             \
-	 << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**<                                   \
-								INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \
-								Setting */
-#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                         \
-	((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
-#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                                              \
-	(MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                                             \
-	 << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**<                                   \
-								INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \
-								Setting */
-
-/**
- * GPIO Input Mode Config 1. Each bit in this register enables the
- * weak pull-up for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS                                  \
-	0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
-#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**<                      \
-							      PAD_CFG1_GPIO_PAD_CFG1 \
-							      Mask */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                            \
-	((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
-#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                                    \
-	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                                   \
-	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                                \
-						      PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \
-						      Setting */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                   \
-	((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
-#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                    \
-	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                   \
-	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                         \
-						      PAD_CFG1_GPIO_PAD_CFG1_PU \
-						      Setting */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                   \
-	((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
-#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                    \
-	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                   \
-	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                         \
-						      PAD_CFG1_GPIO_PAD_CFG1_PD \
-						      Setting */
-
-/**
- * GPIO Input Mode Config 2. Each bit in this register enables the
- * weak pull-up for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS                                  \
-	0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
-#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**<                      \
-							      PAD_CFG2_GPIO_PAD_CFG2 \
-							      Mask */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                            \
-	((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
-#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                                    \
-	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                                   \
-	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                                \
-						      PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \
-						      Setting */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                   \
-	((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
-#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                    \
-	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                   \
-	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                         \
-						      PAD_CFG2_GPIO_PAD_CFG2_PU \
-						      Setting */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                   \
-	((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
-#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                    \
-	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                   \
-	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                         \
-						      PAD_CFG2_GPIO_PAD_CFG2_PD \
-						      Setting */
-
-/**
- * GPIO Alternate Function Enable Register. Each bit in this register
- * selects between primary/secondary functions for the associated GPIO pin in
- * this port.
- */
-#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
-#define MXC_F_GPIO_EN1_GPIO_EN1                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
-#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                                        \
-	((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
-#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                                        \
-	(MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                                       \
-	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
-#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                      \
-	((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
-#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY                                      \
-	(MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                     \
-	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting   \
-					  */
-
-/**
- * GPIO Alternate Function Set. Writing a 1 to one or more bits in
- * this register sets the bits in the same positions in GPIO_EN1 to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
-#define MXC_F_GPIO_EN1_SET_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
-
-/**
- * GPIO Alternate Function Clear. Writing a 1 to one or more bits in
- * this register clears the bits in the same positions in GPIO_EN1 to 0, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
-#define MXC_F_GPIO_EN1_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
-
-/**
- * GPIO Alternate Function Enable Register. Each bit in this register
- * selects between primary/secondary functions for the associated GPIO pin in
- * this port.
- */
-#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
-#define MXC_F_GPIO_EN2_GPIO_EN2                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
-#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                                        \
-	((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
-#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                                        \
-	(MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                                       \
-	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
-#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                      \
-	((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
-#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY                                      \
-	(MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                     \
-	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting   \
-					  */
-
-/**
- * GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in
- * this register sets the bits in the same positions in GPIO_EN2 to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
-#define MXC_F_GPIO_EN2_SET_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
-
-/**
- * GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits
- * in this register clears the bits in the same positions in GPIO_EN2 to 0,
- * without affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
-#define MXC_F_GPIO_EN2_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
-
-/**
- * GPIO Drive Strength  Register. Each bit in this register selects
- * the drive strength for the associated GPIO pin in this port. Refer to the
- * Datasheet for sink/source current of GPIO pins in each mode.
- */
-#define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */
-#define MXC_F_GPIO_DS_DS                                                       \
-	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */
-#define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */
-#define MXC_S_GPIO_DS_DS_LD                                                    \
-	(MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */
-#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL)	 /**< DS_DS_HD Value */
-#define MXC_S_GPIO_DS_DS_HD                                                    \
-	(MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */
-
-/**
- * GPIO Drive Strength 1 Register. Each bit in this register selects
- * the drive strength for the associated GPIO pin in this port. Refer to the
- * Datasheet for sink/source current of GPIO pins in each mode.
- */
-#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */
-#define MXC_F_GPIO_DS1_ALL                                                     \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
-
-/**
- * GPIO Pull Select Mode.
- */
-#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
-#define MXC_F_GPIO_PS_ALL                                                      \
-	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask   \
-							     */
-
-/**
- * GPIO Voltage Select.
- */
-#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
-#define MXC_F_GPIO_VSSEL_ALL                                                   \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
-
-#endif /* _GPIO_REGS_H_ */
diff --git a/chip/max32660/hwtimer_chip.c b/chip/max32660/hwtimer_chip.c
deleted file mode 100644
index 5417e161b2..0000000000
--- a/chip/max32660/hwtimer_chip.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 HW Timer module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "task.h"
-#include "timer.h"
-#include "registers.h"
-#include "tmr_regs.h"
-#include "gcr_regs.h"
-
-/* Define the rollover timer */
-#define TMR_ROLLOVER MXC_TMR0
-#define TMR_ROLLOVER_IRQ EC_TMR0_IRQn
-
-/* Define the event timer */
-#define TMR_EVENT MXC_TMR1
-#define TMR_EVENT_IRQ EC_TMR1_IRQn
-
-#define ROLLOVER_EVENT 1
-#define NOT_ROLLOVER_EVENT 0
-
-#define TMR_PRESCALER MXC_V_TMR_CN_PRES_DIV8
-#define TMR_DIV (1 << TMR_PRESCALER)
-
-/* The frequency of timer using the prescaler */
-#define TIMER_FREQ_HZ (PeripheralClock / TMR_DIV)
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-static uint32_t last_deadline;
-
-/* brief Timer prescaler values */
-enum tmr_pres {
-	TMR_PRES_1 = MXC_V_TMR_CN_PRES_DIV1,     /// Divide input clock by 1
-	TMR_PRES_2 = MXC_V_TMR_CN_PRES_DIV2,     /// Divide input clock by 2
-	TMR_PRES_4 = MXC_V_TMR_CN_PRES_DIV4,     /// Divide input clock by 4
-	TMR_PRES_8 = MXC_V_TMR_CN_PRES_DIV8,     /// Divide input clock by 8
-	TMR_PRES_16 = MXC_V_TMR_CN_PRES_DIV16,   /// Divide input clock by 16
-	TMR_PRES_32 = MXC_V_TMR_CN_PRES_DIV32,   /// Divide input clock by 32
-	TMR_PRES_64 = MXC_V_TMR_CN_PRES_DIV64,   /// Divide input clock by 64
-	TMR_PRES_128 = MXC_V_TMR_CN_PRES_DIV128, /// Divide input clock by 128
-	TMR_PRES_256 =
-		(0x20 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 256
-	TMR_PRES_512 =
-		(0x21 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 512
-	TMR_PRES_1024 =
-		(0x22 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 1024
-	TMR_PRES_2048 =
-		(0x23 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 2048
-	TMR_PRES_4096 =
-		(0x24 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 4096
-};
-
-/* Timer modes */
-enum tmr_mode {
-	TMR_MODE_ONESHOT = MXC_V_TMR_CN_TMODE_ONESHOT, /// Timer Mode ONESHOT
-	TMR_MODE_CONTINUOUS =
-		MXC_V_TMR_CN_TMODE_CONTINUOUS,	 /// Timer Mode CONTINUOUS
-	TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, /// Timer Mode COUNTER
-	TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM,	 /// Timer Mode PWM
-	TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, /// Timer Mode CAPTURE
-	TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, /// Timer Mode COMPARE
-	TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED,     /// Timer Mode GATED
-	TMR_MODE_CAPTURE_COMPARE =
-		MXC_V_TMR_CN_TMODE_CAPTURECOMPARE /// Timer Mode CAPTURECOMPARE
-};
-
-/*
- * Calculate the number of microseconds for a given timer tick
- */
-static inline uint32_t ticks_to_usecs(uint32_t ticks)
-{
-	return (uint64_t)ticks * SECOND / TIMER_FREQ_HZ;
-}
-
-/*
- * Calculate the number of timer ticks for a given microsecond value
- */
-static inline uint32_t usecs_to_ticks(uint32_t usecs)
-{
-	return ((uint64_t)(usecs)*TIMER_FREQ_HZ / SECOND);
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint32_t event_time_us;
-	uint32_t event_time_ticks;
-	uint32_t time_now;
-
-	last_deadline = deadline;
-	time_now = __hw_clock_source_read();
-
-	/* check if the deadline has rolled over */
-	if (deadline < time_now) {
-		event_time_us = (0xFFFFFFFF - time_now) + deadline;
-	} else {
-		/* How long from the current time to the deadline? */
-		event_time_us = (deadline - __hw_clock_source_read());
-	}
-
-	/* Convert event_time to ticks rounding up */
-	event_time_ticks = usecs_to_ticks(event_time_us) + 1;
-
-	/* set the event time into the timer compare */
-	TMR_EVENT->cmp = event_time_ticks;
-	/* zero out the timer */
-	TMR_EVENT->cnt = 0;
-	TMR_EVENT->cn |= MXC_F_TMR_CN_TEN;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	TMR_EVENT->cn &= ~(MXC_F_TMR_CN_TEN);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	uint32_t timer_count_ticks;
-
-	/* Read the timer value and return the results in microseconds */
-	timer_count_ticks = TMR_ROLLOVER->cnt;
-	return ticks_to_usecs(timer_count_ticks);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	uint32_t timer_count_ticks;
-	timer_count_ticks = usecs_to_ticks(ts);
-	TMR_ROLLOVER->cnt = timer_count_ticks;
-}
-
-/**
- * Interrupt handler for Timer
- */
-static void __timer_event_isr(void)
-{
-	/* Clear the event timer */
-	TMR_EVENT->intr = MXC_F_TMR_INTR_IRQ_CLR;
-	/* Process the timer, pass in that this was NOT a rollover event */
-	if (TMR_ROLLOVER->intr) {
-		TMR_ROLLOVER->intr = MXC_F_TMR_INTR_IRQ_CLR;
-		process_timers(ROLLOVER_EVENT);
-	} else {
-		process_timers(NOT_ROLLOVER_EVENT);
-	}
-}
-/*
- * Declare the EC Timer lower in priority than the I2C interrupt. This
- * allows the I2C driver to process time sensitive interrupts.
- */
-DECLARE_IRQ(EC_TMR1_IRQn, __timer_event_isr, 2);
-
-static void init_timer(mxc_tmr_regs_t *timer, enum tmr_pres prescaler,
-		       enum tmr_mode mode, uint32_t count)
-{
-	/* Disable the Timer */
-	timer->cn &= ~(MXC_F_TMR_CN_TEN);
-
-	if (timer == MXC_TMR0) {
-		/* Enable Timer 0 Clock */
-		MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_T0D);
-	} else if (timer == MXC_TMR1) {
-		/* Enable Timer 1 Clock */
-		MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_T1D);
-	} else if (timer == MXC_TMR2) {
-		/* Enable Timer 2 Clock */
-		MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_T2D);
-	}
-
-	/* Disable timer and clear settings */
-	timer->cn = 0;
-
-	/* Clear interrupt flag */
-	timer->intr = MXC_F_TMR_INTR_IRQ_CLR;
-
-	/* Set the prescaler */
-	timer->cn = (prescaler << MXC_F_TMR_CN_PRES_POS);
-
-	/* Configure the timer */
-	timer->cn = (timer->cn & ~(MXC_F_TMR_CN_TMODE | MXC_F_TMR_CN_TPOL)) |
-		    ((mode << MXC_F_TMR_CN_TMODE_POS) & MXC_F_TMR_CN_TMODE) |
-		    ((0 << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL);
-
-	timer->cnt = 0x1;
-	timer->cmp = count;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/* Initialize two timers, one for the OS Rollover and one for the OS
-	 * Events */
-	init_timer(TMR_ROLLOVER, TMR_PRESCALER, TMR_MODE_CONTINUOUS,
-		   0xffffffff);
-	init_timer(TMR_EVENT, TMR_PRESCALER, TMR_MODE_COMPARE, 0x0);
-	__hw_clock_source_set(start_t);
-
-	/* Enable the timers */
-	TMR_ROLLOVER->cn |= MXC_F_TMR_CN_TEN;
-	TMR_EVENT->cn |= MXC_F_TMR_CN_TEN;
-
-	/* Enable the IRQ */
-	task_enable_irq(TMR_EVENT_IRQ);
-
-	/* Return the Event timer IRQ number (NOT the Rollover IRQ) */
-	return TMR_EVENT_IRQ;
-}
-
-static int hwtimer_display(int argc, char **argv)
-{
-	CPRINTS(" TMR_EVENT count 0x%08x", TMR_EVENT->cnt);
-	CPRINTS(" TMR_ROLLOVER count 0x%08x", TMR_ROLLOVER->cnt);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(hwtimer, hwtimer_display, "hwtimer",
-			"Display hwtimer counts");
diff --git a/chip/max32660/i2c_chip.c b/chip/max32660/i2c_chip.c
deleted file mode 100644
index f28e85f0ca..0000000000
--- a/chip/max32660/i2c_chip.c
+++ /dev/null
@@ -1,1132 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 I2C port module for Chrome EC. */
-
-#include <stdint.h>
-#include <stddef.h>
-#include "common.h"
-#include "config_chip.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "stdbool.h"
-#include "system.h"
-#include "task.h"
-#include "registers.h"
-#include "i2c_regs.h"
-
-/**
- * Byte to use if the EC HOST requested more data
- * than the I2C Slave is able to send.
- */
-#define EC_PADDING_BYTE 0xec
-
-/* **** Definitions **** */
-#define I2C_ERROR \
-	(MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | \
-	 MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER | \
-	 MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \
-	 MXC_F_I2C_INT_FL0_STOP_ER)
-
-#define T_LOW_MIN (160) /* tLOW minimum in nanoseconds */
-#define T_HIGH_MIN (60) /* tHIGH minimum in nanoseconds */
-#define T_R_MAX_HS (40) /* tR maximum for high speed mode in nanoseconds */
-#define T_F_MAX_HS (40) /* tF maximum for high speed mode in nanoseconds */
-#define T_AF_MIN (10)	/* tAF minimun in nanoseconds */
-
-/**
- * typedef i2c_speed_t - I2C speed modes.
- * @I2C_STD_MODE: 100KHz bus speed
- * @I2C_FAST_MODE: 400KHz Bus Speed
- * @I2C_FASTPLUS_MODE: 1MHz Bus Speed
- * @I2C_HS_MODE: 3.4MHz Bus Speed
- */
-typedef enum {
-	I2C_STD_MODE = 100000,
-	I2C_FAST_MODE = 400000,
-	I2C_FASTPLUS_MODE = 1000000,
-	I2C_HS_MODE = 3400000
-} i2c_speed_t;
-
-/**
- * typedef i2c_autoflush_disable_t - Enable/Disable TXFIFO Autoflush mode.
- */
-typedef enum {
-	I2C_AUTOFLUSH_ENABLE = 0,
-	I2C_AUTOFLUSH_DISABLE = 1
-} i2c_autoflush_disable_t;
-
-/**
- * typedef i2c_master_state_t - Available transaction states for I2C Master.
- */
-typedef enum {
-	I2C_MASTER_IDLE = 1,
-	I2C_MASTER_START = 2,
-	I2C_MASTER_WRITE_COMPLETE = 3,
-	I2C_MASTER_READ_COMPLETE = 4
-} i2c_master_state_t;
-
-/**
- * typedef i2c_slave_state_t - Available transaction states for I2C Slave.
- */
-typedef enum {
-	I2C_SLAVE_WRITE_COMPLETE = 0,
-	I2C_SLAVE_ADDR_MATCH_READ = 1,
-	I2C_SLAVE_ADDR_MATCH_WRITE = 2,
-} i2c_slave_state_t;
-
-/**
- * typedef i2c_req_t - I2C Transaction request.
- */
-typedef struct i2c_req i2c_req_t;
-
-/**
- * typedef i2c_req_state_t - Saves the state of the non-blocking requests.
- * @req: Pointer to I2C transaction request information.
- */
-typedef struct {
-	i2c_req_t *req;
-} i2c_req_state_t;
-
-/**
- * struct i2c_req - I2C Transaction request.
- * @addr: I2C 7-bit Address right aligned, bit 6 to bit 0.
- * 	  Only supports 7-bit addressing. LSb of the given
- * 	  address will be used as the read/write bit, the addr
- * 	  will not be shifted. Used for both master and slave
- * 	  transactions.
- * @addr_match_flag: Indicates which slave address was matched.
- *                   0x1 indicates first slave address matched.
- *                   0x2 indicates second slave address matched.
- *                   0x4 indicates third slave address matched.
- *                   0x8 indicates fourth slave address matched.
- * @tx_data: Data for master write/slave read.
- * @rx_data: Data for master read/slave write.
- * @received_count:  Number of rx bytes sent.
- * @tx_remain: Number of bytes to transmit to the master. This
- *             value is -1 if should clock stretch, 0 if start
- *             sending EC_PADDING_BYTE.  Any other values in this
- *             field will transmit data to the Master.
- * @state: I2C slave state that indicates address match, read and
- *         write status.
- * @restart: Restart or stop bit indicator.
- *           0 to send a stop bit at the end of the transaction
- *           Non-zero to send a restart at end of the transaction
- *           Only used for Master transactions.
- * @response_pending: Indicates that a response to the I2C master
- *           is pending.
- * @expecting_done: Indicates if an I2C done flag is expected. This
- *           is used by the driver to determine the order to process
- *           the flags.
- * @expecting_start: Indicates if an I2C start flag is expected. This
- *           is used by the driver to determine the order to process
- *           the flags.
- */
-struct i2c_req {
-	uint8_t addr;
-	uint8_t addr_match_flag;
-	const uint8_t *tx_data;
-	uint8_t *rx_data;
-	volatile unsigned received_count;
-	volatile int tx_remain;
-	volatile i2c_slave_state_t state;
-	volatile int restart;
-	volatile bool response_pending;
-	volatile bool expecting_done;
-	volatile bool expecting_start;
-};
-
-static i2c_req_state_t states[MXC_I2C_INSTANCES];
-
-/**
- * struct i2c_port_data
- * @out: Output data pointer.
- * @out_size: Output data to transfer, in bytes.
- * @in: Input data pointer.
- * @in_size: Input data to transfer, in bytes.
- * @flags: Flags (I2C_XFER_*).
- * @idx: Index into input/output data.
- * @err: Error code, if any.
- * @timeout_us:	Transaction timeout, or 0 to use default.
- * @task_waiting: Task waiting on port, or TASK_ID_INVALID if none.
- */
-struct i2c_port_data {
-	const uint8_t *out;
-	int out_size;
-	uint8_t *in;
-	int in_size;
-	int flags;
-	int idx;
-	int err;
-	uint32_t timeout_us;
-	volatile int task_waiting;
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-/* **** Function Prototypes **** */
-static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed);
-static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			    int stop, const uint8_t *data, int len,
-			    int restart);
-static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			   int stop, uint8_t *data, int len, int restart);
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-static void init_i2cs(int port);
-static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req);
-static void i2c_slave_handler(mxc_i2c_regs_t *i2c);
-#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
-
-/* Port address for each I2C */
-static mxc_i2c_regs_t *i2c_bus_ports[] = {MXC_I2C0, MXC_I2C1};
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-static void i2c_send_board_response(int len);
-static void i2c_process_board_command(int read, int addr, int len);
-void board_i2c_process(int read, uint8_t addr, int len, char *buffer,
-		       void (*send_response)(int len));
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
-
-/**
- * chip_i2c_xfer() - Low Level function for I2C Master Reads and Writes.
- * @port: Port to access
- * @slave_addr:	Slave device address
- * @out: Data to send
- * @out_size: Number of bytes to send
- * @in: Destination buffer for received data
- * @in_size: Number of bytes to receive
- * @flags: Flags (see I2C_XFER_* above)
- *
- * Chip-level function to transmit one block of raw data, then receive one
- * block of raw data.
- *
- * This is a low-level chip-dependent function and should only be called by
- * i2c_xfer().\
- *
- * Return EC_SUCCESS, or non-zero if error.
- */
-int chip_i2c_xfer(int port, const uint16_t slave_addr_flags, const uint8_t *out,
-		  int out_size, uint8_t *in, int in_size, int flags)
-{
-	int xfer_start;
-	int xfer_stop;
-	int status;
-
-	xfer_start = flags & I2C_XFER_START;
-	xfer_stop = flags & I2C_XFER_STOP;
-
-	if (out_size) {
-		status = i2c_master_write(i2c_bus_ports[port], slave_addr_flags,
-					  xfer_start, xfer_stop, out, out_size,
-					  1);
-		if (status != EC_SUCCESS) {
-			return status;
-		}
-	}
-	if (in_size) {
-		status = i2c_master_read(i2c_bus_ports[port], slave_addr_flags,
-					 xfer_start, xfer_stop, in, in_size, 0);
-		if (status != EC_SUCCESS) {
-			return status;
-		}
-	}
-	return EC_SUCCESS;
-}
-
-/**
- * i2c_get_line_levels() - Read the current digital levels on the I2C pins.
- * @port: Port number to use when reading line levels.
- *
- * Return a byte where bit 0 is the line level of SCL and
- * bit 1 is the line level of SDA.
- */
-int i2c_get_line_levels(int port)
-{
-	/* Retrieve the current levels of SCL and SDA from the control reg. */
-	return (i2c_bus_ports[port]->ctrl >> MXC_F_I2C_CTRL_SCL_POS) & 0x03;
-}
-
-/**
- * i2c_set_timeout()
- * @port: Port number to set timeout for.
- * @timeout: Timeout duration in microseconds.
- */
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-/**
- * i2c_init() - Initialize the I2C ports used on device.
- */
-void i2c_init(void)
-{
-	int i;
-	int port;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Initialize all I2C ports used. */
-	for (i = 0; i < i2c_ports_used; i++) {
-		port = i2c_ports[i].port;
-		i2c_init_peripheral(i2c_bus_ports[port],
-				    i2c_ports[i].kbps * 1000);
-		i2c_set_timeout(i, 0);
-	}
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	/* Initialize the I2C Slave */
-	init_i2cs(I2C_PORT_EC);
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-	/*
-	 * Set the secondary I2C slave address for the board.
-	 */
-	/* Index the secondary slave address. */
-	i2c_bus_ports[I2C_PORT_EC]->slave_addr =
-		(i2c_bus_ports[I2C_PORT_EC]->slave_addr &
-		 ~(MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX |
-		   MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS)) |
-		(1 << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS);
-	/* Set the secondary slave address. */
-	i2c_bus_ports[I2C_PORT_EC]->slave_addr =
-		(1 << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS) |
-		CONFIG_BOARD_I2C_ADDR_FLAGS;
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
-
-}
-
-/**
- *  I2C Peripheral Implementation
- */
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-/* IRQ for each I2C */
-static uint32_t i2c_bus_irqs[] = {EC_I2C0_IRQn, EC_I2C1_IRQn};
-
-/**
- * Buffer for received host command packets (including prefix byte on request,
- * and result/size on response).  After any protocol-specific headers, the
- * buffers must be 32-bit aligned.
- */
-static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
-				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t *const host_buffer = host_buffer_padded + 2;
-static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
-static struct host_packet i2c_packet;
-
-static i2c_req_t req_slave;
-volatile int ec_pending_response = 0;
-
-/**
- * i2c_send_response_packet() - Send the response packet to get processed.
- * @pkt: Packet to send.
- */
-static void i2c_send_response_packet(struct host_packet *pkt)
-{
-	int size = pkt->response_size;
-	uint8_t *out = host_buffer;
-
-	/* Ignore host command in-progress. */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result and size to first two bytes. */
-	*out++ = pkt->driver_result;
-	*out++ = size;
-
-	/* Host_buffer data range. */
-	req_slave.tx_remain = size + 2;
-	req_slave.response_pending = true;
-
-	/* Call the handler to send the response packet. */
-	i2c_slave_handler(i2c_bus_ports[I2C_PORT_EC]);
-}
-
-/**
- * i2c_process_command() - Process the command in the i2c host buffer.
- */
-static void i2c_process_command(void)
-{
-	char *buff = host_buffer;
-
-	i2c_packet.send_response = i2c_send_response_packet;
-	i2c_packet.request = (const void *)(&buff[1]);
-	i2c_packet.request_temp = params_copy;
-	i2c_packet.request_max = sizeof(params_copy);
-	/* Don't know the request size so pass in the entire buffer. */
-	i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE;
-
-	/*
-	 * Stuff response at buff[2] to leave the first two bytes of
-	 * buffer available for the result and size to send over i2c.  Note
-	 * that this 2-byte offset and the 2-byte offset from host_buffer
-	 * add up to make the response buffer 32-bit aligned.
-	 */
-	i2c_packet.response = (void *)(&buff[2]);
-	i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE;
-	i2c_packet.response_size = 0;
-
-	if (*buff >= EC_COMMAND_PROTOCOL_3) {
-		i2c_packet.driver_result = EC_RES_SUCCESS;
-	} else {
-		/* Only host command protocol 3 is supported. */
-		i2c_packet.driver_result = EC_RES_INVALID_HEADER;
-	}
-
-	host_packet_receive(&i2c_packet);
-}
-
-/**
- * i2c_slave_service() - Called by the I2C slave interrupt controller.
- * @req:   Request currently being processed.
- */
-void i2c_slave_service(i2c_req_t *req)
-{
-	/* Check if there was a host command (I2C master write). */
-	if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) {
-		req->state = I2C_SLAVE_WRITE_COMPLETE;
-		/* A response to this write is pending. */
-		/* Assume that there is nothing to send back to the HOST. */
-		req->tx_remain = -1;
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-		if (req->addr_match_flag != 0x1) {
-			i2c_process_board_command(
-				0, CONFIG_BOARD_I2C_ADDR_FLAGS,
-				req->received_count);
-		} else
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-		{
-			i2c_process_command();
-		}
-	}
-}
-
-/**
- * I2C0_IRQHandler() - Async Handler for I2C Slave driver.
- */
-void I2C0_IRQHandler(void)
-{
-	i2c_slave_handler(i2c_bus_ports[0]);
-}
-
-/**
- * I2C1_IRQHandler() - Async Handler for I2C Slave driver.
- */
-void I2C1_IRQHandler(void)
-{
-	i2c_slave_handler(i2c_bus_ports[1]);
-}
-
-DECLARE_IRQ(EC_I2C0_IRQn, I2C0_IRQHandler, 1);
-DECLARE_IRQ(EC_I2C1_IRQn, I2C1_IRQHandler, 1);
-
-/**
- * i2c_slave_service_read() - Services the Master I2C read from the slave.
- * @i2c: I2C peripheral pointer.
- * @req: Pointer to the request info.
- */
-static void i2c_slave_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
-{
-	/*
-	 * Clear the RX Threshold interrupt if set. Make sure and preserve
-	 * a possible done bit, address match, or multiple slave address
-	 * flags.
-	 */
-	i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-		MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
-	i2c->int_fl1 = i2c->int_fl1;
-	/*
-	 * If there is nothing to transmit to the EC HOST, then default
-	 * to clock stretching.
-	 */
-	if (req->tx_remain < 0) {
-		return;
-	}
-	/* If there is data to send to the Master then fill the TX FIFO. */
-	if (req->tx_remain != 0) {
-		/* There is no longer a response pending from the slave to the master. */
-		req->response_pending = false;
-		/* Fill the FIFO with data to transimit to the I2C Master. */
-		while ((req->tx_remain > 0) &&
-			!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-			i2c->fifo = *(req->tx_data)++;
-			req->tx_remain--;
-		}
-	}
-	/*
-	 * If we have sent everything to the Master that we can,
-	 * then send padding byte.
-	 */
-	if (req->tx_remain == 0) {
-		/* Tx response is fulfilled. */
-		/* Fill the FIFO with the EC padding byte. */
-		while (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-			i2c->fifo = EC_PADDING_BYTE;
-		}
-	}
-	/* Set the threshold for TX, the threshold is a four bit field. */
-	i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
-			(2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
-	/* Enable interrupts of interest. */
-	i2c->int_en0 = MXC_F_I2C_INT_EN0_TX_THRESH | MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-}
-
-/**
- * i2c_slave_service_write() - Services the Master I2C write to the slave.
- * @i2c: I2C peripheral pointer.
- * @req: Pointer to the request info.
- */
-static void i2c_slave_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req)
-{
-	/* Clear all flags except address matching and done. */
-	i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-		MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
-	i2c->int_fl1 = i2c->int_fl1;
-	/* Read out any data in the RX FIFO. */
-	while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
-		*(req->rx_data)++ = i2c->fifo;
-		req->received_count++;
-	}
-	/* Set the RX threshold interrupt level. */
-	i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-			~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-			(MXC_I2C_FIFO_DEPTH - 1)
-				<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
-	/* Enable interrupts of interest. */
-	i2c->int_en0 = MXC_F_I2C_INT_EN0_RX_THRESH | MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-}
-
-/**
- * i2c_slave_handler() - I2C interrupt handler.
- * @i2c: Base address of the I2C module.
- *
- * This function should be called by the application from the interrupt
- * handler if I2C interrupts are enabled. Alternately, this function
- * can be periodically called by the application if I2C interrupts are
- * disabled.
- */
-static void i2c_slave_handler(mxc_i2c_regs_t *i2c)
-{
-	i2c_req_t *req;
-
-	/* Get the request context for this interrupt. */
-	req = states[MXC_I2C_GET_IDX(i2c)].req;
-
-
-	/* Check for an address match flag. */
-	if ((req->expecting_start) && (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH)) {
-		req->expecting_done = true;
-		req->expecting_start = false;
-		/*
-		* Save the address match index to identify
-		* targeted slave address.
-		*/
-		req->addr_match_flag =
-			(i2c->int_fl0 & MXC_F_I2C_INT_FL0_MAMI_MASK) >>
-			MXC_F_I2C_INT_FL0_MAMI_POS;
-
-		/* Clear all interrupt flags except a done interrupt. */
-		i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_DONE);
-		i2c->int_fl1 = i2c->int_fl1;
-
-		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-
-		/* Check if Master is writing to the slave. */
-		if (!(i2c->ctrl & MXC_F_I2C_CTRL_READ)) {
-			/* I2C Master is writing to the slave. */
-			req->rx_data = host_buffer;
-			req->tx_data = host_buffer;
-			req->tx_remain = -1; /* Nothing to send yet. */
-			/* Clear the RX (receive from I2C Master) byte counter. */
-			req->received_count = 0;
-			req->state = I2C_SLAVE_ADDR_MATCH_WRITE;
-			/* The Master is writing, there can not be a response pending yet. */
-			req->response_pending = false;
-			/* Set the RX threshold interrupt level. */
-			i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-					~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-					(MXC_I2C_FIFO_DEPTH - 2)
-						<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
-		} else {
-			/* The Master is reading from the slave. */
-			/* Start transmitting to the Master from the start of buffer. */
-			req->tx_data = host_buffer;
-			req->state = I2C_SLAVE_ADDR_MATCH_READ;
-			/* Set the threshold for TX, the threshold is a four bit field. */
-			i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
-				(2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-			/*
-			* If this is a board address match and there is not
-			* already a pending response to the I2C Master then
-			* fulfill this board read request.
-			*/
-			if ((req->response_pending == 0) &&
-				(req->addr_match_flag != 0x1)) {
-				i2c_process_board_command(
-					1, CONFIG_BOARD_I2C_ADDR_FLAGS, 0);
-			}
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-		}
-		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-		/* Inhibit sleep mode when addressed until STOPF flag is set. */
-		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Check for DONE interrupt. */
-	if ((req->expecting_done) && (i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
-		req->expecting_start = true;
-		req->expecting_done = false;
-		/* Clear all interrupts except a possible address match. */
-		i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-			MXC_F_I2C_INT_FL0_MAMI_MASK);
-		i2c->int_fl1 = i2c->int_fl1;
-
-		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-		i2c->int_en1 = 0;
-		/* If this was a DONE after a write then read the fifo until empty. */
-		if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) {
-			/* Read out any data in the RX FIFO. */
-			while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
-				*(req->rx_data)++ = i2c->fifo;
-				req->received_count++;
-			}
-		}
-		/* Manually clear the RX FIFO. */
-		i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
-		/* Manually clear the TX FIFO. */
-		i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
-
-		/* Process the Master write that just finished. */
-		i2c_slave_service(req);
-
-		/* No longer inhibit deep sleep after done. */
-		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Check for an I2C Master Read or Write. */
-	if (i2c->int_fl0 & I2C_ERROR) {
-		/* Clear the error interrupt. */
-		i2c->int_fl0 = I2C_ERROR;
-		i2c->int_en0 = 0;
-		/* Manually clear the TXFIFO. */
-		i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
-		/* Disable and clear interrupts. */
-		i2c->int_en0 = 0;
-		i2c->int_en1 = 0;
-		i2c->int_fl0 = i2c->int_fl0;
-		i2c->int_fl1 = i2c->int_fl1;
-		/* Cycle the I2C peripheral enable on error. */
-		i2c->ctrl = 0;
-		i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;
-	} else if (req->state == I2C_SLAVE_ADDR_MATCH_READ) {
-		/* Service a read request from the I2C Master. */
-		i2c_slave_service_read(i2c, req);
-	} else if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) {
-		/* Service a write request from the I2C Master. */
-		i2c_slave_service_write(i2c, req);
-	}
-
-}
-
-/**
- * init_i2cs() - Async Handler for I2C Slave driver.
- * @port: I2C port number to initialize.
- */
-void init_i2cs(int port)
-{
-	int error;
-
-	error = i2c_init_peripheral(i2c_bus_ports[port], I2C_STD_MODE);
-	if (error != EC_SUCCESS) {
-		while (1)
-			;
-	}
-	/* Prepare for interrupt driven slave requests. */
-	req_slave.addr = CONFIG_HOSTCMD_I2C_ADDR_FLAGS;
-	req_slave.tx_data = host_buffer; /* Transmitted to host. */
-	req_slave.tx_remain = -1;
-	req_slave.rx_data = host_buffer; /* Received from host. */
-	req_slave.restart = 0;
-	req_slave.response_pending = false;
-	states[port].req = &req_slave;
-	error = i2c_slave_async(i2c_bus_ports[port], &req_slave);
-	if (error != EC_SUCCESS) {
-		while (1)
-			;
-	}
-	states[port].req->expecting_done = false;
-	states[port].req->expecting_start = true;
-	task_enable_irq(i2c_bus_irqs[port]);
-}
-
-/**
- * i2c_slave_async() - Slave Read and Write Asynchronous.
- * @i2c:   Pointer to I2C regs.
- * @req:   Request for an I2C transaction.
- *
- * Return EC_SUCCESS if successful, otherwise returns a common error code.
- */
-static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
-{
-	/* Make sure the I2C has been initialized. */
-	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN))
-		return EC_ERROR_UNKNOWN;
-	/* Disable master mode. */
-	i2c->ctrl &= ~(MXC_F_I2C_CTRL_MST);
-	/* Set the Slave Address in the I2C peripheral register. */
-	i2c->slave_addr = req->addr;
-	/* Clear the receive count from the I2C Master. */
-	req->received_count = 0;
-	/* Disable and clear the interrupts. */
-	i2c->int_en0 = 0;
-	i2c->int_en1 = 0;
-	i2c->int_fl0 = i2c->int_fl0;
-	i2c->int_fl1 = i2c->int_fl1;
-
-	/* Set the RX threshold interrupt level. */
-	i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-			~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-			(MXC_I2C_FIFO_DEPTH - 2)
-				<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
-
-	/* Only enable the I2C Address match interrupt. */
-	i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-
-static void i2c_send_board_response(int len)
-{
-	/* Set the number of bytes to send to the I2C master. */
-	req_slave.tx_remain = len;
-	/* Indicate that there is a response pending from the slave. */
-	req_slave.response_pending = true;
-}
-
-
-static void i2c_process_board_command(int read, int addr, int len)
-{
-	board_i2c_process(read, addr, len, &host_buffer[0],
-			  i2c_send_board_response);
-}
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
-
-/**
- * i2c_set_speed() - Set the transfer speed of the selected I2C.
- * @i2c: Pointer to I2C peripheral.
- * @i2cspeed: Speed to set.
- *
- * Return EC_SUCCESS, or non-zero if error.
- */
-static int i2c_set_speed(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
-{
-	uint32_t ticks;
-	uint32_t ticks_lo;
-	uint32_t ticks_hi;
-	uint32_t time_pclk;
-	uint32_t target_bus_freq;
-	uint32_t time_scl_min;
-	uint32_t clock_low_min;
-	uint32_t clock_high_min;
-	uint32_t clock_min;
-
-	if (i2cspeed == I2C_HS_MODE) {
-		/* Compute dividers for high speed mode. */
-		time_pclk = 1000000 / (PeripheralClock / 1000);
-
-		target_bus_freq = i2cspeed;
-		if (target_bus_freq < 1000) {
-			return EC_ERROR_INVAL;
-		}
-
-		time_scl_min = 1000000 / (target_bus_freq / 1000);
-		clock_low_min =
-			((T_LOW_MIN + T_F_MAX_HS + (time_pclk - 1) - T_AF_MIN) /
-			 time_pclk) - 1;
-		clock_high_min = ((T_HIGH_MIN + T_R_MAX_HS + (time_pclk - 1) -
-				  T_AF_MIN) /
-				  time_pclk) - 1;
-		clock_min = ((time_scl_min + (time_pclk - 1)) / time_pclk) - 2;
-
-		ticks_lo = (clock_low_min > (clock_min - clock_high_min))
-				   ? (clock_low_min)
-				   : (clock_min - clock_high_min);
-		ticks_hi = clock_high_min;
-
-		if ((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >>
-				 MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) ||
-		    (ticks_hi > (MXC_F_I2C_HS_CLK_HS_CLK_HI >>
-				 MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))) {
-			return EC_ERROR_INVAL;
-		}
-
-		/* Write results to destination registers. */
-		i2c->hs_clk = (ticks_lo << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS) |
-			      (ticks_hi << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS);
-
-		/* Still need to load dividers for the preamble that each
-		 * high-speed transaction starts with. Switch setting to fast
-		 * mode and fall out of if statement.
-		 */
-		i2cspeed = I2C_FAST_MODE;
-	}
-
-	/* Get the number of periph clocks needed to achieve selected speed. */
-	ticks = PeripheralClock / i2cspeed;
-
-	/* For a 50% duty cycle, half the ticks will be spent high and half will
-	 * be low.
-	 */
-	ticks_hi = (ticks >> 1) - 1;
-	ticks_lo = (ticks >> 1) - 1;
-
-	/* Account for rounding error in odd tick counts. */
-	if (ticks & 1) {
-		ticks_hi++;
-	}
-
-	/* Will results fit into 9 bit registers?  (ticks_hi will always be >=
-	 * ticks_lo.  No need to check ticks_lo.)
-	 */
-	if (ticks_hi > 0x1FF) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* 0 is an invalid value for the destination registers. (ticks_hi will
-	 * always be >= ticks_lo.  No need to check ticks_hi.)
-	 */
-	if (ticks_lo == 0) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Write results to destination registers. */
-	i2c->clk_lo = ticks_lo;
-	i2c->clk_hi = ticks_hi;
-
-	return EC_SUCCESS;
-}
-
-/**
- * i2c_init_peripheral() - Initialize and enable I2C.
- * @i2c:      Pointer to I2C peripheral registers.
- * @i2cspeed: Desired speed (I2C mode).
- * @sys_cfg:  System configuration object.
- *
- * Return EC_SUCCESS, or non-zero if error.
- */
-static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
-{
-	/**
-	 * Always disable the HW autoflush on data NACK and let the SW handle
-	 * the flushing.
-	 */
-	i2c->tx_ctrl0 |= 0x20;
-
-	i2c->ctrl = 0; /* Clear configuration bits. */
-	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C. */
-	i2c->master_ctrl = 0; /* Clear master configuration bits. */
-	i2c->status = 0; /* Clear status bits. */
-
-	i2c->ctrl = 0; /* Clear configuration bits. */
-	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C. */
-	i2c->master_ctrl = 0; /* Clear master configuration bits. */
-	i2c->status = 0; /* Clear status bits. */
-
-	/* Check for HS mode. */
-	if (i2cspeed == I2C_HS_MODE) {
-		i2c->ctrl |= MXC_F_I2C_CTRL_HS_MODE; /* Enable HS mode. */
-	}
-
-	/* Disable and clear interrupts. */
-	i2c->int_en0 = 0;
-	i2c->int_en1 = 0;
-	i2c->int_fl0 = i2c->int_fl0;
-	i2c->int_fl1 = i2c->int_fl1;
-
-	i2c->timeout = 0x0; /* Set timeout. */
-	i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; /* Clear the RX FIFO. */
-	i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; /* Clear the TX FIFO. */
-
-	return i2c_set_speed(i2c, i2cspeed);
-}
-
-/**
- * i2c_master_write()
- * @i2c:  Pointer to I2C regs.
- * @addr: I2C 7-bit Address left aligned, bit 7 to bit 1.
- *        Only supports 7-bit addressing. LSb of the given address
- *        will be used as the read/write bit, the \p addr <b>will
- *        not be shifted. Used for both master and
- *        slave transactions.
- * @data: Data to be written.
- * @len:  Number of bytes to Write.
- * @restart: 0 to send a stop bit at the end of the transaction,
- *	     otherwise send a restart.
- *
- * Will block until transaction is complete.
- *
- * Return  EC_SUCCESS, or non-zero if error.
- */
-static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			    int stop, const uint8_t *data, int len, int restart)
-{
-	if (len == 0) {
-		return EC_SUCCESS;
-	}
-
-	/* Clear the interrupt flag. */
-	i2c->int_fl0 = i2c->int_fl0;
-
-	/* Make sure the I2C has been initialized. */
-	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Enable master mode. */
-	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
-
-	/* Load FIFO with slave address for WRITE and as much data as we can. */
-	while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
-	}
-
-	if (start) {
-		/**
-		 * The slave address is right-aligned, bits 6 to 0, shift
-		 * to the left and make room for the write bit.
-		 */
-		i2c->fifo = (addr << 1) & ~(0x1);
-	}
-
-	while ((len > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-		i2c->fifo = *data++;
-		len--;
-	}
-	/* Generate Start signal. */
-	if (start) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
-	}
-
-	/* Write remaining data to FIFO. */
-	while (len > 0) {
-		/* Check for errors. */
-		if (i2c->int_fl0 & I2C_ERROR) {
-			/* Set the stop bit. */
-			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-			return EC_ERROR_UNKNOWN;
-		}
-
-		if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-			i2c->fifo = *data++;
-			len--;
-		}
-	}
-	/* Check if Repeated Start requested. */
-	if (restart) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
-	} else {
-		if (stop) {
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-		}
-	}
-
-	if (stop) {
-		/* Wait for Done. */
-		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
-			/* Check for errors */
-			if (i2c->int_fl0 & I2C_ERROR) {
-				/* Set the stop bit */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		/* Clear Done interrupt flag. */
-		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
-	}
-
-	/* Wait for Stop if requested and there is no restart. */
-	if (stop && !restart) {
-		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
-			/* Check for errors */
-			if (i2c->int_fl0 & I2C_ERROR) {
-				/* Set the stop bit */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		/* Clear stop interrupt flag. */
-		i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
-	}
-
-	/* Check for errors. */
-	if (i2c->int_fl0 & I2C_ERROR) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * i2c_master_read()
- * @i2c:        Pointer to I2C regs.
- * @addr:       I2C 7-bit Address right aligned, bit 6 to bit 0.
- * @data:       Data to be written.
- * @len:        Number of bytes to Write.
- * @restart:    0 to send a stop bit at the end of the transaction,
- * 	       otherwise send a restart.
- *
- * Will block until transaction is complete.
- *
- * Return:     EC_SUCCESS if successful, otherwise returns a common error code
- */
-static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			   int stop, uint8_t *data, int len, int restart)
-{
-	volatile int length = len;
-	int interactive_receive_mode;
-
-	if (len == 0) {
-		return EC_SUCCESS;
-	}
-
-	if (len > 255) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Clear the interrupt flag. */
-	i2c->int_fl0 = i2c->int_fl0;
-
-	/* Make sure the I2C has been initialized. */
-	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Enable master mode. */
-	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
-
-	if (stop) {
-		/* Set receive count. */
-		i2c->ctrl &= ~MXC_F_I2C_CTRL_RX_MODE;
-		i2c->rx_ctrl1 = len;
-		interactive_receive_mode = 0;
-	} else {
-		i2c->ctrl |= MXC_F_I2C_CTRL_RX_MODE;
-		i2c->rx_ctrl1 = 1;
-		interactive_receive_mode = 1;
-	}
-
-	/* Load FIFO with slave address. */
-	if (start) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
-		while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
-		}
-		/**
-		 * The slave address is right-aligned, bits 6 to 0, shift
-		 * to the left and make room for the read bit.
-		 */
-		i2c->fifo = ((addr << 1) | 1);
-	}
-
-	/* Wait for all data to be received or error. */
-	while (length > 0) {
-		/* Check for errors */
-		if (i2c->int_fl0 & I2C_ERROR) {
-			/* Set the stop bit. */
-			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* If in interactive receive mode then ack each received byte. */
-		if (interactive_receive_mode) {
-			while (!(i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE))
-				;
-			if (i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE) {
-				/* Read the data. */
-				*data++ = i2c->fifo;
-				length--;
-				/* Clear the bit. */
-				if (length != 1) {
-					i2c->int_fl0 =
-						MXC_F_I2C_INT_EN0_RX_MODE;
-				}
-			}
-		} else {
-			if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
-				*data++ = i2c->fifo;
-				length--;
-			}
-		}
-	}
-
-	if (restart) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
-	} else {
-		if (stop) {
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-		}
-	}
-
-	/* Wait for Done. */
-	if (stop) {
-		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
-			/* Check for errors. */
-			if (i2c->int_fl0 & I2C_ERROR) {
-				/* Set the stop bit. */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		/* Clear Done interrupt flag. */
-		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
-	}
-
-	/* Wait for Stop. */
-	if (!restart) {
-		if (stop) {
-			while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
-				/* Check for errors. */
-				if (i2c->int_fl0 & I2C_ERROR) {
-					/* Set the stop bit. */
-					i2c->master_ctrl &= ~(
-						MXC_F_I2C_MASTER_CTRL_RESTART);
-					i2c->master_ctrl |=
-						MXC_F_I2C_MASTER_CTRL_STOP;
-					return EC_ERROR_UNKNOWN;
-				}
-			}
-			/* Clear Stop interrupt flag. */
-			i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
-		}
-	}
-
-	/* Check for errors. */
-	if (i2c->int_fl0 & I2C_ERROR) {
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
diff --git a/chip/max32660/i2c_regs.h b/chip/max32660/i2c_regs.h
deleted file mode 100644
index 8cd2fd8868..0000000000
--- a/chip/max32660/i2c_regs.h
+++ /dev/null
@@ -1,1627 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the I2C Peripheral */
-
-#ifndef _I2C_REGS_H_
-#define _I2C_REGS_H_
-
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/**
- * Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
- */
-
-/**
- * typedef mxc_i2c_regs_t - Structure type to access the I2C Registers.
- */
-typedef struct {
-	__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */
-	__IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */
-	__IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */
-	__IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */
-	__IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */
-	__IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */
-	__IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */
-	__IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */
-	__IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */
-	__IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */
-	__IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */
-	__IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
-	__IO uint32_t
-		master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */
-	__IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */
-	__IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */
-	__IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */
-	__IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
-	__IO uint32_t
-		slave_addr; /**< <tt>\b 0x44:</tt> I2C SLAVE_ADDR Register */
-	__IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */
-} mxc_i2c_regs_t;
-
-/* Register offsets for module I2C */
-/**
- * I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
- */
-#define MXC_R_I2C_CTRL \
-	((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0000</tt> */
-#define MXC_R_I2C_STATUS \
-	((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0004</tt> */
-#define MXC_R_I2C_INT_FL0 \
-	((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0008</tt> */
-#define MXC_R_I2C_INT_EN0 \
-	((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x000C</tt> */
-#define MXC_R_I2C_INT_FL1 \
-	((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0010</tt> */
-#define MXC_R_I2C_INT_EN1 \
-	((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0014</tt> */
-#define MXC_R_I2C_FIFO_LEN \
-	((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0018</tt> */
-#define MXC_R_I2C_RX_CTRL0 \
-	((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x001C</tt> */
-#define MXC_R_I2C_RX_CTRL1 \
-	((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0020</tt> */
-#define MXC_R_I2C_TX_CTRL0 \
-	((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0024</tt> */
-#define MXC_R_I2C_TX_CTRL1 \
-	((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0028</tt> */
-#define MXC_R_I2C_FIFO \
-	((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x002C</tt> */
-#define MXC_R_I2C_MASTER_CTRL \
-	((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0030</tt> */
-#define MXC_R_I2C_CLK_LO \
-	((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0034</tt> */
-#define MXC_R_I2C_CLK_HI \
-	((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0038</tt> */
-#define MXC_R_I2C_HS_CLK \
-	((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x003C</tt> */
-#define MXC_R_I2C_TIMEOUT \
-	((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0040</tt> */
-#define MXC_R_I2C_SLAVE_ADDR \
-	((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0044</tt> */
-#define MXC_R_I2C_DMA \
-	((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0048</tt> */
-
-/**
- * Control Register0.
- */
-#define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */
-#define MXC_F_I2C_CTRL_I2C_EN \
-	((uint32_t)(0x1UL     \
-		    << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */
-#define MXC_V_I2C_CTRL_I2C_EN_DIS \
-	((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */
-#define MXC_S_I2C_CTRL_I2C_EN_DIS  \
-	(MXC_V_I2C_CTRL_I2C_EN_DIS \
-	 << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */
-#define MXC_V_I2C_CTRL_I2C_EN_EN \
-	((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value                            \
-			   */
-#define MXC_S_I2C_CTRL_I2C_EN_EN  \
-	(MXC_V_I2C_CTRL_I2C_EN_EN \
-	 << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */
-
-#define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */
-#define MXC_F_I2C_CTRL_MST \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */
-#define MXC_V_I2C_CTRL_MST_SLAVE_MODE \
-	((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */
-#define MXC_S_I2C_CTRL_MST_SLAVE_MODE  \
-	(MXC_V_I2C_CTRL_MST_SLAVE_MODE \
-	 << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */
-#define MXC_V_I2C_CTRL_MST_MASTER_MODE \
-	((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */
-#define MXC_S_I2C_CTRL_MST_MASTER_MODE  \
-	(MXC_V_I2C_CTRL_MST_MASTER_MODE \
-	 << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */
-
-#define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */
-#define MXC_F_I2C_CTRL_GEN_CALL_ADDR \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR  \
-							 Mask */
-#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \
-	((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */
-#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS  \
-	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \
-	 << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS      \
-						 Setting */
-#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \
-	((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */
-#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN  \
-	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \
-	 << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN       \
-						 Setting */
-
-#define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */
-#define MXC_F_I2C_CTRL_RX_MODE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */
-#define MXC_V_I2C_CTRL_RX_MODE_DIS \
-	((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */
-#define MXC_S_I2C_CTRL_RX_MODE_DIS  \
-	(MXC_V_I2C_CTRL_RX_MODE_DIS \
-	 << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */
-#define MXC_V_I2C_CTRL_RX_MODE_EN \
-	((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */
-#define MXC_S_I2C_CTRL_RX_MODE_EN  \
-	(MXC_V_I2C_CTRL_RX_MODE_EN \
-	 << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */
-
-#define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */
-#define MXC_F_I2C_CTRL_RX_MODE_ACK \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK  \
-							   Mask */
-#define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \
-	((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */
-#define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK  \
-	(MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \
-	 << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting  \
-					     */
-#define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \
-	((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */
-#define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK  \
-	(MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \
-	 << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting \
-					     */
-
-#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */
-#define MXC_F_I2C_CTRL_SCL_OUT \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
-#define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \
-	((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */
-#define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW  \
-	(MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \
-	 << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW        \
-					   Setting */
-#define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \
-	((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */
-#define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL  \
-	(MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \
-	 << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting  \
-					 */
-
-#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */
-#define MXC_F_I2C_CTRL_SDA_OUT \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
-#define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \
-	((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */
-#define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW  \
-	(MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \
-	 << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW        \
-					   Setting */
-#define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \
-	((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */
-#define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA  \
-	(MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \
-	 << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting  \
-					 */
-
-#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */
-#define MXC_F_I2C_CTRL_SCL \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
-
-#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */
-#define MXC_F_I2C_CTRL_SDA \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
-
-#define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */
-#define MXC_F_I2C_CTRL_SW_OUT_EN \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */
-#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \
-	((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */
-#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE  \
-	(MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \
-	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE  \
-					     Setting */
-#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \
-	((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */
-#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE  \
-	(MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \
-	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE   \
-					     Setting */
-
-#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */
-#define MXC_F_I2C_CTRL_READ \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */
-#define MXC_V_I2C_CTRL_READ_WRITE \
-	((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */
-#define MXC_S_I2C_CTRL_READ_WRITE  \
-	(MXC_V_I2C_CTRL_READ_WRITE \
-	 << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */
-#define MXC_V_I2C_CTRL_READ_READ \
-	((uint32_t)0x1UL) /**< CTRL_READ_READ Value                            \
-			   */
-#define MXC_S_I2C_CTRL_READ_READ  \
-	(MXC_V_I2C_CTRL_READ_READ \
-	 << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */
-
-#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS \
-	12 /**< CTRL_SCL_CLK_STRECH_DIS Position */
-#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS \
-	((uint32_t)(                      \
-		0x1UL                     \
-		<< MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**<                       \
-							      CTRL_SCL_CLK_STRECH_DIS \
-							      Mask */
-#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \
-	((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */
-#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN  \
-	(MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \
-	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**<                          \
-						      CTRL_SCL_CLK_STRECH_DIS_EN \
-						      Setting */
-#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \
-	((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */
-#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS  \
-	(MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \
-	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**<                           \
-						      CTRL_SCL_CLK_STRECH_DIS_DIS \
-						      Setting */
-
-#define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */
-#define MXC_F_I2C_CTRL_SCL_PP_MODE \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE  \
-							   Mask */
-#define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \
-	((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */
-#define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS  \
-	(MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \
-	 << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting  \
-					     */
-#define MXC_V_I2C_CTRL_SCL_PP_MODE_EN \
-	((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */
-#define MXC_S_I2C_CTRL_SCL_PP_MODE_EN  \
-	(MXC_V_I2C_CTRL_SCL_PP_MODE_EN \
-	 << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting   \
-					     */
-
-#define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */
-#define MXC_F_I2C_CTRL_HS_MODE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */
-#define MXC_V_I2C_CTRL_HS_MODE_DIS \
-	((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */
-#define MXC_S_I2C_CTRL_HS_MODE_DIS  \
-	(MXC_V_I2C_CTRL_HS_MODE_DIS \
-	 << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */
-#define MXC_V_I2C_CTRL_HS_MODE_EN \
-	((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */
-#define MXC_S_I2C_CTRL_HS_MODE_EN  \
-	(MXC_V_I2C_CTRL_HS_MODE_EN \
-	 << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */
-
-/**
- * I2C_STATUS I2C_STATUS
- */
-#define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */
-#define MXC_F_I2C_STATUS_BUS \
-	((uint32_t)(0x1UL    \
-		    << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask   \
-							 */
-#define MXC_V_I2C_STATUS_BUS_IDLE \
-	((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */
-#define MXC_S_I2C_STATUS_BUS_IDLE  \
-	(MXC_V_I2C_STATUS_BUS_IDLE \
-	 << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */
-#define MXC_V_I2C_STATUS_BUS_BUSY \
-	((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */
-#define MXC_S_I2C_STATUS_BUS_BUSY  \
-	(MXC_V_I2C_STATUS_BUS_BUSY \
-	 << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */
-
-#define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */
-#define MXC_F_I2C_STATUS_RX_EMPTY \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY  \
-							    Mask */
-#define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \
-	((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */
-#define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY  \
-	(MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \
-	 << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY      \
-					      Setting */
-#define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \
-	((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */
-#define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY  \
-	(MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \
-	 << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting  \
-					    */
-
-#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */
-#define MXC_F_I2C_STATUS_RX_FULL \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
-#define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \
-	((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */
-#define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL  \
-	(MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \
-	 << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting \
-					   */
-#define MXC_V_I2C_STATUS_RX_FULL_FULL \
-	((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */
-#define MXC_S_I2C_STATUS_RX_FULL_FULL  \
-	(MXC_V_I2C_STATUS_RX_FULL_FULL \
-	 << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */
-
-#define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */
-#define MXC_F_I2C_STATUS_TX_EMPTY \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY  \
-							    Mask */
-#define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \
-	((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY      \
-					      Setting */
-#define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \
-	((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting  \
-					    */
-
-#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */
-#define MXC_F_I2C_STATUS_TX_FULL \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
-#define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \
-	((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY        \
-					     Setting */
-#define MXC_V_I2C_STATUS_TX_FULL_EMPTY \
-	((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_FULL_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_FULL_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */
-
-#define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */
-#define MXC_F_I2C_STATUS_CLK_MODE \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE  \
-							    Mask */
-#define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
-	((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK  \
-			     Value */
-#define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK  \
-	(MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
-	 << MXC_F_I2C_STATUS_CLK_MODE_POS) /**<                                              \
-					      STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
-					      Setting */
-#define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
-	((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK      \
-			     Value */
-#define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK  \
-	(MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
-	 << MXC_F_I2C_STATUS_CLK_MODE_POS) /**<                                          \
-					      STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
-					      Setting */
-
-#define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */
-#define MXC_F_I2C_STATUS_STATUS \
-	((uint32_t)(            \
-		0xFUL           \
-		<< MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
-#define MXC_V_I2C_STATUS_STATUS_IDLE \
-	((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */
-#define MXC_S_I2C_STATUS_STATUS_IDLE  \
-	(MXC_V_I2C_STATUS_STATUS_IDLE \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */
-#define MXC_V_I2C_STATUS_STATUS_MTX_ADDR \
-	((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_MTX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_MTX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting   \
-					  */
-#define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \
-	((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK       \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \
-	((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR        \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \
-	((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR        \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_SRX_ADDR \
-	((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_SRX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_SRX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting   \
-					  */
-#define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \
-	((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK       \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \
-	((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR        \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \
-	((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK    \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_TX \
-	((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */
-#define MXC_S_I2C_STATUS_STATUS_TX  \
-	(MXC_V_I2C_STATUS_STATUS_TX \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */
-#define MXC_V_I2C_STATUS_STATUS_RX_ACK \
-	((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_RX_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_RX_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */
-#define MXC_V_I2C_STATUS_STATUS_RX \
-	((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */
-#define MXC_S_I2C_STATUS_STATUS_RX  \
-	(MXC_V_I2C_STATUS_STATUS_RX \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */
-#define MXC_V_I2C_STATUS_STATUS_TX_ACK \
-	((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_TX_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_TX_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */
-#define MXC_V_I2C_STATUS_STATUS_NACK \
-	((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */
-#define MXC_S_I2C_STATUS_STATUS_NACK  \
-	(MXC_V_I2C_STATUS_STATUS_NACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */
-#define MXC_V_I2C_STATUS_STATUS_BY_ST \
-	((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */
-#define MXC_S_I2C_STATUS_STATUS_BY_ST  \
-	(MXC_V_I2C_STATUS_STATUS_BY_ST \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */
-
-/**
- * Interrupt Status Register.
- */
-#define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */
-#define MXC_F_I2C_INT_FL0_DONE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */
-#define MXC_V_I2C_INT_FL0_DONE_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_DONE_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_DONE_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */
-#define MXC_V_I2C_INT_FL0_DONE_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */
-#define MXC_S_I2C_INT_FL0_DONE_PENDING  \
-	(MXC_V_I2C_INT_FL0_DONE_PENDING \
-	 << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */
-
-#define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */
-#define MXC_F_I2C_INT_FL0_RX_MODE \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE  \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE       \
-					      Setting */
-#define MXC_V_I2C_INT_FL0_RX_MODE_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */
-#define MXC_S_I2C_INT_FL0_RX_MODE_PENDING  \
-	(MXC_V_I2C_INT_FL0_RX_MODE_PENDING \
-	 << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING        \
-					      Setting */
-
-#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS \
-	2 /**< INT_FL0_GEN_CALL_ADDR Position */
-#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR \
-	((uint32_t)(                    \
-		0x1UL                   \
-		<< MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**<                     \
-							    INT_FL0_GEN_CALL_ADDR \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**<                              \
-						    INT_FL0_GEN_CALL_ADDR_INACTIVE \
-						    Setting */
-#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */
-#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING  \
-	(MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \
-	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**<                             \
-						    INT_FL0_GEN_CALL_ADDR_PENDING \
-						    Setting */
-
-#define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */
-#define MXC_F_I2C_INT_FL0_ADDR_MATCH \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH  \
-							 Mask */
-#define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE \
-						 Setting */
-#define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING  \
-	(MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \
-	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING  \
-						 Setting */
-
-#define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */
-#define MXC_F_I2C_INT_FL0_RX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE   \
-						Setting */
-#define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */
-#define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING  \
-	(MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \
-	 << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING    \
-						Setting */
-
-#define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */
-#define MXC_F_I2C_INT_FL0_TX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE   \
-						Setting */
-#define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */
-#define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING  \
-	(MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \
-	 << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING    \
-						Setting */
-
-#define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */
-#define MXC_F_I2C_INT_FL0_STOP \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */
-#define MXC_V_I2C_INT_FL0_STOP_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_STOP_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_STOP_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */
-#define MXC_V_I2C_INT_FL0_STOP_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */
-#define MXC_S_I2C_INT_FL0_STOP_PENDING  \
-	(MXC_V_I2C_INT_FL0_STOP_PENDING \
-	 << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */
-
-#define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */
-#define MXC_F_I2C_INT_FL0_ADDR_ACK \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK  \
-							   Mask */
-#define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE     \
-					       Setting */
-#define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING  \
-	(MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \
-	 << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING      \
-					       Setting */
-
-#define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */
-#define MXC_F_I2C_INT_FL0_ARB_ER \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */
-#define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting \
-					   */
-#define MXC_V_I2C_INT_FL0_ARB_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ARB_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_ARB_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting  \
-					   */
-
-#define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */
-#define MXC_F_I2C_INT_FL0_TO_ER \
-	((uint32_t)(            \
-		0x1UL           \
-		<< MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */
-#define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting   \
-					  */
-#define MXC_V_I2C_INT_FL0_TO_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_TO_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_TO_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */
-
-#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS \
-	10 /**< INT_FL0_ADDR_NACK_ER Position */
-#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER \
-	((uint32_t)(                   \
-		0x1UL                  \
-		<< MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**<                    \
-							   INT_FL0_ADDR_NACK_ER \
-							   Mask */
-#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**<                             \
-						   INT_FL0_ADDR_NACK_ER_INACTIVE \
-						   Setting */
-#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**<                            \
-						   INT_FL0_ADDR_NACK_ER_PENDING \
-						   Setting */
-
-#define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */
-#define MXC_F_I2C_INT_FL0_DATA_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE       \
-					      Setting */
-#define MXC_V_I2C_INT_FL0_DATA_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_DATA_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_DATA_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING        \
-					      Setting */
-
-#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS \
-	12 /**< INT_FL0_DO_NOT_RESP_ER Position */
-#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**<                      \
-							     INT_FL0_DO_NOT_RESP_ER \
-							     Mask */
-#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**<                               \
-						     INT_FL0_DO_NOT_RESP_ER_INACTIVE \
-						     Setting */
-#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**<                              \
-						     INT_FL0_DO_NOT_RESP_ER_PENDING \
-						     Setting */
-
-#define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */
-#define MXC_F_I2C_INT_FL0_START_ER \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER  \
-							   Mask */
-#define MXC_V_I2C_INT_FL0_START_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_START_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_START_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE     \
-					       Setting */
-#define MXC_V_I2C_INT_FL0_START_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_START_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_START_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING      \
-					       Setting */
-
-#define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */
-#define MXC_F_I2C_INT_FL0_STOP_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE       \
-					      Setting */
-#define MXC_V_I2C_INT_FL0_STOP_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_STOP_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_STOP_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING        \
-					      Setting */
-
-#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS \
-	15 /**< INT_FL0_TX_LOCK_OUT Position */
-#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**<                    \
-							  INT_FL0_TX_LOCK_OUT  \
-							  Mask */
-
-#define MXC_F_I2C_INT_FL0_MAMI_POS 16 /**< INT_FL0_MAMI Position */
-/* INT_FL0_MAMI Mask */
-#define MXC_F_I2C_INT_FL0_MAMI_MASK \
-	((uint32_t)(0xFUL << MXC_F_I2C_INT_FL0_MAMI_POS))
-/* INT_FL0_MAMI Address Match 0 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_0 \
-	((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_MAMI_POS))
-/* INT_FL0_MAMI Address Match 1 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_1 \
-	((uint32_t)(0x2UL << MXC_F_I2C_INT_FL0_MAMI_POS))
-/* INT_FL0_MAMI Address Match 2 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_2 \
-	((uint32_t)(0x4UL << MXC_F_I2C_INT_FL0_MAMI_POS))
-/* INT_FL0_MAMI Address Match 3 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_3 \
-	((uint32_t)(0x8UL << MXC_F_I2C_INT_FL0_MAMI_POS)) 
-
-/**
- * Interrupt Enable Register.
- */
-#define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */
-#define MXC_F_I2C_INT_EN0_DONE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */
-#define MXC_V_I2C_INT_EN0_DONE_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */
-#define MXC_S_I2C_INT_EN0_DONE_DIS  \
-	(MXC_V_I2C_INT_EN0_DONE_DIS \
-	 << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */
-#define MXC_V_I2C_INT_EN0_DONE_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */
-#define MXC_S_I2C_INT_EN0_DONE_EN  \
-	(MXC_V_I2C_INT_EN0_DONE_EN \
-	 << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */
-#define MXC_F_I2C_INT_EN0_RX_MODE \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_RX_MODE_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */
-#define MXC_S_I2C_INT_EN0_RX_MODE_DIS  \
-	(MXC_V_I2C_INT_EN0_RX_MODE_DIS \
-	 << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */
-#define MXC_V_I2C_INT_EN0_RX_MODE_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */
-#define MXC_S_I2C_INT_EN0_RX_MODE_EN  \
-	(MXC_V_I2C_INT_EN0_RX_MODE_EN \
-	 << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS \
-	2 /**< INT_EN0_GEN_CTRL_ADDR Position */
-#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR \
-	((uint32_t)(                    \
-		0x1UL                   \
-		<< MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**<                     \
-							    INT_EN0_GEN_CTRL_ADDR \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */
-#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS  \
-	(MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \
-	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**<                          \
-						    INT_EN0_GEN_CTRL_ADDR_DIS  \
-						    Setting */
-#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */
-#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN  \
-	(MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \
-	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN \
-						    Setting */
-
-#define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */
-#define MXC_F_I2C_INT_EN0_ADDR_MATCH \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH  \
-							 Mask */
-#define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */
-#define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS  \
-	(MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \
-	 << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS      \
-						 Setting */
-#define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */
-#define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN  \
-	(MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \
-	 << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN       \
-						 Setting */
-
-#define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */
-#define MXC_F_I2C_INT_EN0_RX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_EN0_RX_THRESH_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */
-#define MXC_S_I2C_INT_EN0_RX_THRESH_DIS  \
-	(MXC_V_I2C_INT_EN0_RX_THRESH_DIS \
-	 << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS        \
-						Setting */
-#define MXC_V_I2C_INT_EN0_RX_THRESH_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */
-#define MXC_S_I2C_INT_EN0_RX_THRESH_EN  \
-	(MXC_V_I2C_INT_EN0_RX_THRESH_EN \
-	 << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting \
-					      */
-
-#define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */
-#define MXC_F_I2C_INT_EN0_TX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_EN0_TX_THRESH_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */
-#define MXC_S_I2C_INT_EN0_TX_THRESH_DIS  \
-	(MXC_V_I2C_INT_EN0_TX_THRESH_DIS \
-	 << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS        \
-						Setting */
-#define MXC_V_I2C_INT_EN0_TX_THRESH_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */
-#define MXC_S_I2C_INT_EN0_TX_THRESH_EN  \
-	(MXC_V_I2C_INT_EN0_TX_THRESH_EN \
-	 << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting \
-					      */
-
-#define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */
-#define MXC_F_I2C_INT_EN0_STOP \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */
-#define MXC_V_I2C_INT_EN0_STOP_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */
-#define MXC_S_I2C_INT_EN0_STOP_DIS  \
-	(MXC_V_I2C_INT_EN0_STOP_DIS \
-	 << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */
-#define MXC_V_I2C_INT_EN0_STOP_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */
-#define MXC_S_I2C_INT_EN0_STOP_EN  \
-	(MXC_V_I2C_INT_EN0_STOP_EN \
-	 << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */
-#define MXC_F_I2C_INT_EN0_ADDR_ACK \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK  \
-							   Mask */
-#define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS  \
-	(MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \
-	 << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting  \
-					     */
-#define MXC_V_I2C_INT_EN0_ADDR_ACK_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ACK_EN  \
-	(MXC_V_I2C_INT_EN0_ADDR_ACK_EN \
-	 << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting   \
-					     */
-
-#define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */
-#define MXC_F_I2C_INT_EN0_ARB_ER \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */
-#define MXC_V_I2C_INT_EN0_ARB_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_ARB_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_ARB_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_ARB_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_ARB_ER_EN  \
-	(MXC_V_I2C_INT_EN0_ARB_ER_EN \
-	 << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */
-#define MXC_F_I2C_INT_EN0_TO_ER \
-	((uint32_t)(            \
-		0x1UL           \
-		<< MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */
-#define MXC_V_I2C_INT_EN0_TO_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_TO_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_TO_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_TO_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_TO_ER_EN  \
-	(MXC_V_I2C_INT_EN0_TO_ER_EN \
-	 << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */
-#define MXC_F_I2C_INT_EN0_ADDR_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_ADDR_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_ADDR_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_ADDR_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ER_EN  \
-	(MXC_V_I2C_INT_EN0_ADDR_ER_EN \
-	 << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */
-#define MXC_F_I2C_INT_EN0_DATA_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_DATA_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_DATA_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_DATA_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_DATA_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_DATA_ER_EN  \
-	(MXC_V_I2C_INT_EN0_DATA_ER_EN \
-	 << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS \
-	12 /**< INT_EN0_DO_NOT_RESP_ER Position */
-#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**<                      \
-							     INT_EN0_DO_NOT_RESP_ER \
-							     Mask */
-#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**<                          \
-						     INT_EN0_DO_NOT_RESP_ER_DIS \
-						     Setting */
-#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN  \
-	(MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \
-	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**<                         \
-						     INT_EN0_DO_NOT_RESP_ER_EN \
-						     Setting */
-
-#define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */
-#define MXC_F_I2C_INT_EN0_START_ER \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER  \
-							   Mask */
-#define MXC_V_I2C_INT_EN0_START_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_START_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_START_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting  \
-					     */
-#define MXC_V_I2C_INT_EN0_START_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_START_ER_EN  \
-	(MXC_V_I2C_INT_EN0_START_ER_EN \
-	 << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting   \
-					     */
-
-#define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */
-#define MXC_F_I2C_INT_EN0_STOP_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_STOP_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_STOP_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_STOP_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_STOP_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_STOP_ER_EN  \
-	(MXC_V_I2C_INT_EN0_STOP_ER_EN \
-	 << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS \
-	15 /**< INT_EN0_TX_LOCK_OUT Position */
-#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**<                    \
-							  INT_EN0_TX_LOCK_OUT  \
-							  Mask */
-#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */
-#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS  \
-	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \
-	 << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS    \
-						  Setting */
-#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */
-#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN  \
-	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \
-	 << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN     \
-						  Setting */
-
-/**
- * Interrupt Status Register 1.
- */
-#define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS \
-	0 /**< INT_FL1_RX_OVERFLOW Position                                    \
-	   */
-#define MXC_F_I2C_INT_FL1_RX_OVERFLOW \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**<                    \
-							  INT_FL1_RX_OVERFLOW  \
-							  Mask */
-#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */
-#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE  \
-	(MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \
-	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**<                            \
-						  INT_FL1_RX_OVERFLOW_INACTIVE \
-						  Setting */
-#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */
-#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING  \
-	(MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \
-	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**<                            \
-						  INT_FL1_RX_OVERFLOW_PENDING  \
-						  Setting */
-
-#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS \
-	1 /**< INT_FL1_TX_UNDERFLOW Position */
-#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW \
-	((uint32_t)(                   \
-		0x1UL                  \
-		<< MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**<                    \
-							   INT_FL1_TX_UNDERFLOW \
-							   Mask */
-#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */
-#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE  \
-	(MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \
-	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**<                             \
-						   INT_FL1_TX_UNDERFLOW_INACTIVE \
-						   Setting */
-#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */
-#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING  \
-	(MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \
-	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**<                            \
-						   INT_FL1_TX_UNDERFLOW_PENDING \
-						   Setting */
-
-/**
- * Interrupt Staus Register 1.
- */
-#define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS \
-	0 /**< INT_EN1_RX_OVERFLOW Position                                    \
-	   */
-#define MXC_F_I2C_INT_EN1_RX_OVERFLOW \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**<                    \
-							  INT_EN1_RX_OVERFLOW  \
-							  Mask */
-#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \
-	((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */
-#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS  \
-	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \
-	 << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS    \
-						  Setting */
-#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \
-	((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */
-#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN  \
-	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \
-	 << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN     \
-						  Setting */
-
-#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS \
-	1 /**< INT_EN1_TX_UNDERFLOW Position */
-#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW \
-	((uint32_t)(                   \
-		0x1UL                  \
-		<< MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**<                    \
-							   INT_EN1_TX_UNDERFLOW \
-							   Mask */
-#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \
-	((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */
-#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS  \
-	(MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \
-	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS  \
-						   Setting */
-#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \
-	((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */
-#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN  \
-	(MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \
-	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN   \
-						   Setting */
-
-/**
- * FIFO Configuration Register.
- */
-#define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */
-#define MXC_F_I2C_FIFO_LEN_RX_LEN \
-	((uint32_t)(0xFFUL        \
-		    << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN \
-							     Mask */
-
-#define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */
-#define MXC_F_I2C_FIFO_LEN_TX_LEN \
-	((uint32_t)(0xFFUL        \
-		    << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN \
-							     Mask */
-
-/**
- * Receive Control Register 0.
- */
-#define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */
-#define MXC_F_I2C_RX_CTRL0_DNR \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */
-#define MXC_V_I2C_RX_CTRL0_DNR_RESPOND \
-	((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */
-#define MXC_S_I2C_RX_CTRL0_DNR_RESPOND  \
-	(MXC_V_I2C_RX_CTRL0_DNR_RESPOND \
-	 << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */
-#define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
-	((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */
-#define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY  \
-	(MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
-	 << MXC_F_I2C_RX_CTRL0_DNR_POS) /**<                                      \
-					   RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
-					   Setting */
-
-#define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */
-#define MXC_F_I2C_RX_CTRL0_RX_FLUSH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH    \
-							Mask */
-#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \
-	((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */
-#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED  \
-	(MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \
-	 << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**<                              \
-						RX_CTRL0_RX_FLUSH_NOT_FLUSHED  \
-						Setting */
-#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \
-	((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */
-#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH  \
-	(MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \
-	 << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH      \
-						Setting */
-
-#define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */
-#define MXC_F_I2C_RX_CTRL0_RX_THRESH \
-	((uint32_t)(                 \
-		0xFUL                \
-		<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH  \
-							 Mask */
-
-/**
- * Receive Control Register 1.
- */
-#define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */
-#define MXC_F_I2C_RX_CTRL1_RX_CNT \
-	((uint32_t)(0xFFUL        \
-		    << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT \
-							     Mask */
-
-#define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */
-#define MXC_F_I2C_RX_CTRL1_RX_FIFO \
-	((uint32_t)(               \
-		0xFUL              \
-		<< MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO  \
-							   Mask */
-
-/**
- * Transmit Control Register 0.
- */
-#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS \
-	0 /**< TX_CTRL0_TX_PRELOAD Position                                    \
-	   */
-#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**<                    \
-							  TX_CTRL0_TX_PRELOAD  \
-							  Mask */
-
-#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS \
-	1 /**< TX_CTRL0_TX_READY_MODE Position */
-#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**<                      \
-							     TX_CTRL0_TX_READY_MODE \
-							     Mask */
-#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \
-	((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */
-#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN  \
-	(MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \
-	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**<                         \
-						     TX_CTRL0_TX_READY_MODE_EN \
-						     Setting */
-#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \
-	((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */
-#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS  \
-	(MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \
-	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**<                          \
-						     TX_CTRL0_TX_READY_MODE_DIS \
-						     Setting */
-
-#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */
-#define MXC_F_I2C_TX_CTRL0_TX_FLUSH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH    \
-							Mask */
-#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \
-	((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */
-#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED  \
-	(MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \
-	 << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**<                              \
-						TX_CTRL0_TX_FLUSH_NOT_FLUSHED  \
-						Setting */
-#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \
-	((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */
-#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH  \
-	(MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \
-	 << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH      \
-						Setting */
-
-#define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */
-#define MXC_F_I2C_TX_CTRL0_TX_THRESH \
-	((uint32_t)(                 \
-		0xFUL                \
-		<< MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH  \
-							 Mask */
-
-/**
- * Transmit Control Register 1.
- */
-#define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */
-#define MXC_F_I2C_TX_CTRL1_TX_READY \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY    \
-							Mask */
-
-#define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */
-#define MXC_F_I2C_TX_CTRL1_TX_LAST \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST  \
-							   Mask */
-#define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
-	((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */
-#define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW  \
-	(MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
-	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
-					       Setting */
-#define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \
-	((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */
-#define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION  \
-	(MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \
-	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**<                                \
-					       TX_CTRL1_TX_LAST_END_TRANSACTION \
-					       Setting */
-
-#define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */
-#define MXC_F_I2C_TX_CTRL1_TX_FIFO \
-	((uint32_t)(               \
-		0xFUL              \
-		<< MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO  \
-							   Mask */
-
-/**
- * Data Register.
- */
-#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
-#define MXC_F_I2C_FIFO_DATA \
-	((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
-
-/**
- * Master Control Register.
- */
-#define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */
-#define MXC_F_I2C_MASTER_CTRL_START \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START    \
-							Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_RESTART_POS \
-	1 /**< MASTER_CTRL_RESTART Position                                    \
-	   */
-#define MXC_F_I2C_MASTER_CTRL_RESTART \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**<                    \
-							  MASTER_CTRL_RESTART  \
-							  Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */
-#define MXC_F_I2C_MASTER_CTRL_STOP \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP  \
-							   Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS \
-	7 /**< MASTER_CTRL_SL_EX_ADDR Position */
-#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**<                      \
-							     MASTER_CTRL_SL_EX_ADDR \
-							     Mask */
-#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
-	((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */
-#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS  \
-	(MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
-	 << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**<                                     \
-						     MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
-						     Setting */
-#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
-	((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */
-#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS  \
-	(MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
-	 << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**<                                      \
-						     MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
-						     Setting */
-
-#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS \
-	8 /**< MASTER_CTRL_MASTER_CODE Position */
-#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE \
-	((uint32_t)(                      \
-		0x7UL                     \
-		<< MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**<                       \
-							      MASTER_CTRL_MASTER_CODE \
-							      Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS \
-	11 /**< MASTER_CTRL_SCL_SPEED_UP Position */
-#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP \
-	((uint32_t)(                       \
-		0x1UL                      \
-		<< MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**<                        \
-							       MASTER_CTRL_SCL_SPEED_UP \
-							       Mask */
-#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \
-	((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */
-#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN  \
-	(MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \
-	 << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**<                           \
-						       MASTER_CTRL_SCL_SPEED_UP_EN \
-						       Setting */
-#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \
-	((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */
-#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS  \
-	(MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \
-	 << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**<                            \
-						       MASTER_CTRL_SCL_SPEED_UP_DIS \
-						       Setting */
-
-/**
- * Clock Low Register.
- */
-#define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */
-#define MXC_F_I2C_CLK_LO_CLK_LO \
-	((uint32_t)(            \
-		0x1FFUL         \
-		<< MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */
-
-/**
- * Clock high Register.
- */
-#define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */
-#define MXC_F_I2C_CLK_HI_CKH \
-	((uint32_t)(0x1FFUL  \
-		    << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */
-
-/**
- * HS-Mode Clock Control Register
- */
-#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */
-#define MXC_F_I2C_HS_CLK_HS_CLK_LO \
-	((uint32_t)(               \
-		0xFFUL             \
-		<< MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO  \
-							   Mask */
-
-#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */
-#define MXC_F_I2C_HS_CLK_HS_CLK_HI \
-	((uint32_t)(               \
-		0xFFUL             \
-		<< MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI  \
-							   Mask */
-
-/**
- * Timeout Register
- */
-#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */
-#define MXC_F_I2C_TIMEOUT_TO \
-	((uint32_t)(0xFFFFUL \
-		    << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
-
-/**
- * Slave Address Register.
- */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS \
-	0 /**< SLAVE_ADDR_SLAVE_ADDR Position */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR \
-	((uint32_t)(                    \
-		0x3FFUL                 \
-		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**<                     \
-							    SLAVE_ADDR_SLAVE_ADDR \
-							    Mask */
-
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS \
-	10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS \
-	((uint32_t)(                        \
-		0x1UL                       \
-		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**<                         \
-								SLAVE_ADDR_SLAVE_ADDR_DIS \
-								Mask */
-
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS \
-	11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX \
-	((uint32_t)(                        \
-		0xFUL                       \
-		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**<                         \
-								SLAVE_ADDR_SLAVE_ADDR_IDX \
-								Mask */
-
-#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS \
-	15 /**< SLAVE_ADDR_EX_ADDR Position                                    \
-	    */
-#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR  \
-							 Mask */
-#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
-	((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */
-#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS  \
-	(MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
-	 << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**<                                 \
-						 SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
-						 Setting */
-#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
-	((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */
-#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS  \
-	(MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
-	 << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**<                                  \
-						 SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
-						 Setting */
-
-/**
- * DMA Register.
- */
-#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */
-#define MXC_F_I2C_DMA_TX_EN \
-	((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
-#define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */
-#define MXC_S_I2C_DMA_TX_EN_DIS  \
-	(MXC_V_I2C_DMA_TX_EN_DIS \
-	 << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */
-#define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */
-#define MXC_S_I2C_DMA_TX_EN_EN  \
-	(MXC_V_I2C_DMA_TX_EN_EN \
-	 << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */
-
-#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */
-#define MXC_F_I2C_DMA_RX_EN \
-	((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
-#define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */
-#define MXC_S_I2C_DMA_RX_EN_DIS  \
-	(MXC_V_I2C_DMA_RX_EN_DIS \
-	 << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */
-#define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */
-#define MXC_S_I2C_DMA_RX_EN_EN  \
-	(MXC_V_I2C_DMA_RX_EN_EN \
-	 << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */
-
-#endif /* _I2C_REGS_H_ */
diff --git a/chip/max32660/icc_regs.h b/chip/max32660/icc_regs.h
deleted file mode 100644
index 5f40e4203d..0000000000
--- a/chip/max32660/icc_regs.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the ICC */
-
-#ifndef _ICC_REGS_H_
-#define _ICC_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/**
- * Structure type to access the ICC Registers.
- */
-typedef struct {
-	__I uint32_t cache_id; /**< <tt>\b 0x0000:<\tt> ICC CACHE_ID Register */
-	__I uint32_t memcfg;   /**< <tt>\b 0x0004:<\tt> ICC MEMCFG Register */
-	__R uint32_t rsv_0x8_0xff[62];
-	__IO uint32_t
-		cache_ctrl; /**< <tt>\b 0x0100:<\tt> ICC CACHE_CTRL Register */
-	__R uint32_t rsv_0x104_0x6ff[383];
-	__IO uint32_t
-		invalidate; /**< <tt>\b 0x0700:<\tt> ICC INVALIDATE Register */
-} mxc_icc_regs_t;
-
-/**
- * ICC Peripheral Register Offsets from the ICC Base Peripheral
- * Address.
- */
-#define MXC_R_ICC_CACHE_ID                                                     \
-	((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_ICC_MEMCFG                                                       \
-	((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt>       \
-				    0x0x004 */
-#define MXC_R_ICC_CACHE_CTRL                                                   \
-	((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt>       \
-				    0x0x100 */
-#define MXC_R_ICC_INVALIDATE                                                   \
-	((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt>       \
-				    0x0x700 */
-
-/**
- * Cache ID Register.
- */
-#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
-#define MXC_F_ICC_CACHE_ID_RELNUM                                              \
-	((uint32_t)(                                                           \
-		0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \
-							     Mask */
-
-#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
-#define MXC_F_ICC_CACHE_ID_PARTNUM                                             \
-	((uint32_t)(0xFUL                                                      \
-		    << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM  \
-							   Mask */
-
-#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
-#define MXC_F_ICC_CACHE_ID_CCHID                                               \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
-
-/**
- * Memory Configuration Register.
- */
-#define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
-#define MXC_F_ICC_MEMCFG_CCHSZ                                                 \
-	((uint32_t)(0xFFFFUL                                                   \
-		    << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
-
-#define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
-#define MXC_F_ICC_MEMCFG_MEMSZ                                                 \
-	((uint32_t)(0xFFFFUL                                                   \
-		    << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
-
-/**
- * Cache Control and Status Register.
- */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS                                      \
-	0 /**< CACHE_CTRL_CACHE_EN Position                                    \
-	   */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_EN                                          \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**<                    \
-							  CACHE_CTRL_CACHE_EN  \
-							  Mask */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                      \
-	((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS                                      \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                     \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS    \
-						  Setting */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                       \
-	((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN                                       \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                      \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN     \
-						  Setting */
-
-#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS                                     \
-	16 /**< CACHE_CTRL_CACHE_RDY Position */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY                                          \
-	((uint32_t)(                                                            \
-		0x1UL                                                           \
-		<< MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**<                    \
-							   CACHE_CTRL_CACHE_RDY \
-							   Mask */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                \
-	((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                  \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                 \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                             \
-						   CACHE_CTRL_CACHE_RDY_NOTREADY \
-						   Setting */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                   \
-	((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY                                   \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                  \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                           \
-						   CACHE_CTRL_CACHE_RDY_READY  \
-						   Setting */
-
-#endif /* _ICC_REGS_H_ */
diff --git a/chip/max32660/pwrseq_regs.h b/chip/max32660/pwrseq_regs.h
deleted file mode 100644
index f323b4568c..0000000000
--- a/chip/max32660/pwrseq_regs.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.

- * Use of this source code is governed by a BSD-style license that can be

- * found in the LICENSE file.

- */

-

-/* MAX32660 Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral */

-

-#ifndef _PWRSEQ_REGS_H_

-#define _PWRSEQ_REGS_H_

-

-/* **** Includes **** */

-#include <stdint.h>

-

-#ifdef __cplusplus

-extern "C" {

-#endif

-

-#if defined(__ICCARM__)

-#pragma system_include

-#endif

-

-#if defined(__CC_ARM)

-#pragma anon_unions

-#endif

-

-/*

-    If types are not defined elsewhere (CMSIS) define them here

-*/

-#ifndef __IO

-#define __IO volatile

-#endif

-#ifndef __I

-#define __I volatile const

-#endif

-#ifndef __O

-#define __O volatile

-#endif

-#ifndef __R

-#define __R volatile const

-#endif

-

-/* **** Definitions **** */

-

-/**

- * mxc_pwrseq_regs_t

- * Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral

- * Module.

- */

-

-/**

- * pwrseq_registers

- * Structure type to access the PWRSEQ Registers.

- */

-typedef struct {

-	__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */

-	__IO uint32_t

-		lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */

-	__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */

-	__R uint32_t rsv_0xc_0x3f[13];

-	__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */

-} mxc_pwrseq_regs_t;

-

-/**

- * Register offsets for module PWRSEQ

- * PWRSEQ Peripheral Register Offsets from the PWRSEQ Base

- */

-#define MXC_R_PWRSEQ_LP_CTRL                                                   \

-	((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \  \

-				    \ \ \ 0x0000</tt> */

-#define MXC_R_PWRSEQ_LP_WAKEFL                                                 \

-	((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \  \

-				    \ \ \ 0x0004</tt> */

-#define MXC_R_PWRSEQ_LPWK_EN                                                   \

-	((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \  \

-				    \ \ \ 0x0008</tt> */

-#define MXC_R_PWRSEQ_LPMEMSD                                                   \

-	((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \  \

-				    \ \ \ 0x0040</tt> */

-

-/**

- * pwrseq_registers

- * Low Power Control Register.

- */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS                                   \

-	0 /**< LP_CTRL_RAMRET_SEL0 Position */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0                                         \

-	((uint32_t)(                                                             \

-		0x1UL                                                            \

-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \                                                                               \

-							     LP_CTRL_RAMRET_SEL0 \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                   \

-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \

-						     \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                    \

-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN  \

-						     \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS                                   \

-	1 /**< LP_CTRL_RAMRET_SEL1 Position */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1                                         \

-	((uint32_t)(                                                             \

-		0x1UL                                                            \

-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \                                                                               \

-							     LP_CTRL_RAMRET_SEL1 \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                   \

-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \

-						     \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                    \

-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN  \

-						     \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS                                   \

-	2 /**< LP_CTRL_RAMRET_SEL2 Position */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2                                         \

-	((uint32_t)(                                                             \

-		0x1UL                                                            \

-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \                                                                               \

-							     LP_CTRL_RAMRET_SEL2 \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                   \

-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \

-						     \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                    \

-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN  \

-						     \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS                                   \

-	3 /**< LP_CTRL_RAMRET_SEL3 Position */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3                                         \

-	((uint32_t)(                                                             \

-		0x1UL                                                            \

-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \                                                                               \

-							     LP_CTRL_RAMRET_SEL3 \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                   \

-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \

-						     \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                    \

-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN  \

-						     \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */

-#define MXC_F_PWRSEQ_LP_CTRL_OVR                                               \

-	((uint32_t)(0x3UL                                                      \

-		    << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                                          \

-	((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */

-#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V                                          \

-	(MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                                         \

-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                                          \

-	((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */

-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V                                          \

-	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                                         \

-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                                          \

-	((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */

-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V                                          \

-	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                                         \

-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS                              \

-	6 /**< LP_CTRL_VCORE_DET_BYPASS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS                                              \

-	((uint32_t)(                                                                       \

-		0x1UL                                                                      \

-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ \ \ \                                                                                         \

-								  LP_CTRL_VCORE_DET_BYPASS \

-								  \                        \

-								  \ \ \ \                                                                                         \

-								  Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                          \

-	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                      \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                     \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                                                                                         \

-							  LP_CTRL_VCORE_DET_BYPASS_ENABLED \

-							  \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                          \

-	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                      \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                     \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                                                                                         \

-							  LP_CTRL_VCORE_DET_BYPASS_DISABLE \

-							  \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS                                     \

-	8 /**< LP_CTRL_RETREG_EN Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                     \

-	((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                     \

-	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                    \

-	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \

-						   \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                      \

-	((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN                                      \

-	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                     \

-	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \  \

-						   \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS                                    \

-	10 /**< LP_CTRL_FAST_WK_EN Position */

-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN                                        \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \                                                                             \

-							    LP_CTRL_FAST_WK_EN \

-							    \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                    \

-	((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \

-						    \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                     \

-	((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                     \

-	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                    \

-	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \  \

-						    \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */

-#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF                                            \

-	((uint32_t)(                                                           \

-		0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \

-							      \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON                                         \

-	((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */

-#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON                                         \

-	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON                                        \

-	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                                        \

-	((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */

-#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF                                        \

-	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                                       \

-	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \

-					      * \                              \

-					      * \ \                                                                             \

-					      * \ \ \                                                                             \

-					      */

-

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS                                 \

-	12 /**< LP_CTRL_VCORE_POR_DIS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS                                           \

-	((uint32_t)(                                                                 \

-		0x1UL                                                                \

-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \                                                                                   \

-							       LP_CTRL_VCORE_POR_DIS \

-							       \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                 \

-	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                                                                               \

-						       LP_CTRL_VCORE_POR_DIS_DIS \

-						       \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                  \

-	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                                                                              \

-						       LP_CTRL_VCORE_POR_DIS_EN \

-						       \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS                                           \

-	((uint32_t)(0x1UL                                                      \

-		    << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                        \

-	((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN                                        \

-	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                       \

-	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting  \

-					       * \                             \

-					       * \ \                                                                             \

-					       * \ \ \                                                                             \

-					       * \ \ \ \                                                                             \

-					       */

-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                       \

-	((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                       \

-	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                      \

-	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \

-					       * \                             \

-					       * \ \                                                                             \

-					       * \ \ \                                                                             \

-					       * \ \ \ \                                                                             \

-					       */

-

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS                                 \

-	20 /**< LP_CTRL_VCORE_SVM_DIS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS                                           \

-	((uint32_t)(                                                                 \

-		0x1UL                                                                \

-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \                                                                                   \

-							       LP_CTRL_VCORE_SVM_DIS \

-							       \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                  \

-	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                                                                              \

-						       LP_CTRL_VCORE_SVM_DIS_EN \

-						       \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                 \

-	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                                                                               \

-						       LP_CTRL_VCORE_SVM_DIS_DIS \

-						       \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS                                 \

-	25 /**< LP_CTRL_VDDIO_POR_DIS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS                                           \

-	((uint32_t)(                                                                 \

-		0x1UL                                                                \

-		<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \                                                                                   \

-							       LP_CTRL_VDDIO_POR_DIS \

-							       \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                  \

-	((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                                                                              \

-						       LP_CTRL_VDDIO_POR_DIS_EN \

-						       \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                 \

-	((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                                                                               \

-						       LP_CTRL_VDDIO_POR_DIS_DIS \

-						       \ \ \ \ Setting */

-

-/**

- * pwrseq_registers

- * Low Power Mode Wakeup Flags for GPIO0

- */

-#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */

-#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST                                          \

-	((uint32_t)(                                                           \

-		0x3FFFUL                                                       \

-		<< MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST \ \

-							  \ \ \ Mask */

-

-/**

- * pwrseq_registers

- * Low Power I/O Wakeup Enable Register 0. This register enables low

- * power wakeup functionality for GPIO0.

- */

-#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */

-#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN                                            \

-	((uint32_t)(0x3FFFUL                                                   \

-		    << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN \ \

-							    \ \ \ Mask */

-

-/**

- * pwrseq_registers

- * Low Power Memory Shutdown Control.

- */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS                                     \

-	0 /**< LPMEMSD_SRAM0_OFF Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                  \

-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                  \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                 \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL  \

-						   \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                                \

-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                                \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                               \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \                                                                             \

-						   LPMEMSD_SRAM0_OFF_SHUTDOWN  \

-						   \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS                                     \

-	1 /**< LPMEMSD_SRAM1_OFF Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                  \

-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                  \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                 \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL  \

-						   \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                                \

-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                                \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                               \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \                                                                             \

-						   LPMEMSD_SRAM1_OFF_SHUTDOWN  \

-						   \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS                                     \

-	2 /**< LPMEMSD_SRAM2_OFF Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                  \

-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                  \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                 \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL  \

-						   \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                                \

-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                                \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                               \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \                                                                             \

-						   LPMEMSD_SRAM2_OFF_SHUTDOWN  \

-						   \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS                                     \

-	3 /**< LPMEMSD_SRAM3_OFF Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                  \

-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                  \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                 \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL  \

-						   \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                                \

-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                                \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                               \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \                                                                             \

-						   LPMEMSD_SRAM3_OFF_SHUTDOWN  \

-						   \ \ \ \ Setting */

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* _PWRSEQ_REGS_H_ */

diff --git a/chip/max32660/registers.h b/chip/max32660/registers.h
deleted file mode 100644
index e444888fa0..0000000000
--- a/chip/max32660/registers.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Register map, needed for a common include file */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include <stdint.h>
-
-#define EC_PF_IRQn 0 /* 0x10  0x0040  16: Power Fail */
-#define EC_WDT0_IRQn 1 /* 0x11  0x0044  17: Watchdog 0 */
-#define EC_RSV00_IRQn 2 /* 0x12  0x0048  18: RSV00 */
-#define EC_RTC_IRQn 3 /* 0x13  0x004C  19: RTC */
-#define EC_RSV1_IRQn 4 /* 0x14  0x0050  20: RSV1 */
-#define EC_TMR0_IRQn 5 /* 0x15  0x0054  21: Timer 0 */
-#define EC_TMR1_IRQn 6 /* 0x16  0x0058  22: Timer 1 */
-#define EC_TMR2_IRQn 7 /* 0x17  0x005C  23: Timer 2 */
-#define EC_RSV02_IRQn 8 /* 0x18  0x0060  24: RSV02 */
-#define EC_RSV03_IRQn 9 /* 0x19  0x0064  25: RSV03 */
-#define EC_RSV04_IRQn 10 /* 0x1A  0x0068  26: RSV04 */
-#define EC_RSV05_IRQn 11 /* 0x1B  0x006C  27: RSV05 */
-#define EC_RSV06_IRQn 12 /* 0x1C  0x0070  28: RSV06 */
-#define EC_I2C0_IRQn 13 /* 0x1D  0x0074  29: I2C0 */
-#define EC_UART0_IRQn 14 /* 0x1E  0x0078  30: UART 0 */
-#define EC_UART1_IRQn 15 /* 0x1F  0x007C  31: UART 1 */
-#define EC_SPI17Y_IRQn 16 /* 0x20  0x0080  32: SPI17Y */
-#define EC_SPIMSS_IRQn 17 /* 0x21  0x0084  33: SPIMSS */
-#define EC_RSV07_IRQn 18 /* 0x22  0x0088  34: RSV07 */
-#define EC_RSV08_IRQn 19 /* 0x23  0x008C  35: RSV08 */
-#define EC_RSV09_IRQn 20 /* 0x24  0x0090  36: RSV09 */
-#define EC_RSV10_IRQn 21 /* 0x25  0x0094  37: RSV10 */
-#define EC_RSV11_IRQn 22 /* 0x26  0x0098  38: RSV11 */
-#define EC_FLC_IRQn 23 /* 0x27  0x009C  39: FLC */
-#define EC_GPIO0_IRQn 24 /* 0x28  0x00A0  40: GPIO0 */
-#define EC_RSV12_IRQn 25 /* 0x29  0x00A4  41: RSV12 */
-#define EC_RSV13_IRQn 26 /* 0x2A  0x00A8  42: RSV13 */
-#define EC_RSV14_IRQn 27 /* 0x2B  0x00AC  43: RSV14 */
-#define EC_DMA0_IRQn 28 /* 0x2C  0x00B0  44: DMA0 */
-#define EC_DMA1_IRQn 29 /* 0x2D  0x00B4  45: DMA1 */
-#define EC_DMA2_IRQn 30 /* 0x2E  0x00B8  46: DMA2 */
-#define EC_DMA3_IRQn 31 /* 0x2F  0x00BC  47: DMA3 */
-#define EC_RSV15_IRQn 32 /* 0x30  0x00C0  48: RSV15 */
-#define EC_RSV16_IRQn 33 /* 0x31  0x00C4  49: RSV16 */
-#define EC_RSV17_IRQn 34 /* 0x32  0x00C8  50: RSV17 */
-#define EC_RSV18_IRQn 35 /* 0x33  0x00CC  51: RSV18 */
-#define EC_I2C1_IRQn 36 /* 0x34  0x00D0  52: I2C1 */
-#define EC_RSV19_IRQn 37 /* 0x35  0x00D4  53: RSV19 */
-#define EC_RSV20_IRQn 38 /* 0x36  0x00D8  54: RSV20 */
-#define EC_RSV21_IRQn 39 /* 0x37  0x00DC  55: RSV21 */
-#define EC_RSV22_IRQn 40 /* 0x38  0x00E0  56: RSV22 */
-#define EC_RSV23_IRQn 41 /* 0x39  0x00E4  57: RSV23 */
-#define EC_RSV24_IRQn 42 /* 0x3A  0x00E8  58: RSV24 */
-#define EC_RSV25_IRQn 43 /* 0x3B  0x00EC  59: RSV25 */
-#define EC_RSV26_IRQn 44 /* 0x3C  0x00F0  60: RSV26 */
-#define EC_RSV27_IRQn 45 /* 0x3D  0x00F4  61: RSV27 */
-#define EC_RSV28_IRQn 46 /* 0x3E  0x00F8  62: RSV28 */
-#define EC_RSV29_IRQn 47 /* 0x3F  0x00FC  63: RSV29 */
-#define EC_RSV30_IRQn 48 /* 0x40  0x0100  64: RSV30 */
-#define EC_RSV31_IRQn 49 /* 0x41  0x0104  65: RSV31 */
-#define EC_RSV32_IRQn 50 /* 0x42  0x0108  66: RSV32 */
-#define EC_RSV33_IRQn 51 /* 0x43  0x010C  67: RSV33 */
-#define EC_RSV34_IRQn 52 /* 0x44  0x0110  68: RSV34 */
-#define EC_RSV35_IRQn 53 /* 0x45  0x0114  69: RSV35 */
-#define EC_GPIOWAKE_IRQn 54 /* 0x46  0x0118  70: GPIO Wakeup */
-
-#ifndef HIRC96_FREQ
-#define HIRC96_FREQ 96000000
-#endif
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
-#ifndef PeripheralClock
-#define PeripheralClock    \
-	(SystemCoreClock / \
-	 2) /*!< Peripheral Clock Frequency                  \
-			       */
-#endif
-
-#define MXC_FLASH_MEM_BASE 0x00000000UL
-#define MXC_FLASH_PAGE_SIZE 0x00002000UL
-#define MXC_FLASH_MEM_SIZE 0x00040000UL
-#define MXC_INFO_MEM_BASE 0x00040000UL
-#define MXC_INFO_MEM_SIZE 0x00001000UL
-#define MXC_SRAM_MEM_BASE 0x20000000UL
-#define MXC_SRAM_MEM_SIZE 0x00018000UL
-
-/*
-   Base addresses and configuration settings for all MAX32660 peripheral
-   modules.
-*/
-
-/******************************************************************************/
-/*                                                             Global control */
-#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
-#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
-
-/******************************************************************************/
-/*                                            Non-battery backed SI Registers */
-#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
-#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
-
-/******************************************************************************/
-/*                                                                   Watchdog */
-#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
-#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
-
-/******************************************************************************/
-/*                                                            Real Time Clock */
-#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
-#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
-
-/******************************************************************************/
-/*                                                            Power Sequencer */
-#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
-#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
-
-/******************************************************************************/
-/*                                                                       GPIO */
-#define MXC_CFG_GPIO_INSTANCES (1)
-#define MXC_CFG_GPIO_PINS_PORT (14)
-
-#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
-#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
-
-#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : -1)
-
-#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0)
-
-#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0)
-
-#define PORT_0 ((uint32_t)(0UL)) /**< Port 0  Define*/
-#define PORT_1 ((uint32_t)(1UL)) /**< Port 1  Define*/
-#define PORT_2 ((uint32_t)(2UL)) /**< Port 2  Define*/
-#define PORT_3 ((uint32_t)(3UL)) /**< Port 3  Define*/
-#define PORT_4 ((uint32_t)(4UL)) /**< Port 4  Define*/
-
-#define GPIO_0 PORT_0 /**< Port 0  Define*/
-#define GPIO_1 PORT_1 /**< Port 1  Define*/
-#define GPIO_2 PORT_2 /**< Port 2  Define*/
-#define GPIO_3 PORT_3 /**< Port 3  Define*/
-#define GPIO_4 PORT_4 /**< Port 4  Define*/
-
-#define UNIMPLEMENTED_GPIO_BANK GPIO_0
-
-/******************************************************************************/
-/*                                                                        I2C */
-#define MXC_I2C_INSTANCES (2)
-#define MXC_I2C_FIFO_DEPTH (8)
-
-#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
-#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
-#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
-#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
-
-#define MXC_I2C_GET_IRQ(i) \
-	(IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0)
-
-#define MXC_I2C_GET_BASE(i) \
-	((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0)
-
-#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0)
-
-#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1)
-
-#define MXC_CFG_TMR_INSTANCES (3)
-
-#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
-#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
-#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
-#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
-#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
-#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
-
-#define MXC_TMR_GET_IRQ(i)              \
-	(IRQn_Type)((i) == 0 ?          \
-			    TMR0_IRQn : \
-			    (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0)
-
-#define MXC_TMR_GET_BASE(i)         \
-	((i) == 0 ? MXC_BASE_TMR0 : \
-		    (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0)
-
-#define MXC_TMR_GET_TMR(i) \
-	((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0)
-
-#define MXC_TMR_GET_IDX(p) \
-	((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : -1)
-
-/******************************************************************************/
-/*                                                                        FLC */
-#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
-#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
-
-/******************************************************************************/
-/*                                                          Instruction Cache */
-#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
-#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
-
-/******************************************************************************/
-/*                                               UART / Serial Port Interface */
-
-#define MXC_UART_INSTANCES (2)
-#define MXC_UART_FIFO_DEPTH (8)
-
-#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
-#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
-#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
-#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
-
-#define MXC_UART_GET_IRQ(i) \
-	(IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : 0)
-
-#define MXC_UART_GET_BASE(i) \
-	((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : 0)
-
-#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : 0)
-
-#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : -1)
-
-#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask))
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/max32660/system_chip.c b/chip/max32660/system_chip.c
deleted file mode 100644
index 07127dc8c5..0000000000
--- a/chip/max32660/system_chip.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 System module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "host_command.h"
-#include "panic.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "registers.h"
-#include "gcr_regs.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-void chip_pre_init(void)
-{
-}
-
-void system_pre_init(void)
-{
-}
-
-void system_reset(int flags)
-{
-	MXC_GCR->rstr0 = MXC_F_GCR_RSTR0_SYSTEM;
-	while (1)
-		;
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* chip specific standby mode */
-	CPRINTS("TODO: implement %s()", __func__);
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "maxim";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "max32660";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "A1";
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/chip/max32660/tmr_regs.h b/chip/max32660/tmr_regs.h
deleted file mode 100644
index 946cacbc50..0000000000
--- a/chip/max32660/tmr_regs.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the TMR Peripheral */
-
-#ifndef _TMR_REGS_H_
-#define _TMR_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * 32-bit reloadable timer that can be used for timing and event
- * counting.
- */
-
-/**
- * Structure type to access the TMR Registers.
- */
-typedef struct {
-	__IO uint32_t cnt;    /**< <tt>\b 0x00:<\tt> TMR CNT Register */
-	__IO uint32_t cmp;    /**< <tt>\b 0x04:<\tt> TMR CMP Register */
-	__IO uint32_t pwm;    /**< <tt>\b 0x08:<\tt> TMR PWM Register */
-	__IO uint32_t intr;   /**< <tt>\b 0x0C:<\tt> TMR INTR Register */
-	__IO uint32_t cn;     /**< <tt>\b 0x10:<\tt> TMR CN Register */
-	__IO uint32_t nolcmp; /**< <tt>\b 0x14:<\tt> TMR NOLCMP Register */
-} mxc_tmr_regs_t;
-
-/**
- * TMR Peripheral Register Offsets from the TMR Base Peripheral
- * Address.
- */
-#define MXC_R_TMR_CNT                                                          \
-	((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_TMR_CMP                                                          \
-	((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x004 */
-#define MXC_R_TMR_PWM                                                          \
-	((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x008 */
-#define MXC_R_TMR_INTR                                                         \
-	((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x00C */
-#define MXC_R_TMR_CN                                                           \
-	((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x010 */
-#define MXC_R_TMR_NOLCMP                                                       \
-	((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x014 */
-
-/**
- * Clear Interrupt. Writing a value (0 or 1) to a bit in this register
- * clears the associated interrupt.
- */
-#define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */
-#define MXC_F_TMR_INTR_IRQ_CLR                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */
-
-/**
- * Timer Control Register.
- */
-#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
-#define MXC_F_TMR_CN_TMODE                                                     \
-	((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
-#define MXC_V_TMR_CN_TMODE_ONESHOT                                             \
-	((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */
-#define MXC_S_TMR_CN_TMODE_ONESHOT                                             \
-	(MXC_V_TMR_CN_TMODE_ONESHOT                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */
-#define MXC_V_TMR_CN_TMODE_CONTINUOUS                                          \
-	((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
-#define MXC_S_TMR_CN_TMODE_CONTINUOUS                                          \
-	(MXC_V_TMR_CN_TMODE_CONTINUOUS                                         \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
-#define MXC_V_TMR_CN_TMODE_COUNTER                                             \
-	((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
-#define MXC_S_TMR_CN_TMODE_COUNTER                                             \
-	(MXC_V_TMR_CN_TMODE_COUNTER                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
-#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
-#define MXC_S_TMR_CN_TMODE_PWM                                                 \
-	(MXC_V_TMR_CN_TMODE_PWM                                                \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
-#define MXC_V_TMR_CN_TMODE_CAPTURE                                             \
-	((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
-#define MXC_S_TMR_CN_TMODE_CAPTURE                                             \
-	(MXC_V_TMR_CN_TMODE_CAPTURE                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
-#define MXC_V_TMR_CN_TMODE_COMPARE                                             \
-	((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
-#define MXC_S_TMR_CN_TMODE_COMPARE                                             \
-	(MXC_V_TMR_CN_TMODE_COMPARE                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
-#define MXC_V_TMR_CN_TMODE_GATED                                               \
-	((uint32_t)0x6UL) /**< CN_TMODE_GATED Value                            \
-			   */
-#define MXC_S_TMR_CN_TMODE_GATED                                               \
-	(MXC_V_TMR_CN_TMODE_GATED                                              \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
-#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                                      \
-	((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */
-#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE                                      \
-	(MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                                     \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */
-
-#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
-#define MXC_F_TMR_CN_PRES                                                      \
-	((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
-#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL)     /**< CN_PRES_DIV1 Value */
-#define MXC_S_TMR_CN_PRES_DIV1                                                 \
-	(MXC_V_TMR_CN_PRES_DIV1                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV1 Setting */
-#define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */
-#define MXC_S_TMR_CN_PRES_DIV2                                                 \
-	(MXC_V_TMR_CN_PRES_DIV2                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV2 Setting */
-#define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */
-#define MXC_S_TMR_CN_PRES_DIV4                                                 \
-	(MXC_V_TMR_CN_PRES_DIV4                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV4 Setting */
-#define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */
-#define MXC_S_TMR_CN_PRES_DIV8                                                 \
-	(MXC_V_TMR_CN_PRES_DIV8                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV8 Setting */
-#define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */
-#define MXC_S_TMR_CN_PRES_DIV16                                                \
-	(MXC_V_TMR_CN_PRES_DIV16                                               \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV16 Setting */
-#define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */
-#define MXC_S_TMR_CN_PRES_DIV32                                                \
-	(MXC_V_TMR_CN_PRES_DIV32                                               \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV32 Setting */
-#define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */
-#define MXC_S_TMR_CN_PRES_DIV64                                                \
-	(MXC_V_TMR_CN_PRES_DIV64                                               \
-	 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */
-#define MXC_V_TMR_CN_PRES_DIV128                                               \
-	((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value                            \
-			   */
-#define MXC_S_TMR_CN_PRES_DIV128                                               \
-	(MXC_V_TMR_CN_PRES_DIV128                                              \
-	 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */
-
-#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
-#define MXC_F_TMR_CN_TPOL                                                      \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
-#define MXC_V_TMR_CN_TPOL_ACTIVEHI                                             \
-	((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */
-#define MXC_S_TMR_CN_TPOL_ACTIVEHI                                             \
-	(MXC_V_TMR_CN_TPOL_ACTIVEHI                                            \
-	 << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */
-#define MXC_V_TMR_CN_TPOL_ACTIVELO                                             \
-	((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */
-#define MXC_S_TMR_CN_TPOL_ACTIVELO                                             \
-	(MXC_V_TMR_CN_TPOL_ACTIVELO                                            \
-	 << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */
-
-#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
-#define MXC_F_TMR_CN_TEN                                                       \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
-#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL)      /**< CN_TEN_DIS Value */
-#define MXC_S_TMR_CN_TEN_DIS                                                   \
-	(MXC_V_TMR_CN_TEN_DIS                                                  \
-	 << MXC_F_TMR_CN_TEN_POS)	     /**< CN_TEN_DIS Setting */
-#define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */
-#define MXC_S_TMR_CN_TEN_EN                                                    \
-	(MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting   \
-						       */
-
-#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
-#define MXC_F_TMR_CN_PRES3                                                     \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
-
-#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
-#define MXC_F_TMR_CN_PWMSYNC                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask   \
-							 */
-#define MXC_V_TMR_CN_PWMSYNC_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value                            \
-			   */
-#define MXC_S_TMR_CN_PWMSYNC_DIS                                               \
-	(MXC_V_TMR_CN_PWMSYNC_DIS                                              \
-	 << MXC_F_TMR_CN_PWMSYNC_POS)		  /**< CN_PWMSYNC_DIS Setting */
-#define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */
-#define MXC_S_TMR_CN_PWMSYNC_EN                                                \
-	(MXC_V_TMR_CN_PWMSYNC_EN                                               \
-	 << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */
-
-#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
-#define MXC_F_TMR_CN_NOLHPOL                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask   \
-							 */
-#define MXC_V_TMR_CN_NOLHPOL_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value                            \
-			   */
-#define MXC_S_TMR_CN_NOLHPOL_DIS                                               \
-	(MXC_V_TMR_CN_NOLHPOL_DIS                                              \
-	 << MXC_F_TMR_CN_NOLHPOL_POS)		  /**< CN_NOLHPOL_DIS Setting */
-#define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */
-#define MXC_S_TMR_CN_NOLHPOL_EN                                                \
-	(MXC_V_TMR_CN_NOLHPOL_EN                                               \
-	 << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */
-
-#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
-#define MXC_F_TMR_CN_NOLLPOL                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask   \
-							 */
-#define MXC_V_TMR_CN_NOLLPOL_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value                            \
-			   */
-#define MXC_S_TMR_CN_NOLLPOL_DIS                                               \
-	(MXC_V_TMR_CN_NOLLPOL_DIS                                              \
-	 << MXC_F_TMR_CN_NOLLPOL_POS)		  /**< CN_NOLLPOL_DIS Setting */
-#define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */
-#define MXC_S_TMR_CN_NOLLPOL_EN                                                \
-	(MXC_V_TMR_CN_NOLLPOL_EN                                               \
-	 << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */
-
-#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
-#define MXC_F_TMR_CN_PWMCKBD                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask   \
-							 */
-#define MXC_V_TMR_CN_PWMCKBD_DIS                                               \
-	((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value                            \
-			   */
-#define MXC_S_TMR_CN_PWMCKBD_DIS                                               \
-	(MXC_V_TMR_CN_PWMCKBD_DIS                                              \
-	 << MXC_F_TMR_CN_PWMCKBD_POS)		  /**< CN_PWMCKBD_DIS Setting */
-#define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */
-#define MXC_S_TMR_CN_PWMCKBD_EN                                                \
-	(MXC_V_TMR_CN_PWMCKBD_EN                                               \
-	 << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */
-
-/**
- * Timer Non-Overlapping Compare Register.
- */
-#define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */
-#define MXC_F_TMR_NOLCMP_NOLLCMP                                               \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */
-
-#define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */
-#define MXC_F_TMR_NOLCMP_NOLHCMP                                               \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _TMR_REGS_H_ */
diff --git a/chip/max32660/uart_chip.c b/chip/max32660/uart_chip.c
deleted file mode 100644
index c30a6ebd45..0000000000
--- a/chip/max32660/uart_chip.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Console UART Module for Chrome EC */
-
-#include <stdint.h>
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "registers.h"
-#include "tmr_regs.h"
-#include "gpio_regs.h"
-#include "common.h"
-#include "gcr_regs.h"
-#include "uart_regs.h"
-
-static int done_uart_init_yet;
-
-#ifndef UARTN
-#define UARTN CONFIG_UART_HOST
-#endif
-
-#if (UARTN == 0)
-#define MXC_UART MXC_UART0
-#define EC_UART_IRQn EC_UART0_IRQn
-#elif (UARTN == 1)
-#define MXC_UART MXC_UART1
-#define EC_UART_IRQn EC_UART1_IRQn
-#else
-#error "MAX32660 supports only UART 0 or 1 for EC console"
-#endif
-
-#define UART_BAUD 115200
-
-#define UART_ER_IF                                                             \
-	(MXC_F_UART_INT_FL_RX_FRAME_ERROR |                                    \
-	 MXC_F_UART_INT_FL_RX_PARITY_ERROR | MXC_F_UART_INT_FL_RX_OVERRUN)
-
-#define UART_ER_IE                                                             \
-	(MXC_F_UART_INT_EN_RX_FRAME_ERROR |                                    \
-	 MXC_F_UART_INT_EN_RX_PARITY_ERROR | MXC_F_UART_INT_EN_RX_OVERRUN)
-
-#define UART_RX_IF (UART_ER_IF | MXC_F_UART_INT_FL_RX_FIFO_THRESH)
-
-#define UART_RX_IE (UART_ER_IE | MXC_F_UART_INT_EN_RX_FIFO_THRESH)
-
-#define UART_TX_IF                                                             \
-	(UART_ER_IF | MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY |                 \
-	 MXC_F_UART_INT_FL_TX_FIFO_THRESH)
-
-#define UART_TX_IE                                                             \
-	(UART_ER_IE | MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY |                 \
-	 MXC_F_UART_INT_EN_TX_FIFO_THRESH)
-
-#define UART_RX_THRESHOLD_LEVEL 1
-
-/**
- * Alternate clock rate. (7.3728MHz) */
-#define UART_ALTERNATE_CLOCK_HZ 7372800
-
-/* ************************************************************************* */
-static unsigned int uart_number_write_available(mxc_uart_regs_t *uart)
-{
-	return MXC_UART_FIFO_DEPTH -
-	       ((uart->status & MXC_F_UART_STATUS_TX_FIFO_CNT) >>
-		MXC_F_UART_STATUS_TX_FIFO_CNT_POS);
-}
-
-/* ************************************************************************* */
-static unsigned int uart_number_read_available(mxc_uart_regs_t *uart)
-{
-	return ((uart->status & MXC_F_UART_STATUS_RX_FIFO_CNT) >>
-		MXC_F_UART_STATUS_RX_FIFO_CNT_POS);
-}
-
-static void uartn_enable_tx_interrupt(int uart_num)
-{
-	// Enable the interrupts
-	MXC_UART_GET_UART(uart_num)->int_en |= UART_TX_IE;
-}
-
-static void uartn_disable_tx_interrupt(int uart_num)
-{
-	// Disable the interrupts
-	MXC_UART_GET_UART(uart_num)->int_en &= ~UART_TX_IE;
-}
-
-static int uartn_tx_in_progress(int uart_num)
-{
-	return ((MXC_UART_GET_UART(uart_num)->status &
-		 (MXC_F_UART_STATUS_TX_BUSY)) != 0);
-}
-
-static void uartn_tx_flush(int uart_num)
-{
-	while (uartn_tx_in_progress(uart_num)) {
-	}
-}
-
-static int uartn_tx_ready(int uart_num)
-{
-	int avail;
-	avail = uart_number_write_available(MXC_UART_GET_UART(uart_num));
-	/* True if the TX buffer is not completely full */
-	return (avail != 0);
-}
-
-static int uartn_rx_available(int uart_num)
-{
-	int avail;
-	/* True if the RX buffer is not completely empty. */
-	avail = uart_number_read_available(MXC_UART_GET_UART(uart_num));
-	return (avail != 0);
-}
-
-static void uartn_write_char(int uart_num, char c)
-{
-	int avail;
-	mxc_uart_regs_t *uart;
-
-	uart = MXC_UART_GET_UART(uart_num);
-	/* Refill the TX FIFO */
-	avail = uart_number_write_available(uart);
-
-	/* wait until there is room in the fifo */
-	while (avail == 0) {
-		avail = uart_number_write_available(uart);
-	}
-
-	/* stuff the fifo with the character */
-	uart->fifo = c;
-}
-
-static int uartn_read_char(int uart_num)
-{
-	int c;
-	c = MXC_UART_GET_UART(uart_num)->fifo;
-	return c;
-}
-
-static void uartn_clear_interrupt_flags(int uart_num)
-{
-	uint32_t flags;
-	// Read and clear interrupts
-	//    intst = MXC_UART_GET_UART(uart_num)->int_fl;
-	//    MXC_UART_GET_UART(uart_num)->int_fl = ~intst;
-
-	flags = MXC_UART_GET_UART(uart_num)->int_fl;
-	MXC_UART_GET_UART(uart_num)->int_fl = flags;
-}
-
-static inline int uartn_is_rx_interrupt(int uart_num)
-{
-	return MXC_UART_GET_UART(uart_num)->int_fl & UART_RX_IF;
-}
-
-static inline int uartn_is_tx_interrupt(int uart_num)
-{
-	return MXC_UART_GET_UART(uart_num)->int_fl & UART_TX_IF;
-}
-
-int uart_init_done(void)
-{
-	return done_uart_init_yet;
-}
-
-void uart_tx_start(void)
-{
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.
-	 */
-	uartn_enable_tx_interrupt(UARTN);
-	task_trigger_irq(EC_UART_IRQn);
-}
-
-void uart_tx_stop(void)
-{
-	uartn_disable_tx_interrupt(UARTN);
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-int uart_tx_in_progress(void)
-{
-	return uartn_tx_in_progress(UARTN);
-}
-
-void uart_tx_flush(void)
-{
-	uartn_tx_flush(UARTN);
-}
-
-int uart_tx_ready(void)
-{
-	/* True if the TX buffer is not completely full */
-	return uartn_tx_ready(UARTN);
-}
-
-int uart_rx_available(void)
-{
-	/* True if the RX buffer is not completely empty. */
-	return uartn_rx_available(UARTN);
-}
-
-void uart_write_char(char c)
-{
-	/* write a character to the UART */
-	uartn_write_char(UARTN, c);
-}
-
-int uart_read_char(void)
-{
-	return uartn_read_char(UARTN);
-}
-
-/**
- * Interrupt handlers for UART
- */
-void uart_rxtx_interrupt(void)
-{
-	/* Process the Console Input */
-	uart_process_input();
-	/* Process the Buffered Console Output */
-	uart_process_output();
-	uartn_clear_interrupt_flags(UARTN);
-}
-DECLARE_IRQ(EC_UART_IRQn, uart_rxtx_interrupt, 1);
-
-void uart_init(void)
-{
-	uint32_t flags;
-	uint32_t baud0 = 0, baud1 = 0, div;
-	int32_t factor = -1;
-
-	/* Init the GPIO Port Mapping */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Drain FIFOs and enable UART and set configuration */
-	MXC_UART->ctrl = (MXC_F_UART_CTRL_ENABLE | MXC_S_UART_CTRL_CHAR_SIZE_8 | 1);
-
-	/* Set the baud rate */
-	div = PeripheralClock / (UART_BAUD); 	// constant part of DIV (i.e. DIV
-					     					// * (Baudrate*factor_int))
-
-	do {
-		factor += 1;
-		baud0 = div >> (7 - factor); 	// divide by 128,64,32,16 to
-					     				// extract integer part
-		baud1 = ((div << factor) -
-			 (baud0 << 7)); 			// subtract factor corrected div -
-										// integer parts
-
-	} while ((baud0 == 0) && (factor < 4));
-
-	MXC_UART->baud0 = ((factor << MXC_F_UART_BAUD0_FACTOR_POS) | baud0);
-	MXC_UART->baud1 = baud1;
-
-	MXC_UART->thresh_ctrl = UART_RX_THRESHOLD_LEVEL
-			    << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
-
-	/* Clear Interrupt Flags */
-	flags = MXC_UART->int_fl;
-	MXC_UART->int_fl = flags;
-
-	/* Enable the RX interrupts */
-	MXC_UART->int_en |= UART_RX_IE;
-
-	/* Enable the IRQ */
-	task_enable_irq(EC_UART_IRQn);
-	/* Set a flag for the system that the UART has been initialized */
-	done_uart_init_yet = 1;
-}
diff --git a/chip/max32660/uart_regs.h b/chip/max32660/uart_regs.h
deleted file mode 100644
index a2de0cc0a0..0000000000
--- a/chip/max32660/uart_regs.h
+++ /dev/null
@@ -1,677 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the UART Peripheral */
-
-#ifndef _UART_REGS_H_
-#define _UART_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/**
- * Structure type to access the UART Registers.
- */
-typedef struct {
-	__IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> UART CTRL Register */
-	__IO uint32_t
-		thresh_ctrl; /**< <tt>\b 0x04:<\tt> UART THRESH_CTRL Register */
-	__I uint32_t status; /**< <tt>\b 0x08:<\tt> UART STATUS Register */
-	__IO uint32_t int_en;  /**< <tt>\b 0x0C:<\tt> UART INT_EN Register */
-	__IO uint32_t int_fl;  /**< <tt>\b 0x10:<\tt> UART INT_FL Register */
-	__IO uint32_t baud0;   /**< <tt>\b 0x14:<\tt> UART BAUD0 Register */
-	__IO uint32_t baud1;   /**< <tt>\b 0x18:<\tt> UART BAUD1 Register */
-	__IO uint32_t fifo;    /**< <tt>\b 0x1C:<\tt> UART FIFO Register */
-	__IO uint32_t dma;     /**< <tt>\b 0x20:<\tt> UART DMA Register */
-	__IO uint32_t tx_fifo; /**< <tt>\b 0x24:<\tt> UART TX_FIFO Register */
-} mxc_uart_regs_t;
-
-/**
- * UART Peripheral Register Offsets from the UART Base Peripheral
- * Address.
- */
-#define MXC_R_UART_CTRL                                                        \
-	((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x000 */
-#define MXC_R_UART_THRESH_CTRL                                                 \
-	((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x004 */
-#define MXC_R_UART_STATUS                                                      \
-	((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x008 */
-#define MXC_R_UART_INT_EN                                                      \
-	((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x00C */
-#define MXC_R_UART_INT_FL                                                      \
-	((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x010 */
-#define MXC_R_UART_BAUD0                                                       \
-	((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x014 */
-#define MXC_R_UART_BAUD1                                                       \
-	((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x018 */
-#define MXC_R_UART_FIFO                                                        \
-	((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x01C */
-#define MXC_R_UART_DMA                                                         \
-	((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x020 */
-#define MXC_R_UART_TX_FIFO                                                     \
-	((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x024 */
-
-/**
- * Control Register.
- */
-#define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
-#define MXC_F_UART_CTRL_ENABLE                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
-#define MXC_V_UART_CTRL_ENABLE_DIS                                             \
-	((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */
-#define MXC_S_UART_CTRL_ENABLE_DIS                                             \
-	(MXC_V_UART_CTRL_ENABLE_DIS                                            \
-	 << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */
-#define MXC_V_UART_CTRL_ENABLE_EN                                              \
-	((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value                            \
-			   */
-#define MXC_S_UART_CTRL_ENABLE_EN                                              \
-	(MXC_V_UART_CTRL_ENABLE_EN                                             \
-	 << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */
-
-#define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */
-#define MXC_F_UART_CTRL_PARITY_EN                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */
-#define MXC_V_UART_CTRL_PARITY_EN_DIS                                          \
-	((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */
-#define MXC_S_UART_CTRL_PARITY_EN_DIS                                          \
-	(MXC_V_UART_CTRL_PARITY_EN_DIS                                         \
-	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */
-#define MXC_V_UART_CTRL_PARITY_EN_EN                                           \
-	((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */
-#define MXC_S_UART_CTRL_PARITY_EN_EN                                           \
-	(MXC_V_UART_CTRL_PARITY_EN_EN                                          \
-	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */
-
-#define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */
-#define MXC_F_UART_CTRL_PARITY                                                 \
-	((uint32_t)(                                                           \
-		0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */
-#define MXC_V_UART_CTRL_PARITY_EVEN                                            \
-	((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */
-#define MXC_S_UART_CTRL_PARITY_EVEN                                            \
-	(MXC_V_UART_CTRL_PARITY_EVEN                                           \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */
-#define MXC_V_UART_CTRL_PARITY_ODD                                             \
-	((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */
-#define MXC_S_UART_CTRL_PARITY_ODD                                             \
-	(MXC_V_UART_CTRL_PARITY_ODD                                            \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */
-#define MXC_V_UART_CTRL_PARITY_MARK                                            \
-	((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */
-#define MXC_S_UART_CTRL_PARITY_MARK                                            \
-	(MXC_V_UART_CTRL_PARITY_MARK                                           \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */
-#define MXC_V_UART_CTRL_PARITY_SPACE                                           \
-	((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */
-#define MXC_S_UART_CTRL_PARITY_SPACE                                           \
-	(MXC_V_UART_CTRL_PARITY_SPACE                                          \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */
-
-#define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */
-#define MXC_F_UART_CTRL_PARMD                                                  \
-	((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask  \
-							  */
-#define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */
-#define MXC_S_UART_CTRL_PARMD_1                                                \
-	(MXC_V_UART_CTRL_PARMD_1                                               \
-	 << MXC_F_UART_CTRL_PARMD_POS)		  /**< CTRL_PARMD_1 Setting */
-#define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */
-#define MXC_S_UART_CTRL_PARMD_0                                                \
-	(MXC_V_UART_CTRL_PARMD_0                                               \
-	 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */
-
-#define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */
-#define MXC_F_UART_CTRL_TX_FLUSH                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
-
-#define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */
-#define MXC_F_UART_CTRL_RX_FLUSH                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
-
-#define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */
-#define MXC_F_UART_CTRL_BITACC                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */
-#define MXC_V_UART_CTRL_BITACC_FRAME                                           \
-	((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */
-#define MXC_S_UART_CTRL_BITACC_FRAME                                           \
-	(MXC_V_UART_CTRL_BITACC_FRAME                                          \
-	 << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */
-#define MXC_V_UART_CTRL_BITACC_BIT                                             \
-	((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */
-#define MXC_S_UART_CTRL_BITACC_BIT                                             \
-	(MXC_V_UART_CTRL_BITACC_BIT                                            \
-	 << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */
-
-#define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */
-#define MXC_F_UART_CTRL_CHAR_SIZE                                              \
-	((uint32_t)(                                                           \
-		0x3UL                                                          \
-		<< MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
-#define MXC_V_UART_CTRL_CHAR_SIZE_5                                            \
-	((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_5                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_5                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_6                                            \
-	((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_6                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_6                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_7                                            \
-	((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_7                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_7                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_8                                            \
-	((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_8                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_8                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */
-
-#define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */
-#define MXC_F_UART_CTRL_STOPBITS                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
-#define MXC_V_UART_CTRL_STOPBITS_1                                             \
-	((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */
-#define MXC_S_UART_CTRL_STOPBITS_1                                             \
-	(MXC_V_UART_CTRL_STOPBITS_1                                            \
-	 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */
-#define MXC_V_UART_CTRL_STOPBITS_1_5                                           \
-	((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */
-#define MXC_S_UART_CTRL_STOPBITS_1_5                                           \
-	(MXC_V_UART_CTRL_STOPBITS_1_5                                          \
-	 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */
-
-#define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */
-#define MXC_F_UART_CTRL_FLOW_CTRL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */
-#define MXC_V_UART_CTRL_FLOW_CTRL_EN                                           \
-	((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */
-#define MXC_S_UART_CTRL_FLOW_CTRL_EN                                           \
-	(MXC_V_UART_CTRL_FLOW_CTRL_EN                                          \
-	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */
-#define MXC_V_UART_CTRL_FLOW_CTRL_DIS                                          \
-	((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */
-#define MXC_S_UART_CTRL_FLOW_CTRL_DIS                                          \
-	(MXC_V_UART_CTRL_FLOW_CTRL_DIS                                         \
-	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */
-
-#define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */
-#define MXC_F_UART_CTRL_FLOW_POL                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */
-#define MXC_V_UART_CTRL_FLOW_POL_0                                             \
-	((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */
-#define MXC_S_UART_CTRL_FLOW_POL_0                                             \
-	(MXC_V_UART_CTRL_FLOW_POL_0                                            \
-	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */
-#define MXC_V_UART_CTRL_FLOW_POL_1                                             \
-	((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */
-#define MXC_S_UART_CTRL_FLOW_POL_1                                             \
-	(MXC_V_UART_CTRL_FLOW_POL_1                                            \
-	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */
-
-#define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */
-#define MXC_F_UART_CTRL_NULL_MODEM                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \
-							     Mask */
-#define MXC_V_UART_CTRL_NULL_MODEM_DIS                                         \
-	((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */
-#define MXC_S_UART_CTRL_NULL_MODEM_DIS                                         \
-	(MXC_V_UART_CTRL_NULL_MODEM_DIS                                        \
-	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting   \
-					     */
-#define MXC_V_UART_CTRL_NULL_MODEM_EN                                          \
-	((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */
-#define MXC_S_UART_CTRL_NULL_MODEM_EN                                          \
-	(MXC_V_UART_CTRL_NULL_MODEM_EN                                         \
-	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */
-
-#define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */
-#define MXC_F_UART_CTRL_BREAK                                                  \
-	((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask  \
-							  */
-#define MXC_V_UART_CTRL_BREAK_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value                            \
-			   */
-#define MXC_S_UART_CTRL_BREAK_DIS                                              \
-	(MXC_V_UART_CTRL_BREAK_DIS                                             \
-	 << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */
-#define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */
-#define MXC_S_UART_CTRL_BREAK_EN                                               \
-	(MXC_V_UART_CTRL_BREAK_EN                                              \
-	 << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */
-
-#define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */
-#define MXC_F_UART_CTRL_CLKSEL                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */
-#define MXC_V_UART_CTRL_CLKSEL_SYSTEM                                          \
-	((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */
-#define MXC_S_UART_CTRL_CLKSEL_SYSTEM                                          \
-	(MXC_V_UART_CTRL_CLKSEL_SYSTEM                                         \
-	 << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */
-#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE                                       \
-	((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */
-#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE                                       \
-	(MXC_V_UART_CTRL_CLKSEL_ALTERNATE                                      \
-	 << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */
-
-#define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */
-#define MXC_F_UART_CTRL_RX_TO                                                  \
-	((uint32_t)(                                                           \
-		0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */
-
-/**
- * Threshold Control register.
- */
-#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS                              \
-	0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH                                                \
-	((uint32_t)(                                                                         \
-		0x3FUL                                                                       \
-		<< MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**<                          \
-								  THRESH_CTRL_RX_FIFO_THRESH \
-								  Mask */
-
-#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS                              \
-	8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH                                                \
-	((uint32_t)(                                                                         \
-		0x3FUL                                                                       \
-		<< MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**<                          \
-								  THRESH_CTRL_TX_FIFO_THRESH \
-								  Mask */
-
-#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS                             \
-	16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH                                                 \
-	((uint32_t)(                                                                           \
-		0x3FUL                                                                         \
-		<< MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**<                           \
-								   THRESH_CTRL_RTS_FIFO_THRESH \
-								   Mask */
-
-/**
- * Status Register.
- */
-#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
-#define MXC_F_UART_STATUS_TX_BUSY                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
-
-#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
-#define MXC_F_UART_STATUS_RX_BUSY                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
-
-#define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */
-#define MXC_F_UART_STATUS_PARITY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */
-
-#define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */
-#define MXC_F_UART_STATUS_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */
-
-#define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */
-#define MXC_F_UART_STATUS_RX_EMPTY                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \
-							     Mask */
-
-#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
-#define MXC_F_UART_STATUS_RX_FULL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
-
-#define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */
-#define MXC_F_UART_STATUS_TX_EMPTY                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \
-							     Mask */
-
-#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
-#define MXC_F_UART_STATUS_TX_FULL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
-
-#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS                                      \
-	8 /**< STATUS_RX_FIFO_CNT Position                                     \
-	   */
-#define MXC_F_UART_STATUS_RX_FIFO_CNT                                          \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT \
-							  Mask */
-
-#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS                                      \
-	16 /**< STATUS_TX_FIFO_CNT Position                                    \
-	    */
-#define MXC_F_UART_STATUS_TX_FIFO_CNT                                          \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT \
-							  Mask */
-
-#define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */
-#define MXC_F_UART_STATUS_RX_TO                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */
-
-/**
- * Interrupt Enable Register.
- */
-#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS                                   \
-	0 /**< INT_EN_RX_FRAME_ERROR Position */
-#define MXC_F_UART_INT_EN_RX_FRAME_ERROR                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**<                     \
-							     INT_EN_RX_FRAME_ERROR \
-							     Mask */
-
-#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS                                  \
-	1 /**< INT_EN_RX_PARITY_ERROR Position */
-#define MXC_F_UART_INT_EN_RX_PARITY_ERROR                                            \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**<                      \
-							      INT_EN_RX_PARITY_ERROR \
-							      Mask */
-
-#define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */
-#define MXC_F_UART_INT_EN_CTS_CHANGE                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE   \
-							 Mask */
-
-#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
-#define MXC_F_UART_INT_EN_RX_OVERRUN                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN   \
-							 Mask */
-
-#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS                                   \
-	4 /**< INT_EN_RX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_EN_RX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**<                     \
-							     INT_EN_RX_FIFO_THRESH \
-							     Mask */
-
-#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS                             \
-	5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */
-#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY                                                 \
-	((uint32_t)(                                                                           \
-		0x1UL                                                                          \
-		<< MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
-								   INT_EN_TX_FIFO_ALMOST_EMPTY \
-								   Mask */
-
-#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS                                   \
-	6 /**< INT_EN_TX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_EN_TX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**<                     \
-							     INT_EN_TX_FIFO_THRESH \
-							     Mask */
-
-#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
-#define MXC_F_UART_INT_EN_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
-
-#define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */
-#define MXC_F_UART_INT_EN_RX_TIMEOUT                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT   \
-							 Mask */
-
-#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
-#define MXC_F_UART_INT_EN_LAST_BREAK                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK   \
-							 Mask */
-
-/**
- * Interrupt Status Flags.
- */
-#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS                                   \
-	0 /**< INT_FL_RX_FRAME_ERROR Position */
-#define MXC_F_UART_INT_FL_RX_FRAME_ERROR                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**<                     \
-							     INT_FL_RX_FRAME_ERROR \
-							     Mask */
-
-#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS                                  \
-	1 /**< INT_FL_RX_PARITY_ERROR Position */
-#define MXC_F_UART_INT_FL_RX_PARITY_ERROR                                            \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**<                      \
-							      INT_FL_RX_PARITY_ERROR \
-							      Mask */
-
-#define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */
-#define MXC_F_UART_INT_FL_CTS_CHANGE                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE   \
-							 Mask */
-
-#define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */
-#define MXC_F_UART_INT_FL_RX_OVERRUN                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN   \
-							 Mask */
-
-#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS                                   \
-	4 /**< INT_FL_RX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_FL_RX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**<                     \
-							     INT_FL_RX_FIFO_THRESH \
-							     Mask */
-
-#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS                             \
-	5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */
-#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY                                                 \
-	((uint32_t)(                                                                           \
-		0x1UL                                                                          \
-		<< MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
-								   INT_FL_TX_FIFO_ALMOST_EMPTY \
-								   Mask */
-
-#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS                                   \
-	6 /**< INT_FL_TX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_FL_TX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**<                     \
-							     INT_FL_TX_FIFO_THRESH \
-							     Mask */
-
-#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
-#define MXC_F_UART_INT_FL_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
-
-#define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */
-#define MXC_F_UART_INT_FL_RX_TIMEOUT                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT   \
-							 Mask */
-
-#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
-#define MXC_F_UART_INT_FL_LAST_BREAK                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK   \
-							 Mask */
-
-/**
- * Baud rate register. Integer portion.
- */
-#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
-#define MXC_F_UART_BAUD0_IBAUD                                                 \
-	((uint32_t)(0xFFFUL                                                    \
-		    << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
-
-#define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */
-#define MXC_F_UART_BAUD0_FACTOR                                                \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */
-#define MXC_V_UART_BAUD0_FACTOR_128                                            \
-	((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */
-#define MXC_S_UART_BAUD0_FACTOR_128                                            \
-	(MXC_V_UART_BAUD0_FACTOR_128                                           \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_64                                             \
-	((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */
-#define MXC_S_UART_BAUD0_FACTOR_64                                             \
-	(MXC_V_UART_BAUD0_FACTOR_64                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_32                                             \
-	((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */
-#define MXC_S_UART_BAUD0_FACTOR_32                                             \
-	(MXC_V_UART_BAUD0_FACTOR_32                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_16                                             \
-	((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */
-#define MXC_S_UART_BAUD0_FACTOR_16                                             \
-	(MXC_V_UART_BAUD0_FACTOR_16                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */
-
-/**
- * Baud rate register. Decimal Setting.
- */
-#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
-#define MXC_F_UART_BAUD1_DBAUD                                                 \
-	((uint32_t)(0xFFFUL                                                    \
-		    << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
-
-/**
- * FIFO Data buffer.
- */
-#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
-#define MXC_F_UART_FIFO_FIFO                                                   \
-	((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask   \
-							  */
-
-
-/**
- * DMA Configuration.
- */
-#define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */
-#define MXC_F_UART_DMA_TDMA_EN                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */
-#define MXC_V_UART_DMA_TDMA_EN_DIS                                             \
-	((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */
-#define MXC_S_UART_DMA_TDMA_EN_DIS                                             \
-	(MXC_V_UART_DMA_TDMA_EN_DIS                                            \
-	 << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */
-#define MXC_V_UART_DMA_TDMA_EN_EN                                              \
-	((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value                            \
-			   */
-#define MXC_S_UART_DMA_TDMA_EN_EN                                              \
-	(MXC_V_UART_DMA_TDMA_EN_EN                                             \
-	 << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */
-
-#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
-#define MXC_F_UART_DMA_RXDMA_EN                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
-#define MXC_V_UART_DMA_RXDMA_EN_DIS                                            \
-	((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */
-#define MXC_S_UART_DMA_RXDMA_EN_DIS                                            \
-	(MXC_V_UART_DMA_RXDMA_EN_DIS                                           \
-	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */
-#define MXC_V_UART_DMA_RXDMA_EN_EN                                             \
-	((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */
-#define MXC_S_UART_DMA_RXDMA_EN_EN                                             \
-	(MXC_V_UART_DMA_RXDMA_EN_EN                                            \
-	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */
-
-#define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */
-#define MXC_F_UART_DMA_TXDMA_LEVEL                                             \
-	((uint32_t)(0x3FUL                                                     \
-		    << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL   \
-							   Mask */
-
-#define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */
-#define MXC_F_UART_DMA_RXDMA_LEVEL                                             \
-	((uint32_t)(0x3FUL                                                     \
-		    << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL   \
-							   Mask */
-
-/**
- * Transmit FIFO Status register.
- */
-#define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */
-#define MXC_F_UART_TX_FIFO_DATA                                                \
-	((uint32_t)(0x7FUL                                                     \
-		    << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */
-
-#endif /* _UART_REGS_H_ */
diff --git a/chip/max32660/wdt_chip.c b/chip/max32660/wdt_chip.c
deleted file mode 100644
index 1c99c798fc..0000000000
--- a/chip/max32660/wdt_chip.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Watchdog Module */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-#include "console.h"
-#include "registers.h"
-#include "board.h"
-#include "wdt_regs.h"
-
-#define CPUTS(outstr) cputs(CC_COMMAND, outstr)
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
-
-/* For a System clock of 96MHz, 
- *     Time in seconds = 96000000 / 2 * 2^power
- * Example for MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29
- *     Time in seconds = 96000000 / 2 * 2^29
- *                     = 11.1 Seconds
- */
-#define WATCHDOG_TIMER_PERIOD MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29
-
-volatile int starve_dog = 0;
-
-void watchdog_reload(void)
-{
-	if (!starve_dog) {
-		/* Reset the watchdog */
-		MXC_WDT0->rst = 0x00A5;
-		MXC_WDT0->rst = 0x005A;
-	}
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	/* Set the Watchdog period */
-	MXC_SETFIELD(MXC_WDT0->ctrl, MXC_F_WDT_CTRL_RST_PERIOD,
-		     (WATCHDOG_TIMER_PERIOD << 4));
-
-	/* We want the WD to reset us if it is not fed in time. */
-	MXC_WDT0->ctrl |= MXC_F_WDT_CTRL_RST_EN;
-	/* Enable the watchdog */
-	MXC_WDT0->ctrl |= MXC_F_WDT_CTRL_WDT_EN;
-	/* Reset the watchdog */
-	MXC_WDT0->rst = 0x00A5;
-	MXC_WDT0->rst = 0x005A;
-	return EC_SUCCESS;
-}
-
-static int command_watchdog_test(int argc, char **argv)
-{
-	starve_dog = 1;
-
-	CPRINTS("done command_watchdog_test.");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(wdttest, command_watchdog_test, "wdttest",
-			"Force a WDT reset.");
diff --git a/chip/max32660/wdt_regs.h b/chip/max32660/wdt_regs.h
deleted file mode 100644
index 32d6fe0925..0000000000
--- a/chip/max32660/wdt_regs.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the WDT Peripheral */
-
-#ifndef _WDT_REGS_H_
-#define _WDT_REGS_H_
-
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/**
- * Structure type to access the WDT Registers.
- */
-typedef struct {
-	__IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> WDT CTRL Register */
-	__O uint32_t rst;   /**< <tt>\b 0x04:<\tt> WDT RST Register */
-} mxc_wdt_regs_t;
-
-/**
- * WDT Peripheral Register Offsets from the WDT Base Peripheral
- * Address.
- */
-#define MXC_R_WDT_CTRL                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_WDT_RST                                                          \
-	((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt>       \
-				    0x0x004 */
-
-/**
- * Watchdog Timer Control Register.
- */
-#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */
-#define MXC_F_WDT_CTRL_INT_PERIOD                                              \
-	((uint32_t)(                                                           \
-		0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD  \
-							    Mask */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                                    \
-	((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                                    \
-	((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                                    \
-	((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                                    \
-	((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                                    \
-	((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                                    \
-	((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                                    \
-	((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                                    \
-	((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                                    \
-	((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                                    \
-	((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                                    \
-	((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                                    \
-	((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                                    \
-	((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                                    \
-	((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                                    \
-	((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                                    \
-	((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16      \
-					      Setting */
-
-#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */
-#define MXC_F_WDT_CTRL_RST_PERIOD                                              \
-	((uint32_t)(                                                           \
-		0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD  \
-							    Mask */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                                    \
-	((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                                    \
-	((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                                    \
-	((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                                    \
-	((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                                    \
-	((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                                    \
-	((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                                    \
-	((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                                    \
-	((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                                    \
-	((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                                    \
-	((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                                    \
-	((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                                    \
-	((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                                    \
-	((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                                    \
-	((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                                    \
-	((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                                    \
-	((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16      \
-					      Setting */
-
-#define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */
-#define MXC_F_WDT_CTRL_WDT_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
-#define MXC_V_WDT_CTRL_WDT_EN_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */
-#define MXC_S_WDT_CTRL_WDT_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_WDT_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_WDT_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value                            \
-			   */
-#define MXC_S_WDT_CTRL_WDT_EN_EN                                               \
-	(MXC_V_WDT_CTRL_WDT_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */
-
-#define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */
-#define MXC_F_WDT_CTRL_INT_FLAG                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
-#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                       \
-	((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */
-#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE                                       \
-	(MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                      \
-	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting   \
-					  */
-#define MXC_V_WDT_CTRL_INT_FLAG_PENDING                                        \
-	((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */
-#define MXC_S_WDT_CTRL_INT_FLAG_PENDING                                        \
-	(MXC_V_WDT_CTRL_INT_FLAG_PENDING                                       \
-	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */
-
-#define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */
-#define MXC_F_WDT_CTRL_INT_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
-#define MXC_V_WDT_CTRL_INT_EN_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */
-#define MXC_S_WDT_CTRL_INT_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_INT_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_INT_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value                            \
-			   */
-#define MXC_S_WDT_CTRL_INT_EN_EN                                               \
-	(MXC_V_WDT_CTRL_INT_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */
-
-#define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */
-#define MXC_F_WDT_CTRL_RST_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
-#define MXC_V_WDT_CTRL_RST_EN_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */
-#define MXC_S_WDT_CTRL_RST_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_RST_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_RST_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value                            \
-			   */
-#define MXC_S_WDT_CTRL_RST_EN_EN                                               \
-	(MXC_V_WDT_CTRL_RST_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */
-
-#define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */
-#define MXC_F_WDT_CTRL_RST_FLAG                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
-#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                                        \
-	((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */
-#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT                                        \
-	(MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                                       \
-	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */
-#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                       \
-	((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */
-#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED                                       \
-	(MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                      \
-	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting   \
-					  */
-
-/**
- * Watchdog Timer Reset Register.
- */
-#define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */
-#define MXC_F_WDT_RST_WDT_RST                                                  \
-	((uint32_t)(                                                           \
-		0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
-#define MXC_V_WDT_RST_WDT_RST_SEQ0                                             \
-	((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
-#define MXC_S_WDT_RST_WDT_RST_SEQ0                                             \
-	(MXC_V_WDT_RST_WDT_RST_SEQ0                                            \
-	 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
-#define MXC_V_WDT_RST_WDT_RST_SEQ1                                             \
-	((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
-#define MXC_S_WDT_RST_WDT_RST_SEQ1                                             \
-	(MXC_V_WDT_RST_WDT_RST_SEQ1                                            \
-	 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
-
-#endif /* _WDT_REGS_H_ */
diff --git a/chip/mchp/adc.c b/chip/mchp/adc.c
deleted file mode 100644
index d40a8a9d1c..0000000000
--- a/chip/mchp/adc.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-/*
- * Conversion on a single channel takes less than 12 ms. Set timeout to
- * 15 ms so that we have a 3-ms margin.
- */
-#define ADC_SINGLE_READ_TIME 15000
-
-struct mutex adc_lock;
-
-/*
- * Volatile should not be needed.
- * ADC ISR only reads task_waiting.
- * Two other non-ISR routines only write task_waiting when
- * interrupt is disabled or before starting ADC.
- */
-static task_id_t task_waiting;
-
-/*
- * Start ADC single-shot conversion.
- * 1. Disable ADC interrupt.
- * 2. Clear sticky hardware status.
- * 3. Start conversion.
- * 4. Enable interrupt.
- * 5. Wait with timeout for ADC ISR to
- *    to set TASK_EVENT_TIMER.
- */
-static int start_single_and_wait(int timeout)
-{
-	int event;
-
-	MCHP_INT_DISABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-	task_waiting = task_get_current();
-
-	/* clear all R/W1C channel status */
-	MCHP_ADC_STS = 0xffffu;
-	/* clear R/W1C single done status */
-	MCHP_ADC_CTRL |= BIT(7);
-	/* clear GIRQ single status */
-	MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-	/* make sure all writes are issued before starting conversion */
-	asm volatile ("dsb");
-
-	/* Start conversion */
-	MCHP_ADC_CTRL |= BIT(1);
-
-	MCHP_INT_ENABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-
-	/* Wait for interrupt, ISR disables interrupt */
-	event = task_wait_event(timeout);
-	task_waiting = TASK_ID_INVALID;
-	return event != TASK_EVENT_TIMER;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-
-	mutex_lock(&adc_lock);
-
-	MCHP_ADC_SINGLE = 1 << adc->channel;
-
-	if (start_single_and_wait(ADC_SINGLE_READ_TIME))
-		value = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) /
-			adc->factor_div + adc->shift;
-	else
-		value = ADC_READ_ERROR;
-
-	mutex_unlock(&adc_lock);
-	return value;
-}
-
-int adc_read_all_channels(int *data)
-{
-	int i;
-	int ret = EC_SUCCESS;
-	const struct adc_t *adc;
-
-	mutex_lock(&adc_lock);
-
-	MCHP_ADC_SINGLE = 0;
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		MCHP_ADC_SINGLE |= 1 << adc_channels[i].channel;
-
-	if (!start_single_and_wait(ADC_SINGLE_READ_TIME * ADC_CH_COUNT)) {
-		ret = EC_ERROR_TIMEOUT;
-		goto exit_all_channels;
-	}
-
-	for (i = 0; i < ADC_CH_COUNT; ++i) {
-		adc = adc_channels + i;
-		data[i] = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) /
-			  adc->factor_div + adc->shift;
-	}
-
-exit_all_channels:
-	mutex_unlock(&adc_lock);
-
-	return ret;
-}
-
-/*
- * Enable GPIO pins.
- * Using MEC17xx direct mode interrupts. Do not
- * set Interrupt Aggregator Block Enable bit
- * for GIRQ containing ADC.
- */
-static void adc_init(void)
-{
-	trace0(0, ADC, 0, "adc_init");
-
-	gpio_config_module(MODULE_ADC, 1);
-
-	/* clear ADC sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ADC);
-
-	/* Activate ADC module */
-	MCHP_ADC_CTRL |= BIT(0);
-
-	/* Enable interrupt */
-	task_waiting = TASK_ID_INVALID;
-	MCHP_INT_ENABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-	task_enable_irq(MCHP_IRQ_ADC_SNGL);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
-
-void adc_interrupt(void)
-{
-	MCHP_INT_DISABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-
-	/* clear individual chan conversion status */
-	MCHP_ADC_STS = 0xffffu;
-
-	/* Clear interrupt status bit */
-	MCHP_ADC_CTRL |= BIT(7);
-
-	MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-
-	if (task_waiting != TASK_ID_INVALID)
-		task_wake(task_waiting);
-}
-DECLARE_IRQ(MCHP_IRQ_ADC_SNGL, adc_interrupt, 2);
diff --git a/chip/mchp/adc_chip.h b/chip/mchp/adc_chip.h
deleted file mode 100644
index 0f14d5a459..0000000000
--- a/chip/mchp/adc_chip.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MCHP MEC specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-};
-
-/* List of ADC channels */
-enum chip_adc_channel {
-	CHIP_ADC_CH0 = 0,
-	CHIP_ADC_CH1,
-	CHIP_ADC_CH2,
-	CHIP_ADC_CH3,
-	CHIP_ADC_CH4,
-	CHIP_ADC_CH5,
-	CHIP_ADC_CH6,
-	CHIP_ADC_CH7,
-	CHIP_ADC_COUNT,
-};
-
-/* Minimum and maximum values returned by adc_read_channel(). */
-#define ADC_READ_MIN 0
-#ifdef CHIP_FAMILY_MEC172X
-/* MEC172x ADC is 12BIT resolution in default */
-#define ADC_READ_MAX 4095
-#else
-#define ADC_READ_MAX 1023
-#endif
-
-/* Just plain id mapping for code readability */
-#define MCHP_ADC_CH(x) (x)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
deleted file mode 100644
index 155fbf385f..0000000000
--- a/chip/mchp/build.mk
+++ /dev/null
@@ -1,119 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Microchip(MCHP) MEC chip specific files build
-#
-
-# pass verbose build setting to SPI image generation script
-SCRIPTVERBOSE=
-ifeq ($(V),1)
-SCRIPTVERBOSE=--verbose
-endif
-
-# MCHP MEC SoC's have a Cortex-M4 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# JTAG debug with Keil ARM MDK debugger
-# do not allow GCC dwarf debug extensions
-#CFLAGS_DEBUG_EXTRA=-gdwarf-3 -gstrict-dwarf
-
-LDFLAGS_EXTRA=
-
-ifeq ($(CONFIG_LTO),y)
-# Re-include the core's build.mk file so we can remove the lto flag.
-include core/$(CORE)/build.mk
-endif
-
-# Required chip modules
-chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o tfdp.o
-chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_DMA)+=dma.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_MEC_GPIO_EC_CMDS)+=gpio_cmds.o
-chip-$(CONFIG_HOSTCMD_X86)+=lpc.o
-chip-$(CONFIG_MCHP_GPSPI)+=gpspi.o
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_SPI)+=spi.o qmspi.o
-chip-$(CONFIG_TFDP)+=tfdp.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-
-# location of the scripts and keys used to pack the SPI flash image
-SCRIPTDIR:=./chip/${CHIP}/util
-
-# Allow SPI size to be overridden by board specific size, default to 512KB
-CHIP_SPI_SIZE_KB?=512
-
-TEST_SPI=
-ifeq ($(CONFIG_MCHP_LFW_DEBUG),y)
-	TEST_SPI=--test_spi
-endif
-
-# Select chip. Default is MEC170X
-PACK_EC=pack_ec.py
-ifeq ($(CHIP_FAMILY),mec152x)
-	PACK_EC=pack_ec_mec152x.py
-endif
-ifeq ($(CHIP_FAMILY),mec172x)
-	PACK_EC=pack_ec_mec172x.py
-endif
-
-# pack_ec.py creates SPI flash image for MEC
-# _rw_size is CONFIG_RW_SIZE
-# Commands to convert $^ to $@.tmp
-cmd_obj_to_bin = $(OBJCOPY) --gap-fill=0xff -O binary $< $@.tmp1 ; \
-		 ${SCRIPTDIR}/${PACK_EC} -o $@.tmp -i $@.tmp1 \
-		--loader_file $(chip-lfw-flat) ${TEST_SPI} \
-		--spi_size ${CHIP_SPI_SIZE_KB} \
-		--image_size $(_rw_size) ${SCRIPTVERBOSE}; rm -f $@.tmp1
-
-chip-lfw = chip/${CHIP}/lfw/ec_lfw
-chip-lfw-flat = $(out)/RW/$(chip-lfw)-lfw.flat
-
-# build these specifically for lfw with -lfw suffix
-objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \
-		$(addprefix common/, util util_stdlib gpio) \
-		$(addprefix chip/$(CHIP)/, spi qmspi dma gpio clock hwtimer tfdp) \
-		core/$(CORE)/cpu $(chip-lfw))
-
-# reuse version.o (and its dependencies) from main board
-objs_lfw += $(out)/RW/common/version.o
-
-dirs-y+=chip/$(CHIP)/lfw
-
-# objs with -lfw suffix are to include lfw's gpio
-$(out)/RW/%-lfw.o: private CC+=-Ichip/mchp/lfw -DLFW=$(EMPTY)
-# Remove the lto flag for the loader.  It actually causes it to bloat in size.
-ifeq ($(CONFIG_LTO),y)
-$(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU))
-endif
-$(out)/RW/%-lfw.o: %.c
-	$(call quiet,c_to_o,CC     )
-
-# let lfw's elf link only with selected objects
-ifeq ($(CHIP_FAMILY),mec172x)
-$(out)/RW/%-lfw.elf: private objs = $(objs_lfw)
-$(out)/RW/%-lfw.elf: override shlib :=
-$(out)/RW/%-lfw.elf: %_416kb.ld $(objs_lfw)
-	$(call quiet,elf,LD     )
-
-# final image needs lfw loader
-$(out)/$(PROJECT).bin: $(chip-lfw-flat)
-else
-$(out)/RW/%-lfw.elf: private objs = $(objs_lfw)
-$(out)/RW/%-lfw.elf: override shlib :=
-$(out)/RW/%-lfw.elf: %.ld $(objs_lfw)
-	$(call quiet,elf,LD     )
-
-# final image needs lfw loader
-$(out)/$(PROJECT).bin: $(chip-lfw-flat)
-endif
diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c
deleted file mode 100644
index 362025ee1c..0000000000
--- a/chip/mchp/clock.c
+++ /dev/null
@@ -1,780 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "tfdp_chip.h"
-#include "vboot_hash.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#ifdef CONFIG_LOW_POWER_IDLE
-
-#define HTIMER_DIV_1_US_MAX	(1998848)
-#define HTIMER_DIV_1_1SEC	(0x8012)
-
-/* Recovery time for HvySlp2 is 0 us */
-#define HEAVY_SLEEP_RECOVER_TIME_USEC   75
-
-#define SET_HTIMER_DELAY_USEC           200
-
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t total_idle_dsleep_time_us;
-
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-static uint32_t pcr_slp_en[MCHP_PCR_SLP_RST_REG_MAX];
-static uint32_t pcr_clk_req[MCHP_PCR_SLP_RST_REG_MAX];
-static uint32_t ecia_result[MCHP_INT_GIRQ_NUM];
-#endif
-
-/*
- * Fixed amount of time to keep the console in use flag true after
- * boot in order to give a permanent window in which the heavy sleep
- * mode is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-static int console_in_use_timeout_sec = 60;
-static timestamp_t console_expire_time;
-#endif /*CONFIG_LOW_POWER_IDLE */
-
-static int freq = 48000000;
-
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-/*
- * MEC170x and MEC152x have the same 32 KHz clock enable hardware.
- * MEC172x 32 KHz clock configuration is different and includes
- * hardware to check the crystal before switching and to monitor
- * the 32 KHz input if desired.
- */
-#ifdef CHIP_FAMILY_MEC172X
-/* 32 KHz crystal connected in parallel */
-static inline void config_32k_src_crystal(void)
-{
-	MCHP_VBAT_CSS = MCHP_VBAT_CSS_XTAL_EN
-			| MCHP_VBAT_CSS_SRC_XTAL;
-}
-
-/* 32 KHz source is 32KHZ_IN pin which must be configured */
-static inline void config_32k_src_se_input(void)
-{
-	MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN
-				| MCHP_VBAT_CSS_SRC_SWPS;
-}
-
-static inline void config_32k_src_sil_osc(void)
-{
-	MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN;
-}
-
-#else
-static void config_32k_src_crystal(void)
-{
-	MCHP_VBAT_CE = MCHP_VBAT_CE_XOSEL_PAR
-			| MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL;
-}
-
-/* 32 KHz source is 32KHZ_IN pin which must be configured */
-static inline void config_32k_src_se_input(void)
-{
-	MCHP_VBAT_CE = MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN
-			| MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT;
-}
-
-static inline void config_32k_src_sil_osc(void)
-{
-	MCHP_VBAT_CE = ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN
-			| MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL);
-}
-#endif
-
-/** clock_init
- * @note
- * MCHP MEC implements 4 control bits in the VBAT Clock Enable register.
- * It also implements an internal silicon 32KHz +/- 2% oscillator powered
- * by VBAT.
- * b[3] = XOSEL 0=parallel, 1=single-ended
- * b[2] = 32KHZ_SOURCE specifies source of always-on clock domain
- *        0=internal silicon oscillator
- *        1=crystal XOSEL pin(s)
- * b[1] = EXT_32K use always-on clock domain or external 32KHZ_IN pin
- *        0=32K source is always-on clock domain
- *        1=32K source is 32KHZ_IN pin (GPIO 0165)
- * b[0] = 32K_SUPPRESS
- *        0=32K clock domain stays enabled if VTR is off. Powered by VBAT
- *        1=32K clock domain is disabled if VTR is off.
- * Set b[3] based on CONFIG_CLOCK_CRYSTAL
- * Set b[2:0] = 100b
- *    b[0]=0 32K clock domain always on (requires VBAT if VTR is off)
- *    b[1]=0 32K source is the 32K clock domain NOT the 32KHZ_IN pin
- *    b[2]=1 If activity detected on crystal pins switch 32K input from
- *           internal silicon oscillator to XOSEL pin(s) based on b[3].
- */
-void clock_init(void)
-{
-	if (IS_ENABLED(CONFIG_CLOCK_SRC_EXTERNAL))
-		if (IS_ENABLED(CONFIG_CLOCK_CRYSTAL))
-			config_32k_src_crystal();
-		else
-			/* 32KHz 50% duty waveform on 32KHZ_IN pin */
-			config_32k_src_se_input();
-	else
-		/* Use internal silicon 32KHz OSC */
-		config_32k_src_sil_osc();
-
-	/* Wait for PLL to lock onto 32KHz source (OSC_LOCK == 1) */
-	while (!(MCHP_PCR_CHIP_OSC_ID & 0x100))
-		;
-}
-
-/**
- * Speed through boot + vboot hash calculation, dropping our processor
- * clock only after vboot hashing is completed.
- */
-static void clock_turbo_disable(void);
-DECLARE_DEFERRED(clock_turbo_disable);
-
-static void clock_turbo_disable(void)
-{
-#ifdef CONFIG_VBOOT_HASH
-	if (vboot_hash_in_progress())
-		hook_call_deferred(&clock_turbo_disable_data, 100 * MSEC);
-	else
-#endif
-		/* Use 12 MHz processor clock for power savings */
-		MCHP_PCR_PROC_CLK_CTL = MCHP_PCR_CLK_CTL_12MHZ;
-}
-DECLARE_HOOK(HOOK_INIT,
-		clock_turbo_disable,
-		HOOK_PRIO_INIT_VBOOT_HASH + 1);
-
-/**
- * initialization of Hibernation timer 0
- * Clear PCR sleep enable.
- * GIRQ=21, aggregator bit = 1, Direct NVIC = 112
- * NVIC direct connect interrupts are used for all peripherals
- * (exception GPIO's) then the MCHP_INT_BLK_EN GIRQ bit should not be
- * set.
- */
-void htimer_init(void)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_HTMR0);
-	MCHP_HTIMER_PRELOAD(0) = 0; /* disable at beginning */
-	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) = MCHP_HTIMER_GIRQ_BIT(0);
-	MCHP_INT_ENABLE(MCHP_HTIMER_GIRQ) = MCHP_HTIMER_GIRQ_BIT(0);
-
-	task_enable_irq(MCHP_IRQ_HTIMER0);
-}
-
-/**
- * Use hibernate module to set up an htimer interrupt at a given
- * time from now
- *
- * @param seconds      Number of seconds before htimer interrupt
- * @param microseconds Number of microseconds before htimer interrupt
- * @note hibernation timer input clock is 32.768KHz.
- * Control register bit[0] selects the divider.
- * 0 is divide by 1 for 30.5 us per LSB for a maximum of
- *	65535 * 30.5 us = 1998817.5 us or 32.786 counts per second
- * 1 is divide by 4096 for 0.125 s per LSB for a maximum of ~2 hours.
- *	65535 * 0.125 s ~ 8192 s = 2.27 hours
- */
-void system_set_htimer_alarm(uint32_t seconds,
-		uint32_t microseconds)
-{
-	uint32_t hcnt, ns;
-	uint8_t hctrl;
-
-	MCHP_HTIMER_PRELOAD(0) = 0; /* disable */
-
-	if (microseconds > 1000000ul) {
-		ns = (microseconds / 1000000ul);
-		microseconds %= 1000000ul;
-		if ((0xfffffffful - seconds) > ns)
-			seconds += ns;
-		else
-			seconds = 0xfffffffful;
-	}
-
-	if (seconds > 1) {
-		hcnt = (seconds << 3);	/* divide by 0.125 */
-		if (hcnt > 0xfffful)
-			hcnt = 0xfffful;
-		hctrl = 1;
-	} else {
-		/*
-		 * approximate(~2% error) as seconds is 0 or 1
-		 * seconds / 30.5e-6 + microseconds / 30.5
-		 */
-		hcnt = (seconds << 15) + (microseconds >> 5) +
-			(microseconds >> 10);
-		hctrl = 0;
-	}
-
-	MCHP_HTIMER_CONTROL(0) = hctrl;
-	MCHP_HTIMER_PRELOAD(0) = hcnt;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-
-/**
- * return time slept in micro-seconds
- */
-static timestamp_t system_get_htimer(void)
-{
-	uint16_t count;
-	timestamp_t time;
-
-	count =  MCHP_HTIMER_COUNT(0);
-
-
-	if (MCHP_HTIMER_CONTROL(0) == 1) /* if > 2 sec */
-		/* 0.125 sec per count */
-		time.le.lo = (uint32_t)(count * 125000);
-	else    /* if < 2 sec */
-		/* 30.5(=61/2) us per count */
-		time.le.lo = (uint32_t)(count * 61 / 2);
-
-	time.le.hi = 0;
-
-	return time;  /* in uSec */
-}
-
-/**
- * Disable and clear hibernation timer interrupt
- */
-static void system_reset_htimer_alarm(void)
-{
-	MCHP_HTIMER_PRELOAD(0) = 0;
-	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) =
-			MCHP_HTIMER_GIRQ_BIT(0);
-}
-
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-static void print_pcr_regs(void)
-{
-	int i;
-
-	trace0(0, MEC, 0, "Current PCR registers");
-	for (i = 0; i < 5; i++) {
-		trace12(0, MEC, 0, "REG  SLP_EN[%d] = 0x%08X",
-			i, MCHP_PCR_SLP_EN(i));
-		trace12(0, MEC, 0, "REG CLK_REQ[%d] = 0x%08X",
-			i, MCHP_PCR_CLK_REQ(i));
-	}
-}
-
-static void print_ecia_regs(void)
-{
-	int i;
-
-	trace0(0, MEC, 0, "Current GIRQn.Result registers");
-	for (i = MCHP_INT_GIRQ_FIRST;
-			i <= MCHP_INT_GIRQ_LAST; i++)
-		trace12(0, MEC, 0, "GIRQ[%d].Result = 0x%08X",
-			i, MCHP_INT_RESULT(i));
-}
-
-static void save_regs(void)
-{
-	int i;
-
-	for (i = 0; i < MCHP_PCR_SLP_RST_REG_MAX; i++) {
-		pcr_slp_en[i] = MCHP_PCR_SLP_EN(i);
-		pcr_clk_req[i] = MCHP_PCR_CLK_REQ(i);
-	}
-
-	for (i = 0; i < MCHP_INT_GIRQ_NUM; i++)
-		ecia_result[i] =
-			MCHP_INT_RESULT(MCHP_INT_GIRQ_FIRST + i);
-}
-
-static void print_saved_regs(void)
-{
-	int i;
-
-	trace0(0, BRD, 0, "Before sleep saved registers");
-	for (i = 0; i < MCHP_PCR_SLP_RST_REG_MAX; i++) {
-		trace12(0, BRD, 0, "PCR_SLP_EN[%d]  = 0x%08X",
-			i, pcr_slp_en[i]);
-		trace12(0, BRD, 0, "PCR_CLK_REQ[%d] = 0x%08X",
-			i, pcr_clk_req[i]);
-	}
-
-	for (i = 0; i < MCHP_INT_GIRQ_NUM; i++)
-		trace12(0, BRD, 0, "GIRQ[%d].Result = 0x%08X",
-			(i+MCHP_INT_GIRQ_FIRST), ecia_result[i]);
-}
-#else
-static __maybe_unused void print_pcr_regs(void) {}
-static __maybe_unused void print_ecia_regs(void) {}
-static __maybe_unused void save_regs(void) {}
-static __maybe_unused void print_saved_regs(void) {}
-#endif /* #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG */
-
-/**
- * This is MCHP specific and equivalent to ARM Cortex's
- * 'DeepSleep' via system control block register, CPU_SCB_SYSCTRL
- * MCHP has new SLP_ALL feature.
- * When SLP_ALL is enabled and HW sees sleep entry trigger from CPU.
- * 1. HW saves PCR.SLP_EN registers
- * 2. HW sets all PCR.SLP_EN bits to 1.
- * 3. System sleeps
- * 4. wake event wakes system
- * 5. HW restores original values of all PCR.SLP_EN registers
- * NOTE1: Current RTOS core (Cortex-M4) does not use SysTick timer.
- * We can leave code to disable it but do not re-enable on wake.
- * NOTE2: Some peripherals will not sleep until outstanding transactions
- * are complete: I2C, DMA, GPSPI, QMSPI, etc.
- * NOTE3: Security blocks do not fully implement HW sleep therefore their
- * sleep enables must be manually set/restored.
- *
- */
-static void prepare_for_deep_sleep(void)
-{
-	/* sysTick timer */
-	CPU_NVIC_ST_CTRL &= ~ST_ENABLE;
-	CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG;
-
-	CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */
-
-	/* Enable assertion of DeepSleep signals
-	 * from the core when core enters sleep.
-	 */
-	CPU_SCB_SYSCTRL |= BIT(2);
-
-	/* Stop timers */
-	MCHP_TMR32_CTL(0) &= ~1;
-	MCHP_TMR32_CTL(1) &= ~1;
-#ifdef CONFIG_WATCHDOG_HELP
-	MCHP_TMR16_CTL(0) &= ~1;
-	MCHP_INT_DISABLE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
-	MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
-#endif
-	MCHP_INT_DISABLE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-
-#ifdef CONFIG_WATCHDOG
-	/* Stop watchdog */
-	MCHP_WDG_CTL &= ~1;
-#endif
-
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-	MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-#else
-	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-	MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-#endif
-
-#ifdef CONFIG_ADC
-	/*
-	 * Clear ADC activate bit. If a conversion is in progress the
-	 * ADC block will not enter low power until the conversion is
-	 * complete.
-	 */
-	MCHP_ADC_CTRL &= ~1;
-#endif
-
-	/* stop Port80 capture timer */
-#ifndef CHIP_FAMILY_MEC172X
-	MCHP_P80_ACTIVATE(0) = 0;
-#endif
-
-	/*
-	 * Clear SLP_EN bit(s) for wake sources.
-	 * Currently only Hibernation timer 0.
-	 * GPIO pins can always wake.
-	 */
-	MCHP_PCR_SLP_EN3 &= ~(MCHP_PCR_SLP_EN3_HTMR0);
-
-#ifdef CONFIG_PWM
-	pwm_keep_awake(); /* clear sleep enables of active PWM's */
-#else
-	/* Disable 100 Khz clock */
-	MCHP_PCR_SLOW_CLK_CTL &= 0xFFFFFC00;
-#endif
-
-#ifdef CONFIG_CHIPSET_DEBUG
-	/* Disable JTAG and preserve mode */
-	MCHP_EC_JTAG_EN &= ~(MCHP_JTAG_ENABLE);
-#endif
-
-	/* call board level */
-#ifdef CONFIG_BOARD_DEEP_SLEEP
-	board_prepare_for_deep_sleep();
-#endif
-
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-	save_regs();
-#endif
-}
-
-static void resume_from_deep_sleep(void)
-{
-	MCHP_PCR_SYS_SLP_CTL = 0x00;  /* default */
-
-	/* Disable assertion of DeepSleep signal when core executes WFI */
-	CPU_SCB_SYSCTRL &= ~BIT(2);
-
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-	print_saved_regs();
-	print_pcr_regs();
-	print_ecia_regs();
-#endif
-
-#ifdef CONFIG_CHIPSET_DEBUG
-	MCHP_EC_JTAG_EN |= (MCHP_JTAG_ENABLE);
-#endif
-
-	MCHP_PCR_SLOW_CLK_CTL |= 0x1e0;
-
-	/* call board level */
-#ifdef CONFIG_BOARD_DEEP_SLEEP
-	board_resume_from_deep_sleep();
-#endif
-	/*
-	 * re-enable hibernation timer 0 PCR.SLP_EN to
-	 * reduce power.
-	 */
-	MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	#ifdef CONFIG_POWER_S0IX
-	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-	#else
-	MCHP_ESPI_ACTIVATE |= 1;
-	#endif
-#else
-	#ifdef CONFIG_POWER_S0IX
-	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-	#else
-	MCHP_LPC_ACT |= 1;
-	#endif
-#endif
-
-	/* re-enable Port 80 capture */
-#ifndef CHIP_FAMILY_MEC172X
-	MCHP_P80_ACTIVATE(0) = 1;
-#endif
-
-#ifdef CONFIG_ADC
-	MCHP_ADC_CTRL |= 1;
-#endif
-
-	/* Enable timer */
-	MCHP_TMR32_CTL(0) |= 1;
-	MCHP_TMR32_CTL(1) |= 1;
-	MCHP_TMR16_CTL(0) |= 1;
-	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-	MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
-
-	/* Enable watchdog */
-#ifdef CONFIG_WATCHDOG
-#ifdef CONFIG_CHIPSET_DEBUG
-	/* enable WDG stall on active JTAG and do not start */
-	MCHP_WDG_CTL = BIT(4);
-#else
-	MCHP_WDG_CTL |= 1;
-#endif
-#endif
-}
-
-
-void clock_refresh_console_in_use(void)
-{
-	disable_sleep(SLEEP_MASK_CONSOLE);
-
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-}
-
-/**
- * Low power idle task. Executed when no tasks are ready to be scheduled.
- */
-void __idle(void)
-{
-	timestamp_t t0;
-	timestamp_t t1;
-	timestamp_t ht_t1;
-	uint32_t next_delay;
-	uint32_t max_sleep_time;
-	int time_for_dsleep;
-	int uart_ready_for_deepsleep;
-
-	htimer_init(); /* hibernation timer initialize */
-
-	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val +
-			CONSOLE_IN_USE_ON_BOOT_TIME;
-
-
-	/*
-	 * Print when the idle task starts. This is the lowest priority
-	 * task, so this only starts once all other tasks have gotten a
-	 * chance to do their task initializations and have gone to sleep.
-	 */
-	CPRINTS("MEC low power idle task started");
-
-	while (1) {
-		/* Disable interrupts */
-		interrupt_disable();
-
-		t0 = get_time();  /* uSec */
-
-		/* __hw_clock_event_get() is next programmed timer event */
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		time_for_dsleep = next_delay >
-			(HEAVY_SLEEP_RECOVER_TIME_USEC +
-			SET_HTIMER_DELAY_USEC);
-
-		max_sleep_time = next_delay -
-				HEAVY_SLEEP_RECOVER_TIME_USEC;
-
-		/* check if there enough time for deep sleep */
-		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-			/*
-			 * Check if the console use has expired and
-			 * console sleep is masked by GPIO(UART-RX)
-			 * interrupt.
-			 */
-			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-				t0.val > console_expire_time.val) {
-				/* allow console to sleep. */
-				enable_sleep(SLEEP_MASK_CONSOLE);
-
-				/*
-				 * Wait one clock before checking if
-				 * heavy sleep is allowed to give time
-				 * for sleep mask to be updated.
-				 */
-				clock_wait_cycles(1);
-
-				if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
-					CPRINTS("MEC Disable console "
-						"in deep sleep");
-			}
-
-
-			/* UART is not being used  */
-			uart_ready_for_deepsleep =
-				LOW_SPEED_DEEP_SLEEP_ALLOWED &&
-					!uart_tx_in_progress() &&
-					uart_buffer_empty();
-
-			/*
-			 * Since MCHP's heavy sleep mode requires all
-			 * blocks to be sleep capable, UART/console
-			 * readiness is final decision factor of
-			 * heavy sleep of EC.
-			 */
-			if (uart_ready_for_deepsleep) {
-
-				idle_dsleep_cnt++;
-
-				/*
-				 * configure UART Rx as GPIO wakeup
-				 * interrupt source
-				 */
-				uart_enter_dsleep();
-
-				/* MCHP specific deep-sleep mode */
-				prepare_for_deep_sleep();
-
-				/*
-				 * 'max_sleep_time' value should be big
-				 * enough so that hibernation timer's
-				 * interrupt triggers only after 'wfi'
-				 * completes its execution.
-				 */
-				max_sleep_time -=
-					(get_time().le.lo - t0.le.lo);
-
-				/* setup/enable htimer wakeup interrupt */
-				system_set_htimer_alarm(0,
-						max_sleep_time);
-
-				/* set sleep all just before WFI */
-				MCHP_PCR_SYS_SLP_CTL |=
-						MCHP_PCR_SYS_SLP_HEAVY;
-				MCHP_PCR_SYS_SLP_CTL |=
-						MCHP_PCR_SYS_SLP_ALL;
-
-			} else {
-				idle_sleep_cnt++;
-			}
-
-			/* Wait for interrupt: goes into deep sleep. */
-			asm("dsb");
-			asm("wfi");
-			asm("isb");
-			asm("nop");
-
-			if (uart_ready_for_deepsleep) {
-
-				resume_from_deep_sleep();
-
-				/*
-				 * Fast forward timer according to htimer
-				 * counter:
-				 * Since all blocks including timers
-				 * will be in sleep mode, timers stops
-				 * except hibernate timer.
-				 * And system schedule timer should be
-				 * corrected after wakeup by either
-				 * hibernate timer or GPIO_UART_RX
-				 * interrupt.
-				 */
-				ht_t1 = system_get_htimer();
-
-				/* disable/clear htimer wakeup interrupt */
-				system_reset_htimer_alarm();
-
-				t1.val = t0.val +
-					(uint64_t)(max_sleep_time -
-							ht_t1.le.lo);
-
-				force_time(t1);
-
-				/* re-enable UART */
-				uart_exit_dsleep();
-
-				/* Record time spent in deep sleep. */
-				total_idle_dsleep_time_us +=
-					(uint64_t)(max_sleep_time -
-							ht_t1.le.lo);
-			}
-
-		} else { /* CPU 'Sleep' mode */
-
-			idle_sleep_cnt++;
-
-			asm("wfi");
-
-		}
-
-		interrupt_enable();
-	} /* while(1) */
-}
-
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n",
-			idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n",
-			idle_dsleep_cnt);
-
-	ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n",
-			total_idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n\n",
-			ts.val);
-
-	if (IS_ENABLED(CONFIG_MCHP_DEEP_SLP_DEBUG))
-		print_pcr_regs();	/* debug */
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* defined(CONFIG_CMD_IDLE_STATS) */
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use heavy sleep mode or
-			 * allow it to use the heavy sleep mode.
-			 */
-			if (v)  /* 'on' */
-				disable_sleep(
-					SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else    /* 'off' */
-				enable_sleep(
-					SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-		"[ on | off | <timeout> sec]",
-		"Deep sleep clock settings:\nUse 'on' to force deep "
-		"sleep NOT to enter heavy sleep mode.\nUse 'off' to "
-		"allow deep sleep to use heavy sleep whenever conditions "
-		"allow.\n"
-		"Give a timeout value for the console in use timeout.\n"
-		"See also 'sleep mask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mchp/clock_chip.h b/chip/mchp/clock_chip.h
deleted file mode 100644
index 2e7de60358..0000000000
--- a/chip/mchp/clock_chip.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Microchip MEC1701 specific module for Chrome EC */
-
-#ifndef __CROS_EC_CLOCK_CHIP_H
-#define __CROS_EC_CLOCK_CHIP_H
-
-#include <stdint.h>
-
-void htimer_init(void);
-void system_set_htimer_alarm(uint32_t seconds,
-		uint32_t microseconds);
-
-#endif /* __CROS_EC_I2C_CLOCK_H */
diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h
deleted file mode 100644
index cf7ead512a..0000000000
--- a/chip/mchp/config_chip.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* Number of IRQ vectors on the NVIC */
-#ifdef CHIP_FAMILY_MEC152X
-#define CONFIG_IRQ_COUNT 174
-#elif defined(CHIP_FAMILY_MEC170X)
-#define CONFIG_IRQ_COUNT 157
-#elif defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_IRQ_COUNT 181
-#endif
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	1024
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
-
-/*
- * Enable chip_pre_init called from main
- * Used for configuring peripheral block
- * sleep enables.
- */
-#define CONFIG_CHIP_PRE_INIT
-
-/*
- * MCHP EC's have I2C controllers and multiple I2C ports. Any port may be
- * mapped to any controller at run time. Enable multi-port controller feature.
- * Board level configuration determines how many controllers/ports are used
- * and the mapping of port(s) to controller(s). NOTE: Some MCHP packages
- * may not implement all I2C ports.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-
-/*
- * MCHP I2C controllers also act as I2C peripherals listening for their
- * peripheral address. Each controller has two programmable peripheral
- * addresses. Define fake peripheral addresses that aren't used by
- * peripherals on the board.
- */
-#define CONFIG_MCHP_I2C0_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C1_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C2_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C3_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C4_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C5_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C6_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C7_SLAVE_ADDRS	0xE3E1
-
-/************************************************************************/
-/* Memory mapping */
-
-/*
- * MEC170x-H and MEC152x-H have a total of 256KB SRAM.
- *   CODE at 0xE0000 - 0x117FFF, DATA at 0x118000 - 0x11FFFF
- * MEC172x-N has a total of 416KB SRAM: 352KB CODE 64KB DATA
- *   CODE at 0xC0000 - 0x117FFF, DATA at 0x118000 - 0x127FFF
- *   Customer data preserved across reset is 1KB at 0x12_7400.
- *   Set top of SRAM to 0x12_7800.  We lose the top 2KB.
- * MCHP MEC can fetch code from data or data from code.
- */
-
-/************************************************************************/
-/* Define our RAM layout. */
-
-#if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_MEC_SRAM_BASE_START	0x000C0000
-#define CONFIG_MEC_SRAM_BASE_END	(0x00128000 - (2 * 1024))
-#else
-#define CONFIG_MEC_SRAM_BASE_START	0x000E0000
-#define CONFIG_MEC_SRAM_BASE_END	0x00120000
-#endif
-
-#define CONFIG_MEC_SRAM_SIZE		(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_MEC_SRAM_BASE_START)
-/* 64k Data RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE			0x00010000
-#define CONFIG_RAM_BASE			(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_RAM_SIZE)
-
-/* System stack size */
-/* was 1024, temporarily expanded to 2048 for debug */
-#define CONFIG_STACK_SIZE		2048
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		672
-#define LARGER_TASK_STACK_SIZE		800
-#define VENTI_TASK_STACK_SIZE		928
-#define ULTRA_TASK_STACK_SIZE		1056
-#define TRENTA_TASK_STACK_SIZE		1184
-
-#define CHARGER_TASK_STACK_SIZE		1024	/* 640 */
-#define HOOKS_TASK_STACK_SIZE		1024	/* 640 */
-#define CONSOLE_TASK_STACK_SIZE		1024	/* 640 */
-#define HOST_CMD_TASK_STACK_SIZE	1024	/* 640 */
-
-/*
- * TODO: Large stack consumption
- * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
- */
-/* original = 800, if stack exceptions expand to 1024 for debug */
-#define PD_TASK_STACK_SIZE		2048
-
-/* Default task stack size */
-#define TASK_STACK_SIZE			672
-
-/************************************************************************/
-/* Define our flash layout. */
-
-/*
- * MEC1521H loads firmware using QMSPI controller
- * CONFIG_SPI_FLASH_PORT is the index into
- * spi_devices[] in board.c
- */
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_SPI_FLASH
-
-/*
- * MEC1727 chip has integrated SPI flash with 512KB size
- */
-#if (defined(CHIP_VARIANT_MEC1727SZ) || defined(CHIP_VARIANT_MEC1727LJ))
-/* Total size of writable flash */
-#define CONFIG_FLASH_SIZE_BYTES 524288
-#endif
-
-/* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
-/* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00001000
-/* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000004
-
-/* One page size for write */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256
-
-/* Program memory base address */
-#if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_PROGRAM_MEMORY_BASE	0x000C0000
-#else
-#define CONFIG_PROGRAM_MEMORY_BASE	0x000E0000
-#endif
-
-/*
- * Optimize SPI flash read timing, MEC172x QMSPI controller controls CS#
- * by hardware, it will add several system clock cycles delay between CS
- * deassertion to CS assertion at the start of the next transaction, this
- * guarantees SPI back to back transactions, so 1ms delay can be removed
- * to optimze timing. MEC172x chip supports this hardware feature.
- */
-#if defined(CHIP_FAMILY_MEC172X)
-#undef CONFIG_SPI_FLASH_READ_WAIT_MS
-#define CONFIG_SPI_FLASH_READ_WAIT_MS 0
-#endif
-
-#include "config_flash_layout.h"
-
-/************************************************************************/
-/* Customize the build */
-/* Optional features present on this chip */
-#define CONFIG_ADC
-#define CONFIG_DMA
-#define CONFIG_HOSTCMD_X86
-#define CONFIG_SPI
-#define CONFIG_SWITCH
-
-/*
- * Enable configuration after ESPI_RESET# de-asserts
- */
-#undef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT
-
-/*
- * Enable CPRINT in chip eSPI module
- * Define at board level.
- */
-#undef CONFIG_MCHP_ESPI_DEBUG
-
-/*
- * Enable EC UART commands in eSPI module useful for debugging.
- */
-#undef CONFIG_MCHP_ESPI_EC_CMD
-
-/*
- * Enable CPRINT debug messages in LPC module
- */
-#undef CONFIG_MCHP_DEBUG_LPC
-
-/*
- * Define this to use MEC1701 ROM SPI read API
- * in little firmware module instead of SPI code
- * from this module
- */
-#undef CONFIG_CHIP_LFW_USE_ROM_SPI
-
-/*
- * Use DMA when transmitting commands & data
- * with GPSPI controllers.
- */
-#if defined(CHIP_FAMILY_MEC170X) || defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_MCHP_GPSPI_TX_DMA
-#endif
-
-/*
- * Use DMA when transmitting command & data of length
- * greater than QMSPI TX FIFO size.
- */
-#define CONFIG_MCHP_QMSPI_TX_DMA
-
-/*
- * Board level gpio.inc is using MCHP data sheet GPIO pin
- * numbers which are octal.
- * MCHP has 6 banks/ports each containing 32 GPIO's.
- * Each bank/port is connected to a GIRQ.
- * Port numbering:
- * GPIO_015 = 13 decimal. Port = 13/32 = 0, bit = 13 % 32 = 13
- * GPIO_0123 = 83 decimal. Port 83/32 = 2, bit = 83 % 32 = 19
- * OR port = 0123 >> 5, bit = 0123 & 037(0x1F) = 023 = 19 decimal.
- * You must use octal GPIO numbers in PIN(gpio_num) macro in
- * gpio.inc files.
- * Example: GPIO 211 in documentation 0211 = 137 = 0x89
- * GPIO(PCH_SLP_S0_L, PIN(0211), GPIO_INPUT | GPIO_PULL_DOWN)
- * OR
- * GPIO(PCH_SLP_S0_L, PIN(0x89), GPIO_INPUT | GPIO_PULL_DOWN)
- */
-#define GPIO_BANK(index) ((index) >> 5)
-#define GPIO_BANK_MASK(index) (1ul << ((index) & 0x1F))
-
-#define GPIO_PIN(index) GPIO_BANK(index), GPIO_BANK_MASK(index)
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-
-#ifndef __ASSEMBLER__
-
-
-#endif /* #ifndef __ASSEMBLER__ */
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mchp/config_flash_layout.h b/chip/mchp/config_flash_layout.h
deleted file mode 100644
index d423ac0238..0000000000
--- a/chip/mchp/config_flash_layout.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
-#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
-
-/*
- * mec17xx flash layout:
- * - Non memory-mapped, external SPI.
- * - RW image at the beginning of writable region.
- * - Bootloader at the beginning of protected region, followed by RO image.
- * - Loader + (RO | RW) loaded into program memory.
- */
-
-/* Non-memmory mapped, external SPI */
-#define CONFIG_EXTERNAL_STORAGE
-#undef  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
-#define CONFIG_SPI_FLASH
-
-/*
- * MEC170x/MEC152x BootROM uses two 4-byte TAG's at SPI offset 0x0 and 0x04.
- * One valid TAG must be present.
- * TAG's point to a Header which must be located on a 256 byte
- * boundary anywhere in the flash (24-bit addressing).
- * Locate BootROM load Header + LFW + EC_RO at start of second
- * 4KB sector (offset 0x1000).
- * Locate BootROM load Header + EC_RW at start of second half of
- * SPI flash.
- * LFW size is 4KB
- * EC_RO and EC_RW padded sizes from the build are 188KB each.
- * Storage size is 1/2 flash size.
- */
-#define CONFIG_EC_PROTECTED_STORAGE_OFF	0
-/* Lower 256KB of flash is protected region */
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-/* Writable storage for EC_RW starts at 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
-/* Writeable storage is 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-
-
-/* Loader resides at the beginning of program memory */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0x1000
-
-/* Write protect Loader and RO Image */
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-/*
- * Write protect LFW + EC_RO
- */
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * RO / RW images follow the loader in program memory. Either RO or RW
- * image will be loaded -- both cannot be loaded at the same time.
- */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
-/*
- * Total SRAM and the amount allocated for data are specified
- * by CONFIG_MEC_SRAM_SIZE and CONFIG_RAM_SIZE in config_chip.h
- * The little firmware (lfw) loader is resident in first 4KB of Code SRAM.
- * EC_RO/RW size = Total SRAM - Data SRAM - LFW size.
- * !!! EC_RO/RW size MUST be a multiple of flash erase block size.
- * defined by CONFIG_FLASH_ERASE_SIZE in chip/config_chip.h
- * and must be located on a erase block boundary. !!!
- */
-#if (CONFIG_MEC_SRAM_SIZE > CONFIG_EC_PROTECTED_STORAGE_SIZE)
-#define CONFIG_RO_SIZE			(CONFIG_EC_PROTECTED_STORAGE_SIZE - \
-					CONFIG_LOADER_SIZE - 0x2000)
-#else
-#define CONFIG_RO_SIZE			(CONFIG_MEC_SRAM_SIZE - \
-					CONFIG_RAM_SIZE - CONFIG_LOADER_SIZE)
-#endif
-
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
-/*
- * NOTE: CONFIG_RW_SIZE is passed to the SPI image generation script by
- * chip build.mk
- * LFW requires CONFIG_RW_SIZE is equal to CONFIG_RO_SIZE !!!
- */
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-
-/*
- * WP region consists of first half of SPI containing TAGs at beginning
- * of SPI flash and header + binary(LFW+EC_RO) an offset aligned on
- * a 256 byte boundary.
- * NOTE: Changing CONFIG_BOOT_HEADER_STORAGE_OFF requires changing
- * parameter --payload_offset parameter in build.mk passed to the
- * python image builder.
- * Two 4-byte TAG's exist at offset 0 and 4 in the SPI flash device.
- * We only use first TAG pointing to LFW + EC_RO.
- * MEC170x Header size is 128 bytes.
- * MEC152x Header size is 320 bytes.
- * Firmware binary is located immediately after the header.
- * Second half of SPI flash contains:
- * Header(128/320 bytes) + EC_RW
- * EC flash erase/write commands check alignment base on
- * CONFIG_FLASH_ERASE_SIZE defined in config_chip.h
- * NOTE: EC_RO and EC_RW must start at CONFIG_FLASH_ERASE_SIZE or
- * greater aligned boundaries.
- */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF		0x1000
-#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF	0
-#if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE		0xc0
-#elif defined(CHIP_FAMILY_MEC152X)
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE		0x140
-#elif defined(CHIP_FAMILY_MEC170X)
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE		0x80
-#else
-#error "FORCED BUILD ERROR: CHIP_FAMILY_xxxx not set or invalid"
-#endif
-#define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE	0
-
-/* Loader / lfw image immediately follows the boot header on SPI */
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
-
-/* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
-
-/*
- * RW image starts at offset 0 of second half of SPI.
- * RW Header not needed.
- */
-#define CONFIG_RW_STORAGE_OFF		(CONFIG_RW_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_RW_BOOT_HEADER_STORAGE_SIZE)
-
-
-#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/mchp/dma.c b/chip/mchp/dma.c
deleted file mode 100644
index 982dfa8122..0000000000
--- a/chip/mchp/dma.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
-
-dma_chan_t *dma_get_channel(enum dma_channel channel)
-{
-	dma_chan_t *pd = NULL;
-
-	if (channel < MCHP_DMAC_COUNT) {
-		pd = (dma_chan_t *)(MCHP_DMA_BASE + MCHP_DMA_CH_OFS +
-				(channel << MCHP_DMA_CH_OFS_BITPOS));
-	}
-
-	return pd;
-}
-
-void dma_disable(enum dma_channel channel)
-{
-	if (channel < MCHP_DMAC_COUNT) {
-		if (MCHP_DMA_CH_CTRL(channel) & MCHP_DMA_RUN)
-			MCHP_DMA_CH_CTRL(channel) &= ~(MCHP_DMA_RUN);
-
-		if (MCHP_DMA_CH_ACT(channel)	& MCHP_DMA_ACT_EN)
-			MCHP_DMA_CH_ACT(channel) = 0;
-	}
-}
-
-void dma_disable_all(void)
-{
-	uint16_t ch;
-	uint32_t unused = 0;
-
-	for (ch = 0; ch < MCHP_DMAC_COUNT; ch++) {
-		/* Abort any current transfer. */
-		MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_ABORT;
-		/* Disable the channel. */
-		MCHP_DMA_CH_CTRL(ch) &= ~(MCHP_DMA_RUN);
-		MCHP_DMA_CH_ACT(ch) = 0;
-	}
-
-	/* Soft-reset the block. */
-	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_SRST;
-	unused += MCHP_DMA_MAIN_CTRL;
-	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_ACT;
-}
-
-/**
- * Prepare a channel for use and start it
- *
- * @param chan	Channel to read
- * @param count	Number of bytes to transfer
- * @param periph Pointer to peripheral data register
- * @param memory Pointer to memory address for receive/transmit
- * @param flags	DMA flags for the control register, normally:
- *		MCHP_DMA_INC_MEM | MCHP_DMA_TO_DEV for tx
- *		MCHP_DMA_INC_MEM for rx
- *		Plus transfer unit length(1, 2, or 4) in bits[22:20]
- * @note MCHP DMA does not require address aliasing. Because count
- * is the number of bytes to transfer memory start - memory end = count.
- */
-static void prepare_channel(enum dma_channel ch, unsigned int count,
-		void *periph, void *memory, unsigned int flags)
-{
-	if (ch < MCHP_DMAC_COUNT) {
-
-		MCHP_DMA_CH_CTRL(ch) = 0;
-		MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory;
-		MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + count;
-
-		MCHP_DMA_CH_DEV_ADDR(ch) = (uint32_t)periph;
-
-		MCHP_DMA_CH_CTRL(ch) = flags;
-		MCHP_DMA_CH_ACT(ch) = MCHP_DMA_ACT_EN;
-	}
-}
-
-void dma_go(dma_chan_t *chan)
-{
-	/* Flush data in write buffer so that DMA can get the
-	 *  latest data.
-	 */
-	asm volatile("dsb;");
-
-	if (chan != NULL)
-		chan->ctrl |= MCHP_DMA_RUN;
-}
-
-void dma_go_chan(enum dma_channel ch)
-{
-	asm volatile("dsb;");
-	if (ch < MCHP_DMAC_COUNT)
-		MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_RUN;
-}
-
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
-		    const void *memory)
-{
-	if (option != NULL)
-		/*
-		 * Cast away const for memory pointer; this is ok because
-		 * we know we're preparing the channel for transmit.
-		 */
-		prepare_channel(option->channel, count, option->periph,
-			(void *)memory,
-			MCHP_DMA_INC_MEM |
-			MCHP_DMA_TO_DEV |
-			MCHP_DMA_DEV(option->channel) |
-			option->flags);
-}
-
-void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
-		const void *memory, uint32_t dma_xfr_units)
-{
-	uint32_t nflags;
-
-	if (option != NULL) {
-		nflags = option->flags & ~(MCHP_DMA_XFER_SIZE_MASK);
-		nflags |= MCHP_DMA_XFER_SIZE(dma_xfr_units & 0x07);
-		/*
-		 * Cast away const for memory pointer; this is ok because
-		 * we know we're preparing the channel for transmit.
-		 */
-		prepare_channel(option->channel, count, option->periph,
-			(void *)memory,
-			MCHP_DMA_INC_MEM |
-			MCHP_DMA_TO_DEV |
-			MCHP_DMA_DEV(option->channel) |
-			nflags);
-	}
-}
-
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
-{
-	if (option != NULL) {
-		prepare_channel(option->channel, count, option->periph,
-				memory,
-				MCHP_DMA_INC_MEM |
-				MCHP_DMA_DEV(option->channel) |
-				option->flags);
-		dma_go_chan(option->channel);
-	}
-}
-
-/*
- * Configure and start DMA channel for read from device and write to
- * memory. Allow caller to override DMA transfer unit length.
- */
-void dma_xfr_start_rx(const struct dma_option *option,
-		uint32_t dma_xfr_ulen,
-		uint32_t count, void *memory)
-{
-	uint32_t ch, ctrl;
-
-	if (option != NULL) {
-		ch = option->channel;
-		if (ch < MCHP_DMAC_COUNT) {
-
-			MCHP_DMA_CH_CTRL(ch) = 0;
-			MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory;
-			MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory +
-					count;
-
-			MCHP_DMA_CH_DEV_ADDR(ch) =
-					(uint32_t)option->periph;
-
-			ctrl = option->flags &
-					~(MCHP_DMA_XFER_SIZE_MASK);
-			ctrl |= MCHP_DMA_INC_MEM;
-			ctrl |= MCHP_DMA_XFER_SIZE(dma_xfr_ulen);
-			ctrl |= MCHP_DMA_DEV(option->channel);
-			MCHP_DMA_CH_CTRL(ch) = ctrl;
-			MCHP_DMA_CH_ACT(ch) = MCHP_DMA_ACT_EN;
-		}
-
-		dma_go_chan(option->channel);
-	}
-}
-
-/*
- * Return the number of bytes transferred.
- * The number of bytes transferred can be easily determined
- * from the difference in DMA memory start address register
- * and memory end address register. No need to look at DMA
- * transfer size field because the hardware increments memory
- * start address by unit size on each unit transferred.
- * Why is a signed integer being used for a count value?
- */
-int dma_bytes_done(dma_chan_t *chan, int orig_count)
-{
-	int bcnt;
-
-	if (chan == NULL)
-		return 0;
-
-	bcnt = (int)chan->mem_end;
-	bcnt -= (int)chan->mem_start;
-	bcnt = orig_count - bcnt;
-
-	return bcnt;
-}
-
-bool dma_is_enabled(dma_chan_t *chan)
-{
-	return (chan->ctrl & MCHP_DMA_RUN);
-}
-
-int dma_bytes_done_chan(enum dma_channel ch, uint32_t orig_count)
-{
-	uint32_t cnt;
-
-	cnt = 0;
-	if (ch < MCHP_DMAC_COUNT)
-		if (MCHP_DMA_CH_CTRL(ch) & MCHP_DMA_RUN)
-			cnt = (uint32_t)orig_count -
-					(MCHP_DMA_CH_MEM_END(ch) -
-					 MCHP_DMA_CH_MEM_START(ch));
-
-	return (int)cnt;
-}
-
-/*
- * Initialize DMA block.
- * Clear PCR DMA sleep enable.
- * Soft-Reset block should clear after one clock but read-back to
- * be safe.
- * Set block activate bit after reset.
- */
-void dma_init(void)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_DMA);
-	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_SRST;
-	MCHP_DMA_MAIN_CTRL;
-	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_ACT;
-}
-
-int dma_wait(enum dma_channel channel)
-{
-	timestamp_t deadline;
-
-	if (channel < MCHP_DMAC_COUNT) {
-		if (MCHP_DMA_CH_ACT(channel) == 0)
-			return EC_SUCCESS;
-
-		deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
-
-		while (!(MCHP_DMA_CH_ISTS(channel) &
-			 MCHP_DMA_STS_DONE)) {
-
-			if (deadline.val <= get_time().val)
-				return EC_ERROR_TIMEOUT;
-
-			udelay(DMA_POLLING_INTERVAL_US);
-		}
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-/*
- * Clear all interrupt status in specified DMA channel
- */
-void dma_clear_isr(enum dma_channel channel)
-{
-	if (channel < MCHP_DMAC_COUNT)
-		MCHP_DMA_CH_ISTS(channel) = 0x0f;
-}
-
-void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
-			uint32_t nb, const void *pdev)
-{
-	if (ch < MCHP_DMAC_COUNT) {
-		MCHP_DMA_CH_MEM_START(ch) = (uint32_t)membuf;
-		MCHP_DMA_CH_MEM_END(ch) = (uint32_t)membuf + nb;
-		MCHP_DMA_CH_DEV_ADDR(ch) = (uint32_t)pdev;
-	}
-}
-
-/*
- * ch = zero based DMA channel number
- * unit_len = DMA unit size 1, 2 or 4 bytes
- * flags
- *   b[0] = direction, 0=device_to_memory, 1=memory_to_device
- *   b[1] = 1 increment memory address
- *   b[2] = 1 increment device address
- *   b[3] = disable HW flow control
- */
-void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len,
-			uint8_t dev_id, uint8_t flags)
-{
-	uint32_t ctrl;
-
-	if (ch < MCHP_DMAC_COUNT) {
-		ctrl = MCHP_DMA_XFER_SIZE(unit_len & 0x07);
-		ctrl += MCHP_DMA_DEV(dev_id & MCHP_DMA_DEV_MASK0);
-		if (flags & 0x01)
-			ctrl |= MCHP_DMA_TO_DEV;
-		if (flags & 0x02)
-			ctrl |= MCHP_DMA_INC_MEM;
-		if (flags & 0x04)
-			ctrl |= MCHP_DMA_INC_DEV;
-		if (flags & 0x08)
-			ctrl |= MCHP_DMA_DIS_HW_FLOW;
-		MCHP_DMA_CH_CTRL(ch) = ctrl;
-	}
-}
-
-void dma_clr_chan(enum dma_channel ch)
-{
-	if (ch < MCHP_DMAC_COUNT) {
-		MCHP_DMA_CH_ACT(ch) = 0;
-		MCHP_DMA_CH_CTRL(ch) = 0;
-		MCHP_DMA_CH_IEN(ch) = 0;
-		MCHP_DMA_CH_ISTS(ch) = 0xff;
-		MCHP_DMA_CH_FSM_RO(ch) = MCHP_DMA_CH_ISTS(ch);
-		MCHP_DMA_CH_ACT(ch) = 1;
-	}
-}
-
-void dma_run(enum dma_channel ch)
-{
-	if (ch < MCHP_DMAC_COUNT) {
-		if (MCHP_DMA_CH_CTRL(ch) & MCHP_DMA_DIS_HW_FLOW)
-			MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_SW_GO;
-		else
-			MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_RUN;
-	}
-}
-
-/*
- * Check if DMA channel is done or stopped on error
- * Returns 0 not done or stopped on error
- * Returns non-zero if done or stopped.
- * Caller should check bit pattern for specific bit,
- * done, flow control error, and bus error.
- */
-uint32_t dma_is_done_chan(enum dma_channel ch)
-{
-	if (ch < MCHP_DMAC_COUNT)
-		return (uint32_t)(MCHP_DMA_CH_ISTS(ch) & 0x07);
-
-	return 0;
-}
-
-/*
- * Use DMA Channel 0 CRC32 ALU to compute CRC32 of data.
- * Hardware implements IEEE 802.3 CRC32.
- * IEEE 802.3 CRC32 initial value = 0xffffffff.
- * Data must be aligned >= 4-bytes and number of bytes must
- * be a multiple of 4.
- */
-int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien)
-{
-	if ((mstart == NULL) || (nbytes == 0))
-		return EC_ERROR_INVAL;
-
-	if ((((uint32_t)mstart | nbytes) & 0x03) != 0)
-		return EC_ERROR_INVAL;
-
-	MCHP_DMA_CH_ACT(0) = 0;
-	MCHP_DMA_CH_CTRL(0) = 0;
-	MCHP_DMA_CH_IEN(0) = 0;
-	MCHP_DMA_CH_ISTS(0) = 0xff;
-	MCHP_DMA_CH0_CRC32_EN = 1;
-	MCHP_DMA_CH0_CRC32_DATA	= 0xfffffffful;
-	/* program device address to point to read-only register */
-	MCHP_DMA_CH_DEV_ADDR(0) = (uint32_t)(MCHP_DMA_CH_BASE + 0x1c);
-	MCHP_DMA_CH_MEM_START(0) = (uint32_t)mstart;
-	MCHP_DMA_CH_MEM_END(0) = (uint32_t)mstart + nbytes;
-	if (ien != 0)
-		MCHP_DMA_CH_IEN(0) = 0x07;
-	MCHP_DMA_CH_ACT(0) = 1;
-	MCHP_DMA_CH_CTRL(0) = MCHP_DMA_TO_DEV + MCHP_DMA_INC_MEM +
-		MCHP_DMA_DIS_HW_FLOW + MCHP_DMA_XFER_SIZE(4);
-	MCHP_DMA_CH_CTRL(0) |= MCHP_DMA_SW_GO;
-	return EC_SUCCESS;
-}
diff --git a/chip/mchp/dma_chip.h b/chip/mchp/dma_chip.h
deleted file mode 100644
index 4784b2c922..0000000000
--- a/chip/mchp/dma_chip.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC DMA controller chip level API
- */
-/** @file dma_chip.h
- *MCHP MEC Direct Memory Access block
- */
-/** @defgroup MEC dma
- */
-
-#ifndef _DMA_CHIP_H
-#define _DMA_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Place any C interfaces here */
-
-void dma_xfr_start_rx(const struct dma_option *option,
-		uint32_t dma_xfr_ulen,
-		uint32_t count, void *memory);
-
-void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
-		const void *memory, uint32_t dma_xfr_units);
-
-void dma_clr_chan(enum dma_channel ch);
-
-void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
-			uint32_t nb, const void *pdev);
-
-/*
- * ch = zero based DMA channel number
- * unit_len = DMA unit size 1, 2 or 4 bytes
- * flags
- *   b[0] = direction, 0=device_to_memory, 1=memory_to_device
- *   b[1] = 1 increment memory address
- *   b[2] = 1 increment device address
- *   b[3] = disable HW flow control
- */
-#define DMA_FLAG_D2M		0
-#define DMA_FLAG_M2D		1
-#define DMA_FLAG_INCR_MEM	2
-#define DMA_FLAG_INCR_DEV	4
-#define DMA_FLAG_SW_FLOW	8
-void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len,
-			uint8_t dev_id, uint8_t flags);
-
-void dma_run(enum dma_channel ch);
-
-uint32_t dma_is_done_chan(enum dma_channel ch);
-
-int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef _DMA_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c
deleted file mode 100644
index 8a38a82688..0000000000
--- a/chip/mchp/espi.c
+++ /dev/null
@@ -1,1505 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ESPI module for Chrome EC */
-
-#include "common.h"
-#include "acpi.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "port80.h"
-#include "util.h"
-#include "chipset.h"
-
-#include "registers.h"
-#include "espi.h"
-#include "lpc.h"
-#include "lpc_chip.h"
-#include "system.h"
-#include "task.h"
-#include "console.h"
-#include "uart.h"
-#include "util.h"
-#include "power.h"
-#include "timer.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-#ifdef CONFIG_MCHP_TFDP
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#endif
-#else
-#define CPUTS(...)
-#define CPRINTS(...)
-#endif
-
-/* Default config to use maximum frequency */
-#ifndef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
-#if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ		MCHP_ESPI_CAP1_MAX_FREQ_66M
-#else
-#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ		MCHP_ESPI_CAP1_MAX_FREQ_50M
-#endif
-#endif
-
-/* Default config to support all modes */
-#ifndef CONFIG_HOSTCMD_ESPI_EC_MODE
-#define CONFIG_HOSTCMD_ESPI_EC_MODE		MCHP_ESPI_CAP1_ALL_MODE
-#endif
-
-/* Default config to support all channels */
-#ifndef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP
-#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP	MCHP_ESPI_CAP0_ALL_CHAN_SUPP
-#endif
-/*
- * eSPI slave to master virtual wire pulse timeout.
- */
-#define ESPI_S2M_VW_PULSE_LOOP_CNT		50
-#define ESPI_S2M_VW_PULSE_LOOP_DLY_US		10
-
-/*
- * eSPI master enable virtual wire channel timeout.
- */
-#define ESPI_CHAN_READY_TIMEOUT_US (100 * MSEC)
-#define ESPI_CHAN_READY_POLL_INTERVAL_US 100
-
-static uint32_t espi_channels_ready;
-
-/*
- * eSPI Virtual Wire reset values
- * VWire name used by chip independent code.
- * Host eSPI Master VWire index containing signal
- * Reset value of VWire. Note, each Host VWire index may
- * have a different reset source:
- *	EC Power-on/chip reset
- *	ESPI_RESET# assertion by Host eSPI master
- *	eSPI Platform Reset assertion by Host eSPI master
- *		MEC1701H allows eSPI Platform reset to
- *		be a VWire or side band signal.
- *
- * NOTE MEC1701H Boot-ROM will restore VWires ... from
- * VBAT power register MCHP_VBAT_VWIRE_BACKUP.
- *	bits[3:0] = Master-to-Slave Index 02h SRC3:SRC0 values
- *		MSVW00 register
- *			SRC0 = SLP_S3#
- *			SRC1 = SLP_S4#
- *			SRC2 = SLP_S5#
- *			SRC3 = reserved
- *	bits[7:4] = Master-to-Slave Index 42h SRC3:SRC0 values
- *		MSVW04 register
- *			SRC0 = SLP_LAN#
- *			SRC1 = SLP_WLAN#
- *			SRC2 = reserved
- *			SRC3 = reserved
- *
- */
-struct vw_info_t {
-	uint16_t name;		/* signal name */
-	uint8_t  host_idx;	/* Host VWire index of signal */
-	uint8_t  reset_val;	/* reset value of VWire */
-	uint8_t  flags;		/* b[0]=0(MSVW), =1(SMVW) */
-	uint8_t  reg_idx;	/* MSVW or SMVW index */
-	uint8_t  src_num;	/* SRC number */
-	uint8_t  rsvd;
-};
-
-
-/* VW signals used in eSPI */
-/*
- * MEC1701H VWire mapping based on eSPI Spec 1.0,
- * eSPI Compatibility spec 0.96,
- * MCHP HW defaults and ec/include/espi.h
- *
- * MSVW00 index=02h PORValue=00000000_04040404_00000102 reset=RESET_SYS
- *	SRC0 = VW_SLP_S3_L, IntrDis
- *	SRC1 = VW_SLP_S4_L, IntrDis
- *	SRC2 = VW_SLP_S5_L, IntrDis
- *	SRC3 = reserved, IntrDis
- * MSVW01 index=03h PORValue=00000000_04040404_00000003 reset=RESET_ESPI
- *	SRC0 = VW_SUS_STAT_L, IntrDis
- *	SRC1 = VW_PLTRST_L, IntrDis
- *	SRC2 = VW_OOB_RST_WARN, IntrDis
- *	SRC3 = reserved, IntrDis
- * MSVW02 index=07h PORValue=00000000_04040404_00000307 reset=PLTRST
- *	SRC0 = VW_HOST_RST_WARN
- *	SRC1 = 0 reserved
- *	SRC2 = 0 reserved
- *	SRC3 = 0 reserved
- * MSVW03 index=41h PORValue=00000000_04040404_00000041 reset=RESET_ESPI
- *	SRC0 = VW_SUS_WARN_L, IntrDis
- *	SRC1 = VW_SUS_PWRDN_ACK_L, IntrDis
- *	SRC2 = 0 reserved, IntrDis
- *	SRC3 = VW_SLP_A_L, IntrDis
- * MSVW04 index=42h PORValue=00000000_04040404_00000141 reset=RESET_SYS
- *	SRC0 = VW_SLP_LAN, IntrDis
- *	SRC1 = VW_SLP_WLAN, IntrDis
- *	SRC2 = reserved, IntrDis
- *	SRC3 = reserved, IntrDis
- *
- * SMVW00 index=04h PORValue=01010000_0000C004 STOM=1100 reset=RESET_ESPI
- *	SRC0 = VW_OOB_RST_ACK
- *	SRC1 = 0 reserved
- *	SRC2 = VW_WAKE_L
- *	SRC3 = VW_PME_L
- * SMVW01 index=05h PORValue=00000000_00000005 STOM=0000 reset=RESET_ESPI
- *	SRC0 = SLAVE_BOOT_LOAD_DONE   !!! NOTE: Google combines SRC0 & SRC3
- *	SRC1 = VW_ERROR_FATAL
- *	SRC2 = VW_ERROR_NON_FATAL
- *	SRC3 = SLAVE_BOOT_LOAD_STATUS !!! into VW_PERIPHERAL_BTLD_STATUS_DONE
- * SMVW02 index=06h PORValue=00010101_00007306 STOM=0111 reset=PLTRST
- *	SRC0 = VW_SCI_L
- *	SRC1 = VW_SMI_L
- *	SRC2 = VW_RCIN_L
- *	SRC3 = VW_HOST_RST_ACK
- * SMVW03 index=40h PORValue=00000000_00000040 STOM=0000 reset=RESET_ESPI
- *	SRC0 = assign VW_SUS_ACK
- *	SRC1 = 0
- *	SRC2 = 0
- *	SRC3 = 0
- *
- * table of vwire structures
- * MSVW00 at 0x400F9C00 offset = 0x000
- * MSVW01 at 0x400F9C0C offset = 0x00C
- *
- * SMVW00 at 0x400F9E00 offset = 0x200
- * SMVW01 at 0x400F9E08 offset = 0x208
- *
- */
-
-/*
- * Virtual Wire table
- * Each entry contains:
- *	Signal name from include/espi.h
- *	Host chipset VWire index number
- *      Reset value of VWire
- *      flags where bit[0]==0 Wire is Master-to-Slave or 1 Slave-to-Master
- *	MEC1701 register index into MSVW or SMVW register banks
- *	MEC1701 source number in MSVW or SMVW bank
- *      Reserved
- *	Pointer to name string for debug
- */
-static const struct vw_info_t vw_info_tbl[] = {
-	/* name				host  reset       reg   SRC
-	 *				index value flags index num   rsvd
-	 */
-	/* MSVW00 Host index 02h (In) */
-	{VW_SLP_S3_L,			 0x02, 0x00, 0x00, 0x00, 0x00, 0x00},
-	{VW_SLP_S4_L,			 0x02, 0x00, 0x00, 0x00, 0x01, 0x00},
-	{VW_SLP_S5_L,			 0x02, 0x00, 0x10, 0x00, 0x02, 0x00},
-	/* MSVW01 Host index 03h (In) */
-	{VW_SUS_STAT_L,			 0x03, 0x00, 0x10, 0x01, 0x00, 0x00},
-	{VW_PLTRST_L,			 0x03, 0x00, 0x10, 0x01, 0x01, 0x00},
-	{VW_OOB_RST_WARN,		 0x03, 0x00, 0x10, 0x01, 0x02, 0x00},
-	/* SMVW00 Host Index 04h (Out) */
-	{VW_OOB_RST_ACK,		 0x04, 0x00, 0x01, 0x00, 0x00, 0x00},
-	{VW_WAKE_L,			 0x04, 0x01, 0x01, 0x00, 0x02, 0x00},
-	{VW_PME_L,			 0x04, 0x01, 0x01, 0x00, 0x03, 0x00},
-	/* SMVW01 Host index 05h (Out) */
-	{VW_ERROR_FATAL,		 0x05, 0x00, 0x01, 0x01, 0x01, 0x00},
-	{VW_ERROR_NON_FATAL,		 0x05, 0x00, 0x01, 0x01, 0x02, 0x00},
-	{VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x00, 0x01, 0x01, 0x30, 0x00},
-	/* SMVW02 Host index 06h (Out) */
-	{VW_SCI_L,			 0x06, 0x01, 0x01, 0x02, 0x00, 0x00},
-	{VW_SMI_L,			 0x06, 0x01, 0x01, 0x02, 0x01, 0x00},
-	{VW_RCIN_L,			 0x06, 0x01, 0x01, 0x02, 0x02, 0x00},
-	{VW_HOST_RST_ACK,		 0x06, 0x00, 0x01, 0x02, 0x03, 0x00},
-	/* MSVW02 Host index 07h (In) */
-	{VW_HOST_RST_WARN,		 0x07, 0x00, 0x10, 0x02, 0x00, 0x00},
-	/* SMVW03 Host Index 40h (Out) */
-	{VW_SUS_ACK,			 0x40, 0x00, 0x01, 0x03, 0x00, 0x00},
-	/* MSVW03 Host Index 41h (In) */
-	{VW_SUS_WARN_L,			 0x41, 0x00, 0x10, 0x03, 0x00, 0x00},
-	{VW_SUS_PWRDN_ACK_L,		 0x41, 0x00, 0x10, 0x03, 0x01, 0x00},
-	{VW_SLP_A_L,			 0x41, 0x00, 0x10, 0x03, 0x03, 0x00},
-	/* MSVW04 Host index 42h (In) */
-	{VW_SLP_LAN,			 0x42, 0x00, 0x10, 0x04, 0x00, 0x00},
-	{VW_SLP_WLAN,			 0x42, 0x00, 0x10, 0x04, 0x01, 0x00}
-};
-BUILD_ASSERT(ARRAY_SIZE(vw_info_tbl) == VW_SIGNAL_COUNT);
-
-
-/************************************************************************/
-/* eSPI internal utilities */
-
-static int espi_vw_get_signal_index(enum espi_vw_signal event)
-{
-	int i;
-
-	/* Search table by signal name */
-	for (i = 0; i < ARRAY_SIZE(vw_info_tbl); i++) {
-		if (vw_info_tbl[i].name == event)
-			return i;
-	}
-
-	return -1;
-}
-
-
-/*
- * Initialize eSPI hardware upon ESPI_RESET# de-assertion
- */
-#ifdef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT
-static void espi_reset_deassert_init(void)
-{
-
-}
-#endif
-
-/* Call this on entry to deepest sleep state with EC turned off.
- * May not be required in future host eSPI chipsets.
- *
- * Save Master-to-Slave VWire Index 02h & 42h before
- * entering a deep sleep state where EC power is shut off.
- * PCH requires we restore these VWires on wake.
- * SLP_S3#, SLP_S4#, SLP_S5# in index 02h
- * SLP_LAN#, SLP_WLAN# in index 42h
- * Current VWire states are saved to a battery backed 8-bit
- * register in MEC1701H.
- * If a VBAT POR occurs the value of this register = 0 which
- * is the default state of the above VWires on a hardware
- * POR.
- * VBAT byte bit definitions
- * Host Index 02h -> MSVW00
- * Host Index 42h -> MSVW04
- * 0 Host Index 02h SRC0
- * 1 Host Index 02h SRC1
- * 2 Host Index 02h SRC2
- * 3 Host Index 02h SRC3
- * 4 Host Index 42h SRC0
- * 5 Host Index 42h SRC1
- * 6 Host Index 42h SRC2
- * 7 Host Index 42h SRC3
- */
-#ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
-static void espi_vw_save(void)
-{
-	uint32_t i, r;
-	uint8_t vb;
-
-	vb = 0;
-	r = MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H42);
-	for (i = 0; i < 4; i++) {
-		if (r & (1ul << (i << 3)))
-			vb |= (1u << i);
-	}
-
-	vb <<= 4;
-	r = MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H02);
-	for (i = 0; i < 4; i++) {
-		if (r & (1ul << (i << 3)))
-			vb |= (1u << i);
-	}
-
-	r = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP);
-	r = (r & 0xFFFFFF00) | vb;
-	MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) = r;
-}
-
-/*
- * Update MEC1701H VBAT powered VWire backup values restored on
- * MCHP chip reset. MCHP Boot-ROM loads these values into
- * MSVW00 SRC[0:3](Index 02h) and MSVW04 SRC[0:3](Index 42h)
- * on chip reset(POR, WDT reset, chip reset, wake from EC off).
- * Always clear backup value after restore.
- */
-static void espi_vw_restore(void)
-{
-	uint32_t i, r;
-	uint8_t vb;
-
-#ifdef EVB_NO_ESPI_TEST_MODE
-	vb = 0xff; /* force SLP_Sx# signals to 1 */
-#else
-	vb = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) & 0xff;
-#endif
-	r = 0;
-	for (i = 0; i < 4; i++) {
-		if (vb & (1u << i))
-			r |= (1ul << (i << 3));
-	}
-	MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H02) = r;
-	CPRINTS("eSPI restore MSVW00(Index 02h) = 0x%08x", r);
-
-	vb >>= 4;
-	r = 0;
-	for (i = 0; i < 4; i++) {
-		if (vb & (1u << i))
-			r |= (1ul << (i << 3));
-	}
-	MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H42) = r;
-	CPRINTS("eSPI restore MSVW00(Index 42h) = 0x%08x", r);
-
-	r = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP);
-	MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) = r & 0xFFFFFF00;
-
-}
-#endif
-
-static uint8_t __attribute__((unused)) espi_msvw_srcs_get(uint8_t msvw_id)
-{
-	uint8_t msvw;
-
-	msvw = 0;
-	if (msvw_id < MSVW_MAX) {
-		uint32_t r = MCHP_ESPI_VW_M2S_SRC_ALL(msvw_id);
-
-		msvw = (r & 0x01);
-		msvw |= ((r >> 7) & 0x02);
-		msvw |= ((r >> 14) & 0x04);
-		msvw |= ((r >> 21) & 0x08);
-	}
-
-	return msvw;
-}
-
-static void __attribute__((unused)) espi_msvw_srcs_set(uint8_t msvw_id,
-						       uint8_t src_bitmap)
-{
-	if (msvw_id < MSVW_MAX) {
-		uint32_t r = (src_bitmap & 0x08) << 21;
-
-		r |= (src_bitmap & 0x04) << 14;
-		r |= (src_bitmap & 0x02) << 7;
-		r |= (src_bitmap & 0x01);
-		MCHP_ESPI_VW_M2S_SRC_ALL(msvw_id) = r;
-	}
-}
-
-static uint8_t __attribute__((unused)) espi_smvw_srcs_get(uint8_t smvw_id)
-{
-	uint8_t smvw;
-
-	smvw = 0;
-	if (smvw_id < SMVW_MAX) {
-		uint32_t r = MCHP_ESPI_VW_S2M_SRC_ALL(smvw_id);
-
-		smvw = (r & 0x01);
-		smvw |= ((r >> 7) & 0x02);
-		smvw |= ((r >> 14) & 0x04);
-		smvw |= ((r >> 21) & 0x08);
-	}
-
-	return smvw;
-}
-
-static void __attribute__((unused)) espi_smvw_srcs_set(uint8_t smvw_id,
-						       uint8_t src_bitmap)
-{
-	if (smvw_id < SMVW_MAX) {
-		uint32_t r = (src_bitmap & 0x08) << 21;
-
-		r |= (src_bitmap & 0x04) << 14;
-		r |= (src_bitmap & 0x02) << 7;
-		r |= (src_bitmap & 0x01);
-		MCHP_ESPI_VW_S2M_SRC_ALL(smvw_id) = r;
-	}
-}
-
-
-/*
- * Called before releasing RSMRST#
- *	ESPI_RESET# is asserted
- *	PLATFORM_RESET# is asserted
- */
-static void espi_bar_pre_init(void)
-{
-	/* Configuration IO BAR set to 0x2E/0x2F */
-	MCHP_ESPI_IO_BAR_ADDR_LSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x2E;
-	MCHP_ESPI_IO_BAR_ADDR_MSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x00;
-	MCHP_ESPI_IO_BAR_VALID(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 1;
-}
-
-/*
- * Called before releasing RSMRST#
- *	ESPI_RESET# is asserted
- *	PLATFORM_RESET# is asserted
- * Set all MSVW to either edge interrupt
- *	IRQ_SELECT fields are reset on RESET_SYS not ESPI_RESET or PLTRST
- *
- */
-static void espi_vw_pre_init(void)
-{
-	uint32_t i;
-
-	CPRINTS("eSPI VW Pre-Init");
-
-#ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
-	espi_vw_restore();
-#endif
-
-	/* disable all */
-	for (i = 0; i < MSVW_MAX; i++)
-		MCHP_ESPI_VW_M2S_IRQSEL_ALL(i) = 0x0f0f0f0ful;
-
-	/* clear spurious status */
-	MCHP_INT_SOURCE(24) = 0xfffffffful;
-	MCHP_INT_SOURCE(25) = 0xfffffffful;
-
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H02) = 0x040f0f0ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H03) = 0x040f0f0ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H07) = 0x0404040ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H41) = 0x0f040f0ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H42) = 0x04040f0ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H47) = 0x0404040ful;
-
-	MCHP_INT_ENABLE(24) = 0xfff3b177ul;
-	MCHP_INT_ENABLE(25) = 0x01ul;
-
-	MCHP_INT_SOURCE(24) = 0xfffffffful;
-	MCHP_INT_SOURCE(25) = 0xfffffffful;
-
-	MCHP_INT_BLK_EN = (1ul << 24) + (1ul << 25);
-
-	task_enable_irq(MCHP_IRQ_GIRQ24);
-	task_enable_irq(MCHP_IRQ_GIRQ25);
-
-	CPRINTS("eSPI VW Pre-Init Done");
-}
-
-
-/*
- * If VWire, Flash, and OOB channels have been enabled
- * then set VWires SLAVE_BOOT_LOAD_STATUS = SLAVE_BOOT_LOAD_DONE = 1
- * SLAVE_BOOT_LOAD_STATUS = SRC3 of Slave-to-Master Index 05h
- * SLAVE_BOOT_LOAD_DONE = SRC0 of Slave-to-Master Index 05h
- * Note, if set individually then set status first then done.
- * We set both simultaneously. ESPI_ALERT# will assert only if one
- * or both bits change.
- * SRC0 is bit[32] of SMVW01
- * SRC3 is bit[56] of SMVW01
- */
-static void espi_send_boot_load_done(void)
-{
-	/* First set SLAVE_BOOT_LOAD_STATUS = 1 */
-	MCHP_ESPI_VW_S2M_SRC3(SMVW_H05) = 1;
-	/* Next set SLAVE_BOOT_LOAD_DONE = 1 */
-	MCHP_ESPI_VW_S2M_SRC0(SMVW_H05) = 1;
-
-	CPRINTS("eSPI Send SLAVE_BOOT_LOAD_STATUS/DONE = 1");
-}
-
-
-/*
- * Called when eSPI PLTRST# VWire de-asserts
- * Re-initialize any hardware that was reset while PLTRST# was
- * asserted.
- * Logical Device BAR's, etc.
- *   Each BAR requires address, mask, and valid bit
- *     mask = bit map of address[7:0] to mask out
- *	0 = no masking, match exact address
- *	0x01 = mask bit[0], match two consecutive addresses
- *	0xff = mask bits[7:0], match 256 consecutive bytes
- *     eSPI has two registers for each BAR
- *       Host visible register
- *		base address in bits[31:16]
- *		valid = bit[0]
- *       EC only register
- *		mask = bits[7:0]
- *		Logical device number = bits[13:8]
- *		Virtualized = bit[16] Not Implemented
- */
-static void espi_host_init(void)
-{
-	CPRINTS("eSPI - espi_host_init");
-
-	/* BAR's */
-
-	/* Configuration IO BAR set to 0x2E/0x2F */
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x01;
-	MCHP_ESPI_IO_BAR_ADDR_LSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x2E;
-	MCHP_ESPI_IO_BAR_ADDR_MSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x00;
-	MCHP_ESPI_IO_BAR_VALID(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 1;
-
-	/* Set up ACPI0 for 0x62/0x66 */
-	chip_acpi_ec_config(0, 0x62, 0x04);
-
-	/* Set up ACPI1 for 0x200-0x203, 0x204-0x207 */
-	chip_acpi_ec_config(1, 0x200, 0x07);
-
-	/* Set up 8042 interface at 0x60/0x64 */
-	chip_8042_config(0x60);
-
-	/* EMI at 0x800 for accessing shared memory */
-	chip_emi0_config(0x800);
-
-	/* Setup Port80 Debug Hardware for I/O 80h */
-	chip_port80_config(0x80);
-
-	lpc_mem_mapped_init();
-
-	MCHP_ESPI_PC_STATUS = 0xfffffffful;
-	/* PC enable & Mastering enable changes */
-	MCHP_ESPI_PC_IEN = (1ul << 25) + (1ul << 28);
-
-
-	/* Sufficiently initialized */
-	lpc_set_init_done(1);
-
-	/* last set eSPI Peripheral Channel Ready = 1 */
-	/* Done in ISR for PC Channel */
-	MCHP_ESPI_IO_PC_READY = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	/* NOTE: This routine may pulse SCI# and/or SMI#
-	 * For eSPI these are virtual wires. VWire channel should be
-	 * enabled before PLTRST# is de-asserted so its safe BUT has
-	 * PC Channel(I/O) Enable occurred?
-	 */
-	lpc_update_host_event_status();
-
-	CPRINTS("eSPI - espi_host_init Done");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, espi_host_init, HOOK_PRIO_FIRST);
-
-
-/*
- * Called in response to VWire OOB_RST_WARN==1 from
- * espi_vw_evt_oob_rst_warn.
- * Host chipset eSPI documentation states eSPI slave should
- * if necessary flush any OOB upstream (OOB TX) data before the slave
- * sends OOB_RST_ACK=1 to the Host.
- */
-static void espi_oob_flush(void)
-{
-}
-
-
-/*
- * Called in response to VWire HOST_RST_WARN==1 from
- * espi_vw_evt_host_rst_warn.
- * Host chipset eSPI documentation states assertion of HOST_RST_WARN
- * can be used if necessary to flush any Peripheral Channel data
- * before slave sends HOST_RST_ACK to Host.
- */
-static void espi_pc_flush(void)
-{
-}
-
-/* The ISRs of VW signals which used for power sequences */
-void espi_vw_power_signal_interrupt(enum espi_vw_signal signal)
-{
-	CPRINTS("eSPI power signal interrupt for VW %d", signal);
-	power_signal_interrupt((enum gpio_signal) signal);
-}
-
-/************************************************************************/
-/* IC specific low-level driver */
-
-
-/**
- * Set eSPI Virtual-Wire signal to Host
- *
- * @param signal vw signal needs to set
- * @param level  level of vw signal
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
-{
-	int tidx;
-	uint8_t ridx, src_num;
-
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx < 0)
-		return EC_ERROR_PARAM1;
-
-	if (0 == (vw_info_tbl[tidx].flags & (1u << 0)))
-		return EC_ERROR_PARAM1; /* signal is Master-to-Slave */
-
-	ridx = vw_info_tbl[tidx].reg_idx;
-	src_num = vw_info_tbl[tidx].src_num;
-
-	if (level)
-		level = 1;
-
-	if (signal == VW_PERIPHERAL_BTLD_STATUS_DONE) {
-		/* SLAVE_BOOT_LOAD_STATUS */
-		MCHP_ESPI_VW_S2M_SRC3(ridx) = level;
-		/* SLAVE_BOOT_LOAD_DONE after status */
-		MCHP_ESPI_VW_S2M_SRC0(ridx) = level;
-	} else {
-		MCHP_ESPI_VW_S2M_SRC(ridx, src_num) = level;
-	}
-
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("eSPI VW Set Wire %s = %d",
-		espi_vw_get_wire_name(signal), level);
-#endif
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set Slave to Master virtual wire to level and wait for hardware
- * to process virtual wire.
- * If virtual wire written to same value then hardware change bit
- * is 0 and routine returns success.
- * If virtual wire written to different value then hardware change bit
- * goes to 1 until bit is transmitted upstream to the master. This may
- * happen quickly is bus is idle. Poll for hardware clearing change bit
- * until timeout.
- */
-static int espi_vw_s2m_set_w4m(uint32_t ridx, uint32_t src_num,
-		uint8_t level)
-{
-	uint32_t i;
-
-	MCHP_ESPI_VW_S2M_SRC(ridx, src_num) = level & 0x01;
-
-	for (i = 0; i < ESPI_S2M_VW_PULSE_LOOP_CNT; i++) {
-		if ((MCHP_ESPI_VW_S2M_CHANGE(ridx) &
-		     (1u << src_num)) == 0)
-			return EC_SUCCESS;
-		udelay(ESPI_S2M_VW_PULSE_LOOP_DLY_US);
-	}
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/*
- * Create a pulse on a Slave-to-Master VWire
- * Use case is generate low pulse on SCI# virtual wire.
- * Should a timeout mechanism be added because we are
- * waiting on Host eSPI Master to respond to eSPI Alert and
- * then read the VWires. If the eSPI Master is OK the maximum
- * time will still be variable depending upon link frequency and
- * other activity on the link. Other activity is currently bounded by
- * Host chipset eSPI maximum payload length of 64 bytes + packet overhead.
- * Lowest eSPI transfer rate is 1x at 20 MHz, assume 30% packet overhead.
- * (64 * 1.3) * 8 = 666 bits is roughly 34 us. Pad to 100 us.
- */
-int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level)
-{
-	int rc, tidx;
-	uint8_t ridx, src_num, level;
-
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx < 0)
-		return EC_ERROR_PARAM1;
-
-	if (0 == (vw_info_tbl[tidx].flags & (1u << 0)))
-		return EC_ERROR_PARAM1; /* signal is Master-to-Slave */
-
-	ridx = vw_info_tbl[tidx].reg_idx;
-	src_num = vw_info_tbl[tidx].src_num;
-
-	level = 0;
-	if (pulse_level)
-		level = 1;
-
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("eSPI VW Pulse Wire %s to %d",
-		espi_vw_get_wire_name(signal), level);
-#endif
-
-	/* set requested inactive state */
-	rc = espi_vw_s2m_set_w4m(ridx, src_num, ~level);
-	if (rc != EC_SUCCESS)
-		return rc;
-
-	/* drive to requested active state */
-	rc = espi_vw_s2m_set_w4m(ridx, src_num, level);
-	if (rc != EC_SUCCESS)
-		return rc;
-
-	/* set to requested inactive state */
-	rc = espi_vw_s2m_set_w4m(ridx, src_num, ~level);
-
-	return rc;
-}
-
-/**
- * Get eSPI Virtual-Wire signal from host
- *
- * @param signal vw signal needs to get
- * @return      1: set by host, otherwise: no signal
- */
-int espi_vw_get_wire(enum espi_vw_signal signal)
-{
-	int vw, tidx;
-	uint8_t ridx, src_num;
-
-	vw = 0;
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx >= 0 && (0 == (vw_info_tbl[tidx].flags & (1u << 0)))) {
-		ridx = vw_info_tbl[tidx].reg_idx;
-		src_num = vw_info_tbl[tidx].src_num;
-		vw = MCHP_ESPI_VW_M2S_SRC(ridx, src_num) & 0x01;
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-		CPRINTS("VW GetWire %s = %d",
-			espi_vw_get_wire_name(signal), vw);
-#endif
-	}
-
-	return vw;
-}
-
-/**
- * Enable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to enable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_enable_wire_int(enum espi_vw_signal signal)
-{
-	int tidx;
-	uint8_t ridx, src_num, girq_num, bpos;
-
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx < 0)
-		return EC_ERROR_PARAM1;
-
-	if (0 != (vw_info_tbl[tidx].flags & (1u << 0)))
-		return EC_ERROR_PARAM1; /* signal is Slave-to-Master */
-
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("VW IntrEn for VW[%s]",
-		espi_vw_get_wire_name(signal));
-#endif
-
-	ridx = vw_info_tbl[tidx].reg_idx;
-	src_num = vw_info_tbl[tidx].src_num;
-
-	/*
-	 * Set SRCn_IRQ_SELECT field for VWire to either edge
-	 * Write enable set bit in GIRQ24 or GIRQ25
-	 * GIRQ24 MSVW00[0:3] through MSVW06[0:3] (bits[0:27])
-	 * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25])
-	 */
-	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) =
-			MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES;
-
-	girq_num = 24;
-	if (ridx > 6) {
-		girq_num++;
-		ridx -= 7;
-	}
-	bpos = (ridx << 2) + src_num;
-
-	MCHP_INT_SOURCE(girq_num) = (1ul << bpos);
-	MCHP_INT_ENABLE(girq_num) = (1ul << bpos);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Disable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to disable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_disable_wire_int(enum espi_vw_signal signal)
-{
-	int tidx;
-	uint8_t ridx, src_num, bpos;
-
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx < 0)
-		return EC_ERROR_PARAM1;
-
-	if (0 != (vw_info_tbl[tidx].flags & (1u << 0)))
-		return EC_ERROR_PARAM1; /* signal is Slave-to-Master */
-
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("VW IntrDis for VW[%s]",
-		espi_vw_get_wire_name(signal));
-#endif
-
-	ridx = vw_info_tbl[tidx].reg_idx;
-	src_num = vw_info_tbl[tidx].src_num;
-
-	/*
-	 * Set SRCn_IRQ_SELECT field for VWire to disabled
-	 * Write enable set bit in GIRQ24 or GIRQ25
-	 * GIRQ24 MSVW00[0:3] through MSVW06[0:3] (bits[0:27])
-	 * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25])
-	 */
-	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) =
-			MCHP_ESPI_MSVW_IRQSEL_DISABLED;
-
-	if (ridx < 7) {
-		bpos = (ridx << 2) + src_num;
-		MCHP_INT_DISABLE(24) = (1ul << bpos);
-
-	} else {
-		bpos = ((ridx - 7) << 2) + src_num;
-		MCHP_INT_DISABLE(25) = (1ul << bpos);
-	}
-
-	return EC_SUCCESS;
-}
-
-/************************************************************************/
-/* VW event handlers */
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void espi_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(espi_chipset_reset);
-#endif
-
-
-/* SLP_Sx event handler */
-void espi_vw_evt_slp_s3_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_S3: %d", wire_state);
-	espi_vw_power_signal_interrupt(VW_SLP_S3_L);
-}
-
-void espi_vw_evt_slp_s4_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_S4: %d", wire_state);
-	espi_vw_power_signal_interrupt(VW_SLP_S4_L);
-}
-
-void espi_vw_evt_slp_s5_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_S5: %d", wire_state);
-	espi_vw_power_signal_interrupt(VW_SLP_S5_L);
-}
-
-void espi_vw_evt_sus_stat_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SUS_STAT: %d", wire_state);
-	espi_vw_power_signal_interrupt(VW_SUS_STAT_L);
-}
-
-/* PLTRST# event handler */
-void espi_vw_evt_pltrst_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW PLTRST#: %d", wire_state);
-
-	if (wire_state) /* Platform Reset de-assertion */
-		espi_host_init();
-	else /* assertion */
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-		hook_call_deferred(&espi_chipset_reset_data, MSEC);
-#endif
-
-}
-
-/* OOB Reset Warn event handler */
-void espi_vw_evt_oob_rst_warn(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW OOB_RST_WARN: %d", wire_state);
-
-	espi_oob_flush();
-
-	espi_vw_set_wire(VW_OOB_RST_ACK, wire_state);
-}
-
-/* SUS_WARN# event handler */
-void espi_vw_evt_sus_warn_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SUS_WARN#: %d", wire_state);
-
-	udelay(100);
-
-	/*
-	 *  Add any Deep Sx prep here
-	 * NOTE: we could schedule a deferred function and have
-	 * it send ACK to host after preparing for Deep Sx
-	 */
-#ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
-	espi_vw_save();
-#endif
-	/* Send ACK to host by WARN#'s wire */
-	espi_vw_set_wire(VW_SUS_ACK, wire_state);
-}
-
-/*
- * SUS_PWRDN_ACK
- * PCH is informing us it does not need suspend power well.
- * if SUS_PWRDN_ACK == 1 we can turn off suspend power well assuming
- * hardware design allow.
- */
-void espi_vw_evt_sus_pwrdn_ack(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SUS_PWRDN_ACK: %d", wire_state);
-}
-
-/* SLP_A#(SLP_M#) */
-void espi_vw_evt_slp_a_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_A: %d", wire_state);
-
-	/* Put handling of ASW well devices here, if any */
-}
-
-/* HOST_RST WARN event handler */
-void espi_vw_evt_host_rst_warn(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW HOST_RST_WARN: %d", wire_state);
-
-	espi_pc_flush();
-
-	/* Send HOST_RST_ACK to host */
-	espi_vw_set_wire(VW_HOST_RST_ACK, wire_state);
-}
-
-/* SLP_LAN# */
-void espi_vw_evt_slp_lan_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_LAN: %d", wire_state);
-}
-
-/* SLP_WLAN# */
-void espi_vw_evt_slp_wlan_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_WLAN: %d", wire_state);
-
-}
-
-void espi_vw_evt_host_c10(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW HOST_C10: %d", wire_state);
-}
-
-void espi_vw_evt1_dflt(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("Unknown M2S VW: state=%d GIRQ24 bitpos=%d", wire_state, bpos);
-}
-
-void espi_vw_evt2_dflt(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("Unknown M2S VW: state=%d GIRQ25 bitpos=%d", wire_state, bpos);
-}
-
-/************************************************************************/
-/* Interrupt handlers */
-
-/* MEC1701H
- * GIRQ19 all direct connect capable, none wake capable
- *	b[0] = Peripheral Channel (PC)
- *	b[1] = Bus Master 1 (BM1)
- *	b[2] = Bus Master 2 (BM2)
- *	b[3] = LTR
- *	b[4] = OOB_UP
- *	b[5] = OOB_DN
- *	b[6] = Flash Channel (FC)
- *	b[7] = ESPI_RESET# change
- *	b[8] = VWire Channel (VW) enable assertion
- *	b[9:31] = 0 reserved
- *
- * GIRQ22 b[9]=ESPI interface wake peripheral logic only, not EC.
- *	Not direct connect capable
- *
- * GIRQ24
- *	b[0:3]   = MSVW00_SRC[0:3]
- *	b[4:7]   = MSVW01_SRC[0:3]
- *	b[8:11]  = MSVW02_SRC[0:3]
- *	b[12:15] = MSVW03_SRC[0:3]
- *	b[16:19] = MSVW04_SRC[0:3]
- *	b[20:23] = MSVW05_SRC[0:3]
- *	b[24:27] = MSVW06_SRC[0:3]
- *	b[28:31] = 0 reserved
- *
- * GIRQ25
- *	b[0:3]   = MSVW07_SRC[0:3]
- *	b[4:7]   = MSVW08_SRC[0:3]
- *	b[8:11]  = MSVW09_SRC[0:3]
- *	b[12:15] = MSVW10_SRC[0:3]
- *	b[16:31] = 0 reserved
- *
- */
-
-typedef void (*FPVW)(uint32_t, uint32_t);
-
-#define MCHP_GIRQ24_NUM_M2S	(7 * 4)
-const FPVW girq24_vw_handlers[MCHP_GIRQ24_NUM_M2S] = {
-	espi_vw_evt_slp_s3_n,	/* MSVW00, Host M2S 02h */
-	espi_vw_evt_slp_s4_n,
-	espi_vw_evt_slp_s5_n,
-	espi_vw_evt1_dflt,
-	espi_vw_evt_sus_stat_n,	/* MSVW01, Host M2S 03h */
-	espi_vw_evt_pltrst_n,
-	espi_vw_evt_oob_rst_warn,
-	espi_vw_evt1_dflt,
-	espi_vw_evt_host_rst_warn, /* MSVW02, Host M2S 07h */
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt_sus_warn_n,	/* MSVW03, Host M2S 41h */
-	espi_vw_evt_sus_pwrdn_ack,
-	espi_vw_evt1_dflt,
-	espi_vw_evt_slp_a_n,
-	espi_vw_evt_slp_lan_n,	/* MSVW04, Host M2S 42h */
-	espi_vw_evt_slp_wlan_n,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,	/* MSVW05, Host M2S 43h */
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,	/* MSVW06, Host M2S 44h */
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt
-};
-
-#define MCHP_GIRQ25_NUM_M2S	(4 * 4)
-const FPVW girq25_vw_handlers[MCHP_GIRQ25_NUM_M2S] = {
-	espi_vw_evt_host_c10,	/* MSVW07, Host M2S 47h */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW08 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW09 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW10 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-};
-
-/* Interrupt handler for eSPI virtual wires in MSVW00 - MSVW01 */
-void espi_mswv1_interrupt(void)
-{
-	uint32_t d, girq24_result, bpos;
-
-	d = MCHP_INT_ENABLE(24);
-	girq24_result = MCHP_INT_RESULT(24);
-	MCHP_INT_SOURCE(24) = girq24_result;
-
-	bpos = __builtin_ctz(girq24_result); /* rbit, clz sequence */
-	while (bpos != 32) {
-		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + 8 +
-				(12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01;
-		(girq24_vw_handlers[bpos])(d, bpos);
-		girq24_result &= ~(1ul << bpos);
-		bpos = __builtin_ctz(girq24_result);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_GIRQ24, espi_mswv1_interrupt, 2);
-
-
-/* Interrupt handler for eSPI virtual wires in MSVW07 - MSVW10 */
-void espi_msvw2_interrupt(void)
-{
-	uint32_t d, girq25_result, bpos;
-
-	d = MCHP_INT_ENABLE(25);
-	girq25_result = MCHP_INT_RESULT(25);
-	MCHP_INT_SOURCE(25) = girq25_result;
-
-	bpos = __builtin_ctz(girq25_result); /* rbit, clz sequence */
-	while (bpos != 32) {
-		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + (12 * 7) + 8 +
-				(12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01;
-		(girq25_vw_handlers[bpos])(d, bpos);
-		girq25_result &= ~(1ul << bpos);
-		bpos = __builtin_ctz(girq25_result);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_GIRQ25, espi_msvw2_interrupt, 2);
-
-
-
-/*
- * NOTES:
- * While ESPI_RESET# is asserted, all eSPI blocks are held in reset and
- * their registers can't be programmed. All channel Enable and Ready bits
- * are cleared. The only operational logic is the ESPI_RESET# change
- * detection logic.
- * Once ESPI_RESET# de-asserts, firmware can enable interrupts on all
- * other eSPI channels/components.
- * Implications are:
- * ESPI_RESET# assertion -
- *	All channel ready bits are cleared stopping all outstanding
- *	transactions and clearing registers and internal FIFO's.
- * ESPI_RESET# de-assertion -
- *	All channels/components can now be programmed and can detect
- *	reception of channel enable messages from the eSPI Master.
- */
-
-/*
- * eSPI Reset change handler
- * Multiple scenarios must be handled.
- * eSPI Link initialization from de-assertion of RSMRST#
- *	Upon RSMRST# de-assertion, the PCH may drive ESPI_RESET# low
- *	and then back high. If the platform has a pull-down on ESPI_RESET#
- *	then we will not see both edges. We must handle the scenario where
- *	ESPI_RESET# has only a rising edge or is pulsed low once RSMRST#
- *	has been released.
- * eSPI Link is operational and PCH asserts ESPI_RESET# due to
- * global reset event or some other system problem.
- *	eSPI link is operational and the system generates a global reset
- *	event to the PCH. EC is unaware of global reset and sees PCH
- *	activate ESPI_RESET#.
- *
- * ESPI_RESET# assertion will disable all MCHP eSPI channel ready
- * bits and place all channels is reset state. Any hardware affected by
- * ESPI_RESET# must be re-initialized after ESPI_RESET# de-asserts.
- *
- * Note ESPI_RESET# is not equivalent to LPC LRESET#. LRESET# is
- * equivalent to eSPI Platform Reset.
- *
- */
-void espi_reset_isr(void)
-{
-	uint8_t erst;
-
-	erst = MCHP_ESPI_IO_RESET_STATUS;
-	MCHP_ESPI_IO_RESET_STATUS = erst;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT;
-	if (erst & (1ul << 1)) { /* rising edge - reset de-asserted */
-		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = (
-				MCHP_ESPI_PC_GIRQ_BIT +
-				MCHP_ESPI_OOB_TX_GIRQ_BIT +
-				MCHP_ESPI_FC_GIRQ_BIT +
-				MCHP_ESPI_VW_EN_GIRQ_BIT);
-		MCHP_ESPI_OOB_TX_IEN = (1ul << 1);
-		MCHP_ESPI_FC_IEN = (1ul << 1);
-		MCHP_ESPI_PC_IEN = (1ul << 25);
-		CPRINTS("eSPI Reset de-assert");
-
-	} else { /* falling edge - reset asserted */
-		MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = (
-					MCHP_ESPI_PC_GIRQ_BIT +
-					MCHP_ESPI_OOB_TX_GIRQ_BIT +
-					MCHP_ESPI_FC_GIRQ_BIT +
-					MCHP_ESPI_VW_EN_GIRQ_BIT);
-		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = (
-					MCHP_ESPI_PC_GIRQ_BIT +
-					MCHP_ESPI_OOB_TX_GIRQ_BIT +
-					MCHP_ESPI_FC_GIRQ_BIT +
-					MCHP_ESPI_VW_EN_GIRQ_BIT);
-		espi_channels_ready = 0;
-
-		chipset_handle_espi_reset_assert();
-
-		CPRINTS("eSPI Reset assert");
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_RESET, espi_reset_isr, 3);
-
-/*
- * eSPI Virtual Wire channel enable handler
- * Must disable once VW Enable is set by eSPI Master
- */
-void espi_vw_en_isr(void)
-{
-	MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_VW_EN_GIRQ_BIT;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_VW_EN_GIRQ_BIT;
-
-	MCHP_ESPI_IO_VW_READY = 1;
-
-	espi_channels_ready |= (1ul << 0);
-
-	CPRINTS("eSPI VW Enable received, set VW Ready");
-
-	if (0x03 == (espi_channels_ready & 0x03))
-		espi_send_boot_load_done();
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_VW_EN, espi_vw_en_isr, 2);
-
-
-/*
- * eSPI OOB TX and OOB channel enable change interrupt handler
- */
-void espi_oob_tx_isr(void)
-{
-	uint32_t sts;
-
-	sts = MCHP_ESPI_OOB_TX_STATUS;
-	MCHP_ESPI_OOB_TX_STATUS = sts;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_OOB_TX_GIRQ_BIT;
-	if (sts & (1ul << 1)) {
-		/* Channel Enable change */
-		if (sts & (1ul << 9)) { /* enable? */
-			MCHP_ESPI_OOB_RX_LEN = 73;
-			MCHP_ESPI_IO_OOB_READY = 1;
-			espi_channels_ready |= (1ul << 2);
-			CPRINTS("eSPI OOB_UP ISR: OOB Channel Enable");
-		} else { /* no, disabled by Master */
-			espi_channels_ready &= ~(1ul << 2);
-			CPRINTS("eSPI OOB_UP ISR: OOB Channel Disable");
-		}
-	} else {
-		/* Handle OOB Up transmit status: done and/or errors, here */
-		CPRINTS("eSPI OOB_UP status = 0x%x", sts);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_UP, espi_oob_tx_isr, 2);
-
-
-/* eSPI OOB RX interrupt handler */
-void espi_oob_rx_isr(void)
-{
-	uint32_t sts;
-
-	sts = MCHP_ESPI_OOB_RX_STATUS;
-	MCHP_ESPI_OOB_RX_STATUS = sts;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_OOB_RX_GIRQ_BIT;
-	/* Handle OOB Up transmit status: done and/or errors, if any */
-	CPRINTS("eSPI OOB_DN status = 0x%x", sts);
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_DN, espi_oob_rx_isr, 2);
-
-
-/*
- * eSPI Flash Channel enable change and data transfer
- * interrupt handler
- */
-void espi_fc_isr(void)
-{
-	uint32_t sts;
-
-	sts = MCHP_ESPI_FC_STATUS;
-	MCHP_ESPI_FC_STATUS = sts;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_FC_GIRQ_BIT;
-	if (sts & (1ul << 1)) {
-		/* Channel Enable change */
-		if (sts & (1ul << 0)) { /* enable? */
-			MCHP_ESPI_IO_FC_READY = 1;
-			espi_channels_ready |= (1ul << 1);
-			CPRINTS("eSPI FC ISR: Enable");
-			if (0x03 == (espi_channels_ready & 0x03))
-				espi_send_boot_load_done();
-		} else { /* no, disabled by Master */
-			espi_channels_ready &= ~(1ul << 1);
-			CPRINTS("eSPI FC ISR: Disable");
-		}
-	} else {
-		/* Handle FC command status: done and/or errors */
-		CPRINTS("eSPI FC status = 0x%x", sts);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_FC, espi_fc_isr, 2);
-
-
-/* eSPI Peripheral Channel interrupt handler */
-void espi_pc_isr(void)
-{
-	uint32_t sts;
-
-	sts = MCHP_ESPI_PC_STATUS;
-	MCHP_ESPI_PC_STATUS = sts;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_PC_GIRQ_BIT;
-	if (sts & (1ul << 25)) {
-		if (sts & (1ul << 24)) {
-			MCHP_ESPI_IO_PC_READY = 1;
-			espi_channels_ready |= (1ul << 3);
-			CPRINTS("eSPI PC Channel Enable");
-		} else {
-			espi_channels_ready &= ~(1ul << 3);
-			CPRINTS("eSPI PC Channel Disable");
-		}
-
-	} else {
-		/* Handler PC channel errors here */
-		CPRINTS("eSPI PC status = 0x%x", sts);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_PC, espi_pc_isr, 2);
-
-
-/************************************************************************/
-
-/*
- * Enable/disable direct mode interrupt for ESPI_RESET# change.
- * Optionally clear status before enable or after disable.
- */
-static void espi_reset_ictrl(int enable, int clr_status)
-{
-	if (enable) {
-		if (clr_status) {
-			MCHP_ESPI_IO_RESET_STATUS =
-					MCHP_ESPI_RST_CHG_STS;
-			MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
-					MCHP_ESPI_RESET_GIRQ_BIT;
-		}
-		MCHP_ESPI_IO_RESET_IEN |= MCHP_ESPI_RST_IEN;
-		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) =
-				MCHP_ESPI_RESET_GIRQ_BIT;
-		task_enable_irq(MCHP_IRQ_ESPI_RESET);
-	} else {
-		task_disable_irq(MCHP_IRQ_ESPI_RESET);
-		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) =
-				MCHP_ESPI_RESET_GIRQ_BIT;
-		MCHP_ESPI_IO_RESET_IEN &= ~(MCHP_ESPI_RST_IEN);
-		if (clr_status) {
-			MCHP_ESPI_IO_RESET_STATUS =
-					MCHP_ESPI_RST_CHG_STS;
-			MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
-					MCHP_ESPI_RESET_GIRQ_BIT;
-		}
-	}
-}
-
-/* eSPI Initialization functions */
-
-/* MEC1701H */
-void espi_init(void)
-{
-	espi_channels_ready = 0;
-
-	CPRINTS("eSPI - espi_init");
-
-	/* Clear PCR eSPI sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ESPI);
-
-	/*
-	 * b[8]=0(eSPI PLTRST# VWire is platform reset), b[0]=0
-	 * VCC_PWRGD is asserted when PLTRST# VWire is 1(inactive)
-	 */
-	MCHP_PCR_PWR_RST_CTL = 0;
-
-	/*
-	 * There is no MODULE_ESPI in include/module_id.h
-	 * eSPI pins marked as MODULE_LPC in board/myboard/board.h
-	 * eSPI pins are on VTR3.
-	 * Make sure VTR3 chip knows VTR3 is 1.8V
-	 * This is done in system_pre_init()
-	 */
-	gpio_config_module(MODULE_LPC, 1);
-
-	/* Set channel */
-	MCHP_ESPI_IO_CAP0 = CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP;
-
-	/* Set eSPI frequency & mode */
-	MCHP_ESPI_IO_CAP1 = (MCHP_ESPI_IO_CAP1 &
-				(~(MCHP_ESPI_CAP1_MAX_FREQ_MASK |
-				MCHP_ESPI_CAP1_IO_MASK))) |
-				CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ |
-				(CONFIG_HOSTCMD_ESPI_EC_MODE
-				<< MCHP_ESPI_CAP1_IO_BITPOS);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW;
-#else
-	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_PIN;
-#endif
-
-	MCHP_PCR_PWR_RST_CTL &=
-		~(1ul << MCHP_PCR_PWR_HOST_RST_SEL_BITPOS);
-
-	MCHP_ESPI_ACTIVATE = 1;
-
-	espi_bar_pre_init();
-
-	/*
-	 * VWires are configured to be reset by different events.
-	 * Default configuration has:
-	 * RESET_SYS (chip reset) MSVW00, MSVW04
-	 * RESET_ESPI MSVW01, MSVW03, SMVW00, SMVW01
-	 * PLTRST MSVW02, SMVW02
-	 */
-	espi_vw_pre_init();
-
-	/*
-	 * Configure MSVW00 & MSVW04
-	 * Any change to default values (SRCn bits)
-	 * Any change to interrupt enable, SRCn_IRQ_SELECT bit fields
-	 *   Should interrupt bits in MSVWyx and GIRQ24/25 be touched
-	 *   before ESPI_RESET# de-asserts?
-	 */
-
-	MCHP_ESPI_PC_STATUS = 0xfffffffful;
-	MCHP_ESPI_OOB_RX_STATUS = 0xfffffffful;
-	MCHP_ESPI_FC_STATUS = 0xfffffffful;
-	MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = 0xfffffffful;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = 0xfffffffful;
-
-	task_enable_irq(MCHP_IRQ_ESPI_PC);
-	task_enable_irq(MCHP_IRQ_ESPI_OOB_UP);
-	task_enable_irq(MCHP_IRQ_ESPI_OOB_DN);
-	task_enable_irq(MCHP_IRQ_ESPI_FC);
-	task_enable_irq(MCHP_IRQ_ESPI_VW_EN);
-
-	/* Enable eSPI Master-to-Slave Virtual wire NVIC inputs
-	 * VWire block interrupts are all disabled by default
-	 * and will be controlled by espi_vw_enable/disable_wire_in
-	 */
-	CPRINTS("eSPI - enable ESPI_RESET# interrupt");
-
-	/* Enable ESPI_RESET# interrupt and clear status */
-	espi_reset_ictrl(1, 1);
-
-	CPRINTS("eSPI - espi_init - done");
-}
-
-
-#ifdef CONFIG_MCHP_ESPI_EC_CMD
-static int command_espi(int argc, char **argv)
-{
-	uint32_t chan, w0, w1, w2;
-	char *e;
-
-	if (argc == 1) {
-		return EC_ERROR_INVAL;
-	/* Get value of eSPI registers */
-	} else if (argc == 2) {
-		int i;
-
-		if (strcasecmp(argv[1], "cfg") == 0) {
-			ccprintf("eSPI Reg32A [0x%08x]\n",
-				 MCHP_ESPI_IO_REG32_A);
-			ccprintf("eSPI Reg32B [0x%08x]\n",
-				 MCHP_ESPI_IO_REG32_B);
-			ccprintf("eSPI Reg32C [0x%08x]\n",
-				 MCHP_ESPI_IO_REG32_C);
-			ccprintf("eSPI Reg32D [0x%08x]\n",
-				 MCHP_ESPI_IO_REG32_D);
-		} else if (strcasecmp(argv[1], "vsm") == 0) {
-			for (i = 0; i < MSVW_MAX; i++) {
-				w0 = MSVW(i, 0);
-				w1 = MSVW(i, 1);
-				w2 = MSVW(i, 2);
-				ccprintf("MSVW%d: 0x%08x:%08x:%08x\n", i,
-					w2, w1, w0);
-			}
-		} else if (strcasecmp(argv[1], "vms") == 0) {
-			for (i = 0; i < SMVW_MAX; i++) {
-				w0 = SMVW(i, 0);
-				w1 = SMVW(i, 1);
-				ccprintf("SMVW%d: 0x%08x:%08x\n", i, w1, w0);
-			}
-		}
-	/* Enable/Disable the channels of eSPI */
-	} else if (argc == 3) {
-		uint32_t m = (uint32_t) strtoi(argv[2], &e, 0);
-
-		if (*e)
-			return EC_ERROR_PARAM2;
-		if (m < 0 || m > 4)
-			return EC_ERROR_PARAM2;
-		else if (m == 4)
-			chan = 0x0F;
-		else
-			chan = 0x01 << m;
-		if (strcasecmp(argv[1], "en") == 0)
-			MCHP_ESPI_IO_CAP0 |= chan;
-		else if (strcasecmp(argv[1], "dis") == 0)
-			MCHP_ESPI_IO_CAP0 &= ~chan;
-		else
-			return EC_ERROR_PARAM1;
-		ccprintf("eSPI IO Cap0 [0x%02x]\n", MCHP_ESPI_IO_CAP0);
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(espi, command_espi,
-			"cfg/vms/vsm/en/dis [channel]",
-			"eSPI configurations");
-#endif
diff --git a/chip/mchp/fan.c b/chip/mchp/fan.c
deleted file mode 100644
index 17b60b703d..0000000000
--- a/chip/mchp/fan.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MCHP MEC fan control module. */
-
-/* This assumes 2-pole fan. For each rotation, 5 edges are measured. */
-
-#include "fan.h"
-#include "registers.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-/* Maximum fan driver setting value */
-#define MAX_FAN_DRIVER_SETTING 0x3ff
-
-/* Fan driver setting data in bit[15:6] of hardware register */
-#define FAN_DRIVER_SETTING_SHIFT 6
-
-/* Maximum tach reading/target value */
-#define MAX_TACH 0x1fff
-
-/* Tach target value for disable fan */
-#define FAN_OFF_TACH 0xfff8
-
-/*
- * RPM = (n - 1) * m * f * 60 / poles / TACH
- *   n = number of edges = 5
- *   m = multiplier defined by RANGE = 2 in our case
- *   f = 32.768K
- *   poles = 2
- */
-#define RPM_TO_TACH(rpm) MIN((7864320 / MAX((rpm), 1)), MAX_TACH)
-#define TACH_TO_RPM(tach) (7864320 / MAX((tach), 1))
-
-static int rpm_setting;
-static int duty_setting;
-static int in_rpm_mode = 1;
-
-
-static void clear_status(void)
-{
-	/* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */
-	MCHP_FAN_STATUS(0) = 0x23;
-}
-
-void fan_set_enabled(int ch, int enabled)
-{
-	if (in_rpm_mode) {
-		if (enabled)
-			fan_set_rpm_target(ch, rpm_setting);
-		else
-			MCHP_FAN_TARGET(0) = FAN_OFF_TACH;
-	} else {
-		if (enabled)
-			fan_set_duty(ch, duty_setting);
-		else
-			MCHP_FAN_SETTING(0) = 0;
-	}
-	clear_status();
-}
-
-int fan_get_enabled(int ch)
-{
-	if (in_rpm_mode)
-		return (MCHP_FAN_TARGET(0) & 0xff00) != 0xff00;
-	else
-		return !!MCHP_FAN_SETTING(0);
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	duty_setting = percent;
-	MCHP_FAN_SETTING(0) = (percent * MAX_FAN_DRIVER_SETTING / 100)
-		<< FAN_DRIVER_SETTING_SHIFT;
-	clear_status();
-}
-
-int fan_get_duty(int ch)
-{
-	duty_setting = (MCHP_FAN_SETTING(0) >> FAN_DRIVER_SETTING_SHIFT)
-		* 100 / MAX_FAN_DRIVER_SETTING;
-	return duty_setting;
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	return !!(MCHP_FAN_CFG1(0) & BIT(7));
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	if (rpm_mode)
-		MCHP_FAN_CFG1(0) |= BIT(7);
-	else
-		MCHP_FAN_CFG1(0) &= ~BIT(7);
-	clear_status();
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	if ((MCHP_FAN_READING(0) >> 8) == 0xff)
-		return 0;
-	else
-		return TACH_TO_RPM(MCHP_FAN_READING(0) >> 3);
-}
-
-int fan_get_rpm_target(int ch)
-{
-	return rpm_setting;
-}
-
-void fan_set_rpm_target(int ch, int rpm)
-{
-	rpm_setting = rpm;
-	MCHP_FAN_TARGET(0) = RPM_TO_TACH(rpm) << 3;
-	clear_status();
-}
-
-enum fan_status fan_get_status(int ch)
-{
-	uint8_t sts = MCHP_FAN_STATUS(0);
-
-	if (sts & (BIT(5) | BIT(1)))
-		return FAN_STATUS_FRUSTRATED;
-	if (fan_get_rpm_actual(ch) == 0)
-		return FAN_STATUS_STOPPED;
-	return FAN_STATUS_LOCKED;
-}
-
-int fan_is_stalled(int ch)
-{
-	uint8_t sts = MCHP_FAN_STATUS(0);
-
-	if (fan_get_rpm_actual(ch)) {
-		MCHP_FAN_STATUS(0) = 0x1;
-		return 0;
-	}
-	return sts & 0x1;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	/* Clear PCR sleep enable for RPM2FAN0 */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_RPMPWM0);
-	/* Configure PWM Min drive */
-	MCHP_FAN_MIN_DRV(0) = 0x0A;
-	/*
-	 * Fan configuration 1 register:
-	 *   0x80 = bit 7    = RPM mode (0x00 if FAN_USE_RPM_MODE not set)
-	 *   0x20 = bits 6:5 = min 1000 RPM, multiplier = 2
-	 *   0x08 = bits 4:3 = 5 edges, 2 poles
-	 *   0x03 = bits 2:0 = 400 ms update time
-	 *
-	 * Fan configuration 2 register:
-	 *   0x00 = bit 7    = Ramp control disabled
-	 *   0x00 = bit 6    = Glitch filter enabled
-	 *   0x30 = bits 5:4 = Using both derivative options
-	 *   0x04 = bits 3:2 = error range is 50 RPM
-	 *   0x00 = bits 1   = normal polarity
-	 *   0x00 = bit 0    = Reserved
-	 */
-	if (flags & FAN_USE_RPM_MODE)
-		MCHP_FAN_CFG1(0) = 0xab;
-	else
-		MCHP_FAN_CFG1(0) = 0x2b;
-	MCHP_FAN_CFG2(0) = 0x34;
-	clear_status();
-}
diff --git a/chip/mchp/flash.c b/chip/mchp/flash.c
deleted file mode 100644
index 1679cf92cb..0000000000
--- a/chip/mchp/flash.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "host_command.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "system.h"
-#include "util.h"
-#include "hooks.h"
-#include "tfdp_chip.h"
-
-#define PAGE_SIZE 256
-
-#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
-#define FLASH_HOOK_VERSION 1
-
-static int entire_flash_locked;
-
-/* The previous write protect state before sys jump */
-
-struct flash_wp_state {
-	int entire_flash_locked;
-};
-
-/**
- * Read from physical flash.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Destination buffer for data.
- */
-int crec_flash_physical_read(int offset, int size, char *data)
-{
-	trace13(0, FLASH, 0,
-		"flash_phys_read: offset=0x%08X size=0x%08X dataptr=0x%08X",
-		offset, size, (uint32_t)data);
-	return spi_flash_read(data, offset, size);
-}
-
-/**
- * Write to physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Data to write to flash.  Must be 32-bit aligned.
- */
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int ret = EC_SUCCESS;
-	int  i, write_size;
-
-	trace13(0, FLASH, 0,
-		"flash_phys_write: offset=0x%08X size=0x%08X dataptr=0x%08X",
-		offset, size, (uint32_t)data);
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	for (i = 0; i < size; i += write_size) {
-		write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE);
-		ret = spi_flash_write(offset + i,
-				      write_size,
-				      (uint8_t *)data + i);
-		if (ret != EC_SUCCESS)
-			break;
-	}
-	return ret;
-}
-
-/**
- * Erase physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE.
- *
- * @param offset        Flash offset to erase.
- * @param size          Number of bytes to erase.
- */
-int crec_flash_physical_erase(int offset, int size)
-{
-	int ret;
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	trace12(0, FLASH, 0,
-		"flash_phys_erase: offset=0x%08X size=0x%08X",
-		offset, size);
-	ret = spi_flash_erase(offset, size);
-	return ret;
-}
-
-/**
- * Read physical write protect setting for a flash bank.
- *
- * @param bank    Bank index to check.
- * @return        non-zero if bank is protected until reboot.
- */
-int crec_flash_physical_get_protect(int bank)
-{
-	return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE,
-			CONFIG_FLASH_BANK_SIZE);
-}
-
-/**
- * Protect flash now.
- *
- * This is always successful, and only emulates "now" protection
- *
- * @param all      Protect all (=1) or just read-only
- * @return         non-zero if error.
- */
-int crec_flash_physical_protect_now(int all)
-{
-	if (all)
-		entire_flash_locked = 1;
-
-	/*
-	 * RO "now" protection is not currently implemented. If needed, it
-	 * can be added by splitting the entire_flash_locked variable into
-	 * and RO and RW vars, and setting + checking the appropriate var
-	 * as required.
-	 */
-	return EC_SUCCESS;
-}
-
-/**
- * Return flash protect state flags from the physical layer.
- *
- * This should only be called by flash_get_protect().
- *
- * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	if (spi_flash_check_protect(CONFIG_WP_STORAGE_OFF,
-				    CONFIG_WP_STORAGE_SIZE)) {
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	if (entire_flash_locked)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return flags;
-}
-
-/**
- * Return the valid flash protect flags.
- *
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-/**
- * Return the writable flash protect flags.
- *
- * @param    cur_flags The current flash protect flags.
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-	enum spi_flash_wp wp_status = SPI_WP_NONE;
-
-	wp_status = spi_flash_check_wp();
-
-	if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE &&
-	   !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
-		ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-
-	if (!entire_flash_locked)
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-/**
- * Enable write protect for the specified range.
- *
- * Once write protect is enabled, it will stay enabled until HW PIN is
- * de-asserted and SRP register is unset.
- *
- * However, this implementation treats FLASH_WP_ALL as FLASH_WP_RO but
- * tries to remember if "all" region is protected.
- *
- * @param range         The range to protect.
- * @return              EC_SUCCESS, or nonzero if error.
- */
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int offset, size, ret;
-	enum spi_flash_wp flashwp = SPI_WP_NONE;
-
-	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
-			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
-		/* Clear protection */
-		offset = size = 0;
-		flashwp = SPI_WP_NONE;
-	} else {
-		if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-			entire_flash_locked = 1;
-
-		offset = CONFIG_WP_STORAGE_OFF;
-		size = CONFIG_WP_STORAGE_SIZE;
-		flashwp = SPI_WP_HARDWARE;
-	}
-
-	ret = spi_flash_set_protect(offset, size);
-	if (ret == EC_SUCCESS)
-		ret = spi_flash_set_wp(flashwp);
-	return ret;
-}
-
-/**
- * Initialize the module.
- *
- * Applies at-boot protection settings if necessary.
- */
-int crec_flash_pre_init(void)
-{
-	crec_flash_physical_restore_state();
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	int version, size;
-	const struct flash_wp_state *prev;
-
-	/*
-	 * If we have already jumped between images, an earlier image
-	 * could have applied write protection. Nothing additional needs
-	 * to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
-		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
-		if (prev && version == FLASH_HOOK_VERSION &&
-		    size == sizeof(*prev))
-			entire_flash_locked = prev->entire_flash_locked;
-		return 1;
-	}
-
-	return 0;
-}
-
-/************************************************************************/
-/* Hooks */
-
-static void flash_preserve_state(void)
-{
-	struct flash_wp_state state;
-
-	state.entire_flash_locked = entire_flash_locked;
-
-	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c
deleted file mode 100644
index 611ced1019..0000000000
--- a/chip/mchp/gpio.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for MCHP MEC */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "lpc_chip.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-
-struct gpio_int_mapping {
-	int8_t girq_id;
-	int8_t port_offset;
-};
-
-/*
- * Mapping from GPIO port to GIRQ info
- * MEC17xx each bank contains 32 GPIO's.
- * Pin Id is the bit position [0:31]
- * Bank		GPIO's		GIRQ
- * 0		0000 - 0036	11
- * 1		0040 - 0076	10
- * 2		0100 - 0135	9
- * 3		0140 - 0175	8
- * 4		0200 - 0235	12
- * 5		0240 - 0276	26
- */
-static const struct gpio_int_mapping int_map[] = {
-	{ 11, 0 }, { 10, 1 }, { 9, 2 },
-	{ 8, 3 }, { 12, 4 }, { 26, 5 }
-};
-BUILD_ASSERT(ARRAY_SIZE(int_map) == MCHP_GPIO_MAX_PORT);
-
-/*
- * These pins default to BGPO functionality. BGPO overrides GPIO Control
- * register programming. If the pin is in the GPIO list the user wants to
- * use the pin as GPIO and we must disable BGPIO functionality for this pin.
- */
-struct bgpo_pin {
-	uint16_t pin;
-	uint8_t bgpo_pos;
-};
-
-static const struct bgpo_pin bgpo_list[] = {
-	{ 0101, 1 }, /* GPIO 0101 */
-	{ 0102, 2 }, /* GPIO 0102 */
-#if defined(CHIP_FAMILY_MEC152X)
-	{ 0253, 0 }, /* GPIO 0253 */
-#elif defined(CHIP_FAMILY_MEC170X)
-	{ 0172, 3 }, /* GPIO 0172 */
-#endif
-};
-
-static const uint32_t bgpo_map[] = {
-#if defined(CHIP_FAMILY_MEC152X)
-	0, 0, (BIT(1) | BIT(2)), 0, 0, BIT(11)
-#elif defined(CHIP_FAMILY_MEC170X)
-	0, 0, (BIT(1) | BIT(2)), BIT(26), 0, 0
-#else
-	0, 0, 0, 0, 0, 0
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(bgpo_map) == MCHP_GPIO_MAX_PORT);
-
-/* Check for BGPO capable pins on this port and disable BGPO feature */
-static void disable_bgpo(uint32_t port, uint32_t mask)
-{
-	int i, n;
-	uint32_t gpnum;
-	uint32_t m = bgpo_map[port] & mask;
-
-	while (m) {
-		i = __builtin_ffs(m) - 1;
-		gpnum = (port * 32U) + i;
-		for (n = 0; n < ARRAY_SIZE(bgpo_list); n++)
-			if (gpnum == bgpo_list[n].pin)
-				MCHP_WKTIMER_BGPO_POWER &=
-					~BIT(bgpo_list[n].bgpo_pos);
-		m &= ~BIT(i);
-	}
-}
-
-/*
- * NOTE: GCC __builtin_ffs(val) returns (index + 1) of least significant
- * 1-bit of val or if val == 0 returns 0
- */
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int i;
-	uint32_t val;
-
-	if (port >= MCHP_GPIO_MAX_PORT)
-		return;
-
-	while (mask) {
-		i = __builtin_ffs(mask) - 1;
-		val = MCHP_GPIO_CTL(port, i);
-		val &= ~(BIT(12) | BIT(13));
-		/* mux_control = DEFAULT, indicates GPIO */
-		if (func > GPIO_ALT_FUNC_DEFAULT)
-			val |= (func & 0x3) << 12;
-		MCHP_GPIO_CTL(port, i) = val;
-		mask &= ~BIT(i);
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-	uint32_t val;
-
-	if (mask == 0)
-		return 0;
-	i = GPIO_MASK_TO_NUM(mask);
-	val = MCHP_GPIO_CTL(gpio_list[signal].port, i);
-
-	return (val & BIT(24)) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-
-	if (mask == 0)
-		return;
-	i = GPIO_MASK_TO_NUM(mask);
-
-	if (value)
-		MCHP_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16);
-	else
-		MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16);
-}
-
-/*
- * Add support for new #ifdef CONFIG_CMD_GPIO_POWER_DOWN.
- * If GPIO_POWER_DOWN flag is set force GPIO Control to
- * GPIO input, interrupt detect disabled, power control field
- * in bits[3:2]=10b.
- * NOTE: if interrupt detect is enabled when pin is powered down
- * then a false edge may be detected.
- * NOTE 2: MEC152x family implements input pad disable (bit[15]=1).
- */
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	int i;
-	uint32_t val;
-
-	if (port >= MCHP_GPIO_MAX_PORT)
-		return;
-
-	while (mask) {
-		i = GPIO_MASK_TO_NUM(mask);
-		mask &= ~BIT(i);
-		val = MCHP_GPIO_CTL(port, i);
-
-#ifdef CONFIG_GPIO_POWER_DOWN
-		if (flags & GPIO_POWER_DOWN) {
-			val = (MCHP_GPIO_CTRL_PWR_OFF
-				| MCHP_GPIO_INTDET_DISABLED
-				| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
-
-			MCHP_GPIO_CTL(port, i) = val;
-			continue;
-		}
-#endif
-		val &= ~(MCHP_GPIO_CTRL_PWR_MASK
-			| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
-
-		val |= MCHP_GPIO_CTRL_PWR_VTR;
-		/*
-		 * Select open drain first, so that we don't
-		 * glitch the signal when changing the line to
-		 * an output.
-		 */
-		if (flags & GPIO_OPEN_DRAIN)
-			val |= (MCHP_GPIO_OPEN_DRAIN);
-		else
-			val &= ~(MCHP_GPIO_OPEN_DRAIN);
-
-		if (flags & GPIO_OUTPUT) {
-			val |= (MCHP_GPIO_OUTPUT);
-			val &= ~(MCHP_GPIO_OUTSEL_PAR);
-		} else {
-			val &= ~(MCHP_GPIO_OUTPUT);
-			val |= (MCHP_GPIO_OUTSEL_PAR);
-		}
-
-		/* Handle pull-up / pull-down */
-		val &= ~(MCHP_GPIO_CTRL_PUD_MASK);
-		if (flags & GPIO_PULL_UP)
-			val |= MCHP_GPIO_CTRL_PUD_PU;
-		else if (flags & GPIO_PULL_DOWN)
-			val |= MCHP_GPIO_CTRL_PUD_PD;
-		else
-			val |= MCHP_GPIO_CTRL_PUD_NONE;
-
-		/* Set up interrupt */
-		val &= ~(MCHP_GPIO_INTDET_MASK);
-		switch (flags & GPIO_INT_ANY) {
-		case GPIO_INT_F_RISING:
-			val |= MCHP_GPIO_INTDET_EDGE_RIS;
-			break;
-		case GPIO_INT_F_FALLING:
-			val |= MCHP_GPIO_INTDET_EDGE_FALL;
-			break;
-		case GPIO_INT_BOTH: /* both edges */
-			val |= MCHP_GPIO_INTDET_EDGE_BOTH;
-			break;
-		case GPIO_INT_F_LOW:
-			val |= MCHP_GPIO_INTDET_LVL_LO;
-			break;
-		case GPIO_INT_F_HIGH:
-			val |= MCHP_GPIO_INTDET_LVL_HI;
-			break;
-		default:
-			val |= MCHP_GPIO_INTDET_DISABLED;
-			break;
-		}
-
-		/* Set up level */
-		if (flags & GPIO_HIGH)
-			val |= (MCHP_GPIO_CTRL_OUT_LVL);
-		else if (flags & GPIO_LOW)
-			val &= ~(MCHP_GPIO_CTRL_OUT_LVL);
-
-		MCHP_GPIO_CTL(port, i) = val;
-	}
-}
-
-void gpio_power_off_by_mask(uint32_t port, uint32_t mask)
-{
-	int i;
-
-	if (port >= MCHP_GPIO_MAX_PORT)
-		return;
-
-	while (mask) {
-		i = GPIO_MASK_TO_NUM(mask);
-		mask &= ~BIT(i);
-		MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF
-					| MCHP_GPIO_INTDET_DISABLED
-					| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
-	}
-}
-
-int gpio_power_off(enum gpio_signal signal)
-{
-	int i, port;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_ERROR_INVAL;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF
-				| MCHP_GPIO_INTDET_DISABLED
-				| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
-
-	return EC_SUCCESS;
-}
-
-/*
- * gpio_list[signal].port = [0, 6] each port contains up to 32 pins
- * gpio_list[signal].mask = bit mask in 32-bit port
- * NOTE: MCHP GPIO are always aggregated not direct connected to NVIC.
- * GPIO's are aggregated into banks of 32 pins.
- * Each bank/port are connected to a GIRQ.
- * int_map[port].girq_id is the GIRQ ID
- * The bit number in the GIRQ registers is the same as the bit number
- * in the GPIO bank.
- */
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-
-	MCHP_INT_ENABLE(girq_id) = BIT(i);
-	MCHP_INT_BLK_EN |= BIT(girq_id);
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-
-
-	MCHP_INT_DISABLE(girq_id) = BIT(i);
-
-	return EC_SUCCESS;
-}
-
-/*
- * MCHP Interrupt Source is R/W1C no need for read-modify-write.
- * GPIO's are aggregated meaning the NVIC Pending bit may be
- * set for another GPIO in the GIRQ. You can clear NVIC pending
- * and the hardware should re-assert it within one Cortex-M4 clock.
- * If the Cortex-M4 is clocked slower than AHB then the Cortex-M4
- * will take longer to register the interrupt. Not clearing NVIC
- * pending leave a pending status if only the GPIO this routine
- * clears is pending.
- * NVIC (system control) register space is strongly-ordered
- * Interrupt Aggregator is in Device space (system bus connected
- * to AHB) with the Cortex-M4 write buffer.
- * We need to insure the write to aggregator register in device
- * AHB space completes before NVIC pending is cleared.
- * The Cortex-M4 memory ordering rules imply Device access
- * comes before strongly ordered access. Cortex-M4 will not re-order
- * the writes. Due to the presence of the write buffer a DSB will
- * not guarantee the clearing of the device status completes. Add
- * a read back before clearing NVIC pending.
- * GIRQ 8, 9, 10, 11, 12, 26 map to NVIC inputs 0, 1, 2, 3, 4, and 18.
- */
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-
-	/* Clear interrupt source sticky status bit even if not enabled */
-	MCHP_INT_SOURCE(girq_id) = BIT(i);
-	i = MCHP_INT_SOURCE(girq_id);
-	task_clear_pending_irq(girq_id - 8);
-
-	return EC_SUCCESS;
-}
-
-/*
- * MCHP NOTE - called from main before scheduler started
- */
-void gpio_pre_init(void)
-{
-	int i;
-	int flags;
-	int is_warm = system_is_reboot_warm();
-	const struct gpio_info *g = gpio_list;
-
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		disable_bgpo(g->port, g->mask);
-
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-}
-
-/* Clear any interrupt flags before enabling GPIO interrupt
- * Original code has flaws.
- * Writing result register to source only clears bits that have their
- * enable and sources bits set.
- * We must clear the NVIC pending R/W bit before setting NVIC enable.
- * NVIC Pending is only cleared by the NVIC HW on ISR entry.
- * Modifications are:
- * 1. Clear all status bits in each GPIO GIRQ. This assumes any edges
- *    will occur after gpio_init. The old code is also making this
- *    assumption for the GPIO's that have been enabled.
- * 2. Clear NVIC pending to prevent ISR firing on false edge.
- */
-#define ENABLE_GPIO_GIRQ(x) \
-	do { \
-		MCHP_INT_SOURCE(x) = 0xfffffffful; \
-		task_clear_pending_irq(MCHP_IRQ_GIRQ ## x); \
-		task_enable_irq(MCHP_IRQ_GIRQ ## x); \
-	} while (0)
-
-
-static void gpio_init(void)
-{
-	ENABLE_GPIO_GIRQ(8);
-	ENABLE_GPIO_GIRQ(9);
-	ENABLE_GPIO_GIRQ(10);
-	ENABLE_GPIO_GIRQ(11);
-	ENABLE_GPIO_GIRQ(12);
-	ENABLE_GPIO_GIRQ(26);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/************************************************************************/
-/* Interrupt handlers */
-
-
-/**
- * Handler for each GIRQ interrupt. This reads and clears the interrupt
- * bits for the GIRQ interrupt, then finds and calls the corresponding
- * GPIO interrupt handlers.
- *
- * @param girq		GIRQ index
- * @param port	zero based GPIO port number [0, 5]
- * @note __builtin_ffs(x) returns bitpos+1 of least significant 1-bit
- * in x or 0 if no bits are set.
- */
-static void gpio_interrupt(int girq, int port)
-{
-	int i, bit;
-	const struct gpio_info *g = gpio_list;
-	uint32_t sts = MCHP_INT_RESULT(girq);
-
-	/* RW1C, no need for read-modify-write */
-	MCHP_INT_SOURCE(girq) = sts;
-
-	trace12(0, GPIO, 0, "GPIO GIRQ %d result = 0x%08x", girq, sts);
-	trace12(0, GPIO, 0, "GPIO ParIn[%d]      = 0x%08x",
-		port, MCHP_GPIO_PARIN(port));
-
-	for (i = 0; (i < GPIO_IH_COUNT) && sts; ++i, ++g) {
-		if (g->port != port)
-			continue;
-
-		bit = __builtin_ffs(g->mask);
-		if (bit) {
-			bit--;
-			if (sts & BIT(bit)) {
-				trace12(0, GPIO, 0,
-					"Bit[%d]: handler @ 0x%08x", bit,
-					(uint32_t)gpio_irq_handlers[i]);
-				gpio_irq_handlers[i](i);
-			}
-			sts &= ~BIT(bit);
-		}
-	}
-}
-
-#define GPIO_IRQ_FUNC(irqfunc, girq, port)\
-	void irqfunc(void) \
-	{ \
-		gpio_interrupt(girq, port);\
-	}
-
-GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 3);
-GPIO_IRQ_FUNC(__girq_9_interrupt, 9, 2);
-GPIO_IRQ_FUNC(__girq_10_interrupt, 10, 1);
-GPIO_IRQ_FUNC(__girq_11_interrupt, 11, 0);
-GPIO_IRQ_FUNC(__girq_12_interrupt, 12, 4);
-GPIO_IRQ_FUNC(__girq_26_interrupt, 26, 5);
-
-#undef GPIO_IRQ_FUNC
-
-/*
- * Declare IRQs.  Nesting this macro inside the GPIO_IRQ_FUNC macro works
- * poorly because DECLARE_IRQ() stringizes its inputs.
- */
-DECLARE_IRQ(MCHP_IRQ_GIRQ8, __girq_8_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ9, __girq_9_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ10, __girq_10_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ11, __girq_11_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ12, __girq_12_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ26, __girq_26_interrupt, 1);
-
diff --git a/chip/mchp/gpio_chip.h b/chip/mchp/gpio_chip.h
deleted file mode 100644
index 7baaa76fa2..0000000000
--- a/chip/mchp/gpio_chip.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MCHP MEC processor
- */
-/** @file gpio_chip.h
- *MEC GPIO module
- */
-/** @defgroup MEC gpio
- */
-
-#ifndef _GPIO_CHIP_H
-#define _GPIO_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#include "gpio.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Place any C interfaces here */
-
-int gpio_power_off(enum gpio_signal signal);
-
-void gpio_power_off_by_mask(uint32_t port, uint32_t mask);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef _GPIO_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/gpio_cmds.c b/chip/mchp/gpio_cmds.c
deleted file mode 100644
index cbf5f4c462..0000000000
--- a/chip/mchp/gpio_cmds.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MCHP MEC GPIO module EC UART commands */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "util.h"
-#include "gpio_chip.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-
-
-static int cmd_gp_get_config(int argc, char **argv)
-{
-	char *e;
-	int i;
-	uint32_t gctrl;
-
-	/* If a signal is specified, print only that one */
-	if (argc == 2) {
-		i = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		if (!gpio_is_implemented(i))
-			return EC_ERROR_PARAM1;
-
-		gctrl = MCHP_GPIO_CTRL(i);
-
-		ccprintf(" GPIO[0x%X].Ctrl = 0x%08X\n", i, gctrl);
-
-	} else { /* Otherwise print them all */
-		for (i = 0; i < GPIO_COUNT; i++) {
-			if (!gpio_is_implemented(i))
-				continue;  /* Skip unsupported signals */
-
-			gctrl = MCHP_GPIO_CTRL(i);
-
-			ccprintf(" GPIO[0x%X].Ctrl = 0x%08X\n", i, gctrl);
-		}
-	}
-
-	/* Flush console to avoid truncating output */
-	cflush();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(gpgetcfg, cmd_gp_get_config,
-			"[number]",
-			"Read GPIO config");
-
-static int cmd_gp_set_config(int argc, char **argv)
-{
-	char *e;
-	int i;
-	uint32_t gctrl;
-
-	/* If a signal is specified, print only that one */
-	if (argc > 2) {
-		i = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		if (!gpio_is_implemented(i))
-			return EC_ERROR_PARAM1;
-
-		gctrl = (uint32_t)strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		MCHP_GPIO_CTRL(i) = gctrl;
-		gctrl = MCHP_GPIO_CTRL(i);
-		ccprintf(" GPIO[0x%X].Ctrl = 0x%08X\n", i, gctrl);
-
-	} else {
-		ccprintf(" Requires two parameters: GPIO num and new config");
-	}
-	/* Flush console to avoid truncating output */
-	cflush();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(gpsetcfg, cmd_gp_set_config,
-			"gp_num val",
-			"Set GPIO config");
-
diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c
deleted file mode 100644
index 5234db8260..0000000000
--- a/chip/mchp/gpspi.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* General Purpose SPI master module for MCHP MEC */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-#include "spi_chip.h"
-#include "gpspi_chip.h"
-#include "tfdp_chip.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
-/* One byte at 12 MHz full duplex = 0.67 us */
-#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 20
-
-/*
- * GP-SPI
- */
-
-/**
- * Return zero based GPSPI controller index given hardware port.
- * @param hw_port b[7:4]==1 (GPSPI), b[3:0]=0(GPSPI0), 1(GPSPI1)
- * @return 0(GPSPI0) or 1(GPSPI1)
- */
-static uint8_t gpspi_port_to_ctrl_id(uint8_t hw_port)
-{
-	return (hw_port & 0x01);
-}
-
-static int gpspi_wait_byte(const int ctrl)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	while ((MCHP_SPI_SR(ctrl) & 0x3) != 0x3) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-/* NOTE: auto-read must be disabled before calling this routine! */
-static void gpspi_rx_fifo_clean(const int ctrl)
-{
-	uint8_t unused = 0;
-
-	/* If ACTIVE and/or RXFF then clean it */
-	if ((MCHP_SPI_SR(ctrl) & 0x4) == 0x4)
-		unused += MCHP_SPI_RD(ctrl);
-
-	if ((MCHP_SPI_SR(ctrl) & 0x2) == 0x2)
-		unused += MCHP_SPI_RD(ctrl);
-}
-/*
- * NOTE: auto-read must be disabled before calling this routine!
- */
-#ifndef CONFIG_MCHP_GPSPI_TX_DMA
-static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen)
-{
-	int i;
-	int ret;
-	uint8_t unused = 0;
-
-	gpspi_rx_fifo_clean(ctrl);
-
-	ret = EC_SUCCESS;
-	for (i = 0; i < txlen; ++i) {
-		MCHP_SPI_TD(ctrl) = txdata[i];
-		ret = gpspi_wait_byte(ctrl);
-		if (ret != EC_SUCCESS)
-			break;
-		unused += MCHP_SPI_RD(ctrl);
-	}
-
-	return ret;
-}
-#endif
-
-int gpspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
-{
-	int hw_port, ctrl;
-	int ret = EC_SUCCESS;
-	int cs_asserted = 0;
-	const struct dma_option *opdma;
-#ifdef CONFIG_MCHP_GPSPI_TX_DMA
-	dma_chan_t *chan;
-#endif
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-	hw_port = spi_device->port;
-
-	ctrl = gpspi_port_to_ctrl_id(hw_port);
-
-	/* Disable auto read */
-	MCHP_SPI_CR(ctrl) &= ~BIT(5);
-
-	if ((txdata != NULL) && (txdata != 0)) {
-#ifdef CONFIG_MCHP_GPSPI_TX_DMA
-		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_WR);
-		if (opdma == NULL)
-			return EC_ERROR_INVAL;
-
-		gpspi_rx_fifo_clean(ctrl);
-
-		dma_prepare_tx(opdma, txlen, txdata);
-
-		chan = dma_get_channel(opdma->channel);
-
-		gpio_set_level(spi_device->gpio_cs, 0);
-		cs_asserted = 1;
-
-		dma_go(chan);
-		ret = dma_wait(opdma->channel);
-		if (ret == EC_SUCCESS)
-			ret = gpspi_wait_byte(ctrl);
-
-		dma_disable(opdma->channel);
-		dma_clear_isr(opdma->channel);
-
-		gpspi_rx_fifo_clean(ctrl);
-#else
-		gpio_set_level(spi_device->gpio_cs, 0);
-		cs_asserted = 1;
-
-		ret = gpspi_tx(ctrl, txdata, txlen);
-#endif
-	}
-
-	if (ret == EC_SUCCESS)
-		if ((rxlen != 0) && (rxdata != NULL)) {
-			ret = EC_ERROR_INVAL;
-			opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-			if (opdma != NULL) {
-				if (!cs_asserted)
-					gpio_set_level(spi_device->gpio_cs, 0);
-				/* Enable auto read */
-				MCHP_SPI_CR(ctrl) |= BIT(5);
-				dma_start_rx(opdma, rxlen, rxdata);
-				MCHP_SPI_TD(ctrl) = 0;
-				ret = EC_SUCCESS;
-			}
-		}
-
-	return ret;
-}
-
-int gpspi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int ctrl, hw_port;
-	int ret;
-	enum dma_channel chan;
-	const struct dma_option *opdma;
-	timestamp_t deadline;
-
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-	hw_port = spi_device->port;
-	ctrl = gpspi_port_to_ctrl_id(hw_port);
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-	chan = opdma->channel;
-
-	ret = dma_wait(chan);
-
-	/* Disable auto read */
-	MCHP_SPI_CR(ctrl) &= ~BIT(5);
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	/* Wait for FIFO empty SPISR_TXBE */
-	while ((MCHP_SPI_SR(ctrl) & 0x01) != 0x1) {
-		if (timestamp_expired(deadline, NULL)) {
-			ret = EC_ERROR_TIMEOUT;
-			break;
-		}
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-
-	dma_disable(chan);
-	dma_clear_isr(chan);
-	if (MCHP_SPI_SR(ctrl) & 0x2)
-		hw_port = MCHP_SPI_RD(ctrl);
-
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return ret;
-}
-
-int gpspi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	const struct dma_option *opdma;
-
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-
-	return dma_wait(opdma->channel);
-}
-
-/**
- * Enable GPSPI controller and MODULE_SPI_CONTROLLER pins
- *
- * @param hw_port b[7:4]=1 b[3:0]=0(GPSPI0), 1(GPSPI1)
- * @param enable
- * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized
- * @note called from mec1701/spi.c
- *
- */
-int gpspi_enable(int hw_port, int enable)
-{
-	uint32_t ctrl;
-
-	if ((hw_port != GPSPI0_PORT) && (hw_port != GPSPI1_PORT))
-		return EC_ERROR_INVAL;
-
-	gpio_config_module(MODULE_SPI_CONTROLLER, (enable > 0));
-
-	ctrl = (uint32_t)hw_port & 0x0f;
-
-	if (enable) {
-
-		if (ctrl)
-			MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_GPSPI1);
-		else
-			MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_GPSPI0);
-
-		/* Set enable bit in SPI_AR */
-		MCHP_SPI_AR(ctrl) |= 0x1;
-
-		/* Set SPDIN to 0 -> Full duplex */
-		MCHP_SPI_CR(ctrl) &= ~(0x3 << 2);
-
-		/* Set CLKPOL, TCLKPH, RCLKPH to 0 */
-		MCHP_SPI_CC(ctrl) &= ~0x7;
-
-		/* Set LSBF to 0 -> MSB first */
-		MCHP_SPI_CR(ctrl) &= ~0x1;
-	} else {
-		/* soft reset */
-		MCHP_SPI_CR(ctrl) |= (1u << 4);
-
-		/* Clear enable bit in SPI_AR */
-		MCHP_SPI_AR(ctrl) &= ~0x1;
-
-		if (ctrl)
-			MCHP_PCR_SLP_EN_DEV(MCHP_PCR_GPSPI1);
-		else
-			MCHP_PCR_SLP_EN_DEV(MCHP_PCR_GPSPI0);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/mchp/gpspi_chip.h b/chip/mchp/gpspi_chip.h
deleted file mode 100644
index 529a727e36..0000000000
--- a/chip/mchp/gpspi_chip.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MCHP MEC processor
- */
-/** @file gpspi_chip.h
- *MCHP MEC General Purpose SPI Master
- */
-/** @defgroup MCHP MEC gpspi
- */
-
-#ifndef _GPSPI_CHIP_H
-#define _GPSPI_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-/* struct spi_device_t */
-#include "spi.h"
-
-int gpspi_transaction_flush(const struct spi_device_t *spi_device);
-
-int gpspi_transaction_wait(const struct spi_device_t *spi_device);
-
-int gpspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
-
-int gpspi_enable(int port, int enable);
-
-#endif /* #ifndef _GPSPI_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c
deleted file mode 100644
index e84f278f4a..0000000000
--- a/chip/mchp/hwtimer.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "tfdp_chip.h"
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) -
-			       (0xffffffff - deadline);
-	MCHP_TMR32_CTL(1) |= BIT(5);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return MCHP_TMR32_CNT(1) - MCHP_TMR32_CNT(0) + 0xffffffff;
-}
-
-void __hw_clock_event_clear(void)
-{
-	MCHP_TMR32_CTL(1) &= ~BIT(5);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return 0xffffffff - MCHP_TMR32_CNT(0);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	MCHP_TMR32_CTL(0) &= ~BIT(5);
-	MCHP_TMR32_CNT(0) = 0xffffffff - ts;
-	MCHP_TMR32_CTL(0) |= BIT(5);
-}
-
-/*
- * Always clear both timer and aggregator status
- */
-static void __hw_clock_source_irq(int timer_id)
-{
-	MCHP_TMR32_STS(timer_id & 0x01) |= 1;
-	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(timer_id & 0x01);
-
-	/* If IRQ is from timer 0, 32-bit timer overflowed */
-	process_timers(timer_id == 0);
-}
-
-void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
-DECLARE_IRQ(MCHP_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
-void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
-DECLARE_IRQ(MCHP_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
-
-static void configure_timer(int timer_id)
-{
-	uint32_t val;
-
-	/* Ensure timer is not running */
-	MCHP_TMR32_CTL(timer_id) &= ~BIT(5);
-
-	/* Enable timer */
-	MCHP_TMR32_CTL(timer_id) |= BIT(0);
-
-	val = MCHP_TMR32_CTL(timer_id);
-
-	/* Pre-scale = 48 -> 1MHz -> Period = 1us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MCHP_TMR32_CTL(timer_id) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MCHP_TMR32_PRE(timer_id) = 0xffffffff;
-
-	/* Enable interrupt */
-	MCHP_TMR32_IEN(timer_id) |= 1;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	MCHP_PCR_SLP_DIS_DEV_MASK(3, MCHP_PCR_SLP_EN3_BTMR32_0 +
-			MCHP_PCR_SLP_EN3_BTMR32_1);
-
-	/*
-	 * The timer can only fire interrupt when its value reaches zero.
-	 * Therefore we need two timers:
-	 *   - Timer 0 as free running timer
-	 *   - Timer 1 as event timer
-	 */
-	configure_timer(0);
-	configure_timer(1);
-
-	/* Override the count */
-	MCHP_TMR32_CNT(0) = 0xffffffff - start_t;
-
-	/* Auto restart */
-	MCHP_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MCHP_TMR32_CTL(0) |= BIT(5);
-
-	/* Enable interrupt */
-	task_enable_irq(MCHP_IRQ_TIMER32_0);
-	task_enable_irq(MCHP_IRQ_TIMER32_1);
-	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-	/*
-	 * Not needed when using direct mode interrupts
-	 * MCHP_INT_BLK_EN |= BIT(MCHP_TMR32_GIRQ);
-	 */
-	return MCHP_IRQ_TIMER32_1;
-}
diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c
deleted file mode 100644
index 9891f4d41e..0000000000
--- a/chip/mchp/i2c.c
+++ /dev/null
@@ -1,1096 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for MCHP MEC */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "i2c_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "tfdp_chip.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
-
-/*
- * MCHP I2C BAUD clock source is 16 MHz.
- */
-#define I2C_CLOCK			16000000UL
-#define MCHP_I2C_SUPPORTED_BUS_CLOCKS	6
-
-/* SMBus Timing values for 1MHz Speed */
-#define SPEED_1MHZ_BUS_CLOCK		0x0509ul
-#define SPEED_1MHZ_DATA_TIMING		0x06060601ul
-#define SPEED_1MHZ_DATA_TIMING_2	0x06ul
-#define SPEED_1MHZ_IDLE_SCALING		0x01000050ul
-#define SPEED_1MHZ_TIMEOUT_SCALING	0x149CC2C7ul
-/* SMBus Timing values for 400kHz speed */
-#define SPEED_400KHZ_BUS_CLOCK		0x0F17ul
-#define SPEED_400KHZ_DATA_TIMING	0x040A0F01ul
-#define SPEED_400KHZ_DATA_TIMING_2	0x0Aul
-#define SPEED_400KHZ_IDLE_SCALING	0x01000050ul
-#define SPEED_400KHZ_TIMEOUT_SCALING	0x149CC2C7ul
-/* SMBus Timing values for 100kHz speed */
-#define SPEED_100KHZ_BUS_CLOCK		0x4F4Ful
-#define SPEED_100KHZ_DATA_TIMING	0x0C4D4306ul
-#define SPEED_100KHZ_DATA_TIMING_2	0x4Dul
-#define SPEED_100KHZ_IDLE_SCALING	0x01FC01EDul
-#define SPEED_100KHZ_TIMEOUT_SCALING	0x4B9CC2C7ul
-/* Bus clock dividers for 333, 80, and 40 kHz */
-#define SPEED_333KHZ_BUS_CLOCK		0x0F1Ful
-#define SPEED_80KHZ_BUS_CLOCK		0x6363ul
-#define SPEED_40KHZ_BUS_CLOCK		0xC7C7ul
-
-/* Status */
-#define STS_NBB			BIT(0) /* Bus busy */
-#define STS_LAB			BIT(1) /* Arbitration lost */
-#define STS_LRB			BIT(3) /* Last received bit */
-#define STS_BER			BIT(4) /* Bus error */
-#define STS_PIN			BIT(7) /* Pending interrupt */
-/* Control */
-#define CTRL_ACK		BIT(0) /* Acknowledge */
-#define CTRL_STO		BIT(1) /* STOP */
-#define CTRL_STA		BIT(2) /* START */
-#define CTRL_ENI		BIT(3) /* Enable interrupt */
-#define CTRL_ESO		BIT(6) /* Enable serial output */
-#define CTRL_PIN		BIT(7) /* Pending interrupt not */
-/* Completion */
-#define COMP_DTEN		BIT(2) /* enable device timeouts */
-#define COMP_MCEN		BIT(3) /* enable ctrl. cumulative timeouts */
-#define COMP_SCEN		BIT(4) /* enable periph. cumulative timeouts */
-#define COMP_BIDEN		BIT(5) /* enable Bus idle timeouts */
-#define COMP_IDLE		BIT(29) /* i2c bus is idle */
-#define COMP_RW_BITS_MASK	0x3C /* R/W bits mask */
-/* Configuration */
-#define CFG_PORT_MASK		(0x0F) /* port selection field */
-#define CFG_TCEN		BIT(4) /* Enable HW bus timeouts */
-#define CFG_FEN			BIT(8) /* enable input filtering */
-#define CFG_RESET		BIT(9) /* reset controller */
-#define CFG_ENABLE		BIT(10) /* enable controller */
-#define CFG_GC_DIS		BIT(14) /* disable general call address */
-#define CFG_ENIDI		BIT(29) /* Enable I2C idle interrupt */
-/* Enable network layer controller done interrupt */
-#define CFG_ENMI		BIT(30)
-/* Enable network layer peripheral done interrupt */
-#define CFG_ENSI		BIT(31)
-/* Controller Command */
-#define MCMD_MRUN		BIT(0)
-#define MCMD_MPROCEED		BIT(1)
-#define MCMD_START0		BIT(8)
-#define MCMD_STARTN		BIT(9)
-#define MCMD_STOP		BIT(10)
-#define MCMD_READM		BIT(12)
-#define MCMD_WCNT_BITPOS	(16)
-#define MCMD_WCNT_MASK0		(0xFF)
-#define MCMD_WCNT_MASK		(0xFF << 16)
-#define MCMD_RCNT_BITPOS	(24)
-#define MCMD_RCNT_MASK0		(0xFF)
-#define MCMD_RCNT_MASK		(0xFF << 24)
-
-/* Maximum transfer of a SMBUS block transfer */
-#define SMBUS_MAX_BLOCK_SIZE 32
-/*
- * Amount of time to blocking wait for i2c bus to finish. After this
- * blocking timeout, if the bus is still not finished, then allow other
- * tasks to run.
- * Note: this is just long enough for a 400kHz bus to finish transmitting
- * one byte assuming the bus isn't being held.
- */
-#define I2C_WAIT_BLOCKING_TIMEOUT_US 25
-
-enum i2c_transaction_state {
-	/* Stop condition was sent in previous transaction */
-	I2C_TRANSACTION_STOPPED,
-	/* Stop condition was not sent in previous transaction */
-	I2C_TRANSACTION_OPEN,
-};
-
-/* I2C controller state data
- * NOTE: I2C_CONTROLLER_COUNT is defined at board level.
- */
-static struct {
-	/* Transaction timeout, or 0 to use default. */
-	uint32_t timeout_us;
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	/*
-	 * MCHP Remove volatile.
-	 * ISR only reads.
-	 * Non-ISR only writes when interrupt is disabled.
-	 */
-	task_id_t task_waiting;
-	enum i2c_transaction_state transaction_state;
-	/* transaction context */
-	int out_size;
-	const uint8_t *outp;
-	int in_size;
-	uint8_t *inp;
-	int xflags;
-	uint32_t i2c_complete; /* ISR write */
-	uint32_t flags;
-	uint8_t port;
-	uint8_t periph_addr_8bit;
-	uint8_t ctrl;
-	uint8_t hwsts;
-	uint8_t hwsts2;
-	uint8_t hwsts3; /* ISR write */
-	uint8_t hwsts4;
-	uint8_t lines;
-} cdata[I2C_CONTROLLER_COUNT];
-
-static const uint16_t i2c_ctrl_nvic_id[] = {
-	MCHP_IRQ_I2C_0, MCHP_IRQ_I2C_1, MCHP_IRQ_I2C_2, MCHP_IRQ_I2C_3,
-#if defined(CHIP_FAMILY_MEC172X)
-	MCHP_IRQ_I2C_4
-#elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_IRQ_I2C_4, MCHP_IRQ_I2C_5, MCHP_IRQ_I2C_6, MCHP_IRQ_I2C_7
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_nvic_id) == MCHP_I2C_CTRL_MAX);
-
-static const uint16_t i2c_controller_pcr[] = {
-	MCHP_PCR_I2C0, MCHP_PCR_I2C1, MCHP_PCR_I2C2, MCHP_PCR_I2C3,
-#if defined(CHIP_FAMILY_MEC172X)
-	MCHP_PCR_I2C4
-#elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_PCR_I2C4, MCHP_PCR_I2C5, MCHP_PCR_I2C6, MCHP_PCR_I2C7,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_controller_pcr) == MCHP_I2C_CTRL_MAX);
-
-static uintptr_t i2c_ctrl_base_addr[] = {
-	MCHP_I2C0_BASE, MCHP_I2C1_BASE, MCHP_I2C2_BASE, MCHP_I2C3_BASE,
-#if defined(CHIP_FAMILY_MEC172X)
-	MCHP_I2C4_BASE
-#elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_I2C4_BASE,
-	/* NOTE: 5-7 do not implement network layer hardware */
-	MCHP_I2C5_BASE, MCHP_I2C6_BASE, MCHP_I2C7_BASE
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_base_addr) == MCHP_I2C_CTRL_MAX);
-
-static bool chip_i2c_is_controller_valid(int controller)
-{
-	if ((controller < 0) || (controller >= MCHP_I2C_CTRL_MAX))
-		return false;
-	return true;
-}
-
-static uintptr_t chip_i2c_ctrl_base(int controller)
-{
-	if (!chip_i2c_is_controller_valid(controller))
-		return 0;
-
-	return i2c_ctrl_base_addr[controller];
-}
-
-static uint32_t chip_i2c_ctrl_nvic_id(int controller)
-{
-	if (!chip_i2c_is_controller_valid(controller))
-		return 0;
-
-	return (uint32_t)i2c_ctrl_nvic_id[controller];
-}
-
-static void i2c_ctrl_slp_en(int controller, int sleep_en)
-{
-	if (!chip_i2c_is_controller_valid(controller))
-		return;
-	if (sleep_en)
-		MCHP_PCR_SLP_EN_DEV(i2c_controller_pcr[controller]);
-	else
-		MCHP_PCR_SLP_DIS_DEV(i2c_controller_pcr[controller]);
-}
-
-uint32_t chip_i2c_get_ctx_flags(int port)
-{
-	int controller = i2c_port_to_controller(port);
-
-	if (!chip_i2c_is_controller_valid(controller))
-		return 0;
-	return cdata[controller].flags;
-}
-
-/*
- * MCHP I2C controller tuned bus clock values.
- * MCHP I2C_SMB_Controller_3.6.pdf Table 6-3
- */
-struct i2c_bus_clk {
-	int freq_khz;
-	int bus_clk;
-};
-
-const struct i2c_bus_clk i2c_freq_tbl[] = {
-	{ 40, SPEED_40KHZ_BUS_CLOCK }, { 80, SPEED_80KHZ_BUS_CLOCK },
-	{ 100, SPEED_100KHZ_BUS_CLOCK }, { 333, SPEED_333KHZ_BUS_CLOCK },
-	{ 400, SPEED_400KHZ_BUS_CLOCK }, { 1000, SPEED_1MHZ_BUS_CLOCK },
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_freq_tbl) == MCHP_I2C_SUPPORTED_BUS_CLOCKS);
-
-/* I2C controller assignment to a port */
-static int i2c_p2c[MCHP_I2C_PORT_COUNT];
-
-static int get_closest(int lesser, int greater, int target)
-{
-	if (target - i2c_freq_tbl[lesser].freq_khz >=
-	    i2c_freq_tbl[greater].freq_khz - target)
-		return greater;
-	else
-		return lesser;
-}
-
-/*
- * Return index in i2c_freq_tbl of supported frequencies
- * closest to requested frequency.
- */
-static const struct i2c_bus_clk *get_supported_speed_idx(int req_kbps)
-{
-	int i, limit, m, imax;
-
-	if (req_kbps <= i2c_freq_tbl[0].freq_khz)
-		return &i2c_freq_tbl[0];
-
-	imax = ARRAY_SIZE(i2c_freq_tbl);
-	if (req_kbps >= i2c_freq_tbl[imax - 1].freq_khz)
-		return &i2c_freq_tbl[imax - 1];
-
-	/* we only get here if ARRAY_SIZE(...) > 1
-	 * and req_kbps is in range.
-	 */
-	i = 0;
-	limit = imax;
-	while (i < limit) {
-		m = (i + limit) / 2;
-		if (i2c_freq_tbl[m].freq_khz == req_kbps)
-			break;
-
-		if (req_kbps < i2c_freq_tbl[m].freq_khz) {
-			if (m > 0 && req_kbps > i2c_freq_tbl[m - 1].freq_khz) {
-				m = get_closest(m - 1, m, req_kbps);
-				break;
-			}
-			limit = m;
-		} else {
-			if (m < imax - 1 &&
-			    req_kbps < i2c_freq_tbl[m + 1].freq_khz) {
-				m = get_closest(m, m + 1, req_kbps);
-				break;
-			}
-			i = m + 1;
-		}
-	}
-
-	return &i2c_freq_tbl[m];
-}
-
-/*
- * Refer to NXP UM10204 for minimum timing requirement of T_Low and T_High.
- * http://www.nxp.com/documents/user_manual/UM10204.pdf
- * I2C spec. timing value are used in recommended registers values
- * in MCHP I2C_SMB_Controller_3.6.pdf
- * Restrict frequencies to those in the above MCHP spec.
- * 40, 80, 100, 333, 400, and 1000 kHz.
- */
-static void configure_controller_speed(int controller, int kbps)
-{
-	const struct i2c_bus_clk *p;
-	uintptr_t raddr;
-
-	raddr = chip_i2c_ctrl_base(controller);
-
-	p = get_supported_speed_idx(kbps);
-	MCHP_I2C_BUS_CLK(raddr) = p->bus_clk;
-
-	if (p->freq_khz > 400) { /* Fast mode plus */
-		MCHP_I2C_DATA_TIM(raddr) = SPEED_1MHZ_DATA_TIMING;
-		MCHP_I2C_DATA_TIM_2(raddr) = SPEED_1MHZ_DATA_TIMING_2;
-		MCHP_I2C_IDLE_SCALE(raddr) = SPEED_1MHZ_IDLE_SCALING;
-		MCHP_I2C_TOUT_SCALE(raddr) = SPEED_1MHZ_TIMEOUT_SCALING;
-	} else if (p->freq_khz > 100) { /* Fast mode */
-		MCHP_I2C_DATA_TIM(raddr) = SPEED_400KHZ_DATA_TIMING;
-		MCHP_I2C_DATA_TIM_2(raddr) = SPEED_400KHZ_DATA_TIMING_2;
-		MCHP_I2C_IDLE_SCALE(raddr) = SPEED_400KHZ_IDLE_SCALING;
-		MCHP_I2C_TOUT_SCALE(raddr) = SPEED_400KHZ_TIMEOUT_SCALING;
-	} else { /* Standard mode */
-		MCHP_I2C_DATA_TIM(raddr) = SPEED_100KHZ_DATA_TIMING;
-		MCHP_I2C_DATA_TIM_2(raddr) = SPEED_100KHZ_DATA_TIMING_2;
-		MCHP_I2C_IDLE_SCALE(raddr) = SPEED_100KHZ_IDLE_SCALING;
-		MCHP_I2C_TOUT_SCALE(raddr) = SPEED_100KHZ_TIMEOUT_SCALING;
-	}
-}
-
-/*
- * NOTE: direct mode interrupts do not need GIRQn bit
- * set in aggregator block enable register.
- */
-static void enable_controller_irq(int controller)
-{
-	uint32_t nvic_id = chip_i2c_ctrl_nvic_id(controller);
-
-	MCHP_INT_ENABLE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
-	task_enable_irq(nvic_id);
-}
-
-static void disable_controller_irq(int controller)
-{
-	uint32_t nvic_id = chip_i2c_ctrl_nvic_id(controller);
-
-	MCHP_INT_DISABLE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
-	/* read back into read-only reg. to insure disable takes effect */
-	MCHP_INT_BLK_IRQ = MCHP_INT_DISABLE(MCHP_I2C_GIRQ);
-	task_disable_irq(nvic_id);
-	task_clear_pending_irq(nvic_id);
-}
-
-/*
- * Do NOT enable controller's IDLE interrupt in the configuration
- * register. IDLE is meant for multi-controller and controller acting
- * as a peripheral.
- */
-static void configure_controller(int controller, int port, int kbps)
-{
-	uintptr_t raddr = chip_i2c_ctrl_base(controller);
-
-	if (raddr == 0)
-		return;
-
-	disable_controller_irq(controller);
-	MCHP_INT_SOURCE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
-
-	/* set to default except for port select field b[3:0] */
-	MCHP_I2C_CONFIG(raddr) = (uint32_t)(port & 0xf);
-	MCHP_I2C_CTRL(raddr) = CTRL_PIN;
-
-	/* Set both controller peripheral addresses to 0 the
-	 * general call address. We disable general call
-	 * below.
-	 */
-	MCHP_I2C_OWN_ADDR(raddr) = 0;
-
-	configure_controller_speed(controller, kbps);
-
-	/* Controller timings done, clear RO status, enable
-	 * output, and ACK generation.
-	 */
-	MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_ACK;
-
-	/* filter enable, disable General Call */
-	MCHP_I2C_CONFIG(raddr) |= CFG_FEN + CFG_GC_DIS;
-	/* enable controller */
-	MCHP_I2C_CONFIG(raddr) |= CFG_ENABLE;
-}
-
-static void reset_controller(int controller)
-{
-	int i;
-	uintptr_t raddr;
-
-	raddr = chip_i2c_ctrl_base(controller);
-	if (raddr == 0)
-		return;
-
-	/* Reset asserted for at least one AHB clock */
-	MCHP_I2C_CONFIG(raddr) |= BIT(9);
-	MCHP_EC_ID_RO = 0;
-	MCHP_I2C_CONFIG(raddr) &= ~BIT(9);
-
-	for (i = 0; i < i2c_ports_used; ++i)
-		if (controller == i2c_port_to_controller(i2c_ports[i].port)) {
-			configure_controller(controller, i2c_ports[i].port,
-					     i2c_ports[i].kbps);
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-			break;
-		}
-}
-
-/*
- * !!! WARNING !!!
- * We have observed task_wait_event_mask() returning 0 if the I2C
- * controller IDLE interrupt is enabled. We believe it is due to the ISR
- * post multiple events too quickly but don't have absolute proof.
- */
-static int wait_for_interrupt(int controller, int timeout)
-{
-	int event;
-
-	if (timeout <= 0)
-		return EC_ERROR_TIMEOUT;
-
-	cdata[controller].task_waiting = task_get_current();
-	enable_controller_irq(controller);
-
-	/* Wait until I2C interrupt or timeout. */
-	event = task_wait_event_mask(TASK_EVENT_I2C_IDLE, timeout);
-
-	disable_controller_irq(controller);
-	cdata[controller].task_waiting = TASK_ID_INVALID;
-
-	return (event & TASK_EVENT_TIMER) ? EC_ERROR_TIMEOUT : EC_SUCCESS;
-}
-
-static int wait_idle(int controller)
-{
-	uintptr_t raddr = chip_i2c_ctrl_base(controller);
-	uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	uint64_t task_timeout = block_timeout + cdata[controller].timeout_us;
-	int rv = 0;
-	uint8_t sts = MCHP_I2C_STATUS(raddr);
-
-	while (!(sts & STS_NBB)) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout)
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		sts = MCHP_I2C_STATUS(raddr);
-	}
-
-	if (sts & (STS_BER | STS_LAB))
-		return EC_ERROR_UNKNOWN;
-	return EC_SUCCESS;
-}
-
-/*
- * Return EC_SUCCESS on ACK of byte else EC_ERROR_UNKNOWN.
- * Record I2C.Status in cdata[controller] structure.
- * Byte transmit finished with no I2C bus error or lost arbitration.
- *	PIN -> 0. LRB bit contains peripheral ACK/NACK bit.
- *	Peripheral ACK:  I2C.Status == 0x00
- *	Peripheral NACK: I2C.Status == 0x08
- * Byte transmit finished with I2C bus errors or lost arbitration.
- *	PIN -> 0 and BER and/or LAB set.
- *
- * Byte receive finished with no I2C bus errors or lost arbitration.
- *	PIN -> 0. LRB=0/1 based on ACK bit in I2C.Control.
- *	Controller receiver must NACK last byte it wants to receive.
- *	How do we handle this if we don't know direction of transfer?
- *	I2C.Control is write-only so we can't see Controller's ACK control
- *	bit.
- */
-static int wait_byte_done(int controller, uint8_t mask, uint8_t expected)
-{
-	uint64_t block_timeout;
-	uint64_t task_timeout;
-	uintptr_t raddr;
-	int rv;
-	uint8_t sts;
-
-	rv = 0;
-	raddr = chip_i2c_ctrl_base(controller);
-	block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	task_timeout = block_timeout + cdata[controller].timeout_us;
-	sts = MCHP_I2C_STATUS(raddr);
-	cdata[controller].hwsts = sts;
-	while (sts & STS_PIN) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout) {
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		}
-		sts = MCHP_I2C_STATUS(raddr);
-		cdata[controller].hwsts = sts;
-	}
-
-	rv = EC_SUCCESS;
-	if ((sts & mask) != expected)
-		rv = EC_ERROR_UNKNOWN;
-	return rv;
-}
-
-/*
- * Select port on controller. If controller configured
- * for port do nothing.
- * Switch port by reset and reconfigure to handle cases where
- * the peripheral on current port is driving line(s) low.
- * NOTE: I2C hardware reset only requires one AHB clock, back to back
- * writes is OK but we added an extra write as insurance.
- */
-static void select_port(int port, int controller)
-{
-	uint32_t port_sel;
-	uintptr_t raddr;
-
-	raddr = chip_i2c_ctrl_base(controller);
-	port_sel = (uint32_t)(port & 0x0f);
-	if ((MCHP_I2C_CONFIG(raddr) & 0x0f) == port_sel)
-		return;
-
-	MCHP_I2C_CONFIG(raddr) |= BIT(9);
-	MCHP_EC_ID_RO = 0; /* extra write to read-only as delay */
-	MCHP_I2C_CONFIG(raddr) &= ~BIT(9);
-	configure_controller(controller, port_sel, i2c_ports[port].kbps);
-}
-
-/*
- * Use safe method (reading GPIO.Control PAD input bit)
- * to obtain SCL line state in bit[0] and SDA line state in bit[1].
- * NOTE: I2C controller bit-bang register is not safe. Using
- * bit-bang requires timeouts be disabled and the controller in an
- * idle state. Switching controller to bit-bang mode when the controller
- * is not idle will cause problems.
- */
-static uint32_t get_line_level(int port)
-{
-	uint32_t lines;
-
-	lines = i2c_raw_get_scl(port) & 0x01;
-	lines |= (i2c_raw_get_sda(port) & 0x01) << 1;
-	return lines;
-}
-
-/*
- * Check if I2C port connected to controller has bus error or
- * other issues such as stuck clock/data lines.
- */
-static int i2c_check_recover(int port, int controller)
-{
-	uintptr_t raddr;
-	uint32_t lines;
-	uint8_t reg;
-
-	raddr = chip_i2c_ctrl_base(controller);
-	lines = get_line_level(port);
-	reg = MCHP_I2C_STATUS(raddr);
-
-	if ((((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) ||
-	     (lines != I2C_LINE_IDLE))) {
-		cdata[controller].flags |= (1ul << 16);
-		CPRINTS("I2C%d port%d recov status 0x%02x, SDA:SCL=0x%0x",
-			controller, port, reg, lines);
-		/* Attempt to unwedge the port. */
-		if (lines != I2C_LINE_IDLE)
-			if (i2c_unwedge(port))
-				return EC_ERROR_UNKNOWN;
-
-		/* Bus error, bus busy, or arbitration lost. Try reset. */
-		reset_controller(controller);
-		select_port(port, controller);
-		/*
-		 * We don't know what edges the peripheral saw, so sleep long
-		 * enough that the peripheral will see the new start condition
-		 * below.
-		 */
-		usleep(1000);
-		reg = MCHP_I2C_STATUS(raddr);
-		lines = get_line_level(port);
-		if ((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB) ||
-		    (lines != I2C_LINE_IDLE))
-			return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static inline void push_in_buf(uint8_t **in, uint8_t val, int skip)
-{
-	if (!skip) {
-		**in = val;
-		(*in)++;
-	}
-}
-
-/*
- * I2C Controller transmit
- * Caller has filled in cdata[ctrl] parameters
- */
-static int i2c_mtx(int ctrl)
-{
-	uintptr_t raddr;
-	int i, rv;
-
-	raddr = chip_i2c_ctrl_base(ctrl);
-	rv = EC_SUCCESS;
-	cdata[ctrl].flags |= (1ul << 1);
-	if (cdata[ctrl].xflags & I2C_XFER_START) {
-		cdata[ctrl].flags |= (1ul << 2);
-		MCHP_I2C_DATA(raddr) = cdata[ctrl].periph_addr_8bit;
-		/* Clock out the peripheral address, sending START bit */
-		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
-				       CTRL_ACK | CTRL_STA;
-		cdata[ctrl].transaction_state = I2C_TRANSACTION_OPEN;
-	}
-
-	for (i = 0; i < cdata[ctrl].out_size; ++i) {
-		rv = wait_byte_done(ctrl, 0xff, 0x00);
-		if (rv) {
-			cdata[ctrl].flags |= (1ul << 17);
-			MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
-					      CTRL_STO | CTRL_ACK;
-			return rv;
-		}
-		cdata[ctrl].flags |= (1ul << 15);
-		MCHP_I2C_DATA(raddr) = cdata[ctrl].outp[i];
-	}
-
-	rv = wait_byte_done(ctrl, 0xff, 0x00);
-	if (rv) {
-		cdata[ctrl].flags |= (1ul << 18);
-		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
-				       CTRL_STO | CTRL_ACK;
-		return rv;
-	}
-
-	/*
-	 * Send STOP bit if the stop flag is on, and caller
-	 * doesn't expect to receive data.
-	 */
-	if ((cdata[ctrl].xflags & I2C_XFER_STOP) &&
-	    (cdata[ctrl].in_size == 0)) {
-		cdata[ctrl].flags |= (1ul << 3);
-		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO |
-				       CTRL_ACK;
-		cdata[ctrl].transaction_state = I2C_TRANSACTION_STOPPED;
-	}
-	return rv;
-}
-
-/*
- * I2C Controller-Receive helper routine for sending START or
- * Repeated-START.
- * This routine should only be called if a (Repeated-)START
- * is required.
- * If I2C controller is Idle or Stopped
- *   Send START by:
- *	Write read address to I2C.Data
- *	Write PIN=ESO=STA=ACK=1, STO=0 to I2C.Ctrl. This
- *	will trigger controller to output 8-bits of data.
- * Else if I2C controller is Open (previous START sent)
- *   Send Repeated-START by:
- *	Write ESO=STA=ACK=1, PIN=STO=0 to I2C.Ctrl. Controller
- *	will generate START but not transmit data.
- *	Write read address to I2C.Data. Controller will transmit
- *	8-bits of data
- * NOTE: Controller clocks in address on SDA as its transmitting.
- * Therefore 1-byte RX-FIFO will contain address plus R/nW bit.
- * Controller will wait for peripheral to release SCL before transmitting
- * 9th clock and latching (N)ACK on SDA.
- * Spin on I2C.Status PIN -> 0. Enable I2C interrupt if spin time
- * exceeds threshold. If a timeout occurs generate STOP and return
- * an error.
- *
- * Because I2C generates clocks for next byte when reading I2C.Data
- * register we must prepare control logic.
- * If the caller requests STOP and read length is 1 then set
- * clear ACK bit in I2C.Ctrl. Set ESO=ENI=1, PIN=STA=STO=ACK=0
- * in I2C.Ctrl. Controller must NACK last byte.
- */
-static int i2c_mrx_start(int ctrl)
-{
-	uintptr_t raddr;
-	int rv;
-	uint8_t u8;
-
-	raddr = chip_i2c_ctrl_base(ctrl);
-
-	cdata[ctrl].flags |= (1ul << 4);
-	u8 = CTRL_ESO | CTRL_ENI | CTRL_STA | CTRL_ACK;
-	if (cdata[ctrl].transaction_state == I2C_TRANSACTION_OPEN) {
-		cdata[ctrl].flags |= (1ul << 5);
-		/* Repeated-START then address */
-		MCHP_I2C_CTRL(raddr) = u8;
-	}
-	MCHP_I2C_DATA(raddr) = cdata[ctrl].periph_addr_8bit | 0x01;
-	if (cdata[ctrl].transaction_state == I2C_TRANSACTION_STOPPED) {
-		cdata[ctrl].flags |= (1ul << 6);
-		/* address then START */
-		MCHP_I2C_CTRL(raddr) = u8 | CTRL_PIN;
-	}
-	cdata[ctrl].transaction_state = I2C_TRANSACTION_OPEN;
-	/* Controller generates START, transmits data(address) capturing
-	 * 9-bits from SDA (8-bit address + (N)Ack bit).
-	 * We leave captured address in I2C.Data register.
-	 * Controller receive data read routine assumes data is pending
-	 * in I2C.Data
-	 */
-	cdata[ctrl].flags |= (1ul << 7);
-	rv = wait_byte_done(ctrl, 0xff, 0x00);
-	if (rv) {
-		cdata[ctrl].flags |= (1ul << 19);
-		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO |
-				       CTRL_ACK;
-		return rv;
-	}
-	/* if STOP requested and last 1 or 2 bytes prepare controller
-	 * to NACK last byte. Do this before read of extra data so
-	 * controller is setup to NACK last byte.
-	 */
-	cdata[ctrl].flags |= (1ul << 8);
-	if (cdata[ctrl].xflags & I2C_XFER_STOP && (cdata[ctrl].in_size < 2)) {
-		cdata[ctrl].flags |= (1ul << 9);
-		MCHP_I2C_CTRL(raddr) = CTRL_ESO | CTRL_ENI;
-	}
-	/*
-	 * Read & discard peripheral address.
-	 * Generates clocks for next data
-	 */
-	cdata[ctrl].flags |= (1ul << 10);
-	u8 = MCHP_I2C_DATA(raddr);
-	return rv;
-}
-/*
- * I2C Controller-Receive data read helper.
- * Assumes I2C is in use, (Rpt-)START was previously sent.
- * Reading I2C.Data generates clocks for the next byte. If caller
- * requests STOP then we must clear I2C.Ctrl ACK before reading
- * second to last byte from RX-FIFO data register. Before reading
- * the last byte we must set I2C.Ctrl to generate a stop after
- * the read from RX-FIFO register.
- * NOTE: I2C.Status.LRB only records the (N)ACK bit in controller
- * transmit mode, not in controller receive mode.
- * NOTE2: Do not set ENI bit in I2C.Ctrl for STOP generation.
- */
-static int i2c_mrx_data(int ctrl)
-{
-	uint32_t nrx = (uint32_t)cdata[ctrl].in_size;
-	uint32_t stop = (uint32_t)cdata[ctrl].xflags & I2C_XFER_STOP;
-	uint8_t *pdest = cdata[ctrl].inp;
-	int rv;
-	uintptr_t raddr;
-
-	raddr = chip_i2c_ctrl_base(ctrl);
-
-	cdata[ctrl].flags |= (1ul << 11);
-	while (nrx) {
-		rv = wait_byte_done(ctrl, 0xff, 0x00);
-		if (rv) {
-			cdata[ctrl].flags |= (1ul << 20);
-			MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO |
-					       CTRL_ACK;
-			return rv;
-		}
-		if (stop) {
-			if (nrx == 2) {
-				cdata[ctrl].flags |= (1ul << 12);
-				MCHP_I2C_CTRL(raddr) = CTRL_ESO | CTRL_ENI;
-			} else if (nrx == 1) {
-				cdata[ctrl].flags |= (1ul << 13);
-				MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO |
-						       CTRL_STO | CTRL_ACK;
-			}
-		}
-		*pdest++ = MCHP_I2C_DATA(raddr);
-		nrx--;
-	}
-	cdata[ctrl].flags |= (1ul << 14);
-	return EC_SUCCESS;
-}
-
-/*
- * Called from common I2C
- */
-int chip_i2c_xfer(int port, uint16_t periph_addr_flags, const uint8_t *out,
-		  int out_size, uint8_t *in, int in_size, int flags)
-{
-	int ctrl;
-	int ret_done;
-	uintptr_t raddr;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	ctrl = i2c_port_to_controller(port);
-	if (ctrl < 0)
-		return EC_ERROR_INVAL;
-
-	raddr = chip_i2c_ctrl_base(ctrl);
-	if (raddr == 0)
-		return EC_ERROR_INVAL;
-
-	cdata[ctrl].flags = (1ul << 0);
-	disable_controller_irq(ctrl);
-	select_port(port, ctrl);
-
-	/* store transfer context */
-	cdata[ctrl].i2c_complete = 0;
-	cdata[ctrl].hwsts = 0;
-	cdata[ctrl].hwsts2 = 0;
-	cdata[ctrl].hwsts3 = 0;
-	cdata[ctrl].hwsts4 = 0;
-	cdata[ctrl].port = port & 0xff;
-	cdata[ctrl].periph_addr_8bit = I2C_STRIP_FLAGS(periph_addr_flags) << 1;
-	cdata[ctrl].out_size = out_size;
-	cdata[ctrl].outp = out;
-	cdata[ctrl].in_size = in_size;
-	cdata[ctrl].inp = in;
-	cdata[ctrl].xflags = flags;
-
-	if ((flags & I2C_XFER_START) &&
-	    cdata[ctrl].transaction_state == I2C_TRANSACTION_STOPPED) {
-		wait_idle(ctrl);
-		ret_done = i2c_check_recover(port, ctrl);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-	}
-
-	ret_done = EC_SUCCESS;
-	if (out_size) {
-		ret_done = i2c_mtx(ctrl);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-	}
-
-	if (in_size) {
-		if (cdata[ctrl].xflags & I2C_XFER_START) {
-			ret_done = i2c_mrx_start(ctrl);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-		}
-		ret_done = i2c_mrx_data(ctrl);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-	}
-
-	cdata[ctrl].flags |= (1ul << 15);
-	/* MCHP wait for STOP to complete */
-	if (cdata[ctrl].xflags & I2C_XFER_STOP)
-		wait_idle(ctrl);
-
-	/* Check for error conditions */
-	if (MCHP_I2C_STATUS(raddr) & (STS_LAB | STS_BER)) {
-		cdata[ctrl].flags |= (1ul << 21);
-		goto err_chip_i2c_xfer;
-	}
-	cdata[ctrl].flags |= (1ul << 14);
-	return EC_SUCCESS;
-
-err_chip_i2c_xfer:
-	cdata[ctrl].flags |= (1ul << 22);
-	cdata[ctrl].hwsts2 = MCHP_I2C_STATUS(raddr); /* record status */
-	/* NOTE: writing I2C.Ctrl.PIN=1 will clear all bits
-	 * except NBB in I2C.Status
-	 */
-	MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO | CTRL_ACK;
-	cdata[ctrl].transaction_state = I2C_TRANSACTION_STOPPED;
-	/* record status after STOP */
-	cdata[ctrl].hwsts4 = MCHP_I2C_STATUS(raddr);
-
-	/* record line levels.
-	 * Note line levels may reflect STOP condition
-	 */
-	cdata[ctrl].lines = (uint8_t)get_line_level(cdata[ctrl].port);
-	if (cdata[ctrl].hwsts2 & STS_BER) {
-		cdata[ctrl].flags |= (1ul << 23);
-		reset_controller(ctrl);
-	}
-	return EC_ERROR_UNKNOWN;
-}
-/*
- * A safe method of reading port's SCL pin level.
- */
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SCL pin defined for this port,
-	 * then return 1 to appear idle.
-	 */
-	if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-	return gpio_get_level(g);
-}
-
-/*
- * A safe method of reading port's SDA pin level.
- */
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SDA pin defined for this port,
-	 * then return 1 to appear idle.
-	 */
-	if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-	return gpio_get_level(g);
-}
-
-/*
- * Caller is responsible for locking the port.
- */
-int i2c_get_line_levels(int port)
-{
-	int rv, controller;
-
-	controller = i2c_port_to_controller(port);
-	if (controller < 0)
-		return 0x03; /* No controller, return high line levels */
-
-	select_port(port, controller);
-	rv = get_line_level(port);
-	return rv;
-}
-
-/*
- * this function returns the controller for I2C
- * return mod of MCHP_I2C_CTRL_MAX
- */
-__overridable int board_i2c_p2c(int port)
-{
-	if (port < 0 || port >= I2C_PORT_COUNT)
-		return -1;
-	return i2c_p2c[port];
-}
-
-/*
- * I2C port must be a zero based number.
- * MCHP I2C can map any port to any of the 4 controllers.
- * Call board level function as board designs may choose
- * to wire up and group ports differently.
- */
-int i2c_port_to_controller(int port)
-{
-	return board_i2c_p2c(port);
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	/* Parameter is port, but timeout is stored by-controller. */
-	cdata[i2c_port_to_controller(port)].timeout_us =
-		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-/*
- * Initialize I2C controllers specified by the board configuration.
- * If multiple ports are mapped to the same controller choose the
- * lowest speed.
- */
-void i2c_init(void)
-{
-	int i, controller, kbps;
-	int controller_kbps[MCHP_I2C_CTRL_MAX];
-	const struct i2c_bus_clk *pbc;
-
-	for (i = 0; i < MCHP_I2C_CTRL_MAX; i++)
-		controller_kbps[i] = 0;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	memset(cdata, 0, sizeof(cdata));
-
-	for (i = 0; i < i2c_ports_used; ++i) {
-		/* Assign I2C controller to I2C port */
-		i2c_p2c[i2c_ports[i].port] = i % MCHP_I2C_CTRL_MAX;
-
-		controller = i2c_port_to_controller(i2c_ports[i].port);
-		kbps = i2c_ports[i].kbps;
-
-		/* Clear PCR sleep enable for controller */
-		i2c_ctrl_slp_en(controller, 0);
-
-		if (controller_kbps[controller] &&
-		    (controller_kbps[controller] != kbps)) {
-			CPRINTF("I2C[%d] init speed conflict: %d != %d\n",
-				controller, kbps, controller_kbps[controller]);
-			kbps = MIN(kbps, controller_kbps[controller]);
-		}
-
-		/* controller speed hardware limits */
-		pbc = get_supported_speed_idx(kbps);
-		if (pbc->freq_khz != kbps)
-			CPRINTF("I2C[%d] init requested speed %d"
-				" using closest supported speed %d\n",
-				controller, kbps, pbc->freq_khz);
-
-		controller_kbps[controller] = pbc->freq_khz;
-		configure_controller(controller, i2c_ports[i].port,
-				     controller_kbps[controller]);
-		cdata[controller].task_waiting = TASK_ID_INVALID;
-		cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
-		/* Use default timeout. */
-		i2c_set_timeout(i2c_ports[i].port, 0);
-	}
-}
-
-/*
- * Handle I2C interrupts.
- * I2C controller is configured to fire interrupts on
- * anything causing PIN 1->0 and I2C IDLE (NBB -> 1).
- * NVIC interrupt disable must clear NVIC pending bit.
- */
-static void handle_interrupt(int controller)
-{
-	uint32_t r;
-	int id = cdata[controller].task_waiting;
-	uintptr_t raddr = chip_i2c_ctrl_base(controller);
-
-	/*
-	 * Write to control register interferes with I2C transaction.
-	 * Instead, let's disable IRQ from the core until the next time
-	 * we want to wait for STS_PIN/STS_NBB.
-	 */
-	disable_controller_irq(controller);
-	cdata[controller].hwsts3 = MCHP_I2C_STATUS(raddr);
-	/* Clear all interrupt status */
-	r = MCHP_I2C_COMPLETE(raddr);
-	MCHP_I2C_COMPLETE(raddr) = r;
-	cdata[controller].i2c_complete = r;
-	MCHP_INT_SOURCE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
-
-	/* Wake up the task which was waiting on the I2C interrupt, if any. */
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_I2C_IDLE);
-}
-
-void i2c0_interrupt(void)
-{
-	handle_interrupt(0);
-}
-void i2c1_interrupt(void)
-{
-	handle_interrupt(1);
-}
-void i2c2_interrupt(void)
-{
-	handle_interrupt(2);
-}
-void i2c3_interrupt(void)
-{
-	handle_interrupt(3);
-}
-#if defined(CHIP_FAMILY_MEC172X)
-void i2c4_interrupt(void)
-{
-	handle_interrupt(4);
-}
-#elif defined(CHIP_FAMILY_MEC152X)
-void i2c4_interrupt(void)
-{
-	handle_interrupt(4);
-}
-void i2c5_interrupt(void)
-{
-	handle_interrupt(5);
-}
-void i2c6_interrupt(void)
-{
-	handle_interrupt(6);
-}
-void i2c7_interrupt(void)
-{
-	handle_interrupt(7);
-}
-#endif
-
-DECLARE_IRQ(MCHP_IRQ_I2C_0, i2c0_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_1, i2c1_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_2, i2c2_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_3, i2c3_interrupt, 2);
-#if defined(CHIP_FAMILY_MEC172X)
-DECLARE_IRQ(MCHP_IRQ_I2C_4, i2c4_interrupt, 2);
-#elif defined(CHIP_FAMILY_MEC152X)
-DECLARE_IRQ(MCHP_IRQ_I2C_4, i2c4_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_5, i2c5_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_6, i2c6_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_7, i2c7_interrupt, 2);
-#endif
diff --git a/chip/mchp/i2c_chip.h b/chip/mchp/i2c_chip.h
deleted file mode 100644
index c8ceb98d04..0000000000
--- a/chip/mchp/i2c_chip.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MCHP-specific I2C module for Chrome EC */
-
-#ifndef _I2C_CHIP_H
-#define _I2C_CHIP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Place any C interfaces here */
-
-/*
- * Function returns the controller for I2C.
- *
- * Default function assigns controller for I2C port with modulo operation. If
- * the I2C ports used are greater than MCHP_I2C_CTRL_MAX, then I2C ports will
- * share the controller. Typically Type-C chips need individual controller per
- * port because of heavy I2C transactions. Hence, define a board specific
- * controller assignment when the I2C ports used are greater than
- * MCHP_I2C_CTRL_MAX.
- */
-__override_proto int board_i2c_p2c(int port);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _I2C_CHIP_H */
diff --git a/chip/mchp/keyboard_raw.c b/chip/mchp/keyboard_raw.c
deleted file mode 100644
index 946ea1ca90..0000000000
--- a/chip/mchp/keyboard_raw.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for MCHP MEC
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-/*
- * Using direct mode interrupt, do not enable
- * GIRQ bit in aggregator block enable register.
- */
-void keyboard_raw_init(void)
-{
-	/* clear key scan PCR sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_KEYSCAN);
-
-	keyboard_raw_enable_interrupt(0);
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
-
-	/* Enable keyboard scan interrupt */
-	MCHP_INT_ENABLE(MCHP_KS_GIRQ) = MCHP_KS_GIRQ_BIT;
-	MCHP_KS_KSI_INT_EN = 0xff;
-}
-
-void keyboard_raw_task_start(void)
-{
-	task_enable_irq(MCHP_IRQ_KSC_INT);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	if (out == KEYBOARD_COLUMN_ALL) {
-		MCHP_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 1);
-#endif
-	} else if (out == KEYBOARD_COLUMN_NONE) {
-		MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 0);
-#endif
-	} else {
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		if (out == 2) {
-			MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-			gpio_set_level(GPIO_KBD_KSO2, 1);
-		} else {
-			MCHP_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-			gpio_set_level(GPIO_KBD_KSO2, 0);
-		}
-#else
-		MCHP_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-#endif
-	}
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	uint8_t b1, b2;
-
-	b1 = MCHP_KS_KSI_INPUT;
-	b2 = (b1 & 0xff) ^ 0xff;
-
-	/* Invert it so 0=not pressed, 1=pressed */
-	/* return (MCHP_KS_KSI_INPUT & 0xff) ^ 0xff; */
-	return b2;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		MCHP_INT_SOURCE(MCHP_KS_GIRQ) = MCHP_KS_GIRQ_BIT;
-		task_clear_pending_irq(MCHP_IRQ_KSC_INT);
-		task_enable_irq(MCHP_IRQ_KSC_INT);
-	} else {
-		task_disable_irq(MCHP_IRQ_KSC_INT);
-	}
-}
-
-void keyboard_raw_interrupt(void)
-{
-	/* Clear interrupt status bits */
-	MCHP_KS_KSI_STATUS = 0xff;
-
-	MCHP_INT_SOURCE(MCHP_KS_GIRQ) = MCHP_KS_GIRQ_BIT;
-
-	/* Wake keyboard scan task to handle interrupt */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(MCHP_IRQ_KSC_INT, keyboard_raw_interrupt, 1);
-
-int keyboard_raw_is_input_low(int port, int id)
-{
-	return (MCHP_GPIO_CTL(port, id) & BIT(24)) == 0;
-}
diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c
deleted file mode 100644
index 6f34a33a8d..0000000000
--- a/chip/mchp/lfw/ec_lfw.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC SoC little FW
- *
- */
-
-#include <stdint.h>
-
-#include "config.h"
-#include "cros_version.h"
-#include "gpio.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "util.h"
-#include "timer.h"
-#include "dma.h"
-#include "registers.h"
-#include "cpu.h"
-#include "clock.h"
-#include "system.h"
-#include "hwtimer.h"
-#include "gpio_list.h"
-#include "tfdp_chip.h"
-
-#ifdef CONFIG_MCHP_LFW_DEBUG
-#include "dma_chip.h"
-#endif
-
-#include "ec_lfw.h"
-
-/*
- * Check if LFW build is pulling in GPSPI which is not
- * used for EC firmware SPI flash access.
- */
-#ifdef CONFIG_MCHP_GPSPI
-#error "FORCED BUILD ERROR: CONFIG_MCHP_GPSPI is defined"
-#endif
-
-#define LFW_SPI_BYTE_TRANSFER_TIMEOUT_US (1 * MSEC)
-#define LFW_SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
-
-__attribute__ ((section(".intvector")))
-const struct int_vector_t hdr_int_vect = {
-	/* init sp, unused. set by MEC ROM loader */
-	(void *)lfw_stack_top,  /* preserve ROM log. was (void *)0x11FA00, */
-	&lfw_main,	/* was &lfw_main, */	  /* reset vector */
-	&fault_handler,   /* NMI handler */
-	&fault_handler,   /* HardFault handler */
-	&fault_handler,   /* MPU fault handler */
-	&fault_handler    /* Bus fault handler */
-};
-
-/* SPI devices - from board.c */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 4, GPIO_QMSPI_CS0 },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/*
- * At POR or EC reset MCHP Boot-ROM should only load LFW and jumps
- * into LFW entry point located at offset 0x04 of LFW.
- * Entry point is programmed into SPI Header by Python SPI image
- * builder in chip/mchp/util.
- *
- * EC_RO/RW calling LFW should enter through this routine if you
- * want the vector table updated. The stack should be set to
- * LFW linker file parameter lfw_stack_top because we do not
- * know if the callers stack is OK.
- *
- * Make sure lfw_stack_top will not overwrite panic data!
- * from include/panic.h
- * Panic data goes at the end of RAM. This is safe because we don't
- * context switch away from the panic handler before rebooting,
- * and stacks and data start at the beginning of RAM.
- *
- * chip level config_chip.h
- * #define CONFIG_RAM_SIZE 0x00008000
- * #define CONFIG_RAM_BASE 0x120000 - 0x8000 = 0x118000
- *
- *  #define PANIC_DATA_PTR ((struct panic_data *)\
- *	(CONFIG_RAM_BASE + CONFIG_RAM_SIZE - sizeof(struct panic_data)))
- *
- * LFW stack located by ec_lfw.ld linker file 256 bytes below top of
- * data SRAM.
- * PROVIDE( lfw_stack_top = 0x11F000 );
- *
- * !!!WARNING!!!
- * Current MEC BootROM's zeros all memory therefore any chip reset
- * will destroy panic data.
- */
-
-/*
- * Configure 32-bit basic timer 0 for 1MHz, auto-reload and
- * no interrupt.
- */
-void timer_init(void)
-{
-	uint32_t val = 0;
-
-	/* Ensure timer is not running */
-	MCHP_TMR32_CTL(0) &= ~BIT(5);
-
-	/* Enable timer */
-	MCHP_TMR32_CTL(0) |= BIT(0);
-
-	val = MCHP_TMR32_CTL(0);
-
-	/* Prescale = 48 -> 1MHz -> Period = 1 us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MCHP_TMR32_CTL(0) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MCHP_TMR32_PRE(0) = 0xffffffff;
-
-	/* Override the count */
-	MCHP_TMR32_CNT(0) = 0xffffffff;
-
-	/* Auto restart */
-	MCHP_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MCHP_TMR32_CTL(0) |= BIT(5);
-
-}
-
-/*
- * Use copy of SPI flash read compiled for LFW (no semaphores).
- * LFW timeout code does not use interrupts so reset timer
- * before starting SPI read to minimize probability of
- * timer wrap.
- */
-static int spi_flash_readloc(uint8_t *buf_usr,
-				unsigned int offset,
-				unsigned int bytes)
-{
-	uint8_t cmd[4] = {SPI_FLASH_READ,
-				(offset >> 16) & 0xFF,
-				(offset >> 8) & 0xFF,
-				offset & 0xFF};
-
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	__hw_clock_source_set(0); /* restart free run timer */
-	return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes);
-}
-
-/*
- * Load EC_RO/RW image from local SPI flash.
- * If CONFIG_MEC_TEST_EC_RORW_CRC was define the last 4 bytes
- * of the binary is IEEE 802.3 CRC32 of the previous bytes.
- * Use DMA channel 0 CRC32 HW to check data integrity.
- */
-int spi_image_load(uint32_t offset)
-{
-	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
-				    CONFIG_PROGRAM_MEMORY_BASE);
-	uint32_t i;
-#ifdef CONFIG_MCHP_LFW_DEBUG
-	uint32_t crc_calc, crc_exp;
-	int rc;
-#endif
-
-	BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE);
-
-	/* Why fill all but last 4-bytes? */
-	memset((void *)buf, 0xFF, (CONFIG_RO_SIZE - 4));
-
-	for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE)
-#ifdef CONFIG_MCHP_LFW_DEBUG
-		rc = spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
-		if (rc != EC_SUCCESS) {
-			trace2(0, LFW, 0,
-				"spi_flash_readloc block %d ret = %d",
-				i, rc);
-			while (MCHP_PCR_PROC_CLK_CTL)
-				MCHP_PCR_CHIP_OSC_ID &= 0x1FE;
-		}
-#else
-		spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
-#endif
-
-#ifdef CONFIG_MCHP_LFW_DEBUG
-	dma_crc32_start(buf, (CONFIG_RO_SIZE - 4), 0);
-	do {
-		MCHP_USEC_DELAY(31); /* delay(stall) CPU by 32 us */
-		i = dma_is_done_chan(0);
-	} while (i == 0);
-	crc_calc = MCHP_DMA_CH0_CRC32_DATA;
-	crc_exp = *((uint32_t *)&buf[CONFIG_RO_SIZE - 4]);
-	trace12(0, LFW, 0, "EC image CRC32 = 0x%08x  expected = 0x%08x",
-		crc_calc, crc_exp);
-#endif
-
-	return 0;
-}
-
-void udelay(unsigned int us)
-{
-	uint32_t t0 = __hw_clock_source_read();
-
-	while (__hw_clock_source_read() - t0 < us)
-		;
-}
-
-void usleep(unsigned int us)
-{
-	udelay(us);
-}
-
-int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
-{
-	timestamp_t now_val;
-
-	if (!now) {
-		now_val = get_time();
-		now = &now_val;
-	}
-
-	return ((int64_t)(now->val - deadline.val) >= 0);
-}
-
-/*
- * LFW does not use interrupts so no ISR will fire to
- * increment high 32-bits of timestap_t. Force high
- * word to zero. NOTE: There is a risk of false timeout
- * errors due to timer wrap. We will reset timer before
- * each SPI transaction.
- */
-timestamp_t get_time(void)
-{
-	timestamp_t ts;
-
-	ts.le.hi = 0;	/* clksrc_high; */
-	ts.le.lo = __hw_clock_source_read();
-	return ts;
-}
-
-#ifdef CONFIG_UART_CONSOLE
-
-BUILD_ASSERT(CONFIG_UART_CONSOLE < MCHP_UART_INSTANCES);
-
-void uart_write_c(char c)
-{
-	/* Put in carriage return prior to newline to mimic uart_vprintf() */
-	if (c == '\n')
-		uart_write_c('\r');
-
-	/* Wait for space in transmit FIFO. */
-	while (!(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & BIT(5)))
-		;
-	MCHP_UART_TB(CONFIG_UART_CONSOLE) = c;
-}
-
-void uart_puts(const char *str)
-{
-	if (!str || !*str)
-		return;
-
-	do {
-		uart_write_c(*str++);
-	} while (*str);
-}
-
-void uart_init(void)
-{
-	/* Set UART to reset on VCC1_RESET instead of nSIO_RESET */
-	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MCHP_UART_PBRG0(CONFIG_UART_CONSOLE) = 1;
-	MCHP_UART_PBRG1(CONFIG_UART_CONSOLE) = 0;
-
-	/* Set DLAB = 0 */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MCHP_UART_FCR(CONFIG_UART_CONSOLE) = BIT(0);
-
-	/* Activate UART */
-	MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
-
-	gpio_config_module(MODULE_UART, 1);
-}
-#else
-void uart_write_c(char c __attribute__((unused))) {}
-
-void uart_puts(const char *str __attribute__((unused))) {}
-
-void uart_init(void) {}
-#endif /* #ifdef CONFIG_UART_CONSOLE */
-
-void fault_handler(void)
-{
-	uart_puts("EXCEPTION!\nTriggering watchdog reset\n");
-	/* trigger reset in 1 ms */
-	usleep(1000);
-	MCHP_PCR_SYS_RST = MCHP_PCR_SYS_SOFT_RESET;
-	while (1)
-		;
-
-}
-
-void jump_to_image(uintptr_t init_addr)
-{
-	void (*resetvec)(void) = (void(*)(void))init_addr;
-
-	resetvec();
-}
-
-/*
- * If any of VTR POR, VBAT POR, chip resets, or WDT reset are active
- * force VBAT image type to none causing load of EC_RO.
- */
-void system_init(void)
-{
-	uint32_t wdt_sts = MCHP_VBAT_STS & MCHP_VBAT_STS_ANY_RST;
-	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS &
-				MCHP_PWR_RST_STS_SYS;
-
-	trace12(0, LFW, 0,
-		"VBAT_STS = 0x%08x  PCR_PWR_RST_STS = 0x%08x",
-		wdt_sts, rst_sts);
-
-	if (rst_sts || wdt_sts)
-		MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX)
-					= EC_IMAGE_UNKNOWN;
-}
-
-enum ec_image system_get_image_copy(void)
-{
-	return MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX);
-}
-
-
-/*
- * lfw_main is entered by MEC BootROM or EC_RO/RW calling it directly.
- * NOTE: Based on LFW from MEC1322
- * Upon chip reset, BootROM loads image = LFW+EC_RO and enters LFW.
- * LFW checks reset type:
- *   VTR POR, chip reset, WDT reset then set VBAT Load type to Unknown.
- * LFW reads VBAT Load type:
- *   EC_IMAGE_RO then read EC_RO from SPI flash and jump into it.
- *   EC_IMAGE_RO then read EC_RW from SPI flash and jump into it.
- *   Other then jump into EC image loaded by Boot-ROM.
- */
-void lfw_main(void)
-{
-
-	uintptr_t init_addr;
-
-	/* install vector table */
-	*((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect;
-
-	/* Use 48 MHz processor clock to power through boot */
-	MCHP_PCR_PROC_CLK_CTL = 1;
-
-#ifdef CONFIG_WATCHDOG
-	/* Reload watchdog which may be running in case of sysjump */
-	MCHP_WDG_KICK = 1;
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Stop aux timer */
-	MCHP_TMR16_CTL(0) &= ~1;
-#endif
-#endif
-	/*
-	 * TFDP functions will compile to nothing if CONFIG_MEC1701_TFDP
-	 * is not defined.
-	 */
-	tfdp_power(1);
-	tfdp_enable(1, 1);
-	trace0(0, LFW, 0, "LFW first trace");
-
-	timer_init();
-	clock_init();
-	cpu_init();
-	dma_init();
-	uart_init();
-	system_init();
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	uart_puts("littlefw ");
-	uart_puts(current_image_data.version);
-	uart_puts("\n");
-
-	switch (system_get_image_copy()) {
-	case EC_IMAGE_RW:
-		trace0(0, LFW, 0, "LFW EC_RW Load");
-		uart_puts("lfw-RW load\n");
-
-		init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-		spi_image_load(CONFIG_EC_WRITABLE_STORAGE_OFF +
-			       CONFIG_RW_STORAGE_OFF);
-		break;
-	case EC_IMAGE_RO:
-		trace0(0, LFW, 0, "LFW EC_RO Load");
-		uart_puts("lfw-RO load\n");
-
-		init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-		spi_image_load(CONFIG_EC_PROTECTED_STORAGE_OFF +
-			       CONFIG_RO_STORAGE_OFF);
-		break;
-	default:
-		trace0(0, LFW, 0, "LFW default: use EC_RO loaded by BootROM");
-		uart_puts("lfw-default case\n");
-
-		MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = EC_IMAGE_RO;
-
-		init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-	}
-
-	trace11(0, LFW, 0, "Get EC reset handler from 0x%08x", (init_addr + 4));
-	trace11(0, LFW, 0, "Jump to EC @ 0x%08x",
-		*((uint32_t *)(init_addr + 4)));
-	jump_to_image(*(uintptr_t *)(init_addr + 4));
-
-	/* should never get here */
-	while (1)
-		;
-}
diff --git a/chip/mchp/lfw/ec_lfw.h b/chip/mchp/lfw/ec_lfw.h
deleted file mode 100644
index c989a3bc1b..0000000000
--- a/chip/mchp/lfw/ec_lfw.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC SoC little FW
- *
- */
-
-#include <stdint.h>
-#include <stdnoreturn.h>
-
-/* Why naked?  This is dangerous except for
- * function/ISR wrappers using inline assembly.
- * lfw_main() makes many calls and has one local variable.
- * Naked C functions should not use local data unless the local
- * data can fit in CPU registers.
- * Note other C functions called by lfw_main() are not marked naked and
- * do include compiler generated prolog and epilog code.
- * We also do not know how much stack space is available when
- * EC_RO calls lfw_main().
- *
-noreturn void lfw_main(void) __attribute__ ((naked));
-*/
-noreturn void lfw_main(void);
-void fault_handler(void) __attribute__((naked));
-
-/*
- * Defined in linker file ec_lfw.ld
- */
-extern uint32_t lfw_stack_top[];
-
-struct int_vector_t {
-	void   *stack_ptr;
-	void   *reset_vector;
-	void   *nmi;
-	void   *hard_fault;
-	void   *bus_fault;
-	void   *usage_fault;
-};
-
-#define SPI_CHUNK_SIZE			1024
diff --git a/chip/mchp/lfw/ec_lfw.ld b/chip/mchp/lfw/ec_lfw.ld
deleted file mode 100644
index 8e8601a5ee..0000000000
--- a/chip/mchp/lfw/ec_lfw.ld
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC parts with 256KB SRAM SoC little FW
- *
- */
-
-/*
- * Memory Spaces Definitions
- * LFW occupies first 4KB of CODE SRAM.
- * First 24 bytes contain a minimal Cortex-M4
- * vector table.
- */
-MEMORY
-{
-    VECTOR(r )  : ORIGIN =  0x0E0000, LENGTH = 0x18
-    SRAM (xrw)  : ORIGIN =  0x0E0018, LENGTH = 0xFE8
-}
-
-/*
- * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the
- * values here.
- */
-ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.")
-ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0x1000, "Invalid VECTOR+SRAM length.")
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(lfw_main)
-
-/*
- * MEC 256KB SRAM 0xE0000 - 0x11FFFF
- * Data Top 32KB at 0x118000 - 0x11FFFF
- * Boot-ROM log is 0x11FF00 - 0x11FFFF
- * Set top of LFW stack 1KB below top of SRAM
- * because EC panic and jump data live at
- * top of SRAM.
- * !!!WARNING!!!
- * POR or any chip reset will cause MEC BootROM
- * to run. BootROM will clear all CODE & DATA SRAM.
- * Panic data will be lost.
- *
- */
-PROVIDE( lfw_stack_top = 0x11F000 );
-
-/* Sections Definitions */
-
-SECTIONS
-{
-
-    /*
-     * The vector table goes first
-     */
-    .intvector :
-    {
-        . = ALIGN(4);
-        KEEP(*(.intvector))
-    } > VECTOR
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to FLASH.
-     */
-
-    .text :
-    {
-        *(.text .text.*)                        /* all remaining code */
-        *(.rodata .rodata.*)            /* read-only data (constants) */
-    } >SRAM
-
-    . = ALIGN(4);
-
-    /* Padding */
-
-    .fill : {
-        FILL(0xFF);
-        . = ORIGIN(SRAM) + LENGTH(SRAM) - 1;
-        BYTE(0xFF);   /* emit at least a byte to make linker happy */
-    }
-
-    __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR);
-}
diff --git a/chip/mchp/lfw/ec_lfw_416kb.ld b/chip/mchp/lfw/ec_lfw_416kb.ld
deleted file mode 100644
index 97be2fe06a..0000000000
--- a/chip/mchp/lfw/ec_lfw_416kb.ld
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC parts with 416KB SRAM SoC little FW
- *
- */
-
-/*
- * Memory Spaces Definitions
- * LFW occupies first 4KB of CODE SRAM.
- * First 24 bytes contain a minimal Cortex-M4
- * vector table.
- */
-MEMORY
-{
-    VECTOR(r )  : ORIGIN =  0x0C0000, LENGTH = 0x18
-    SRAM (xrw)  : ORIGIN =  0x0C0018, LENGTH = 0xFE8
-}
-
-/*
- * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the
- * values here.
- */
-ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.")
-ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0x1000, "Invalid VECTOR+SRAM length.")
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(lfw_main)
-
-/*
- * MEC172xN has 416KB total SRAM: 352KB CODE 64KB DATA
- * CODE: 0x0C0000 - 0x117FFF
- * DATA: 0x118000 - 0x127FFF
- * Boot-ROM log is 0x11FF00 - 0x11FFFF
- * MEC172x Top 1KB is not cleared if OTP customer flag enabled.
- * !!! TODO !!! Does presence of PUF feature move customer area?
- * Boot-ROM spec states 3.5KB from top is lost.
- * 0x12_7800 - 0x12_7fff 2KB used by PUF option
- * 0x12_7400 - 0x12_77ff 1KB Customer use. Not cleared by Boot-ROM
- * 0x12_7200 - 0x12_73ff 512 byte Boot-ROM log
- * CrOS EC puts panic data at Top of RAM.
- * We must set Top of RAM to be customer region far enough to
- * hold panic data.
- * Set Top of SRAM to 0x12_7800.
- * This requires size of SRAM = 0x127800 - 0x118000 = 0xF800 (62 KB)
- */
-PROVIDE( lfw_stack_top = 0x127800 );
-
-/* Sections Definitions */
-
-SECTIONS
-{
-
-    /*
-     * The vector table goes first
-     */
-    .intvector :
-    {
-        . = ALIGN(4);
-        KEEP(*(.intvector))
-    } > VECTOR
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to FLASH.
-     */
-
-    .text :
-    {
-        *(.text .text.*)                        /* all remaining code */
-        *(.rodata .rodata.*)            /* read-only data (constants) */
-    } >SRAM
-
-    . = ALIGN(4);
-
-    /* Padding */
-
-    .fill : {
-        FILL(0xFF);
-        . = ORIGIN(SRAM) + LENGTH(SRAM) - 1;
-        BYTE(0xFF);   /* emit at least a byte to make linker happy */
-    }
-
-    __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR);
-}
diff --git a/chip/mchp/lfw/gpio.inc b/chip/mchp/lfw/gpio.inc
deleted file mode 100644
index 598a6044d7..0000000000
--- a/chip/mchp/lfw/gpio.inc
+++ /dev/null
@@ -1,107 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common GPIOs needed for LFW loader and main process FW
- */
-
-/* SPI
- * External SPI chip select must be open drain and driven high or
- * internal SPI chip select must be push-pull and driven high before
- * SPI controller configuration.
- * QMSPI external Shared CS0# is GPIO_0055
- * QMSPI internal CS0# is GPIO_0116
- */
-#if defined(CHIP_VARIANT_MEC1727SZ)
-GPIO(QMSPI_CS0, PIN(0116), GPIO_PULL_UP | GPIO_HIGH)
-#else
-GPIO(QMSPI_CS0, PIN(055), GPIO_ODR_HIGH)
-#endif
-
-/* Boot-ROM loads from external or internal SPI flash.
- * There are two external ports: shared(default) and private.
- * NOTE: QMSPI Shared SPI Port pins are on VTR2
- * SHD_CS0# = GPIO 0055 Func 2 bank 1 b[13]
- * SHD_CLK  = GPIO 0056 Func 2 bank 1 b[14]
- * SHD_IO0  = GPIO 0223 Func 1 bank 4 b[19]
- * SHD_IO1  = GPIO 0224 Func 2 bank 4 b[20]
- * Not using IO2 and IO2 as data
- * SHD_IO2  = GPIO 0227 Func 1 bank 4 b[23]
- * SHD_IO3  = GPIO 0016 Func 2 bank 0 b[14]
- * MEC1727 variants load from internal 512KB SPI flash(internal only pins)
- * INT_CS# = GPIO 0116 Func 1 bank 2 14
- * INT_SCK = GPIO 0117 Func 1 bank 2 15
- * INT_IO0 = GPIO 0074 Func 1 bank 1 28
- * INT_IO1 = GPIO 0075 Func 1 bank 1 29
- * INT_WP# = GPIO 0076 Func 0 for WP# control
- * Internal flash HOLD# connected to VTR1 rail.
- */
-#if defined(CHIP_VARIANT_MEC1727SZ)
-/* MEC1727 variants have internal SPI flash on internal only pins */
-ALTERNATE(PIN_MASK(2, 0x4000), 1, MODULE_SPI_FLASH, GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(2, 0x8000), 1, MODULE_SPI_FLASH, 0)
-ALTERNATE(PIN_MASK(1, 0x30000000), 1, MODULE_SPI_FLASH, 0)
-#else
-/* external SPI flash on QMSPI SHD_xx pins */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-ALTERNATE(PIN_MASK(4, 0x080000), 1, MODULE_SPI_FLASH, 0)
-ALTERNATE(PIN_MASK(4, 0x100000), 2, MODULE_SPI_FLASH, 0)
-#endif
-
-/* UART
- * Per CONFIG_UART_CONSOLE and chip to configure UART pins
- */
-#if CONFIG_UART_CONSOLE == 0
-/* select UART0 */
-/* MEC170X, MEC152X and MEC172X support same UART0 pins and ALT function */
-/*
- * UART0
- * GPIO_0105 Func 1 = UART_RX
- * GPIO_0104 Func 1 = UART_TX
- * Bank 2 bits[5:4]
- */
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
-#elif CONFIG_UART_CONSOLE == 1
-/* select UART1 */
-/* MEC170X, MEC152X and MEC172X support same UART1 pins
- * but ALT function 2 on MEC170X, function 1 on others
- */
-#if defined(CHIP_FAMILY_MEC170X)
-/*
- * UART1
- * GPIO_0171 Func 2 = UART_RX
- * GPIO_0170 Func 2 = UART_TX
- * Bank 3 bits[25:24]
- */
-ALTERNATE(PIN_MASK(3, 0x03000000), 2, MODULE_UART, 0)
-
-#else
-/*
- * UART1
- * GPIO_0171 Func 1 = UART_RX
- * GPIO_0170 Func 1 = UART_TX
- * Bank 3 bits[25:24]
- */
-ALTERNATE(PIN_MASK(3, 0x03000000), 1, MODULE_UART, 0)
-
-#endif /* defined(CHIP_FAMILY_MEC170X) */
-
-#else
-/* select UART2 */
-/* only MEC152X supports UART2 pins */
-#if defined(CHIP_FAMILY_MEC152X)
-/*
- * UART2
- * GPIO_0145 Func 2 = UART_RX
- * GPIO_0146 Func 2 = UART_TX
- * Bank 3 bits[6:5]
- */
-ALTERNATE(PIN_MASK(3, 0x60), 2, MODULE_UART, 0)
-
-#endif /* defined(CHIP_FAMILY_MEC152X) */
-
-#endif /* CONFIG_UART_CONSOLE == 0 */
diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c
deleted file mode 100644
index b5db07b88f..0000000000
--- a/chip/mchp/lpc.c
+++ /dev/null
@@ -1,1022 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for MCHP MEC family */
-
-#include "common.h"
-#include "acpi.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "lpc_chip.h"
-#include "espi.h"
-#include "port80.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "chipset.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#ifdef CONFIG_MCHP_DEBUG_LPC
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#else
-#define CPUTS(...)
-#define CPRINTS(...)
-#endif
-
-static uint8_t
-mem_mapped[0x200] __attribute__((section(".bss.big_align")));
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)mem_mapped;
-
-#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
-static uint8_t custom_acpi_cmd;
-static uint8_t custom_acpi_ec2os_cnt;
-static uint8_t custom_apci_ec2os[4];
-#endif
-
-
-static void keyboard_irq_assert(void)
-{
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-	/*
-	 * Enforce signal-high for long enough for the signal to be
-	 * pulled high by the external pull up resistor. This ensures the
-	 * host will see the following falling edge, regardless of the
-	 * line state before this function call.
-	 */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	udelay(4);
-
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-#else
-	/*
-	 * SERIRQ is automatically sent by KBC
-	 */
-#endif
-}
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length
- * is 60 ns. If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need
- * pulse length >61us. Both are short enough and events are infrequent,
- * so just delay for 65 us.
- */
-static void lpc_generate_smi(void)
-{
-	CPUTS("LPC Pulse SMI");
-#ifdef CONFIG_HOSTCMD_ESPI
-	/* eSPI: pulse SMI# Virtual Wire low */
-	espi_vw_pulse_wire(VW_SMI_L, 0);
-#else
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#endif
-}
-
-static void lpc_generate_sci(void)
-{
-	CPUTS("LPC Pulse SCI");
-#ifdef CONFIG_SCI_GPIO
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#else
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_vw_pulse_wire(VW_SCI_L, 0);
-#else
-	MCHP_ACPI_PM_STS |= 1;
-	udelay(65);
-	MCHP_ACPI_PM_STS &= ~1;
-#endif
-#endif
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that
-	 * through a separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_vw_set_wire(VW_WAKE_L, !wake_events);
-#else
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-#endif
-}
-
-static uint8_t *lpc_get_hostcmd_data_range(void)
-{
-	return mem_mapped;
-}
-
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via PCH_SMI_L GPIO
- *   - SCI pulse via PCH_SCI_L GPIO
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	CPUTS("LPC update_host_event_status");
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	task_disable_irq(MCHP_IRQ_ACPIEC0_IBF);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(MCHP_ACPI_EC_STATUS(0) & EC_LPC_STATUS_SMI_PENDING))
-			need_smi = 1;
-		MCHP_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SMI_PENDING;
-	} else {
-		MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SMI_PENDING;
-	}
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		MCHP_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SCI_PENDING;
-	} else {
-		MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SCI_PENDING;
-	}
-
-	/* Copy host events to mapped memory */
-	*(uint32_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-			lpc_get_host_events();
-
-	task_enable_irq(MCHP_IRQ_ACPIEC0_IBF);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-static void lpc_send_response(struct host_cmd_handler_args *args)
-{
-	uint8_t *out;
-	int size = args->response_size;
-	int csum;
-	int i;
-
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (args->result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Handle negative size */
-	if (size < 0) {
-		args->result = EC_RES_INVALID_RESPONSE;
-		size = 0;
-	}
-
-	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-			EC_HOST_ARGS_FLAG_TO_HOST;
-
-	lpc_host_args->data_size = size;
-
-	csum = args->command + lpc_host_args->flags +
-			lpc_host_args->command_version +
-			lpc_host_args->data_size;
-
-	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
-		csum += *out;
-
-	lpc_host_args->checksum = (uint8_t)csum;
-
-	/* Fail if response doesn't fit in the parameter buffer */
-	if (size > EC_PROTO2_MAX_PARAM_SIZE)
-		args->result = EC_RES_INVALID_RESPONSE;
-
-	/* Write result to the data byte. */
-	MCHP_ACPI_EC_EC2OS(1, 0) = args->result;
-
-	/*
-	 * Clear processing flag in hardware and
-	 * sticky status in interrupt aggregator.
-	 */
-	MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
-
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is
-	 * synchronous anyway
-	 */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS) {
-		/* CPRINTS("LPC EC_RES_IN_PROGRESS"); */
-		return;
-	}
-
-	CPRINTS("LPC Set EC2OS(1,0)=0x%02x", pkt->driver_result);
-
-	/* Write result to the data byte. */
-	MCHP_ACPI_EC_EC2OS(1, 0) = pkt->driver_result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return mem_mapped + 0x100;
-}
-
-void lpc_mem_mapped_init(void)
-{
-	/* We support LPC arguments and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-}
-
-const int acpi_ec_pcr_slp[] = {
-	MCHP_PCR_ACPI_EC0,
-	MCHP_PCR_ACPI_EC1,
-	MCHP_PCR_ACPI_EC2,
-	MCHP_PCR_ACPI_EC3,
-#ifndef CHIP_FAMILY_MEC152X
-	MCHP_PCR_ACPI_EC4,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(acpi_ec_pcr_slp) == MCHP_ACPI_EC_INSTANCES);
-
-const int acpi_ec_nvic_ibf[] = {
-	MCHP_IRQ_ACPIEC0_IBF,
-	MCHP_IRQ_ACPIEC1_IBF,
-	MCHP_IRQ_ACPIEC2_IBF,
-	MCHP_IRQ_ACPIEC3_IBF,
-#ifndef CHIP_FAMILY_MEC152X
-	MCHP_IRQ_ACPIEC4_IBF,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(acpi_ec_nvic_ibf) == MCHP_ACPI_EC_INSTANCES);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-const int acpi_ec_espi_bar_id[] = {
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC0,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC1,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC2,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC3,
-#ifndef CHIP_FAMILY_MEC152X
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC4,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(acpi_ec_espi_bar_id) == MCHP_ACPI_EC_INSTANCES);
-#endif
-
-void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask)
-{
-	if (instance >= MCHP_ACPI_EC_INSTANCES) {
-		CPUTS("ACPI EC CFG invalid");
-		return;
-	}
-
-	MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) =
-			mask;
-	MCHP_ESPI_IO_BAR(acpi_ec_espi_bar_id[instance]) =
-			(io_base << 16) + 0x01ul;
-#else
-	MCHP_LPC_ACPI_EC_BAR(instance) = (io_base << 16) +
-		(1ul << 15) + mask;
-#endif
-	MCHP_ACPI_EC_STATUS(instance) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_IBF_GIRQ_BIT(instance);
-	task_enable_irq(acpi_ec_nvic_ibf[instance]);
-}
-
-/*
- * 8042EM hardware decodes with fixed mask of 0x04
- * Example: io_base == 0x60 -> decodes 0x60/0x64
- * Enable both IBF and OBE interrupts.
- */
-void chip_8042_config(uint32_t io_base)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_8042);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_8042) = 0x04;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) =
-			(io_base << 16) + 0x01ul;
-#else
-	/* Set up 8042 interface at 0x60/0x64 */
-	MCHP_LPC_8042_BAR = (io_base << 16) + (1ul << 15);
-#endif
-	/* Set up indication of Auxiliary status */
-	MCHP_8042_KB_CTRL |= BIT(7);
-
-	MCHP_8042_ACT |= 1;
-
-	MCHP_INT_ENABLE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT +
-			MCHP_8042_IBF_GIRQ_BIT;
-
-	task_enable_irq(MCHP_IRQ_8042EM_IBF);
-	task_enable_irq(MCHP_IRQ_8042EM_OBE);
-
-#ifndef CONFIG_KEYBOARD_IRQ_GPIO
-	/* Set up SERIRQ for keyboard */
-	MCHP_8042_KB_CTRL |= BIT(5);
-#ifdef CONFIG_HOSTCMD_ESPI
-	/* Delivery 8042 keyboard interrupt as IRQ1 using eSPI SERIRQ */
-	MCHP_ESPI_IO_SERIRQ_REG(MCHP_ESPI_SIRQ_8042_KB) = 1;
-#else
-	MCHP_LPC_SIRQ(1) = 0x01;
-#endif
-#endif
-}
-
-/*
- * Access data RAM
- * MCHP EMI Base address register = physical address of buffer
- * in SRAM. EMI hardware adds 16-bit offset Host programs into
- * EC_Address_LSB/MSB registers.
- * Limit EMI read / write range. First 256 bytes are RW for host
- * commands. Second 256 bytes are RO for memory-mapped data.
- * Hardware decodes a fixed 16 byte IO range.
- */
-void chip_emi0_config(uint32_t io_base)
-{
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_EMI0) = 0x0F;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) =
-			(io_base << 16) + 0x01ul;
-#else
-	MCHP_LPC_EMI0_BAR = (io_base << 16) + (1ul << 15);
-#endif
-
-	MCHP_EMI_MBA0(0) = (uint32_t)mem_mapped;
-
-	MCHP_EMI_MRL0(0) = 0x200;
-	MCHP_EMI_MWL0(0) = 0x100;
-
-	MCHP_INT_ENABLE(MCHP_EMI_GIRQ) = MCHP_EMI_GIRQ_BIT(0);
-	task_enable_irq(MCHP_IRQ_EMI0);
-}
-
-/* Setup Port 80 Debug Hardware ports.
- * First instance for I/O 80h only.
- * Clear FIFO's and time stamp.
- * Set FIFO interrupt threshold to maximum of 14 bytes.
- */
-#if defined(CHIP_FAMILY_MEC172X)
-void chip_port80_config(uint32_t io_base)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BDP0);
-
-	/* reset, configure, and enable */
-	MCHP_BDP0_CONFIG = MCHP_BDP_CFG_SRST;
-	MCHP_BDP0_CONFIG = MCHP_BDP_CFG_FIFO_THRH_28;
-	MCHP_BDP0_INTR_EN = MCHP_BDP_IEN_THRH;
-	MCHP_BDP0_ACTV = 1;
-
-	MCHP_INT_SOURCE(15) = MCHP_INT15_BDP0;
-	MCHP_INT_ENABLE(15) = MCHP_INT15_BDP0;
-	task_enable_irq(MCHP_IRQ_BDP0);
-
-	/* Last: Enable Host access via eSPI IO BAR */
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_BDP0) = 0x00;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_BDP0) =
-			(io_base << 16) + 0x01ul;
-}
-#else
-void chip_port80_config(uint32_t io_base)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0);
-
-	MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO +
-			MCHP_P80_RESET_TIMESTAMP_WO;
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_P80_0) = 0x00;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) =
-			(io_base << 16) + 0x01ul;
-#else
-	MCHP_LPC_P80DBG0_BAR = (io_base << 16) + (1ul << 15);
-#endif
-	MCHP_P80_CFG(0) = MCHP_P80_FIFO_THRHOLD_14 +
-			MCHP_P80_TIMEBASE_1500KHZ +
-			MCHP_P80_TIMER_ENABLE;
-
-	MCHP_P80_ACTIVATE(0) = 1;
-
-	MCHP_INT_SOURCE(15) = MCHP_P80_GIRQ_BIT(0);
-	MCHP_INT_ENABLE(15) = MCHP_P80_GIRQ_BIT(0);
-	task_enable_irq(MCHP_IRQ_PORT80DBG0);
-}
-#endif
-
-#ifdef CONFIG_MCHP_DEBUG_LPC
-static void chip_lpc_iobar_debug(void)
-{
-	CPRINTS("LPC ACPI EC0 IO BAR = 0x%08x", MCHP_LPC_ACPI_EC_BAR(0));
-	CPRINTS("LPC ACPI EC1 IO BAR = 0x%08x", MCHP_LPC_ACPI_EC_BAR(1));
-	CPRINTS("LPC 8042EM IO BAR   = 0x%08x", MCHP_LPC_8042_BAR);
-	CPRINTS("LPC EMI0 IO BAR     = 0x%08x", MCHP_LPC_EMI0_BAR);
-	CPRINTS("LPC Port80Dbg0 IO BAR = 0x%08x", MCHP_LPC_P80DBG0_BAR);
-}
-#endif
-
-/*
- * Most registers in LPC module are reset when the host is off.
- * We need to set up LPC again when the host is starting up.
- * MCHP LRESET# can be one of two pins
- *	GPIO_0052 Function 2
- *	GPIO_0064 Function 1
- * Use GPIO interrupt to detect LRESET# changes.
- * Use GPIO_0064 for LRESET#. Must update board/board_name/gpio.inc
- *
- * For eSPI PLATFORM_RESET# virtual wire is used as LRESET#
- *
- */
-#ifndef CONFIG_HOSTCMD_ESPI
-static void setup_lpc(void)
-{
-	MCHP_LPC_CFG_BAR |= (1ul << 15);
-
-	/* Set up ACPI0 for 0x62/0x66 */
-	chip_acpi_ec_config(0, 0x62, 0x04);
-
-	/* Set up ACPI1 for 0x200 - 0x207 */
-	chip_acpi_ec_config(1, 0x200, 0x07);
-
-	/* Set up 8042 interface at 0x60/0x64 */
-	chip_8042_config(0x60);
-
-#ifndef CONFIG_KEYBOARD_IRQ_GPIO
-	/* Set up SERIRQ for keyboard */
-	MCHP_8042_KB_CTRL |= BIT(5);
-	MCHP_LPC_SIRQ(1) = 0x01;
-#endif
-	/* EMI0 at IO 0x800 */
-	chip_emi0_config(0x800);
-
-	chip_port80_config(0x80);
-
-	lpc_mem_mapped_init();
-
-	/* Activate LPC interface */
-	MCHP_LPC_ACT |= 1;
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-
-#ifdef CONFIG_MCHP_DEBUG_LPC
-	chip_lpc_iobar_debug();
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST);
-#endif
-
-static void lpc_init(void)
-{
-	CPUTS("LPC HOOK_INIT");
-
-	/* Initialize host args and memory map to all zero */
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-
-	/*
-	 * Clear PCR sleep enables for peripherals we are using for
-	 * both LPC and eSPI.
-	 * Global Configuration, ACPI EC0/1, 8042 Keyboard controller.
-	 * NOTE: EMI doesn't have a sleep enable.
-	 */
-	MCHP_PCR_SLP_DIS_DEV_MASK(2, MCHP_PCR_SLP_EN2_GCFG +
-		MCHP_PCR_SLP_EN2_ACPI_EC0 +
-		MCHP_PCR_SLP_EN2_ACPI_EC0 +
-		MCHP_PCR_SLP_EN2_MIF8042);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-
-	espi_init();
-
-#else
-	/* Clear PCR LPC sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_LPC);
-
-	/* configure pins */
-	gpio_config_module(MODULE_LPC, 1);
-
-	/*
-	 * MCHP LRESET# interrupt is GPIO interrupt
-	 * and configured by GPIO table in board level gpio.inc
-	 * Refer to lpcrst_interrupt() in this file.
-	 */
-	gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
-
-	/*
-	 * b[8]=1(LRESET# is platform reset), b[0]=0 VCC_PWRGD is
-	 * asserted when LRESET# is 1(inactive)
-	 */
-	MCHP_PCR_PWR_RST_CTL = 0x100ul;
-
-	/*
-	 * Allow LPC sleep if Host CLKRUN# signals
-	 * clock stop and there are no pending SERIRQ
-	 * or LPC DMA.
-	 */
-	MCHP_LPC_EC_CLK_CTRL =
-		(MCHP_LPC_EC_CLK_CTRL & ~(0x03ul)) | 0x01ul;
-
-	setup_lpc();
-#endif
-}
-/*
- * Set priority to higher than default; this way LPC memory mapped
- * data is ready before other inits try to initialize their
- * memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-void lpc_set_init_done(int val)
-{
-	init_done = val;
-}
-
-/*
- * MCHP MCHP family allows selecting one of two GPIO pins alternate
- * functions as LRESET#.
- * LRESET# can be monitored as bit[1](read-only) of the
- * LPC Bus Monitor register. NOTE: Bus Monitor is synchronized with
- * LPC clock. We have observed APL configurations where LRESET#
- * changes while LPC clock is not running!
- * bit[1]==0 -> LRESET# is high
- * bit[1]==1 -> LRESET# is low (active)
- * LRESET# active causes the EC to activate internal signal RESET_HOST.
- * MCHP_PCR_PWR_RST_STS bit[3](read-only) = RESET_HOST_STATUS =
- * 0 = Reset active
- * 1 = Reset not active
- * MCHP is different than MEC1322 in that LRESET# is not connected
- * to a separate interrupt source.
- * If using LPC the board design must select on of the two GPIO pins
- * dedicated for LRESET# and this pin must be configured in the
- * board level gpio.inc
- */
-void lpcrst_interrupt(enum gpio_signal signal)
-{
-#ifndef CONFIG_HOSTCMD_ESPI
-	/* Initialize LPC module when LRESET# is de-asserted */
-	if (!lpc_get_pltrst_asserted()) {
-		setup_lpc();
-	} else {
-		/* Store port 80 reset event */
-		port_80_write(PORT_80_EVENT_RESET);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-		/* Notify HOOK_CHIPSET_RESET */
-		hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-	}
-#ifdef CONFIG_MCHP_DEBUG_LPC
-	CPRINTS("LPC RESET# %sasserted",
-		lpc_get_pltrst_asserted() ? "" : "de");
-#endif
-#endif
-}
-
-/*
- * TODO - Is this only for debug of EMI host communication
- * or logging of EMI host communication? We don't observe
- * this ISR so Host is not writing to MCHP_EMI_H2E_MBX(0).
- */
-void emi0_interrupt(void)
-{
-	uint8_t h2e;
-
-	h2e = MCHP_EMI_H2E_MBX(0);
-	CPRINTS("LPC Host 0x%02x -> EMI0 H2E(0)", h2e);
-	port_80_write(h2e);
-}
-DECLARE_IRQ(MCHP_IRQ_EMI0, emi0_interrupt, 1);
-
-/*
- * ISR empties BIOS Debug 0 FIFO and
- * writes data to circular buffer. How can we be
- * sure this routine can read the last Port 80h byte?
- * MEC172x BDP capture data is different. It returns a
- * 16-bit value where bits [7:0] are the data and bits [15:7]
- * are flags indicating if the data is part of a multi-byte
- * write sequence by the host and read-only FIFO status bits.
- * The capture HW in previous chips included an optional time
- * stamp in bits[31:8] of the data register.
- */
-int port_80_read(void)
-{
-	int data = PORT_80_IGNORE;
-
-#if defined(CHIP_FAMILY_MEC172X)
-	if (MCHP_BDP0_STATUS & MCHP_BDP_STATUS_NOT_EMPTY)
-		data = MCHP_BDP0_DATTR & 0xFFU;
-#else
-	if (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY)
-		data = MCHP_P80_CAP(0) & 0xFF;
-#endif
-
-	return data;
-}
-
-#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
-/*
- * Handle custom ACPI EC0 commands.
- * Some chipset CoreBoot will send read board ID command expecting
- * a two byte response.
- */
-static int acpi_ec0_custom(int is_cmd, uint8_t value,
-		uint8_t *resultptr)
-{
-	int rval;
-
-	rval = 0;
-	custom_acpi_ec2os_cnt = 0;
-	*resultptr = 0x00;
-
-	if (is_cmd && (value == 0x0d)) {
-		MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
-		/* Write two bytes sequence 0xC2, 0x04 to Host */
-		if (MCHP_ACPI_EC_BYTE_CTL(0) & 0x01) {
-			/* Host enabled 4-byte mode */
-			MCHP_ACPI_EC_EC2OS(0, 0) = 0x02;
-			MCHP_ACPI_EC_EC2OS(0, 1) = 0x04;
-			MCHP_ACPI_EC_EC2OS(0, 2) = 0x00;
-			/* Sets OBF */
-			MCHP_ACPI_EC_EC2OS(0, 3) = 0x00;
-		} else {
-			/* single byte mode */
-			*resultptr = 0x02;
-			custom_acpi_ec2os_cnt = 1;
-			custom_apci_ec2os[0] = 0x04;
-			MCHP_ACPI_EC_EC2OS(0, 0) = 0x02;
-			MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) =
-					MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
-			task_enable_irq(MCHP_IRQ_ACPIEC0_OBE);
-		}
-		custom_acpi_cmd = 0;
-		rval = 1;
-	}
-
-	return rval;
-}
-#endif
-
-void acpi_0_interrupt(void)
-{
-	uint8_t value, result, is_cmd;
-
-	is_cmd = MCHP_ACPI_EC_STATUS(0);
-
-	/* Set the bust bi */
-	MCHP_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_PROCESSING;
-
-	result = MCHP_ACPI_EC_BYTE_CTL(0);
-
-	/* Read command/data; this clears the FRMH bit. */
-	value = MCHP_ACPI_EC_OS2EC(0, 0);
-
-	is_cmd &= EC_LPC_STATUS_LAST_CMD;
-
-	/* Handle whatever this was. */
-	result = 0;
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		MCHP_ACPI_EC_EC2OS(0, 0) = result;
-#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
-	else
-		acpi_ec0_custom(is_cmd, value, &result);
-#endif
-	/* Clear the busy bit */
-	MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
-
-	/* Clear R/W1C status bit in Aggregator */
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_IBF_GIRQ_BIT(0);
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty /
-	 * Output Buffer Full condition on the kernel channel/
-	 */
-	lpc_generate_sci();
-}
-DECLARE_IRQ(MCHP_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1);
-
-#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
-/*
- * ACPI EC0 output buffer empty ISR.
- * Used to handle custom ACPI EC0 command requiring
- * two byte response.
- */
-void acpi_0_obe_isr(void)
-{
-	uint8_t sts, data;
-
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
-
-	sts = MCHP_ACPI_EC_STATUS(0);
-	data = MCHP_ACPI_EC_BYTE_CTL(0);
-	data = sts;
-	if (custom_acpi_ec2os_cnt) {
-		custom_acpi_ec2os_cnt--;
-		data = custom_apci_ec2os[custom_acpi_ec2os_cnt];
-	}
-
-	if (custom_acpi_ec2os_cnt == 0) { /* was last byte? */
-		MCHP_INT_DISABLE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
-	}
-
-	lpc_generate_sci();
-}
-DECLARE_IRQ(MCHP_IRQ_ACPIEC0_OBE, acpi_0_obe_isr, 1);
-#endif
-
-void acpi_1_interrupt(void)
-{
-	uint8_t st = MCHP_ACPI_EC_STATUS(1);
-
-	if (!(st & EC_LPC_STATUS_FROM_HOST) ||
-	    !(st & EC_LPC_STATUS_LAST_CMD))
-		return;
-
-	/* Set the busy bit */
-	MCHP_ACPI_EC_STATUS(1) |= EC_LPC_STATUS_PROCESSING;
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = MCHP_ACPI_EC_OS2EC(1, 0);
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_args.send_response = lpc_send_response;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* We only support new style command (v3) now */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request =
-			(const void *)lpc_get_hostcmd_data_range();
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so
-		 * pass in the entire buffer
-		 */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response =
-			(void *)lpc_get_hostcmd_data_range();
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-
-		host_packet_receive(&lpc_packet);
-
-	} else {
-		/* Old style command unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-
-		/* Hand off to host command handler */
-		host_command_received(&host_cmd_args);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1);
-
-#ifdef HAS_TASK_KEYPROTO
-/*
- * Reading data out of input buffer clears read-only status
- * in 8042EM. Next, we must clear aggregator status.
- */
-void kb_ibf_interrupt(void)
-{
-	if (lpc_keyboard_input_pending())
-		keyboard_host_write(MCHP_8042_H2E,
-				    MCHP_8042_STS & BIT(3));
-
-	MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_IBF_GIRQ_BIT;
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MCHP_IRQ_8042EM_IBF, kb_ibf_interrupt, 1);
-
-/*
- * Interrupt generated when Host reads data byte from 8042EM
- * output buffer. The 8042EM STATUS.OBF bit will clear when the
- * Host reads the data and assert its OBE signal to interrupt
- * aggregator. Clear aggregator 8042EM OBE R/WC status bit before
- * invoking task.
- */
-void kb_obe_interrupt(void)
-{
-	MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT;
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MCHP_IRQ_8042EM_OBE, kb_obe_interrupt, 1);
-#endif
-
-/*
- * Bit 0 of 8042EM STATUS register is OBF meaning EC has written
- * data to EC2HOST data register. OBF is cleared when the host
- * reads the data.
- */
-int lpc_keyboard_has_char(void)
-{
-	return (MCHP_8042_STS & BIT(0)) ? 1 : 0;
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	return (MCHP_8042_STS & BIT(1)) ? 1 : 0;
-}
-
-/*
- * called from common/keyboard_8042.c
- */
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	MCHP_8042_E2H = chr;
-	if (send_irq)
-		keyboard_irq_assert();
-}
-
-/*
- * Read 8042 register and write to read-only register
- * insuring compiler does not optimize out the read.
- */
-void lpc_keyboard_clear_buffer(void)
-{
-	MCHP_PCR_CHIP_OSC_ID = MCHP_8042_OBF_CLR;
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	MCHP_ACPI_EC_STATUS(0) |= mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	MCHP_ACPI_EC_STATUS(0) &= ~mask;
-}
-
-/*
- * Read hardware to determine state of platform reset signal.
- * LPC issue: Observed APL chipset changing LRESET# while LPC
- * clock is not running. This violates original LPC specification.
- * Unable to find information in APL chipset documentation
- * stating APL can change LRESET# with LPC clock not running.
- * Could this be a CoreBoot issue during CB LPC configuration?
- * We work-around this issue by reading the GPIO state.
- */
-int lpc_get_pltrst_asserted(void)
-{
-#ifdef CONFIG_HOSTCMD_ESPI
-	/*
-	 * eSPI PLTRST# a VWire or side-band signal
-	 * Controlled by CONFIG_HOSTCMD_ESPI
-	 */
-	return !espi_vw_get_wire(VW_PLTRST_L);
-#else
-	/* returns 1 if LRESET# pin is asserted(low) else 0 */
-#ifdef CONFIG_CHIPSET_APL_GLK
-	/* Use GPIO */
-	return !gpio_get_level(GPIO_PCH_PLTRST_L);
-#else
-	/* assumes LPC clock is running when host changes LRESET# */
-	return (MCHP_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0;
-#endif
-#endif
-}
-
-/* Enable LPC ACPI-EC0 interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	task_enable_irq(MCHP_IRQ_ACPIEC0_IBF);
-}
-
-/* Disable LPC ACPI-EC0 interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	task_disable_irq(MCHP_IRQ_ACPIEC0_IBF);
-}
-
-/* On boards without a host, this command is used to set up LPC */
-static int lpc_command_init(int argc, char **argv)
-{
-	lpc_init();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(lpcinit, lpc_command_init, NULL, NULL);
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	CPUTS("MEC1701 Handler EC_CMD_GET_PROTOCOL_INFO");
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
-
-#ifdef CONFIG_MCHP_DEBUG_LPC
-static int command_lpc(int argc, char **argv)
-{
-	if (argc == 1)
-		return EC_ERROR_PARAM1;
-
-	if (!strcasecmp(argv[1], "sci"))
-		lpc_generate_sci();
-	else if (!strcasecmp(argv[1], "smi"))
-		lpc_generate_smi();
-	else if (!strcasecmp(argv[1], "wake"))
-		lpc_update_wake(-1);
-	else
-		return EC_ERROR_PARAM1;
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]",
-	"Trigger SCI/SMI");
-#endif
-
diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h
deleted file mode 100644
index dcb5577fc1..0000000000
--- a/chip/mchp/lpc_chip.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Microchip MEC1701 specific module for Chrome EC */
-
-#ifndef __CROS_EC_LPC_CHIP_H
-#define __CROS_EC_LPC_CHIP_H
-
-#ifdef CONFIG_HOSTCMD_ESPI
-
-#include "espi.h"
-
-#define MCHP_HOST_IF_LPC  (0)
-#define MCHP_HOST_IF_ESPI (1)
-
-/* eSPI Initialization functions */
-void espi_init(void);
-
-/* eSPI ESPI_RESET# interrupt handler */
-void espi_reset_handler(void);
-
-/*
- *
- */
-int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level);
-
-void lpc_update_host_event_status(void);
-
-#endif
-
-/* LPC LRESET interrupt handler */
-void lpcrst_interrupt(enum gpio_signal signal);
-
-void lpc_set_init_done(int val);
-
-void lpc_mem_mapped_init(void);
-
-#ifndef CONFIG_HOSTCMD_ESPI
-void lpcrst_interrupt(enum gpio_signal signal);
-#endif
-
-void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask);
-void chip_8042_config(uint32_t io_base);
-void chip_emi0_config(uint32_t io_base);
-void chip_port80_config(uint32_t io_base);
-
-#endif /* __CROS_EC_LPC_CHIP_H */
diff --git a/chip/mchp/port80.c b/chip/mchp/port80.c
deleted file mode 100644
index ecfd0b5ebb..0000000000
--- a/chip/mchp/port80.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Port 80 Timer Interrupt for MCHP MEC family */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "lpc.h"
-#include "port80.h"
-#include "registers.h"
-#include "task.h"
-#include "tfdp_chip.h"
-
-
-#if defined(CHIP_FAMILY_MEC172X)
-/*
- * MEC172x family implements a new Port 0x80 capture block.
- * The BDP HW can capture 8, 16, and 32 bit writes.
- * Interrupt fires when BDP FIFO threshold is reached.
- * Data can be read from a 16-bit register containing:
- * b[7:0] data byte
- * b[9:8] = byte lane
- * b[11:10]= flags indicating current byte is a single byte or part of
- * a multi-byte sequence.
- * b[14:12] = copy of bits[2:0] of the status register
- * b[15] = 0 reserved
- * NOTE: The overrun bit could be used to set a flag indicating EC could
- * not keep up with the host.
- */
-void port_80_interrupt(void)
-{
-	int d = MCHP_BDP0_DATTR;
-
-	while (d & MCHP_BDP_DATTR_NE) {
-		port_80_write(d & 0xffU);
-		d = MCHP_BDP0_DATTR;
-	}
-
-	MCHP_INT_SOURCE(MCHP_BDP0_GIRQ) = MCHP_BDP0_GIRQ_BIT;
-}
-DECLARE_IRQ(MCHP_IRQ_BDP0, port_80_interrupt, 3);
-#else
-/*
- * Interrupt fires when number of bytes written
- * to eSPI/LPC I/O 80h-81h exceeds Por80_0 FIFO level
- * Issues:
- * 1. eSPI will not break 16-bit I/O into two 8-bit writes
- *    as LPC does. This means Port 80h hardware will capture
- *    only bits[7:0] of data.
- * 2. If Host performs write of 16-bit code as consecutive
- *    byte writes the Port 80h hardware will capture both but
- *    we do not know the order it was written.
- * 3. If Host sometimes writes one byte code to I/O 80h and
- *    sometimes two byte code to I/O 80h/81h how do we determine
- *    what to do?
- *
- * An alternative is to document Host must write 16-bit codes
- * to I/O 80h and 90h.  LSB to 0x80 and MSB to 0x90.
- *
- */
-void port_80_interrupt(void)
-{
-	int d;
-
-	while (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY) {
-		/*
-		 * This masks off time stamp d = port_80_read();
-		 * b[7:0] = data, b[32:8] = time stamp
-		 */
-		d = MCHP_P80_CAP(0);
-		trace1(0, P80, 0, "Port80h = 0x%02x", (d & 0xff));
-		port_80_write(d & 0xff);
-	}
-
-	MCHP_INT_SOURCE(MCHP_P80_GIRQ) = MCHP_P80_GIRQ_BIT(0);
-}
-DECLARE_IRQ(MCHP_IRQ_PORT80DBG0, port_80_interrupt, 3);
-#endif
-
diff --git a/chip/mchp/pwm.c b/chip/mchp/pwm.c
deleted file mode 100644
index ae22f13ca5..0000000000
--- a/chip/mchp/pwm.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for MCHP MEC family */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-#define CPUTS(outstr) cputs(CC_PWM, outstr)
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-
-/* Bit map of PWM channels that must remain active during low power idle. */
-static uint32_t pwm_keep_awake_mask;
-
-/* Table of PWM PCR sleep enable register index and bit position. */
-static const uint16_t pwm_pcr[] = {
-	MCHP_PCR_PWM0,
-	MCHP_PCR_PWM1,
-	MCHP_PCR_PWM2,
-	MCHP_PCR_PWM3,
-	MCHP_PCR_PWM4,
-	MCHP_PCR_PWM5,
-	MCHP_PCR_PWM6,
-	MCHP_PCR_PWM7,
-	MCHP_PCR_PWM8,
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_pcr) == MCHP_PWM_ID_MAX);
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (enabled) {
-		MCHP_PWM_CFG(id) |= BIT(0);
-		if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-			pwm_keep_awake_mask |= BIT(id);
-	} else {
-		MCHP_PWM_CFG(id) &= ~BIT(0);
-		pwm_keep_awake_mask &= ~BIT(id);
-	}
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return MCHP_PWM_CFG(pwm_channels[ch].channel) & 0x1;
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	MCHP_PWM_ON(id) = percent;
-	MCHP_PWM_OFF(id) = 100 - percent;
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	return MCHP_PWM_ON(pwm_channels[ch].channel);
-}
-
-void pwm_keep_awake(void)
-{
-	if (pwm_keep_awake_mask) {
-		for (uint32_t i = 0; i < MCHP_PWM_ID_MAX; i++)
-			if (pwm_keep_awake_mask & BIT(i))
-				MCHP_PCR_SLP_DIS_DEV(pwm_pcr[i]);
-	} else {
-		MCHP_PCR_SLOW_CLK_CTL &= ~(MCHP_PCR_SLOW_CLK_CTL_MASK);
-	}
-}
-
-/*
- * clock_low=0 selects the 48MHz Ring Oscillator source
- * clock_low=1 selects the 100kHz_Clk source
- */
-static void pwm_configure(int ch, int active_low, int clock_low)
-{
-	MCHP_PWM_CFG(ch) = (15 << 3) /* divider = 16 */
-		| (active_low ? BIT(2) : 0)
-		| (clock_low  ? BIT(1) : 0);
-}
-
-static void pwm_slp_en(int pwm_id, int sleep_en)
-{
-	if ((pwm_id < 0) || (pwm_id > MCHP_PWM_ID_MAX))
-		return;
-
-	if (sleep_en)
-		MCHP_PCR_SLP_EN_DEV(pwm_pcr[pwm_id]);
-	else
-		MCHP_PCR_SLP_DIS_DEV(pwm_pcr[pwm_id]);
-}
-
-static void pwm_init(void)
-{
-	int i;
-
-	for (i = 0; i < PWM_CH_COUNT; ++i) {
-		pwm_slp_en(pwm_channels[i].channel, 0);
-		pwm_configure(pwm_channels[i].channel,
-			      pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW,
-			      pwm_channels[i].flags & PWM_CONFIG_ALT_CLOCK);
-		pwm_set_duty(i, 0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/mchp/pwm_chip.h b/chip/mchp/pwm_chip.h
deleted file mode 100644
index f828a234a7..0000000000
--- a/chip/mchp/pwm_chip.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1701H-specific PWM module for Chrome EC */
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/*
- * MEC152x SZ 144-pin has 9 PWM and 4 TACH
- * MEC170x SZ 144-pin has 9 PWM and 3 TACH
- * MEC172x SZ 144-pin has 9 PWM and 4 TACH
- */
-enum pwm_hw_id {
-	PWM_HW_CH_0 = 0,
-	PWM_HW_CH_1,
-	PWM_HW_CH_2,
-	PWM_HW_CH_3,
-	PWM_HW_CH_4,
-	PWM_HW_CH_5,
-	PWM_HW_CH_6,
-	PWM_HW_CH_7,
-	PWM_HW_CH_8,
-	PWM_HW_CH_COUNT
-};
-
-enum tach_hw_id {
-	TACH_HW_CH_0 = 0,
-	TACH_HW_CH_1,
-	TACH_HW_CH_2,
-#ifndef CHIP_FAMILY_MEC170X
-	TACH_HW_CH_3,
-#endif
-	TACH_HW_CH_COUNT
-};
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM Channel ID */
-	int channel;
-
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-void pwm_keep_awake(void);
-
-#endif  /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/mchp/qmspi.c b/chip/mchp/qmspi.c
deleted file mode 100644
index 72eaa91d37..0000000000
--- a/chip/mchp/qmspi.c
+++ /dev/null
@@ -1,700 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* QMSPI master module for MCHP MEC family */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-#include "dma_chip.h"
-#include "spi_chip.h"
-#include "qmspi_chip.h"
-#include "tfdp_chip.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-#define QMSPI_TRANSFER_TIMEOUT (100 * MSEC)
-#define QMSPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
-#define QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US 20
-
-
-
-#ifndef CONFIG_MCHP_QMSPI_TX_DMA
-#ifdef LFW
-/*
- * MCHP 32-bit timer 0 configured for 1us count down mode and no
- * interrupt in the LFW environment. Don't need to sleep CPU in LFW.
- */
-static int qmspi_wait(uint32_t mask, uint32_t mval)
-{
-	uint32_t t1, t2, td;
-
-	t1 = MCHP_TMR32_CNT(0);
-
-	while ((MCHP_QMSPI0_STS & mask) != mval) {
-		t2 = MCHP_TMR32_CNT(0);
-		if (t1 >= t2)
-			td = t1 - t2;
-		else
-			td = t1 + (0xfffffffful - t2);
-		if (td > QMSPI_BYTE_TRANSFER_TIMEOUT_US)
-			return EC_ERROR_TIMEOUT;
-	}
-	return EC_SUCCESS;
-}
-#else
-/*
- * This version uses the full EC_RO/RW timer infrastructure and it needs
- * a timer ISR to handle timer underflow. Without the ISR we observe false
- * timeouts when debugging with JTAG.
- * QMSPI_BYTE_TRANSFER_TIMEOUT_US currently 3ms
- * QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US currently 100 us
- */
-
-static int qmspi_wait(uint32_t mask, uint32_t mval)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + (QMSPI_BYTE_TRANSFER_TIMEOUT_US);
-
-	while ((MCHP_QMSPI0_STS & mask) != mval) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-
-		usleep(QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-#endif /* #ifdef LFW */
-#endif /* #ifndef CONFIG_MCHP_QMSPI_TX_DMA */
-
-/*
- * Wait for QMSPI read using DMA to finish.
- * DMA subsystem has 100 ms timeout
- */
-int qmspi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	const struct dma_option *opdma;
-
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-	if (opdma != NULL)
-		return dma_wait(opdma->channel);
-
-	return EC_ERROR_INVAL;
-}
-
-/*
- * Create QMSPI transmit data descriptor not using DMA.
- * Transmit on MOSI pin (single/full-duplex) from TX FIFO.
- * TX FIFO filled by CPU.
- * Caller will apply close and last flags if applicable.
- */
-#ifndef CONFIG_MCHP_QMSPI_TX_DMA
-static uint32_t qmspi_build_tx_descr(uint32_t ntx, uint32_t ndid)
-{
-	uint32_t d;
-
-	d = MCHP_QMSPI_C_1X + MCHP_QMSPI_C_TX_DATA;
-	d |= ((ndid & 0x0F) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
-
-	if (ntx <= MCHP_QMSPI_C_MAX_UNITS)
-		d |= MCHP_QMSPI_C_XFRU_1B;
-	else {
-		if ((ntx & 0x0f) == 0) {
-			ntx >>= 4;
-			d |= MCHP_QMSPI_C_XFRU_16B;
-		} else if ((ntx & 0x03) == 0) {
-			ntx >>= 2;
-			d |= MCHP_QMSPI_C_XFRU_4B;
-		} else
-			d |= MCHP_QMSPI_C_XFRU_1B;
-
-		if (ntx > MCHP_QMSPI_C_MAX_UNITS)
-			return 0; /* overflow unit count field */
-	}
-
-	d |= (ntx << MCHP_QMSPI_C_NUM_UNITS_BITPOS);
-
-	return d;
-}
-
-/*
- * Create QMSPI receive data descriptor using DMA.
- * Receive data on MISO pin (single/full-duplex) and store in QMSPI
- * RX FIFO. QMSPI triggers DMA channel to read from RX FIFO and write
- * to memory. Return value is an uint64_t where low 32-bit word is the
- * descriptor and upper 32-bit word is DMA channel unit length with
- * value (1, 2, or 4).
- * Caller will apply close and last flags if applicable.
- */
-static uint64_t qmspi_build_rx_descr(uint32_t raddr,
-		uint32_t nrx, uint32_t ndid)
-{
-	uint32_t d, dmau, na;
-	uint64_t u;
-
-	d = MCHP_QMSPI_C_1X + MCHP_QMSPI_C_RX_EN;
-	d |= ((ndid & 0x0F) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
-
-	dmau = 1;
-	na = (raddr | nrx) & 0x03;
-	if (na == 0) {
-		d |= MCHP_QMSPI_C_RX_DMA_4B;
-		dmau <<= 2;
-	} else if (na == 0x02) {
-		d |= MCHP_QMSPI_C_RX_DMA_2B;
-		dmau <<= 1;
-	} else {
-		d |= MCHP_QMSPI_C_RX_DMA_1B;
-	}
-
-	if ((nrx & 0x0f) == 0) {
-		nrx >>= 4;
-		d |= MCHP_QMSPI_C_XFRU_16B;
-	} else if ((nrx & 0x03) == 0) {
-		nrx >>= 2;
-		d |= MCHP_QMSPI_C_XFRU_4B;
-	} else {
-		d |= MCHP_QMSPI_C_XFRU_1B;
-	}
-
-	u = 0;
-	if (nrx <= MCHP_QMSPI_C_MAX_UNITS) {
-		d |= (nrx << MCHP_QMSPI_C_NUM_UNITS_BITPOS);
-		u = dmau;
-		u <<= 32;
-		u |= d;
-	}
-
-	return u;
-}
-#endif
-
-#ifdef CONFIG_MCHP_QMSPI_TX_DMA
-
-#define QMSPI_ERR_ANY			0x80
-#define QMSPI_ERR_BAD_PTR		0x81
-#define QMSPI_ERR_OUT_OF_DESCR		0x85
-
-/*
- * bits[1:0] of word
- * 1 -> 0
- * 2 -> 1
- * 4 -> 2
- */
-static uint32_t qmspi_pins_encoding(uint8_t npins)
-{
-	return (uint32_t)(npins >> 1) & 0x03;
-}
-
-/*
- * Clear status, FIFO's, and all descriptors.
- * Enable descriptor mode.
- */
-static void qmspi_descr_mode_ready(void)
-{
-	int i;
-
-	MCHP_QMSPI0_CTRL = 0;
-	MCHP_QMSPI0_IEN  = 0;
-	MCHP_QMSPI0_EXE  = MCHP_QMSPI_EXE_CLR_FIFOS;
-	MCHP_QMSPI0_STS  = 0xfffffffful;
-	MCHP_QMSPI0_CTRL = MCHP_QMSPI_C_DESCR_MODE_EN;
-	/* clear all descriptors */
-	for (i = 0; i < MCHP_QMSPI_MAX_DESCR; i++)
-		MCHP_QMSPI0_DESCR(i) = 0;
-}
-
-/*
- * helper
- * did = zero based index of start descriptor
- * descr = descriptor configuration
- * nb = number of bytes to transfer
- * Return index of last descriptor allocated or 0xffff
- * if out of descriptors.
- * Algorithm:
- * If requested number of bytes will fit in one descriptor then
- * configure descriptor for QMSPI byte units and return.
- * Otherwise allocate multiple descriptor using QMSPI 16-byte mode
- * and remaining < 16 bytes in byte unit descriptor until all bytes
- * exhausted or out of descriptors error.
- */
-static uint32_t qmspi_descr_alloc(uint32_t did,
-				uint32_t descr, uint32_t nb)
-{
-	uint32_t nu;
-
-	while (nb) {
-		if (did >= MCHP_QMSPI_MAX_DESCR)
-			return 0xffff;
-
-		descr &= ~(MCHP_QMSPI_C_NUM_UNITS_MASK +
-			MCHP_QMSPI_C_XFRU_MASK);
-
-		if (nb < (MCHP_QMSPI_C_MAX_UNITS + 1)) {
-			descr |= MCHP_QMSPI_C_XFRU_1B;
-			descr += (nb << MCHP_QMSPI_C_NUM_UNITS_BITPOS);
-			nb = 0;
-		} else {
-			descr |= MCHP_QMSPI_C_XFRU_16B;
-			nu = (nb >> 4) & MCHP_QMSPI_C_NUM_UNITS_MASK0;
-			descr += (nu << MCHP_QMSPI_C_NUM_UNITS_BITPOS);
-			nb -= (nu << 4);
-		}
-
-		descr |= ((did+1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
-		MCHP_QMSPI0_DESCR(did) = descr;
-		if (nb)
-			did++;
-	}
-
-	return did;
-}
-
-/*
- * Build one or more descriptors for command/data transmit.
- * cfg b[7:0] = start descriptor index
- * cfg b[15:8] = number of pins for transmit.
- * If bytes to transmit will fit in TX FIFO then fill TX FIFO and build
- * one descriptor.
- * Otherwise build one or more descriptors to fill TX FIFO using DMA
- * channel and configure the DMA channel for memory to device transfer.
- */
-static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
-					uint32_t cfg,
-					const uint8_t *data,
-					uint32_t ndata)
-{
-	uint32_t d, d2, did, dma_cfg;
-
-	did = cfg & 0x0f;
-	d = qmspi_pins_encoding((cfg >> 8) & 0x07);
-
-	if (ndata <= MCHP_QMSPI_TX_FIFO_LEN) {
-		d2 = d + (ndata << MCHP_QMSPI_C_NUM_UNITS_BITPOS) +
-			MCHP_QMSPI_C_XFRU_1B + MCHP_QMSPI_C_TX_DATA;
-		d2 += ((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
-		MCHP_QMSPI0_DESCR(did) = d2;
-		while (ndata--)
-			MCHP_QMSPI0_TX_FIFO8 = *data++;
-	} else { // TX DMA
-		if (((uint32_t)data | ndata) & 0x03) {
-			dma_cfg = 1;
-			d |= (MCHP_QMSPI_C_TX_DATA +
-				MCHP_QMSPI_C_TX_DMA_1B);
-		} else {
-			dma_cfg = 4;
-			d |= (MCHP_QMSPI_C_TX_DATA +
-				MCHP_QMSPI_C_TX_DMA_4B);
-		}
-		did = qmspi_descr_alloc(did, d, ndata);
-		if (did == 0xffff)
-			return QMSPI_ERR_OUT_OF_DESCR;
-
-		dma_clr_chan(opdma->channel);
-		dma_cfg_buffers(opdma->channel, data, ndata,
-			(void *)MCHP_QMSPI0_TX_FIFO_ADDR);
-		dma_cfg_xfr(opdma->channel, dma_cfg,
-			MCHP_DMA_QMSPI0_TX_REQ_ID,
-			(DMA_FLAG_M2D + DMA_FLAG_INCR_MEM));
-		dma_run(opdma->channel);
-	}
-
-	return did;
-}
-
-/*
- * QMSPI0 Start
- * flags
- *  b[0] = 1 de-assert chip select when done
- *  b[1] = 1 enable QMSPI interrupts
- *  b[2] = 1 start
- */
-void qmspi_cfg_irq_start(uint8_t flags)
-{
-	MCHP_INT_DISABLE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT;
-	MCHP_INT_SOURCE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT;
-	MCHP_QMSPI0_IEN = 0;
-
-	if (flags & (1u << 1)) {
-		MCHP_QMSPI0_IEN = (MCHP_QMSPI_STS_DONE +
-			MCHP_QMSPI_STS_PROG_ERR);
-		MCHP_INT_ENABLE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT;
-	}
-
-	if (flags & (1u << 2))
-		MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_START;
-}
-
-/*
- * QMSPI transmit and/or receive
- * np_flags
- *  b[7:0] = flags
- *	b[0] = close(de-assert chip select when done)
- *	b[1] = enable Done and ProgError interrupt
- *	b[2] = start
- *  b[15:8] = number of tx pins
- *  b[24:16] = number of rx pins
- *
- * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR
- * or error (bit[7]==1)
- */
-uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
-			uint32_t np_flags,
-			const uint8_t *txdata, uint32_t ntx,
-			uint8_t *rxdata, uint32_t nrx)
-{
-	uint32_t d, did, dma_cfg;
-	const struct dma_option *opdma;
-
-	qmspi_descr_mode_ready();
-
-	did = 0;
-	if (ntx) {
-		if (txdata == NULL)
-			return QMSPI_ERR_BAD_PTR;
-
-		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_WR);
-
-		d = qmspi_pins_encoding((np_flags >> 8) & 0xff);
-		dma_cfg = (np_flags & 0xFF00) + did;
-		did = qmspi_xmit_data_descr(opdma, dma_cfg, txdata, ntx);
-		if (did & QMSPI_ERR_ANY)
-			return (uint8_t)(did & 0xff);
-
-		if (nrx)
-			did++; /* point to next descriptor */
-	}
-
-	if (nrx) {
-		if (rxdata == NULL)
-			return QMSPI_ERR_BAD_PTR;
-
-		if (did >= MCHP_QMSPI_MAX_DESCR)
-			return QMSPI_ERR_OUT_OF_DESCR;
-
-		d = qmspi_pins_encoding((np_flags >> 16) & 0xff);
-		/* compute DMA units: 1 or 4 */
-		if (((uint32_t)rxdata | nrx) & 0x03) {
-			dma_cfg = 1;
-			d |= (MCHP_QMSPI_C_RX_EN + MCHP_QMSPI_C_RX_DMA_1B);
-		} else {
-			dma_cfg = 4;
-			d |= (MCHP_QMSPI_C_RX_EN + MCHP_QMSPI_C_RX_DMA_4B);
-		}
-		did = qmspi_descr_alloc(did, d, nrx);
-		if (did & QMSPI_ERR_ANY)
-			return (uint8_t)(did & 0xff);
-
-		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-		dma_clr_chan(opdma->channel);
-		dma_cfg_buffers(opdma->channel, rxdata, nrx,
-			(void *)MCHP_QMSPI0_RX_FIFO_ADDR);
-		dma_cfg_xfr(opdma->channel, dma_cfg,
-			MCHP_DMA_QMSPI0_RX_REQ_ID,
-			(DMA_FLAG_D2M + DMA_FLAG_INCR_MEM));
-		dma_run(opdma->channel);
-	}
-
-	if (ntx || nrx) {
-		d = MCHP_QMSPI0_DESCR(did);
-		d |= MCHP_QMSPI_C_DESCR_LAST;
-		if (np_flags & 0x01)
-			d |= MCHP_QMSPI_C_CLOSE;
-		MCHP_QMSPI0_DESCR(did) = d;
-		qmspi_cfg_irq_start(np_flags & 0xFF);
-	}
-
-	return (uint8_t)(did & 0xFF);
-}
-#endif /* #ifdef CONFIG_MCHP_QMSPI_TX_DMA */
-
-/*
- * QMSPI controller must control chip select therefore this routine
- * configures QMSPI to assert SPI CS# and de-assert when done.
- * Transmit using QMSPI TX FIFO only when tx data fits in TX FIFO else
- * use TX DMA.
- * Transmit and receive will allocate as many QMSPI descriptors as
- * needed for data size. This could result in an error if the maximum
- * number of descriptors is exceeded.
- * Descriptors are limited to 0x7FFF units where unit size is 1, 4, or
- * 16 bytes. Code determines unit size based upon number of bytes and
- * alignment of data buffer.
- * DMA channel will move data in units of 1 or 4 bytes also based upon
- * the number of data bytes and buffer alignment.
- * The most efficient transfers are those where TX and RX buffers are
- * aligned >= 4 bytes and the number of bytes is a multiple of 4.
- * NOTE on SPI flash commands:
- * This routine does NOT handle SPI flash commands requiring
- * extra clocks or special mode bytes. Extra clocks and special mode
- * bytes require additional descriptors. For example the flash read
- * dual command (0x3B):
- * 1. First descriptor transmits 4 bytes (opcode + 24-bit address) on
- *    one pin (IO0).
- * 2. Second descriptor set for 2 IO pins, 2 bytes, TX disabled. When
- *    this descriptor is executed QMSPI will tri-state IO0 & IO1 and
- *    output 8 clocks (dual mode 4 clocks per byte). The SPI flash may
- *    turn on its output drivers on the first clock.
- * 3. Third descriptor set for 2 IO pins, read data using DMA. Unit
- *    size and DMA unit size based on number of bytes to read and
- *    alignment of destination buffer.
- * The common SPI API will be required to supply more information about
- * SPI flash read commands.  A further complication is some larger SPI
- * flash devices support a 4-byte address mode. 4-byte address mode can
- * be implemented as separate command code or a configuration bit in
- * the SPI flash that changes the default 24-bit address command to
- * require a 32-bit address.
- * 0x03 is 1-1-1
- * 0x3B is 1-1-2 with 8 clocks
- * 0x6B is 1-1-4 with 8 clocks
- * 0xBB is 1-2-2 with 4 clocks
- * Number of IO pins for command
- * Number of IO pins for address
- * Number of IO pins for data
- * Number of bit/bytes for address (3 or 4)
- * Number of clocks after address phase
- */
-#ifdef CONFIG_MCHP_QMSPI_TX_DMA
-int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
-{
-	uint32_t np_flags, ntx, nrx;
-	int ret;
-	uint8_t rc;
-
-	ntx = 0;
-	if (txlen >= 0)
-		ntx = (uint32_t)txlen;
-
-	nrx = 0;
-	if (rxlen >= 0)
-		nrx = (uint32_t)rxlen;
-
-	np_flags = 0x010105; /* b[0]=1 close on done, b[2]=1 start */
-	rc = qmspi_xfr(spi_device, np_flags,
-			txdata, ntx,
-			rxdata, nrx);
-
-	if (rc & QMSPI_ERR_ANY)
-		return EC_ERROR_INVAL;
-
-	ret = EC_SUCCESS;
-	return ret;
-}
-#else
-/*
- * Transmit using CPU and QMSPI TX FIFO(no DMA).
- * Receive using DMA as above.
- */
-int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
-{
-	const struct dma_option *opdma;
-	uint32_t d, did, dmau;
-	uint64_t u;
-
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-	/* soft reset the controller */
-	MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
-	d = spi_device->div;
-	d <<= MCHP_QMSPI_M_CLKDIV_BITPOS;
-	d += (MCHP_QMSPI_M_ACTIVATE + MCHP_QMSPI_M_SPI_MODE0);
-	MCHP_QMSPI0_MODE = d;
-	MCHP_QMSPI0_CTRL = MCHP_QMSPI_C_DESCR_MODE_EN;
-
-	d = did = 0;
-
-	if (txlen > 0) {
-		if (txdata == NULL)
-			return EC_ERROR_PARAM2;
-
-		d = qmspi_build_tx_descr((uint32_t)txlen, 1);
-		if (d == 0) /* txlen too large */
-			return EC_ERROR_OVERFLOW;
-
-		MCHP_QMSPI0_DESCR(did) = d;
-	}
-
-	if (rxlen > 0) {
-		if (rxdata == NULL)
-			return EC_ERROR_PARAM4;
-
-		u = qmspi_build_rx_descr((uint32_t)rxdata,
-				(uint32_t)rxlen, 2);
-
-		d = (uint32_t)u;
-		dmau = u >> 32;
-
-		if (txlen > 0)
-			did++;
-		MCHP_QMSPI0_DESCR(did) = d;
-
-		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-		dma_xfr_start_rx(opdma, dmau, (uint32_t)rxlen, rxdata);
-	}
-
-	MCHP_QMSPI0_DESCR(did) |= (MCHP_QMSPI_C_CLOSE +
-			MCHP_QMSPI_C_DESCR_LAST);
-
-	MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_START;
-
-	while (txlen--) {
-		if (MCHP_QMSPI0_STS & MCHP_QMSPI_STS_TX_BUFF_FULL) {
-			if (qmspi_wait(MCHP_QMSPI_STS_TX_BUFF_EMPTY,
-					MCHP_QMSPI_STS_TX_BUFF_EMPTY) !=
-							EC_SUCCESS) {
-				MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_STOP;
-				return EC_ERROR_TIMEOUT;
-			}
-		} else
-			MCHP_QMSPI0_TX_FIFO8 = *txdata++;
-	}
-
-	return EC_SUCCESS;
-}
-#endif /* #ifdef CONFIG_MCHP_QMSPI_TX_DMA */
-
-/*
- * Wait for QMSPI descriptor mode transfer to finish.
- * QMSPI is configured to perform a complete transaction.
- * Assert CS#
- * optional transmit
- *   CPU keeps filling TX FIFO until all bytes are transmitted.
- * optional receive
- *   QMSPI is configured to read rxlen bytes and uses a DMA channel
- *   to move data from its RX FIFO to memory.
- * De-assert CS#
- * This routine can be called with QMSPI hardware in four states:
- * 1. Transmit only and QMSPI has finished (empty TX FIFO) by the time
- *    this routine is called. QMSPI.Status transfer done status will be
- *    set and QMSPI HW has de-asserted SPI CS#.
- * 2. Transmit only and QMSPI TX FIFO is still transmitting.
- *    QMSPI transfer done status is not asserted and CS# is still
- *    asserted. QMSPI HW will de-assert CS# when done or firmware
- *    manually stops QMSPI.
- * 3. Receive was enabled and DMA channel is moving data from
- *    QMSPI RX FIFO to memory. QMSPI.Status transfer done and DMA done
- *    status bits are not set. QMSPI SPI CS# will stay asserted until
- *    transaction finishes or firmware manually stops QMSPI.
- * 4. Receive was enabled and DMA channel is finished. QMSPI RX FIFO
- *    should be empty and DMA channel is done.  QMSPI.Status transfer
- *    done and DMA done status bits will be set. QMSPI HW has de-asserted
- *    SPI CS#.
- * We are using QMSPI in descriptor mode. The definition of QMSPI.Status
- * transfer complete bit in this mode is: complete will be set to 1 only
- * when the last buffer completes its transfer.
- * TX only sets complete when transfer unit count is matched and all units
- * have been clocked out of the TX FIFO.
- * RX DMA transfer complete will be set when the last transfer unit
- * is out of the RX FIFO but DMA may not be complete until it finishes
- * moving the transfer unit to memory.
- * If TX only spin on QMSPI.Status Transfer_Complete bit.
- * If RX used spin on QMsPI.Status Transfer_Complete and DMA_Complete.
- * Search descriptors looking for RX DMA enabled.
- * If RX DMA is enabled add DMA complete flag to status mask.
- * Spin while QMSPI.Status & mask != mask or timeout.
- * If timeout force QMSPI to stop and exit spin loop.
- * if DMA was enabled disable DMA channel.
- * Clear QMSPI.Status and FIFO's
- */
-int qmspi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int ret;
-	uint32_t qsts, mask;
-	const struct dma_option *opdma;
-	timestamp_t deadline;
-
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-	mask = MCHP_QMSPI_STS_DONE;
-
-	ret = EC_SUCCESS;
-	deadline.val = get_time().val + QMSPI_TRANSFER_TIMEOUT;
-
-	qsts = MCHP_QMSPI0_STS;
-	while ((qsts & mask) != mask) {
-		if (timestamp_expired(deadline, NULL)) {
-			MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_STOP;
-			ret = EC_ERROR_TIMEOUT;
-			break;
-		}
-		usleep(QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-		qsts = MCHP_QMSPI0_STS;
-	}
-
-	/* clear transmit DMA channel */
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_WR);
-	if (opdma == NULL)
-		return EC_ERROR_INVAL;
-
-	dma_disable(opdma->channel);
-	dma_clear_isr(opdma->channel);
-
-	/* clear receive DMA channel */
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-	if (opdma == NULL)
-		return EC_ERROR_INVAL;
-
-	dma_disable(opdma->channel);
-	dma_clear_isr(opdma->channel);
-
-	/* clear QMSPI FIFO's */
-	MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_CLR_FIFOS;
-	MCHP_QMSPI0_STS = 0xffffffff;
-
-	return ret;
-}
-
-/**
- * Enable QMSPI controller and MODULE_SPI_FLASH pins.
- *
- * @param hw_port b[3:0]=0 and b[7:4]=0
- * @param enable
- * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized
- * @note called by spi_enable in mec1701/spi.c
- *
- */
-int qmspi_enable(int hw_port, int enable)
-{
-	uint8_t unused __attribute__((unused)) = 0;
-
-	trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d",
-			hw_port, enable);
-
-	if (hw_port != QMSPI0_PORT)
-		return EC_ERROR_INVAL;
-
-	gpio_config_module(MODULE_SPI_FLASH, (enable > 0));
-
-	if (enable) {
-		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_QMSPI);
-		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
-		unused = MCHP_QMSPI0_MODE_ACT_SRST;
-		MCHP_QMSPI0_MODE = (MCHP_QMSPI_M_ACTIVATE +
-				MCHP_QMSPI_M_SPI_MODE0 +
-				MCHP_QMSPI_M_CLKDIV_12M);
-	} else {
-		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
-		unused = MCHP_QMSPI0_MODE_ACT_SRST;
-		MCHP_QMSPI0_MODE_ACT_SRST = 0;
-		MCHP_PCR_SLP_EN_DEV(MCHP_PCR_QMSPI);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/mchp/qmspi_chip.h b/chip/mchp/qmspi_chip.h
deleted file mode 100644
index 1a1d764267..0000000000
--- a/chip/mchp/qmspi_chip.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MEC17xx processor
- */
-/** @file qmspi_chip.h
- *MEC17xx Quad SPI Master
- */
-/** @defgroup MCHP MEC qmspi
- */
-
-#ifndef _QMSPI_CHIP_H
-#define _QMSPI_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-/* struct spi_device_t */
-#include "spi.h"
-
-
-int qmspi_transaction_flush(const struct spi_device_t *spi_device);
-
-int qmspi_transaction_wait(const struct spi_device_t *spi_device);
-
-int qmspi_transaction_sync(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
-
-int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
-
-int qmspi_enable(int port, int enable);
-
-/*
- * QMSPI0 Start
- * flags
- *  b[0] = ignored
- *  b[1] = 1 enable QMSPI interrupts
- *  b[2] = 1 start
- */
-void qmspi_cfg_irq_start(uint8_t flags);
-
-/*
- * QMSPI transmit and/or receive
- * np_flags
- *  b[7:0] = flags
- *	b[0] = close(de-assert chip select when done)
- *	b[1] = enable Done and ProgError interrupt
- *	b[2] = start
- *  b[15:8] = number of tx pins
- *  b[24:16] = number of rx pins
- *
- * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR
- * or error (bit[7]==1)
- */
-uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
-			uint32_t np_flags,
-			const uint8_t *txdata, uint32_t ntx,
-			uint8_t *rxdata, uint32_t nrx);
-
-#endif /* #ifndef _QMSPI_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/registers-mec152x.h b/chip/mchp/registers-mec152x.h
deleted file mode 100644
index 10021ede8b..0000000000
--- a/chip/mchp/registers-mec152x.h
+++ /dev/null
@@ -1,1289 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for Microchip MEC152x family controllers
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/*
- * IRQ Numbers
- * NOTE: GIRQ22 aggregated output and its sources are not connected to
- * the NVIC.
- */
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
-/* GIRQ13 direct sources */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
-#define MCHP_IRQ_I2C_4		158
-#define MCHP_IRQ_I2C_5		168
-#define MCHP_IRQ_I2C_6		169
-#define MCHP_IRQ_I2C_7		170
-/* GIRQ14 direct sources */
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
-/* GIRQ15 direct sources */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_UART2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-#define MCHP_IRQ_PORT80DBG0	62
-#define MCHP_IRQ_PORT80DBG1	63
-#define MCHP_IRQ_LASIC		64
-/* GIRQ16 direct sources */
-#define MCHP_IRQ_PKE_ERR	65
-#define MCHP_IRQ_PKE_END	66
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AES		68
-#define MCHP_IRQ_HASH		69
-/* GIRQ17 direct sources */
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_TACH_3		159
-#define MCHP_IRQ_HDMI_CEC	160
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_PROCHOT	87
-/* GIRQ18 direct sources */
-#define MCHP_IRQ_SLAVE_SPI	90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_PS2_1		101
-#define MCHP_IRQ_PSPI		155
-#define MCHP_IRQ_SGPIO_0	161
-#define MCHP_IRQ_SGPIO_1	162
-#define MCHP_IRQ_SGPIO_2	163
-#define MCHP_IRQ_SGPIO_3	164
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
-/* GIRQ19 direct sources */
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_ESPI_VW_EN	156
-/* GIRQ20 direct sources */
-#define MCHP_IRQ_OTP		173
-/* GIRQ21 direct sources */
-#define MCHP_IRQ_WDG		171
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_PS21B_WAKE	132
-#define MCHP_IRQ_KSC_INT	135
-/* GIRQ23 direct sources */
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
-/* Must match CONFIG_IRQ_COUNT in config_chip.h */
-#define MCHP_IRQ_MAX		174
-
-/* Block base addresses */
-#define MCHP_WDG_BASE		0x40000400
-#define MCHP_TMR16_0_BASE	0x40000c00
-#define MCHP_TMR32_0_BASE	0x40000c80
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_PROCHOT_BASE	0x40003400
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_I2C4_BASE		0x40005000
-#define MCHP_I2C5_BASE		0x40005100
-#define MCHP_I2C6_BASE		0x40005200
-#define MCHP_I2C7_BASE		0x40005300
-#define MCHP_QMSPI0_BASE	0x40070000
-#define MCHP_PWM_0_BASE		0x40005800
-#define MCHP_TACH_0_BASE	0x40006000
-#define MCHP_PECI_BASE		0x40006400
-#define MCHP_RTMR_BASE		0x40007400
-#define MCHP_ADC_BASE		0x40007c00
-#define MCHP_TFDP_BASE		0x40008c00
-#define MCHP_HTIMER_BASE	0x40009800
-#define MCHP_KEYSCAN_BASE	0x40009c00
-#define MCHP_VBAT_BASE		0x4000a400
-#define MCHP_VBAT_RAM_BASE	0x4000a800
-#define MCHP_WKTIMER_BASE	0x4000ac80
-#define MCHP_BBLED_0_BASE	0x4000B800
-#define MCHP_INT_BASE		0x4000e000
-#define MCHP_EC_BASE		0x4000fc00
-
-#define MCHP_PCR_BASE		0x40080100
-#define MCHP_GPIO_BASE		0x40081000
-
-#define MCHP_MBOX_BASE		0x400f0000
-#define MCHP_8042_BASE		0x400f0400
-#define MCHP_ACPI_EC_0_BASE	0x400f0800
-#define MCHP_ACPI_PM1_BASE	0x400f1c00
-#define MCHP_UART0_BASE		0x400f2400
-#define MCHP_UART1_BASE		0x400f2800
-#define MCHP_UART2_BASE		0x400f2c00
-#define MCHP_ESPI_IO_BASE	0x400f3400
-#define MCHP_ESPI_MEM_BASE	0x400f3800
-#define MCHP_EMI_0_BASE		0x400f4000
-#define MCHP_EMI_1_BASE		0x400f4400
-#define MCHP_P80CAP0_BASE	0x400f8000
-#define MCHP_P80CAP1_BASE	0x400f8400
-#define MCHP_ESPI_VW_BASE	0x400f9c00
-#define MCHP_CHIP_BASE		0x400fff00
-
-#ifndef __ASSEMBLER__
-
-/*
- * Helper function for RAM address aliasing
- * NOTE: MCHP AHB masters do NOT require aliasing.
- * Cortex-M4 bit-banding does require aliasing of the
- * DATA SRAM region.
- */
-#define MCHP_RAM_ALIAS(x) \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
-
-/* EC Chip Configuration */
-/* 16-bit Device ID */
-#define MCHP_CHIP_DEV_ID		REG16(MCHP_CHIP_BASE + 0x1E)
-/* 8-bit Device Sub ID */
-#define MCHP_CHIP_DEV_SUB_ID		REG8(MCHP_CHIP_BASE + 0x1D)
-/* 8-bit Device Revision */
-#define MCHP_CHIP_DEV_REV		REG8(MCHP_CHIP_BASE + 0x1C)
-/* All in one */
-#define MCHP_CHIP_DEVRID32		REG32(MCHP_CHIP_BASE + 0x1C)
-#define MCHP_CHIP_DEVID_POS		16
-#define MCHP_CHIP_DEVID_MASK		(0xfffful << MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_SUBID_POS		8
-#define MCHP_CHIP_SUBID_MASK		(0xfful << MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_REV_POS		0
-#define MCHP_CHIP_REV_MASK		(0xfful << MCHP_CHIP_REV_POS)
-#define MCHP_CHIP_EXTRACT_DEVID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_EXTRACT_SUBID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_EXTRACT_REV(d) \
-	(((uint32_t)(d) & MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
-
-/* PCR clock control dividers */
-#define MCHP_PCR_CLK_CTL_FASTEST	1U
-#define MCHP_PCR_CLK_CTL_48MHZ		1U
-#define MCHP_PCR_CLK_CTL_12MHZ		4U
-
-/*
- * PCR Peripheral Reset Lock register
- * MEC152x PCR Peripheral reset registers do not reset on
- * peripheral sleep. The peripheral is reset immediately.
- * Firmware must write an unlock value to this new lock
- * register, write to PCR reset enable register(s), and
- * write a lock value.
- */
-#define MCHP_PCR_RST_LOCK		REG32(MCHP_PCR_BASE + 0x84)
-#define MCHP_PCR_RST_LOCK_VAL		0xa6382d4d
-#define MCHP_PCR_RST_UNLOCK_VAL		0xa6382d4c
-
-/* Number of PCR Sleep Enable, Clock Required, and Reset registers */
-#define MCHP_PCR_SLP_RST_REG_MAX	5
-
-/* MC152x new bit allow sleep entry when PLL is not locked */
-#define MCHP_PCR_SYS_SLP_NO_PLL		BIT(8)
-
-/* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_JTAG	BIT(0) /* CLKREQ only */
-#define MCHP_PCR_OTP	BIT(1)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_OTP	BIT(1)
-#define MCHP_PCR_SLP_EN0_SLEEP	0xffffffff
-
-/*
- * Encode register number and bit position
- * b[4:0] = bit number
- * b[10:8] = zero based register number
- */
-#define MCHP_PCR_ERB(rnum, bnum) \
-	((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f))
-
-/* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_BTMR16_1	MCHP_PCR_ERB(1, 31)
-#define MCHP_PCR_BTMR16_0	MCHP_PCR_ERB(1, 30)
-#define MCHP_PCR_ECS		MCHP_PCR_ERB(1, 29)
-#define MCHP_PCR_PWM8		MCHP_PCR_ERB(1, 27)
-#define MCHP_PCR_PWM7		MCHP_PCR_ERB(1, 26)
-#define MCHP_PCR_PWM6		MCHP_PCR_ERB(1, 25)
-#define MCHP_PCR_PWM5		MCHP_PCR_ERB(1, 24)
-#define MCHP_PCR_PWM4		MCHP_PCR_ERB(1, 23)
-#define MCHP_PCR_PWM3		MCHP_PCR_ERB(1, 22)
-#define MCHP_PCR_PWM2		MCHP_PCR_ERB(1, 21)
-#define MCHP_PCR_PWM1		MCHP_PCR_ERB(1, 20)
-#define MCHP_PCR_TACH3		MCHP_PCR_ERB(1, 13)
-#define MCHP_PCR_TACH2		MCHP_PCR_ERB(1, 12)
-#define MCHP_PCR_TACH1		MCHP_PCR_ERB(1, 11)
-#define MCHP_PCR_I2C0		MCHP_PCR_ERB(1, 10)
-#define MCHP_PCR_WDT		MCHP_PCR_ERB(1, 9)
-#define MCHP_PCR_CPU		MCHP_PCR_ERB(1, 8)
-#define MCHP_PCR_TFDP		MCHP_PCR_ERB(1, 7)
-#define MCHP_PCR_DMA		MCHP_PCR_ERB(1, 6)
-#define MCHP_PCR_PMC		MCHP_PCR_ERB(1, 5)
-#define MCHP_PCR_PWM0		MCHP_PCR_ERB(1, 4)
-#define MCHP_PCR_TACH0		MCHP_PCR_ERB(1, 2)
-#define MCHP_PCR_PECI		MCHP_PCR_ERB(1, 1)
-#define MCHP_PCR_ECIA		MCHP_PCR_ERB(1, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) + (0xff << 20))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-#define MCHP_PCR_SLP_EN1_TACH3		BIT(13)
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
-/* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
-/*
- * block not used by default
- * Do not sleep ECIA, PMC, CPU and ECS
- */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
-
-/* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
-#define MCHP_PCR_GLUE		MCHP_PCR_ERB(2, 29)
-#define MCHP_PCR_UART2		MCHP_PCR_ERB(2, 28)
-#define MCHP_PCR_SAF		MCHP_PCR_ERB(2, 27)
-#define MCHP_PCR_P80CAP1	MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_P80CAP0	MCHP_PCR_ERB(2, 25)
-#define MCHP_PCR_ASIF		MCHP_PCR_ERB(2, 24)
-#define MCHP_PCR_ACPI_EC3	MCHP_PCR_ERB(2, 22)
-#define MCHP_PCR_ACPI_EC2	MCHP_PCR_ERB(2, 21)
-#define MCHP_PCR_ESPI_SCR	MCHP_PCR_ERB(2, 20)
-#define MCHP_PCR_ESPI		MCHP_PCR_ERB(2, 19)
-#define MCHP_PCR_RTC		MCHP_PCR_ERB(2, 18)
-#define MCHP_PCR_MBOX		MCHP_PCR_ERB(2, 17)
-#define MCHP_PCR_8042		MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_ACPI_PM1	MCHP_PCR_ERB(2, 15)
-#define MCHP_PCR_ACPI_EC1	MCHP_PCR_ERB(2, 14)
-#define MCHP_PCR_ACPI_EC0	MCHP_PCR_ERB(2, 13)
-#define MCHP_PCR_GCFG		MCHP_PCR_ERB(2, 12)
-#define MCHP_PCR_UART1		MCHP_PCR_ERB(2, 2)
-#define MCHP_PCR_UART0		MCHP_PCR_ERB(2, 1)
-#define MCHP_PCR_EMI0		MCHP_PCR_ERB(2, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN2_GLUE		BIT(29)
-#define MCHP_PCR_SLP_EN2_UART2		BIT(28)
-#define MCHP_PCR_SLP_EN2_SAF		BIT(27)
-#define MCHP_PCR_SLP_EN2_P80CAP1	BIT(26)
-#define MCHP_PCR_SLP_EN2_P80CAP0	BIT(25)
-#define MCHP_PCR_SLP_EN2_ASIF		BIT(24)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-#define MCHP_PCR_SLP_EN2_ESPI_SCR	BIT(20)
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_EMI0		BIT(0)
-/* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0xffffffff
-
-/* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
-#define MCHP_PCR_CCT0		MCHP_PCR_ERB(3, 30)
-#define MCHP_PCR_HTMR1		MCHP_PCR_ERB(3, 29)
-#define MCHP_PCR_AESHASH	MCHP_PCR_ERB(3, 28)
-#define MCHP_PCR_RNG		MCHP_PCR_ERB(3, 27)
-#define MCHP_PCR_PKE		MCHP_PCR_ERB(3, 26)
-#define MCHP_PCR_BTMR32_1	MCHP_PCR_ERB(3, 24)
-#define MCHP_PCR_BTMR32_0	MCHP_PCR_ERB(3, 23)
-#define MCHP_PCR_I2C4		MCHP_PCR_ERB(3, 20)
-#define MCHP_PCR_LED2		MCHP_PCR_ERB(3, 18)
-#define MCHP_PCR_LED1		MCHP_PCR_ERB(3, 17)
-#define MCHP_PCR_LED0		MCHP_PCR_ERB(3, 16)
-#define MCHP_PCR_I2C3		MCHP_PCR_ERB(3, 15)
-#define MCHP_PCR_I2C2		MCHP_PCR_ERB(3, 14)
-#define MCHP_PCR_I2C1		MCHP_PCR_ERB(3, 13)
-#define MCHP_PCR_KEYSCAN	MCHP_PCR_ERB(3, 11)
-#define MCHP_PCR_HTMR0		MCHP_PCR_ERB(3, 10)
-#define MCHP_PCR_PS2_1		MCHP_PCR_ERB(3, 6)
-#define MCHP_PCR_PS2_0		MCHP_PCR_ERB(3, 5)
-#define MCHP_PCR_ADC		MCHP_PCR_ERB(3, 3)
-#define MCHP_PCR_HDMI_CEC	MCHP_PCR_ERB(3, 1)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_AESHASH	BIT(28)
-#define MCHP_PCR_SLP_EN3_RNG		BIT(27)
-#define MCHP_PCR_SLP_EN3_PKE		BIT(26)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_I2C4		BIT(20)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_PS2_1		BIT(6)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-#define MCHP_PCR_SLP_EN3_HDMI_CEC	BIT(1)
-#define MCHP_PCR_SLP_EN3_ALL_CRYPTO	(0x07 << 26)
-/* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xfffffffd
-#define MCHP_PCR_SLP_EN3_PWM_ALL	0
-
-/* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
-#define MCHP_PCR_SGPIO3		MCHP_PCR_ERB(4, 20)
-#define MCHP_PCR_SGPIO2		MCHP_PCR_ERB(4, 19)
-#define MCHP_PCR_SGPIO1		MCHP_PCR_ERB(4, 18)
-#define MCHP_PCR_SGPIO0		MCHP_PCR_ERB(4, 17)
-#define MCHP_PCR_SLV_SPI	MCHP_PCR_ERB(4, 16)
-#define MCHP_PCR_PSPI		MCHP_PCR_ERB(4, 14)
-#define MCHP_PCR_PROCHOT	MCHP_PCR_ERB(4, 13)
-#define MCHP_PCR_I2C7		MCHP_PCR_ERB(4, 12)
-#define MCHP_PCR_I2C6		MCHP_PCR_ERB(4, 11)
-#define MCHP_PCR_I2C5		MCHP_PCR_ERB(4, 10)
-#define MCHP_PCR_QMSPI		MCHP_PCR_ERB(4, 8)
-#define MCHP_PCR_RTMR		MCHP_PCR_ERB(4, 6)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN4_SGPIO3		BIT(20)
-#define MCHP_PCR_SLP_EN4_SGPIO2		BIT(19)
-#define MCHP_PCR_SLP_EN4_SGPIO1		BIT(18)
-#define MCHP_PCR_SLP_EN4_SGPIO0		BIT(17)
-#define MCHP_PCR_SLP_EN4_SLV_SPI	BIT(16)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_I2C7		BIT(12)
-#define MCHP_PCR_SLP_EN4_I2C6		BIT(11)
-#define MCHP_PCR_SLP_EN4_I2C5		BIT(10)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
-/* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN4_PWM_ALL	0
-
-/* Allow all blocks to request clocks */
-#define MCHP_PCR_SLP_EN0_WAKE	(~(MCHP_PCR_SLP_EN0_SLEEP))
-#define MCHP_PCR_SLP_EN1_WAKE	(~(MCHP_PCR_SLP_EN1_SLEEP))
-#define MCHP_PCR_SLP_EN2_WAKE	(~(MCHP_PCR_SLP_EN2_SLEEP))
-#define MCHP_PCR_SLP_EN3_WAKE	(~(MCHP_PCR_SLP_EN3_SLEEP))
-#define MCHP_PCR_SLP_EN4_WAKE	(~(MCHP_PCR_SLP_EN4_SLEEP))
-
-/* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_MASK_RO	0xc8c
-#define MCHP_PWR_RST_STS_MASK_RWC	0x170
-#define MCHP_PWR_RST_STS_MASK \
-	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
-
-#define MCHP_PWR_RST_STS_ESPI_CLK_ACT		BIT(11) /* RO */
-#define MCHP_PWR_RST_STS_32K_ACT		BIT(10) /* RO */
-#define MCHP_PWR_RST_STS_WDT			BIT(8) /* R/WC */
-#define MCHP_PWR_RST_STS_JTAG_RSTN		BIT(7) /* RO */
-#define MCHP_PWR_RST_STS_SYS			BIT(6) /* R/WC */
-#define MCHP_PWR_RST_STS_VBAT			BIT(5) /* R/WC */
-#define MCHP_PWR_RST_STS_VTR			BIT(4) /* R/WC */
-#define MCHP_PWR_RST_STS_HOST			BIT(3) /* RO */
-#define MCHP_PWR_RST_STS_VCC_PWRGD		BIT(2) /* RO */
-
-/* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_PCI_RESET		BIT(8)
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	(0 << 8)
-#define MCHP_PCR_PWR_OK_INV_BITPOS		0
-
-/* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET			BIT(8)
-
-/* EC Subsystem */
-#define MCHP_EC_AHB_ERR				REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO				REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN			REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL			REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN			REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN				REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT				REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_AES_SHA_SWAP_CTRL		REG8(MCHP_EC_BASE + 0x2c)
-#define MCHP_EC_VCI_FW_OVRD			REG8(MCHP_EC_BASE + 0x50)
-#define MCHP_EC_CRYPTO_SRESET			REG8(MCHP_EC_BASE + 0x5c)
-#define MCHP_EC_GPIO_BANK_PWR			REG8(MCHP_EC_BASE + 0x64)
-#define MCHP_EC_SLP_STS_MIRROR			REG8(MCHP_EC_BASE + 0x114)
-
-/* AHB ERR Enable bit[0]=0(enable), 1(disable) */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
-
-/* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE	0x01
-/* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN	0x00
-/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV	0x02
-/* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD	0x04
-
-/* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */
-#define MCHP_CRYPTO_NDRNG_SRST		0x01
-#define MCHP_CRYPTO_PKE_SRST		0x02
-#define MCHP_CRYPTO_AES_SHA_SRST	0x04
-#define MCHP_CRYPTO_ALL_SRST		0x07
-
-/* MCHP_GPIO_BANK_PWR bit definitions */
-#define MCHP_EC_GPIO_BANK_PWR_MASK	0x86
-#define MCHP_EC_GPIO_BANK_PWR_VTR2_18	0x02
-#define MCHP_EC_GPIO_BANK_PWR_VTR3_18	0x04
-#define MCHP_EC_GPIO_BANK_PWR_LOCK	0x80
-
-/* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_GIRQ_LEN		20 /* 5 32-bit registers */
-#define MCHP_INT_GIRQ_FIRST		8
-#define MCHP_INT_GIRQ_LAST		26
-#define MCHP_INT_GIRQ_NUM		(26-8+1)
-/* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
-#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN))
-
-/*
- * GPIO GIRQ's are not direct capable
- * GIRQ08 GPIO 0140 - 0176
- * GIRQ09 GPIO 0100 - 0136
- * GIRQ10 GPIO 040 - 076
- * GIRQ11 GPIO 000 - 036
- * GIRQ12 GPIO 0200 - 0236
- * GIRQ26 GPIO 0240 - 0276
- * Other GIRQ's not direct capable:
- * GIRQ22 wake peripheral clock only
- * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
- */
-#define MCHP_INT_AGGR_ONLY_BITMAP	0x07401F00U
-#define MCHP_INT_DIRECT_CAPABLE_BITMAP	0x00BFE000U
-
-/* GIRQ13 I2C controllers. Direct capable */
-#define MCHP_INT13_I2C(x) (1ul << (x))
-
-/* GIRQ14 DMA channels 0 - 11. Direct capable */
-#define MCHP_INT14_DMA(x) (1ul << (x))
-
-/* GIQ15 interrupt sources. Direct capable */
-#define MCHP_INT15_UART_0		BIT(0)
-#define MCHP_INT15_UART_1		BIT(1)
-#define MCHP_INT15_UART_2		BIT(4)
-#define MCHP_INT15_EMI_0		BIT(2)
-#define MCHP_INT15_EMI_1		BIT(3)
-#define MCHP_INT15_ACPI_EC0_IBF		BIT(5)
-#define MCHP_INT15_ACPI_EC0_OBE		BIT(6)
-#define MCHP_INT15_ACPI_EC1_IBF		BIT(7)
-#define MCHP_INT15_ACPI_EC1_OBE		BIT(8)
-#define MCHP_INT15_ACPI_EC2_IBF		BIT(9)
-#define MCHP_INT15_ACPI_EC2_OBE		BIT(10)
-#define MCHP_INT15_ACPI_EC3_IBF		BIT(11)
-#define MCHP_INT15_ACPI_EC3_OBE		BIT(12)
-#define MCHP_INT15_ACPI_PM1_CTL		BIT(15)
-#define MCHP_INT15_ACPI_PM1_EN		BIT(16)
-#define MCHP_INT15_ACPI_PM1_STS		BIT(17)
-#define MCHP_INT15_8042_OBE		BIT(18)
-#define MCHP_INT15_8042_IBF		BIT(19)
-#define MCHP_INT15_MAILBOX		BIT(20)
-#define MCHP_INT15_P80_0		BIT(22)
-#define MCHP_INT15_P80_1		BIT(23)
-#define MCHP_INT15_P80(x)		BIT(22 + ((x) & 0x01U))
-
-/* GIRQ16 interrupt sources. Direct capable */
-#define MCHP_INT16_PKE_ERR		BIT(0)
-#define MCHP_INT16_PKE_DONE		BIT(1)
-#define MCHP_INT16_RNG_DONE		BIT(2)
-#define MCHP_INT16_AES_DONE		BIT(3)
-#define MCHP_INT16_HASH_DONE		BIT(4)
-
-/* GIR17 interrupt sources. Direct capable */
-#define MCHP_INT17_PECI			BIT(0)
-#define MCHP_INT17_TACH_0		BIT(1)
-#define MCHP_INT17_TACH_1		BIT(2)
-#define MCHP_INT17_TACH_2		BIT(3)
-#define MCHP_INT17_TACH_3		BIT(4)
-#define MCHP_INT17_HDMI_CEC		BIT(5)
-#define MCHP_INT17_ADC_SINGLE		BIT(8)
-#define MCHP_INT17_ADC_REPEAT		BIT(9)
-#define MCHP_INT17_LED_WDT_0		BIT(13)
-#define MCHP_INT17_LED_WDT_1		BIT(14)
-#define MCHP_INT17_LED_WDT_2		BIT(15)
-#define MCHP_INT17_PROCHOT		BIT(17)
-
-/* GIRQ18 interrupt sources. Direct capable */
-#define MCHP_INT18_SLV_SPI		BIT(0)
-#define MCHP_INT18_QMSPI		BIT(1)
-#define MCHP_INT18_PS2_0		BIT(10)
-#define MCHP_INT18_PS2_1		BIT(11)
-#define MCHP_INT18_CCT			BIT(20)
-#define MCHP_INT18_CCT_CAP0		BIT(21)
-#define MCHP_INT18_CCT_CAP1		BIT(22)
-#define MCHP_INT18_CCT_CAP2		BIT(23)
-#define MCHP_INT18_CCT_CAP3		BIT(24)
-#define MCHP_INT18_CCT_CAP4		BIT(25)
-#define MCHP_INT18_CCT_CAP6		BIT(26)
-#define MCHP_INT18_CCT_CMP0		BIT(27)
-#define MCHP_INT18_CCT_CMP1		BIT(28)
-
-/* GIRQ19 interrupt sources. Direct capable */
-#define MCHP_INT19_ESPI_PC		BIT(0)
-#define MCHP_INT19_ESPI_BM1		BIT(1)
-#define MCHP_INT19_ESPI_BM2		BIT(2)
-#define MCHP_INT19_ESPI_LTR		BIT(3)
-#define MCHP_INT19_ESPI_OOB_TX		BIT(4)
-#define MCHP_INT19_ESPI_OOB_RX		BIT(5)
-#define MCHP_INT19_ESPI_FC		BIT(6)
-#define MCHP_INT19_ESPI_RESET		BIT(7)
-#define MCHP_INT19_ESPI_VW_EN		BIT(8)
-#define MCHP_INT19_ESPI_SAF		BIT(9)
-#define MCHP_INT19_ESPI_SAF_ERR		BIT(10)
-
-/* GIRQ20 interrupt sources. Direct capable */
-#define MCHP_INT20_OPT			BIT(3)
-
-/* GIRQ21 interrupt sources. Direct capable */
-#define MCHP_INT21_WDT			BIT(2)
-#define MCHP_INT21_WEEK_ALARM		BIT(3)
-#define MCHP_INT21_WEEK_SUB		BIT(4)
-#define MCHP_INT21_WEEK_1SEC		BIT(5)
-#define MCHP_INT21_WEEK_1SEC_SUB	BIT(6)
-#define MCHP_INT21_WEEK_PWR_PRES	BIT(7)
-#define MCHP_INT21_RTC			BIT(8)
-#define MCHP_INT21_RTC_ALARM		BIT(9)
-#define MCHP_INT21_VCI_OVRD		BIT(10)
-#define MCHP_INT21_VCI_IN0		BIT(11)
-#define MCHP_INT21_VCI_IN1		BIT(12)
-#define MCHP_INT21_VCI_IN2		BIT(13)
-#define MCHP_INT21_VCI_IN3		BIT(14)
-#define MCHP_INT21_PS2_0A_WAKE		BIT(18)
-#define MCHP_INT21_PS2_0B_WAKE		BIT(19)
-#define MCHP_INT21_PS2_1B_WAKE		BIT(21)
-#define MCHP_INT21_KEYSCAN		BIT(25)
-
-/* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
-#define MCHP_INT22_WAKE_ONLY_SLV_SPI	BIT(0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	BIT(1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	BIT(2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	BIT(3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	BIT(4)
-#define MCHP_INT22_WAKE_ONLY_I2C4	BIT(5)
-#define MCHP_INT22_WAKE_ONLY_I2C5	BIT(6)
-#define MCHP_INT22_WAKE_ONLY_I2C6	BIT(7)
-#define MCHP_INT22_WAKE_ONLY_I2C7	BIT(8)
-#define MCHP_INT22_WAKE_ONLY_ESPI	BIT(9)
-
-/* GIRQ23 sources. Direct capable */
-#define MCHP_INT23_BTMR16_0		BIT(0)
-#define MCHP_INT23_BTMR16_1		BIT(1)
-#define MCHP_INT23_BTMR32_0		BIT(4)
-#define MCHP_INT23_BTMR32_1		BIT(5)
-#define MCHP_INT23_RTMR			BIT(10)
-#define MCHP_INT23_HTMR_0		BIT(16)
-#define MCHP_INT23_HTMR_1		BIT(17)
-
-/* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
-#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
-
-/* GIRQ25 sources Master-to-Slave v=[7:10], Source=[0:3] */
-#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
-
-/* UART Peripheral 0 <= x <= 2 */
-#define MCHP_UART_INSTANCES		3
-#define MCHP_UART_SPACING		0x400
-#define MCHP_UART_CFG_OFS		0x300
-#define MCHP_UART_CONFIG_BASE(x) \
-	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_RUNTIME_BASE(x) \
-	(MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_GIRQ			15
-#define MCHP_UART0_GIRQ_BIT		(MCHP_INT15_UART_0)
-#define MCHP_UART1_GIRQ_BIT		(MCHP_INT15_UART_1)
-#define MCHP_UART2_GIRQ_BIT		(MCHP_INT15_UART_2)
-#define MCHP_UART_GIRQ_BIT(x)		BIT(x)
-/* BIT defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY		BIT(5)
-
-/*
- * GPIO
- * MCHP each Port contains 32 GPIO's.
- * GPIO Control 1 registers are 32-bit registers starting at
- * MCHP_GPIO_BASE.
- * index = octal GPIO number from MCHP specification.
- * port/bank = index >> 5
- * id = index & 0x1F
- *
- * The port/bank, id pair may also be used to access GPIO's via
- * parallel I/O registers if GPIO control is configured for
- * parallel I/O.
- *
- * From ec/chip/mec1701/config_chip.h
- * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
- *
- * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
- *
- * Example: GPIO043, Control 1 register address = 0x4008108c
- * port/bank = 0x23 >> 5 = 1
- * id        = 0x23 & 0x1F = 0x03
- * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
- *
- * Example: GPIO235, Control 1 register address = 0x40081274
- * port/bank = 0x9d >> 5   = 4
- * id        = 0x9d & 0x1f = 0x1d
- * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
- */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
-
-/* MCHP implements 6 GPIO ports */
-#define MCHP_GPIO_MAX_PORT 6
-#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT
-
-/*
- * In MECxxxx documentation GPIO numbers are octal, each control
- * register is located on a 32-bit boundary.
- */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
-
-/*
- * GPIO control register bit fields
- */
-#define MCHP_GPIO_CTRL_PUD_BITPOS		0
-#define MCHP_GPIO_CTRL_PUD_MASK0		0x03
-#define MCHP_GPIO_CTRL_PUD_MASK			0x03
-#define MCHP_GPIO_CTRL_PUD_NONE			0x00
-#define MCHP_GPIO_CTRL_PUD_PU			0x01
-#define MCHP_GPIO_CTRL_PUD_PD			0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER		0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS		2
-#define MCHP_GPIO_CTRL_PWR_MASK0		0x03
-#define MCHP_GPIO_CTRL_PWR_MASK			(0x03 << 2)
-#define MCHP_GPIO_CTRL_PWR_VTR			(0x00 << 2)
-#define MCHP_GPIO_CTRL_PWR_OFF			(0x02 << 2)
-#define MCHP_GPIO_INTDET_MASK			0xF0
-#define MCHP_GPIO_INTDET_LVL_LO			0x00
-#define MCHP_GPIO_INTDET_LVL_HI			0x10
-#define MCHP_GPIO_INTDET_DISABLED		0x40
-#define MCHP_GPIO_INTDET_EDGE_RIS		0xD0
-#define MCHP_GPIO_INTDET_EDGE_FALL		0xE0
-#define MCHP_GPIO_INTDET_EDGE_BOTH		0xF0
-#define MCHP_GPIO_INTDET_EDGE_EN		BIT(7)
-#define MCHP_GPIO_PUSH_PULL			0u
-#define MCHP_GPIO_OPEN_DRAIN			BIT(8)
-#define MCHP_GPIO_INPUT				0u
-#define MCHP_GPIO_OUTPUT			BIT(9)
-#define MCHP_GPIO_OUTSET_CTRL			0u
-#define MCHP_GPIO_OUTSEL_PAR			BIT(10)
-#define MCHP_GPIO_POLARITY_NINV			0u
-#define MCHP_GPIO_POLARITY_INV			BIT(11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS		12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0		0x0F
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK		(0x0F << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO		(0 << 12)
-#define MCHP_GPIO_CTRL_FUNC_1			(1 << 12)
-#define MCHP_GPIO_CTRL_FUNC_2			(2 << 12)
-#define MCHP_GPIO_CTRL_FUNC_3			(3 << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL			BIT(16)
-/* MEC15xx only */
-#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS		15
-#define MCHP_GPIO_CTRL_DIS_INPUT_BIT		BIT(15)
-
-/*
- * GPIO Parallel Input and Output registers.
- * gpio_bank in [0, 5]
- */
-#define MCHP_GPIO_PARIN(bank) \
-	REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
-#define MCHP_GPIO_PAROUT(bank) \
-	REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
-
-/* Basic timers */
-#define MCHP_TMR_SPACING		0x20
-#define MCHP_TMR16_INSTANCES		2
-#define MCHP_TMR32_INSTANCES		2
-#define MCHP_TMR16_MAX			(MCHP_TMR16_INSTANCES)
-#define MCHP_TMR32_MAX			(MCHP_TMR32_INSTANCES)
-#define MCHP_TMR16_BASE(n)	\
-	(MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR32_BASE(n)	\
-	(MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR16_GIRQ			23
-#define MCHP_TMR16_GIRQ_BIT(n)		BIT(0 + (n))
-#define MCHP_TMR32_GIRQ			23
-#define MCHP_TMR32_GIRQ_BIT(n)		BIT(4 + (n))
-
-/* RTimer */
-#define MCHP_RTMR_GIRQ			23
-#define MCHP_RTMR_GIRQ_BIT(x)		BIT(10)
-
-/* Watchdog */
-/* MEC152x specific registers */
-#define MCHP_WDG_STATUS			REG32(MCHP_WDG_BASE + 0x10)
-#define MCHP_WDG_IEN			REG32(MCHP_WDG_BASE + 0x14)
-/* Status */
-#define MCHP_WDG_STS_IRQ		BIT(0)
-/* Interrupt enable */
-#define MCHP_WDG_IEN_IRQ_EN		BIT(0)
-#define MCHP_WDG_GIRQ			21
-#define MCHP_WDG_GIRQ_BIT		BIT(2)
-/* Control register has a bit to enable IRQ generation */
-#define MCHP_WDG_RESET_IRQ_EN		BIT(9)
-
-/* VBAT */
-#define MCHP_VBAT_STS			REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CE			REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_SHDN_DIS		REG32(MCHP_VBAT_BASE + 0xC)
-#define MCHP_VBAT_MONOTONIC_CTR_LO	REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI	REG32(MCHP_VBAT_BASE + 0x24)
-/* read 32-bit word at 32-bit offset x where 0 <= x <= 16 */
-#define MCHP_VBAT_RAM_SIZE		64
-#define MCHP_VBAT_RAM(wnum)		REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4))
-#define MCHP_VBAT_RAM8(bnum)		REG8(MCHP_VBAT_RAM_BASE + (bnum))
-#define MCHP_VBAT_VWIRE_BACKUP		14
-/*
- * Miscellaneous firmware control fields
- * scratch pad index cannot be more than 32 as
- * MEC152x has 64 bytes = 16 words of scratch pad RAM
- */
-#define MCHP_IMAGETYPE_IDX	15
-
-/* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT		BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		0xF4u
-
-/* Bit definitions for MCHP_VBAT_CE */
-#define MCHP_VBAT_CE_XOSEL_BITPOS	3
-#define MCHP_VBAT_CE_XOSEL_MASK		BIT(3)
-#define MCHP_VBAT_CE_XOSEL_PAR		0
-#define MCHP_VBAT_CE_XOSEL_SE		BIT(3)
-
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS		2
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK		BIT(2)
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT		0
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL		BIT(2)
-
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS		1
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK		BIT(1)
-#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON		0
-#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN		BIT(1)
-
-/* Blinking-Breathing LED 0 <= n <= 2 */
-#define MCHP_BBLEB_INSTANCES	3
-#define MCHP_BBLED_BASE(n)	(MCHP_BBLED_0_BASE + (((n) & 0x03) * 256))
-
-/* EMI */
-#define MCHP_EMI_INSTANCES	2
-#define MCHP_EMI_SPACING	0x400
-#define MCHP_EMI_ECREG_OFS	0x100
-/* base of EMI registers only accessible by EC */
-#define MCHP_EMI_BASE(n) \
-	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING))
-/* base of EMI registers accessible by EC and Host */
-#define MCHP_EMI_RT_BASE(n)	(MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING))
-#define MCHP_EMI_GIRQ		15
-#define MCHP_EMI_GIRQ_BIT(n)	BIT(2 + (n))
-
-/* Mailbox */
-#define MCHP_MBX_ECREGS_OFS	0x100
-#define MCHP_MBX_RT_BASE	MCHP_MBOX_BASE
-#define MCHP_MBX_BASE		(MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	BIT(20)
-
-/* Port 80 Capture */
-#define MCHP_P80_SPACING	0x400
-#define MCHP_P80_BASE(n)	\
-	(MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING)))
-#define MCHP_P80_HOST_DATA(n)	REG8(MCHP_P80_BASE(n))
-/* Data capture with time stamp register */
-#define MCHP_P80_CAP(n)		REG32(MCHP_P80_BASE(n) + 0x100)
-#define MCHP_P80_CFG(n)		REG8(MCHP_P80_BASE(n) + 0x104)
-#define MCHP_P80_STS(n)		REG8(MCHP_P80_BASE(n) + 0x108)
-#define MCHP_P80_CNT(n)		REG32(MCHP_P80_BASE(n) + 0x10c)
-#define MCHP_P80_CNT_GET(n)	(REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
-#define MCHP_P80_CNT_SET(n, c)	\
-	(REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
-#define MCHP_P80_ACTIVATE(n)	REG8(MCHP_P80_BASE(n) + 0x330)
-#define MCHP_P80_GIRQ		15
-#define MCHP_P80_GIRQ_BIT(n)	BIT(22 + (n))
-/*
- * Port 80 Data register bits
- * bits[7:0] = data captured on Host write
- * bits[31:8] = optional time stamp
- */
-#define MCHP_P80_CAP_DATA_MASK		0xFFul
-#define MCHP_P80_CAP_TS_BITPOS		8
-#define MCHP_P80_CAP_TS_MASK0		0xfffffful
-#define MCHP_P80_CAP_TS_MASK		\
-	((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS))
-
-/* Port 80 Configuration register bits */
-#define MCHP_P80_FLUSH_FIFO_WO		BIT(1)
-#define MCHP_P80_RESET_TIMESTAMP_WO	BIT(2)
-#define MCHP_P80_TIMEBASE_BITPOS	3
-#define MCHP_P80_TIMEBASE_MASK0		0x03
-#define MCHP_P80_TIMEBASE_MASK		\
-	((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_750KHZ	\
-	(0x03 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_1500KHZ	\
-	(0x02 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_3MHZ		\
-	(0x01 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_6MHZ		\
-	(0x00 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMER_ENABLE		BIT(5)
-#define MCHP_P80_FIFO_THRHOLD_MASK	(3u << 6)
-#define MCHP_P80_FIFO_THRHOLD_1		0u
-#define MCHP_P80_FIFO_THRHOLD_4		(1u << 6)
-#define MCHP_P80_FIFO_THRHOLD_8		(2u << 6)
-#define MCHP_P80_FIFO_THRHOLD_14	(3u << 6)
-#define MCHP_P80_FIFO_LEN		16
-/* Port 80 Status register bits, read-only */
-#define MCHP_P80_STS_NOT_EMPTY		BIT(0)
-#define MCHP_P80_STS_OVERRUN		BIT(1)
-/* Port 80 Count register bits */
-#define MCHP_P80_CNT_BITPOS		8
-#define MCHP_P80_CNT_MASK0		0xfffffful
-#define MCHP_P80_CNT_MASK	\
-	((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS))
-
-/* PWM */
-#define MCHP_PWM_INSTANCES	9
-#define MCHP_PWM_ID_MAX		(MCHP_PWM_INSTANCES)
-#define MCHP_PWM_SPACING	16
-#define MCHP_PWM_BASE(x)	(MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING))
-
-/* TACH */
-#define MCHP_TACH_INSTANCES	4
-#define MCHP_TACH_SPACING	16
-#define MCHP_TACH_BASE(x)	\
-	(MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING))
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	BIT(1 + (x))
-
-/* ACPI EC */
-#define MCHP_ACPI_EC_INSTANCES	4
-#define MCHP_ACPI_EC_MAX	(ACPI_EC_INSTANCES)
-#define MCHP_ACPI_EC_SPACING	0x400
-#define MCHP_ACPI_EC_BASE(x) \
-	(MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING))
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	BIT(5 + ((x) * 2))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	BIT(6 + ((x) * 2))
-
-/* ACPI PM1 */
-#define MCHP_ACPI_PM1_ECREGS_OFS	0x100
-#define MCHP_ACPI_PM_RT_BASE		MCHP_ACPI_PM1_BASE
-#define MCHP_ACPI_PM_EC_BASE		\
-	(MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	BIT(15)
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	BIT(16)
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	BIT(17)
-
-/* 8042 */
-#define MCHP_8042_ECREGS_OFS		0x100
-#define MCHP_8042_GIRQ			15
-#define MCHP_8042_OBE_GIRQ_BIT		BIT(18)
-#define MCHP_8042_IBF_GIRQ_BIT		BIT(19)
-
-/*
- * I2C controllers 0 - 4 include SMBus network layer functionality.
- * I2C controllers 5 - 7 are I2C only and include slave mode
- * promiscuous functionality.
- */
-#define MCHP_I2C_CTRL0		0
-#define MCHP_I2C_CTRL1		1
-#define MCHP_I2C_CTRL2		2
-#define MCHP_I2C_CTRL3		3
-#define MCHP_I2C_CTRL4		4
-#define MCHP_I2C_CTRL5		5
-#define MCHP_I2C_CTRL6		6
-#define MCHP_I2C_CTRL7		7
-#define MCHP_I2C_CTRL_MAX	8
-
-#define MCHP_I2C_SEP0		0x400
-#define MCHP_I2C_SEP1		0x100
-
-/*
- * MEC152xH 144-pin package has eight I2C controllers and sixteen ports.
- * Any port can be mapped to any I2C controller.
- *
- * I2C port values must be zero based consecutive whole numbers due to
- * port number used as an index for I2C mutex array, etc.
- *
- * Refer to chip i2c_port_to_controller function for mapping
- * of port to controller.
- *
- * Locking must occur by-controller (not by-port).
- * I2C00_SCL/SDA on GPIO004 F1, GPIO003 F1
- * I2C01_SCL/SDA on GPIO0131 F1, GPIO130 F1
- *	Alternate pins: GPIO073 F2, GPIO072 F2
- * I2C02_SCL/SDA on GPIO0155 F1, GPIO0154 F1
- * I2C03_SCL/SDA on GPIO010 F1, GPIO007 F1
- * I2C04_SCL/SDA on GPIO0144 F1, GPIO0143 F1
- * I2C05_SCL/SDA on GPIO0142 F1, GPIO0141 F1
- * I2C06_SCL/SDA on GPIO0140 F1, GPIO0132 F1
- * I2C07_SCL/SDA on GPIO013 F1, GPIO012 F1
- *	Alternate pins: GPIO0024 F3, GPIO0152 F3
- * I2C08_SCL/SDA on GPIO012 F1, GPIO0211 F1
- * I2C09_SCL/SDA on GPIO0146 F1, GPIO0145 F1
- * I2C10_SCL/SDA on GPIO0107 F3, GPIO030 F2
- * I2C11_SCL/SDA on GPIO062 F2, GPIO000 F3
- * I2C12_SCL/SDA on GPIO027 F3, GPIO026 F3
- * I2C13_SCL/SDA on GPIO065 F2, GPIO066 F2
- * I2C14_SCL/SDA on GPIO071 F2, GPIO070 F2
- * I2C15_SCL/SDA on GPIO0150 F1, GPIO0147 F1
- */
-
-#define MCHP_MEC1521SZ_I2C_PORT_MASK	0xFEFFul
-#define MCHP_MEC1523SZ_I2C_PORT_MASK	0xFFFFul
-
-#define MCHP_I2C_PORT_MASK	MCHP_MEC1521SZ_I2C_PORT_MASK
-
-enum MCHP_i2c_port {
-	MCHP_I2C_PORT0 = 0,
-	MCHP_I2C_PORT1,
-	MCHP_I2C_PORT2,
-	MCHP_I2C_PORT3,
-	MCHP_I2C_PORT4,
-	MCHP_I2C_PORT5,
-	MCHP_I2C_PORT6,
-	MCHP_I2C_PORT7,
-	MCHP_I2C_PORT8,
-	MCHP_I2C_PORT9,
-	MCHP_I2C_PORT10,
-	MCHP_I2C_PORT11,
-	MCHP_I2C_PORT12,
-	MCHP_I2C_PORT13,
-	MCHP_I2C_PORT14,
-	MCHP_I2C_PORT15,
-	MCHP_I2C_PORT_COUNT,
-};
-
-/* I2C ports & Configs */
-#define I2C_CONTROLLER_COUNT	MCHP_I2C_CTRL_MAX
-#define I2C_PORT_COUNT		MCHP_I2C_PORT_COUNT
-
-/*
- * I2C controllers 0-4 implement network layer hardware.
- * I2C controllers 5-7 do include network layer hardware.
- * MEC152x has I2C promiscuous mode feature in the following
- * additional registers.
- */
-#define MCHP_I2C_SLAVE_ADDR(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x6c))
-#define MCHP_I2C_PROM_INTR(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x70))
-#define MCHP_I2C_PROM_INTR_EN(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x74))
-#define MCHP_I2C_PROM_CTRL(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x78))
-
-/* All I2C controllers connected to GIRQ13 */
-#define MCHP_I2C_GIRQ		13
-/* I2C[0:7] -> GIRQ13 bits[0:7] */
-#define MCHP_I2C_GIRQ_BIT(n)	BIT((n))
-
-/* Keyboard scan matrix */
-#define MCHP_KS_GIRQ			21
-#define MCHP_KS_GIRQ_BIT		BIT(25)
-#define MCHP_KS_DIRECT_NVIC		135
-
-/* ADC */
-#define MCHP_ADC_GIRQ				17
-#define MCHP_ADC_GIRQ_SINGLE_BIT		BIT(8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT		BIT(9)
-#define MCHP_ADC_SINGLE_DIRECT_NVIC		78
-#define MCHP_ADC_REPEAT_DIRECT_NVIC		79
-
-/* Hibernation timer */
-#define MCHP_HTIMER_SPACING			0x20
-#define MCHP_HTIMER_ADDR(n)		\
-	(MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING))
-#define MCHP_HTIMER_GIRQ			23
-/* HTIMER[0:1] -> GIRQ23 bits[16:17] */
-#define MCHP_HTIMER_GIRQ_BIT(n)			BIT(16 + (n))
-#define MCHP_HTIMER_DIRECT_NVIC(n)		(112 + (n))
-
-/*
- * Quad Master SPI (QMSPI)
- * MEC152x implements 16 descriptors, support for two chip selects,
- * and additional SPI signal timing registers.
- */
-#define MCHP_QMSPI_MAX_DESCR	16
-/*
- * Chip select implemented in bit[13:12] of the Mode register.
- * These bits are reserved in earlier chips.
- */
-#define MCHP_QMSPI_M_CS_POS	12
-#define MCHP_QMSPI_M_CS_MASK0	0x03
-#define MCHP_QMSPI_M_CS_MASK	(0x03 << MCHP_QMSPI_M_CS_POS)
-#define MCHP_QMSPI_M_CS0	(0x00 << MCHP_QMSPI_M_CS_POS)
-#define MCHP_QMSPI_M_CS1	(0x01 << MCHP_QMSPI_M_CS_POS)
-
-/* New QMSPI chip select timing register */
-#define MCHP_QMSPI_CS_TIMING			\
-	REG32(MCHP_QMSPI0_BASE + 0x28)
-#define MCHP_QMSPI_CST_DFLT_VAL			0x06060406
-#define MCHP_QMSPI_CST_ON2CLK_MASK		0x0f
-#define MCHP_QMSPI_CST_ON2CLK_DFLT		0x06
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_POS		8
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK0	0x0f
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK		0x0f00
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_DFLT		0x0400
-#define MCHP_QMSPI_CST_DLY_LDH_POS		16
-#define MCHP_QMSPI_CST_DLY_LDH_MASK0		0x0f
-#define MCHP_QMSPI_CST_DLY_LDH_MASK		0xf0000
-#define MCHP_QMSPI_CST_DLY_LDH_DFLT		0x60000
-#define MCHP_QMSPI_CST_DLY_OFF2ON_POS		24
-#define MCHP_QMSPI_CST_DLY_OFF2ON_DFLT		0x06000000
-#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK0		0xff
-#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK		0xff000000
-
-#define MCHP_QMSPI_GIRQ		18
-#define MCHP_QMSPI_GIRQ_BIT	BIT(1)
-#define MCHP_QMSPI_DIRECT_NVIC	91
-
-/* eSPI */
-
-/* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_P80_0		0x10
-#define MCHP_ESPI_IO_BAR_P80_1		0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
-#define MCHP_ESPI_IO_BAR_ID_UART2	0x15
-
-/* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
-#define MCHP_ESPI_MBAR_ID_MBOX		0
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_0	1
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_1	2
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_2	3
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_3	4
-#define MCHP_ESPI_MBAR_ID_EMI_0		6
-#define MCHP_ESPI_MBAR_ID_EMI_1		7
-
-/* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
-#define MCHP_ESPI_SIRQ_MBOX		0 /* Host SIRQ */
-#define MCHP_ESPI_SIRQ_MBOX_SMI		1 /* Host SMI */
-#define MCHP_ESPI_SIRQ_8042_KB		2 /* KIRQ */
-#define MCHP_ESPI_SIRQ_8042_MS		3 /* MIRQ */
-#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF	4
-#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF	5
-#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF	6
-#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF	7
-#define MCHP_ESPI_SIRQ_UART0		9
-#define MCHP_ESPI_SIRQ_UART1		10
-#define MCHP_ESPI_SIRQ_EMI0_HEV		11 /* Host Event */
-#define MCHP_ESPI_SIRQ_EMI0_EC2H	12 /* EC to Host */
-#define MCHP_ESPI_SIRQ_EMI1_HEV		13
-#define MCHP_ESPI_SIRQ_EMI1_EC2H	14
-#define MCHP_ESPI_SIRQ_RTC		17
-#define MCHP_ESPI_SIRQ_EC		18
-#define MCHP_ESPI_SIRQ_UART2		19
-
-#define MCHP_ESPI_MSVW_BASE	(MCHP_ESPI_VW_BASE)
-#define MCHP_ESPI_SMVW_BASE	((MCHP_ESPI_VW_BASE) + 0x200ul)
-
-/*
- * eSPI RESET, channel enables and operations except Master-to-Slave
- * WWires are all on GIRQ19
- */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		BIT(0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		BIT(1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		BIT(2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		BIT(3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	BIT(4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	BIT(5)
-#define MCHP_ESPI_FC_GIRQ_BIT		BIT(6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	BIT(7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	BIT(8)
-#define MCHP_ESPI_SAF_DONE_GIRQ_BIT	BIT(9)
-#define MCHP_ESPI_SAF_ERR_GIRQ_BIT	BIT(10)
-
-/*
- * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25
- */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
-/*
- * Four source bits, SRC[0:3] per Master-to-Slave register
- * v = MSVW [0:10]
- * n = VWire SRC bit = [0:3]
- */
-#define MCHP_ESPI_MSVW_GIRQ(v)		(24 + ((v) > 6 ? 1 : 0))
-
-#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
-
-
-/* DMA */
-#define MCHP_DMA_MAX_CHAN	12
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
-#define MCHP_DMA_CH_BASE	(MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
-
-/*
- * Available DMA channels.
- * On MCHP, any DMA channel may serve any device. Since we have
- * 12 channels and 12 devices request signals, we make each channel
- * dedicated to the device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MCHP_DMAC_I2C0_SLAVE = 0,
-	MCHP_DMAC_I2C0_MASTER,
-	MCHP_DMAC_I2C1_SLAVE,
-	MCHP_DMAC_I2C1_MASTER,
-	MCHP_DMAC_I2C2_SLAVE,
-	MCHP_DMAC_I2C2_MASTER,
-	MCHP_DMAC_I2C3_SLAVE,
-	MCHP_DMAC_I2C3_MASTER,
-	MCHP_DMAC_I2C4_SLAVE,
-	MCHP_DMAC_I2C4_MASTER,
-	MCHP_DMAC_QMSPI0_TX,
-	MCHP_DMAC_QMSPI0_RX,
-	/* Channel count */
-	MCHP_DMAC_COUNT,
-};
-
-/*
- * Peripheral device DMA Device ID's for bits [15:9]
- * in DMA channel control register.
- */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_I2C4_SLV_REQ_ID	8
-#define MCHP_DMA_I2C4_MTR_REQ_ID	9
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	10
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	11
-
-/*
- * Hardware delay register.
- * Write of 0 <= n <= 31 will stall the Cortex-M4
- * for n+1 microseconds. Interrupts will not be
- * serviced during the delay period. Reads have
- * no effect.
- */
-#define MCHP_USEC_DELAY_REG_ADDR	0x10000000
-#define MCHP_USEC_DELAY(x)		(REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
-
-#endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers-mec1701.h b/chip/mchp/registers-mec1701.h
deleted file mode 100644
index bfe012a0d8..0000000000
--- a/chip/mchp/registers-mec1701.h
+++ /dev/null
@@ -1,1350 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for Microchip MEC170x family controllers
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/*
- * IRQ Numbers
- * NOTE: GIRQ22 aggregated output and its sources are not connected to
- * the NVIC.
- */
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
-/* GIRQ13 direct sources */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
-/* GIRQ14 direct sources */
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
-#define MCHP_IRQ_DMA_12		36
-#define MCHP_IRQ_DMA_13		37
-/* GIRQ15 direct sources */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_EMI2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIEC4_IBF	53
-#define MCHP_IRQ_ACPIEC4_OBE	54
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-#define MCHP_IRQ_PORT80DBG0	62
-#define MCHP_IRQ_PORT80DBG1	63
-/* GIRQ16 direct sources */
-#define MCHP_IRQ_PKE_ERR	65
-#define MCHP_IRQ_PKE_END	66
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AES		68
-#define MCHP_IRQ_HASH		69
-/* GIRQ17 direct sources */
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_FAN0_FAIL	74
-#define MCHP_IRQ_FAN0_STALL	75
-#define MCHP_IRQ_FAN1_FAIL	76
-#define MCHP_IRQ_FAN1_STALL	77
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_RCID0		80
-#define MCHP_IRQ_RCID1		81
-#define MCHP_IRQ_RCID2		82
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_LED3_WDT	86
-#define MCHP_IRQ_PHOT		87
-#define MCHP_IRQ_PWRGRD0	88
-#define MCHP_IRQ_PWRGRD1	89
-/* GIRQ18 direct sources */
-#define MCHP_IRQ_LPC		90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_SPI0_TX	92
-#define MCHP_IRQ_SPI0_RX	93
-#define MCHP_IRQ_SPI1_TX	94
-#define MCHP_IRQ_SPI1_RX	95
-#define MCHP_IRQ_BCM0_ERR	96
-#define MCHP_IRQ_BCM0_BUSY	97
-#define MCHP_IRQ_BCM1_ERR	98
-#define MCHP_IRQ_BCM1_BUSY	99
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_PS2_1		101
-#define MCHP_IRQ_PS2_2		102
-#define MCHP_IRQ_EEPROM		155
-/* GIRQ19 direct sources */
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_ESPI_VW_EN	156
-/* GIRQ21 direct sources */
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_VCI_IN4	126
-#define MCHP_IRQ_VCI_IN5	127
-#define MCHP_IRQ_VCI_IN6	128
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_PS21A_WAKE	131
-#define MCHP_IRQ_PS21B_WAKE	132
-#define MCHP_IRQ_PS2_2_WAKE	133
-#define MCHP_IRQ_ENVMON		134
-#define MCHP_IRQ_KSC_INT	135
-/* GIRQ23 direct sources */
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER16_2	138
-#define MCHP_IRQ_TIMER16_3	139
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_CNTR_TM0	142
-#define MCHP_IRQ_CNTR_TM1	143
-#define MCHP_IRQ_CNTR_TM2	144
-#define MCHP_IRQ_CNTR_TM3	145
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
-/* Must match CONFIG_IRQ_COUNT in config_chip.h */
-#define MCHP_IRQ_MAX 157
-
-/* Block base addresses */
-#define MCHP_WDG_BASE		0x40000000
-#define MCHP_TMR16_0_BASE	0x40000c00
-#define MCHP_TMR32_0_BASE	0x40000c80
-#define MCHP_CNT16_0_BASE	0x40000d00
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_PROCHOT_BASE	0x40003400
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_QMSPI0_BASE	0x40005400
-#define MCHP_PWM_0_BASE		0x40005800
-#define MCHP_TACH_0_BASE	0x40006000
-#define MCHP_PECI_BASE		0x40006400
-#define MCHP_RTMR_BASE		0x40007400
-#define MCHP_ADC_BASE		0x40007c00
-#define MCHP_TFDP_BASE		0x40008c00
-#define MCHP_GPSPI0_BASE	0x40009400
-#define MCHP_GPSPI1_BASE	0x40009480
-#define MCHP_HTIMER_BASE	0x40009800
-#define MCHP_KEYSCAN_BASE	0x40009c00
-#define MCHP_RPM2PWM0_BASE	0x4000a000
-#define MCHP_RPM2PWM1_BASE	0x4000a080
-#define MCHP_VBAT_BASE		0x4000a400
-#define MCHP_VBAT_RAM_BASE	0x4000a800
-#define MCHP_WKTIMER_BASE	0x4000ac80
-#define MCHP_BBLED_0_BASE	0x4000B800
-#define MCHP_INT_BASE		0x4000e000
-#define MCHP_EC_BASE		0x4000fc00
-
-#define MCHP_PCR_BASE		0x40080100
-#define MCHP_GPIO_BASE		0x40081000
-
-#define MCHP_MBOX_BASE		0x400f0000
-#define MCHP_8042_BASE		0x400f0400
-#define MCHP_ACPI_EC_0_BASE	0x400f0800
-#define MCHP_ACPI_PM1_BASE	0x400f1c00
-#define MCHP_UART0_BASE		0x400f2400
-#define MCHP_UART1_BASE		0x400f2800
-#define MCHP_LPC_BASE		0x400f3000
-#define MCHP_ESPI_IO_BASE	0x400f3400
-#define MCHP_ESPI_MEM_BASE	0x400f3800
-#define MCHP_EMI_0_BASE		0x400f4000
-#define MCHP_EMI_1_BASE		0x400f4400
-#define MCHP_EMI_2_BASE		0x400f4800
-#define MCHP_P80CAP0_BASE	0x400f8000
-#define MCHP_P80CAP1_BASE	0x400f8400
-#define MCHP_ESPI_VW_BASE	0x400f9c00
-#define MCHP_CHIP_BASE		0x400fff00
-
-#ifndef __ASSEMBLER__
-
-/*
- * Helper function for RAM address aliasing
- * NOTE: MCHP AHB masters do NOT require aliasing.
- * Cortex-M4 bit-banding does require aliasing of the
- * DATA SRAM region.
- */
-#define MCHP_RAM_ALIAS(x) \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
-
-/* EC Chip Configuration */
-/* 8-bit Device ID */
-#define MCHP_CHIP_DEV_ID	REG8(MCHP_CHIP_BASE + 0x20)
-/* 8-bit Device Revision */
-#define MCHP_CHIP_DEV_REV	REG8(MCHP_CHIP_BASE + 0x21)
-
-/* PCR clock control dividers */
-#define MCHP_PCR_CLK_CTL_FASTEST	1U
-#define MCHP_PCR_CLK_CTL_48MHZ		1U
-#define MCHP_PCR_CLK_CTL_12MHZ		4U
-
-/* Number of PCR Sleep Enable, Clock Required, and Reset registers */
-#define MCHP_PCR_SLP_RST_REG_MAX 5
-
-/* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_JTAG		BIT(0) /* CLKREQ only */
-#define MCHP_PCR_OTP		BIT(1)
-#define MCHP_PCR_ISPI		BIT(2)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_OTP	BIT(1)
-#define MCHP_PCR_SLP_EN0_ISPI	BIT(2)
-#define MCHP_PCR_SLP_EN0_SLEEP	0xffffffff
-
-/*
- * Encode register number and bit position
- * b[4:0] = bit number
- * b[10:8] = zero based register number
- */
-#define MCHP_PCR_ERB(rnum, bnum) \
-	((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f))
-
-/* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_BTMR16_1	MCHP_PCR_ERB(1, 31)
-#define MCHP_PCR_BTMR16_0	MCHP_PCR_ERB(1, 30)
-#define MCHP_PCR_ECS		MCHP_PCR_ERB(1, 29)
-#define MCHP_PCR_PWM8		MCHP_PCR_ERB(1, 27)
-#define MCHP_PCR_PWM7		MCHP_PCR_ERB(1, 26)
-#define MCHP_PCR_PWM6		MCHP_PCR_ERB(1, 25)
-#define MCHP_PCR_PWM5		MCHP_PCR_ERB(1, 24)
-#define MCHP_PCR_PWM4		MCHP_PCR_ERB(1, 23)
-#define MCHP_PCR_PWM3		MCHP_PCR_ERB(1, 22)
-#define MCHP_PCR_PWM2		MCHP_PCR_ERB(1, 21)
-#define MCHP_PCR_PWM1		MCHP_PCR_ERB(1, 20)
-#define MCHP_PCR_TACH2		MCHP_PCR_ERB(1, 12)
-#define MCHP_PCR_TACH1		MCHP_PCR_ERB(1, 11)
-#define MCHP_PCR_I2C0		MCHP_PCR_ERB(1, 10)
-#define MCHP_PCR_WDT		MCHP_PCR_ERB(1, 9)
-#define MCHP_PCR_CPU		MCHP_PCR_ERB(1, 8)
-#define MCHP_PCR_TFDP		MCHP_PCR_ERB(1, 7)
-#define MCHP_PCR_DMA		MCHP_PCR_ERB(1, 6)
-#define MCHP_PCR_PMC		MCHP_PCR_ERB(1, 5)
-#define MCHP_PCR_PWM0		MCHP_PCR_ERB(1, 4)
-#define MCHP_PCR_TACH0		MCHP_PCR_ERB(1, 2)
-#define MCHP_PCR_PECI		MCHP_PCR_ERB(1, 1)
-#define MCHP_PCR_ECIA		MCHP_PCR_ERB(1, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) + (0xff << 20))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
-/* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
-/*
- * block not used by default
- * Do not sleep ECIA, PMC, CPU and ECS
- */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
-
-/* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
-#define MCHP_PCR_P80CAP1	MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_P80CAP0	MCHP_PCR_ERB(2, 25)
-#define MCHP_PCR_ACPI_EC4	MCHP_PCR_ERB(2, 23)
-#define MCHP_PCR_ACPI_EC3	MCHP_PCR_ERB(2, 22)
-#define MCHP_PCR_ACPI_EC2	MCHP_PCR_ERB(2, 21)
-#define MCHP_PCR_ESPI		MCHP_PCR_ERB(2, 19)
-#define MCHP_PCR_RTC		MCHP_PCR_ERB(2, 18)
-#define MCHP_PCR_MBOX		MCHP_PCR_ERB(2, 17)
-#define MCHP_PCR_8042		MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_ACPI_PM1	MCHP_PCR_ERB(2, 15)
-#define MCHP_PCR_ACPI_EC1	MCHP_PCR_ERB(2, 14)
-#define MCHP_PCR_ACPI_EC0	MCHP_PCR_ERB(2, 13)
-#define MCHP_PCR_GCFG		MCHP_PCR_ERB(2, 12)
-#define MCHP_PCR_UART1		MCHP_PCR_ERB(2, 2)
-#define MCHP_PCR_UART0		MCHP_PCR_ERB(2, 1)
-#define MCHP_PCR_LPC		MCHP_PCR_ERB(2, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN2_P80CAP1	BIT(26)
-#define MCHP_PCR_SLP_EN2_P80CAP0	BIT(25)
-#define MCHP_PCR_SLP_EN2_ACPI_EC4	BIT(23)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-#define MCHP_PCR_SLP_EN2_ESPI_SCR	BIT(20)
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_LPC		BIT(0)
-/* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0xffffffff
-
-/* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
-#define MCHP_PCR_PWM9		MCHP_PCR_ERB(3, 31)
-#define MCHP_PCR_CCT0		MCHP_PCR_ERB(3, 30)
-#define MCHP_PCR_HTMR1		MCHP_PCR_ERB(3, 29)
-#define MCHP_PCR_AESHASH	MCHP_PCR_ERB(3, 28)
-#define MCHP_PCR_RNG		MCHP_PCR_ERB(3, 27)
-#define MCHP_PCR_PKE		MCHP_PCR_ERB(3, 26)
-#define MCHP_PCR_LED3		MCHP_PCR_ERB(3, 25)
-#define MCHP_PCR_BTMR32_1	MCHP_PCR_ERB(3, 24)
-#define MCHP_PCR_BTMR32_0	MCHP_PCR_ERB(3, 23)
-#define MCHP_PCR_BTMR16_3	MCHP_PCR_ERB(3, 22)
-#define MCHP_PCR_BTMR16_2	MCHP_PCR_ERB(3, 21)
-#define MCHP_PCR_GPSPI1		MCHP_PCR_ERB(3, 20)
-#define MCHP_PCR_BCM0		MCHP_PCR_ERB(3, 19)
-#define MCHP_PCR_LED2		MCHP_PCR_ERB(3, 18)
-#define MCHP_PCR_LED1		MCHP_PCR_ERB(3, 17)
-#define MCHP_PCR_LED0		MCHP_PCR_ERB(3, 16)
-#define MCHP_PCR_I2C3		MCHP_PCR_ERB(3, 15)
-#define MCHP_PCR_I2C2		MCHP_PCR_ERB(3, 14)
-#define MCHP_PCR_I2C1		MCHP_PCR_ERB(3, 13)
-#define MCHP_PCR_RPMPWM0	MCHP_PCR_ERB(3, 12)
-#define MCHP_PCR_KEYSCAN	MCHP_PCR_ERB(3, 11)
-#define MCHP_PCR_HTMR0		MCHP_PCR_ERB(3, 10)
-#define MCHP_PCR_GPSPI0		MCHP_PCR_ERB(3, 9)
-#define MCHP_PCR_PS2_2		MCHP_PCR_ERB(3, 7)
-#define MCHP_PCR_PS2_1		MCHP_PCR_ERB(3, 6)
-#define MCHP_PCR_PS2_0		MCHP_PCR_ERB(3, 5)
-#define MCHP_PCR_ADC		MCHP_PCR_ERB(3, 3)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN3_PWM9		BIT(31)
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_AESHASH	BIT(28)
-#define MCHP_PCR_SLP_EN3_RNG		BIT(27)
-#define MCHP_PCR_SLP_EN3_PKE		BIT(26)
-#define MCHP_PCR_SLP_EN3_LED3		BIT(25)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_BTMR16_3	BIT(22)
-#define MCHP_PCR_SLP_EN3_BTMR16_2	BIT(21)
-#define MCHP_PCR_SLP_EN3_I2C4		BIT(20)
-#define MCHP_PCR_SLP_EN3_BCM0		BIT(19)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_RPM2PWM0	BIT(12)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_GPSPI0		BIT(9)
-#define MCHP_PCR_SLP_EN3_PS2_2		BIT(7)
-#define MCHP_PCR_SLP_EN3_PS2_1		BIT(6)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-#define MCHP_PCR_SLP_EN3_ALL_CRYPTO	(0x07 << 26)
-/* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN3_PWM_ALL	(MCHP_PCR_SLP_EN3_PWM9)
-
-/* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
-#define MCHP_PCR_FJCL		MCHP_PCR_ERB(4, 15)
-#define MCHP_PCR_PSPI		MCHP_PCR_ERB(4, 14)
-#define MCHP_PCR_PROCHOT	MCHP_PCR_ERB(4, 13)
-#define MCHP_PCR_RCID2		MCHP_PCR_ERB(4, 12)
-#define MCHP_PCR_RCID1		MCHP_PCR_ERB(4, 11)
-#define MCHP_PCR_RCID0		MCHP_PCR_ERB(4, 10)
-#define MCHP_PCR_BCM1		MCHP_PCR_ERB(4, 9)
-#define MCHP_PCR_QMSPI		MCHP_PCR_ERB(4, 8)
-#define MCHP_PCR_RPMPWM1	MCHP_PCR_ERB(4, 7)
-#define MCHP_PCR_RTMR		MCHP_PCR_ERB(4, 6)
-#define MCHP_PCR_CNT16_3	MCHP_PCR_ERB(4, 5)
-#define MCHP_PCR_CNT16_2	MCHP_PCR_ERB(4, 4)
-#define MCHP_PCR_CNT16_1	MCHP_PCR_ERB(4, 3)
-#define MCHP_PCR_CNT16_0	MCHP_PCR_ERB(4, 2)
-#define MCHP_PCR_PWM11		MCHP_PCR_ERB(4, 1)
-#define MCHP_PCR_PWM10		MCHP_PCR_ERB(4, 0)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN4_FJCL		BIT(15)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_RCID2		BIT(12)
-#define MCHP_PCR_SLP_EN4_RCID1		BIT(11)
-#define MCHP_PCR_SLP_EN4_RCID0		BIT(10)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RPMPWM1	BIT(7)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
-#define MCHP_PCR_SLP_EN4_CNT16_3	BIT(5)
-#define MCHP_PCR_SLP_EN4_CNT16_2	BIT(4)
-#define MCHP_PCR_SLP_EN4_CNT16_1	BIT(3)
-#define MCHP_PCR_SLP_EN4_CNT16_0	BIT(2)
-#define MCHP_PCR_SLP_EN4_PWM11		BIT(1)
-#define MCHP_PCR_SLP_EN4_PWM10		BIT(0)
-
-/* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN4_PWM_ALL \
-	(MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11)
-
-/* Allow all blocks to request clocks */
-#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP))
-#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP))
-#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP))
-#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP))
-#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
-
-/* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_MASK_RO	0xc8c
-#define MCHP_PWR_RST_STS_MASK_RWC	0x060
-#define MCHP_PWR_RST_STS_MASK \
-	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
-
-#define MCHP_PWR_RST_STS_ESPI_CLK_ACT	BIT(11) /* RO */
-#define MCHP_PWR_RST_STS_32K_ACT	BIT(10) /* RO */
-#define MCHP_PWR_RST_STS_JTAG_RSTN	BIT(7) /* RO */
-#define MCHP_PWR_RST_STS_SYS		BIT(6) /* R/WC */
-/* same function, old bit name */
-#define MCHP_PWR_RST_STS_VTR		BIT(6)
-#define MCHP_PWR_RST_STS_VBAT		BIT(5) /* R/WC */
-#define MCHP_PWR_RST_STS_HOST		BIT(3) /* RO */
-#define MCHP_PWR_RST_STS_VCC_PWRGD	BIT(2) /* RO */
-
-/* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_PCI_RESET		BIT(8)
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	(0 << 8)
-#define MCHP_PCR_PWR_OK_INV_BITPOS		0
-
-/* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET			BIT(8)
-
-/* EC Subsystem */
-#define MCHP_EC_AHB_ERR			REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO			REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN		REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL		REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN		REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN			REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT			REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_AES_SHA_SWAP_CTRL	REG8(MCHP_EC_BASE + 0x2c)
-#define MCHP_EC_PECI_DISABLE		REG8(MCHP_EC_BASE + 0x40)
-#define MCHP_EC_CRYPTO_SRESET		REG8(MCHP_EC_BASE + 0x5c)
-#define MCHP_EC_GPIO_BANK_PWR		REG8(MCHP_EC_BASE + 0x64)
-
-/* AHB ERR Enable bit[0]=0(enable), 1(disable) */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
-
-/* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE		0x01
-/* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN		0x00
-/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV		0x02
-/* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD		0x04
-
-/* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */
-#define MCHP_CRYPTO_NDRNG_SRST		0x01
-#define MCHP_CRYPTO_PKE_SRST		0x02
-#define MCHP_CRYPTO_AES_SHA_SRST	0x04
-#define MCHP_CRYPTO_ALL_SRST		0x07
-
-/* MCHP_GPIO_BANK_PWR bit definitions */
-#define MCHP_EC_GPIO_BANK_PWR_MASK	0x86
-#define MCHP_EC_GPIO_BANK_PWR_VTR2_18	0x02
-#define MCHP_EC_GPIO_BANK_PWR_VTR3_18	0x04
-#define MCHP_EC_GPIO_BANK_PWR_LOCK	0x80
-
-/* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_GIRQ_LEN	20 /* 5 32-bit registers */
-#define MCHP_INT_GIRQ_FIRST	8
-#define MCHP_INT_GIRQ_LAST	26
-#define MCHP_INT_GIRQ_NUM	(26-8+1)
-/* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
-#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN))
-
-/*
- * GPIO GIRQ's are not direct capable
- * GIRQ08 GPIO 0140 - 0176
- * GIRQ09 GPIO 0100 - 0136
- * GIRQ10 GPIO 040 - 076
- * GIRQ11 GPIO 000 - 036
- * GIRQ12 GPIO 0200 - 0236
- * GIRQ26 GPIO 0240 - 0276
- * Other GIRQ's not direct capable:
- * GIRQ22 wake peripheral clock only
- * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
- */
-#define MCHP_INT_AGGR_ONLY_BITMAP	0x07401F00U
-#define MCHP_INT_DIRECT_CAPABLE_BITMAP	0x00BFE000U
-
-/* GIRQ13 I2C controllers. Direct capable */
-#define MCHP_INT13_I2C(x) (1ul << (x))
-
-/* GIRQ14 DMA channels 0 - 13. Direct capable */
-#define MCHP_INT14_DMA(x) (1ul << (x))
-
-/* GIQ15 interrupt sources. Direct capable */
-#define MCHP_INT15_UART_0		BIT(0)
-#define MCHP_INT15_UART_1		BIT(1)
-#define MCHP_INT15_EMI_0		BIT(2)
-#define MCHP_INT15_EMI_1		BIT(3)
-#define MCHP_INT15_EMI_2		BIT(4)
-#define MCHP_INT15_ACPI_EC0_IBF		BIT(5)
-#define MCHP_INT15_ACPI_EC0_OBE		BIT(6)
-#define MCHP_INT15_ACPI_EC1_IBF		BIT(7)
-#define MCHP_INT15_ACPI_EC1_OBE		BIT(8)
-#define MCHP_INT15_ACPI_EC2_IBF		BIT(9)
-#define MCHP_INT15_ACPI_EC2_OBE		BIT(10)
-#define MCHP_INT15_ACPI_EC3_IBF		BIT(11)
-#define MCHP_INT15_ACPI_EC3_OBE		BIT(12)
-#define MCHP_INT15_ACPI_EC4_IBF		BIT(13)
-#define MCHP_INT15_ACPI_EC4_OBE		BIT(14)
-#define MCHP_INT15_ACPI_PM1_CTL		BIT(15)
-#define MCHP_INT15_ACPI_PM1_EN		BIT(16)
-#define MCHP_INT15_ACPI_PM1_STS		BIT(17)
-#define MCHP_INT15_8042_OBE		BIT(18)
-#define MCHP_INT15_8042_IBF		BIT(19)
-#define MCHP_INT15_MAILBOX		BIT(20)
-#define MCHP_INT15_P80_0		BIT(22)
-#define MCHP_INT15_P80_1		BIT(23)
-#define MCHP_INT15_P80(x)		BIT(22 + ((x) & 0x01U))
-
-/* GIRQ16 interrupt sources. Direct capable */
-#define MCHP_INT16_PKE_ERR		BIT(0)
-#define MCHP_INT16_PKE_DONE		BIT(1)
-#define MCHP_INT16_RNG_DONE		BIT(2)
-#define MCHP_INT16_AES_DONE		BIT(3)
-#define MCHP_INT16_HASH_DONE		BIT(4)
-
-/* GIR17 interrupt sources. Direct capable */
-#define MCHP_INT17_PECI			BIT(0)
-#define MCHP_INT17_TACH_0		BIT(1)
-#define MCHP_INT17_TACH_1		BIT(2)
-#define MCHP_INT17_TACH_2		BIT(3)
-#define MCHP_INT17_RPM2PWM0_FAIL	BIT(4)
-#define MCHP_INT17_RPM2PWM0_STALL	BIT(5)
-#define MCHP_INT17_RPM2PWM1_FAIL	BIT(6)
-#define MCHP_INT17_RPM2PWM1_STALL	BIT(7)
-#define MCHP_INT17_ADC_SINGLE		BIT(8)
-#define MCHP_INT17_ADC_REPEAT		BIT(9)
-#define MCHP_INT17_RCID_0		BIT(10)
-#define MCHP_INT17_RCID_1		BIT(11)
-#define MCHP_INT17_RCID_2		BIT(12)
-#define MCHP_INT17_LED_WDT_0		BIT(13)
-#define MCHP_INT17_LED_WDT_1		BIT(14)
-#define MCHP_INT17_LED_WDT_2		BIT(15)
-#define MCHP_INT17_LED_WDT_3		BIT(16)
-#define MCHP_INT17_PROCHOT		BIT(17)
-#define MCHP_INT17_PWRGRD0		BIT(18)
-#define MCHP_INT17_PWRGRD1		BIT(19)
-
-/* GIRQ18 interrupt sources. Direct capable */
-#define MCHP_INT18_LPC_ERR		BIT(0)
-#define MCHP_INT18_QMSPI		BIT(1)
-#define MCHP_INT18_GPSPI0_TXBE		BIT(2)
-#define MCHP_INT18_GPSPI0_RXBF		BIT(3)
-#define MCHP_INT18_GPSPI1_TXBE		BIT(4)
-#define MCHP_INT18_GPSPI1_RXBF		BIT(5)
-#define MCHP_INT18_BCM0_BUSY		BIT(6)
-#define MCHP_INT18_BCM0_ERR		BIT(7)
-#define MCHP_INT18_BCM1_BUSY		BIT(8)
-#define MCHP_INT18_BCM1_ERR		BIT(9)
-#define MCHP_INT18_PS2_0		BIT(10)
-#define MCHP_INT18_PS2_1		BIT(11)
-#define MCHP_INT18_PS2_2		BIT(12)
-#define MCHP_INT18_PSPI			BIT(13)
-
-/* GIRQ19 interrupt sources. Direct capable */
-#define MCHP_INT19_ESPI_PC		BIT(0)
-#define MCHP_INT19_ESPI_BM1		BIT(1)
-#define MCHP_INT19_ESPI_BM2		BIT(2)
-#define MCHP_INT19_ESPI_LTR		BIT(3)
-#define MCHP_INT19_ESPI_OOB_TX		BIT(4)
-#define MCHP_INT19_ESPI_OOB_RX		BIT(5)
-#define MCHP_INT19_ESPI_FC		BIT(6)
-#define MCHP_INT19_ESPI_RESET		BIT(7)
-#define MCHP_INT19_ESPI_VW_EN		BIT(8)
-
-/* GIRQ20 interrupt sources. Direct capable */
-#define MCHP_INT20_STAP_OBF		BIT(0)
-#define MCHP_INT20_STAP_IBF		BIT(1)
-#define MCHP_INT20_STAP_WAKE		BIT(2)
-#define MCHP_INT20_ISPI			BIT(8)
-
-/* GIRQ21 interrupt sources. Direct capable */
-#define MCHP_INT21_RTMR			BIT(0)
-#define MCHP_INT21_HTMR_0		BIT(1)
-#define MCHP_INT21_HTMR_1		BIT(2)
-#define MCHP_INT21_WEEK_ALARM		BIT(3)
-#define MCHP_INT21_WEEK_SUB		BIT(4)
-#define MCHP_INT21_WEEK_1SEC		BIT(5)
-#define MCHP_INT21_WEEK_1SEC_SUB	BIT(6)
-#define MCHP_INT21_WEEK_PWR_PRES	BIT(7)
-#define MCHP_INT21_RTC			BIT(8)
-#define MCHP_INT21_RTC_ALARM		BIT(9)
-#define MCHP_INT21_VCI_OVRD		BIT(10)
-#define MCHP_INT21_VCI_IN0		BIT(11)
-#define MCHP_INT21_VCI_IN1		BIT(12)
-#define MCHP_INT21_VCI_IN2		BIT(13)
-#define MCHP_INT21_VCI_IN3		BIT(14)
-#define MCHP_INT21_VCI_IN4		BIT(15)
-#define MCHP_INT21_VCI_IN5		BIT(16)
-#define MCHP_INT21_VCI_IN6		BIT(17)
-#define MCHP_INT21_PS2_0A_WAKE		BIT(18)
-#define MCHP_INT21_PS2_0B_WAKE		BIT(19)
-#define MCHP_INT21_PS2_1A_WAKE		BIT(20)
-#define MCHP_INT21_PS2_1B_WAKE		BIT(21)
-#define MCHP_INT21_PS2_2_WAKE		BIT(22)
-#define MCHP_INT21_ENVMON		BIT(24)
-#define MCHP_INT21_KEYSCAN		BIT(25)
-
-/* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
-#define MCHP_INT22_WAKE_ONLY_LPC	BIT(0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	BIT(1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	BIT(2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	BIT(3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	BIT(4)
-#define MCHP_INT22_WAKE_ONLY_ESPI	BIT(9)
-
-/* GIRQ23 sources. Direct capable */
-#define MCHP_INT23_BTMR16_0		BIT(0)
-#define MCHP_INT23_BTMR16_1		BIT(1)
-#define MCHP_INT23_BTMR16_2		BIT(2)
-#define MCHP_INT23_BTMR16_3		BIT(3)
-#define MCHP_INT23_BTMR32_0		BIT(4)
-#define MCHP_INT23_BTMR32_1		BIT(5)
-#define MCHP_INT23_CNT16_0		BIT(6)
-#define MCHP_INT23_CNT16_1		BIT(7)
-#define MCHP_INT23_CNT16_2		BIT(8)
-#define MCHP_INT23_CNT16_3		BIT(9)
-#define MCHP_INT23_CCT			BIT(10)
-#define MCHP_INT23_CCT_CAP0		BIT(11)
-#define MCHP_INT23_CCT_CAP1		BIT(12)
-#define MCHP_INT23_CCT_CAP2		BIT(13)
-#define MCHP_INT23_CCT_CAP3		BIT(14)
-#define MCHP_INT23_CCT_CAP4		BIT(15)
-#define MCHP_INT23_CCT_CAP6		BIT(16)
-#define MCHP_INT23_CCT_CMP0		BIT(17)
-#define MCHP_INT23_CCT_CMP1		BIT(18)
-
-/* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
-#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
-
-/* GIRQ25 sources Master-to-Slave v=[7:10], Source=[0:3] */
-#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
-
-/* UART Peripheral 0 <= x <= 1 */
-#define MCHP_UART_INSTANCES	2
-#define MCHP_UART_SPACING	0x400
-#define MCHP_UART_CFG_OFS	0x300
-#define MCHP_UART_CONFIG_BASE(x) \
-	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_RUNTIME_BASE(x) \
-	(MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_GIRQ		15
-#define MCHP_UART0_GIRQ_BIT	(MCHP_INT15_UART_0)
-#define MCHP_UART1_GIRQ_BIT	(MCHP_INT15_UART_1)
-#define MCHP_UART_GIRQ_BIT(x)	BIT(x)
-/* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY	BIT(5)
-
-/*
- * GPIO
- * MCHP each Port contains 32 GPIO's.
- * GPIO Control 1 registers are 32-bit registers starting at
- * MCHP_GPIO_BASE.
- * index = octal GPIO number from MCHP specification.
- * port/bank = index >> 5
- * id = index & 0x1F
- *
- * The port/bank, id pair may also be used to access GPIO's via
- * parallel I/O registers if GPIO control is configured for
- * parallel I/O.
- *
- * From ec/chip/mec1701/config_chip.h
- * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
- *
- * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
- *
- * Example: GPIO043, Control 1 register address = 0x4008108c
- * port/bank = 0x23 >> 5 = 1
- * id        = 0x23 & 0x1F = 0x03
- * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
- *
- * Example: GPIO235, Control 1 register address = 0x40081274
- * port/bank = 0x9d >> 5   = 4
- * id        = 0x9d & 0x1f = 0x1d
- * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
- *
- */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
-
-/* MCHP implements 6 GPIO ports */
-#define MCHP_GPIO_MAX_PORT	6
-#define UNIMPLEMENTED_GPIO_BANK	MCHP_GPIO_MAX_PORT
-/*
- * In MECxxxx documentation GPIO numbers are octal, each control
- * register is located on a 32-bit boundary.
- */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
-
-/*
- * GPIO control register bit fields
- */
-#define MCHP_GPIO_CTRL_PUD_BITPOS	0
-#define MCHP_GPIO_CTRL_PUD_MASK0	0x03
-#define MCHP_GPIO_CTRL_PUD_MASK		0x03
-#define MCHP_GPIO_CTRL_PUD_NONE		0x00
-#define MCHP_GPIO_CTRL_PUD_PU		0x01
-#define MCHP_GPIO_CTRL_PUD_PD		0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER	0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS	2
-#define MCHP_GPIO_CTRL_PWR_MASK0	0x03
-#define MCHP_GPIO_CTRL_PWR_MASK		(0x03 << 2)
-#define MCHP_GPIO_CTRL_PWR_VTR		0
-#define MCHP_GPIO_CTRL_PWR_OFF		(0x02 << 2)
-#define MCHP_GPIO_INTDET_MASK		0xF0
-#define MCHP_GPIO_INTDET_LVL_LO		0x00
-#define MCHP_GPIO_INTDET_LVL_HI		0x10
-#define MCHP_GPIO_INTDET_DISABLED	0x40
-#define MCHP_GPIO_INTDET_EDGE_RIS	0xD0
-#define MCHP_GPIO_INTDET_EDGE_FALL	0xE0
-#define MCHP_GPIO_INTDET_EDGE_BOTH	0xF0
-#define MCHP_GPIO_INTDET_EDGE_EN	BIT(7)
-#define MCHP_GPIO_PUSH_PULL		0u
-#define MCHP_GPIO_OPEN_DRAIN		BIT(8)
-#define MCHP_GPIO_INPUT			0u
-#define MCHP_GPIO_OUTPUT		BIT(9)
-#define MCHP_GPIO_OUTSET_CTRL		0u
-#define MCHP_GPIO_OUTSEL_PAR		BIT(10)
-#define MCHP_GPIO_POLARITY_NINV		0u
-#define MCHP_GPIO_POLARITY_INV		BIT(11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS	12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0	0x0F
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK	(0x0F << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO	(0 << 12)
-#define MCHP_GPIO_CTRL_FUNC_1		(1 << 12)
-#define MCHP_GPIO_CTRL_FUNC_2		(2 << 12)
-#define MCHP_GPIO_CTRL_FUNC_3		(3 << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL		BIT(16)
-/* MEC170x reserved read-only 0 bit. Value set to 0 */
-#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS	15
-#define MCHP_GPIO_CTRL_DIS_INPUT_BIT	0
-
-/*
- * GPIO Parallel Input and Output registers.
- * gpio_bank in [0, 5]
- */
-#define MCHP_GPIO_PARIN(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
-#define MCHP_GPIO_PAROUT(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
-
-/* Basic timers */
-#define MCHP_TMR_SPACING	0x20
-#define MCHP_TMR16_INSTANCES	4
-#define MCHP_TMR32_INSTANCES	2
-#define MCHP_TMR16_MAX		(MCHP_TMR16_INSTANCES)
-#define MCHP_TMR32_MAX		(MCHP_TMR32_INSTANCES)
-#define MCHP_TMR16_BASE(n)	(MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR32_BASE(n)	(MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR16_GIRQ		23
-#define MCHP_TMR16_GIRQ_BIT(n)	BIT(0 + (n))
-#define MCHP_TMR32_GIRQ		23
-#define MCHP_TMR32_GIRQ_BIT(n)	BIT(4 + (n))
-
-/* 16-bit Counter/timer */
-#define MCHP_CNT16_SPACING	0x20
-#define MCHP_CNT16_INSTANCES	4
-#define MCHP_CNT16_BASE(n)	\
-	(MCHP_CNT16_0_BASE + (n) * MCHP_CNT16_SPACING)
-#define MCHP_CNT16_GIRQ		23
-#define MCHP_CNT16_GIRQ_BIT(x)	BIT(6 + (x))
-
-/* RTimer */
-#define MCHP_RTMR_GIRQ		21
-#define MCHP_RTMR_GIRQ_BIT(x)	MCHP_INT21_RTMR
-
-/* VBAT */
-#define MCHP_VBAT_STS			REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CE			REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_SHDN_DIS		REG32(MCHP_VBAT_BASE + 0xC)
-#define MCHP_VBAT_MONOTONIC_CTR_LO	REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI	REG32(MCHP_VBAT_BASE + 0x24)
-/* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */
-#define MCHP_VBAT_RAM_SIZE		128
-#define MCHP_VBAT_RAM(wnum)		\
-	REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4))
-#define MCHP_VBAT_RAM8(bnum)		\
-	REG8(MCHP_VBAT_RAM_BASE + (bnum))
-#define MCHP_VBAT_VWIRE_BACKUP		30
-/*
- * Miscellaneous firmware control fields
- * scratch pad index cannot be more than 32 as
- * MEC152x has 64 bytes = 16 words of scratch RAM
- */
-#define MCHP_IMAGETYPE_IDX	31
-
-/* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT		BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		0xF4u
-
-/* Bit definitions for MCHP_VBAT_CE */
-#define MCHP_VBAT_CE_XOSEL_BITPOS	3
-#define MCHP_VBAT_CE_XOSEL_MASK		BIT(3)
-#define MCHP_VBAT_CE_XOSEL_PAR		0
-#define MCHP_VBAT_CE_XOSEL_SE		BIT(3)
-
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS	2
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK	BIT(2)
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT	0
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL	BIT(2)
-
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS	1
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK	BIT(1)
-#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON	0
-#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN	BIT(1)
-
-/* Blinking-Breathing LED 0 <= n <= 2 */
-#define MCHP_BBLEB_INSTANCES	4
-#define MCHP_BBLED_BASE(n)	(MCHP_BBLED_0_BASE + (((n) & 0x03) * 256))
-
-/* EMI */
-#define MCHP_EMI_INSTANCES	3
-#define MCHP_EMI_SPACING	0x400
-#define MCHP_EMI_ECREG_OFS	0x100
-/* base of EMI registers only accessible by EC */
-#define MCHP_EMI_BASE(n) \
-	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING))
-/* base of EMI registers accessible by EC and Host */
-#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING))
-#define MCHP_EMI_GIRQ		15
-#define MCHP_EMI_GIRQ_BIT(n)	BIT(2 + (n))
-
-/* Mailbox */
-#define MCHP_MBX_ECREGS_OFS	0x100
-#define MCHP_MBX_RT_BASE	MCHP_MBOX_BASE
-#define MCHP_MBX_BASE		(MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	BIT(20)
-
-/* Port 80 Capture */
-#define MCHP_P80_SPACING	0x400
-#define MCHP_P80_BASE(n) (MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING)))
-#define MCHP_P80_HOST_DATA(n) REG8(MCHP_P80_BASE(n))
-/* Data capture with time stamp register */
-#define MCHP_P80_CAP(n)		REG32(MCHP_P80_BASE(n) + 0x100)
-#define MCHP_P80_CFG(n)		REG8(MCHP_P80_BASE(n) + 0x104)
-#define MCHP_P80_STS(n)		REG8(MCHP_P80_BASE(n) + 0x108)
-#define MCHP_P80_CNT(n)		REG32(MCHP_P80_BASE(n) + 0x10c)
-#define MCHP_P80_CNT_GET(n)	(REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
-#define MCHP_P80_CNT_SET(n, c)	\
-	(REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
-#define MCHP_P80_ACTIVATE(n)	REG8(MCHP_P80_BASE(n) + 0x330)
-#define MCHP_P80_GIRQ		15
-#define MCHP_P80_GIRQ_BIT(n)	BIT(22 + (n))
-/*
- * Port 80 Data register bits
- * bits[7:0] = data captured on Host write
- * bits[31:8] = optional time stamp
- */
-#define MCHP_P80_CAP_DATA_MASK		0xFFul
-#define MCHP_P80_CAP_TS_BITPOS		8
-#define MCHP_P80_CAP_TS_MASK0		0xfffffful
-#define MCHP_P80_CAP_TS_MASK		\
-	((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS))
-
-/* Port 80 Configuration register bits */
-#define MCHP_P80_FLUSH_FIFO_WO		BIT(1)
-#define MCHP_P80_RESET_TIMESTAMP_WO	BIT(2)
-#define MCHP_P80_TIMEBASE_BITPOS	3
-#define MCHP_P80_TIMEBASE_MASK0		0x03
-#define MCHP_P80_TIMEBASE_MASK		\
-	((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_750KHZ	\
-	(0x03 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_1500KHZ	\
-	(0x02 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_3MHZ		\
-	(0x01 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_6MHZ		\
-	(0x00 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMER_ENABLE		BIT(5)
-#define MCHP_P80_FIFO_THRHOLD_MASK	(3u << 6)
-#define MCHP_P80_FIFO_THRHOLD_1		0u
-#define MCHP_P80_FIFO_THRHOLD_4		(1u << 6)
-#define MCHP_P80_FIFO_THRHOLD_8		(2u << 6)
-#define MCHP_P80_FIFO_THRHOLD_14	(3u << 6)
-#define MCHP_P80_FIFO_LEN		16
-/* Port 80 Status register bits, read-only */
-#define MCHP_P80_STS_NOT_EMPTY		BIT(0)
-#define MCHP_P80_STS_OVERRUN		BIT(1)
-/* Port 80 Count register bits */
-#define MCHP_P80_CNT_BITPOS		8
-#define MCHP_P80_CNT_MASK0		0xfffffful
-#define MCHP_P80_CNT_MASK ((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS))
-
-/* PWM SZ 144 pin package has 9 PWM's */
-#define MCHP_PWM_INSTANCES		9
-#define MCHP_PWM_ID_MAX			(MCHP_PWM_INSTANCES)
-#define MCHP_PWM_SPACING		16
-#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING))
-
-/* TACH */
-#define MCHP_TACH_INSTANCES	3
-#define MCHP_TACH_SPACING	16
-#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING))
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	BIT(1 + (x))
-
-/* FAN */
-#define MCHP_FAN_INSTANCES	2
-#define MCHP_FAN_SPACING	0x80U
-#define MCHP_FAN_BASE(x)	\
-	(MCHP_RPM2PWM0_BASE + ((x) * MCHP_FAN_SPACING))
-#define MCHP_FAN_SETTING(x)	REG16(MCHP_FAN_BASE(x) + 0x0)
-#define MCHP_FAN_CFG1(x)	REG8(MCHP_FAN_BASE(x) + 0x2)
-#define MCHP_FAN_CFG2(x)	REG8(MCHP_FAN_BASE(x) + 0x3)
-#define MCHP_FAN_PWM_DIVIDE(x)	REG8(MCHP_FAN_BASE(x) + 0x4)
-#define MCHP_FAN_GAIN(x)	REG8(MCHP_FAN_BASE(x) + 0x5)
-#define MCHP_FAN_SPIN_UP(x)	REG8(MCHP_FAN_BASE(x) + 0x6)
-#define MCHP_FAN_STEP(x)	REG8(MCHP_FAN_BASE(x) + 0x7)
-#define MCHP_FAN_MIN_DRV(x)	REG8(MCHP_FAN_BASE(x) + 0x8)
-#define MCHP_FAN_VALID_CNT(x)	REG8(MCHP_FAN_BASE(x) + 0x9)
-#define MCHP_FAN_DRV_FAIL(x)	REG16(MCHP_FAN_BASE(x) + 0xa)
-#define MCHP_FAN_TARGET(x)	REG16(MCHP_FAN_BASE(x) + 0xc)
-#define MCHP_FAN_READING(x)	REG16(MCHP_FAN_BASE(x) + 0xe)
-#define MCHP_FAN_BASE_FREQ(x)	REG8(MCHP_FAN_BASE(x) + 0x10)
-#define MCHP_FAN_STATUS(x)	REG8(MCHP_FAN_BASE(x) + 0x11)
-
-/* ACPI EC */
-#define MCHP_ACPI_EC_INSTANCES		5
-#define MCHP_ACPI_EC_MAX		(MCHP_ACPI_EC_INSTANCES)
-#define MCHP_ACPI_EC_SPACING		0x400
-#define MCHP_ACPI_EC_BASE(x) \
-	(MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING))
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	BIT(5 + ((x) * 2))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	BIT(6 + ((x) * 2))
-
-/* ACPI PM1 */
-#define MCHP_ACPI_PM1_ECREGS_OFS	0x100
-#define MCHP_ACPI_PM_RT_BASE		MCHP_ACPI_PM1_BASE
-#define MCHP_ACPI_PM_EC_BASE	(MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	BIT(15)
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	BIT(16)
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	BIT(17)
-
-/* 8042 */
-#define MCHP_8042_ECREGS_OFS		0x100
-#define MCHP_8042_GIRQ			15
-#define MCHP_8042_OBE_GIRQ_BIT		BIT(18)
-#define MCHP_8042_IBF_GIRQ_BIT		BIT(19)
-
-/* I2C controllers 0 - 4 include SMBus network layer functionality. */
-#define MCHP_I2C_CTRL0		0
-#define MCHP_I2C_CTRL1		1
-#define MCHP_I2C_CTRL2		2
-#define MCHP_I2C_CTRL3		3
-#define MCHP_I2C_CTRL_MAX	4
-
-#define MCHP_I2C_SEP0		0x400
-
-/*
- * MEC1701H 144-pin package has four I2C controllers and eleven ports.
- * Any port can be mapped to any I2C controller.
- * NOTE: 144-pin package does not implement port 1.
- *
- * I2C port values must be zero based consecutive whole numbers due to
- * port number used as an index for I2C mutex array, etc.
- *
- * Refer to chip i2c_port_to_controller function for mapping
- * of port to controller.
- *
- * Locking must occur by-controller (not by-port).
- */
-#define MCHP_I2C_PORT_MASK 0x07FDul
-enum MCHP_i2c_port {
-	MCHP_I2C_PORT0 = 0,
-	MCHP_I2C_PORT1,	/* port 1, do not use. pins not present */
-	MCHP_I2C_PORT2,
-	MCHP_I2C_PORT3,
-	MCHP_I2C_PORT4,
-	MCHP_I2C_PORT5,
-	MCHP_I2C_PORT6,
-	MCHP_I2C_PORT7,
-	MCHP_I2C_PORT8,
-	MCHP_I2C_PORT9,
-	MCHP_I2C_PORT10,
-	MCHP_I2C_PORT_COUNT,
-};
-
-/* All I2C controllers connected to GIRQ13 */
-#define MCHP_I2C_GIRQ		13
-/* I2C[0:7] -> GIRQ13 bits[0:7] */
-#define MCHP_I2C_GIRQ_BIT(n)	BIT((n))
-
-/* Keyboard scan matrix */
-#define MCHP_KS_GIRQ		21
-#define MCHP_KS_GIRQ_BIT	BIT(25)
-#define MCHP_KS_DIRECT_NVIC	135
-
-/* ADC */
-#define MCHP_ADC_GIRQ			17
-#define MCHP_ADC_GIRQ_SINGLE_BIT	BIT(8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT	BIT(9)
-#define MCHP_ADC_SINGLE_DIRECT_NVIC	78
-#define MCHP_ADC_REPEAT_DIRECT_NVIC	79
-
-/* Hibernation timer */
-#define MCHP_HTIMER_SPACING		0x20
-#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING))
-#define MCHP_HTIMER_GIRQ		21
-/* HTIMER[0:1] -> GIRQ21 bits[1:2] */
-#define MCHP_HTIMER_GIRQ_BIT(n)		BIT(1 + (n))
-#define MCHP_HTIMER_DIRECT_NVIC(n)	(112 + (n))
-
-/* General Purpose SPI (GP-SPI) */
-#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port) * 0x80))
-#define MCHP_SPI_AR(port)	REG8(MCHP_SPI_BASE(port) + 0x00)
-#define MCHP_SPI_CR(port)	REG8(MCHP_SPI_BASE(port) + 0x04)
-#define MCHP_SPI_SR(port)	REG8(MCHP_SPI_BASE(port) + 0x08)
-#define MCHP_SPI_TD(port)	REG8(MCHP_SPI_BASE(port) + 0x0c)
-#define MCHP_SPI_RD(port)	REG8(MCHP_SPI_BASE(port) + 0x10)
-#define MCHP_SPI_CC(port)	REG8(MCHP_SPI_BASE(port) + 0x14)
-#define MCHP_SPI_CG(port)	REG8(MCHP_SPI_BASE(port) + 0x18)
-/* Addresses of TX/RX register used in tables */
-#define MCHP_SPI_TD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x0c)
-#define MCHP_SPI_RD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x10)
-/* All GP-SPI controllers connected to GIRQ18 */
-#define MCHP_SPI_GIRQ			18
-#define MCHP_SPI_GIRQ_TXBE_BIT(x)	BIT(2 + ((x) * 2))
-#define MCHP_SPI_GIRQ_RXBF_BIT(x)	BIT(3 + ((x) * 2))
-#define MCHP_GPSPI0_ID			0
-#define MCHP_GPSPI1_ID			1
-
-/*
- * Quad Master SPI (QMSPI)
- * MEC1701 implements 5 descriptors and a single chip select.
- */
-#define MCHP_QMSPI_MAX_DESCR	5
-#define MCHP_QMSPI_GIRQ		18
-#define MCHP_QMSPI_GIRQ_BIT	BIT(1)
-#define MCHP_QMSPI_DIRECT_NVIC	91
-
-/* LPC */
-#define MCHP_LPC_RT_BASE	(MCHP_LPC_BASE + 0x100)
-#define MCHP_LPC_CFG_BASE	(MCHP_LPC_BASE + 0x300)
-#define MCHP_LPC_ACT		REG8(MCHP_LPC_CFG_BASE + 0x30)
-#define MCHP_LPC_SIRQ(x)	REG8(MCHP_LPC_CFG_BASE + 0x40 + (x))
-#define MCHP_LPC_CFG_BAR	REG32(MCHP_LPC_CFG_BASE + 0x60)
-#define MCHP_LPC_MAILBOX_BAR	REG32(MCHP_LPC_CFG_BASE + 0x64)
-#define MCHP_LPC_8042_BAR	REG32(MCHP_LPC_CFG_BASE + 0x68)
-#define MCHP_LPC_ACPI_EC0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x6C)
-#define MCHP_LPC_ACPI_EC1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x70)
-#define MCHP_LPC_ACPI_EC2_BAR	REG32(MCHP_LPC_CFG_BASE + 0x74)
-#define MCHP_LPC_ACPI_EC3_BAR	REG32(MCHP_LPC_CFG_BASE + 0x78)
-#define MCHP_LPC_ACPI_EC4_BAR	REG32(MCHP_LPC_CFG_BASE + 0x7C)
-#define MCHP_LPC_ACPI_PM1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x80)
-#define MCHP_LPC_PORT92_BAR	REG32(MCHP_LPC_CFG_BASE + 0x84)
-#define MCHP_LPC_UART0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x88)
-#define MCHP_LPC_UART1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x8C)
-#define MCHP_LPC_EMI0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x90)
-#define MCHP_LPC_EMI1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x94)
-#define MCHP_LPC_EMI2_BAR	REG32(MCHP_LPC_CFG_BASE + 0x98)
-#define MCHP_LPC_P80DBG0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x9C)
-#define MCHP_LPC_P80DBG1_BAR	REG32(MCHP_LPC_CFG_BASE + 0xA0)
-#define MCHP_LPC_RTC_BAR	REG32(MCHP_LPC_CFG_BASE + 0xA4)
-#define MCHP_LPC_ACPI_EC_BAR(x)	REG32(MCHP_LPC_CFG_BASE + 0x6C + ((x)<<2))
-/* LPC BAR bits */
-#define MCHP_LPC_IO_BAR_ADDR_BITPOS	(16)
-#define MCHP_LPC_IO_BAR_EN		(1ul << 15)
-/* LPC Generic Memory BAR's, 64-bit registers */
-#define MCHP_LPC_SRAM0_BAR_LO	REG32(MCHP_LPC_CFG_BASE + 0xB0)
-#define MCHP_LPC_SRAM0_BAR_HI	REG32(MCHP_LPC_CFG_BASE + 0xB4)
-#define MCHP_LPC_SRAM1_BAR_LO	REG32(MCHP_LPC_CFG_BASE + 0xB8)
-#define MCHP_LPC_SRAM1_BAR_HI	REG32(MCHP_LPC_CFG_BASE + 0xBC)
-/*
- * LPC Logical Device Memory BAR's, 48-bit registers
- * Use 16-bit aligned access
- */
-#define MCHP_LPC_MAILBOX_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xC0)
-#define MCHP_LPC_MAILBOX_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xC2)
-#define MCHP_LPC_MAILBOX_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xC4)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xC6)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xC8)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xCA)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xCC)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xCE)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xD0)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xD2)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xD4)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xD6)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xD8)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xDA)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xDC)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xDE)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xE0)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xE2)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xE4)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xE6)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xE8)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xEA)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xEC)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xEE)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xF0)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xF2)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xF4)
-
-#define MCHP_LPC_BUS_MONITOR	REG32(MCHP_LPC_RT_BASE + 0x4)
-#define MCHP_LPC_HOST_ERROR	REG32(MCHP_LPC_RT_BASE + 0x8)
-#define MCHP_LPC_EC_SERIRQ	REG32(MCHP_LPC_RT_BASE + 0xC)
-#define MCHP_LPC_EC_CLK_CTRL	REG32(MCHP_LPC_RT_BASE + 0x10)
-#define MCHP_LPC_BAR_INHIBIT	REG32(MCHP_LPC_RT_BASE + 0x20)
-#define MCHP_LPC_BAR_INIT	REG32(MCHP_LPC_RT_BASE + 0x30)
-#define MCHP_LPC_SRAM0_BAR	REG32(MCHP_LPC_RT_BASE + 0xf8)
-#define MCHP_LPC_SRAM1_BAR	REG32(MCHP_LPC_RT_BASE + 0xfc)
-
-/* eSPI */
-/* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4	8
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_ID_EMI2	0xF
-#define MCHP_ESPI_IO_BAR_P80_0		0x10
-#define MCHP_ESPI_IO_BAR_P80_1		0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
-
-/* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
-#define MCHP_ESPI_MBAR_ID_MBOX		0
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_0	1
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_1	2
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_2	3
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_3	4
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_4	5
-#define MCHP_ESPI_MBAR_ID_EMI_0		6
-#define MCHP_ESPI_MBAR_ID_EMI_1		7
-#define MCHP_ESPI_MBAR_ID_EMI_2		8
-
-/* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
-#define MCHP_ESPI_SIRQ_MBOX		0 /* Host SIRQ */
-#define MCHP_ESPI_SIRQ_MBOX_SMI		1 /* Host SMI */
-#define MCHP_ESPI_SIRQ_8042_KB		2 /* KIRQ */
-#define MCHP_ESPI_SIRQ_8042_MS		3 /* MIRQ */
-#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF	4
-#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF	5
-#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF	6
-#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF	7
-#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF	8
-#define MCHP_ESPI_SIRQ_UART0		9
-#define MCHP_ESPI_SIRQ_UART1		10
-#define MCHP_ESPI_SIRQ_EMI0_HEV		11 /* Host Event */
-#define MCHP_ESPI_SIRQ_EMI0_EC2H	12 /* EC to Host */
-#define MCHP_ESPI_SIRQ_EMI1_HEV		13
-#define MCHP_ESPI_SIRQ_EMI1_EC2H	14
-#define MCHP_ESPI_SIRQ_EMI2_HEV		15
-#define MCHP_ESPI_SIRQ_EMI2_EC2H	16
-#define MCHP_ESPI_SIRQ_RTC		17
-#define MCHP_ESPI_SIRQ_EC		18
-
-#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
-#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
-
-/*
- * eSPI RESET, channel enables and operations except Master-to-Slave
- * WWires are all on GIRQ19
- */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		BIT(0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		BIT(1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		BIT(2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		BIT(3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	BIT(4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	BIT(5)
-#define MCHP_ESPI_FC_GIRQ_BIT		BIT(6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	BIT(7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	BIT(8)
-
-/*
- * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25
- */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
-/*
- * Four source bits, SRC[0:3] per Master-to-Slave register
- * v = MSVW [0:10]
- * n = VWire SRC bit = [0:3]
- */
-#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
-
-#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
-
-/* DMA */
-#define MCHP_DMA_MAX_CHAN	14
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
-#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
-
-/*
- * Available DMA channels.
- *
- * On MCHP, any DMA channel may serve any device. Since we have
- * 14 channels and 14 device request signals, we make each channel
- * dedicated to the device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MCHP_DMAC_I2C0_SLAVE = 0,
-	MCHP_DMAC_I2C0_MASTER,
-	MCHP_DMAC_I2C1_SLAVE,
-	MCHP_DMAC_I2C1_MASTER,
-	MCHP_DMAC_I2C2_SLAVE,
-	MCHP_DMAC_I2C2_MASTER,
-	MCHP_DMAC_I2C3_SLAVE,
-	MCHP_DMAC_I2C3_MASTER,
-	MCHP_DMAC_SPI0_TX,
-	MCHP_DMAC_SPI0_RX,
-	MCHP_DMAC_SPI1_TX,
-	MCHP_DMAC_SPI1_RX,
-	MCHP_DMAC_QMSPI0_TX,
-	MCHP_DMAC_QMSPI0_RX,
-	/* Channel count */
-	MCHP_DMAC_COUNT,
-};
-
-/*
- * Peripheral device DMA Device ID's for bits [15:9]
- * in DMA channel control register.
- */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_SPI0_TX_REQ_ID		8
-#define MCHP_DMA_SPI0_RX_REQ_ID		9
-#define MCHP_DMA_SPI1_TX_REQ_ID		10
-#define MCHP_DMA_SPI1_RX_REQ_ID		11
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	12
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	13
-
-/*
- * Hardware delay register.
- * Write of 0 <= n <= 31 will stall the Cortex-M4
- * for n+1 microseconds. Interrupts will not be
- * serviced during the delay period. Reads have
- * no effect.
- */
-#define MCHP_USEC_DELAY_REG_ADDR 0x10000000
-#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
-
-#endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers-mec172x.h b/chip/mchp/registers-mec172x.h
deleted file mode 100644
index dc811ea3c7..0000000000
--- a/chip/mchp/registers-mec172x.h
+++ /dev/null
@@ -1,1503 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for Microchip MEC172x family controllers
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/*
- * IRQ Numbers
- * NOTE: GIRQ22 aggregated output and its sources are not connected to
- * the NVIC.
- */
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
-/* GIRQ13 direct sources */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
-#define MCHP_IRQ_I2C_4		158
-/* GIRQ14 direct sources */
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
-#define MCHP_IRQ_DMA_12		36
-#define MCHP_IRQ_DMA_13		37
-#define MCHP_IRQ_DMA_14		38
-#define MCHP_IRQ_DMA_15		39
-/* GIRQ15 direct sources */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_EMI2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIEC4_IBF	53
-#define MCHP_IRQ_ACPIEC4_OBE	54
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-#define MCHP_IRQ_BDP0		62
-/* GIRQ16 direct sources */
-#define MCHP_IRQ_PKE		65
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AESH		68
-/* GIRQ17 direct sources */
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_TACH_3		159
-#define MCHP_IRQ_FAN0_FAIL	74
-#define MCHP_IRQ_FAN0_STALL	75
-#define MCHP_IRQ_FAN1_FAIL	76
-#define MCHP_IRQ_FAN1_STALL	77
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_RCID0		80
-#define MCHP_IRQ_RCID1		81
-#define MCHP_IRQ_RCID2		82
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_LED3_WDT	86
-#define MCHP_IRQ_PHOT		87
-/* GIRQ18 direct sources */
-#define MCHP_IRQ_SLAVE_SPI	90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_SPI0_TX	92
-#define MCHP_IRQ_SPI0_RX	93
-#define MCHP_IRQ_SPI1_TX	94
-#define MCHP_IRQ_SPI1_RX	95
-#define MCHP_IRQ_BCM0_ERR	96
-#define MCHP_IRQ_BCM0_BUSY	97
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_EEPROM		155
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
-/* GIRQ19 direct sources */
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_ESPI_VW_EN	156
-#define MCHP_IRQ_ESPI_SAF_DONE	166
-#define MCHP_IRQ_ESPI_SAF_ERR	166
-#define MCHP_IRQ_ESPI_SAF_CACHE	169
-/* GIRQ20 direct sources */
-#define MCHP_IRQ_OTP		173
-#define MCHP_IRQ_CLK32K_MON	174
-/* GIRQ21 direct sources */
-#define MCHP_IRQ_WDG		171
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_VCI_IN4	126
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_KSC_INT	135
-#define MCHP_IRQ_GLUE		172
-/* GIRQ23 direct sources */
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER16_2	138
-#define MCHP_IRQ_TIMER16_3	139
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_CNTR_TM0	142
-#define MCHP_IRQ_CNTR_TM1	143
-#define MCHP_IRQ_CNTR_TM2	144
-#define MCHP_IRQ_CNTR_TM3	145
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
-/* Must match CONFIG_IRQ_COUNT in config_chip.h */
-#define MCHP_IRQ_MAX 180
-
-/* Block base addresses */
-#define MCHP_WDG_BASE		0x40000400
-#define MCHP_TMR16_0_BASE	0x40000c00
-#define MCHP_TMR32_0_BASE	0x40000c80
-#define MCHP_CNT16_0_BASE	0x40000d00
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_PROCHOT_BASE	0x40003400
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_I2C4_BASE		0x40005000
-#define MCHP_CACHE_CTRL_BASE	0x40005400
-#define MCHP_PWM_0_BASE		0x40005800
-#define MCHP_TACH_0_BASE	0x40006000
-#define MCHP_PECI_BASE		0x40006400
-#define MCHP_SPIEP_BASE		0x40007000
-#define MCHP_RTMR_BASE		0x40007400
-#define MCHP_ADC_BASE		0x40007c00
-#define MCHP_ESPI_SAF_BASE	0x40008000
-#define MCHP_TFDP_BASE		0x40008c00
-#define MCHP_GPSPI0_BASE	0x40009400
-#define MCHP_GPSPI1_BASE	0x40009480
-#define MCHP_HTIMER_BASE	0x40009800
-#define MCHP_KEYSCAN_BASE	0x40009c00
-#define MCHP_RPM2PWM0_BASE	0x4000a000
-#define MCHP_RPM2PWM1_BASE	0x4000a080
-#define MCHP_VBAT_BASE		0x4000a400
-#define MCHP_VBAT_RAM_BASE	0x4000a800
-#define MCHP_WKTIMER_BASE	0x4000ac80
-#define MCHP_VCI_BASE		0x4000ae00
-#define MCHP_BBLED_0_BASE	0x4000B800
-#define MCHP_BCL_0_BASE		0x4000cd00
-#define MCHP_INT_BASE		0x4000e000
-#define MCHP_EC_BASE		0x4000fc00
-
-#define MCHP_QMSPI0_BASE	0x40070000
-#define MCHP_ESPI_SAF_COMM_BASE 0x40071000
-
-#define MCHP_PCR_BASE		0x40080100
-#define MCHP_GPIO_BASE		0x40081000
-#define MCHP_OTP_BASE		0x40082000
-
-#define MCHP_MBOX_BASE		0x400f0000
-#define MCHP_8042_BASE		0x400f0400
-#define MCHP_ACPI_EC_0_BASE	0x400f0800
-#define MCHP_ACPI_PM1_BASE	0x400f1c00
-#define MCHP_PORT92_BASE	0x400f2000
-#define MCHP_UART0_BASE		0x400f2400
-#define MCHP_UART1_BASE		0x400f2800
-#define MCHP_LPC_BASE		0x400f3000
-#define MCHP_ESPI_IO_BASE	0x400f3400
-#define MCHP_ESPI_MEM_BASE	0x400f3800
-#define MCHP_GLUE_BASE		0x400f3c00
-#define MCHP_EMI_0_BASE		0x400f4000
-#define MCHP_EMI_1_BASE		0x400f4400
-#define MCHP_EMI_2_BASE		0x400f4800
-#define MCHP_RTC_BASE		0x400f5000
-#define MCHP_BDP0_BASE		0x400f8000
-#define MCHP_ESPI_VW_BASE	0x400f9c00
-#define MCHP_CHIP_BASE		0x400fff00
-
-#ifndef __ASSEMBLER__
-
-/*
- * Helper function for RAM address aliasing
- * NOTE: MEC17xx and MEC15xx AHB controllers do NOT require aliasing.
- * Cortex-M4 bit-banding does require aliasing of the
- * DATA SRAM region.
- */
-#define MCHP_RAM_ALIAS(x) \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
-
-/* EC Chip Configuration */
-/* 16-bit Device ID */
-#define MCHP_CHIP_DEV_ID		REG16(MCHP_CHIP_BASE + 0x1E)
-/* 8-bit Device Sub ID */
-#define MCHP_CHIP_DEV_SUB_ID		REG8(MCHP_CHIP_BASE + 0x1D)
-/* 8-bit Device Revision */
-#define MCHP_CHIP_DEV_REV		REG8(MCHP_CHIP_BASE + 0x1C)
-/* All in one */
-#define MCHP_CHIP_DEVRID32		REG32(MCHP_CHIP_BASE + 0x1C)
-#define MCHP_CHIP_DEVID_POS		16
-#define MCHP_CHIP_DEVID_MASK		(0xfffful << MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_SUBID_POS		8
-#define MCHP_CHIP_SUBID_MASK		(0xfful << MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_REV_POS		0
-#define MCHP_CHIP_REV_MASK		(0xfful << MCHP_CHIP_REV_POS)
-#define MCHP_CHIP_EXTRACT_DEVID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_EXTRACT_SUBID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_EXTRACT_REV(d) \
-	(((uint32_t)(d) & MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
-
-/* PCR clock control dividers */
-#define MCHP_PCR_CLK_CTL_FASTEST	1U
-#define MCHP_PCR_CLK_CTL_96MHZ		1U
-#define MCHP_PCR_CLK_CTL_48MHZ		2U
-#define MCHP_PCR_CLK_CTL_24MHZ		4U
-#define MCHP_PCR_CLK_CTL_12MHZ		8U
-
-/* Number of PCR Sleep Enable, Clock Required, and Reset registers */
-#define MCHP_PCR_SLP_RST_REG_MAX 5
-
-/* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_JTAG		BIT(0) /* CLKREQ only */
-#define MCHP_PCR_OTP		BIT(1)
-#define MCHP_PCR_ISPI		BIT(2)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_OTP	BIT(1)
-#define MCHP_PCR_SLP_EN0_ISPI	BIT(2)
-#define MCHP_PCR_SLP_EN0_SLEEP	0xffffffff
-
-/*
- * Encode register number and bit position
- * b[4:0] = bit number
- * b[10:8] = zero based register number
- */
-#define MCHP_PCR_ERB(rnum, bnum) \
-	((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f))
-
-/* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_BTMR16_1	MCHP_PCR_ERB(1, 31)
-#define MCHP_PCR_BTMR16_0	MCHP_PCR_ERB(1, 30)
-#define MCHP_PCR_ECS		MCHP_PCR_ERB(1, 29)
-#define MCHP_PCR_PWM8		MCHP_PCR_ERB(1, 27)
-#define MCHP_PCR_PWM7		MCHP_PCR_ERB(1, 26)
-#define MCHP_PCR_PWM6		MCHP_PCR_ERB(1, 25)
-#define MCHP_PCR_PWM5		MCHP_PCR_ERB(1, 24)
-#define MCHP_PCR_PWM4		MCHP_PCR_ERB(1, 23)
-#define MCHP_PCR_PWM3		MCHP_PCR_ERB(1, 22)
-#define MCHP_PCR_PWM2		MCHP_PCR_ERB(1, 21)
-#define MCHP_PCR_PWM1		MCHP_PCR_ERB(1, 20)
-#define MCHP_PCR_TACH3		MCHP_PCR_ERB(1, 13)
-#define MCHP_PCR_TACH2		MCHP_PCR_ERB(1, 12)
-#define MCHP_PCR_TACH1		MCHP_PCR_ERB(1, 11)
-#define MCHP_PCR_I2C0		MCHP_PCR_ERB(1, 10)
-#define MCHP_PCR_WDT		MCHP_PCR_ERB(1, 9)
-#define MCHP_PCR_CPU		MCHP_PCR_ERB(1, 8)
-#define MCHP_PCR_TFDP		MCHP_PCR_ERB(1, 7)
-#define MCHP_PCR_DMA		MCHP_PCR_ERB(1, 6)
-#define MCHP_PCR_PMC		MCHP_PCR_ERB(1, 5)
-#define MCHP_PCR_PWM0		MCHP_PCR_ERB(1, 4)
-#define MCHP_PCR_TACH0		MCHP_PCR_ERB(1, 2)
-#define MCHP_PCR_PECI		MCHP_PCR_ERB(1, 1)
-#define MCHP_PCR_ECIA		MCHP_PCR_ERB(1, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) | BIT(20) | BIT(21) |\
-	BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-#define MCHP_PCR_SLP_EN1_TACH3		BIT(13)
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
-/* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
-/*
- * block not used by default
- * Do not sleep ECIA, PMC, CPU and ECS
- */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
-
-/* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
-#define MCHP_PCR_GLUE		MCHP_PCR_ERB(2, 29)
-#define MCHP_PCR_SAF		MCHP_PCR_ERB(2, 27)
-#define MCHP_PCR_BDP0		MCHP_PCR_ERB(2, 25)
-#define MCHP_PCR_ACPI_EC4	MCHP_PCR_ERB(2, 23)
-#define MCHP_PCR_ACPI_EC3	MCHP_PCR_ERB(2, 22)
-#define MCHP_PCR_ACPI_EC2	MCHP_PCR_ERB(2, 21)
-#define MCHP_PCR_ESPI_SCR	MCHP_PCR_ERB(2, 20)
-#define MCHP_PCR_ESPI		MCHP_PCR_ERB(2, 19)
-#define MCHP_PCR_RTC		MCHP_PCR_ERB(2, 18)
-#define MCHP_PCR_MBOX		MCHP_PCR_ERB(2, 17)
-#define MCHP_PCR_8042		MCHP_PCR_ERB(2, 16)
-#define MCHP_PCR_ACPI_PM1	MCHP_PCR_ERB(2, 15)
-#define MCHP_PCR_ACPI_EC1	MCHP_PCR_ERB(2, 14)
-#define MCHP_PCR_ACPI_EC0	MCHP_PCR_ERB(2, 13)
-#define MCHP_PCR_GCFG		MCHP_PCR_ERB(2, 12)
-#define MCHP_PCR_UART1		MCHP_PCR_ERB(2, 2)
-#define MCHP_PCR_UART0		MCHP_PCR_ERB(2, 1)
-#define MCHP_PCR_EMI0		MCHP_PCR_ERB(2, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN2_GLUE		BIT(29)
-#define MCHP_PCR_SLP_EN2_SAF		BIT(27)
-#define MCHP_PCR_SLP_EN2_BDP0		BIT(25)
-#define MCHP_PCR_SLP_EN2_ACPI_EC4	BIT(23)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-#define MCHP_PCR_SLP_EN2_ESPI_SCR	BIT(20)
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_EMI0		BIT(0)
-/* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0xffffffff
-
-/* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
-#define MCHP_PCR_PWM9		MCHP_PCR_ERB(3, 31)
-#define MCHP_PCR_CCT0		MCHP_PCR_ERB(3, 30)
-#define MCHP_PCR_HTMR1		MCHP_PCR_ERB(3, 29)
-#define MCHP_PCR_CRYPTO		MCHP_PCR_ERB(3, 26)
-#define MCHP_PCR_LED3		MCHP_PCR_ERB(3, 25)
-#define MCHP_PCR_BTMR32_1	MCHP_PCR_ERB(3, 24)
-#define MCHP_PCR_BTMR32_0	MCHP_PCR_ERB(3, 23)
-#define MCHP_PCR_BTMR16_3	MCHP_PCR_ERB(3, 22)
-#define MCHP_PCR_BTMR16_2	MCHP_PCR_ERB(3, 21)
-#define MCHP_PCR_I2C4		MCHP_PCR_ERB(3, 20)
-#define MCHP_PCR_BCM0		MCHP_PCR_ERB(3, 19)
-#define MCHP_PCR_LED2		MCHP_PCR_ERB(3, 18)
-#define MCHP_PCR_LED1		MCHP_PCR_ERB(3, 17)
-#define MCHP_PCR_LED0		MCHP_PCR_ERB(3, 16)
-#define MCHP_PCR_I2C3		MCHP_PCR_ERB(3, 15)
-#define MCHP_PCR_I2C2		MCHP_PCR_ERB(3, 14)
-#define MCHP_PCR_I2C1		MCHP_PCR_ERB(3, 13)
-#define MCHP_PCR_RPMPWM0	MCHP_PCR_ERB(3, 12)
-#define MCHP_PCR_KEYSCAN	MCHP_PCR_ERB(3, 11)
-#define MCHP_PCR_HTMR0		MCHP_PCR_ERB(3, 10)
-#define MCHP_PCR_GPSPI0		MCHP_PCR_ERB(3, 9)
-#define MCHP_PCR_PS2_0		MCHP_PCR_ERB(3, 5)
-#define MCHP_PCR_ADC		MCHP_PCR_ERB(3, 3)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN3_PWM9		BIT(31)
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_CRYPTO		BIT(26)
-#define MCHP_PCR_SLP_EN3_LED3		BIT(25)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_BTMR16_3	BIT(22)
-#define MCHP_PCR_SLP_EN3_BTMR16_2	BIT(21)
-#define MCHP_PCR_SLP_EN3_I2C4		BIT(20)
-#define MCHP_PCR_SLP_EN3_BCM0		BIT(19)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_RPM2PWM0	BIT(12)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_GPSPI0		BIT(9)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-#define MCHP_PCR_SLP_EN3_ALL_CRYPTO	BIT(26)
-/* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN3_PWM_ALL	(MCHP_PCR_SLP_EN3_PWM9)
-
-/* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
-#define MCHP_PCR_GPSPI1		MCHP_PCR_ERB(4, 22)
-#define MCHP_PCR_PSPI		MCHP_PCR_ERB(4, 14)
-#define MCHP_PCR_PROCHOT	MCHP_PCR_ERB(4, 13)
-#define MCHP_PCR_RCID2		MCHP_PCR_ERB(4, 12)
-#define MCHP_PCR_RCID1		MCHP_PCR_ERB(4, 11)
-#define MCHP_PCR_RCID0		MCHP_PCR_ERB(4, 10)
-#define MCHP_PCR_QMSPI		MCHP_PCR_ERB(4, 8)
-#define MCHP_PCR_RPMPWM1	MCHP_PCR_ERB(4, 7)
-#define MCHP_PCR_RTMR		MCHP_PCR_ERB(4, 6)
-#define MCHP_PCR_CNT16_3	MCHP_PCR_ERB(4, 5)
-#define MCHP_PCR_CNT16_2	MCHP_PCR_ERB(4, 4)
-#define MCHP_PCR_CNT16_1	MCHP_PCR_ERB(4, 3)
-#define MCHP_PCR_CNT16_0	MCHP_PCR_ERB(4, 2)
-#define MCHP_PCR_PWM11		MCHP_PCR_ERB(4, 1)
-#define MCHP_PCR_PWM10		MCHP_PCR_ERB(4, 0)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN4_GPSPI1		BIT(22)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_RCID2		BIT(12)
-#define MCHP_PCR_SLP_EN4_RCID1		BIT(11)
-#define MCHP_PCR_SLP_EN4_RCID0		BIT(10)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RPMPWM1	BIT(7)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
-#define MCHP_PCR_SLP_EN4_CNT16_3	BIT(5)
-#define MCHP_PCR_SLP_EN4_CNT16_2	BIT(4)
-#define MCHP_PCR_SLP_EN4_CNT16_1	BIT(3)
-#define MCHP_PCR_SLP_EN4_CNT16_0	BIT(2)
-#define MCHP_PCR_SLP_EN4_PWM11		BIT(1)
-#define MCHP_PCR_SLP_EN4_PWM10		BIT(0)
-
-/* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN4_PWM_ALL \
-	(MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11)
-
-/* Allow all blocks to request clocks */
-#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP))
-#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP))
-#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP))
-#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP))
-#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
-
-/* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_MASK_RO	0xc8c
-#define MCHP_PWR_RST_STS_MASK_RWC	0x170
-#define MCHP_PWR_RST_STS_MASK \
-	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
-
-#define MCHP_PWR_RST_STS_ESPI_CLK_ACT	BIT(11) /* RO */
-#define MCHP_PWR_RST_STS_32K_ACT	BIT(10) /* RO */
-#define MCHP_PWR_RST_STS_WDT		BIT(8) /* R/WC */
-#define MCHP_PWR_RST_STS_JTAG_RSTN	BIT(7) /* RO */
-#define MCHP_PWR_RST_STS_SYS		BIT(6) /* R/WC */
-#define MCHP_PWR_RST_STS_VBAT		BIT(5) /* R/WC */
-#define MCHP_PWR_RST_STS_VTR		BIT(4) /* R/WC */
-#define MCHP_PWR_RST_STS_HOST		BIT(3) /* RO */
-#define MCHP_PWR_RST_STS_VCC_PWRGD	BIT(2) /* RO */
-
-/* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_PCI_RESET		BIT(8)
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	0
-#define MCHP_PCR_PWR_OK_INV_BITPOS		0
-
-/* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET			BIT(8)
-
-/*
- * PCR Peripheral Reset Lock register
- * MEC152x PCR Peripheral reset registers do not reset on
- * peripheral sleep. The peripheral is reset immediately.
- * Firmware must write an unlock value to this new lock
- * register, write to PCR reset enable register(s), and
- * write a lock value.
- */
-#define MCHP_PCR_RST_LOCK	REG32(MCHP_PCR_BASE + 0x84)
-#define MCHP_PCR_RST_LOCK_VAL	0xa6382d4d
-#define MCHP_PCR_RST_UNLOCK_VAL	0xa6382d4c
-
-/* PCR VBAT soft reset. Trigger a VBAT reset */
-#define MCHP_PCR_VBAT_SRST	REG32(MCHP_PCR_BASE + 0x88)
-#define MCHP_PCR_VBAT_SRST_EN	BIT(0)
-
-/* PCR 32KHz clock source select */
-#define MCHP_PCR_CK32_SS	REG32(MCHP_PCR_BASE + 0x8c)
-#define MCHP_PCR_CK32_SEL_MASK	GENMASK(1, 0)
-#define MCHP_PCR_CK32_SEL_SIL	0
-#define MCHP_PCR_CK32_SEL_XTAL	1
-#define MCHP_PCR_CK32_SEL_PIN	2
-#define MCHP_PCR_CK32_SEL_OFF	3
-
-/* PCR 32KHz period count (RO) */
-#define MCHP_PCR_CK32_PER_CNT		REG32(MCHP_PCR_BASE + 0xc0)
-#define MCHP_PCR_CD32_PER_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz high pulse count (RO) */
-#define MCHP_PCR_CK32_HP_CNT		REG32(MCHP_PCR_BASE + 0xc4)
-#define MCHP_PCR_CK32_HP_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz minimum acceptable period count */
-#define MCHP_PCR_CK32_MIN_PER_CNT	REG32(MCHP_PCR_BASE + 0xc8)
-#define MCHP_PCR_CK32_MIN_PER_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz maximum acceptable period count */
-#define MCHP_PCR_CK32_MAX_PER_CNT	REG32(MCHP_PCR_BASE + 0xcc)
-#define MCHP_PCR_CK32_MAX_PER_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz duty cycle variation count (RO) */
-#define MCHP_PCR_CK32_DC_VAR_CNT	REG32(MCHP_PCR_BASE + 0xd0)
-#define MCHP_PCR_CK32_DC_VAR_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz duty cycle variation acceptable maximum */
-#define MCHP_PCR_CK32_DC_VAR_MAX	REG32(MCHP_PCR_BASE + 0xd4)
-#define MCHP_PCR_CK32_DC_VAR_MAX_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz valid count */
-#define MCHP_PCR_CK32_VAL_CNT		REG32(MCHP_PCR_BASE + 0xd8)
-#define MCHP_PCR_CK32_VAL_CNT_MSK	GENMASK(7, 0)
-
-/* PCR 32KHz valid count minimum */
-#define MCHP_PCR_CK32_MIN_VAL_CNT	REG32(MCHP_PCR_BASE + 0xdc)
-#define MCHP_PCR_CK32_MIN_VAL_CNT_MSK	GENMASK(7, 0)
-
-/* PCR 32KHz control */
-#define MCHP_PCR_CK32_CTRL		REG32(MCHP_PCR_BASE + 0xe0)
-#define MCHP_PCR_CK32_CTRL_MSK		(GENMASK(2, 0) | BIT(4) | BIT(24))
-#define MCHP_PCR_CK32_CTRL_PER_EN	BIT(0)
-#define MCHP_PCR_CK32_CTRL_DC_EN	BIT(1)
-#define MCHP_PCR_CK32_CTRL_VAL_EN	BIT(2)
-#define MCHP_PCR_CK32_CTRL_SRC_SIL	BIT(3)
-#define MCHP_PCR_CK32_CTRL_CLR_CNT	BIT(24)
-
-/* PCR 32KHz interrupt status */
-#define MCHP_PCR_CK32_INTR_STS		REG8(MCHP_PCR_BASE + 0xe4)
-/* PCR 32KHz interrupt enable */
-#define MCHP_PCR_CK32_INTR_EN		REG8(MCHP_PCR_BASE + 0xe8)
-#define MCHP_PCR_CK32_INTR_PULSE_RDY	BIT(0)
-#define MCHP_PCR_CK32_INTR_PASS_PER	BIT(1)
-#define MCHP_PCR_CK32_INTR_PASS_DUTY	BIT(2)
-#define MCHP_PCR_CK32_INTR_FAIL		BIT(3)
-#define MCHP_PCR_CK32_INTR_STALL	BIT(4)
-#define MCHP_PCR_CK32_INTR_VALID	BIT(5)
-#define MCHP_PCR_CK32_INTR_UNWELL	BIT(6)
-
-/* EC Subsystem */
-#define MCHP_EC_AHB_ERR		REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO		REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN	REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL	REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN	REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN		REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT		REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_PECI_DISABLE	REG8(MCHP_EC_BASE + 0x40)
-#define MCHP_EC_VCI_FW_OVRD	REG32(MCHP_EC_BASE + 0x50)
-#define MCHP_EC_BROM_STS	REG32(MCHP_EC_BASE + 0x54)
-#define MCHP_EC_VW_SRC_CFG	REG32(MCHP_EC_BASE + 0x90)
-#define MCHP_EC_CMP_CTRL	REG32(MCHP_EC_BASE + 0x94)
-#define MCHP_EC_CMP_SLP_CTRL	REG32(MCHP_EC_BASE + 0x98)
-
-/* AHB ERR Disable bit[0]=0(enable), 1(disable) */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
-
-/* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE		0x01
-/* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN		0x00
-/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV		0x02
-/* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD		0x04
-
-/* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_GIRQ_LEN	20 /* 5 32-bit registers */
-#define MCHP_INT_GIRQ_FIRST	8
-#define MCHP_INT_GIRQ_LAST	26
-#define MCHP_INT_GIRQ_NUM	(26-8+1)
-/* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
-#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN))
-
-/*
- * GPIO GIRQ's are not direct capable
- * GIRQ08 GPIO 0140 - 0176
- * GIRQ09 GPIO 0100 - 0136
- * GIRQ10 GPIO 040 - 076
- * GIRQ11 GPIO 000 - 036
- * GIRQ12 GPIO 0200 - 0236
- * GIRQ26 GPIO 0240 - 0276
- * Other GIRQ's not direct capable:
- * GIRQ22 wake peripheral clock only
- * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
- */
-#define MCHP_INT_AGGR_ONLY_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) |\
-		BIT(12) | BIT(22) | BIT(24) | BIT(25) | BIT(26))
-
-#define MCHP_INT_DIRECT_CAPABLE_BITMAP (BIT(13) | BIT(14) | BIT(15) |\
-	BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(23))
-
-/* GIRQ13 I2C controllers 0 - 4. Direct capable */
-#define MCHP_INT13_I2C(x) BIT(x)
-
-/* GIRQ14 DMA channels 0 - 15. Direct capable */
-#define MCHP_INT14_DMA(x) BIT(x)
-
-/* GIQ15 interrupt sources. Direct capable */
-#define MCHP_INT15_UART_0		BIT(0)
-#define MCHP_INT15_UART_1		BIT(1)
-#define MCHP_INT15_EMI_0		BIT(2)
-#define MCHP_INT15_EMI_1		BIT(3)
-#define MCHP_INT15_EMI_2		BIT(4)
-#define MCHP_INT15_ACPI_EC0_IBF		BIT(5)
-#define MCHP_INT15_ACPI_EC0_OBE		BIT(6)
-#define MCHP_INT15_ACPI_EC1_IBF		BIT(7)
-#define MCHP_INT15_ACPI_EC1_OBE		BIT(8)
-#define MCHP_INT15_ACPI_EC2_IBF		BIT(9)
-#define MCHP_INT15_ACPI_EC2_OBE		BIT(10)
-#define MCHP_INT15_ACPI_EC3_IBF		BIT(11)
-#define MCHP_INT15_ACPI_EC3_OBE		BIT(12)
-#define MCHP_INT15_ACPI_EC4_IBF		BIT(13)
-#define MCHP_INT15_ACPI_EC4_OBE		BIT(14)
-#define MCHP_INT15_ACPI_PM1_CTL		BIT(15)
-#define MCHP_INT15_ACPI_PM1_EN		BIT(16)
-#define MCHP_INT15_ACPI_PM1_STS		BIT(17)
-#define MCHP_INT15_8042_OBE		BIT(18)
-#define MCHP_INT15_8042_IBF		BIT(19)
-#define MCHP_INT15_MAILBOX		BIT(20)
-#define MCHP_INT15_BDP0			BIT(22)
-
-/* GIRQ16 interrupt sources. Direct capable */
-#define MCHP_INT16_PKE_DONE		BIT(0)
-#define MCHP_INT16_RNG_DONE		BIT(2)
-#define MCHP_INT16_AESH_DONE		BIT(3)
-
-/* GIR17 interrupt sources. Direct capable */
-#define MCHP_INT17_PECI			BIT(0)
-#define MCHP_INT17_TACH_0		BIT(1)
-#define MCHP_INT17_TACH_1		BIT(2)
-#define MCHP_INT17_TACH_2		BIT(3)
-#define MCHP_INT17_TACH_3		BIT(4)
-#define MCHP_INT17_ADC_SINGLE		BIT(8)
-#define MCHP_INT17_ADC_REPEAT		BIT(9)
-#define MCHP_INT17_RCID_0		BIT(10)
-#define MCHP_INT17_RCID_1		BIT(11)
-#define MCHP_INT17_RCID_2		BIT(12)
-#define MCHP_INT17_LED_WDT_0		BIT(13)
-#define MCHP_INT17_LED_WDT_1		BIT(14)
-#define MCHP_INT17_LED_WDT_2		BIT(15)
-#define MCHP_INT17_LED_WDT_3		BIT(16)
-#define MCHP_INT17_PROCHOT		BIT(17)
-#define MCHP_INT17_RPM2PWM0_FAIL	BIT(20)
-#define MCHP_INT17_RPM2PWM0_STALL	BIT(21)
-#define MCHP_INT17_RPM2PWM1_FAIL	BIT(22)
-#define MCHP_INT17_RPM2PWM1_STALL	BIT(23)
-
-/* GIRQ18 interrupt sources. Direct capable */
-#define MCHP_INT18_SPIEP		BIT(0)
-#define MCHP_INT18_QMSPI		BIT(1)
-#define MCHP_INT18_GPSPI0_TXBE		BIT(2)
-#define MCHP_INT18_GPSPI0_RXBF		BIT(3)
-#define MCHP_INT18_GPSPI1_TXBE		BIT(4)
-#define MCHP_INT18_GPSPI1_RXBF		BIT(5)
-#define MCHP_INT18_BCM0_BUSY		BIT(6)
-#define MCHP_INT18_BCM0_ERR		BIT(7)
-#define MCHP_INT18_PS2_0		BIT(10)
-#define MCHP_INT18_PSPI			BIT(13)
-#define MCHP_INT18_CCT			BIT(20)
-#define MCHP_INT18_CCT_CAP0		BIT(21)
-#define MCHP_INT18_CCT_CAP1		BIT(22)
-#define MCHP_INT18_CCT_CAP2		BIT(23)
-#define MCHP_INT18_CCT_CAP3		BIT(24)
-#define MCHP_INT18_CCT_CAP4		BIT(25)
-#define MCHP_INT18_CCT_CAP6		BIT(26)
-#define MCHP_INT18_CCT_CMP0		BIT(27)
-#define MCHP_INT18_CCT_CMP1		BIT(28)
-
-/* GIRQ19 interrupt sources. Direct capable */
-#define MCHP_INT19_ESPI_PC		BIT(0)
-#define MCHP_INT19_ESPI_BM1		BIT(1)
-#define MCHP_INT19_ESPI_BM2		BIT(2)
-#define MCHP_INT19_ESPI_LTR		BIT(3)
-#define MCHP_INT19_ESPI_OOB_TX		BIT(4)
-#define MCHP_INT19_ESPI_OOB_RX		BIT(5)
-#define MCHP_INT19_ESPI_FC		BIT(6)
-#define MCHP_INT19_ESPI_RESET		BIT(7)
-#define MCHP_INT19_ESPI_VW_EN		BIT(8)
-#define MCHP_INT19_ESPI_SAF		BIT(9)
-#define MCHP_INT19_ESPI_SAF_ERR		BIT(10)
-#define MCHP_INT19_ESPI_SAF_CACHE	BIT(11)
-
-/* GIRQ20 interrupt sources. Direct capable */
-#define MCHP_INT20_STAP_OBF		BIT(0)
-#define MCHP_INT20_STAP_IBF		BIT(1)
-#define MCHP_INT20_STAP_WAKE		BIT(2)
-#define MCHP_INT20_OTP			BIT(3)
-#define MCHP_INT20_ISPI			BIT(8)
-#define MCHP_INT20_CLK32K_MON		BIT(9)
-
-/* GIRQ21 interrupt sources. Direct capable */
-#define MCHP_INT21_WDG			BIT(2)
-#define MCHP_INT21_WEEK_ALARM		BIT(3)
-#define MCHP_INT21_WEEK_SUB		BIT(4)
-#define MCHP_INT21_WEEK_1SEC		BIT(5)
-#define MCHP_INT21_WEEK_1SEC_SUB	BIT(6)
-#define MCHP_INT21_WEEK_PWR_PRES	BIT(7)
-#define MCHP_INT21_RTC			BIT(8)
-#define MCHP_INT21_RTC_ALARM		BIT(9)
-#define MCHP_INT21_VCI_OVRD		BIT(10)
-#define MCHP_INT21_VCI_IN0		BIT(11)
-#define MCHP_INT21_VCI_IN1		BIT(12)
-#define MCHP_INT21_VCI_IN2		BIT(13)
-#define MCHP_INT21_VCI_IN3		BIT(14)
-#define MCHP_INT21_VCI_IN4		BIT(15)
-#define MCHP_INT21_PS2_0A_WAKE		BIT(18)
-#define MCHP_INT21_PS2_0B_WAKE		BIT(19)
-#define MCHP_INT21_KEYSCAN		BIT(25)
-#define MCHP_INT21_GLUE			BIT(26)
-
-/* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
-#define MCHP_INT22_WAKE_ONLY_SPIEP	BIT(0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	BIT(1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	BIT(2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	BIT(3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	BIT(4)
-#define MCHP_INT22_WAKE_ONLY_I2C4	BIT(5)
-#define MCHP_INT22_WAKE_ONLY_ESPI	BIT(9)
-#define MCHP_INT22_WAKE_ONLY_STAP	BIT(15)
-
-/* GIRQ23 sources. Direct capable */
-#define MCHP_INT23_BTMR16_0		BIT(0)
-#define MCHP_INT23_BTMR16_1		BIT(1)
-#define MCHP_INT23_BTMR16_2		BIT(2)
-#define MCHP_INT23_BTMR16_3		BIT(3)
-#define MCHP_INT23_BTMR32_0		BIT(4)
-#define MCHP_INT23_BTMR32_1		BIT(5)
-#define MCHP_INT23_CNT16_0		BIT(6)
-#define MCHP_INT23_CNT16_1		BIT(7)
-#define MCHP_INT23_CNT16_2		BIT(8)
-#define MCHP_INT23_CNT16_3		BIT(9)
-#define MCHP_INT21_RTMR			BIT(10)
-#define MCHP_INT21_HTMR_0		BIT(16)
-#define MCHP_INT21_HTMR_1		BIT(17)
-
-/* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
-#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
-
-/* GIRQ25 sources Master-to-Slave v=[7:10], Source=[0:3] */
-#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
-
-/* UART Peripheral 0 <= x <= 1 */
-#define MCHP_UART_INSTANCES	2
-#define MCHP_UART_SPACING	0x400
-#define MCHP_UART_CFG_OFS	0x300
-#define MCHP_UART_CONFIG_BASE(x) \
-	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_RUNTIME_BASE(x) \
-	(MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_GIRQ		15
-#define MCHP_UART0_GIRQ_BIT	(MCHP_INT15_UART_0)
-#define MCHP_UART1_GIRQ_BIT	(MCHP_INT15_UART_1)
-#define MCHP_UART_GIRQ_BIT(x)	BIT(x)
-/* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY	BIT(5)
-
-/*
- * GPIO
- * MCHP each Port contains 32 GPIO's.
- * GPIO Control 1 registers are 32-bit registers starting at
- * MCHP_GPIO_BASE.
- * index = octal GPIO number from MCHP specification.
- * port/bank = index >> 5
- * id = index & 0x1F
- *
- * The port/bank, id pair may also be used to access GPIO's via
- * parallel I/O registers if GPIO control is configured for
- * parallel I/O.
- *
- * From ec/chip/mec1701/config_chip.h
- * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
- *
- * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
- *
- * Example: GPIO043, Control 1 register address = 0x4008108c
- * port/bank = 0x23 >> 5 = 1
- * id        = 0x23 & 0x1F = 0x03
- * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
- *
- * Example: GPIO235, Control 1 register address = 0x40081274
- * port/bank = 0x9d >> 5   = 4
- * id        = 0x9d & 0x1f = 0x1d
- * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
- *
- */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
-
-/* MCHP implements 6 GPIO ports */
-#define MCHP_GPIO_MAX_PORT	6
-#define UNIMPLEMENTED_GPIO_BANK	MCHP_GPIO_MAX_PORT
-/*
- * In MECxxxx documentation GPIO numbers are octal, each control
- * register is located on a 32-bit boundary.
- */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
-
-/*
- * GPIO control register bit fields
- */
-#define MCHP_GPIO_CTRL_PUD_BITPOS	0
-#define MCHP_GPIO_CTRL_PUD_MASK0	0x03
-#define MCHP_GPIO_CTRL_PUD_MASK		0x03
-#define MCHP_GPIO_CTRL_PUD_NONE		0x00
-#define MCHP_GPIO_CTRL_PUD_PU		0x01
-#define MCHP_GPIO_CTRL_PUD_PD		0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER	0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS	2
-#define MCHP_GPIO_CTRL_PWR_MASK0	0x03
-#define MCHP_GPIO_CTRL_PWR_MASK		GENMASK(2, 1)
-#define MCHP_GPIO_CTRL_PWR_VTR		0
-#define MCHP_GPIO_CTRL_PWR_OFF		(0x02U << 2)
-#define MCHP_GPIO_INTDET_MASK		0xF0U
-#define MCHP_GPIO_INTDET_LVL_LO		0x00
-#define MCHP_GPIO_INTDET_LVL_HI		0x10U
-#define MCHP_GPIO_INTDET_DISABLED	0x40U
-#define MCHP_GPIO_INTDET_EDGE_RIS	0xD0U
-#define MCHP_GPIO_INTDET_EDGE_FALL	0xE0U
-#define MCHP_GPIO_INTDET_EDGE_BOTH	0xF0U
-#define MCHP_GPIO_INTDET_EDGE_EN	BIT(7)
-#define MCHP_GPIO_PUSH_PULL		0U
-#define MCHP_GPIO_OPEN_DRAIN		BIT(8)
-#define MCHP_GPIO_INPUT			0U
-#define MCHP_GPIO_OUTPUT		BIT(9)
-#define MCHP_GPIO_OUTSET_CTRL		0U
-#define MCHP_GPIO_OUTSEL_PAR		BIT(10)
-#define MCHP_GPIO_POLARITY_NINV		0U
-#define MCHP_GPIO_POLARITY_INV		BIT(11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS	12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0	0x07U
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK	(0x07U << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO	0
-#define MCHP_GPIO_CTRL_FUNC_1		(1U << 12)
-#define MCHP_GPIO_CTRL_FUNC_2		(2U << 12)
-#define MCHP_GPIO_CTRL_FUNC_3		(3U << 12)
-#define MCHP_GPIO_CTRL_FUNC_4		(4U << 12)
-#define MCHP_GPIO_CTRL_FUNC_5		(5U << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL		BIT(16)
-/* MEC172x implements input pad disable */
-#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS	15
-#define MCHP_GPIO_CTRL_DIS_INPUT_BIT	BIT(15)
-
-/*
- * GPIO Parallel Input and Output registers.
- * gpio_bank in [0, 5]
- */
-#define MCHP_GPIO_PARIN(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
-#define MCHP_GPIO_PAROUT(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
-
-/* Basic timers */
-#define MCHP_TMR_SPACING	0x20
-#define MCHP_TMR16_INSTANCES	4
-#define MCHP_TMR32_INSTANCES	2
-#define MCHP_TMR16_MAX		(MCHP_TMR16_INSTANCES)
-#define MCHP_TMR32_MAX		(MCHP_TMR32_INSTANCES)
-#define MCHP_TMR16_BASE(n)	(MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR32_BASE(n)	(MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR16_GIRQ		23
-#define MCHP_TMR16_GIRQ_BIT(n)	BIT(0 + (n))
-#define MCHP_TMR32_GIRQ		23
-#define MCHP_TMR32_GIRQ_BIT(n)	BIT(4 + (n))
-
-/* 16-bit Counter/timer */
-#define MCHP_CNT16_SPACING	0x20
-#define MCHP_CNT16_INSTANCES	4
-#define MCHP_CNT16_BASE(n)	\
-	(MCHP_CNT16_0_BASE + (n) * MCHP_CNT16_SPACING)
-#define MCHP_CNT16_GIRQ		23
-#define MCHP_CNT16_GIRQ_BIT(x)	BIT(6 + (x))
-
-/* RTimer */
-#define MCHP_RTMR_GIRQ		21
-#define MCHP_RTMR_GIRQ_BIT(x)	MCHP_INT21_RTMR
-
-/* Watchdog */
-/* MEC152x specific registers */
-#define MCHP_WDG_STATUS			REG32(MCHP_WDG_BASE + 0x10)
-#define MCHP_WDG_IEN			REG32(MCHP_WDG_BASE + 0x14)
-/* Status */
-#define MCHP_WDG_STS_IRQ		BIT(0)
-/* Interrupt enable */
-#define MCHP_WDG_IEN_IRQ_EN		BIT(0)
-#define MCHP_WDG_GIRQ			21
-#define MCHP_WDG_GIRQ_BIT		BIT(2)
-/* Control register has a bit to enable IRQ generation */
-#define MCHP_WDG_RESET_IRQ_EN		BIT(9)
-
-/* VBAT */
-#define MCHP_VBAT_STS			REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CSS			REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_MONOTONIC_CTR_LO	REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI	REG32(MCHP_VBAT_BASE + 0x24)
-#define MCHP_VBAT_ROM_FEAT		REG32(MCHP_VBAT_BASE + 0x28)
-#define MCHP_VBAT_EMB_DEBOUNCE_EN	REG32(MCHP_VBAT_BASE + 0x34)
-/* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */
-#define MCHP_VBAT_RAM_SIZE		128
-#define MCHP_VBAT_RAM(wnum)		\
-	REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4))
-#define MCHP_VBAT_RAM8(bnum)		\
-	REG8(MCHP_VBAT_RAM_BASE + (bnum))
-#define MCHP_VBAT_VWIRE_BACKUP		30
-/*
- * Miscellaneous firmware control fields
- * scratch pad index cannot be more than 32 as
- * MEC152x has 64 bytes = 16 words of scratch RAM
- */
-#define MCHP_IMAGETYPE_IDX	31
-
-/* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT		BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		0xF4u
-
-/* Bit definitions for MCHP_VBAT_CSS */
-#define MCHP_VBAT_CSS_SIL32K_EN		BIT(0)
-#define MCHP_VBAT_CSS_XTAL_EN		BIT(8)
-#define MCHP_VBAT_CSS_XTAL_SINGLE	BIT(9)
-#define MCHP_VBAT_CSS_XTAL_HSC_DIS	BIT(10)
-#define MCHP_VBAT_CSS_XTAL_CNT_POS	11
-#define MCHP_VBAT_CSS_XTAL_CNT_MASK	(0x03U << 11)
-#define MCHP_VBAT_CSS_SRC_POS		16
-#define MCHP_VBAT_CSS_SRC_MASK		(0x03U << 16)
-#define MCHP_VBAT_CSS_SRC_SIL_OSC	0
-#define MCHP_VBAT_CSS_SRC_XTAL		(1U << 16)
-/* Switch from 32KHZ_IN input to silicon OSC when VTR goes down */
-#define MCHP_VBAT_CSS_SRC_SWPS		(2U << 16)
-/* Switch from 32KHZ_IN input to XTAL on VBAT when VTR goes down */
-#define MCHP_VBAT_CSS_SRC_SWPX		(3U << 16)
-/* Disable 32Khz silicon oscillator when VBAT goes off */
-#define MCHP_VBAT_CSS_NVB_SUPS		BIT(18)
-
-/* Blinking-Breathing LED 0 <= n <= 2 */
-#define MCHP_BBLEB_INSTANCES	4
-#define MCHP_BBLED_BASE(n)	(MCHP_BBLED_0_BASE + (((n) & 0x03) * 256))
-
-/* EMI */
-#define MCHP_EMI_INSTANCES	3
-#define MCHP_EMI_SPACING	0x400
-#define MCHP_EMI_ECREG_OFS	0x100
-/* base of EMI registers only accessible by EC */
-#define MCHP_EMI_BASE(n) \
-	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING))
-/* base of EMI registers accessible by EC and Host */
-#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING))
-#define MCHP_EMI_GIRQ		15
-#define MCHP_EMI_GIRQ_BIT(n)	BIT(2 + (n))
-
-/* Mailbox */
-#define MCHP_MBX_ECREGS_OFS	0x100
-#define MCHP_MBX_RT_BASE	MCHP_MBOX_BASE
-#define MCHP_MBX_BASE		(MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	BIT(20)
-
-/* MEC172x includes one instance of the BIOS Debug Port
- * capable of capturing Host I/O port 0x80 and 0x90 writes.
- * EC Data Value register:
- * bits[7:0] oldest FIFO data from Host
- * bits[15:16] data attributes/status
- * Read with 16 or 32 access guarantees attributes/status bits
- * correspond to data in bits[7:0].
- */
-#define MCHP_BDP0_HDATA		REG32(MCHP_BDP0_BASE)
-#define MCHP_BDP0_DATTR		REG16(MCHP_BDP0_BASE + 0x100)
-#define MCHP_BDP0_CONFIG	REG32(MCHP_BDP0_BASE + 0x104)
-#define MCHP_BDP0_STATUS	REG8(MCHP_BDP0_BASE + 0x108)
-#define MCHP_BDP0_INTR_EN	REG8(MCHP_BDP0_BASE + 0x109)
-#define MCHP_BDP0_STS_IEN	REG16(MCHP_BDP0_BASE + 0x108)
-#define MCHP_BDP0_SNAPSHOT	REG32(MCHP_BDP0_BASE + 0x10C)
-#define MCHP_BDP0_CAPTURE	REG32(MCHP_BDP0_BASE + 0x110)
-#define MCHP_BDP0_ACTV		REG8(MCHP_BDP0_BASE + 0x330)
-#define MCHP_BDP0_ALIAS_HDATA	REG8(MCHP_BDP0_BASE + 0x400)
-#define MCHP_BDP0_ALIAS_ACTV	REG8(MCHP_BDP0_BASE + 0x730)
-#define MCHP_BDP0_ALIAS_BLN	REG8(MCHP_BDP0_BASE + 0x7F0)
-
-#define MCHP_BDP0_GIRQ		15
-#define MCHP_BDP0_GIRQ_BIT	BIT(22)
-
-/* BDP DATATR as 16-bit value bit definitions */
-#define MCHP_BDP_DATTR_POS		0
-#define MCHP_BDP_DATTR_DATA_MASK	0xff
-#define MCHP_BDP_DATTR_LANE_POS		8
-#define MCHP_BDP_DATTR_LANE_MASK	GENMASK(9, 8)
-#define MCHP_BDP_DATTR_LANE_0		0
-#define MCHP_BDP_DATTR_LANE_1		(1U << 8)
-#define MCHP_BDP_DATTR_LANE_2		(2U << 8)
-#define MCHP_BDP_DATTR_LANE_3		(3U << 8)
-#define MCHP_BDP_DATTR_LEN_POS		10
-#define MCHP_BDP_DATTR_LEN_MASK		GENMASK(11, 10)
-#define MCHP_BDP_DATTR_LEN_1		0
-#define MCHP_BDP_DATTR_LEN_2		(1U << 10)
-#define MCHP_BDP_DATTR_LEN_4		(2U << 10)
-#define MCHP_BDP_DATTR_LEN_INVAL	(3U << 10)
-#define MCHP_BDP_DATTR_NE		BIT(12)
-#define MCHP_BDP_DATTR_OVR		BIT(13)
-#define MCHP_BDP_DATTR_THRH		BIT(14)
-
-/* BDP Configuration */
-#define MCHP_BDP_CFG_FLUSH_FIFO		BIT(0)
-#define MCHP_BDP_CFG_SNAPSHOT_CLR	BIT(1)
-#define MCHP_BDP_CFG_FIFO_THRH_POS	8
-#define MCHP_BDP_CFG_FIFO_THRH_1	0
-#define MCHP_BDP_CFG_FIFO_THRH_4	(1U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_8	(2U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_16	(3U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_20	(4U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_24	(5U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_28	(6U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_30	(7U << 8)
-#define MCHP_BDP_CFG_SRST		BIT(31)
-
-/* BDP Status */
-#define MCHP_BDP_STATUS_MASK		GENMASK(2, 0)
-#define MCHP_BDP_STATUS_NOT_EMPTY	BIT(0)
-#define MCHP_BDP_STATUS_OVERRUN		BIT(1)
-#define MCHP_BDP_STATUS_THRH		BIT(2)
-
-/* BDP Interrupt enable */
-#define MCHP_BDP_IEN_THRH		BIT(0)
-
-/* PWM SZ 144 pin package has 9 PWM's */
-#define MCHP_PWM_INSTANCES		9
-#define MCHP_PWM_ID_MAX			(MCHP_PWM_INSTANCES)
-#define MCHP_PWM_SPACING		16
-#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING))
-
-/* TACH */
-#define MCHP_TACH_INSTANCES	4
-#define MCHP_TACH_SPACING	16
-#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING))
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	BIT(1 + (x))
-
-/* FAN */
-#define MCHP_FAN_INSTANCES	2
-#define MCHP_FAN_SPACING	0x80U
-#define MCHP_FAN_BASE(x)	\
-	(MCHP_RPM2PWM0_BASE + ((x) * MCHP_FAN_SPACING))
-#define MCHP_FAN_SETTING(x)	REG16(MCHP_FAN_BASE(x) + 0x0)
-#define MCHP_FAN_CFG1(x)	REG8(MCHP_FAN_BASE(x) + 0x2)
-#define MCHP_FAN_CFG2(x)	REG8(MCHP_FAN_BASE(x) + 0x3)
-#define MCHP_FAN_PWM_DIVIDE(x)	REG8(MCHP_FAN_BASE(x) + 0x4)
-#define MCHP_FAN_GAIN(x)	REG8(MCHP_FAN_BASE(x) + 0x5)
-#define MCHP_FAN_SPIN_UP(x)	REG8(MCHP_FAN_BASE(x) + 0x6)
-#define MCHP_FAN_STEP(x)	REG8(MCHP_FAN_BASE(x) + 0x7)
-#define MCHP_FAN_MIN_DRV(x)	REG8(MCHP_FAN_BASE(x) + 0x8)
-#define MCHP_FAN_VALID_CNT(x)	REG8(MCHP_FAN_BASE(x) + 0x9)
-#define MCHP_FAN_DRV_FAIL(x)	REG16(MCHP_FAN_BASE(x) + 0xa)
-#define MCHP_FAN_TARGET(x)	REG16(MCHP_FAN_BASE(x) + 0xc)
-#define MCHP_FAN_READING(x)	REG16(MCHP_FAN_BASE(x) + 0xe)
-#define MCHP_FAN_BASE_FREQ(x)	REG8(MCHP_FAN_BASE(x) + 0x10)
-#define MCHP_FAN_STATUS(x)	REG8(MCHP_FAN_BASE(x) + 0x11)
-
-/* ACPI EC */
-#define MCHP_ACPI_EC_INSTANCES		5
-#define MCHP_ACPI_EC_MAX		(MCHP_ACPI_EC_INSTANCES)
-#define MCHP_ACPI_EC_SPACING		0x400
-#define MCHP_ACPI_EC_BASE(x) \
-	(MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING))
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	BIT(5 + ((x) * 2))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	BIT(6 + ((x) * 2))
-
-/* ACPI PM1 */
-#define MCHP_ACPI_PM1_ECREGS_OFS	0x100
-#define MCHP_ACPI_PM_RT_BASE		MCHP_ACPI_PM1_BASE
-#define MCHP_ACPI_PM_EC_BASE	(MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	BIT(15)
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	BIT(16)
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	BIT(17)
-
-/* 8042 */
-#define MCHP_8042_ECREGS_OFS		0x100
-#define MCHP_8042_GIRQ			15
-#define MCHP_8042_OBE_GIRQ_BIT		BIT(18)
-#define MCHP_8042_IBF_GIRQ_BIT		BIT(19)
-
-/* I2C controllers 0 - 4 include SMBus network layer functionality. */
-#define MCHP_I2C_CTRL0		0
-#define MCHP_I2C_CTRL1		1
-#define MCHP_I2C_CTRL2		2
-#define MCHP_I2C_CTRL3		3
-#define MCHP_I2C_CTRL4		4
-#define MCHP_I2C_CTRL_MAX	5
-
-#define MCHP_I2C_SEP0		0x400
-
-/*
- * MEC172x SZ(144-pin) package implements 15 ports. No Port 11.
- * LJ(176-pin) package implements 16 ports.
- * Any port can be mapped to any I2C controller.
- * I2C port values must be zero based consecutive whole numbers due to
- * port number used as an index for I2C the mutex list, etc.
- * Refer to chip i2c_port_to_controller function for mapping
- * of port to controller.
- * Locking must occur by-controller (not by-port).
- */
-#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ)\
-		|| defined(CHIP_VARIANT_MEC1727LJ))
-#define MCHP_I2C_PORT_MASK GENMASK(15, 0)
-#else
-#define MCHP_I2C_PORT_MASK (GENMASK(15, 0) & ~BIT(11))
-#endif
-enum MCHP_i2c_port {
-	MCHP_I2C_PORT0 = 0,
-	MCHP_I2C_PORT1,
-	MCHP_I2C_PORT2,
-	MCHP_I2C_PORT3,
-	MCHP_I2C_PORT4,
-	MCHP_I2C_PORT5,
-	MCHP_I2C_PORT6,
-	MCHP_I2C_PORT7,
-	MCHP_I2C_PORT8,
-	MCHP_I2C_PORT9,
-	MCHP_I2C_PORT10,
-	MCHP_I2C_PORT11,
-	MCHP_I2C_PORT12,
-	MCHP_I2C_PORT13,
-	MCHP_I2C_PORT14,
-	MCHP_I2C_PORT15,
-	MCHP_I2C_PORT_COUNT,
-};
-
-/* I2C ports & Configs */
-#define I2C_CONTROLLER_COUNT	MCHP_I2C_CTRL_MAX
-#define I2C_PORT_COUNT		MCHP_I2C_PORT_COUNT
-
-/* All I2C controllers connected to GIRQ13 */
-#define MCHP_I2C_GIRQ		13
-/* I2C[0:7] -> GIRQ13 bits[0:7] */
-#define MCHP_I2C_GIRQ_BIT(n)	BIT((n))
-
-/* Keyboard scan matrix */
-#define MCHP_KS_GIRQ		21
-#define MCHP_KS_GIRQ_BIT	BIT(25)
-#define MCHP_KS_DIRECT_NVIC	135
-
-/* ADC */
-#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ)\
-		|| defined(CHIP_VARIANT_MEC1727LJ))
-#define MCHP_ADC_CHAN_MASK GENMASK(15, 0)
-#else
-#define MCHP_ADC_CHAN_MASK GENMASK(7, 0)
-#endif
-#define MCHP_ADC_GIRQ			17
-#define MCHP_ADC_GIRQ_SINGLE_BIT	BIT(8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT	BIT(9)
-#define MCHP_ADC_SINGLE_DIRECT_NVIC	78
-#define MCHP_ADC_REPEAT_DIRECT_NVIC	79
-#define MCHP_ADC_CONFIG			REG32(MCHP_ADC_BASE + 0x7c)
-#define MCHP_ADC_CONFIG_DFLT		0x0101U
-#define MCHP_ADC_CFG_CLK_LO_TM_MSK	GENMASK(7, 0)
-#define MCHP_ADC_CFG_CLK_HI_TM_MSK	GENMASK(15, 8)
-#define MCHP_ADC_VREF_CSEL		REG32(MCHP_ADC_BASE + 0x80)
-#define MCHP_ADC_VREF_CSEL_MSK(ch)	(0x03U << ((ch) * 2U))
-#define MCHP_ADC_VREF_CSEL_GPIO(ch)	BIT((ch) * 2U)
-#define MCHP_ADC_VREF_CTRL		REG32(MCHP_ADC_BASE + 0x84)
-#define MCHP_ADC_VREF_CTRL_DFLT		0U
-#define MCHP_ADC_VCTRL_CHRG_DLY_MSK	GENMASK(15, 0)
-#define MCHP_ADC_VCTRL_SW_DLY_MSK	GENMASK(28, 16)
-#define MCHP_ADC_VCTRL_DRV_UNUSED_LO	BIT(29)
-#define MCHP_ADC_VCTRL_SEL_STS_RO_POS	30
-#define MCHP_ADC_VCTRL_SEL_STS_RO_MSK	GENMASK(31, 30)
-#define MCHP_ADC_SAR_ADC_CTRL		REG32(MCHP_ADC_BASE + 0x88)
-#define MCHP_ADC_SAR_ADC_CTRL_DFLT	((0x202U << 7) | (0x03U << 1))
-#define MCHP_ADC_SAC_DIFF_INPUT		BIT(0)
-#define MCHP_ADC_SAC_RES_POS		1
-#define MCHP_ADC_SAC_RES_MSK		GENMASK(2, 1)
-#define MCHP_ADC_SAC_RES_10BIT		(2U << 1)
-#define MCHP_ADC_SAC_RES_12BIT		(3U << 1)
-#define MCHP_ADC_SAC_RJ_10BIT		BIT(3)
-#define MCHP_ADC_SAC_WU_DLY_POS		7
-#define MCHP_ADC_SAC_WU_DLY_MSK		GENMASK(16, 7)
-#define MCHP_ADC_SAC_WU_DLY_DLFT	(0x202U << 7)
-
-/* Hibernation timer */
-#define MCHP_HTIMER_SPACING		0x20
-#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING))
-#define MCHP_HTIMER_GIRQ		21
-/* HTIMER[0:1] -> GIRQ21 bits[1:2] */
-#define MCHP_HTIMER_GIRQ_BIT(n)		BIT(1 + (n))
-#define MCHP_HTIMER_DIRECT_NVIC(n)	(112 + (n))
-
-/* General Purpose SPI (GP-SPI) */
-#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port) * 0x80))
-#define MCHP_SPI_AR(port)	REG8(MCHP_SPI_BASE(port) + 0x00)
-#define MCHP_SPI_CR(port)	REG8(MCHP_SPI_BASE(port) + 0x04)
-#define MCHP_SPI_SR(port)	REG8(MCHP_SPI_BASE(port) + 0x08)
-#define MCHP_SPI_TD(port)	REG8(MCHP_SPI_BASE(port) + 0x0c)
-#define MCHP_SPI_RD(port)	REG8(MCHP_SPI_BASE(port) + 0x10)
-#define MCHP_SPI_CC(port)	REG8(MCHP_SPI_BASE(port) + 0x14)
-#define MCHP_SPI_CG(port)	REG8(MCHP_SPI_BASE(port) + 0x18)
-/* Addresses of TX/RX register used in tables */
-#define MCHP_SPI_TD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x0c)
-#define MCHP_SPI_RD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x10)
-/* All GP-SPI controllers connected to GIRQ18 */
-#define MCHP_SPI_GIRQ			18
-#define MCHP_SPI_GIRQ_TXBE_BIT(x)	BIT(2 + ((x) * 2))
-#define MCHP_SPI_GIRQ_RXBF_BIT(x)	BIT(3 + ((x) * 2))
-#define MCHP_GPSPI0_ID			0
-#define MCHP_GPSPI1_ID			1
-
-/*
- * Quad Master SPI (QMSPI)
- * MEC172x implements 16 descriptors, support for two chip selects,
- * chip select timing and a local DMA unit with 3 RX channels and
- * 3 TX channels. It retains support of the legacy DMA block.
- */
-#define MCHP_QMSPI_MAX_DESCR	16
-#define MCHP_QMSPI_GIRQ		18
-#define MCHP_QMSPI_GIRQ_BIT	BIT(1)
-#define MCHP_QMSPI_DIRECT_NVIC 91
-/* SAF DMA mode when QMSPI when eSPI SAF is enabled */
-#define MCHP_QMSPI_M_SAF_EN	BIT(2)
-/* Local DMA enables in Mode register */
-#define MCHP_QMSPI_M_LDRX_EN	BIT(3)
-#define MCHP_QMSPI_M_LDTX_EN	BIT(4)
-/* Chip select implemented in bit[13:12] of the Mode register. */
-#define MCHP_QMSPI_M_CS_POS	12
-#define MCHP_QMSPI_M_CS_MASK0	0x03
-#define MCHP_QMSPI_M_CS_MASK	GENMASK(13, 12)
-#define MCHP_QMSPI_M_CS0	0U
-#define MCHP_QMSPI_M_CS1	BIT(12)
-/* QMSPI alternate clock divider when CS1 is active. */
-#define MCHP_QMSPI0_ALTM	REG32(MCHP_QMSPI0_BASE + 0xc0)
-#define MCHP_QMSPI0_ALTM_EN	BIT(0)
-/* QMSPI taps select */
-#define MCHP_QMSPI0_TAPS		REG32(MCHP_QMSPI0_BASE + 0xd0)
-/* QMSPI Taps adjust */
-#define MCHP_QMSPI0_TAPS_ADJ		REG32(MCHP_QMSPI0_BASE + 0xd4)
-#define MCHP_QMSPI0_TAPS_SCK_POS	0
-#define MCHP_QMSPI0_TAPS_SCK_MSK	GENMASK(7, 0)
-#define MCHP_QMSPI0_TAPS_CTL_POS	8
-#define MCHP_QMSPI0_TAPS_CTL_MSK	GENMASK(15, 8)
-/* QMSPI Taps control */
-#define MCHP_QMSPI0_TAPS_CTRL		REG32(MCHP_QMSPI0_BASE + 0xd4)
-#define MCHP_QMSPI0_TAPS_CTRL_MODE_POS	0
-#define MCHP_QMSPI0_TAPS_CTRL_MODE_MSK	GENMASK(1, 0)
-#define MCHP_QMSPI0_TAPS_CTRL_UPDATE	BIT(2)
-#define MCHP_QMSPI0_TAPS_CTRL_GO	BIT(8)
-#define MCHP_QMSPI0_TAPS_CTRL_MULT_POS	16
-#define MCHP_QMSPI0_TAPS_CTRL_MULT_MSK	GENMASK(18, 16)
-/* QMSPI LDMA descriptor enables */
-#define MCHP_QMSPI0_LDRX_DEN	REG32(MCHP_QMSPI0_BASE + 0x100)
-#define MCHP_QMSPI0_LDTX_DEN	REG32(MCHP_QMSPI0_BASE + 0x104)
-/*
- * QMSPI LDMA channel registers.
- * Each channel implement 3 32-bit registers:
- * control, memory base address, and transfer length.
- */
-#define MCHP_QMSPI0_LDRX_CHANS 3U
-#define MCHP_QMSPI0_LDTX_CHANS 3U
-#define MCHP_QMSPI0_LDRX_CTRL(n) REG32(MCHP_QMSPI0_BASE + 0x110 + ((n)*16U))
-#define MCHP_QMSPI0_LDRX_MBASE(n) REG32(MCHP_QMSPI0_BASE + 0x114 + ((n)*16U))
-#define MCHP_QMSPI0_LDRX_LEN(n) REG32(MCHP_QMSPI0_BASE + 0x118 + ((n)*16U))
-#define MCHP_QMSPI0_LDTX_CTRL(n) REG32(MCHP_QMSPI0_BASE + 0x140 + ((n)*16U))
-#define MCHP_QMSPI0_LDTX_MBASE(n) REG32(MCHP_QMSPI0_BASE + 0x144 + ((n)*16U))
-#define MCHP_QMSPI0_LDTX_LEN(n) REG32(MCHP_QMSPI0_BASE + 0x148 + ((n)*16U))
-/* LDMA RX or TX channel control register */
-#define MCHP_QMSPI_LDC_MSK		GENMASK(6, 0)
-#define MCHP_QMSPI_LDC_EN		BIT(0)
-#define MCHP_QMSPI_LDC_RSTART_EN	BIT(1)
-#define MCHP_QMSPI_LDC_RSTART_MA_EN	BIT(2)
-#define MCHP_QMSPI_LDC_LEN_EN		BIT(3)
-#define MCHP_QMSPI_LDC_ACC_SZ_POS	4
-#define MCHP_QMSPI_LDC_ACC_SZ_MSK	GENMASK(5, 4)
-#define MCHP_QMSPI_LDC_ACC_1BYTE	0
-#define MCHP_QMSPI_LDC_ACC_2BYTES	(1U << 4)
-#define MCHP_QMSPI_LDC_ACC_4BYTES	(2U << 4)
-#define MCHP_QMSPI_LDC_INCR_ADDR	BIT(6)
-
-/* eSPI */
-/* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4	8
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_ID_EMI2	0xF
-#define MCHP_ESPI_IO_BAR_BDP0		0x10
-#define MCHP_ESPI_IO_BAR_BDP0_ALT	0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
-#define MCHP_ESPI_IO_BAR_TB32		0x14
-#define MCHP_ESPI_IO_BAR_GLUE		0x16
-
-/* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
-#define MCHP_ESPI_MBAR_ID_MBOX		0
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_0	1
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_1	2
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_2	3
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_3	4
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_4	5
-#define MCHP_ESPI_MBAR_ID_EMI_0		6
-#define MCHP_ESPI_MBAR_ID_EMI_1		7
-#define MCHP_ESPI_MBAR_ID_EMI_2		8
-#define MCHP_ESPI_MBAR_ID_TB32		9
-
-/* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
-#define MCHP_ESPI_SIRQ_MBOX		0 /* Host SIRQ */
-#define MCHP_ESPI_SIRQ_MBOX_SMI		1 /* Host SMI */
-#define MCHP_ESPI_SIRQ_8042_KB		2 /* KIRQ */
-#define MCHP_ESPI_SIRQ_8042_MS		3 /* MIRQ */
-#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF	4
-#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF	5
-#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF	6
-#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF	7
-#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF	8
-#define MCHP_ESPI_SIRQ_UART0		9
-#define MCHP_ESPI_SIRQ_UART1		10
-#define MCHP_ESPI_SIRQ_EMI0_HEV		11 /* Host Event */
-#define MCHP_ESPI_SIRQ_EMI0_EC2H	12 /* EC to Host */
-#define MCHP_ESPI_SIRQ_EMI1_HEV		13
-#define MCHP_ESPI_SIRQ_EMI1_EC2H	14
-#define MCHP_ESPI_SIRQ_EMI2_HEV		15
-#define MCHP_ESPI_SIRQ_EMI2_EC2H	16
-#define MCHP_ESPI_SIRQ_RTC		17
-#define MCHP_ESPI_SIRQ_EC		18
-
-#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
-#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
-
-/*
- * eSPI RESET, channel enables and operations except Master-to-Slave
- * WWires are all on GIRQ19
- */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		BIT(0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		BIT(1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		BIT(2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		BIT(3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	BIT(4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	BIT(5)
-#define MCHP_ESPI_FC_GIRQ_BIT		BIT(6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	BIT(7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	BIT(8)
-#define MCHP_ESPI_SAF_DONE_GIRQ_BIT	BIT(9)
-#define MCHP_ESPI_SAF_ERR_GIRQ_BIT	BIT(10)
-#define MCHP_ESPI_SAF_CACHE_GIRQ_BIT	BIT(11)
-
-/* eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25 */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
-/*
- * Four source bits, SRC[0:3] per Master-to-Slave register
- * v = MSVW [0:10]
- * n = VWire SRC bit = [0:3]
- */
-#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
-
-#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
-
-/* DMA */
-#define MCHP_DMA_MAX_CHAN	16
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
-#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
-
-/*
- * Available DMA channels.
- *
- * On MCHP, any DMA channel may serve any device. Since we have
- * 14 channels and 14 device request signals, we make each channel
- * dedicated to the device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MCHP_DMAC_I2C0_SLAVE = 0,
-	MCHP_DMAC_I2C0_MASTER,
-	MCHP_DMAC_I2C1_SLAVE,
-	MCHP_DMAC_I2C1_MASTER,
-	MCHP_DMAC_I2C2_SLAVE,
-	MCHP_DMAC_I2C2_MASTER,
-	MCHP_DMAC_I2C3_SLAVE,
-	MCHP_DMAC_I2C3_MASTER,
-	MCHP_DMAC_I2C4_SLAVE,
-	MCHP_DMAC_I2C5_MASTER,
-	MCHP_DMAC_QMSPI0_TX,
-	MCHP_DMAC_QMSPI0_RX,
-	MCHP_DMAC_SPI0_TX,
-	MCHP_DMAC_SPI0_RX,
-	MCHP_DMAC_SPI1_TX,
-	MCHP_DMAC_SPI1_RX,
-	/* Channel count */
-	MCHP_DMAC_COUNT,
-};
-
-/*
- * Peripheral device DMA Device ID's for bits [15:9]
- * in DMA channel control register.
- */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_I2C4_SLV_REQ_ID	8
-#define MCHP_DMA_I2C4_MTR_REQ_ID	9
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	10
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	11
-#define MCHP_DMA_SPI0_TX_REQ_ID		12
-#define MCHP_DMA_SPI0_RX_REQ_ID		13
-#define MCHP_DMA_SPI1_TX_REQ_ID		14
-#define MCHP_DMA_SPI1_RX_REQ_ID		15
-
-/*
- * Hardware delay register.
- * Write of 0 <= n <= 31 will stall the Cortex-M4
- * for n+1 microseconds. Interrupts will not be
- * serviced during the delay period. Reads have
- * no effect.
- */
-#define MCHP_USEC_DELAY_REG_ADDR 0x08000000
-#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
-
-#endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h
deleted file mode 100644
index 65936caa2d..0000000000
--- a/chip/mchp/registers.h
+++ /dev/null
@@ -1,895 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for Microchip MEC family processors
- */
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-
-#if defined(CHIP_FAMILY_MEC152X)
-#include "registers-mec152x.h"
-#elif defined(CHIP_FAMILY_MEC170X)
-#include "registers-mec1701.h"
-#elif defined(CHIP_FAMILY_MEC172X)
-#include "registers-mec172x.h"
-#else
-#error "Unsupported chip family"
-#endif
-
-/* Common registers */
-/* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_SOURCE(x)		REG32(MCHP_INTx_BASE(x) + 0x0)
-#define MCHP_INT_ENABLE(x)		REG32(MCHP_INTx_BASE(x) + 0x4)
-#define MCHP_INT_RESULT(x)		REG32(MCHP_INTx_BASE(x) + 0x8)
-#define MCHP_INT_DISABLE(x)		REG32(MCHP_INTx_BASE(x) + 0xc)
-#define MCHP_INT_BLK_EN			REG32(MCHP_INT_BASE + 0x200)
-#define MCHP_INT_BLK_DIS		REG32(MCHP_INT_BASE + 0x204)
-#define MCHP_INT_BLK_IRQ		REG32(MCHP_INT_BASE + 0x208)
-
-/* EC Chip Configuration */
-#define MCHP_CHIP_LEGACY_DEV_ID		REG8(MCHP_CHIP_BASE + 0x20)
-#define MCHP_CHIP_LEGACY_DEV_REV	REG8(MCHP_CHIP_BASE + 0x21)
-
-/* Power/Clocks/Resets */
-#define MCHP_PCR_SYS_SLP_CTL		REG32(MCHP_PCR_BASE + 0x00)
-#define MCHP_PCR_PROC_CLK_CTL		REG32(MCHP_PCR_BASE + 0x04)
-#define MCHP_PCR_SLOW_CLK_CTL		REG32(MCHP_PCR_BASE + 0x08)
-#define MCHP_PCR_CHIP_OSC_ID		REG32(MCHP_PCR_BASE + 0x0C)
-#define MCHP_PCR_PWR_RST_STS		REG32(MCHP_PCR_BASE + 0x10)
-#define MCHP_PCR_PWR_RST_CTL		REG32(MCHP_PCR_BASE + 0x14)
-#define MCHP_PCR_SYS_RST		REG32(MCHP_PCR_BASE + 0x18)
-#define MCHP_PCR_SLP_EN0		REG32(MCHP_PCR_BASE + 0x30)
-#define MCHP_PCR_SLP_EN1		REG32(MCHP_PCR_BASE + 0x34)
-#define MCHP_PCR_SLP_EN2		REG32(MCHP_PCR_BASE + 0x38)
-#define MCHP_PCR_SLP_EN3		REG32(MCHP_PCR_BASE + 0x3C)
-#define MCHP_PCR_SLP_EN4		REG32(MCHP_PCR_BASE + 0x40)
-#define MCHP_PCR_CLK_REQ0		REG32(MCHP_PCR_BASE + 0x50)
-#define MCHP_PCR_CLK_REQ1		REG32(MCHP_PCR_BASE + 0x54)
-#define MCHP_PCR_CLK_REQ2		REG32(MCHP_PCR_BASE + 0x58)
-#define MCHP_PCR_CLK_REQ3		REG32(MCHP_PCR_BASE + 0x5C)
-#define MCHP_PCR_CLK_REQ4		REG32(MCHP_PCR_BASE + 0x60)
-#define MCHP_PCR_RST_EN0		REG32(MCHP_PCR_BASE + 0x70)
-#define MCHP_PCR_RST_EN1		REG32(MCHP_PCR_BASE + 0x74)
-#define MCHP_PCR_RST_EN2		REG32(MCHP_PCR_BASE + 0x78)
-#define MCHP_PCR_RST_EN3		REG32(MCHP_PCR_BASE + 0x7C)
-#define MCHP_PCR_RST_EN4		REG32(MCHP_PCR_BASE + 0x80)
-#define MCHP_PCR_SLP_EN(x)		REG32(MCHP_PCR_BASE + 0x30 + ((x)<<2))
-#define MCHP_PCR_CLK_REQ(x)		REG32(MCHP_PCR_BASE + 0x50 + ((x)<<2))
-#define MCHP_PCR_RST_EN(x)		REG32(MCHP_PCR_BASE + 0x70 + ((x)<<2))
-
-/* Bit definitions for MCHP_PCR_SYS_SLP_CTL */
-#define MCHP_PCR_SYS_SLP_LIGHT		(0ul << 0)
-#define MCHP_PCR_SYS_SLP_HEAVY		(1ul << 0)
-#define MCHP_PCR_SYS_SLP_ALL		(1ul << 3)
-/*
- * Set/clear PCR sleep enable bit for single device
- * d bits[10:8] = register 0 - 4
- * d bits[4:0] = register bit position
- */
-#define MCHP_PCR_SLP_EN_DEV(d) \
-	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) |= (1ul << ((d) & 0x1f)))
-#define MCHP_PCR_SLP_DIS_DEV(d) \
-	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) &= ~(1ul << ((d) & 0x1f)))
-/*
- * Set/clear bit pattern specified by mask in a single PCR sleep enable
- * register.
- * id = zero based ID of sleep enable register (0-4)
- * m = bit mask of bits to change
- */
-#define MCHP_PCR_SLP_EN_DEV_MASK(id, m)		(MCHP_PCR_SLP_EN((id)) |= (m))
-#define MCHP_PCR_SLP_DIS_DEV_MASK(id, m)	(MCHP_PCR_SLP_EN((id)) &= ~(m))
-/* Slow Clock Control Mask */
-#define MCHP_PCR_SLOW_CLK_CTL_MASK		0x03FFul
-
-/* TFDP */
-#define MCHP_TFDP_DATA		REG8(MCHP_TFDP_BASE + 0x00)
-#define MCHP_TFDP_CTRL		REG8(MCHP_TFDP_BASE + 0x04)
-
-/* UART */
-#define MCHP_UART_ACT(x)	REG8(MCHP_UART_CONFIG_BASE(x) + 0x30)
-#define MCHP_UART_CFG(x)	REG8(MCHP_UART_CONFIG_BASE(x) + 0xf0)
-/* DLAB=0 */
-#define MCHP_UART_RB(x) /*R*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_TB(x) /*W*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_IER(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
-/* DLAB=1 */
-#define MCHP_UART_PBRG0(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_PBRG1(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
-#define MCHP_UART_FCR(x) /*W*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
-#define MCHP_UART_IIR(x) /*R*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
-#define MCHP_UART_LCR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x3)
-#define MCHP_UART_MCR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x4)
-#define MCHP_UART_LSR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x5)
-#define MCHP_UART_MSR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x6)
-#define MCHP_UART_SCR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x7)
-/* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY	BIT(5)
-
-/* Timer */
-#define MCHP_TMR16_CNT(x)	REG32(MCHP_TMR16_BASE(x) + 0x0)
-#define MCHP_TMR16_PRE(x)	REG32(MCHP_TMR16_BASE(x) + 0x4)
-#define MCHP_TMR16_STS(x)	REG32(MCHP_TMR16_BASE(x) + 0x8)
-#define MCHP_TMR16_IEN(x)	REG32(MCHP_TMR16_BASE(x) + 0xc)
-#define MCHP_TMR16_CTL(x)	REG32(MCHP_TMR16_BASE(x) + 0x10)
-#define MCHP_TMR32_CNT(x)	REG32(MCHP_TMR32_BASE(x) + 0x0)
-#define MCHP_TMR32_PRE(x)	REG32(MCHP_TMR32_BASE(x) + 0x4)
-#define MCHP_TMR32_STS(x)	REG32(MCHP_TMR32_BASE(x) + 0x8)
-#define MCHP_TMR32_IEN(x)	REG32(MCHP_TMR32_BASE(x) + 0xc)
-#define MCHP_TMR32_CTL(x)	REG32(MCHP_TMR32_BASE(x) + 0x10)
-
-/* RTimer */
-#define MCHP_RTMR_COUNTER	REG32(MCHP_RTMR_BASE + 0x00)
-#define MCHP_RTMR_PRELOAD	REG32(MCHP_RTMR_BASE + 0x04)
-#define MCHP_RTMR_CONTROL	REG8(MCHP_RTMR_BASE + 0x08)
-#define MCHP_RTMR_SOFT_INTR	REG8(MCHP_RTMR_BASE + 0x0c)
-
-/* Watch dog timer */
-#define MCHP_WDG_LOAD			REG16(MCHP_WDG_BASE + 0x0)
-#define MCHP_WDG_CTL			REG16(MCHP_WDG_BASE + 0x4)
-#define MCHP_WDG_KICK			REG8(MCHP_WDG_BASE + 0x8)
-#define MCHP_WDG_CNT			REG16(MCHP_WDG_BASE + 0xc)
-#define MCHP_WDT_CTL_ENABLE		BIT(0)
-#define MCHP_WDT_CTL_HTMR_STALL_EN	BIT(2)
-#define MCHP_WDT_CTL_WKTMR_STALL_EN	BIT(3)
-#define MCHP_WDT_CTL_JTAG_STALL_EN	BIT(4)
-
-/* Blinking-Breathing LED */
-#define MCHP_BBLED_CONFIG(x)		REG32(MCHP_BBLED_BASE(x) + 0x00)
-#define MCHP_BBLED_LIMITS(x)		REG32(MCHP_BBLED_BASE(x) + 0x04)
-#define MCHP_BBLED_LIMIT_MIN(x)		REG8(MCHP_BBLED_BASE(x) + 0x04)
-#define MCHP_BBLED_LIMIT_MAX(x)		REG8(MCHP_BBLED_BASE(x) + 0x06)
-#define MCHP_BBLED_DELAY(x)		REG32(MCHP_BBLED_BASE(x) + 0x08)
-#define MCHP_BBLED_UPDATE_STEP(x)	REG32(MCHP_BBLED_BASE(x) + 0x0C)
-#define MCHP_BBLED_UPDATE_INTV(x)	REG32(MCHP_BBLED_BASE(x) + 0x10)
-#define MCHP_BBLED_OUTPUT_DLY(x)	REG8(MCHP_BBLED_BASE(x) + 0x14)
-/* BBLED Configuration Register */
-#define MCHP_BBLED_ASYMMETRIC		BIT(16)
-#define MCHP_BBLED_WDT_RELOAD_BITPOS	8
-#define MCHP_BBLED_WDT_RELOAD_MASK0	0xFFul
-#define MCHP_BBLED_WDT_RELOAD_MASK	(0xFFul << 8)
-#define MCHP_BBLED_RESET		BIT(7)
-#define MCHP_BBLED_EN_UPDATE		BIT(6)
-#define MCHP_BBLED_PWM_SIZE_BITPOS	4
-#define MCHP_BBLED_PWM_SIZE_MASK0	0x03ul
-#define MCHP_BBLED_PWM_SIZE_MASK	(0x03ul << 4)
-#define MCHP_BBLED_PWM_SIZE_6BIT	(0x02ul << 4)
-#define MCHP_BBLED_PWM_SIZE_7BIT	(0x01ul << 4)
-#define MCHP_BBLED_PWM_SIZE_8BIT	(0x00ul << 4)
-#define MCHP_BBLED_SYNC			BIT(3)
-#define MCHP_BBLED_CLK_48M		BIT(2)
-#define MCHP_BBLED_CLK_32K		0
-#define MCHP_BBLED_CTRL_MASK		0x03ul
-#define MCHP_BBLED_CTRL_ALWAYS_ON	0x03ul
-#define MCHP_BBLED_CTRL_BLINK		0x02ul
-#define MCHP_BBLED_CTRL_BREATHE		0x01ul
-#define MCHP_BBLED_CTRL_OFF		0x00ul
-/* BBLED Delay Register */
-#define MCHP_BBLED_DLY_MASK		0x0FFFul
-#define MCHP_BBLED_DLY_LO_BITPOS	0
-#define MCHP_BBLED_DLY_LO_MASK		0x0FFFul
-#define MCHP_BBLED_DLY_HI_BITPOS	12
-#define MCHP_BBLED_DLY_HI_MASK		(0x0FFFul << 12)
-/*
- * BBLED Update Step Register
- * 8 update fields numbered 0 - 7
- */
-#define MCHP_BBLED_UPD_STEP_MASK0	0x0Ful
-#define MCHP_BBLED_UPD_STEP_MASK(u)	(0x0Ful << (((u) & 0x07) + 4))
-/*
- * BBLED Update Interval Register
- * 8 interval fields numbered 0 - 7
- */
-#define MCHP_BBLED_UPD_INTV_MASK0	0x0Ful
-#define MCHP_BBLED_UPD_INTV_MASK(i)	(0x0Ful << (((i) & 0x07) + 4))
-
-/* EMI */
-#define MCHP_EMI_H2E_MBX(n)		REG8(MCHP_EMI_BASE(n) + 0x0)
-#define MCHP_EMI_E2H_MBX(n)		REG8(MCHP_EMI_BASE(n) + 0x1)
-#define MCHP_EMI_MBA0(n)		REG32(MCHP_EMI_BASE(n) + 0x4)
-#define MCHP_EMI_MRL0(n)		REG16(MCHP_EMI_BASE(n) + 0x8)
-#define MCHP_EMI_MWL0(n)		REG16(MCHP_EMI_BASE(n) + 0xa)
-#define MCHP_EMI_MBA1(n)		REG32(MCHP_EMI_BASE(n) + 0xc)
-#define MCHP_EMI_MRL1(n)		REG16(MCHP_EMI_BASE(n) + 0x10)
-#define MCHP_EMI_MWL1(n)		REG16(MCHP_EMI_BASE(n) + 0x12)
-#define MCHP_EMI_ISR(n)			REG16(MCHP_EMI_BASE(n) + 0x14)
-#define MCHP_EMI_HCE(n)			REG16(MCHP_EMI_BASE(n) + 0x16)
-#define MCHP_EMI_ISR_B0(n)		REG8(MCHP_EMI_RT_BASE(n) + 0x8)
-#define MCHP_EMI_ISR_B1(n)		REG8(MCHP_EMI_RT_BASE(n) + 0x9)
-#define MCHP_EMI_IMR_B0(n)		REG8(MCHP_EMI_RT_BASE(n) + 0xa)
-#define MCHP_EMI_IMR_B1(n)		REG8(MCHP_EMI_RT_BASE(n) + 0xb)
-
-/* Mailbox */
-#define MCHP_MBX_INDEX			REG8(MCHP_MBX_RT_BASE + 0x0)
-#define MCHP_MBX_DATA			REG8(MCHP_MBX_RT_BASE + 0x1)
-#define MCHP_MBX_H2E_MBX		REG8(MCHP_MBX_BASE + 0x0)
-#define MCHP_MBX_E2H_MBX		REG8(MCHP_MBX_BASE + 0x4)
-#define MCHP_MBX_ISR			REG8(MCHP_MBX_BASE + 0x8)
-#define MCHP_MBX_IMR			REG8(MCHP_MBX_BASE + 0xc)
-#define MCHP_MBX_REG(x)			REG8(MCHP_MBX_BASE + 0x10 + (x))
-
-/* PWM */
-#define MCHP_PWM_ON(x)			REG32(MCHP_PWM_BASE(x) + 0x00)
-#define MCHP_PWM_OFF(x)			REG32(MCHP_PWM_BASE(x) + 0x04)
-#define MCHP_PWM_CFG(x)			REG32(MCHP_PWM_BASE(x) + 0x08)
-
-/* TACH */
-#define MCHP_TACH_CTRL(x)		REG32(MCHP_TACH_BASE(x))
-#define MCHP_TACH_CTRL_LO(x)		REG16(MCHP_TACH_BASE(x) + 0x00)
-#define MCHP_TACH_CTRL_CNT(x)		REG16(MCHP_TACH_BASE(x) + 0x02)
-#define MCHP_TACH_STATUS(x)		REG8(MCHP_TACH_BASE(x) + 0x04)
-#define MCHP_TACH_LIMIT_HI(x)		REG16(MCHP_TACH_BASE(x) + 0x08)
-#define MCHP_TACH_LIMIT_LO(x)		REG16(MCHP_TACH_BASE(x) + 0x0C)
-
-/* ACPI */
-#define MCHP_ACPI_EC_EC2OS(x, y)	REG8(MCHP_ACPI_EC_BASE(x) + 0x100 + (y))
-#define MCHP_ACPI_EC_STATUS(x)		REG8(MCHP_ACPI_EC_BASE(x) + 0x104)
-#define MCHP_ACPI_EC_BYTE_CTL(x)	REG8(MCHP_ACPI_EC_BASE(x) + 0x105)
-#define MCHP_ACPI_EC_OS2EC(x, y)	REG8(MCHP_ACPI_EC_BASE(x) + 0x108 + (y))
-#define MCHP_ACPI_PM1_STS1		REG8(MCHP_ACPI_PM_RT_BASE + 0x0)
-#define MCHP_ACPI_PM1_STS2		REG8(MCHP_ACPI_PM_RT_BASE + 0x1)
-#define MCHP_ACPI_PM1_EN1		REG8(MCHP_ACPI_PM_RT_BASE + 0x2)
-#define MCHP_ACPI_PM1_EN2		REG8(MCHP_ACPI_PM_RT_BASE + 0x3)
-#define MCHP_ACPI_PM1_CTL1		REG8(MCHP_ACPI_PM_RT_BASE + 0x4)
-#define MCHP_ACPI_PM1_CTL2		REG8(MCHP_ACPI_PM_RT_BASE + 0x5)
-#define MCHP_ACPI_PM2_CTL1		REG8(MCHP_ACPI_PM_RT_BASE + 0x6)
-#define MCHP_ACPI_PM2_CTL2		REG8(MCHP_ACPI_PM_RT_BASE + 0x7)
-#define MCHP_ACPI_PM_STS		REG8(MCHP_ACPI_PM_EC_BASE + 0x10)
-
-/* 8042 */
-#define MCHP_8042_OBF_CLR		REG8(MCHP_8042_BASE + 0x0)
-#define MCHP_8042_H2E			REG8(MCHP_8042_BASE + 0x100)
-#define MCHP_8042_E2H			REG8(MCHP_8042_BASE + 0x100)
-#define MCHP_8042_STS			REG8(MCHP_8042_BASE + 0x104)
-#define MCHP_8042_KB_CTRL		REG8(MCHP_8042_BASE + 0x108)
-#define MCHP_8042_PCOBF			REG8(MCHP_8042_BASE + 0x114)
-#define MCHP_8042_ACT			REG8(MCHP_8042_BASE + 0x330)
-
-/* PROCHOT */
-#define MCHP_PCHOT_CUM_CNT		REG32(MCHP_PROCHOT_BASE + 0x00)
-#define MCHP_PCHOT_DTY_CYC_CNT		REG32(MCHP_PROCHOT_BASE + 0x04)
-#define MCHP_PCHOT_DTY_PRD_CNT		REG32(MCHP_PROCHOT_BASE + 0x08)
-#define MCHP_PCHOT_STS_CTRL		REG32(MCHP_PROCHOT_BASE + 0x0C)
-#define MCHP_PCHOT_ASERT_CNT		REG32(MCHP_PROCHOT_BASE + 0x10)
-#define MCHP_PCHOT_ASERT_CNT_LMT	REG32(MCHP_PROCHOT_BASE + 0x14)
-#define MCHP_PCHOT_TEST			REG32(MCHP_PROCHOT_BASE + 0x18)
-
-/* I2C registers access given controller base address */
-#define MCHP_I2C_CTRL(addr)		REG8(addr)
-#define MCHP_I2C_STATUS(addr)		REG8(addr)
-#define MCHP_I2C_OWN_ADDR(addr)		REG16(addr + 0x4)
-#define MCHP_I2C_DATA(addr)		REG8(addr + 0x8)
-#define MCHP_I2C_MASTER_CMD(addr)	REG32(addr + 0xc)
-#define MCHP_I2C_SLAVE_CMD(addr)	REG32(addr + 0x10)
-#define MCHP_I2C_PEC(addr)		REG8(addr + 0x14)
-#define MCHP_I2C_DATA_TIM_2(addr)	REG8(addr + 0x18)
-#define MCHP_I2C_COMPLETE(addr)		REG32(addr + 0x20)
-#define MCHP_I2C_IDLE_SCALE(addr)	REG32(addr + 0x24)
-#define MCHP_I2C_CONFIG(addr)		REG32(addr + 0x28)
-#define MCHP_I2C_BUS_CLK(addr)		REG16(addr + 0x2c)
-#define MCHP_I2C_BLK_ID(addr)		REG8(addr + 0x30)
-#define MCHP_I2C_REV(addr)		REG8(addr + 0x34)
-#define MCHP_I2C_BB_CTRL(addr)		REG8(addr + 0x38)
-#define MCHP_I2C_TST_DATA_TIM(addr)	REG32(addr + 0x3c)
-#define MCHP_I2C_DATA_TIM(addr)		REG32(addr + 0x40)
-#define MCHP_I2C_TOUT_SCALE(addr)	REG32(addr + 0x44)
-#define MCHP_I2C_SLAVE_TX_BUF(addr)	REG8(addr + 0x48)
-#define MCHP_I2C_SLAVE_RX_BUF(addr)	REG8(addr + 0x4c)
-#define MCHP_I2C_MASTER_TX_BUF(addr)	REG8(addr + 0x50)
-#define MCHP_I2C_MASTER_RX_BUF(addr)	REG8(addr + 0x54)
-#define MCHP_I2C_TEST_1(addr)		REG32(addr + 0x58)
-#define MCHP_I2C_TEST_2(addr)		REG32(addr + 0x5c)
-#define MCHP_I2C_WAKE_STS(addr)		REG8(addr + 0x60)
-#define MCHP_I2C_WAKE_EN(addr)		REG8(addr + 0x64)
-#define MCHP_I2C_TEST_3(addr)		REG32(addr + 0x68)
-
-/* Keyboard scan matrix */
-#define MCHP_KS_KSO_SEL			REG32(MCHP_KEYSCAN_BASE + 0x4)
-#define MCHP_KS_KSI_INPUT		REG32(MCHP_KEYSCAN_BASE + 0x8)
-#define MCHP_KS_KSI_STATUS		REG32(MCHP_KEYSCAN_BASE + 0xc)
-#define MCHP_KS_KSI_INT_EN		REG32(MCHP_KEYSCAN_BASE + 0x10)
-#define MCHP_KS_EXT_CTRL		REG32(MCHP_KEYSCAN_BASE + 0x14)
-
-/* ADC */
-#define MCHP_ADC_CTRL		REG32(MCHP_ADC_BASE + 0x0)
-#define MCHP_ADC_DELAY		REG32(MCHP_ADC_BASE + 0x4)
-#define MCHP_ADC_STS		REG32(MCHP_ADC_BASE + 0x8)
-#define MCHP_ADC_SINGLE		REG32(MCHP_ADC_BASE + 0xc)
-#define MCHP_ADC_REPEAT		REG32(MCHP_ADC_BASE + 0x10)
-#define MCHP_ADC_READ(x)	REG32(MCHP_ADC_BASE + 0x14 + ((x) * 0x4))
-
-/* Hibernation timer */
-#define MCHP_HTIMER_PRELOAD(x)		REG16(MCHP_HTIMER_ADDR(x) + 0x0)
-#define MCHP_HTIMER_CONTROL(x)		REG16(MCHP_HTIMER_ADDR(x) + 0x4)
-#define MCHP_HTIMER_COUNT(x)		REG16(MCHP_HTIMER_ADDR(x) + 0x8)
-
-/* Week timer and BGPO control */
-#define MCHP_WKTIMER_CTRL		REG32(MCHP_WKTIMER_BASE + 0)
-#define MCHP_WKTIMER_ALARM_CNT		REG32(MCHP_WKTIMER_BASE + 0x04)
-#define MCHP_WKTIMER_COMPARE		REG32(MCHP_WKTIMER_BASE + 0x08)
-#define MCHP_WKTIMER_CLK_DIV		REG32(MCHP_WKTIMER_BASE + 0x0c)
-#define MCHP_WKTIMER_SUBSEC_ISEL	REG32(MCHP_WKTIMER_BASE + 0x10)
-#define MCHP_WKTIMER_SUBWK_CTRL		REG32(MCHP_WKTIMER_BASE + 0x14)
-#define MCHP_WKTIMER_SUBWK_ALARM	REG32(MCHP_WKTIMER_BASE + 0x18)
-#define MCHP_WKTIMER_BGPO_DATA		REG32(MCHP_WKTIMER_BASE + 0x1c)
-#define MCHP_WKTIMER_BGPO_POWER		REG32(MCHP_WKTIMER_BASE + 0x20)
-#define MCHP_WKTIMER_BGPO_RESET		REG32(MCHP_WKTIMER_BASE + 0x24)
-
-/* Quad Master SPI (QMSPI) */
-#define MCHP_QMSPI0_MODE		REG32(MCHP_QMSPI0_BASE + 0x00)
-#define MCHP_QMSPI0_MODE_ACT_SRST	REG8(MCHP_QMSPI0_BASE + 0x00)
-#define MCHP_QMSPI0_MODE_SPI_MODE	REG8(MCHP_QMSPI0_BASE + 0x01)
-#define MCHP_QMSPI0_MODE_FDIV		REG8(MCHP_QMSPI0_BASE + 0x02)
-#define MCHP_QMSPI0_CTRL		REG32(MCHP_QMSPI0_BASE + 0x04)
-#define MCHP_QMSPI0_EXE			REG8(MCHP_QMSPI0_BASE + 0x08)
-#define MCHP_QMSPI0_IFCTRL		REG8(MCHP_QMSPI0_BASE + 0x0C)
-#define MCHP_QMSPI0_STS			REG32(MCHP_QMSPI0_BASE + 0x10)
-#define MCHP_QMSPI0_BUFCNT_STS		REG32(MCHP_QMSPI0_BASE + 0x14)
-#define MCHP_QMSPI0_IEN			REG32(MCHP_QMSPI0_BASE + 0x18)
-#define MCHP_QMSPI0_BUFCNT_TRIG		REG32(MCHP_QMSPI0_BASE + 0x1C)
-#define MCHP_QMSPI0_TX_FIFO_ADDR	(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO8		REG8(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO16		REG16(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO32		REG32(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_RX_FIFO_ADDR	(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO8		REG8(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO16		REG16(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO32		REG32(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_DESCR(x)		\
-	REG32(MCHP_QMSPI0_BASE + 0x30 + ((x) * 4))
-/* Bits in MCHP_QMSPI0_MODE */
-#define MCHP_QMSPI_M_ACTIVATE		BIT(0)
-#define MCHP_QMSPI_M_SOFT_RESET		BIT(1)
-#define MCHP_QMSPI_M_SPI_MODE_MASK	(0x7ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE0		(0x0ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE3		(0x3ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE0_48M	(0x4ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE3_48M	(0x7ul << 8)
-/*
- * clock divider is 8-bit field in bits[23:16]
- * [1, 255] -> 48MHz / [1, 255], 0 -> 48MHz / 256
- */
-#define MCHP_QMSPI_M_CLKDIV_BITPOS	16
-#define MCHP_QMSPI_M_CLKDIV_48M		(1ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_24M		(2ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_16M		(3ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_12M		(4ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_8M		(6ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_6M		(8ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_1M		(48ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_188K	(0x100ul << 16)
-/* Bits in MCHP_QMSPI0_CTRL and MCHP_QMSPI_DESCR(x) */
-#define MCHP_QMSPI_C_1X			(0ul << 0) /* Full Duplex */
-#define MCHP_QMSPI_C_2X			(1ul << 0) /* Dual IO */
-#define MCHP_QMSPI_C_4X			(2ul << 0) /* Quad IO */
-#define MCHP_QMSPI_C_TX_DIS		(0ul << 2)
-#define MCHP_QMSPI_C_TX_DATA		(1ul << 2)
-#define MCHP_QMSPI_C_TX_ZEROS		(2ul << 2)
-#define MCHP_QMSPI_C_TX_ONES		(3ul << 2)
-#define MCHP_QMSPI_C_TX_DMA_DIS		(0ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_1B		(1ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_2B		(2ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_4B		(3ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_MASK	(3ul << 4)
-#define MCHP_QMSPI_C_RX_DIS		0
-#define MCHP_QMSPI_C_RX_EN		BIT(6)
-#define MCHP_QMSPI_C_RX_DMA_DIS		(0ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_1B		(1ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_2B		(2ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_4B		(3ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_MASK	(3ul << 7)
-#define MCHP_QMSPI_C_NO_CLOSE		0
-#define MCHP_QMSPI_C_CLOSE		BIT(9)
-#define MCHP_QMSPI_C_XFRU_BITS		(0ul << 10)
-#define MCHP_QMSPI_C_XFRU_1B		(1ul << 10)
-#define MCHP_QMSPI_C_XFRU_4B		(2ul << 10)
-#define MCHP_QMSPI_C_XFRU_16B		(3ul << 10)
-#define MCHP_QMSPI_C_XFRU_MASK		(3ul << 10)
-/* Control */
-#define MCHP_QMSPI_C_START_DESCR_BITPOS	12
-#define MCHP_QMSPI_C_START_DESCR_MASK	(0xFul << 12)
-#define MCHP_QMSPI_C_DESCR_MODE_EN	BIT(16)
-/* Descriptors, indicates the current descriptor is the last */
-#define MCHP_QMSPI_C_NEXT_DESCR_BITPOS	12
-#define MCHP_QMSPI_C_NEXT_DESCR_MASK0	0xFul
-#define MCHP_QMSPI_C_NEXT_DESCR_MASK \
-	((MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 12)
-#define MCHP_QMSPI_C_NXTD(n) ((n) << 12)
-#define MCHP_QMSPI_C_DESCR_LAST		BIT(16)
-/*
- * Total transfer length is the count in this field
- * scaled by units in MCHP_QMSPI_CTRL_XFRU_xxxx
- */
-#define MCHP_QMSPI_C_NUM_UNITS_BITPOS	17
-#define MCHP_QMSPI_C_MAX_UNITS		0x7ffful
-#define MCHP_QMSPI_C_NUM_UNITS_MASK0	0x7ffful
-#define MCHP_QMSPI_C_NUM_UNITS_MASK \
-	((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17)
-/* Bits in MCHP_QMSPI0_EXE */
-#define MCHP_QMSPI_EXE_START		BIT(0)
-#define MCHP_QMSPI_EXE_STOP		BIT(1)
-#define MCHP_QMSPI_EXE_CLR_FIFOS	BIT(2)
-/* MCHP QMSPI FIFO Sizes */
-#define MCHP_QMSPI_TX_FIFO_LEN		8
-#define MCHP_QMSPI_RX_FIFO_LEN		8
-/* Bits in MCHP_QMSPI0_STS and MCHP_QMSPI0_IEN */
-#define MCHP_QMSPI_STS_DONE		BIT(0)
-#define MCHP_QMSPI_STS_DMA_DONE		BIT(1)
-#define MCHP_QMSPI_STS_TX_BUFF_ERR	BIT(2)
-#define MCHP_QMSPI_STS_RX_BUFF_ERR	BIT(3)
-#define MCHP_QMSPI_STS_PROG_ERR		BIT(4)
-#define MCHP_QMSPI_STS_TX_BUFF_FULL	BIT(8)
-#define MCHP_QMSPI_STS_TX_BUFF_EMPTY	BIT(9)
-#define MCHP_QMSPI_STS_TX_BUFF_REQ	BIT(10)
-#define MCHP_QMSPI_STS_TX_BUFF_STALL	BIT(11) /* status only */
-#define MCHP_QMSPI_STS_RX_BUFF_FULL	BIT(12)
-#define MCHP_QMSPI_STS_RX_BUFF_EMPTY	BIT(13)
-#define MCHP_QMSPI_STS_RX_BUFF_REQ	BIT(14)
-#define MCHP_QMSPI_STS_RX_BUFF_STALL	BIT(15) /* status only */
-#define MCHP_QMSPI_STS_ACTIVE		BIT(16) /* status only */
-/* Bits in MCHP_QMSPI0_BUFCNT (read-only) */
-#define MCHP_QMSPI_BUFCNT_TX_BITPOS	0
-#define MCHP_QMSPI_BUFCNT_TX_MASK	0xFFFFul
-#define MCHP_QMSPI_BUFCNT_RX_BITPOS	16
-#define MCHP_QMSPI_BUFCNT_RX_MASK	(0xFFFFul << 16)
-#define MCHP_QMSPI0_ID			0
-
-/* eSPI */
-/* eSPI IO Component */
-/* Peripheral Channel Registers */
-#define MCHP_ESPI_PC_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x114)
-#define MCHP_ESPI_PC_IEN		REG32(MCHP_ESPI_IO_BASE + 0x118)
-#define MCHP_ESPI_PC_BAR_INHIBIT_LO	REG32(MCHP_ESPI_IO_BASE + 0x120)
-#define MCHP_ESPI_PC_BAR_INHIBIT_HI	REG32(MCHP_ESPI_IO_BASE + 0x124)
-#define MCHP_ESPI_PC_BAR_INIT_LD_0C	REG16(MCHP_ESPI_IO_BASE + 0x128)
-#define MCHP_ESPI_PC_EC_IRQ		REG8(MCHP_ESPI_IO_BASE + 0x12C)
-/* LTR Registers */
-#define MCHP_ESPI_IO_LTR_STATUS		REG16(MCHP_ESPI_IO_BASE + 0x220)
-#define MCHP_ESPI_IO_LTR_IEN		REG8(MCHP_ESPI_IO_BASE + 0x224)
-#define MCHP_ESPI_IO_LTR_CTRL		REG16(MCHP_ESPI_IO_BASE + 0x228)
-#define MCHP_ESPI_IO_LTR_MSG		REG16(MCHP_ESPI_IO_BASE + 0x22C)
-/* OOB Channel Registers */
-#define MCHP_ESPI_OOB_RX_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x240)
-#define MCHP_ESPI_OOB_RX_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x244)
-#define MCHP_ESPI_OOB_TX_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x248)
-#define MCHP_ESPI_OOB_TX_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x24C)
-#define MCHP_ESPI_OOB_RX_LEN		REG32(MCHP_ESPI_IO_BASE + 0x250)
-#define MCHP_ESPI_OOB_TX_LEN		REG32(MCHP_ESPI_IO_BASE + 0x254)
-#define MCHP_ESPI_OOB_RX_CTL		REG32(MCHP_ESPI_IO_BASE + 0x258)
-#define MCHP_ESPI_OOB_RX_IEN		REG8(MCHP_ESPI_IO_BASE + 0x25C)
-#define MCHP_ESPI_OOB_RX_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x260)
-#define MCHP_ESPI_OOB_TX_CTL		REG32(MCHP_ESPI_IO_BASE + 0x264)
-#define MCHP_ESPI_OOB_TX_IEN		REG8(MCHP_ESPI_IO_BASE + 0x268)
-#define MCHP_ESPI_OOB_TX_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x26C)
-/* Flash Channel Registers */
-#define MCHP_ESPI_FC_ADDR_LO		REG32(MCHP_ESPI_IO_BASE + 0x280)
-#define MCHP_ESPI_FC_ADDR_HI		REG32(MCHP_ESPI_IO_BASE + 0x284)
-#define MCHP_ESPI_FC_BUF_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x288)
-#define MCHP_ESPI_FC_BUF_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x28C)
-#define MCHP_ESPI_FC_XFR_LEN		REG32(MCHP_ESPI_IO_BASE + 0x290)
-#define MCHP_ESPI_FC_CTL		REG32(MCHP_ESPI_IO_BASE + 0x294)
-#define MCHP_ESPI_FC_IEN		REG8(MCHP_ESPI_IO_BASE + 0x298)
-#define MCHP_ESPI_FC_CONFIG		REG32(MCHP_ESPI_IO_BASE + 0x29C)
-#define MCHP_ESPI_FC_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x2A0)
-/* VWire Channel Registers */
-#define MCHP_ESPI_VW_STATUS		REG8(MCHP_ESPI_IO_BASE + 0x2B0)
-/* Global Registers */
-/* 32-bit register containing CAP_ID/CAP0/CAP1/PC_CAP */
-#define MCHP_ESPI_IO_REG32_A		REG32(MCHP_ESPI_IO_BASE + 0x2E0)
-#define MCHP_ESPI_IO_CAP_ID		REG8(MCHP_ESPI_IO_BASE + 0x2E0)
-#define MCHP_ESPI_IO_CAP0		REG8(MCHP_ESPI_IO_BASE + 0x2E1)
-#define MCHP_ESPI_IO_CAP1		REG8(MCHP_ESPI_IO_BASE + 0x2E2)
-#define MCHP_ESPI_IO_PC_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E3)
-/* 32-bit register containing VW_CAP/OOB_CAP/FC_CAP/PC_READY */
-#define MCHP_ESPI_IO_REG32_B		REG32(MCHP_ESPI_IO_BASE + 0x2E4)
-#define MCHP_ESPI_IO_VW_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E4)
-#define MCHP_ESPI_IO_OOB_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E5)
-#define MCHP_ESPI_IO_FC_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E6)
-#define MCHP_ESPI_IO_PC_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E7)
-/* 32-bit register containing OOB_READY/FC_READY/RESET_STATUS/RESET_IEN */
-#define MCHP_ESPI_IO_REG32_C		REG32(MCHP_ESPI_IO_BASE + 0x2E8)
-#define MCHP_ESPI_IO_OOB_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E8)
-#define MCHP_ESPI_IO_FC_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E9)
-#define MCHP_ESPI_IO_RESET_STATUS	REG8(MCHP_ESPI_IO_BASE + 0x2EA)
-#define MCHP_ESPI_IO_RESET_IEN		REG8(MCHP_ESPI_IO_BASE + 0x2EB)
-/* 32-bit register containing PLTRST_SRC/VW_READY */
-#define MCHP_ESPI_IO_REG32_D		REG32(MCHP_ESPI_IO_BASE + 0x2EC)
-#define MCHP_ESPI_IO_PLTRST_SRC		REG8(MCHP_ESPI_IO_BASE + 0x2EC)
-#define MCHP_ESPI_IO_VW_READY		REG8(MCHP_ESPI_IO_BASE + 0x2ED)
-/* Bits in MCHP_ESPI_IO_CAP0 */
-#define MCHP_ESPI_CAP0_PC_SUPP		0x01
-#define MCHP_ESPI_CAP0_VW_SUPP		0x02
-#define MCHP_ESPI_CAP0_OOB_SUPP		0x04
-#define MCHP_ESPI_CAP0_FC_SUPP		0x08
-#define MCHP_ESPI_CAP0_ALL_CHAN_SUPP	(MCHP_ESPI_CAP0_PC_SUPP | \
-					MCHP_ESPI_CAP0_VW_SUPP | \
-					MCHP_ESPI_CAP0_OOB_SUPP | \
-					MCHP_ESPI_CAP0_FC_SUPP)
-/* Bits in MCHP_ESPI_IO_CAP1 */
-#define MCHP_ESPI_CAP1_RW_MASK		0x37
-#define MCHP_ESPI_CAP1_MAX_FREQ_MASK	0x07
-#define MCHP_ESPI_CAP1_MAX_FREQ_20M	0
-#define MCHP_ESPI_CAP1_MAX_FREQ_25M	1
-#define MCHP_ESPI_CAP1_MAX_FREQ_33M	2
-#define MCHP_ESPI_CAP1_MAX_FREQ_50M	3
-#define MCHP_ESPI_CAP1_MAX_FREQ_66M	4
-#define MCHP_ESPI_CAP1_SINGLE_MODE	0
-#define MCHP_ESPI_CAP1_SINGLE_DUAL_MODE	BIT(0)
-#define MCHP_ESPI_CAP1_SINGLE_QUAD_MODE	BIT(1)
-#define MCHP_ESPI_CAP1_ALL_MODE		(MCHP_ESPI_CAP1_SINGLE_MODE | \
-					MCHP_ESPI_CAP1_SINGLE_DUAL_MODE | \
-					MCHP_ESPI_CAP1_SINGLE_QUAD_MODE)
-#define MCHP_ESPI_CAP1_IO_BITPOS	4
-#define MCHP_ESPI_CAP1_IO_MASK0		0x03
-#define MCHP_ESPI_CAP1_IO_MASK		(0x03ul << MCHP_ESPI_CAP1_IO_BITPOS)
-#define MCHP_ESPI_CAP1_IO1_VAL		0x00
-#define MCHP_ESPI_CAP1_IO12_VAL		0x01
-#define MCHP_ESPI_CAP1_IO24_VAL		0x02
-#define MCHP_ESPI_CAP1_IO124_VAL	0x03
-#define MCHP_ESPI_CAP1_IO1		(0x00 << 4)
-#define MCHP_ESPI_CAP1_IO12		(0x01 << 4)
-#define MCHP_ESPI_CAP1_IO24		(0x02 << 4)
-#define MCHP_ESPI_CAP1_IO124		(0x03 << 4)
-/* Bits in MCHP_ESPI_IO_RESET_STATUS and MCHP_ESPI_IO_RESET_IEN */
-#define MCHP_ESPI_RST_PIN_MASK		BIT(1)
-#define MCHP_ESPI_RST_CHG_STS		BIT(0)
-#define MCHP_ESPI_RST_IEN		BIT(0)
-/* Bits in MCHP_ESPI_IO_PLTRST_SRC */
-#define MCHP_ESPI_PLTRST_SRC_VW		0
-#define MCHP_ESPI_PLTRST_SRC_PIN	1
-/*
- * eSPI Slave Activate Register
- * bit[0] = 0 de-active block is clock-gates
- * bit[0] = 1 block is powered and functional
- */
-#define MCHP_ESPI_ACTIVATE		REG8(MCHP_ESPI_IO_BASE + 0x330)
-/*
- * IO BAR's starting at offset 0x134
- * b[16]=virtualized R/W
- * b[15:14]=0 reserved RO
- * b[13:8]=Logical Device Number RO
- * b[7:0]=mask
- */
-#define MCHP_ESPI_IO_BAR_CTL(x)	\
-	REG32(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x134)
-/* access mask field of eSPI IO BAR Control register */
-#define MCHP_ESPI_IO_BAR_CTL_MASK(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x134)
-/*
- * IO BAR's starting at offset 0x334
- * b[31:16] = I/O address
- * b[15:1]=0 reserved
- * b[0] = valid
- */
-#define MCHP_ESPI_IO_BAR(x) REG32(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x334)
-#define MCHP_ESPI_IO_BAR_VALID(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x334)
-#define MCHP_ESPI_IO_BAR_ADDR_LSB(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x336)
-#define MCHP_ESPI_IO_BAR_ADDR_MSB(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x337)
-#define MCHP_ESPI_IO_BAR_ADDR(x) \
-	REG16(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x336)
-/* eSPI Serial IRQ registers */
-#define MCHP_ESPI_IO_SERIRQ_REG(x)	REG8(MCHP_ESPI_IO_BASE + 0x3ac + (x))
-/* eSPI Virtual Wire Error Register */
-#define MCHP_ESPI_IO_VW_ERROR		REG8(MCHP_ESPI_IO_BASE + 0x3f0)
-/*
- * eSPI Logical Device Memory Host BAR's to specify Host memory
- * base address and valid bit.
- * Each Logical Device implementing memory access has an 80-bit register.
- * b[0]=Valid
- * b[15:1]=0(reserved)
- * b[79:16]=eSPI bus memory address(Host address space)
- */
-#define MCHP_ESPI_MBAR_VALID(x) \
-	REG8(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x130)
-#define MCHP_ESPI_MBAR_HOST_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x132)
-#define MCHP_ESPI_MBAR_HOST_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x134)
-#define MCHP_ESPI_MBAR_HOST_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x136)
-#define MCHP_ESPI_MBAR_HOST_ADDR_48_63(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x138)
-/*
- * eSPI SRAM BAR's
- * b[0,3,8:15] = 0 reserved
- * b[2:1] = access
- * b[7:4] = size
- * b[79:16] = Host address
- */
-#define MCHP_ESPI_SRAM_BAR_CFG(x) \
-	REG8(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1ac)
-#define MCHP_ESPI_SRAM_BAR_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1ae)
-#define MCHP_ESPI_SRAM_BAR_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b0)
-#define MCHP_ESPI_SRAM_BAR_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b2)
-#define MCHP_ESPI_SRAM_BAR_ADDR_48_63(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b4)
-/* eSPI Memory Bus Master Registers */
-#define MCHP_ESPI_BM_STATUS		REG32(MCHP_ESPI_MEM_BASE + 0x200)
-#define MCHP_ESPI_BM_IEN		REG32(MCHP_ESPI_MEM_BASE + 0x204)
-#define MCHP_ESPI_BM_CONFIG		REG32(MCHP_ESPI_MEM_BASE + 0x208)
-#define MCHP_ESPI_BM1_CTL		REG32(MCHP_ESPI_MEM_BASE + 0x210)
-#define MCHP_ESPI_BM1_HOST_ADDR_LO	REG32(MCHP_ESPI_MEM_BASE + 0x214)
-#define MCHP_ESPI_BM1_HOST_ADDR_HI	REG32(MCHP_ESPI_MEM_BASE + 0x218)
-#define MCHP_ESPI_BM1_EC_ADDR		REG32(MCHP_ESPI_MEM_BASE + 0x21c)
-#define MCHP_ESPI_BM2_CTL		REG32(MCHP_ESPI_MEM_BASE + 0x224)
-#define MCHP_ESPI_BM2_HOST_ADDR_LO	REG32(MCHP_ESPI_MEM_BASE + 0x228)
-#define MCHP_ESPI_BM2_HOST_ADDR_HI	REG32(MCHP_ESPI_MEM_BASE + 0x22c)
-#define MCHP_ESPI_BM2_EC_ADDR		REG32(MCHP_ESPI_MEM_BASE + 0x230)
-/*
- * eSPI Memory BAR's for Logical Devices
- * b[0] = Valid
- * b[2:1] = access
- * b[3] = 0 reserved
- * b[7:4] = size
- * b[15:8] = 0 reserved
- * b[47:16] = EC SRAM Address where Host address is mapped
- * b[79:48] = 0 reserved
- *
- * BAR's start at offset 0x330
- */
-#define MCHP_ESPI_MBAR_EC_VSIZE(x) \
-	REG32(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x330)
-#define MCHP_ESPI_MBAR_EC_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x332)
-#define MCHP_ESPI_MBAR_EC_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x334)
-#define MCHP_ESPI_MBAR_EC_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x336)
-
-/* eSPI Virtual Wire registers */
-#define MCHP_ESPI_MSVW_LEN	12
-#define MCHP_ESPI_SMVW_LEN	8
-
-#define MCHP_ESPI_MSVW_ADDR(n) \
-	((MCHP_ESPI_MSVW_BASE) + ((n) * (MCHP_ESPI_MSVW_LEN)))
-
-#define MCHP_ESPI_MSVW_MTOS_BITPOS 4
-
-#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_LO		0
-#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_HI		1
-#define MCHP_ESPI_MSVW_IRQSEL_DISABLED		4
-#define MCHP_ESPI_MSVW_IRQSEL_RISING		0x0d
-#define MCHP_ESPI_MSVW_IRQSEL_FALLING		0x0e
-#define MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES	0x0f
-
-/*
- * Mapping of eSPI Master Host VWire group indices to
- * MCHP eSPI Master to Slave 96-bit VWire registers.
- * MSVW_xy where xy = PCH VWire number.
- * Each PCH VWire number controls 4 virtual wires.
- */
-#define MSVW_H02	0
-#define MSVW_H03	1
-#define MSVW_H07	2
-#define MSVW_H41	3
-#define MSVW_H42	4
-#define MSVW_H43	5
-#define MSVW_H44	6
-#define MSVW_H47	7
-#define MSVW_H4A	8
-#define MSVW_HSPARE0	9
-#define MSVW_HSPARE1	10
-#define MSVW_MAX	11
-
-/* Access 32-bit word in 96-bit MSVW register. 0 <= w <= 2 */
-#define MSVW(id, w) \
-	REG32(MCHP_ESPI_MSVW_BASE + ((id) * 12) + (((w) & 0x03) * 4))
-/* Access index value in byte 0 */
-#define MCHP_ESPI_VW_M2S_INDEX(id)	REG8(MCHP_ESPI_VW_BASE + ((id) * 12))
-/*
- * Access MTOS_SOURCE and MTOS_STATE in byte 1
- * MTOS_SOURCE = b[1:0] specifies reset source
- * MTOS_STATE = b[7:4] are states loaded into SRC[0:3] on reset event
- */
-#define MCHP_ESPI_VW_M2S_MTOS(id) \
-	REG8(MCHP_ESPI_VW_BASE + 1 + ((id) * 12))
-/*
- * Access Index, MTOS Source, and MTOS State as 16-bit quantity.
- * Index in b[7:0]
- * MTOS Source in b[9:8]
- * MTOS State in b[15:12]
- */
-#define MCHP_ESPI_VW_M2S_INDEX_MTOS(id) \
-	REG16(MCHP_ESPI_VW_BASE + ((id) * 12))
-/* Access SRCn IRQ Select bit fields */
-#define MCHP_ESPI_VW_M2S_IRQSEL0(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 4)
-#define MCHP_ESPI_VW_M2S_IRQSEL1(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 5)
-#define MCHP_ESPI_VW_M2S_IRQSEL2(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 6)
-#define MCHP_ESPI_VW_M2S_IRQSEL3(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 7)
-#define MCHP_ESPI_VW_M2S_IRQSEL(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 4 + ((src) & 0x03))
-#define MCHP_ESPI_VW_M2S_IRQSEL_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + ((id) * 12) + 4)
-/* Access individual source bits */
-#define MCHP_ESPI_VW_M2S_SRC0(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 8)
-#define MCHP_ESPI_VW_M2S_SRC1(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 9)
-#define MCHP_ESPI_VW_M2S_SRC2(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 10)
-#define MCHP_ESPI_VW_M2S_SRC3(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 11)
-/*
- * Access all four Source bits as 32-bit value, Source bits are located
- * at bits[0, 8, 16, 24] of 32-bit word.
- */
-#define MCHP_ESPI_VW_M2S_SRC_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + 8 + ((id) * 12))
-/*
- * Access an individual Source bit as byte where
- * bit[0] contains the source bit.
- */
-#define MCHP_ESPI_VW_M2S_SRC(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + 8 + ((id) * 8) + ((src) & 0x03))
-
-/*
- * Indices of Slave to Master Virtual Wire registers.
- * Registers are 64-bit.
- * Host chipset groups VWires into groups of 4 with
- * a spec. defined index.
- * SMVW_Ixy where xy = eSPI Master defined index.
- * MCHP maps Host indices into its Slave to Master
- * 64-bit registers.
- */
-#define SMVW_H04	0
-#define SMVW_H05	1
-#define SMVW_H06	2
-#define SMVW_H40	3
-#define SMVW_H45	4
-#define SMVW_H46	5
-#define SMVW_HSPARE6	6
-#define SMVW_HSPARE7	7
-#define SMVW_HSPARE8	8
-#define SMVW_HSPARE9	9
-#define SMVW_HSPARE10	10
-#define SMVW_MAX	11
-
-/* Access 32-bit word of 64-bit SMVW register, 0 <= w <= 1 */
-#define SMVW(id, w) \
-	REG32(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200 + (((w) & 0x01) * 4))
-/* Access Index in b[7:0] of byte 0 */
-#define MCHP_ESPI_VW_S2M_INDEX(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200)
-/* Access STOM_SOURCE and STOM_STATE in byte 1
- * STOM_SOURCE = b[1:0]
- * STOM_STATE = b[7:4]
- */
-#define MCHP_ESPI_VW_S2M_STOM(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x201)
-/* Access Index, STOM_SOURCE, and STOM_STATE in bytes[1:0]
- * Index = b[7:0]
- * STOM_SOURCE = b[9:8]
- * STOM_STATE = [15:12]
- */
-#define MCHP_ESPI_VW_S2M_INDEX_STOM(id) \
-	REG16(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200)
-/* Access Change[0:3] RO bits. Set to 1 if any of SRC[0:3] change */
-#define MCHP_ESPI_VW_S2M_CHANGE(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x202)
-/* Access individual SRC bits
- * bit[0] = SRCn
- */
-#define MCHP_ESPI_VW_S2M_SRC0(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x204)
-#define MCHP_ESPI_VW_S2M_SRC1(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x205)
-#define MCHP_ESPI_VW_S2M_SRC2(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x206)
-#define MCHP_ESPI_VW_S2M_SRC3(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x207)
-/*
- * Access specified source bit as byte read/write.
- * Source bit is in bit[0] of byte.
- */
-#define MCHP_ESPI_VW_S2M_SRC(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id) * 8) + ((src) & 0x03))
-/* Access SRC[0:3] as 32-bit word
- * SRC0 = b[0]
- * SRC1 = b[8]
- * SRC2 = b[16]
- * SRC3 = b[24]
- */
-#define MCHP_ESPI_VW_S2M_SRC_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x204)
-
-/* DMA */
-#define MCHP_DMA_MAIN_CTRL REG8(MCHP_DMA_BASE + 0x00)
-#define MCHP_DMA_MAIN_PKT_RO REG32(MCHP_DMA_BASE + 0x04)
-#define MCHP_DMA_MAIN_FSM_RO REG8(MCHP_DMA_BASE + 0x08)
-/* DMA Channel Registers */
-#define MCHP_DMA_CH_ACT(n) REG8(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS))
-#define MCHP_DMA_CH_MEM_START(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x04)
-#define MCHP_DMA_CH_MEM_END(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x08)
-#define MCHP_DMA_CH_DEV_ADDR(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x0c)
-#define MCHP_DMA_CH_CTRL(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x10)
-#define MCHP_DMA_CH_ISTS(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x14)
-#define MCHP_DMA_CH_IEN(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x18)
-#define MCHP_DMA_CH_FSM_RO(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x1c)
-/*
- * DMA Channel 0 implements CRC-32 feature
- */
-#define MCHP_DMA_CH0_CRC32_EN		REG8(MCHP_DMA_CH_BASE + 0x20)
-#define MCHP_DMA_CH0_CRC32_DATA		REG32(MCHP_DMA_CH_BASE + 0x24)
-#define MCHP_DMA_CH0_CRC32_POST_STS	REG8(MCHP_DMA_CH_BASE + 0x28)
-/*
- * DMA Channel 1 implements memory fill feature
- */
-#define MCHP_DMA_CH1_FILL_EN \
-	REG8(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x20)
-#define MCHP_DMA_CH1_FILL_DATA \
-	REG32(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x24)
-/* Bits for DMA Main Control */
-#define MCHP_DMA_MAIN_CTRL_ACT		BIT(0)
-#define MCHP_DMA_MAIN_CTRL_SRST		BIT(1)
-/* Bits for DMA channel regs */
-#define MCHP_DMA_ACT_EN			BIT(0)
-/* DMA Channel Control */
-#define MCHP_DMA_ABORT			BIT(25)
-#define MCHP_DMA_SW_GO			BIT(24)
-#define MCHP_DMA_XFER_SIZE_MASK		(7ul << 20)
-#define MCHP_DMA_XFER_SIZE(x)		((x) << 20)
-#define MCHP_DMA_DIS_HW_FLOW		BIT(19)
-#define MCHP_DMA_INC_DEV		BIT(17)
-#define MCHP_DMA_INC_MEM		BIT(16)
-#define MCHP_DMA_DEV(x)			((x) << 9)
-#define MCHP_DMA_DEV_MASK0		(0x7f)
-#define MCHP_DMA_DEV_MASK		(0x7f << 9)
-#define MCHP_DMA_TO_DEV			BIT(8)
-#define MCHP_DMA_DONE			BIT(2)
-#define MCHP_DMA_RUN			BIT(0)
-/* DMA Channel Status */
-#define MCHP_DMA_STS_ALU_DONE		BIT(3)
-#define MCHP_DMA_STS_DONE		BIT(2)
-#define MCHP_DMA_STS_HWFL_ERR		BIT(1)
-#define MCHP_DMA_STS_BUS_ERR		BIT(0)
-
-/*
- * Required structure typedef for common/dma.h interface
- * !!! checkpatch.pl will not like this !!!
- * structure moved to chip level dma.c
- * We can't remove dma_chan_t as its used in DMA API header.
- */
-struct MCHP_dma_chan {
-	uint32_t act;		/* Activate */
-	uint32_t mem_start;	/* Memory start address */
-	uint32_t mem_end;	/* Memory end address */
-	uint32_t dev;		/* Device address */
-	uint32_t ctrl;		/* Control */
-	uint32_t int_status;	/* Interrupt status */
-	uint32_t int_enabled;	/* Interrupt enabled */
-	uint32_t chfsm;		/* channel fsm read-only */
-	uint32_t alu_en;	/* channels 0 & 1 only */
-	uint32_t alu_data;	/* channels 0 & 1 only */
-	uint32_t alu_sts;	/* channel 0 only */
-	uint32_t alu_ro;	/* channel 0 only */
-	uint32_t rsvd[4];	/* 0x30 - 0x3F */
-};
-
-/* Common code and header file must use this */
-typedef struct MCHP_dma_chan dma_chan_t;
-
-/* Wake pin definitions, defined at board-level */
-extern const enum gpio_signal hibernate_wake_pins[];
-extern const int hibernate_wake_pins_used;
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mchp/spi.c b/chip/mchp/spi.c
deleted file mode 100644
index 48712e8b7e..0000000000
--- a/chip/mchp/spi.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* QMSPI master module for MCHP MEC family */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-#include "spi_chip.h"
-#include "qmspi_chip.h"
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-#include "gpspi_chip.h"
-#endif
-#include "tfdp_chip.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
-#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
-
-#if defined(CONFIG_MCHP_GPSPI) && defined(CHIP_FAMILY_MEC152X)
-#error "FORCED BUILD ERROR: MEC152X does not implement GPSPI!"
-#endif
-
-static const struct dma_option spi_rx_option[] = {
-	{
-		MCHP_DMAC_QMSPI0_RX,
-		(void *)(MCHP_QMSPI0_RX_FIFO_ADDR),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-#if CONFIG_MCHP_GPSPI & 0x01
-	{
-		MCHP_DMAC_SPI0_RX,
-		(void *)&MCHP_SPI_RD(0),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#endif
-#if CONFIG_MCHP_GPSPI & 0x02
-	{
-		MCHP_DMAC_SPI1_RX,
-		(void *)&MCHP_SPI_RD(1),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#endif
-#endif
-};
-
-static const struct dma_option spi_tx_option[] = {
-	{
-		MCHP_DMAC_QMSPI0_TX,
-		(void *)(MCHP_QMSPI0_TX_FIFO_ADDR),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-#if CONFIG_MCHP_GPSPI & 0x01
-	{
-		MCHP_DMAC_SPI0_TX,
-		(void *)&MCHP_SPI_TD(0),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#endif
-#if CONFIG_MCHP_GPSPI & 0x02
-	{
-		MCHP_DMAC_SPI1_TX,
-		(void *)&MCHP_SPI_TD(1),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#endif
-#endif
-};
-
-/* only regular image needs mutex, LFW does not have scheduling */
-#ifndef LFW
-static struct mutex spi_mutex[ARRAY_SIZE(spi_rx_option)];
-
-/*
- * Acquire mutex for specified SPI controller/port.
- * Note if mutex is owned by another task this routine
- * will block until mutex is released.
- */
-static void spi_mutex_lock(uint8_t hw_port)
-{
-	uint32_t n;
-
-	n = 0;
-#ifdef CONFIG_MCHP_GPSPI
-	if (hw_port & 0xF0) {
-#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03
-		n = (hw_port & 0x0F) + 1;
-#else
-		n = 1;
-#endif
-	}
-#endif
-	mutex_lock(&spi_mutex[n]);
-}
-
-/*
- * Release mutex for specified SPI controller/port.
- */
-static void spi_mutex_unlock(uint8_t hw_port)
-{
-	uint32_t n;
-
-	n = 0;
-#ifdef CONFIG_MCHP_GPSPI
-	if (hw_port & 0xF0) {
-#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03
-		n = (hw_port & 0x0F) + 1;
-#else
-		n = 1;
-#endif
-	}
-#endif
-	mutex_unlock(&spi_mutex[n]);
-}
-#endif /* #ifndef LFW */
-
-/*
- * Public SPI interface
- */
-
-const void *spi_dma_option(const struct spi_device_t *spi_device,
-				int is_tx)
-{
-	uint32_t n;
-
-	if (spi_device == NULL)
-		return NULL;
-
-	n = 0;
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-	if (spi_device->port & 0xF0) {
-#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03
-		n = (spi_device->port & 0x0F) + 1;
-#else
-		n = 1;
-#endif
-	}
-#endif
-
-	if (is_tx)
-		return &spi_tx_option[n];
-	else
-		return &spi_rx_option[n];
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
-{
-	int rc;
-
-	if (spi_device == NULL)
-		return EC_ERROR_INVAL;
-
-	switch (spi_device->port) {
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-	case GPSPI0_PORT:
-	case GPSPI1_PORT:
-		rc = gpspi_transaction_async(spi_device, txdata,
-				txlen, rxdata, rxlen);
-		break;
-#endif
-	case QMSPI0_PORT:
-		rc = qmspi_transaction_async(spi_device, txdata,
-				txlen, rxdata, rxlen);
-		break;
-	default:
-		rc = EC_ERROR_INVAL;
-	}
-
-	return rc;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int rc;
-
-	if (spi_device == NULL)
-		return EC_ERROR_INVAL;
-
-	switch (spi_device->port) {
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-	case GPSPI0_PORT:
-	case GPSPI1_PORT:
-		rc = gpspi_transaction_flush(spi_device);
-		break;
-#endif
-	case QMSPI0_PORT:
-		rc = qmspi_transaction_flush(spi_device);
-		break;
-	default:
-		rc = EC_ERROR_INVAL;
-	}
-
-	return rc;
-}
-
-/* Wait for async response received but do not de-assert chip select */
-int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	int rc;
-
-	if (spi_device == NULL)
-		return EC_ERROR_INVAL;
-
-	switch (spi_device->port) {
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-#ifndef LFW
-	case GPSPI0_PORT:
-	case GPSPI1_PORT:
-		rc = gpspi_transaction_wait(spi_device);
-		break;
-#endif
-#endif
-	case QMSPI0_PORT:
-		rc = qmspi_transaction_wait(spi_device);
-		break;
-	default:
-		rc = EC_ERROR_INVAL;
-	}
-
-	return rc;
-}
-
-/*
- * called from common/spi_flash.c
- * For tranfers reading less than the size of QMSPI RX FIFO call
- * a routine where reads use FIFO only no DMA.
- * GP-SPI only has a one byte RX FIFO but small data transfers will be OK
- * without the overhead of DMA setup.
- */
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int rc;
-
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-#ifndef LFW
-	spi_mutex_lock(spi_device->port);
-#endif
-
-	rc = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	if (rc == EC_SUCCESS)
-		rc = spi_transaction_flush(spi_device);
-
-#ifndef LFW
-	spi_mutex_unlock(spi_device->port);
-#endif
-
-	return rc;
-}
-
-/**
- * Enable SPI port and associated controller
- *
- * @param spi_device SPI device
- * @param enable
- * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized
- * @note called from common/spi_flash.c
- *
- * spi_device->port is defined as
- * bits[3:0] = controller instance
- * bits[7:4] = controller family 0 = QMSPI, 1 = GPSPI
- */
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	int rc;
-	uint8_t hw_port = spi_device->port;
-	rc = EC_ERROR_INVAL;
-
-	if ((hw_port & 0xF0) == QMSPI_CLASS)
-		rc = qmspi_enable(hw_port, enable);
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-	if ((hw_port & 0xF0) == GPSPI_CLASS)
-		rc = gpspi_enable(hw_port, enable);
-#endif
-	return rc;
-}
diff --git a/chip/mchp/spi_chip.h b/chip/mchp/spi_chip.h
deleted file mode 100644
index 75973e4a78..0000000000
--- a/chip/mchp/spi_chip.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MCHP MEC processor
- */
-/** @file qmpis_chip.h
- *MCHP MEC Quad SPI Master
- */
-/** @defgroup MCHP MEC qmspi
- */
-
-#ifndef _SPI_CHIP_H
-#define _SPI_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-/* struct spi_device_t */
-#include "spi.h"
-
-#define SPI_DMA_OPTION_RD	0
-#define SPI_DMA_OPTION_WR	1
-
-/*
- * bits[3:0] = controller instance
- * bits[7:4] = controller family
- * 0 = QMSPI, 1 = GPSPI
- */
-#define QMSPI0_PORT	0x00
-#define GPSPI0_PORT	0x10
-#define GPSPI1_PORT	0x11
-
-
-#define QMSPI_CLASS0	0
-#define GPSPI_CLASS0	1
-
-#define QMSPI_CLASS	(0 << 4)
-#define GPSPI_CLASS	BIT(4)
-
-#define QMSPI_CTRL0	0
-#define GPSPI_CTRL0	0
-#define GPSPI_CTRL1	1
-
-/*
- * Encode zero based controller class and instance values
- * in port value of spi_device_t.
- */
-#define SPI_CTRL_ID(c, i) (((c & 0xf) << 4) + (i & 0xf))
-
-/*
- * helper to return pointer to QMSPI or GPSPI struct dma_option
- */
-const void *spi_dma_option(const struct spi_device_t *spi_device,
-				int is_tx);
-
-#endif /* #ifndef _QMSPI_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/system.c b/chip/mchp/system.c
deleted file mode 100644
index d67314d716..0000000000
--- a/chip/mchp/system.c
+++ /dev/null
@@ -1,591 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : MCHP hardware specific implementation */
-
-#include <stdnoreturn.h>
-
-#include "common.h" /* includes config.h and board.h */
-#include "clock.h"
-#include "clock_chip.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lpc_chip.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "tfdp_chip.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-/* Index values for hibernate data registers (RAM backed by VBAT) */
-enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD = 0,    /* General-purpose scratch pad */
-	HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
-	HIBDATA_INDEX_PD0,		/* USB-PD0 saved port state */
-	HIBDATA_INDEX_PD1,		/* USB-PD1 saved port state */
-	HIBDATA_INDEX_PD2,		/* USB-PD2 saved port state */
-};
-
-/*
- * Voltage rail configuration
- * MEC172x VTR1 is 3.3V only, VTR2 is auto-detected 3.3 or 1.8V, and
- * VTR3 is always 1.8V.
- * MEC170x and MEC152x require manual selection of VTR3 for 1.8 or 3.3V.
- * The eSPI pins are on VTR3 and require 1.8V
- */
-#ifdef CHIP_FAMILY_MEC172X
-static void vtr3_voltage_select(int use18v)
-{
-	(void) use18v;
-}
-#else
-static void vtr3_voltage_select(int use18v)
-{
-	if (use18v)
-		MCHP_EC_GPIO_BANK_PWR |= MCHP_EC_GPIO_BANK_PWR_VTR3_18;
-	else
-		MCHP_EC_GPIO_BANK_PWR &= ~(MCHP_EC_GPIO_BANK_PWR_VTR3_18);
-}
-#endif
-
-
-/*
- * The current logic will set EC_RESET_FLAG_RESET_PIN flag
- * even if the reset was caused by WDT. MEC170x/MEC152x HW RESET_SYS
- * status goes active for any of the following:
- *	RESET_VTR: power rail change
- *	WDT Event: WDT timed out
- *	FW triggered chip reset: SYSRESETREQ or PCR sys reset bit
- * The code does check WDT status in the VBAT PFR register.
- * Is it correct to report both EC_RESET_FLAG_RESET_PIN and
- * EC_RESET_FLAG_WATCHDOG on a WDT only reset?
- */
-static void check_reset_cause(void)
-{
-	uint32_t status = MCHP_VBAT_STS;
-	uint32_t flags = 0;
-	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS &
-				(MCHP_PWR_RST_STS_SYS |
-				MCHP_PWR_RST_STS_VBAT);
-
-	/* Clear the reset causes now that we've read them */
-	MCHP_VBAT_STS |= status;
-	MCHP_PCR_PWR_RST_STS |= rst_sts;
-
-	/*
-	 * BIT[6] indicates RESET_SYS asserted.
-	 * RESET_SYS will assert on VTR reset, WDT reset, or
-	 * firmware triggering a reset using Cortex-M4 SYSRESETREQ
-	 * or MCHP PCR system reset register.
-	 */
-	if (rst_sts & MCHP_PWR_RST_STS_SYS)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-
-	flags |= chip_read_reset_flags();
-	chip_save_reset_flags(0);
-
-	if ((status & MCHP_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
-					    EC_RESET_FLAG_HARD |
-					    EC_RESET_FLAG_HIBERNATE)))
-		flags |= EC_RESET_FLAG_WATCHDOG;
-
-	system_set_reset_flags(flags);
-}
-
-int system_is_reboot_warm(void)
-{
-	uint32_t reset_flags;
-	/*
-	 * Check reset cause here,
-	 * gpio_pre_init is executed faster than system_pre_init
-	 */
-	check_reset_cause();
-	reset_flags = system_get_reset_flags();
-
-	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-		(reset_flags & EC_RESET_FLAG_POWER_ON) ||
-		(reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-		(reset_flags & EC_RESET_FLAG_HARD) ||
-		(reset_flags & EC_RESET_FLAG_SOFT))
-		return 0;
-	else
-		return 1;
-}
-
-/*
- * Sleep unused blocks to reduce power.
- * Drivers/modules will clear PCR sleep enables for their blocks.
- * Keep sleep enables cleared for required blocks:
- * ECIA, PMC, CPU, ECS and optionally JTAG.
- * SLEEP_ALL feature will set these upon sleep entry.
- * Based on CONFIG_CHIPSET_DEBUG enable or disable ARM SWD
- * 2-pin JTAG mode.
- */
-static void chip_periph_sleep_control(void)
-{
-	uint32_t d;
-
-	d = MCHP_PCR_SLP_EN0_SLEEP;
-
-	if (IS_ENABLED(CONFIG_CHIPSET_DEBUG)) {
-		d &= ~(MCHP_PCR_SLP_EN0_JTAG);
-		MCHP_EC_JTAG_EN = MCHP_JTAG_MODE_SWD | MCHP_JTAG_ENABLE;
-	} else
-		MCHP_EC_JTAG_EN &= ~(MCHP_JTAG_ENABLE);
-
-	MCHP_PCR_SLP_EN0 = d;
-	MCHP_PCR_SLP_EN1 = MCHP_PCR_SLP_EN1_UNUSED_BLOCKS;
-	MCHP_PCR_SLP_EN2 = MCHP_PCR_SLP_EN2_SLEEP;
-	MCHP_PCR_SLP_EN3 = MCHP_PCR_SLP_EN3_SLEEP;
-	MCHP_PCR_SLP_EN4 = MCHP_PCR_SLP_EN4_SLEEP;
-}
-
-#ifdef CONFIG_CHIP_PRE_INIT
-void chip_pre_init(void)
-{
-	chip_periph_sleep_control();
-
-	if (IS_ENABLED(CONFIG_MCHP_TFDP)) {
-		/* MCHP Enable TFDP for fast debug messages */
-		tfdp_power(1);
-		tfdp_enable(1, 1);
-		CPRINTS("chip_pre_init: Image type = 0x%02x",
-			MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX));
-	}
-}
-#endif
-
-void system_pre_init(void)
-{
-	/*
-	 * Make sure AHB Error capture is enabled.
-	 * Signals bus fault to Cortex-M4 core if an address presented
-	 * to AHB is not claimed by any HW block.
-	 */
-	MCHP_EC_AHB_ERR = 0;	/* write any value to clear */
-	MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */
-
-	/* Manual voltage selection only required for MEC170x and MEC152x */
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI))
-		vtr3_voltage_select(1);
-	else
-		vtr3_voltage_select(0);
-
-	if (!IS_ENABLED(CONFIG_CHIP_PRE_INIT))
-		chip_periph_sleep_control();
-
-	/* Enable direct NVIC */
-	MCHP_EC_INT_CTRL |= 1;
-
-	/* Disable ARM TRACE debug port */
-	MCHP_EC_TRACE_EN &= ~1;
-
-	/*
-	 * Enable aggregated only interrupt GIRQ's
-	 * Make sure direct mode interrupt sources aggregated outputs
-	 * are not enabled.
-	 * Aggregated only GIRQ's 8,9,10,11,12,22,24,25,26
-	 * Direct GIRQ's = 13,14,15,16,17,18,19,21,23
-	 * These bits only need to be touched again on RESET_SYS.
-	 * NOTE: GIRQ22 wake for AHB peripherals not processor.
-	 */
-	MCHP_INT_BLK_DIS = 0xfffffffful;
-	MCHP_INT_BLK_EN = MCHP_INT_AGGR_ONLY_BITMAP;
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return MCHP_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	MCHP_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = flags;
-}
-
-noreturn void _system_reset(int flags, int wake_from_hibernate)
-{
-	uint32_t save_flags = 0;
-
-	/* DEBUG */
-	CPRINTS("MEC system reset: flag = 0x%08x wake = %d", flags,
-		wake_from_hibernate);
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	if (wake_from_hibernate)
-		save_flags |= EC_RESET_FLAG_HIBERNATE;
-	else if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-	else
-		save_flags |= EC_RESET_FLAG_SOFT;
-
-	chip_save_reset_flags(save_flags);
-
-	/*
-	 * Trigger chip reset
-	 */
-	if (!IS_ENABLED(CONFIG_DEBUG_BRINGUP))
-		MCHP_PCR_SYS_RST |= MCHP_PCR_SYS_SOFT_RESET;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-void system_reset(int flags)
-{
-	_system_reset(flags, 0);
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "mchp";
-}
-
-#ifdef CHIP_VARIANT_MEC1701
-/*
- * MEC1701H Chip ID = 0x2D
- *              Rev = 0x82
- */
-const char *system_get_chip_name(void)
-{
-	switch (MCHP_CHIP_DEV_ID) {
-	case 0x2D:
-		return "mec1701";
-	default:
-		return "unknown";
-	}
-}
-#endif
-
-#ifdef CHIP_FAMILY_MEC152X
-/*
- * MEC152x family implements chip ID as a 32-bit
- * register where:
- * b[31:16] = 16-bit Device ID
- * b[15:8] = 8-bit Sub ID
- * b[7:0] = Revision
- *
- * MEC1521-128 WFBGA 0023_33_xxh
- * MEC1521-144 WFBGA 0023_34_xxh
- * MEC1523-144 WFBGA 0023_B4_xxh
- * MEC1527-144 WFBGA 0023_74_xxh
- * MEC1527-128 WFBGA 0023_73_xxh
- */
-const char *system_get_chip_name(void)
-{
-	switch (MCHP_CHIP_DEVRID32 & ~(MCHP_CHIP_REV_MASK)) {
-	case 0x00201400: /* 144 pin rev A? */
-		return "mec1503_revA";
-	case 0x00203400: /* 144 pin */
-		return "mec1501";
-	case 0x00207400: /* 144 pin */
-		return "mec1507";
-	case 0x00208400: /* 144 pin */
-		return "mec1503";
-	case 0x00233300: /* 128 pin */
-	case 0x00233400: /* 144 pin */
-		return "mec1521";
-	case 0x0023B400: /* 144 pin */
-		return "mec1523";
-	case 0x00237300: /* 128 pin */
-	case 0x00237400: /* 144 pin */
-		return "mec1527";
-	default:
-		return "unknown";
-	}
-}
-#endif
-
-#ifdef CHIP_FAMILY_MEC172X
-/*
- * MEC172x family implements chip ID as a 32-bit
- * register where:
- * b[31:16] = 16-bit Device ID
- * b[15:8] = 8-bit Sub ID
- * b[7:0] = Revision
- *
- * MEC1723N-B0-I/SZ 144 pin: 0x0022_34_xx
- * MEC1727N-B0-I/SZ 144 pin: 0x0022_74_xx
- * MEC1721N-B0-I/LJ 176 pin: 0x0022_27_xx
- * MEC1723N-B0-I/LJ 176 pin: 0x0022_37_xx
- * MEC1727N-B0-I/LJ 176 pin: 0x0022_77_xx
- */
-const char *system_get_chip_name(void)
-{
-	switch (MCHP_CHIP_DEVRID32 & ~(MCHP_CHIP_REV_MASK)) {
-	case 0x00223400:
-		return "MEC1723NSZ";
-	case 0x00227400:
-		return "MEC1727NSZ";
-	case 0x00222700:
-		return "MEC1721NLJ";
-	case 0x00223700:
-		return "MEC1723NLJ";
-	case 0x00227700:
-		return "MEC1727NLJ";
-	default:
-		return "unknown";
-	}
-}
-#endif
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char buf[3];
-	uint8_t rev = MCHP_CHIP_DEV_REV;
-
-	buf[0] = to_hex(rev / 16);
-	buf[1] = to_hex(rev & 0xf);
-	buf[2] = '\0';
-	return buf;
-}
-
-static int bbram_idx_lookup(enum system_bbram_idx idx)
-{
-	switch (idx) {
-	case SYSTEM_BBRAM_IDX_PD0:
-		return HIBDATA_INDEX_PD0;
-	case SYSTEM_BBRAM_IDX_PD1:
-		return HIBDATA_INDEX_PD1;
-	case SYSTEM_BBRAM_IDX_PD2:
-		return HIBDATA_INDEX_PD2;
-	default:
-		return 1;
-	}
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	*value = MCHP_VBAT_RAM(hibdata);
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	MCHP_VBAT_RAM(hibdata) = value;
-	return EC_SUCCESS;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	MCHP_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD) = value;
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = MCHP_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-/*
- * Local function to disable clocks in the chip's host interface
- * so the chip can enter deep sleep. Only MEC170X has LPC.
- * MEC152x and MEC172x only include eSPI and SPI host interfaces.
- * NOTE: we do it this way because the LPC registers are only
- * defined for MEC170x and the IS_ENABLED() macro causes the
- * compiler to evaluate both true and false code paths.
- */
-#if defined(CONFIG_HOSTCMD_ESPI)
-static void disable_host_ifc_clocks(void)
-{
-	MCHP_ESPI_ACTIVATE &= ~0x01;
-}
-#else
-static void disable_host_ifc_clocks(void)
-{
-	#ifdef CHIP_FAMILY_MEC170X
-	MCHP_LPC_ACT &= ~0x1;
-	#endif
-}
-#endif
-
-
-/*
- * Called when hibernation timer is not used in deep sleep.
- * Switch 32 KHz clock logic from external 32KHz input to
- * internal silicon OSC.
- * NOTE: MEC172x auto-switches from external source to silicon
- * oscillator.
- */
-#ifdef CHIP_FAMILY_MEC172X
-static void switch_32k_pin2sil(void) {}
-#else
-static void switch_32k_pin2sil(void)
-{
-	MCHP_VBAT_CE &= ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN);
-}
-#endif
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-
-	if (IS_ENABLED(CONFIG_HOSTCMD_PD)) {
-		/* Inform the PD MCU that we are going to hibernate. */
-		host_command_pd_request_hibernate();
-		/* Wait to ensure exchange with PD before hibernating. */
-		msleep(100);
-	}
-
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* Disable interrupts */
-	interrupt_disable();
-	for (i = 0; i < MCHP_IRQ_MAX; ++i) {
-		task_disable_irq(i);
-		task_clear_pending_irq(i);
-	}
-
-	for (i = MCHP_INT_GIRQ_FIRST; i <= MCHP_INT_GIRQ_LAST; ++i) {
-		MCHP_INT_DISABLE(i) = 0xffffffff;
-		MCHP_INT_SOURCE(i)  = 0xffffffff;
-	}
-
-	/* Disable UART */
-	MCHP_UART_ACT(0) &= ~0x1;
-
-	disable_host_ifc_clocks();
-
-	/* Disable JTAG */
-	MCHP_EC_JTAG_EN &= ~1;
-
-	/* Stop watchdog */
-	MCHP_WDG_CTL &= ~(MCHP_WDT_CTL_ENABLE);
-
-	/* Stop timers */
-	MCHP_TMR32_CTL(0) &= ~1;
-	MCHP_TMR32_CTL(1) &= ~1;
-	for (i = 0; i < MCHP_TMR16_INSTANCES; i++)
-		MCHP_TMR16_CTL(i) &= ~1;
-
-	/* Power down ADC */
-	/*
-	 * If ADC is in middle of acquisition it will continue until finished
-	 */
-	MCHP_ADC_CTRL &= ~1;
-
-	/* Disable blocks */
-	MCHP_PCR_SLOW_CLK_CTL &= ~(MCHP_PCR_SLOW_CLK_CTL_MASK);
-
-	/* Setup GPIOs for hibernate */
-	if (board_hibernate_late)
-		board_hibernate_late();
-
-	if (hibernate_wake_pins_used > 0) {
-		for (i = 0; i < hibernate_wake_pins_used; ++i) {
-			const enum gpio_signal pin = hibernate_wake_pins[i];
-
-			gpio_reset(pin);
-			gpio_enable_interrupt(pin);
-		}
-
-		interrupt_enable();
-		task_enable_irq(MCHP_IRQ_GIRQ8);
-		task_enable_irq(MCHP_IRQ_GIRQ9);
-		task_enable_irq(MCHP_IRQ_GIRQ10);
-		task_enable_irq(MCHP_IRQ_GIRQ11);
-		task_enable_irq(MCHP_IRQ_GIRQ12);
-		task_enable_irq(MCHP_IRQ_GIRQ26);
-	}
-
-	if (seconds || microseconds) {
-		htimer_init();
-		system_set_htimer_alarm(seconds, microseconds);
-		interrupt_enable();
-	} else
-		switch_32k_pin2sil();
-
-	/*
-	 * Set sleep state
-	 * arm sleep state to trigger on next WFI
-	 */
-	CPU_SCB_SYSCTRL |= 0x4;
-	MCHP_PCR_SYS_SLP_CTL = MCHP_PCR_SYS_SLP_HEAVY;
-	MCHP_PCR_SYS_SLP_CTL = MCHP_PCR_SYS_SLP_ALL;
-
-	asm("dsb");
-	asm("wfi");
-	asm("isb");
-	asm("nop");
-
-	/* Use fastest clock to speed through wake-up */
-	MCHP_PCR_PROC_CLK_CTL = MCHP_PCR_CLK_CTL_FASTEST;
-
-	/* Reboot */
-	_system_reset(0, 1);
-
-	/* We should never get here. */
-	while (1)
-		;
-}
-
-void htimer_interrupt(void)
-{
-	/* Time to wake up */
-}
-DECLARE_IRQ(MCHP_IRQ_HTIMER0, htimer_interrupt, 1);
-
-enum ec_image system_get_shrspi_image_copy(void)
-{
-	return MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX);
-}
-
-uint32_t system_get_lfw_address(void)
-{
-	uint32_t * const lfw_vector =
-		(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
-
-	return *(lfw_vector + 1);
-}
-
-void system_set_image_copy(enum ec_image copy)
-{
-	MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ?
-				EC_IMAGE_RW : EC_IMAGE_RO;
-}
-
diff --git a/chip/mchp/tfdp.c b/chip/mchp/tfdp.c
deleted file mode 100644
index b4368b46a8..0000000000
--- a/chip/mchp/tfdp.c
+++ /dev/null
@@ -1,499 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/** @file tfdp.c
- *MCHP Trace FIFO Data Port hardware access
- */
-/** @defgroup MCHP Peripherals TFDP
- *  @{
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "tfdp_chip.h"
-
-#ifdef CONFIG_MCHP_TFDP
-
-
-static uint32_t get_disable_intr(void)
-{
-	uint32_t m;
-
-	__asm__ __volatile__ ("mrs %0, primask;cpsid i" : "=r" (m));
-
-	return m;
-}
-
-static void restore_intr(uint32_t m)
-{
-	if (!m)
-		__asm__ __volatile__ ("cpsie i" : : : "memory");
-}
-
-
-/**
- * tfdp_power - Gate clocks On/Off to TFDP block when idle
- *
- * @param pwr_on (0=Gate clocks when idle), (1=Do not gate
- *                 clocks when idle)
- */
-void tfdp_power(uint8_t pwr_on)
-{
-	if (pwr_on)
-		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_TFDP);
-	else
-		MCHP_PCR_SLP_EN_DEV(MCHP_PCR_TFDP);
-}
-
-
-/**
- * tfdp_enable - Init Trace FIFO Data Port
- * @param uint8_t non-zero=enable TFDP, false=disable TFDP
- * @param uint8_t non-zero=change TFDP pin configuration.
- * If TFDP is enabled then GPIO170/171 set to Alt. Func. 1
- * Else GPIO170/171 set to GPIO input, internal pull-up enabled.
- * @note -
- */
-#define MCHP_TFDP_DATA	REG8(MCHP_TFDP_BASE + 0x00)
-#define MCHP_TFDP_CTRL	REG8(MCHP_TFDP_BASE + 0x04)
-
-void tfdp_enable(uint8_t en, uint8_t pin_cfg)
-{
-	if (en) {
-		MCHP_TFDP_CTRL = 0x01u;
-		if (pin_cfg)
-			gpio_config_module(MODULE_TFDP, 1);
-	} else {
-		MCHP_TFDP_CTRL = 0x00u;
-		if (pin_cfg)
-			gpio_config_module(MODULE_TFDP, 0);
-	}
-} /* end tfdp_enable() */
-
-
-/**
- * TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first
- * over TFDP.
- *
- * @param nbr 16-bit trace number
- * @param b unused
- *
- * @return uint8_t always TRUE
- * @note Function implements critical section.
- * Uses tool kit __disable_irq()/__enable_irq() pair which may use
- * priviledged Cortex-Mx instructions.
- */
-void TFDPTrace0(uint16_t nbr)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- * TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first
- * and 16-bit data lsb first over TFDP.
- *
- * @param nbr 16-bit trace number
- * @param b unused
- * @param uint32_t p1 16-bit data1 in b[15:0]
- *
- * @return uint8_t always TRUE
- * @note Function implements critical section.
- * Uses tool kit __disable_irq()/__enable_irq() pair which may use
- * priviledged Cortex-Mx instructions.
- */
-void TFDPTrace1(uint16_t nbr, uint32_t p1)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- * TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first
- * and two 16-bit data parameters lsb first over TFDP.
- *
- * @param nbr trace number
- * @param b unused
- * @param uint32_t p1 16-bit data1 in b[15:0]
- * @param uint32_t p2 16-bit data2 in b[15:0]
- *
- * @return uint8_t always TRUE
- * @note Uses tool kit functions to save/disable/restore
- *       interrupts for critical section. These may use
- *       priviledged instructions.
- */
-void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- * TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first
- * and three 16-bit data parameters lsb first over TFDP.
- *
- * @param nbr trace number
- * @param b unused
- * @param uint32_t p1 16-bit data1 in b[15:0]
- * @param uint32_t p2 16-bit data2 in b[15:0]
- * @param uint32_t p3 16-bit data3 in b[15:0]
- *
- * @return uint8_t always TRUE
- * @note Uses tool kit functions to save/disable/restore
- *       interrupts for critical section. These may use
- *       priviledged instructions.
- */
-void TFDPTrace3(uint16_t nbr, uint32_t p1,
-		uint32_t p2, uint32_t p3)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p3;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- * TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first
- * and four 16-bit data parameters lsb first over TFDP.
- *
- * @param nbr trace number
- * @param b unused
- * @param uint32_t p1 16-bit data1 in b[15:0]
- * @param uint32_t p2 16-bit data2 in b[15:0]
- * @param uint32_t p3 16-bit data3 in b[15:0]
- * @param uint32_t p4 16-bit data4 in b[15:0]
- *
- * @return uint8_t always TRUE
- * @note Uses tool kit functions to save/disable/restore
- *       interrupts for critical section. These may use
- *       priviledged instructions.
- */
-void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p3;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p4;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p4 >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- *  TFDPTrace11 - Transmit one 32-bit data item over TFDP
- *
- *  @param nbr trace number
- *  @param b unused
- *  @param uint32_t p1 32-bit data to be transmitted
- *
- */
-void TFDPTrace11(uint16_t nbr, uint32_t p1)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 24);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- *  TFDPTrace12 - Transmit two 32-bit data items over TFDP
- *
- *  @param nbr trace number
- *  @param b unused
- *  @param uint32_t p1 32-bit data1 to be transmitted
- *  @param uint32_t p2 32-bit data2 to be transmitted
- *
- */
-void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 24);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-/**
- *  TFDPTrace13 - Transmit three 32-bit data items over TFDP
- *
- *  @param nbr trace number
- *  @param b unused
- *  @param uint32_t p1 32-bit data1 to be transmitted
- *  @param uint32_t p2 32-bit data2 to be transmitted
- *  @param uint32_t p3 32-bit data3 to be transmitted
- *
- */
-void TFDPTrace13(uint16_t nbr, uint32_t p1,
-		 uint32_t p2, uint32_t p3)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p3;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 24);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-/**
- *  TFDPTrace14 - Transmit four 32-bit data items over TFDP
- *
- *  @param nbr trace number
- *  @param b unused
- *  @param uint32_t p1 32-bit data1 to be transmitted
- *  @param uint32_t p2 32-bit data2 to be transmitted
- *  @param uint32_t p3 32-bit data3 to be transmitted
- *  @param uint32_t p4 32-bit data4 to be transmitted
- */
-void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p3;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p4;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p4 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p4 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p4 >> 24);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-#endif /* #ifdef CONFIG_MCHP_TFDP */
-
-
-/* end tfdp.c */
-/**   @}
- */
diff --git a/chip/mchp/tfdp_chip.h b/chip/mchp/tfdp_chip.h
deleted file mode 100644
index 64d4d0b77e..0000000000
--- a/chip/mchp/tfdp_chip.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/** @file tfdp_chip.h
- *MCHP MEC TFDP Peripheral Library API
- */
-/** @defgroup MCHP MEC Peripherals Trace
- */
-
-#ifndef _TFDP_CHIP_H
-#define _TFDP_CHIP_H
-
-#include <stdint.h>
-
-
-#ifdef CONFIG_MCHP_TFDP
-
-#undef TRACE0
-#undef TRACE1
-#undef TRACE2
-#undef TRACE3
-#undef TRACE4
-#undef TRACE11
-#undef TRACE12
-#undef TRACE13
-#undef TRACE14
-#undef trace0
-#undef trace1
-#undef trace2
-#undef trace3
-#undef trace4
-#undef trace11
-#undef trace12
-#undef trace13
-#undef trace14
-
-#define MCHP_TFDP_BASE_ADDR	(0x40008c00ul)
-
-#define TFDP_FRAME_START   (0xFD)
-
-#define TFDP_POWER_ON   (1u)
-#define TFDP_POWER_OFF  (0u)
-
-#define TFDP_ENABLE         (1u)
-#define TFDP_DISABLE        (0u)
-#define TFDP_CFG_PINS       (1u)
-#define TFDP_NO_CFG_PINS    (0u)
-
-#define  MCHP_TRACE_MASK_IRQ
-
-#define TFDP_DELAY()
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void tfdp_power(uint8_t pwr_on);
-void tfdp_enable(uint8_t en, uint8_t pin_cfg);
-void TFDPTrace0(uint16_t nbr);
-void TFDPTrace1(uint16_t nbr, uint32_t p1);
-void TFDPTrace2(uint16_t nbr, uint32_t p1,
-		uint32_t p2);
-void TFDPTrace3(uint16_t nbr, uint32_t p1,
-		uint32_t p2, uint32_t p3);
-void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
-		uint32_t p3, uint32_t p4);
-void TFDPTrace11(uint16_t nbr, uint32_t p1);
-void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2);
-void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3);
-void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4);
-
-#ifdef __cplusplus
-}
-#endif
-
-#define TRACE0(nbr, cat, b, str) TFDPTrace0(nbr)
-#define TRACE1(nbr, cat, b, str, p1) TFDPTrace1(nbr, p1)
-#define TRACE2(nbr, cat, b, str, p1, p2) TFDPTrace2(nbr, p1, p2)
-#define TRACE3(nbr, cat, b, str, p1, p2, p3) TFDPTrace3(nbr, p1, p2, p3)
-#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) TFDPTrace4(nbr, p1, p2, \
-	p3, p4)
-#define TRACE11(nbr, cat, b, str, p1) TFDPTrace11(nbr, p1)
-#define TRACE12(nbr, cat, b, str, p1, p2) TFDPTrace12(nbr, p1, p2)
-#define TRACE13(nbr, cat, b, str, p1, p2, p3) TFDPTrace13(nbr, p1, p2, p3)
-#define TRACE14(nbr, cat, b, str, p1, p2, p3, p4) \
-	TFDPTrace14(nbr, p1, p2, p3, p4)
-
-
-#else /* #ifdef MCHP_TRACE */
-
-/* !!! To prevent compiler warnings of unused parameters,
- * when trace is disabled by TRGEN source processing,
- * you can either:
- * 1. Disable compiler's unused parameter warning
- * 2. Change these macros to write parameters to a read-only
- *    register.
- */
-#define tfdp_power(pwr_on)
-#define tfdp_enable(en, pin_cfg)
-#define TRACE0(nbr, cat, b, str)
-#define TRACE1(nbr, cat, b, str, p1)
-#define TRACE2(nbr, cat, b, str, p1, p2)
-#define TRACE3(nbr, cat, b, str, p1, p2, p3)
-#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4)
-#define TRACE11(nbr, cat, b, str, p1)
-#define TRACE12(nbr, cat, b, str, p1, p2)
-#define TRACE13(nbr, cat, b, str, p1, p2, p3)
-#define TRACE14(nbr, cat, b, str, p1, p2, p3, p4)
-
-#endif /* #ifdef CONFIG_MCHP_TFDP */
-
-/*
- * Always define lower case traceN(...) as blank (fully removed)
- */
-#define trace0(nbr, cat, b, str)
-#define trace1(nbr, cat, b, str, p1)
-#define trace2(nbr, cat, b, str, p1, p2)
-#define trace3(nbr, cat, b, str, p1, p2, p3)
-#define trace4(nbr, cat, b, str, p1, p2, p3, p4)
-#define trace11(nbr, cat, b, str, p1)
-#define trace12(nbr, cat, b, str, p1, p2)
-#define trace13(nbr, cat, b, str, p1, p2, p3)
-#define trace14(nbr, cat, b, str, p1, p2, p3, p4)
-
-#endif /* #ifndef _TFDP_CHIP_H */
-/* end tfdp_chip.h */
-/**   @}
- */
diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c
deleted file mode 100644
index 56c99646a4..0000000000
--- a/chip/mchp/uart.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for MCHP MEC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "lpc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-#define TX_FIFO_SIZE	16
-
-BUILD_ASSERT((CONFIG_UART_CONSOLE >= 0) &&
-	     (CONFIG_UART_CONSOLE < MCHP_UART_INSTANCES));
-
-#if CONFIG_UART_CONSOLE == 2
-
-#define UART_IRQ		MCHP_IRQ_UART2
-#define UART_IRQ_BIT		MCHP_UART2_GIRQ_BIT
-#define UART_PCR		MCHP_PCR_UART2
-#define GPIO_UART_RX		GPIO_UART2_RX
-/* MEC152x only. UART2 RX Pin = GPIO 0145 GIRQ08 bit[5] */
-#define UART_RX_PIN_GIRQ	8
-#define UART_RX_PIN_BIT		BIT(5)
-
-#elif CONFIG_UART_CONSOLE == 1
-
-#define UART_IRQ		MCHP_IRQ_UART1
-#define UART_IRQ_BIT		MCHP_UART1_GIRQ_BIT
-#define UART_PCR		MCHP_PCR_UART1
-#define GPIO_UART_RX		GPIO_UART1_RX
-/* MEC152x and MEC170x UART1 RX Pin = GPIO 0171. GIRQ08 bit[25] */
-#define UART_RX_PIN_GIRQ	8
-#define UART_RX_PIN_BIT		BIT(25)
-
-#else
-
-#define UART_IRQ		MCHP_IRQ_UART0
-#define UART_IRQ_BIT		MCHP_UART0_GIRQ_BIT
-#define UART_PCR		MCHP_PCR_UART0
-#define GPIO_UART_RX		GPIO_UART0_RX
-/* MEC152x and MEC170x UART0 RX Pin = GPIO 0105. GIRQ09 bit[5] */
-#define UART_RX_PIN_GIRQ	9
-#define UART_RX_PIN_BIT		BIT(5)
-
-#endif /* CONFIG_UART_CONSOLE == 2 */
-
-static int init_done;
-static int tx_fifo_used;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (MCHP_UART_IER(CONFIG_UART_CONSOLE) & BIT(1))
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	MCHP_UART_IER(CONFIG_UART_CONSOLE) |= BIT(1);
-	task_trigger_irq(UART_IRQ);
-}
-
-void uart_tx_stop(void)
-{
-	MCHP_UART_IER(CONFIG_UART_CONSOLE) &= ~BIT(1);
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/* Wait for transmit FIFO empty */
-	while (!(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * We have no indication of free space in transmit FIFO. To work around
-	 * this, we check transmit FIFO empty bit every 16 characters written.
-	 */
-	return tx_fifo_used != 0 ||
-		(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
-}
-
-int uart_tx_in_progress(void)
-{
-	/* return 0: FIFO is empty, 1: FIFO NOT Empty */
-	return !(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
-}
-
-int uart_rx_available(void)
-{
-	return MCHP_UART_LSR(CONFIG_UART_CONSOLE) & BIT(0);
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE;
-	MCHP_UART_TB(CONFIG_UART_CONSOLE) = c;
-}
-
-int uart_read_char(void)
-{
-	return MCHP_UART_RB(CONFIG_UART_CONSOLE);
-}
-
-static void uart_clear_rx_fifo(int channel)
-{
-	MCHP_UART_FCR(channel) = BIT(0) | BIT(1);
-}
-
-void uart_disable_interrupt(void)
-{
-	task_disable_irq(UART_IRQ);
-}
-
-void uart_enable_interrupt(void)
-{
-	task_enable_irq(UART_IRQ);
-}
-
-/**
- * Interrupt handler for UART.
- * Lower priority below other critical ISR's.
- */
-void uart_ec_interrupt(void)
-{
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	/* Trace statement to provide time marker for UART output? */
-	uart_process_output();
-}
-DECLARE_IRQ(UART_IRQ, uart_ec_interrupt, 2);
-
-void uart_init(void)
-{
-	/* Clear UART PCR sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(UART_PCR);
-
-	/* Set UART to reset on VCC1_RESET instead of nSIO_RESET */
-	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MCHP_UART_PBRG0(CONFIG_UART_CONSOLE) = 1;
-	MCHP_UART_PBRG1(CONFIG_UART_CONSOLE) = 0;
-
-	/* Set DLAB = 0 */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MCHP_UART_FCR(CONFIG_UART_CONSOLE) = BIT(0);
-
-	/* Activate UART */
-	MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
-
-	gpio_config_module(MODULE_UART, 1);
-
-	/*
-	 * Enable interrupts for UART
-	 */
-	uart_clear_rx_fifo(CONFIG_UART_CONSOLE);
-	MCHP_UART_IER(CONFIG_UART_CONSOLE) |= BIT(0);
-	MCHP_UART_MCR(CONFIG_UART_CONSOLE) |= BIT(3);
-
-	MCHP_INT_ENABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
-
-	task_enable_irq(UART_IRQ);
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	/* Disable the UART interrupt. */
-	task_disable_irq(UART_IRQ);  /* NVIC interrupt for UART=13 */
-
-	/*
-	 * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt
-	 * with the flags defined in the gpio.inc file.
-	 */
-	gpio_reset(GPIO_UART_RX);
-
-	/* power-down/deactivate UART */
-	MCHP_UART_ACT(CONFIG_UART_CONSOLE) &= ~BIT(0);
-
-	/* clear interrupt enable for UART */
-	MCHP_INT_DISABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
-
-	/* Clear pending interrupts on UART RX pin */
-	MCHP_INT_SOURCE(UART_RX_PIN_GIRQ) = UART_RX_PIN_BIT;
-
-	/* Enable GPIO interrupts on the UART0 RX pin. */
-	gpio_enable_interrupt(GPIO_UART_RX);
-}
-
-
-void uart_exit_dsleep(void)
-{
-	/*
-	 * If the UART0 RX GPIO interrupt has not fired, then no edge has been
-	 * detected. Disable the GPIO interrupt so that switching the pin over
-	 * to a UART pin doesn't inadvertently cause a GPIO edge interrupt.
-	 * Note: we can't disable this interrupt if it has already fired
-	 * because then the IRQ will not run at all.
-	 */
-	if (!(BIT(5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */
-		gpio_disable_interrupt(GPIO_UART_RX);
-
-	/* Configure UART0 pins for use in UART peripheral. */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Clear pending interrupts on UART peripheral and enable interrupts. */
-	uart_clear_rx_fifo(CONFIG_UART_CONSOLE);
-	MCHP_INT_SOURCE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
-	MCHP_INT_ENABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
-	task_enable_irq(UART_IRQ);
-
-	/* power-up/activate UART0 */
-	MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Activity seen on UART RX pin while UART was disabled for deep sleep.
-	 * The console won't see that character because the UART is disabled,
-	 * so we need to inform the clock module of UART activity ourselves.
-	 */
-	clock_refresh_console_in_use();
-
-	/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py
deleted file mode 100755
index 7908b0bf37..0000000000
--- a/chip/mchp/util/pack_ec.py
+++ /dev/null
@@ -1,536 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# A script to pack EC binary into SPI flash image for MEC17xx
-# Based on MEC170x_ROM_Description.pdf DS00002225C (07-28-17).
-import argparse
-import hashlib
-import os
-import struct
-import subprocess
-import tempfile
-import zlib # CRC32
-
-# MEC1701 has 256KB SRAM from 0xE0000 - 0x120000
-# SRAM is divided into contiguous CODE & DATA
-# CODE at [0xE0000, 0x117FFF] DATA at [0x118000, 0x11FFFF]
-# SPI flash size for board is 512KB
-# Boot-ROM TAG is located at SPI offset 0 (two 4-byte tags)
-#
-
-LFW_SIZE = 0x1000
-LOAD_ADDR = 0x0E0000
-LOAD_ADDR_RW = 0xE1000
-HEADER_SIZE = 0x40
-SPI_CLOCK_LIST = [48, 24, 16, 12]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
-
-def mock_print(*args, **kwargs):
-  pass
-
-debug_print = mock_print
-
-def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
-
-def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return struct.unpack('<I', s)[0]
-
-def GetPayloadFromOffset(payload_file, offset):
-  """Read payload and pad it to 64-byte aligned."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % 64
-  if rem_len:
-    payload += b'\0' * (64 - rem_len)
-  return payload
-
-def GetPayload(payload_file):
-  """Read payload and pad it to 64-byte aligned."""
-  return GetPayloadFromOffset(payload_file, 0)
-
-def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
-
-def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
-
-def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
-
-def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
-
-def BuildHeader(args, payload_len, load_addr, rorofile):
-  # Identifier and header version
-  header = bytearray(b'PHCM\0')
-
-  # byte[5]
-  b = GetSpiClockParameter(args)
-  b |= (1 << 2)
-  header.append(b)
-
-  # byte[6]
-  b = 0
-  header.append(b)
-
-  # byte[7]
-  header.append(GetSpiReadCmdParameter(args))
-
-  # bytes 0x08 - 0x0b
-  header.extend(struct.pack('<I', load_addr))
-  # bytes 0x0c - 0x0f
-  header.extend(struct.pack('<I', GetEntryPoint(rorofile)))
-  # bytes 0x10 - 0x13
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  # bytes 0x14 - 0x17
-  header.extend(struct.pack('<I', args.payload_offset))
-
-  # bytes 0x14 - 0x3F all 0
-  PadZeroTo(header, 0x40)
-
-  # header signature is appended by the caller
-
-  return header
-
-
-def BuildHeader2(args, payload_len, load_addr, payload_entry):
-  # Identifier and header version
-  header = bytearray(b'PHCM\0')
-
-  # byte[5]
-  b = GetSpiClockParameter(args)
-  b |= (1 << 2)
-  header.append(b)
-
-  # byte[6]
-  b = 0
-  header.append(b)
-
-  # byte[7]
-  header.append(GetSpiReadCmdParameter(args))
-
-  # bytes 0x08 - 0x0b
-  header.extend(struct.pack('<I', load_addr))
-  # bytes 0x0c - 0x0f
-  header.extend(struct.pack('<I', payload_entry))
-  # bytes 0x10 - 0x13
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  # bytes 0x14 - 0x17
-  header.extend(struct.pack('<I', args.payload_offset))
-
-  # bytes 0x14 - 0x3F all 0
-  PadZeroTo(header, 0x40)
-
-  # header signature is appended by the caller
-
-  return header
-
-#
-# Compute SHA-256 of data and return digest
-# as a bytearray
-#
-def HashByteArray(data):
-  hasher = hashlib.sha256()
-  hasher.update(data)
-  h = hasher.digest()
-  bah = bytearray(h)
-  return bah
-
-#
-# Return 64-byte signature of byte array data.
-# Signature is SHA256 of data with 32 0 bytes appended
-#
-def SignByteArray(data):
-  debug_print("Signature is SHA-256 of data")
-  sigb = HashByteArray(data)
-  sigb.extend(b'\0' * 32)
-  return sigb
-
-
-# MEC1701H supports two 32-bit Tags located at offsets 0x0 and 0x4
-# in the SPI flash.
-# Tag format:
-#   bits[23:0] correspond to bits[31:8] of the Header SPI address
-#       Header is always on a 256-byte boundary.
-#   bits[31:24] = CRC8-ITU of bits[23:0].
-# Notice there is no chip-select field in the Tag both Tag's point
-# to the same flash part.
-#
-def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
-
-def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
-    tag.append(Crc8(0, tag))
-    return tag
-
-
-#
-# Creates temporary file for read/write
-# Reads binary file containing LFW image_size (loader_file)
-# Writes LFW image to temporary file
-# Reads RO image at beginning of rorw_file up to image_size
-#  (assumes RO/RW images have been padded with 0xFF
-# Returns temporary file name
-#
-def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-  return fo.name
-
-#
-# Generate a test EC_RW image of same size
-# as original.
-# Preserve image_data structure and fill all
-# other bytes with 0xA5.
-# useful for testing SPI read and EC build
-# process hash generation.
-#
-def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
-
-def parseargs():
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x1000)
-  parser.add_argument("-p", "--payload_offset", type=int,
-                      help="The offset of payload from the start of header",
-                      default=0x80)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 220KB",
-                      default=(220 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-
-  return parser.parse_args()
-
-# Debug helper routine
-def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
-
-def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("\n")
-
-def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  debug_print(".payload_offset = ", hex(args.payload_offset))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", args.spi_read_cmd)
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".verbose = ", args.verbose)
-
-#
-# Handle quiet mode build from Makefile
-# Quiet mode when V is unset or V=0
-# Verbose mode when V=1
-#
-def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
-
-  debug_print("Begin MEC17xx pack_ec.py script")
-
-
-  # MEC17xx maximum 192KB each for RO & RW
-  # mec1701 chip Makefile sets args.spi_size = 512
-  # Tags at offset 0
-  #
-  print_args(args)
-
-  spi_size = args.spi_size * 1024
-  debug_print("SPI Flash image size in bytes =", hex(spi_size))
-
-  # !!! IMPORTANT !!!
-  # These values MUST match chip/mec1701/config_flash_layout.h
-  # defines.
-  # MEC17xx Boot-ROM TAGs are at offset 0 and 4.
-  # lfw + EC_RO starts at beginning of second 4KB sector
-  # EC_RW starts at offset 0x40000 (256KB)
-
-  spi_list = []
-
-  debug_print("args.input = ",args.input)
-  debug_print("args.loader_file = ",args.loader_file)
-  debug_print("args.image_size = ",hex(args.image_size))
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-
-  payload = GetPayload(rorofile)
-  payload_len = len(payload)
-  # debug
-  debug_print("EC_LFW + EC_RO length = ",hex(payload_len))
-
-  # SPI image integrity test
-  # compute CRC32 of EC_RO except for last 4 bytes
-  # skip over 4KB LFW
-  # Store CRC32 in last 4 bytes
-  if args.test_spi == True:
-    crc = zlib.crc32(bytes(payload[LFW_SIZE:(payload_len - 4)]))
-    crc_ofs = payload_len - 4
-    debug_print("EC_RO CRC32 = 0x{0:08x} @ 0x{1:08x}".format(crc, crc_ofs))
-    for i in range(4):
-      payload[crc_ofs + i] = crc & 0xff
-      crc = crc >> 8
-
-  # Chromebooks are not using MEC BootROM ECDSA.
-  # We implemented the ECDSA disabled case where
-  # the 64-byte signature contains a SHA-256 of the binary plus
-  # 32 zeros bytes.
-  payload_signature = SignByteArray(payload)
-  # debug
-  printByteArrayAsHex(payload_signature, "LFW + EC_RO payload_signature")
-
-  # MEC17xx Header is 0x80 bytes with an 64 byte signature
-  # (32 byte SHA256 + 32 zero bytes)
-  header = BuildHeader(args, payload_len, LOAD_ADDR, rorofile)
-  # debug
-  printByteArrayAsHex(header, "Header LFW + EC_RO")
-
-  # MEC17xx payload ECDSA not used, 64 byte signature is
-  # SHA256 + 32 zero bytes
-  header_signature = SignByteArray(header)
-  # debug
-  printByteArrayAsHex(header_signature, "header_signature")
-
-  tag = BuildTag(args)
-  # MEC17xx truncate RW length to args.image_size to not overwrite LFW
-  # offset may be different due to Header size and other changes
-  # MCHP we want to append a SHA-256 to the end of the actual payload
-  # to test SPI read routines.
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  payload_rw = GetPayloadFromOffset(args.input, args.image_size)
-  debug_print("type(payload_rw) is ", type(payload_rw))
-  debug_print("len(payload_rw) is ", hex(len(payload_rw)))
-
-  # truncate to args.image_size
-  rw_len = args.image_size
-  payload_rw = payload_rw[:rw_len]
-  payload_rw_len = len(payload_rw)
-  debug_print("Truncated size of EC_RW = ", hex(payload_rw_len))
-
-  payload_entry_tuple = struct.unpack_from('<I', payload_rw, 4)
-  debug_print("payload_entry_tuple = ", payload_entry_tuple)
-
-  payload_entry = payload_entry_tuple[0]
-  debug_print("payload_entry = ", hex(payload_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(payload_rw)
-
-  # SPI image integrity test
-  # compute CRC32 of EC_RW except for last 4 bytes
-  # Store CRC32 in last 4 bytes
-  if args.test_spi == True:
-    crc = zlib.crc32(bytes(payload_rw[:(payload_rw_len - 32)]))
-    crc_ofs = payload_rw_len - 4
-    debug_print("EC_RW CRC32 = 0x{0:08x} at offset 0x{1:08x}".format(crc, crc_ofs))
-    for i in range(4):
-      payload_rw[crc_ofs + i] = crc & 0xff
-      crc = crc >> 8
-
-  payload_rw_sig = SignByteArray(payload_rw)
-  # debug
-  printByteArrayAsHex(payload_rw_sig, "payload_rw_sig")
-
-  os.remove(rorofile)           # clean up the temp file
-
-  # MEC170x Boot-ROM Tags are located at SPI offset 0
-  spi_list.append((0, tag, "tag"))
-
-  spi_list.append((args.header_loc, header, "header(lwf + ro)"))
-  spi_list.append((args.header_loc + HEADER_SIZE, header_signature,
-    "header(lwf + ro) signature"))
-  spi_list.append((args.header_loc + args.payload_offset, payload,
-    "payload(lfw + ro)"))
-
-  offset = args.header_loc + args.payload_offset + payload_len
-
-  # No SPI Header for EC_RW as its not loaded by BootROM
-  spi_list.append((offset, payload_signature,
-                   "payload(lfw_ro) signature"))
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  if rw_offset < offset + len(payload_signature):
-    print("ERROR: EC_RW overlaps EC_RO")
-
-  spi_list.append((rw_offset, payload_rw, "payload(rw)"))
-
-  # don't add to EC_RW. We don't know if Google will process
-  # EC SPI flash binary with other tools during build of
-  # coreboot and OS.
-  #offset = rw_offset + payload_rw_len
-  #spi_list.append((offset, payload_rw_sig, "payload(rw) signature"))
-
-  spi_list = sorted(spi_list)
-
-  dumpsects(spi_list)
-
-  #
-  # MEC17xx Boot-ROM locates TAG at SPI offset 0 instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
-
-    f.flush()
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/mchp/util/pack_ec_mec152x.py b/chip/mchp/util/pack_ec_mec152x.py
deleted file mode 100755
index 34846cd6ba..0000000000
--- a/chip/mchp/util/pack_ec_mec152x.py
+++ /dev/null
@@ -1,803 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# A script to pack EC binary into SPI flash image for MEC152x
-# Based on MEC1521/MEC1523_ROM_Description.pdf
-import argparse
-import hashlib
-import os
-import struct
-import subprocess
-import tempfile
-import zlib # CRC32
-
-# MEC152xH has 256KB SRAM from 0xE0000 - 0x120000
-# SRAM is divided into contiguous CODE & DATA
-# CODE at [0xE0000, 0x117FFF] DATA at [0x118000, 0x11FFFF]
-# SPI flash size for board is 512KB
-# Boot-ROM TAG is located at SPI offset 0 (two 4-byte tags)
-
-LFW_SIZE = 0x1000
-LOAD_ADDR = 0x0E0000
-LOAD_ADDR_RW = 0xE1000
-MEC152X_HEADER_SIZE = 0x140
-MEC152X_HEADER_VERSION = 0x02
-PAYLOAD_PAD_BYTE = b'\xff'
-SPI_ERASE_BLOCK_SIZE = 0x1000
-SPI_CLOCK_LIST = [48, 24, 16, 12]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
-SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3}
-CHIP_MAX_CODE_SRAM_KB = 224
-
-MEC152X_DICT = {
-                "HEADER_SIZE":0x140,
-                "HEADER_VER":0x02,
-                "PAYLOAD_OFFSET":0x140,
-                "PAYLOAD_GRANULARITY":128,
-                "EC_INFO_BLK_SZ":128,
-                "ENCR_KEY_HDR_SZ":128,
-                "COSIG_SZ":96,
-                "TRAILER_SZ":160,
-                "TAILER_PAD_BYTE":b'\xff',
-                "PAD_SIZE":128
-                }
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
-
-def mock_print(*args, **kwargs):
-  pass
-
-debug_print = mock_print
-
-# Debug helper routine
-def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
-
-def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  if ba == None:
-      debug_print("None")
-      return
-
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("")
-
-def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
-
-def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return int.from_bytes(s, byteorder='little')
-
-def GetPayloadFromOffset(payload_file, offset, padsize):
-  """Read payload and pad it to padsize."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % padsize
-  debug_print("GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(padsize,len(payload),rem_len))
-
-  if rem_len:
-    payload += PAYLOAD_PAD_BYTE * (padsize - rem_len)
-    debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len))
-
-  return payload
-
-def GetPayload(payload_file, padsize):
-  """Read payload and pad it to padsize"""
-  return GetPayloadFromOffset(payload_file, 0, padsize)
-
-def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
-
-def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
-
-def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
-
-def GetEncodedSpiDriveStrength(args):
-  assert args.spi_drive_str in SPI_DRIVE_STR_DICT, \
-         "Unsupported SPI drive strength %d mA" % args.spi_drive_str
-  return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
-
-# Return 0=Slow slew rate or 1=Fast slew rate
-def GetSpiSlewRate(args):
-    if args.spi_slew_fast == True:
-        return 1
-    return 0
-
-# Return SPI CPOL = 0 or 1
-def GetSpiCpol(args):
-    if args.spi_cpol == 0:
-        return 0
-    return 1
-
-# Return SPI CPHA_MOSI
-# 0 = SPI Master drives data is stable on inactive to clock edge
-# 1 = SPI Master drives data is stable on active to inactive clock edge
-def GetSpiCphaMosi(args):
-    if args.spi_cpha_mosi == 0:
-        return 0
-    return 1
-
-# Return SPI CPHA_MISO 0 or 1
-# 0 = SPI Master samples data on inactive to active clock edge
-# 1 = SPI Master samples data on active to inactive clock edge
-def GetSpiCphaMiso(args):
-    if args.spi_cpha_miso == 0:
-        return 0
-    return 1
-
-def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
-
-#
-# Boot-ROM SPI image encryption not used with Chromebooks
-#
-def EncryptPayload(args, chip_dict, payload):
-    return None
-
-#
-# Build SPI image header for MEC152x
-# MEC152x image header size = 320(0x140) bytes
-#
-# Description using Python slice notation [start:start+len]
-#
-# header[0:4] = 'PHCM'
-# header[4] = header version = 0x02(MEC152x)
-# header[5] = SPI clock speed, drive strength, sampling mode
-#   bits[1:0] = SPI clock speed: 0=48, 1=24, 2=16, 3=12
-#   bits[3:2] = SPI controller pins drive strength
-#               00b=2mA, 01b=4mA, 10b=8mA, 11b=12mA
-#   bit[4] = SPI controller pins slew rate: 0=slow, 1=fast
-#   bit[5] = SPI CPOL: 0=SPI clock idle is low, 1=idle is high
-#   bit[6] = CHPHA_MOSI
-#       1:data change on first inactive to active clock edge
-#       0:data change on first active to inactive clock edge
-#   bit[7] = CHPHA_MISO:
-#       1: Data captured on first inactive to active clock edge
-#       0: Data captured on first active to inactive clock edge
-# header[6] Boot-ROM loader flags
-#   bits[2:0] = VTR0,1,2 rails. 0=3.3V, 1=1.8V. NOTE VTR1=0 always
-#   bits[5:3] = 111b
-#   bit[6]: For MEC152x controls authentication
-#           0=Authentication disabled. Signature is SHA-384 of FW payload
-#           1=Authentication enabled. Signature is ECDSA P-384
-#   bit[7]: 0=FW pyload not encrypted, 1=FW payload is encrypted
-# header[7]: SPI Flash read command
-#            0x03 1-1-1 read freq < 33MHz
-#            0x0B 1-1-1 + 8 clocks(data tri-stated)
-#            0x3B 1-1-2 + 8 clocks(data tri-stated). Data phase is dual I/O
-#            0x6B 1-1-4 + 8 clocks(data tri-stated). Data phase is Quad I/O
-#            NOTE: Quad requires SPI flash device QE(quad enable) bit
-#            to be factory set. Enabling QE disables HOLD# and WP#
-#            functionality of the SPI flash device.
-# header[0x8:0xC] SRAM Load address little-endian format
-# header[0xC:0x10] SRAM FW entry point. Boot-ROM jumps to
-#                  this address on successful load. (little-endian)
-# header[0x10:0x12] little-endian format: FW binary size in units of
-#                   128 bytes(MEC152x)
-# header[0x12:0x14] = 0 reserved
-# header[0x14:0x18] = Little-ending format: Unsigned offset from start of
-#                     header to FW payload.
-#                     MEC152x: Offset must be a multiple of 128
-#                     Offset must be > header size.
-#                     NOTE: If Authentication is enabled size includes
-#                     the appended signature.
-# MEC152x:
-# header[0x18] = Authentication key select. Set to 0 for no Authentication.
-# header[0x19:0x50] = 0 reserved.
-# header[0x50:0x80] = ECDSA-384 public key x-coord. = 0 Auth. disabled
-# header[0x80:0xB0] = ECDSA-384 public key y-coord. = 0 Auth. disabled
-# header[0xB0:0xE0] = SHA-384 digest of header[0:0xB0]
-# header[0xE0:0x110] = Header ECDSA-384 signature x-coord. = 0 Auth. disabled
-# header[0x110:0x140] = Header ECDSA-384 signature y-coor. = 0 Auth. disabled
-#
-def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
-  header_size = MEC152X_HEADER_SIZE
-
-  # allocate zero filled header
-  header = bytearray(b'\x00' * header_size)
-  debug_print("len(header) = ", len(header))
-
-  # Identifier and header version
-  header[0:4] = b'PHCM'
-  header[4] = MEC152X_HEADER_VERSION
-
-  # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
-  spiFreqMHz = GetSpiClockParameter(args)
-  header[5] = (int(spiFreqMHz // 48) - 1) & 0x03
-  header[5] |= ((GetEncodedSpiDriveStrength(args) & 0x03) << 2)
-  header[5] |= ((GetSpiSlewRate(args) & 0x01) << 4)
-  header[5] |= ((GetSpiCpol(args) & 0x01) << 5)
-  header[5] |= ((GetSpiCphaMosi(args) & 0x01) << 6)
-  header[5] |= ((GetSpiCphaMiso(args) & 0x01) << 7)
-
-  # b[0]=0 VTR1 must be 3.3V
-  # b[1]=0(VTR2 3.3V), 1(VTR2 1.8V)
-  # b[2]=0(VTR3 3.3V), 1(VTR3 1.8V)
-  # b[5:3]=111b
-  # b[6]=0 No ECDSA
-  # b[7]=0 No encrypted FW image
-  header[6] = 0x7 << 3
-  if args.vtr2_V18 == True:
-      header[6] |= 0x02
-  if args.vtr3_V18 == True:
-      header[6] |= 0x04
-
-  # SPI read command set same for both chips
-  header[7] = GetSpiReadCmdParameter(args) & 0xFF
-
-  # bytes 0x08 - 0x0b
-  header[0x08:0x0C] = load_addr.to_bytes(4, byteorder='little')
-  # bytes 0x0c - 0x0f
-  header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder='little')
-  # bytes 0x10 - 0x11 payload length in units of 128 bytes
-
-  payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
-  assert payload_units < 0x10000, \
-      print("Payload too large: len={0} units={1}".format(payload_len, payload_units))
-
-  header[0x10:0x12] = payload_units.to_bytes(2, 'little')
-
-  # bytes 0x14 - 0x17
-  header[0x14:0x18] = chip_dict["PAYLOAD_OFFSET"].to_bytes(4, 'little')
-
-  # MEC152x: Disable ECDSA and encryption
-  header[0x18] = 0
-
-  # header[0xB0:0xE0] = SHA384(header[0:0xB0])
-  header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
-  # When ECDSA authentication is disabled MCHP SPI image generator
-  # is filling the last 48 bytes of the Header with 0xff
-  header[-48:] = b'\xff' * 48
-
-  debug_print("After hash: len(header) = ", len(header))
-
-  return header
-
-#
-# MEC152x 128-byte EC Info Block appended to
-# end of padded FW binary
-# bytes 0 through 103 are undefined, we set to 0xFF
-# bytes 104 through 119 are rollback permissions
-# bytes 120 through 123 are key revocation permissions
-# byte 124 = customer platform ID[7:0]
-# byte 125 = customer platform ID[15:8]
-# byte 126 = customer auto rollback flags
-# byte 127 = customer current image revision
-#
-def GenEcInfoBlock(args, chip_dict):
-  ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
-  return ecinfo
-
-#
-# Generate SPI FW image co-signature.
-# MEC152X cosignature is 96 bytes used by OEM FW
-# developer to sign their binary with ECDSA-P384-SHA384 or
-# some other signature algorithm that fits in 96 bytes.
-# At this time Cros-EC is not using this field, fill with 0xFF.
-# If this feature is implemented we need to read the OEM's
-# generated signature from a file and extract the binary
-# signature.
-#
-def GenCoSignature(args, chip_dict, payload):
-    return bytearray(b'\xff' * chip_dict["COSIG_SZ"])
-
-#
-# Generate SPI FW Image trailer.
-# MEC152X: Size = 160 bytes
-#   binary = payload || encryption_key_header || ec_info_block || cosignature
-#   trailer[0:48] = SHA384(binary)
-#   trailer[48:144] = 0xFF
-#   trailer[144:160] = 0xFF. Boot-ROM spec. says these bytes should be random.
-#       Authentication & encryption are not used therefore random data
-#       is not necessary.
-def GenTrailer(args, chip_dict, payload, encryption_key_header,
-               ec_info_block, cosignature):
-    trailer = bytearray(chip_dict["TAILER_PAD_BYTE"] * chip_dict["TRAILER_SZ"])
-    hasher = hashlib.sha384()
-    hasher.update(payload)
-    if ec_info_block != None:
-      hasher.update(ec_info_block)
-    if encryption_key_header != None:
-      hasher.update(encryption_key_header)
-    if cosignature != None:
-      hasher.update(cosignature)
-    trailer[0:48] = hasher.digest()
-    trailer[-16:] = 16 * b'\xff'
-
-    return trailer
-
-# MEC152xH supports two 32-bit Tags located at offsets 0x0 and 0x4
-# in the SPI flash.
-# Tag format:
-#   bits[23:0] correspond to bits[31:8] of the Header SPI address
-#       Header is always on a 256-byte boundary.
-#   bits[31:24] = CRC8-ITU of bits[23:0].
-# Notice there is no chip-select field in the Tag both Tag's point
-# to the same flash part.
-#
-def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
-
-def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
-    tag.append(Crc8(0, tag))
-    return tag
-
-
-# FlashMap is an option for MEC152x
-# It is a 32 bit structure
-# bits[18:0] = bits[30:12] of second SPI flash base address
-# bits[23:19] = 0 reserved
-# bits[31:24] = CRC8 of bits[23:0]
-# Input:
-#   integer containing base address of second SPI flash
-#   This value is usually equal to the size of the first
-#   SPI flash and should be a multiple of 4KB
-# Output:
-#   bytearray of length 4
-def BuildFlashMap(secondSpiFlashBaseAddr):
-  flashmap = bytearray(4)
-  flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xff
-  flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xff
-  flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xff
-  flashmap[3] = Crc8(0, flashmap)
-  return flashmap
-
-#
-# Creates temporary file for read/write
-# Reads binary file containing LFW image_size (loader_file)
-# Writes LFW image to temporary file
-# Reads RO image at beginning of rorw_file up to image_size
-#  (assumes RO/RW images have been padded with 0xFF
-# Returns temporary file name
-#
-def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-
-  return fo.name
-
-#
-# Generate a test EC_RW image of same size
-# as original.
-# Preserve image_data structure and fill all
-# other bytes with 0xA5.
-# useful for testing SPI read and EC build
-# process hash generation.
-#
-def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
-
-def parseargs():
-  #TODO I commented this out. Why?
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x1000)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 220KB",
-                      default=(220 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-  parser.add_argument("--tag0_loc", type=int,
-                      help="MEC152X TAG0 SPI offset",
-                      default=0)
-  parser.add_argument("--tag1_loc", type=int,
-                      help="MEC152X TAG1 SPI offset",
-                      default=4)
-  parser.add_argument("--spi_drive_str", type=int,
-                      help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
-                      default=4)
-  parser.add_argument("--spi_slew_fast", action='store_true',
-                      help="SPI use fast slew rate. Default is False",
-                      default=False)
-  parser.add_argument("--spi_cpol", type=int,
-                      help="SPI clock polarity when idle. Defealt is 0(low)",
-                      default=0)
-  parser.add_argument("--spi_cpha_mosi", type=int,
-                      help="""SPI clock phase master drives data.
-                              0=Data driven on active to inactive clock edge,
-                              1=Data driven on inactive to active clock edge""",
-                      default=0)
-  parser.add_argument("--spi_cpha_miso", type=int,
-                      help="""SPI clock phase master samples data.
-                              0=Data sampled on inactive to active clock edge,
-                              1=Data sampled on active to inactive clock edge""",
-                      default=0)
-
-  parser.add_argument("--vtr2_V18", action='store_true',
-                      help="Chip VTR2 rail is 1.8V. Default is False(3.3V)",
-                      default=False)
-
-  parser.add_argument("--vtr3_V18", action='store_true',
-                      help="Chip VTR3 rail is 1.8V. Default is False(3.3V)",
-                      default=False)
-
-  return parser.parse_args()
-
-def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".tag0_loc = ", hex(args.tag0_loc))
-  debug_print(".tag1_loc = ", hex(args.tag1_loc))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock (MHz) = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".test_ecrw = ", args.test_ecrw)
-  debug_print(".verbose = ", args.verbose)
-  debug_print(".spi_drive_str = ", args.spi_drive_str)
-  debug_print(".spi_slew_fast = ", args.spi_slew_fast)
-  debug_print(".spi_cpol = ", args.spi_cpol)
-  debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
-  debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
-  debug_print(".vtr2_V18 = ", args.vtr2_V18)
-  debug_print(".vtr3_V18 = ", args.vtr3_V18)
-
-#
-# Handle quiet mode build from Makefile
-# Quiet mode when V is unset or V=0
-# Verbose mode when V=1
-#
-# MEC152x SPI Image Generator
-# No authentication
-# No payload encryption
-#
-# SPI Offset 0x0 = TAG0 points to Header for EC-RO FW
-# SPI Offset 0x4 = TAG1 points to Header for EC-RO FW
-# TAG Size = 4 bytes
-#  bits[23:0] = bits[31:8] of Header SPI offset
-#  bits[31:24] = CRC8-ITU checksum of bits[23:0].
-#
-# MEC152X SPI header and payload layout for minimum size
-# header offset aligned on 256 byte boundary
-# header_spi_address:
-#   header[0:0x4F] = Header data
-#   header[0x50:0x80] = ECDSA-P384 public key x for Header authentication
-#   header[0x80:0xB0] = ECDSA-P384 public key y for Header authentication
-#   header[0xB0:0xE0] = SHA384 digest of header[0:0xB0]
-#   header[0xE0:0x110] = ECDSA-P384-SHA384 Signature.R of header[0:0xB0]
-#   header[0x110:0x140] = ECDSA-P384-SHA384 Signature.S of header[0:0xB0]
-# payload_spi_address = header_spi_address + len(Header)
-#       Payload had been padded such that len(padded_payload) % 128 == 0
-#   padded_payload[padded_payload_len]
-# payload_signature_address = payload_spi_address + len(padded_payload)
-#  payload_encryption_key_header[128] Not present if encryption disabled
-#  payload_cosignature[96] = 0 if Authentication is disabled
-#  payload_trailer[160] = SHA384(padded_payload ||
-#                                optional payload_encryption_key_header)
-#                       || 48 * [0]
-#                       || 48 * [0]
-#
-def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
-
-  debug_print("Begin pack_ec_mec152x.py script")
-
-  print_args(args)
-
-  chip_dict = MEC152X_DICT
-
-  # Boot-ROM requires header location aligned >= 256 bytes.
-  # CrOS EC flash image update code requires EC_RO/RW location to be aligned
-  # on a flash erase size boundary and EC_RO/RW size to be a multiple of
-  # the smallest flash erase block size.
-  #
-  assert (args.header_loc % SPI_ERASE_BLOCK_SIZE) == 0, \
-      "Header location %d is not on a flash erase block boundary boundary" % args.header_loc
-
-  max_image_size = CHIP_MAX_CODE_SRAM_KB - LFW_SIZE
-  if args.test_spi:
-      max_image_size -= 32 # SHA256 digest
-
-  assert args.image_size > max_image_size, \
-      "Image size exceeds maximum" % args.image_size
-
-  spi_size = args.spi_size * 1024
-  debug_print("SPI Flash image size in bytes =", hex(spi_size))
-
-  # !!! IMPORTANT !!!
-  # These values MUST match chip/mchp/config_flash_layout.h
-  # defines.
-  # MEC152x Boot-ROM TAGs are at offset 0 and 4.
-  # lfw + EC_RO starts at beginning of second 4KB sector
-  # EC_RW starts at (flash size / 2) i.e. 0x40000 for a 512KB flash.
-
-  spi_list = []
-
-  debug_print("args.input = ",args.input)
-  debug_print("args.loader_file = ",args.loader_file)
-  debug_print("args.image_size = ",hex(args.image_size))
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
-
-  lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"])
-  lfw_ecro_len = len(lfw_ecro)
-  debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
-
-  # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4]))
-      crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder='little')
-      lfw_ecro[-4:] = crc32_ecro_bytes
-      debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE))
-      debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
-
-  # Reads entry point from offset 4 of file.
-  # This assumes binary has Cortex-M4 vector table at offset 0.
-  # 32-bit word at offset 0x0 initial stack pointer value
-  # 32-bit word at offset 0x4 address of reset handler
-  # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
-  lfw_ecro_entry = GetEntryPoint(rorofile)
-
-  # Chromebooks are not using MEC BootROM SPI header/payload authentication
-  # or payload encryption. In this case the header authentication signature
-  # is filled with the hash digest of the respective entity.
-  # BuildHeader2 computes the hash digest and stores it in the correct
-  # header location.
-  header = BuildHeader2(args, chip_dict, lfw_ecro_len,
-                        LOAD_ADDR, lfw_ecro_entry)
-  printByteArrayAsHex(header, "Header(lfw_ecro)")
-
-  # If payload encryption used then encrypt payload and
-  # generate Payload Key Header. If encryption not used
-  # payload is not modified and the method returns None
-  encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(encryption_key_header,
-                      "LFW + EC_RO encryption_key_header")
-
-  ec_info_block = GenEcInfoBlock(args, chip_dict)
-  printByteArrayAsHex(ec_info_block, "EC Info Block")
-
-  cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
-
-  trailer = GenTrailer(args, chip_dict, lfw_ecro, encryption_key_header,
-                       ec_info_block, cosignature)
-
-  printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
-
-  # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
-  tag0 = BuildTag(args)
-  tag1 = tag0
-
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  ecrw = GetPayloadFromOffset(args.input, args.image_size,
-                              chip_dict["PAD_SIZE"])
-  debug_print("type(ecrw) is ", type(ecrw))
-  debug_print("len(ecrw) is ", hex(len(ecrw)))
-
-  # truncate to args.image_size
-  ecrw_len = len(ecrw)
-  if ecrw_len > args.image_size:
-      debug_print("Truncate EC_RW len={0:0x} to image_size={1:0x}".format(ecrw_len,args.image_size))
-      ecrw = ecrw[:args.image_size]
-      ecrw_len = len(ecrw)
-
-  debug_print("len(EC_RW) = ", hex(ecrw_len))
-
-  # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
-      crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder='little')
-      ecrw[-4:] = crc32_ecrw_bytes
-      debug_print("ecrw len = ", hex(len(ecrw)))
-      debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
-
-  # Assume FW layout is standard Cortex-M style with vector
-  # table at start of binary.
-  # 32-bit word at offset 0x0 = Initial stack pointer
-  # 32-bit word at offset 0x4 = Address of reset handler
-  ecrw_entry_tuple = struct.unpack_from('<I', ecrw, 4)
-  debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
-
-  ecrw_entry = ecrw_entry_tuple[0]
-  debug_print("ecrw_entry = ", hex(ecrw_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(ecrw)
-
-  os.remove(rorofile)           # clean up the temp file
-
-  # MEC152X Add TAG's
-  spi_list.append((args.tag0_loc, tag0, "tag0"))
-  spi_list.append((args.tag1_loc, tag1, "tag1"))
-
-  # flashmap is non-zero only for systems with two external
-  # SPI flash chips.
-  flashmap = BuildFlashMap(0)
-  spi_list.append((8, flashmap, "flashmap"))
-
-  # Boot-ROM SPI image header for LFW+EC-RO
-  spi_list.append((args.header_loc, header, "header(lfw + ro)"))
-  spi_list.append((args.header_loc + chip_dict["PAYLOAD_OFFSET"], lfw_ecro,
-                   "lfw_ecro"))
-
-  offset = args.header_loc + chip_dict["PAYLOAD_OFFSET"] + lfw_ecro_len
-
-  if ec_info_block != None:
-    spi_list.append((offset, ec_info_block, "EC Info Block"))
-    offset += len(ec_info_block)
-
-  if cosignature != None:
-    spi_list.append((offset, cosignature, "ECRO Cosignature"))
-    offset += len(cosignature)
-
-  if trailer != None:
-    spi_list.append((offset, trailer, "ECRO Trailer"))
-    offset += len(trailer)
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  assert rw_offset >= offset, \
-      print("""Offset of EC_RW at {0:08x} overlaps end
-               of EC_RO at {0:08x}""".format(rw_offset, offset))
-
-  spi_list.append((rw_offset, ecrw, "ecrw"))
-  offset = rw_offset + len(ecrw)
-
-  spi_list = sorted(spi_list)
-
-  dumpsects(spi_list)
-
-  #
-  # MEC152X Boot-ROM locates TAG0/1 at SPI offset 0
-  # instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
-
-    f.flush()
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/mchp/util/pack_ec_mec172x.py b/chip/mchp/util/pack_ec_mec172x.py
deleted file mode 100755
index 32747d3d9a..0000000000
--- a/chip/mchp/util/pack_ec_mec172x.py
+++ /dev/null
@@ -1,851 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# A script to pack EC binary into SPI flash image for MEC172x
-# Based on MEC172x_ROM_Description.pdf revision 6/8/2020
-import argparse
-import hashlib
-import os
-import struct
-import subprocess
-import tempfile
-import zlib # CRC32
-
-# MEC172x has 416KB SRAM from 0xC0000 - 0x127FFF
-# SRAM is divided into contiguous CODE & DATA
-# CODE at [0xC0000, 0x117FFF] DATA at [0x118000, 0x127FFF]
-# Google EC SPI flash size for board is currently 512KB
-# split into 1/2.
-# EC_RO: 0 - 0x3FFFF
-# EC_RW: 0x40000 - 0x7FFFF
-#
-SPI_ERASE_BLOCK_SIZE = 0x1000
-SPI_CLOCK_LIST = [48, 24, 16, 12, 96]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
-SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3}
-# Maximum EC_RO/EC_RW code size is based upon SPI flash erase
-# sector size, MEC172x Boot-ROM TAG, Header, Footer.
-# SPI Offset      Description
-# 0x00 - 0x07     TAG0 and TAG1
-# 0x1000 - 0x113F Boot-ROM SPI Header
-# 0x1140 - 0x213F 4KB LFW
-# 0x2040 - 0x3EFFF
-# 0x3F000 - 0x3FFFF BootROM EC_INFO_BLK || COSIG || ENCR_KEY_HDR(optional) || TRAILER
-CHIP_MAX_CODE_SRAM_KB = (256 - 12)
-
-MEC172X_DICT = {
-                "LFW_SIZE": 0x1000,
-                "LOAD_ADDR": 0xC0000,
-                "TAG_SIZE": 4,
-                "KEY_BLOB_SIZE": 1584,
-                "HEADER_SIZE":0x140,
-                "HEADER_VER":0x03,
-                "PAYLOAD_GRANULARITY":128,
-                "PAYLOAD_PAD_BYTE":b'\xff',
-                "EC_INFO_BLK_SZ":128,
-                "ENCR_KEY_HDR_SZ":128,
-                "COSIG_SZ":96,
-                "TRAILER_SZ":160,
-                "TAILER_PAD_BYTE":b'\xff',
-                "PAD_SIZE":128
-                }
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
-
-def mock_print(*args, **kwargs):
-  pass
-
-debug_print = mock_print
-
-# Debug helper routine
-def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
-
-def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  if ba == None:
-      debug_print("None")
-      return
-
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("")
-
-def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
-
-def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return int.from_bytes(s, byteorder='little')
-
-def GetPayloadFromOffset(payload_file, offset, padsize):
-  """Read payload and pad it to padsize."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % padsize
-  debug_print("GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(padsize,len(payload),rem_len))
-
-  if rem_len:
-    payload += PAYLOAD_PAD_BYTE * (padsize - rem_len)
-    debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len))
-
-  return payload
-
-def GetPayload(payload_file, padsize):
-  """Read payload and pad it to padsize"""
-  return GetPayloadFromOffset(payload_file, 0, padsize)
-
-def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
-
-def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
-
-def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
-
-def GetEncodedSpiDriveStrength(args):
-  assert args.spi_drive_str in SPI_DRIVE_STR_DICT, \
-         "Unsupported SPI drive strength %d mA" % args.spi_drive_str
-  return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
-
-# Return 0=Slow slew rate or 1=Fast slew rate
-def GetSpiSlewRate(args):
-    if args.spi_slew_fast == True:
-        return 1
-    return 0
-
-# Return SPI CPOL = 0 or 1
-def GetSpiCpol(args):
-    if args.spi_cpol == 0:
-        return 0
-    return 1
-
-# Return SPI CPHA_MOSI
-# 0 = SPI Master drives data is stable on inactive to clock edge
-# 1 = SPI Master drives data is stable on active to inactive clock edge
-def GetSpiCphaMosi(args):
-    if args.spi_cpha_mosi == 0:
-        return 0
-    return 1
-
-# Return SPI CPHA_MISO 0 or 1
-# 0 = SPI Master samples data on inactive to active clock edge
-# 1 = SPI Master samples data on active to inactive clock edge
-def GetSpiCphaMiso(args):
-    if args.spi_cpha_miso == 0:
-        return 0
-    return 1
-
-def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
-
-#
-# Boot-ROM SPI image encryption not used with Chromebooks
-#
-def EncryptPayload(args, chip_dict, payload):
-    return None
-
-#
-# Build SPI image header for MEC172x
-# MEC172x image header size = 320(0x140) bytes
-#
-# Description using Python slice notation [start:start+len]
-#
-# header[0:4] = 'PHCM'
-# header[4] = header version = 0x03(MEC172x)
-# header[5] = SPI clock speed, drive strength, sampling mode
-#   bits[1:0] = SPI clock speed: 0=48, 1=24, 2=16, 3=12
-#   bits[3:2] = SPI controller pins drive strength
-#               00b=2mA, 01b=4mA, 10b=8mA, 11b=12mA
-#   bit[4] = SPI controller pins slew rate: 0=slow, 1=fast
-#   bit[5] = SPI CPOL: 0=SPI clock idle is low, 1=idle is high
-#   bit[6] = CHPHA_MOSI
-#       1:data change on first inactive to active clock edge
-#       0:data change on first active to inactive clock edge
-#   bit[7] = CHPHA_MISO:
-#       1: Data captured on first inactive to active clock edge
-#       0: Data captured on first active to inactive clock edge
-# header[6] Boot-ROM loader flags
-#   bits[0] = 0(use header[5] b[1:0]), 1(96 MHz)
-#   bits[2:1] = 0 reserved
-#   bits[5:3] = 111b
-#   bit[6]: For MEC172x controls authentication
-#           0=Authentication disabled. Signature is SHA-384 of FW payload
-#           1=Authentication enabled. Signature is ECDSA P-384
-#   bit[7]: 0=FW pyload not encrypted, 1=FW payload is encrypted
-# header[7]: SPI Flash read command
-#            0 -> 0x03 1-1-1 read freq < 33MHz
-#            1 -> 0x0B 1-1-1 + 8 clocks(data tri-stated)
-#            2 -> 0x3B 1-1-2 + 8 clocks(data tri-stated). Data phase is dual I/O
-#            3 -> 0x6B 1-1-4 + 8 clocks(data tri-stated). Data phase is Quad I/O
-#            NOTE: Quad requires SPI flash device QE(quad enable) bit
-#            to be factory set. Enabling QE disables HOLD# and WP#
-#            functionality of the SPI flash device.
-# header[0x8:0xC] SRAM Load address little-endian format
-# header[0xC:0x10] SRAM FW entry point. Boot-ROM jumps to
-#                  this address on successful load. (little-endian)
-# header[0x10:0x12] little-endian format: FW binary size in units of
-#                   128 bytes(MEC172x)
-# header[0x12:0x14] = 0 reserved
-# header[0x14:0x18] = Little-ending format: Unsigned offset from start of
-#                     header to FW payload.
-#                     MEC172x: Offset must be a multiple of 128
-#                     Offset must be >= header size.
-#                     NOTE: If Authentication is enabled size includes
-#                     the appended signature.
-# MEC172x:
-# header[0x18] = Authentication key select. Set to 0 for no Authentication.
-# header[0x19] = SPI flash device(s) drive strength feature flags
-#                 b[0]=1 SPI flash device 0 has drive strength feature
-#                 b[1]=SPI flash 0: DrvStr Write format(0=2 bytes, 1=1 byte)
-#                 b[2]=1 SPI flash device 1 has drive strength feature
-#                 b[3]=SPI flash 1: DrvStr Write format(0=2 bytes, 1=1 byte)
-#                 b[7:4] = 0 reserved
-# header[0x1A:0x20] = 0 reserved
-# header[0x20] = SPI opcode to read drive strength from SPI flash 0
-# header[0x21] = SPI opcode to write drive strength to SPI flash 0
-# header[0x22] = SPI flash 0: drvStr value
-# header[0x23] = SPI flash 0: drvStr mask
-# header[0x24] = SPI opcode to read drive strength from SPI flash 1
-# header[0x25] = SPI opcode to write drive strength to SPI flash 1
-# header[0x26] = SPI flash 1: drvStr value
-# header[0x27] = SPI flash 1: drvStr mask
-# header[0x28:0x48] = reserved, may be any value
-# header[0x48:0x50] = reserved for customer use
-# header[0x50:0x80] = ECDSA-384 public key x-coord. = 0 Auth. disabled
-# header[0x80:0xB0] = ECDSA-384 public key y-coord. = 0 Auth. disabled
-# header[0xB0:0xE0] = SHA-384 digest of header[0:0xB0]
-# header[0xE0:0x110] = Header ECDSA-384 signature x-coord. = 0 Auth. disabled
-# header[0x110:0x140] = Header ECDSA-384 signature y-coor. = 0 Auth. disabled
-#
-def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
-  header_size = chip_dict["HEADER_SIZE"]
-
-  # allocate zero filled header
-  header = bytearray(b'\x00' * header_size)
-  debug_print("len(header) = ", len(header))
-
-  # Identifier and header version
-  header[0:4] = b'PHCM'
-  header[4] = chip_dict["HEADER_VER"]
-
-  # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
-  spiFreqIndex = GetSpiClockParameter(args)
-  if spiFreqIndex > 3:
-    header[6] |= 0x01
-  else:
-    header[5] = spiFreqIndex
-
-  header[5] |= ((GetEncodedSpiDriveStrength(args) & 0x03) << 2)
-  header[5] |= ((GetSpiSlewRate(args) & 0x01) << 4)
-  header[5] |= ((GetSpiCpol(args) & 0x01) << 5)
-  header[5] |= ((GetSpiCphaMosi(args) & 0x01) << 6)
-  header[5] |= ((GetSpiCphaMiso(args) & 0x01) << 7)
-
-  # header[6]
-  # b[0] value set above
-  # b[2:1] = 00b, b[5:3]=111b
-  # b[7]=0 No encryption of FW payload
-  header[6] |= 0x7 << 3
-
-  # SPI read command set same for both chips
-  header[7] = GetSpiReadCmdParameter(args) & 0xFF
-
-  # bytes 0x08 - 0x0b
-  header[0x08:0x0C] = load_addr.to_bytes(4, byteorder='little')
-  # bytes 0x0c - 0x0f
-  header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder='little')
-
-  # bytes 0x10 - 0x11 payload length in units of 128 bytes
-  assert payload_len % chip_dict["PAYLOAD_GRANULARITY"] == 0, \
-         print("Payload size not a multiple of {0}".format(chip_dict["PAYLOAD_GRANULARITY"]))
-
-  payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
-  assert payload_units < 0x10000, \
-      print("Payload too large: len={0} units={1}".format(payload_len, payload_units))
-
-  header[0x10:0x12] = payload_units.to_bytes(2, 'little')
-
-  # bytes 0x14 - 0x17 TODO offset from start of payload to FW payload to be
-  # loaded by Boot-ROM. We ask Boot-ROM to load (LFW || EC_RO).
-  # LFW location provided on the command line.
-  assert (args.lfw_loc % 4096 == 0), \
-         print("LFW location not on a 4KB boundary! 0x{0:0x}".format(args.lfw_loc))
-
-  assert args.lfw_loc >= (args.header_loc + chip_dict["HEADER_SIZE"]), \
-         print("LFW location not greater than header location + header size")
-
-  lfw_ofs = args.lfw_loc - args.header_loc
-  header[0x14:0x18] = lfw_ofs.to_bytes(4, 'little')
-
-  # MEC172x: authentication key select. Authentication not used, set to 0.
-  header[0x18] = 0
-
-  # header[0x19], header[0x20:0x28]
-  # header[0x1A:0x20] reserved 0
-  # MEC172x: supports SPI flash devices with drive strength settings
-  # TODO leave these fields at 0 for now. We must add 6 command line
-  # arguments.
-
-  # header[0x28:0x48] reserve can be any value
-  # header[0x48:0x50] Customer use. TODO
-  # authentication disabled, leave these 0.
-  # header[0x50:0x80] ECDSA P384 Authentication Public key Rx
-  # header[0x80:0xB0] ECDSA P384 Authentication Public key Ry
-
-  # header[0xB0:0xE0] = SHA384(header[0:0xB0])
-  header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
-  # When ECDSA authentication is disabled MCHP SPI image generator
-  # is filling the last 48 bytes of the Header with 0xff
-  header[-48:] = b'\xff' * 48
-
-  debug_print("After hash: len(header) = ", len(header))
-
-  return header
-
-#
-# MEC172x 128-byte EC Info Block appended to end of padded FW binary.
-# Python slice notation
-# byte[0:0x64] are undefined, we set to 0xFF
-# byte[0x64] = FW Build LSB
-# byte[0x65] = FW Build MSB
-# byte[0x66:0x68] = undefined, set to 0xFF
-# byte[0x68:0x78] = Roll back permissions bit maps
-# byte[0x78:0x7c] = key revocation bit maps
-# byte[0x7c] = platform ID LSB
-# byte[0x7d] = platform ID MSB
-# byte[0x7e] = auto-rollback protection enable
-# byte[0x7f] = current imeage revision
-#
-def GenEcInfoBlock(args, chip_dict):
-  # ecinfo = bytearray([0xff] * chip_dict["EC_INFO_BLK_SZ"])
-  ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
-  return ecinfo
-
-#
-# Generate SPI FW image co-signature.
-# MEC172x cosignature is 96 bytes used by OEM FW
-# developer to sign their binary with ECDSA-P384-SHA384 or
-# some other signature algorithm that fits in 96 bytes.
-# At this time Cros-EC is not using this field, fill with 0xFF.
-# If this feature is implemented we need to read the OEM's
-# generated signature from a file and extract the binary
-# signature.
-#
-def GenCoSignature(args, chip_dict, payload):
-    return bytearray(b'\xff' * chip_dict["COSIG_SZ"])
-
-#
-# Generate SPI FW Image trailer.
-# MEC172x: Size = 160 bytes
-#   binary = payload || encryption_key_header || ec_info_block || cosignature
-#   trailer[0:48] = SHA384(binary)
-#   trailer[48:144] = 0xFF
-#   trailer[144:160] = 0xFF. Boot-ROM spec. says these bytes should be random.
-#       Authentication & encryption are not used therefore random data
-#       is not necessary.
-def GenTrailer(args, chip_dict, payload, encryption_key_header,
-               ec_info_block, cosignature):
-    debug_print("GenTrailer SHA384 computation")
-    trailer = bytearray(chip_dict["TAILER_PAD_BYTE"] * chip_dict["TRAILER_SZ"])
-    hasher = hashlib.sha384()
-    hasher.update(payload)
-    debug_print("  Update: payload len=0x{0:0x}".format(len(payload)))
-    if ec_info_block != None:
-      hasher.update(ec_info_block)
-      debug_print("  Update: ec_info_block len=0x{0:0x}".format(len(ec_info_block)))
-    if encryption_key_header != None:
-      hasher.update(encryption_key_header)
-      debug_print("  Update: encryption_key_header len=0x{0:0x}".format(len(encryption_key_header)))
-    if cosignature != None:
-      hasher.update(cosignature)
-      debug_print("  Update: cosignature len=0x{0:0x}".format(len(cosignature)))
-    trailer[0:48] = hasher.digest()
-    trailer[-16:] = 16 * b'\xff'
-
-    return trailer
-
-# MEC172x supports two 32-bit Tags located at offsets 0x0 and 0x4
-# in the SPI flash.
-# Tag format:
-#   bits[23:0] correspond to bits[31:8] of the Header SPI address
-#       Header is always on a 256-byte boundary.
-#   bits[31:24] = CRC8-ITU of bits[23:0].
-# Notice there is no chip-select field in the Tag both Tag's point
-# to the same flash part.
-#
-def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
-
-def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
-    tag.append(Crc8(0, tag))
-    return tag
-
-
-# FlashMap is an option for MEC172x
-# It is a 32 bit structure
-# bits[18:0] = bits[30:12] of second SPI flash base address
-# bits[23:19] = 0 reserved
-# bits[31:24] = CRC8 of bits[23:0]
-# Input:
-#   integer containing base address of second SPI flash
-#   This value is usually equal to the size of the first
-#   SPI flash and should be a multiple of 4KB
-# Output:
-#   bytearray of length 4
-def BuildFlashMap(secondSpiFlashBaseAddr):
-  flashmap = bytearray(4)
-  flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xff
-  flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xff
-  flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xff
-  flashmap[3] = Crc8(0, flashmap)
-  return flashmap
-
-#
-# Creates temporary file for read/write
-# Reads binary file containing LFW image_size (loader_file)
-# Writes LFW image to temporary file
-# Reads RO image at beginning of rorw_file up to image_size
-#  (assumes RO/RW images have been padded with 0xFF
-# Returns temporary file name
-#
-def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-
-  return fo.name
-
-#
-# Generate a test EC_RW image of same size
-# as original.
-# Preserve image_data structure and fill all
-# other bytes with 0xA5.
-# useful for testing SPI read and EC build
-# process hash generation.
-#
-def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
-
-def parseargs():
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("--load_addr", type=int,
-                      help="EC SRAM load address",
-                      default=0xC0000)
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash. Must be on a 256 byte boundary",
-                      default=0x0100)
-  parser.add_argument("--lfw_loc", type=int,
-                      help="Location of LFW in SPI flash. Must be on a 4KB boundary",
-                      default=0x1000)
-  parser.add_argument("--lfw_size", type=int,
-                      help="LFW size in bytes",
-                      default=0x1000)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, 0x3B, or 0x6B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 244KB",
-                      default=(244 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-  parser.add_argument("--tag0_loc", type=int,
-                      help="MEC172x TAG0 SPI offset",
-                      default=0)
-  parser.add_argument("--tag1_loc", type=int,
-                      help="MEC172x TAG1 SPI offset",
-                      default=4)
-  parser.add_argument("--spi_drive_str", type=int,
-                      help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
-                      default=4)
-  parser.add_argument("--spi_slew_fast", action='store_true',
-                      help="SPI use fast slew rate. Default is False",
-                      default=False)
-  parser.add_argument("--spi_cpol", type=int,
-                      help="SPI clock polarity when idle. Defealt is 0(low)",
-                      default=0)
-  parser.add_argument("--spi_cpha_mosi", type=int,
-                      help="""SPI clock phase controller drives data.
-                              0=Data driven on active to inactive clock edge,
-                              1=Data driven on inactive to active clock edge""",
-                      default=0)
-  parser.add_argument("--spi_cpha_miso", type=int,
-                      help="""SPI clock phase controller samples data.
-                              0=Data sampled on inactive to active clock edge,
-                              1=Data sampled on active to inactive clock edge""",
-                      default=0)
-
-  return parser.parse_args()
-
-def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".load_addr", hex(args.load_addr))
-  debug_print(".tag0_loc = ", hex(args.tag0_loc))
-  debug_print(".tag1_loc = ", hex(args.tag1_loc))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  debug_print(".lfw_loc = ", hex(args.lfw_loc))
-  debug_print(".lfw_size = ", hex(args.lfw_size))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock (MHz) = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".test_ecrw = ", args.test_ecrw)
-  debug_print(".verbose = ", args.verbose)
-  debug_print(".spi_drive_str = ", args.spi_drive_str)
-  debug_print(".spi_slew_fast = ", args.spi_slew_fast)
-  debug_print(".spi_cpol = ", args.spi_cpol)
-  debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
-  debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
-
-def spi_list_append(mylist, loc, data, description):
-  """Append SPI data block tuple to list"""
-  t = (loc, data, description)
-  mylist.append(t)
-  debug_print("Add SPI entry: offset=0x{0:08x} len=0x{1:0x} descr={2}".format(loc, len(data), description))
-
-#
-# Handle quiet mode build from Makefile
-# Quiet mode when V is unset or V=0
-# Verbose mode when V=1
-#
-# MEC172x SPI Image Generator
-# No authentication
-# No payload encryption
-#
-# SPI Offset 0x0 = TAG0 points to Header for EC-RO FW
-# SPI Offset 0x4 = TAG1 points to Header for EC-RO FW
-# TAG Size = 4 bytes
-#  bits[23:0] = bits[31:8] of Header SPI offset
-#  bits[31:24] = CRC8-ITU checksum of bits[23:0].
-#
-# MEC172x SPI header and payload layout for minimum size
-# header offset aligned on 256 byte boundary
-# header_spi_address:
-#   header[0:0x4F] = Header data
-#   header[0x50:0x80] = ECDSA-P384 public key x for Header authentication
-#   header[0x80:0xB0] = ECDSA-P384 public key y for Header authentication
-#   header[0xB0:0xE0] = SHA384 digest of header[0:0xB0]
-#   header[0xE0:0x110] = ECDSA-P384-SHA384 Signature.R of header[0:0xB0]
-#   header[0x110:0x140] = ECDSA-P384-SHA384 Signature.S of header[0:0xB0]
-# payload_spi_address = header_spi_address + len(Header)
-#       Payload had been padded such that len(padded_payload) % 128 == 0
-#   padded_payload[padded_payload_len]
-# payload_signature_address = payload_spi_address + len(padded_payload)
-#  payload_encryption_key_header[128] Not present if encryption disabled
-#  payload_cosignature[96] = 0 if Authentication is disabled
-#  payload_trailer[160] = SHA384(padded_payload ||
-#                                optional payload_encryption_key_header)
-#                       || 48 * [0]
-#                       || 48 * [0]
-#
-def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
-
-  debug_print("Begin pack_ec_mec172x.py script")
-
-  print_args(args)
-
-  chip_dict = MEC172X_DICT
-
-  # Boot-ROM requires header location aligned >= 256 bytes.
-  # CrOS EC flash image update code requires EC_RO/RW location to be aligned
-  # on a flash erase size boundary and EC_RO/RW size to be a multiple of
-  # the smallest flash erase block size.
-
-  spi_size = args.spi_size * 1024
-  spi_image_size = spi_size // 2
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
-
-  lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"])
-  lfw_ecro_len = len(lfw_ecro)
-  debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
-
-  # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4]))
-      crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder='little')
-      lfw_ecro[-4:] = crc32_ecro_bytes
-      debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE))
-      debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
-
-  # Reads entry point from offset 4 of file.
-  # This assumes binary has Cortex-M4 vector table at offset 0.
-  # 32-bit word at offset 0x0 initial stack pointer value
-  # 32-bit word at offset 0x4 address of reset handler
-  # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
-  lfw_ecro_entry = GetEntryPoint(rorofile)
-  debug_print("LFW Entry point from GetEntryPoint = 0x{0:08x}".format(lfw_ecro_entry))
-
-  # Chromebooks are not using MEC BootROM SPI header/payload authentication
-  # or payload encryption. In this case the header authentication signature
-  # is filled with the hash digest of the respective entity.
-  # BuildHeader2 computes the hash digest and stores it in the correct
-  # header location.
-  header = BuildHeader2(args, chip_dict, lfw_ecro_len,
-                        args.load_addr, lfw_ecro_entry)
-  printByteArrayAsHex(header, "Header(lfw_ecro)")
-
-  # If payload encryption used then encrypt payload and
-  # generate Payload Key Header. If encryption not used
-  # payload is not modified and the method returns None
-  encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(encryption_key_header,
-                      "LFW + EC_RO encryption_key_header")
-
-  ec_info_block = GenEcInfoBlock(args, chip_dict)
-  printByteArrayAsHex(ec_info_block, "EC Info Block")
-
-  cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
-
-  trailer = GenTrailer(args, chip_dict, lfw_ecro, encryption_key_header,
-                       ec_info_block, cosignature)
-
-  printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
-
-  # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
-  tag0 = BuildTag(args)
-  tag1 = tag0
-
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  ecrw = GetPayloadFromOffset(args.input, args.image_size,
-                              chip_dict["PAD_SIZE"])
-  debug_print("type(ecrw) is ", type(ecrw))
-  debug_print("len(ecrw) is ", hex(len(ecrw)))
-
-  # truncate to args.image_size
-  ecrw_len = len(ecrw)
-  if ecrw_len > args.image_size:
-      debug_print("Truncate EC_RW len={0:0x} to image_size={1:0x}".format(ecrw_len,args.image_size))
-      ecrw = ecrw[:args.image_size]
-      ecrw_len = len(ecrw)
-
-  debug_print("len(EC_RW) = ", hex(ecrw_len))
-
-  # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
-      crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder='little')
-      ecrw[-4:] = crc32_ecrw_bytes
-      debug_print("ecrw len = ", hex(len(ecrw)))
-      debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
-
-  # Assume FW layout is standard Cortex-M style with vector
-  # table at start of binary.
-  # 32-bit word at offset 0x0 = Initial stack pointer
-  # 32-bit word at offset 0x4 = Address of reset handler
-  ecrw_entry_tuple = struct.unpack_from('<I', ecrw, 4)
-  debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
-
-  ecrw_entry = ecrw_entry_tuple[0]
-  debug_print("ecrw_entry = ", hex(ecrw_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(ecrw)
-
-  os.remove(rorofile)           # clean up the temp file
-
-  spi_list = []
-
-  # MEC172x Add TAG's
-  #spi_list.append((args.tag0_loc, tag0, "tag0"))
-  #spi_list.append((args.tag1_loc, tag1, "tag1"))
-  spi_list_append(spi_list, args.tag0_loc, tag0, "TAG0")
-  spi_list_append(spi_list, args.tag1_loc, tag1, "TAG1")
-
-  # Boot-ROM SPI image header for LFW+EC-RO
-  #spi_list.append((args.header_loc, header, "header(lfw + ro)"))
-  spi_list_append(spi_list, args.header_loc, header, "LFW-EC_RO Header")
-
-  spi_list_append(spi_list, args.lfw_loc, lfw_ecro, "LFW-EC_RO FW")
-
-  offset = args.lfw_loc + len(lfw_ecro)
-  debug_print("SPI offset after LFW_ECRO = 0x{0:08x}".format(offset))
-
-  if ec_info_block != None:
-    spi_list_append(spi_list, offset, ec_info_block, "LFW-EC_RO Info Block")
-    offset += len(ec_info_block)
-
-  debug_print("SPI offset after ec_info_block = 0x{0:08x}".format(offset))
-
-  if cosignature != None:
-    #spi_list.append((offset, co-signature, "ECRO Co-signature"))
-    spi_list_append(spi_list, offset, cosignature, "LFW-EC_RO Co-signature")
-    offset += len(cosignature)
-
-  debug_print("SPI offset after co-signature = 0x{0:08x}".format(offset))
-
-  if trailer != None:
-    #spi_list.append((offset, trailer, "ECRO Trailer"))
-    spi_list_append(spi_list, offset, trailer, "LFW-EC_RO trailer")
-    offset += len(trailer)
-
-  debug_print("SPI offset after trailer = 0x{0:08x}".format(offset))
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  #spi_list.append((rw_offset, ecrw, "ecrw"))
-  spi_list_append(spi_list, rw_offset, ecrw, "EC_RW")
-  offset = rw_offset + len(ecrw)
-
-  spi_list = sorted(spi_list)
-
-  debug_print("Display spi_list:")
-  dumpsects(spi_list)
-
-  #
-  # MEC172x Boot-ROM locates TAG0/1 at SPI offset 0
-  # instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
-
-    f.flush()
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/mchp/watchdog.c b/chip/mchp/watchdog.c
deleted file mode 100644
index b8f986f5cd..0000000000
--- a/chip/mchp/watchdog.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "watchdog.h"
-#include "tfdp_chip.h"
-
-void watchdog_reload(void)
-{
-	MCHP_WDG_KICK = 1;
-
-	if (IS_ENABLED(CONFIG_WATCHDOG_HELP)) {
-		/* Reload the auxiliary timer */
-		MCHP_TMR16_CTL(0) &= ~BIT(5);
-		MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-		MCHP_TMR16_CTL(0) |= BIT(5);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-#if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X)
-static void wdg_intr_enable(int enable)
-{
-	if (enable) {
-		MCHP_WDG_STATUS = MCHP_WDG_STS_IRQ;
-		MCHP_WDG_IEN = MCHP_WDG_IEN_IRQ_EN;
-		MCHP_WDG_CTL |= MCHP_WDG_RESET_IRQ_EN;
-		MCHP_INT_ENABLE(MCHP_WDG_GIRQ) = MCHP_WDG_GIRQ_BIT;
-		task_enable_irq(MCHP_IRQ_WDG);
-	} else {
-		MCHP_WDG_IEN = 0U;
-		MCHP_WDG_CTL &= ~(MCHP_WDG_RESET_IRQ_EN);
-		MCHP_INT_DISABLE(MCHP_WDG_GIRQ) = MCHP_WDG_GIRQ_BIT;
-		task_disable_irq(MCHP_IRQ_WDG);
-	}
-}
-#else
-static void wdg_intr_enable(int enable)
-{
-	(void) enable;
-}
-#endif
-
-
-/*
- * MEC1701 WDG asserts chip reset on LOAD count expiration.
- * WDG interrupt is simulated using a 16-bit general purpose
- * timer whose period is sufficiently less that the WDG timeout
- * period allowing watchdog trace data to be saved.
- *
- * MEC152x adds interrupt capability to the WDT.
- * Enable MEC152x WDG interrupt. WDG event will assert
- * IRQ and kick itself starting another LOAD timeout.
- * After the new LOAD expires WDG will assert chip reset.
- * The WDG ISR calls watchdog trace save API, upon return we
- * enter a spin loop waiting for the LOAD period to expire.
- * WDG does not have a way to trigger an immediate reset except
- * by re-programming it.
- */
-int watchdog_init(void)
-{
-	if (IS_ENABLED(CONFIG_WATCHDOG_HELP)) {
-		/*
-		 * MEC170x Watchdog does not warn us before expiring.
-		 * Let's use a 16-bit timer as an auxiliary timer.
-		 */
-
-		/* Clear 16-bit basic timer 0 PCR sleep enable */
-		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BTMR16_0);
-
-		/* Stop the auxiliary timer if it's running */
-		MCHP_TMR16_CTL(0) &= ~BIT(5);
-
-		/* Enable auxiliary timer */
-		MCHP_TMR16_CTL(0) |= BIT(0);
-
-		/* Prescaler = 48000 -> 1kHz -> Period = 1 ms */
-		MCHP_TMR16_CTL(0) = (MCHP_TMR16_CTL(0) & 0xffffU)
-					| (47999 << 16);
-
-		/* No auto restart */
-		MCHP_TMR16_CTL(0) &= ~BIT(3);
-
-		/* Count down */
-		MCHP_TMR16_CTL(0) &= ~BIT(2);
-
-		/* Enable interrupt from auxiliary timer */
-		MCHP_TMR16_IEN(0) |= BIT(0);
-		task_enable_irq(MCHP_IRQ_TIMER16_0);
-		MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
-
-		/* Load and start the auxiliary timer */
-		MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-		MCHP_TMR16_CNT(0) |= BIT(5);
-	}
-
-	MCHP_WDG_CTL = 0;
-
-	/* Clear WDT PCR sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_WDT);
-
-	/* Set timeout. It takes 1007 us to decrement WDG_CNT by 1. */
-	MCHP_WDG_LOAD = CONFIG_WATCHDOG_PERIOD_MS * 1000 / 1007;
-
-	wdg_intr_enable(1);
-
-	/*
-	 * Start watchdog
-	 * If chipset debug build enable feature to prevent watchdog from
-	 * counting if a debug cable is attached to JTAG_RST#.
-	 */
-	if (IS_ENABLED(CONFIG_CHIPSET_DEBUG))
-		MCHP_WDG_CTL |= (MCHP_WDT_CTL_ENABLE
-			| MCHP_WDT_CTL_JTAG_STALL_EN);
-	else
-		MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE;
-
-	return EC_SUCCESS;
-}
-
-/* MEC152x Watchdog can fire an interrupt to CPU before system reset */
-#if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X)
-
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	/* Clear WDG first then aggregator */
-	MCHP_WDG_STATUS = MCHP_WDG_STS_IRQ;
-	MCHP_INT_SOURCE(MCHP_WDG_GIRQ) = MCHP_WDG_GIRQ_BIT;
-
-	/* Cause WDG to reload again. */
-	MCHP_WDG_KICK = 1;
-
-	watchdog_trace(excep_lr, excep_sp);
-
-	/* Reset system by re-programing WDT to trigger after 2 32KHz clocks */
-	MCHP_WDG_CTL = 0; /* clear enable to allow write to load register */
-	MCHP_WDG_LOAD = 2;
-	MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE;
-
-}
-
-/* ISR for watchdog warning naked will keep SP & LR */
-void
-IRQ_HANDLER(MCHP_IRQ_WDG)(void) __keep __attribute__((naked));
-void IRQ_HANDLER(MCHP_IRQ_WDG)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-			"mov r1, sp\n"
-			/*
-			 * Must push registers in pairs to keep 64-bit aligned
-			 * stack for ARM EABI.  This also conveniently saves
-			 * R0=LR so we can pass it to task_resched_if_needed.
-			 */
-			"push {r0, lr}\n"
-			"bl watchdog_check\n"
-			"pop {r0, lr}\n"
-			"b task_resched_if_needed\n");
-}
-
-/* put the watchdog at the highest priority */
-const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_WDG)
-__attribute__((section(".rodata.irqprio")))
-= {MCHP_IRQ_WDG, 0};
-
-#else
-/*
- * MEC1701 watchdog only resets. Use a 16-bit timer to fire in interrupt
- * for saving watchdog trace.
- */
-#ifdef CONFIG_WATCHDOG_HELP
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	/* Clear status */
-	MCHP_TMR16_STS(0) |= 1;
-	/* clear aggregator status */
-	MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void
-IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) __keep __attribute__((naked));
-void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /*
-		      * Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveniently saves
-		      * R0=LR so we can pass it to task_resched_if_needed.
-		      */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0, lr}\n"
-		     "b task_resched_if_needed\n");
-}
-
-/* Put the watchdog at the highest interrupt priority. */
-const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_TIMER16_0)
-	__attribute__((section(".rodata.irqprio")))
-		= {MCHP_IRQ_TIMER16_0, 0};
-
-#endif /* #ifdef CONFIG_WATCHDOG_HELP */
-#endif /* #if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X) */
diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c
deleted file mode 100644
index 95fe99f891..0000000000
--- a/chip/mec1322/adc.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/*
- * Conversion on a single channel takes less than 12 ms. Set timeout to
- * 15 ms so that we have a 3-ms margin.
- */
-#define ADC_SINGLE_READ_TIME 15000
-
-struct mutex adc_lock;
-
-static volatile task_id_t task_waiting;
-
-static int start_single_and_wait(int timeout)
-{
-	int event;
-
-	task_waiting = task_get_current();
-
-	/* Start conversion */
-	MEC1322_ADC_CTRL |= BIT(1);
-
-	/* Wait for interrupt */
-	event = task_wait_event(timeout);
-	task_waiting = TASK_ID_INVALID;
-	return event != TASK_EVENT_TIMER;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-
-	mutex_lock(&adc_lock);
-
-	MEC1322_ADC_SINGLE = 1 << adc->channel;
-
-	if (start_single_and_wait(ADC_SINGLE_READ_TIME))
-		value = MEC1322_ADC_READ(adc->channel) * adc->factor_mul /
-			adc->factor_div + adc->shift;
-	else
-		value = ADC_READ_ERROR;
-
-	mutex_unlock(&adc_lock);
-	return value;
-}
-
-static void adc_init(void)
-{
-	/* Activate ADC module */
-	MEC1322_ADC_CTRL |= BIT(0);
-
-	/* Enable interrupt */
-	task_waiting = TASK_ID_INVALID;
-	MEC1322_INT_ENABLE(17) |= BIT(10);
-	MEC1322_INT_BLK_EN |= BIT(17);
-	task_enable_irq(MEC1322_IRQ_ADC_SNGL);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
-
-void adc_interrupt(void)
-{
-	/* Clear interrupt status bit */
-	MEC1322_ADC_CTRL |= BIT(7);
-
-	if (task_waiting != TASK_ID_INVALID)
-		task_wake(task_waiting);
-}
-DECLARE_IRQ(MEC1322_IRQ_ADC_SNGL, adc_interrupt, 2);
diff --git a/chip/mec1322/adc_chip.h b/chip/mec1322/adc_chip.h
deleted file mode 100644
index a6425d6872..0000000000
--- a/chip/mec1322/adc_chip.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1322-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-};
-
-/* Minimum and maximum values returned by adc_read_channel(). */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 1023
-
-/* Just plain id mapping for code readability */
-#define MEC1322_ADC_CH(x) (x)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk
deleted file mode 100644
index 2b0c9cc229..0000000000
--- a/chip/mec1322/build.mk
+++ /dev/null
@@ -1,79 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# MEC1322 chip specific files build
-#
-
-# MEC1322 SoC has a Cortex-M4 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-ifeq ($(CONFIG_LTO),y)
-# Re-include the core's build.mk file so we can remove the lto flag.
-include core/$(CORE)/build.mk
-endif
-
-# Required chip modules
-chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o
-chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-chip-$(CONFIG_DMA)+=dma.o
-chip-$(CONFIG_SPI)+=spi.o
-
-# location of the scripts and keys used to pack the SPI flash image
-SCRIPTDIR:=./chip/${CHIP}/util
-
-# Allow SPI size to be overridden by board specific size, default to 256KB.
-CHIP_SPI_SIZE_KB?=256
-
-# Commands to convert $^ to $@.tmp
-cmd_obj_to_bin = $(OBJCOPY) --gap-fill=0xff -O binary $< $@.tmp1 ; \
-		 ${SCRIPTDIR}/pack_ec.py -o $@.tmp -i $@.tmp1 \
-		--loader_file $(mec1322-lfw-flat) \
-		--payload_key ${SCRIPTDIR}/rsakey_sign_payload.pem \
-		--header_key ${SCRIPTDIR}/rsakey_sign_header.pem \
-		--spi_size ${CHIP_SPI_SIZE_KB} \
-		--image_size $(_rw_size); rm -f $@.tmp1
-
-mec1322-lfw = chip/mec1322/lfw/ec_lfw
-mec1322-lfw-flat = $(out)/RW/$(mec1322-lfw)-lfw.flat
-
-# build these specifically for lfw with -lfw suffix
-objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \
-		$(addprefix common/, util gpio) \
-		$(addprefix chip/$(CHIP)/, spi dma gpio clock hwtimer) \
-		core/$(CORE)/cpu $(mec1322-lfw))
-
-# reuse version.o (and its dependencies) from main board
-objs_lfw += $(out)/RW/common/version.o
-
-dirs-y+=chip/$(CHIP)/lfw
-
-# objs with -lfw suffix are to include lfw's gpio
-$(out)/RW/%-lfw.o: private CC+=-I$(BDIR)/lfw -DLFW=$(EMPTY)
-# Remove the lto flag for the loader.  It actually causes it to bloat in size.
-ifeq ($(CONFIG_LTO),y)
-$(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU))
-endif
-$(out)/RW/%-lfw.o: %.c
-	$(call quiet,c_to_o,CC     )
-
-# let lfw's elf link only with selected objects
-$(out)/RW/%-lfw.elf: private objs = $(objs_lfw)
-$(out)/RW/%-lfw.elf: override shlib :=
-$(out)/RW/%-lfw.elf: %.ld $(objs_lfw)
-	$(call quiet,elf,LD     )
-
-# final image needs lfw loader
-$(out)/$(PROJECT).bin: $(mec1322-lfw-flat)
diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c
deleted file mode 100644
index ce07284891..0000000000
--- a/chip/mec1322/clock.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "vboot_hash.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Recovery time for HvySlp2 is 0 usec */
-#define HEAVY_SLEEP_RECOVER_TIME_USEC   75
-
-#define SET_HTIMER_DELAY_USEC           200
-
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t total_idle_dsleep_time_us;
-
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the heavy sleep mode is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-static int console_in_use_timeout_sec = 60;
-static timestamp_t console_expire_time;
-#endif /*CONFIG_LOW_POWER_IDLE */
-
-static int freq = 48000000;
-
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-void clock_init(void)
-{
-#ifdef CONFIG_CLOCK_CRYSTAL
-	/* XOSEL: 0 = Parallel resonant crystal */
-	MEC1322_VBAT_CE &= ~0x1;
-#else
-	/* XOSEL: 1 = Single ended clock source */
-	MEC1322_VBAT_CE |= 0x1;
-#endif
-
-	/* 32K clock enable */
-	MEC1322_VBAT_CE |= 0x2;
-
-#ifdef CONFIG_CLOCK_CRYSTAL
-	/* Wait for crystal to stabilize (OSC_LOCK == 1) */
-	while (!(MEC1322_PCR_CHIP_OSC_ID & 0x100))
-		;
-#endif
-}
-
-/**
- * Speed through boot + vboot hash calculation, dropping our processor clock
- * only after vboot hashing is completed.
- */
-static void clock_turbo_disable(void);
-DECLARE_DEFERRED(clock_turbo_disable);
-
-static void clock_turbo_disable(void)
-{
-#ifdef CONFIG_VBOOT_HASH
-	if (vboot_hash_in_progress())
-		hook_call_deferred(&clock_turbo_disable_data, 100 * MSEC);
-	else
-#endif
-		/* Use 12 MHz processor clock for power savings */
-		MEC1322_PCR_PROC_CLK_CTL = 4;
-}
-DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * initialization of Hibernation timer
- */
-static void htimer_init(void)
-{
-	MEC1322_INT_BLK_EN |= BIT(17);
-	MEC1322_INT_ENABLE(17) |= BIT(20);  /* GIRQ=17, aggregator bit = 20 */
-	MEC1322_HTIMER_PRELOAD = 0;  /* disable at beginning */
-
-	task_enable_irq(MEC1322_IRQ_HTIMER);
-}
-
-/**
- * Use hibernate module to set up an htimer interrupt at a given
- * time from now
- *
- * @param seconds      Number of seconds before htimer interrupt
- * @param microseconds Number of microseconds before htimer interrupt
- */
-static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	if (seconds || microseconds) {
-
-		if (seconds > 2) {
-			/* count from 2 sec to 2 hrs, mec1322 sec 18.10.2 */
-			ASSERT(seconds <= 0xffff / 8);
-			MEC1322_HTIMER_CONTROL = 1; /* 0.125(=1/8) per clock */
-			/* (number of counts to be loaded)
-			 * = seconds * ( 8 clocks per second )
-			 *   + microseconds / 125000
-			 *   ---> (0 if (microseconds < 125000)
-			 */
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 8 + microseconds / 125000);
-
-		} else { /* count up to 2 sec. */
-
-			MEC1322_HTIMER_CONTROL = 0; /* 30.5(= 2/61) usec */
-
-			/* (number of counts to be loaded)
-			 * = (total microseconds) / 30.5;
-			 */
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 1000000 + microseconds) * 2 / 61;
-		}
-	}
-}
-
-/**
- * return time slept in micro-seconds
- */
-static timestamp_t system_get_htimer(void)
-{
-	uint16_t count;
-	timestamp_t time;
-
-	count =  MEC1322_HTIMER_COUNT;
-
-
-	if (MEC1322_HTIMER_CONTROL == 1) /* if > 2 sec */
-		/* 0.125 sec per count */
-		time.le.lo = (uint32_t)(count * 125000);
-	else    /* if < 2 sec */
-		/* 30.5(=61/2)usec per count */
-		time.le.lo = (uint32_t)(count * 61 / 2);
-
-	time.le.hi = 0;
-
-	return time;  /* in uSec */
-}
-
-/**
- * Disable and clear hibernation timer interrupt
- */
-static void system_reset_htimer_alarm(void)
-{
-	MEC1322_HTIMER_PRELOAD = 0;
-}
-
-/**
- * This is mec1322 specific and equivalent to ARM Cortex's
- * 'DeepSleep' via system control block register, CPU_SCB_SYSCTRL
- */
-static void prepare_for_deep_sleep(void)
-{
-	uint32_t ec_slp_en = MEC1322_PCR_EC_SLP_EN |
-			     MEC1322_PCR_EC_SLP_EN_SLEEP;
-
-	/* sysTick timer */
-	CPU_NVIC_ST_CTRL &= ~ST_ENABLE;
-	CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG;
-
-	/* Disable JTAG */
-	MEC1322_EC_JTAG_EN &= ~1;
-	/* Power down ADC VREF, ADC_VREF overrides ADC_CTRL. */
-	MEC1322_EC_ADC_VREF_PD |= 1;
-
-	/* Stop watchdog */
-	MEC1322_WDG_CTL &= ~1;
-
-	/* Stop timers */
-	MEC1322_TMR32_CTL(0) &= ~1;
-	MEC1322_TMR32_CTL(1) &= ~1;
-	MEC1322_TMR16_CTL(0) &= ~1;
-
-	MEC1322_PCR_CHIP_SLP_EN |= 0x3;
-#ifdef CONFIG_PWM
-	if (pwm_get_keep_awake_mask())
-		ec_slp_en &= ~pwm_get_keep_awake_mask();
-	else
-#endif
-		/* Disable 100 Khz clock */
-		MEC1322_PCR_SLOW_CLK_CTL &= 0xFFFFFC00;
-
-	MEC1322_PCR_EC_SLP_EN = ec_slp_en;
-	MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
-	MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
-
-#ifndef CONFIG_POWER_S0IX
-	MEC1322_LPC_ACT = 0x0;
-#endif
-
-	MEC1322_PCR_SYS_SLP_CTL = 0x2;  /* heavysleep 2 */
-
-	CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */
-}
-
-static void resume_from_deep_sleep(void)
-{
-	CPU_NVIC_ST_CTRL |= ST_TICKINT; /* SYS_TICK_INT_ENABLE */
-	CPU_NVIC_ST_CTRL |= ST_ENABLE;
-
-	MEC1322_EC_JTAG_EN = 1;
-	MEC1322_EC_ADC_VREF_PD &= ~1;
-	/* ADC_VREF_PD overrides ADC_CTRL ! */
-
-	/* Enable timer */
-	MEC1322_TMR32_CTL(0) |= 1;
-	MEC1322_TMR32_CTL(1) |= 1;
-	MEC1322_TMR16_CTL(0) |= 1;
-
-	/* Enable watchdog */
-	MEC1322_WDG_CTL |= 1;
-
-	MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0;
-	MEC1322_PCR_CHIP_SLP_EN &= ~0x3;
-	MEC1322_PCR_EC_SLP_EN &= MEC1322_PCR_EC_SLP_EN_WAKE;
-	MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE;
-	MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE;
-
-	MEC1322_PCR_SYS_SLP_CTL = 0xF8;  /* default */
-
-#ifndef CONFIG_POWER_S0IX
-	/* Enable LPC */
-	MEC1322_LPC_ACT |= 1;
-#endif
-}
-
-
-void clock_refresh_console_in_use(void)
-{
-	disable_sleep(SLEEP_MASK_CONSOLE);
-
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-}
-
-/**
- * Low power idle task.  Executed when no tasks are ready to be scheduled.
- */
-void __idle(void)
-{
-	timestamp_t t0;
-	timestamp_t t1;
-	timestamp_t ht_t1;
-	uint32_t next_delay;
-	uint32_t max_sleep_time;
-	int time_for_dsleep;
-	int uart_ready_for_deepsleep;
-
-	htimer_init(); /* hibernation timer initialize */
-
-	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-
-
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	CPRINTS("low power idle task started");
-
-	while (1) {
-		/* Disable interrupts */
-		interrupt_disable();
-
-		t0 = get_time();  /* uSec */
-
-		/* __hw_clock_event_get() is next programmed timer event */
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		time_for_dsleep = next_delay > (HEAVY_SLEEP_RECOVER_TIME_USEC +
-						SET_HTIMER_DELAY_USEC);
-
-		max_sleep_time = next_delay - HEAVY_SLEEP_RECOVER_TIME_USEC;
-
-		/* check if there enough time for deep sleep */
-		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-
-
-			/*
-			 * Check if the console use has expired and console
-			 * sleep is masked by GPIO(UART-RX) interrupt.
-			 */
-			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-					t0.val > console_expire_time.val) {
-				/* allow console to sleep. */
-				enable_sleep(SLEEP_MASK_CONSOLE);
-
-				/*
-				 * Wait one clock before checking if heavy sleep
-				 * is allowed to give time for sleep mask
-				 * to be updated.
-				 */
-				clock_wait_cycles(1);
-
-				if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
-					CPRINTS("Disable console in deepsleep");
-			}
-
-
-			/* UART is not being used  */
-			uart_ready_for_deepsleep = LOW_SPEED_DEEP_SLEEP_ALLOWED
-						&& !uart_tx_in_progress()
-						&& uart_buffer_empty();
-
-			/*
-			 * Since MEC1322's heavysleep modes requires all block
-			 * to be sleepable, UART/console's readiness is final
-			 * decision factor of heavysleep of EC.
-			 */
-			if (uart_ready_for_deepsleep) {
-
-				idle_dsleep_cnt++;
-
-				/*
-				 * config UART Rx as GPIO wakeup interrupt
-				 * source
-				 */
-				uart_enter_dsleep();
-
-				/* MEC1322 specific deep-sleep mode */
-				prepare_for_deep_sleep();
-
-				/*
-				 * 'max_sleep_time' value should be big
-				 * enough so that hibernation timer's interrupt
-				 * triggers only after 'wfi' completes its
-				 * excution.
-				 */
-				max_sleep_time -= (get_time().le.lo - t0.le.lo);
-
-				/* setup/enable htimer wakeup interrupt */
-				system_set_htimer_alarm(0, max_sleep_time);
-			} else {
-				idle_sleep_cnt++;
-			}
-
-			/* Wait for interrupt: goes into deep sleep. */
-			asm("wfi");
-
-			if (uart_ready_for_deepsleep) {
-
-				resume_from_deep_sleep();
-
-				/*
-				 * Fast forward timer according to htimer
-				 * counter:
-				 * Since all blocks including timers will be in
-				 * sleep mode, timers stops except hibernate
-				 * timer.
-				 * And system schedule timer should be corrected
-				 * after wakeup by either hibernate timer or
-				 * GPIO_UART_RX interrupt.
-				 */
-				ht_t1 = system_get_htimer();
-
-				/* disable/clear htimer wakeup interrupt */
-				system_reset_htimer_alarm();
-
-				t1.val = t0.val +
-				       (uint64_t)(max_sleep_time - ht_t1.le.lo);
-
-				force_time(t1);
-
-				/* re-eanble UART */
-				uart_exit_dsleep();
-
-				/* Record time spent in deep sleep. */
-				total_idle_dsleep_time_us +=
-				       (uint64_t)(max_sleep_time - ht_t1.le.lo);
-			}
-
-		} else { /* CPU 'Sleep' mode */
-
-			idle_sleep_cnt++;
-
-			asm("wfi");
-
-		}
-
-		interrupt_enable();
-	} /* while(1) */
-}
-
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-
-	ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n",
-						total_idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* defined(CONFIG_CMD_IDLE_STATS) */
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use heavy sleep mode or
-			 * allow it to use the heavy sleep mode.
-			 */
-			if (v)  /* 'on' */
-				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else    /* 'off' */
-				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-			"[ on | off | <timeout> sec]",
-			"Deep sleep clock settings:\nUse 'on' to force deep "
-			"sleep NOT to enter heavysleep mode.\nUse 'off' to "
-			"allow deep sleep to use heavysleep whenever conditions"
-			"allow.\n"
-			"Give a timeout value for the console in use timeout.\n"
-			"See also 'sleepmask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
deleted file mode 100644
index 414fb492bf..0000000000
--- a/chip/mec1322/config_chip.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	93
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	2048
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
-
-/*
- * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
- * additional port.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-
-#define I2C_CONTROLLER_COUNT	4
-#define I2C_PORT_COUNT		5
-
-/****************************************************************************/
-/* Memory mapping */
-
-/*
- * The memory region for RAM is actually 0x00100000-0x00120000.
- * RAM for RO/RW = 20k
- * CODE size of the Loader is 3k
- * As per the above configuartion the upper 20k
- * is used to store data.The rest is for code.
- * the lower 107K is flash[ 3k Loader and 104k RO/RW],
- * and the higher 20K is RAM shared by loader and RO/RW.
- */
-
-/****************************************************************************/
-/* Define our RAM layout. */
-
-#define CONFIG_MEC_SRAM_BASE_START	0x00100000
-#define CONFIG_MEC_SRAM_BASE_END	0x00120000
-#define CONFIG_MEC_SRAM_SIZE		(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_MEC_SRAM_BASE_START)
-
-/* 20k RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE			0x00005000
-#define CONFIG_RAM_BASE			(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_RAM_SIZE)
-
-/* System stack size */
-#define CONFIG_STACK_SIZE		1024
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		512
-#define LARGER_TASK_STACK_SIZE		640
-
-#define CHARGER_TASK_STACK_SIZE		640
-#define HOOKS_TASK_STACK_SIZE		640
-#define CONSOLE_TASK_STACK_SIZE		640
-#define HOST_CMD_TASK_STACK_SIZE	640
-
-/*
- * TODO: Large stack consumption
- * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
- */
-#define PD_TASK_STACK_SIZE		800
-
-/* Default task stack size */
-#define TASK_STACK_SIZE			512
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
-/* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00001000
-/* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000004
-
-/* One page size for write */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256
-
-/* Program memory base address */
-#define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
-
-#include "config_flash_layout.h"
-
-/****************************************************************************/
-/* Customize the build */
-/* Optional features present on this chip */
-#if 0
-#define CONFIG_ADC
-#define CONFIG_PECI
-#define CONFIG_MPU
-#endif
-#define CONFIG_DMA
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_SPI
-#define CONFIG_SWITCH
-
-#define GPIO_PIN(index) (index / 10), (1 << (index % 10))
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h
deleted file mode 100644
index a5b064b8cc..0000000000
--- a/chip/mec1322/config_flash_layout.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
-#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
-
-/*
- * mec1322 flash layout:
- * - Non memory-mapped, external SPI.
- * - RW image at the beginning of writable region.
- * - Bootloader at the beginning of protected region, followed by RO image.
- * - Loader + (RO | RW) loaded into program memory.
- */
-
-/* Non-memmapped, external SPI */
-#define CONFIG_EXTERNAL_STORAGE
-#undef  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
-#define CONFIG_SPI_FLASH
-
-/* EC region of SPI resides at end of ROM, protected region follows writable */
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  (CONFIG_FLASH_SIZE_BYTES - 0x20000)
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (CONFIG_FLASH_SIZE_BYTES - 0x40000)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
-
-/* Loader resides at the beginning of program memory */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0xC00
-
-/* Write protect Loader and RO Image */
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-/*
- * Write protect 128k section of 256k physical flash which contains loader
- * and RO Images.
- */
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * RO / RW images follow the loader in program memory. Either RO or RW
- * image will be loaded -- both cannot be loaded at the same time.
- */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
-#define CONFIG_RO_SIZE			(97 * 1024)
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-
-/* WP region consists of second half of SPI, and begins with the boot header */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF	0
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE	0x240
-
-/* Loader / lfw image immediately follows the boot header on SPI */
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
-
-/* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
-
-/* RW image starts at the beginning of SPI */
-#define CONFIG_RW_STORAGE_OFF		0
-
-#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c
deleted file mode 100644
index a6c6fed5ad..0000000000
--- a/chip/mec1322/dma.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
-
-mec1322_dma_chan_t *dma_get_channel(enum dma_channel channel)
-{
-	mec1322_dma_regs_t *dma = MEC1322_DMA_REGS;
-
-	return &dma->chan[channel];
-}
-
-void dma_disable(enum dma_channel channel)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(channel);
-
-	if (chan->ctrl & BIT(0))
-		chan->ctrl &= ~BIT(0);
-
-	if (chan->act == 1)
-		chan->act = 0;
-}
-
-void dma_disable_all(void)
-{
-	int ch;
-	mec1322_dma_regs_t *dma;
-
-	for (ch = 0; ch < MEC1322_DMAC_COUNT; ch++) {
-		mec1322_dma_chan_t *chan = dma_get_channel(ch);
-		/* Abort any current transfer. */
-		chan->ctrl |= BIT(25);
-		/* Disable the channel. */
-		chan->ctrl &= ~BIT(0);
-		chan->act = 0;
-	}
-
-	/* Soft-reset the block. */
-	dma = MEC1322_DMA_REGS;
-	dma->ctrl |= 0x2;
-}
-
-/**
- * Prepare a channel for use and start it
- *
- * @param chan		Channel to read
- * @param count		Number of bytes to transfer
- * @param periph	Pointer to peripheral data register
- * @param memory	Pointer to memory address for receive/transmit
- * @param flags		DMA flags for the control register, normally:
- *				MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV for tx
- *				MEC1322_DMA_INC_MEM for rx
- */
-static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count,
-		void *periph, void *memory, unsigned flags)
-{
-	int xfer_size = (flags >> 20) & 0x7;
-
-	if (chan->ctrl & BIT(0))
-		chan->ctrl &= ~BIT(0);
-
-	chan->act |= 0x1;
-	chan->dev = (uint32_t)periph;
-	chan->mem_start = MEC1322_RAM_ALIAS((uint32_t)memory);
-	chan->mem_end = MEC1322_RAM_ALIAS((uint32_t)memory) + xfer_size * count;
-	chan->ctrl = flags;
-}
-
-void dma_go(mec1322_dma_chan_t *chan)
-{
-	/* Flush data in write buffer so that DMA can get the latest data */
-	asm volatile("dsb;");
-
-	/* Fire it up */
-	chan->ctrl |= MEC1322_DMA_RUN;
-}
-
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
-		    const void *memory)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(option->channel);
-
-	/*
-	 * Cast away const for memory pointer; this is ok because we know
-	 * we're preparing the channel for transmit.
-	 */
-	prepare_channel(chan, count, option->periph, (void *)memory,
-			MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV |
-			MEC1322_DMA_DEV(option->channel) | option->flags);
-}
-
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
-{
-	mec1322_dma_chan_t *chan;
-
-	chan = dma_get_channel(option->channel);
-
-	prepare_channel(chan, count, option->periph, memory,
-			MEC1322_DMA_INC_MEM | MEC1322_DMA_DEV(option->channel) |
-			option->flags);
-	dma_go(chan);
-}
-
-int dma_bytes_done(mec1322_dma_chan_t *chan, int orig_count)
-{
-	int xfer_size = (chan->ctrl >> 20) & 0x7;
-
-	return orig_count - (chan->mem_end - chan->mem_start) / xfer_size;
-}
-
-bool dma_is_enabled(mec1322_dma_chan_t *chan)
-{
-	return (chan->ctrl & MEC1322_DMA_RUN);
-}
-
-void dma_init(void)
-{
-	mec1322_dma_regs_t *dma = MEC1322_DMA_REGS;
-	dma->ctrl |= 0x1;
-}
-
-int dma_wait(enum dma_channel channel)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(channel);
-	timestamp_t deadline;
-
-	if (chan->act == 0)
-		return EC_SUCCESS;
-
-	deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
-	while (!(chan->int_status & 0x4)) {
-		if (deadline.val <= get_time().val)
-			return EC_ERROR_TIMEOUT;
-
-		udelay(DMA_POLLING_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-void dma_clear_isr(enum dma_channel channel)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(channel);
-
-	chan->int_status |= 0x4;
-}
diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c
deleted file mode 100644
index 1f54389fc7..0000000000
--- a/chip/mec1322/fan.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1322 fan control module. */
-
-/* This assumes 2-pole fan. For each rotation, 5 edges are measured. */
-
-#include "fan.h"
-#include "registers.h"
-#include "util.h"
-
-/* Maximum tach reading/target value */
-#define MAX_TACH 0x1fff
-
-/* Tach target value for disable fan */
-#define FAN_OFF_TACH 0xfff8
-
-/*
- * RPM = (n - 1) * m * f * 60 / poles / TACH
- *   n = number of edges = 5
- *   m = multiplier defined by RANGE = 2 in our case
- *   f = 32.768K
- *   poles = 2
- */
-#define RPM_TO_TACH(rpm) MIN((7864320 / MAX((rpm), 1)), MAX_TACH)
-#define TACH_TO_RPM(tach) (7864320 / MAX((tach), 1))
-
-static int rpm_setting;
-static int duty_setting;
-static int in_rpm_mode = 1;
-
-
-static void clear_status(void)
-{
-	/* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */
-	MEC1322_FAN_STATUS = 0x23;
-}
-
-void fan_set_enabled(int ch, int enabled)
-{
-	if (in_rpm_mode) {
-		if (enabled)
-			fan_set_rpm_target(ch, rpm_setting);
-		else
-			MEC1322_FAN_TARGET = FAN_OFF_TACH;
-	} else {
-		if (enabled)
-			fan_set_duty(ch, duty_setting);
-		else
-			MEC1322_FAN_SETTING = 0;
-	}
-	clear_status();
-}
-
-int fan_get_enabled(int ch)
-{
-	if (in_rpm_mode)
-		return (MEC1322_FAN_TARGET & 0xff00) != 0xff00;
-	else
-		return !!MEC1322_FAN_SETTING;
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	duty_setting = percent;
-	MEC1322_FAN_SETTING = percent * 255 / 100;
-	clear_status();
-}
-
-int fan_get_duty(int ch)
-{
-	return duty_setting;
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	return !!(MEC1322_FAN_CFG1 & BIT(7));
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	if (rpm_mode)
-		MEC1322_FAN_CFG1 |= BIT(7);
-	else
-		MEC1322_FAN_CFG1 &= ~BIT(7);
-	clear_status();
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	if ((MEC1322_FAN_READING >> 8) == 0xff)
-		return 0;
-	else
-		return TACH_TO_RPM(MEC1322_FAN_READING >> 3);
-}
-
-int fan_get_rpm_target(int ch)
-{
-	return rpm_setting;
-}
-
-void fan_set_rpm_target(int ch, int rpm)
-{
-	rpm_setting = rpm;
-	MEC1322_FAN_TARGET = RPM_TO_TACH(rpm) << 3;
-	clear_status();
-}
-
-enum fan_status fan_get_status(int ch)
-{
-	uint8_t sts = MEC1322_FAN_STATUS;
-
-	if (sts & (BIT(5) | BIT(1)))
-		return FAN_STATUS_FRUSTRATED;
-	if (fan_get_rpm_actual(ch) == 0)
-		return FAN_STATUS_STOPPED;
-	return FAN_STATUS_LOCKED;
-}
-
-int fan_is_stalled(int ch)
-{
-	uint8_t sts = MEC1322_FAN_STATUS;
-	if (fan_get_rpm_actual(ch)) {
-		MEC1322_FAN_STATUS = 0x1;
-		return 0;
-	}
-	return sts & 0x1;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	/*
-	 * Fan configuration 1 register:
-	 *   0x80 = bit 7    = RPM mode (0x00 if FAN_USE_RPM_MODE not set)
-	 *   0x20 = bits 6:5 = min 1000 RPM, multiplier = 2
-	 *   0x08 = bits 4:3 = 5 edges, 2 poles
-	 *   0x03 = bits 2:0 = 400 ms update time
-	 *
-	 * Fan configuration 2 register:
-	 *   0x00 = bit 6    = Ramp control disabled
-	 *   0x00 = bit 5    = Glitch filter enabled
-	 *   0x18 = bits 4:3 = Using both derivative options
-	 *   0x02 = bits 2:1 = error range is 50 RPM
-	 *   0x00 = bits 0   = normal polarity
-	 */
-	if (flags & FAN_USE_RPM_MODE)
-		MEC1322_FAN_CFG1 = 0xab;
-	else
-		MEC1322_FAN_CFG1 = 0x2b;
-	MEC1322_FAN_CFG2 = 0x1a;
-	clear_status();
-}
diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c
deleted file mode 100644
index fac5b08d8f..0000000000
--- a/chip/mec1322/flash.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "host_command.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "system.h"
-#include "util.h"
-#include "hooks.h"
-
-#define PAGE_SIZE 256
-
-#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
-#define FLASH_HOOK_VERSION 1
-
-static int entire_flash_locked;
-
-/* The previous write protect state before sys jump */
-
-struct flash_wp_state {
-	int entire_flash_locked;
-};
-
-/**
- * Read from physical flash.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Destination buffer for data.
- */
-int crec_flash_physical_read(int offset, int size, char *data)
-{
-	return spi_flash_read(data, offset, size);
-}
-
-/**
- * Write to physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Data to write to flash.  Must be 32-bit aligned.
- */
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int ret = EC_SUCCESS;
-	int  i, write_size;
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	for (i = 0; i < size; i += write_size) {
-		write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE);
-		ret = spi_flash_write(offset + i,
-				      write_size,
-				      (uint8_t *)data + i);
-		if (ret != EC_SUCCESS)
-			break;
-	}
-	return ret;
-}
-
-/**
- * Erase physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE.
- *
- * @param offset        Flash offset to erase.
- * @param size          Number of bytes to erase.
- */
-int crec_flash_physical_erase(int offset, int size)
-{
-	int ret;
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	ret = spi_flash_erase(offset, size);
-	return ret;
-}
-
-/**
- * Read physical write protect setting for a flash bank.
- *
- * @param bank    Bank index to check.
- * @return        non-zero if bank is protected until reboot.
- */
-int crec_flash_physical_get_protect(int bank)
-{
-	return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE,
-			CONFIG_FLASH_BANK_SIZE);
-}
-
-/**
- * Protect flash now.
- *
- * This is always successful, and only emulates "now" protection
- *
- * @param all      Protect all (=1) or just read-only
- * @return         non-zero if error.
- */
-int crec_flash_physical_protect_now(int all)
-{
-	if (all)
-		entire_flash_locked = 1;
-
-	/*
-	 * RO "now" protection is not currently implemented. If needed, it
-	 * can be added by splitting the entire_flash_locked variable into
-	 * and RO and RW vars, and setting + checking the appropriate var
-	 * as required.
-	 */
-	return EC_SUCCESS;
-}
-
-/**
- * Return flash protect state flags from the physical layer.
- *
- * This should only be called by flash_get_protect().
- *
- * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	if (spi_flash_check_protect(CONFIG_WP_STORAGE_OFF,
-				    CONFIG_WP_STORAGE_SIZE)) {
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	if (entire_flash_locked)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return flags;
-}
-
-/**
- * Return the valid flash protect flags.
- *
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-/**
- * Return the writable flash protect flags.
- *
- * @param    cur_flags The current flash protect flags.
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-	enum spi_flash_wp wp_status = SPI_WP_NONE;
-
-	wp_status = spi_flash_check_wp();
-
-	if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE &&
-	   !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
-		ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-
-	if (!entire_flash_locked)
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-/**
- * Enable write protect for the specified range.
- *
- * Once write protect is enabled, it will stay enabled until HW PIN is
- * de-asserted and SRP register is unset.
- *
- * However, this implementation treats EC_FLASH_PROTECT_ALL_AT_BOOT as
- * EC_FLASH_PROTECT_RO_AT_BOOT but tries to remember if "all" region
- * is protected.
- *
- * @param new_flags to protect (only EC_FLASH_PROTECT_*_AT_BOOT are
- * taken care of)
- * @return              EC_SUCCESS, or nonzero if error.
- */
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int offset, size, ret;
-	enum spi_flash_wp flashwp = SPI_WP_NONE;
-
-	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
-			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
-		/* Clear protection */
-		offset = size = 0;
-		flashwp = SPI_WP_NONE;
-	} else {
-		if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-			entire_flash_locked = 1;
-
-		offset = CONFIG_WP_STORAGE_OFF;
-		size = CONFIG_WP_STORAGE_SIZE;
-		flashwp = SPI_WP_HARDWARE;
-	}
-
-	ret = spi_flash_set_protect(offset, size);
-	if (ret == EC_SUCCESS)
-		ret = spi_flash_set_wp(flashwp);
-	return ret;
-}
-
-/**
- * Initialize the module.
- *
- * Applies at-boot protection settings if necessary.
- */
-int crec_flash_pre_init(void)
-{
-	crec_flash_physical_restore_state();
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	int version, size;
-	const struct flash_wp_state *prev;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
-		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
-		if (prev && version == FLASH_HOOK_VERSION &&
-		    size == sizeof(*prev))
-			entire_flash_locked = prev->entire_flash_locked;
-		return 1;
-	}
-
-	return 0;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void flash_preserve_state(void)
-{
-	struct flash_wp_state state;
-
-	state.entire_flash_locked = entire_flash_locked;
-
-	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c
deleted file mode 100644
index 331022c87c..0000000000
--- a/chip/mec1322/gpio.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for MEC1322 */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-struct gpio_int_mapping {
-	int8_t girq_id;
-	int8_t port_offset;
-};
-
-/* Mapping from GPIO port to GIRQ info */
-static const struct gpio_int_mapping int_map[22] = {
-	{11, 0}, {11, 0}, {11, 0}, {11, 0},
-	{10, 4}, {10, 4}, {10, 4}, {-1, -1},
-	{-1, -1}, {-1, -1}, {9, 10}, {9, 10},
-	{9, 10}, {9, 10}, {8, 14}, {8, 14},
-	{8, 14}, {-1, -1}, {-1, -1}, {-1, -1},
-	{20, 20}, {20, 20}
-};
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int i;
-	uint32_t val;
-
-	while (mask) {
-		i = __builtin_ffs(mask) - 1;
-		val = MEC1322_GPIO_CTL(port, i);
-		val &= ~(BIT(12) | BIT(13));
-		/* mux_control = DEFAULT, indicates GPIO */
-		if (func > GPIO_ALT_FUNC_DEFAULT)
-			val |= (func & 0x3) << 12;
-		MEC1322_GPIO_CTL(port, i) = val;
-		mask &= ~BIT(i);
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-	uint32_t val;
-
-	if (mask == 0)
-		return 0;
-	i = GPIO_MASK_TO_NUM(mask);
-	val = MEC1322_GPIO_CTL(gpio_list[signal].port, i);
-
-	return (val & BIT(24)) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-
-	if (mask == 0)
-		return;
-	i = GPIO_MASK_TO_NUM(mask);
-
-	if (value)
-		MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16);
-	else
-		MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16);
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	int i;
-	uint32_t val;
-	while (mask) {
-		i = GPIO_MASK_TO_NUM(mask);
-		mask &= ~BIT(i);
-		val = MEC1322_GPIO_CTL(port, i);
-
-		/*
-		 * Select open drain first, so that we don't glitch the signal
-		 * when changing the line to an output.
-		 */
-		if (flags & GPIO_OPEN_DRAIN)
-			val |= BIT(8);
-		else
-			val &= ~BIT(8);
-
-		if (flags & GPIO_OUTPUT) {
-			val |= BIT(9);
-			val &= ~BIT(10);
-		} else {
-			val &= ~BIT(9);
-			val |= BIT(10);
-		}
-
-		/* Handle pullup / pulldown */
-		if (flags & GPIO_PULL_UP)
-			val = (val & ~0x3) | 0x1;
-		else if (flags & GPIO_PULL_DOWN)
-			val = (val & ~0x3) | 0x2;
-		else
-			val &= ~0x3;
-
-		/* Set up interrupt */
-		if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING))
-			val |= BIT(7);
-		else
-			val &= ~BIT(7);
-
-		val &= ~(0x7 << 4);
-
-		if ((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING))
-			val |= 0x7 << 4;
-		else if (flags & GPIO_INT_F_RISING)
-			val |= 0x5 << 4;
-		else if (flags & GPIO_INT_F_FALLING)
-			val |= 0x6 << 4;
-		else if (flags & GPIO_INT_F_HIGH)
-			val |= 0x1 << 4;
-		else if (!(flags & GPIO_INT_F_LOW)) /* No interrupt flag set */
-			val |= 0x4 << 4;
-
-		/* Set up level */
-		if (flags & GPIO_HIGH)
-			val |= BIT(16);
-		else if (flags & GPIO_LOW)
-			val &= ~BIT(16);
-
-		MEC1322_GPIO_CTL(port, i) = val;
-	}
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id, bit_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-	bit_id = (port - int_map[port].port_offset) * 8 + i;
-
-	MEC1322_INT_ENABLE(girq_id) |= BIT(bit_id);
-	MEC1322_INT_BLK_EN |= BIT(girq_id);
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id, bit_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-	bit_id = (port - int_map[port].port_offset) * 8 + i;
-
-	MEC1322_INT_DISABLE(girq_id) = BIT(bit_id);
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id, bit_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-	bit_id = (port - int_map[port].port_offset) * 8 + i;
-
-	/* Clear interrupt source sticky status bit even if not enabled */
-	MEC1322_INT_SOURCE(girq_id) |= 1 << bit_id;
-
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	int i;
-	int flags;
-	int is_warm = system_is_reboot_warm();
-	const struct gpio_info *g = gpio_list;
-
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-}
-
-/* Clear any interrupt flags before enabling GPIO interrupt */
-#define ENABLE_GPIO_GIRQ(x) \
-	do { \
-		MEC1322_INT_SOURCE(x) |= MEC1322_INT_RESULT(x); \
-		task_enable_irq(MEC1322_IRQ_GIRQ ## x); \
-	} while (0)
-
-static void gpio_init(void)
-{
-	ENABLE_GPIO_GIRQ(8);
-	ENABLE_GPIO_GIRQ(9);
-	ENABLE_GPIO_GIRQ(10);
-	ENABLE_GPIO_GIRQ(11);
-	ENABLE_GPIO_GIRQ(20);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-
-/**
- * Handler for each GIRQ interrupt. This reads and clears the interrupt bits for
- * the GIRQ interrupt, then finds and calls the corresponding GPIO interrupt
- * handlers.
- *
- * @param girq		GIRQ index
- * @param port_offset	GPIO port offset for the given GIRQ
- */
-static void gpio_interrupt(int girq, int port_offset)
-{
-	int i, bit;
-	const struct gpio_info *g = gpio_list;
-	uint32_t sts = MEC1322_INT_RESULT(girq);
-
-	MEC1322_INT_SOURCE(girq) |= sts;
-
-	for (i = 0; i < GPIO_IH_COUNT && sts; ++i, ++g) {
-		bit = (g->port - port_offset) * 8 + __builtin_ffs(g->mask) - 1;
-		if (sts & BIT(bit))
-			gpio_irq_handlers[i](i);
-		sts &= ~BIT(bit);
-	}
-}
-
-#define GPIO_IRQ_FUNC(irqfunc, girq, port_offset)  \
-	void irqfunc(void)                         \
-	{                                          \
-		gpio_interrupt(girq, port_offset); \
-	}
-
-GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 14);
-GPIO_IRQ_FUNC(__girq_9_interrupt, 9, 10);
-GPIO_IRQ_FUNC(__girq_10_interrupt, 10, 4);
-GPIO_IRQ_FUNC(__girq_11_interrupt, 11, 0);
-GPIO_IRQ_FUNC(__girq_20_interrupt, 20, 20);
-
-#undef GPIO_IRQ_FUNC
-
-/*
- * Declare IRQs.  Nesting this macro inside the GPIO_IRQ_FUNC macro works
- * poorly because DECLARE_IRQ() stringizes its inputs.
- */
-DECLARE_IRQ(MEC1322_IRQ_GIRQ8, __girq_8_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ9, __girq_9_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ10, __girq_10_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ11, __girq_11_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ20, __girq_20_interrupt, 1);
diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c
deleted file mode 100644
index a5c5858620..0000000000
--- a/chip/mec1322/hwtimer.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) -
-			       (0xffffffff - deadline);
-	MEC1322_TMR32_CTL(1) |= BIT(5);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return MEC1322_TMR32_CNT(1) - MEC1322_TMR32_CNT(0) + 0xffffffff;
-}
-
-void __hw_clock_event_clear(void)
-{
-	MEC1322_TMR32_CTL(1) &= ~BIT(5);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return 0xffffffff - MEC1322_TMR32_CNT(0);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	MEC1322_TMR32_CTL(0) &= ~BIT(5);
-	MEC1322_TMR32_CNT(0) = 0xffffffff - ts;
-	MEC1322_TMR32_CTL(0) |= BIT(5);
-}
-
-static void __hw_clock_source_irq(int timer_id)
-{
-	if (timer_id == 1)
-		MEC1322_TMR32_STS(1) |= 1;
-	/* If IRQ is from timer 0, 32-bit timer overflowed */
-	process_timers(timer_id == 0);
-}
-
-void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
-DECLARE_IRQ(MEC1322_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
-void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
-DECLARE_IRQ(MEC1322_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
-
-static void configure_timer(int timer_id)
-{
-	uint32_t val;
-
-	/* Ensure timer is not running */
-	MEC1322_TMR32_CTL(timer_id) &= ~BIT(5);
-
-	/* Enable timer */
-	MEC1322_TMR32_CTL(timer_id) |= BIT(0);
-
-	val = MEC1322_TMR32_CTL(timer_id);
-
-	/* Pre-scale = 48 -> 1MHz -> Period = 1us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MEC1322_TMR32_CTL(timer_id) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MEC1322_TMR32_PRE(timer_id) = 0xffffffff;
-
-	/* Enable interrupt */
-	MEC1322_TMR32_IEN(timer_id) |= 1;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * The timer can only fire interrupt when its value reaches zero.
-	 * Therefore we need two timers:
-	 *   - Timer 0 as free running timer
-	 *   - Timer 1 as event timer
-	 */
-	configure_timer(0);
-	configure_timer(1);
-
-	/* Override the count */
-	MEC1322_TMR32_CNT(0) = 0xffffffff - start_t;
-
-	/* Auto restart */
-	MEC1322_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MEC1322_TMR32_CTL(0) |= BIT(5);
-
-	/* Enable interrupt */
-	task_enable_irq(MEC1322_IRQ_TIMER32_0);
-	task_enable_irq(MEC1322_IRQ_TIMER32_1);
-	MEC1322_INT_ENABLE(23) |= BIT(4) | BIT(5);
-	MEC1322_INT_BLK_EN |= BIT(23);
-
-	return MEC1322_IRQ_TIMER32_1;
-}
diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c
deleted file mode 100644
index aecc8abd9b..0000000000
--- a/chip/mec1322/i2c.c
+++ /dev/null
@@ -1,531 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for MEC1322 */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_CLOCK 16000000 /* 16 MHz */
-
-/* Status */
-#define STS_NBB BIT(0) /* Bus busy */
-#define STS_LAB BIT(1) /* Arbitration lost */
-#define STS_LRB BIT(3) /* Last received bit */
-#define STS_BER BIT(4) /* Bus error */
-#define STS_PIN BIT(7) /* Pending interrupt */
-
-/* Control */
-#define CTRL_ACK BIT(0) /* Acknowledge */
-#define CTRL_STO BIT(1) /* STOP */
-#define CTRL_STA BIT(2) /* START */
-#define CTRL_ENI BIT(3) /* Enable interrupt */
-#define CTRL_ESO BIT(6) /* Enable serial output */
-#define CTRL_PIN BIT(7) /* Pending interrupt not */
-
-/* Completion */
-#define COMP_IDLE BIT(29)    /* i2c bus is idle */
-#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */
-
-/* Maximum transfer of a SMBUS block transfer */
-#define SMBUS_MAX_BLOCK_SIZE 32
-
-/*
- * Amount of time to blocking wait for i2c bus to finish. After this blocking
- * timeout, if the bus is still not finished, then allow other tasks to run.
- * Note: this is just long enough for a 400kHz bus to finish transmitting one
- * byte assuming the bus isn't being held.
- */
-#define I2C_WAIT_BLOCKING_TIMEOUT_US 25
-
-enum i2c_transaction_state {
-	/* Stop condition was sent in previous transaction */
-	I2C_TRANSACTION_STOPPED,
-	/* Stop condition was not sent in previous transaction */
-	I2C_TRANSACTION_OPEN,
-};
-
-/* I2C controller state data */
-static struct {
-	/* Transaction timeout, or 0 to use default. */
-	uint32_t timeout_us;
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	volatile task_id_t task_waiting;
-	enum i2c_transaction_state transaction_state;
-} cdata[I2C_CONTROLLER_COUNT];
-
-/* Map port number to port name in datasheet, for debug prints. */
-static const char *i2c_port_names[MEC1322_I2C_PORT_COUNT] = {
-	[MEC1322_I2C0_0] = "0_0",
-	[MEC1322_I2C0_1] = "0_1",
-	[MEC1322_I2C1] = "1",
-	[MEC1322_I2C2] = "2",
-	[MEC1322_I2C3] = "3",
-};
-
-static void configure_controller_speed(int controller, int kbps)
-{
-	int t_low, t_high;
-	const int period = I2C_CLOCK / 1000 / kbps;
-
-	/*
-	 * Refer to NXP UM10204 for minimum timing requirement of T_Low and
-	 * T_High.
-	 * http://www.nxp.com/documents/user_manual/UM10204.pdf
-	 */
-	if (kbps > 400) {
-		/* Fast mode plus */
-		t_low = t_high = period / 2 - 1;
-		MEC1322_I2C_DATA_TIM(controller) = 0x06060601;
-		MEC1322_I2C_DATA_TIM_2(controller) = 0x06;
-	} else if (kbps > 100) {
-		/* Fast mode */
-		/* By spec, clk low period is 1.3us min */
-		t_low = MAX((int)(I2C_CLOCK * 1.3 / 1000000), period / 2 - 1);
-		t_high = period - t_low - 2;
-		MEC1322_I2C_DATA_TIM(controller) = 0x040a0a01;
-		MEC1322_I2C_DATA_TIM_2(controller) = 0x0a;
-	} else {
-		/* Standard mode */
-		t_low = t_high = period / 2 - 1;
-		MEC1322_I2C_DATA_TIM(controller) = 0x0c4d5006;
-		MEC1322_I2C_DATA_TIM_2(controller) = 0x4d;
-	}
-
-	/* Clock periods is one greater than the contents of these fields */
-	MEC1322_I2C_BUS_CLK(controller) = ((t_high & 0xff) << 8) |
-					  (t_low & 0xff);
-}
-
-static void configure_controller(int controller, int kbps)
-{
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN;
-	MEC1322_I2C_OWN_ADDR(controller) = 0x0;
-	configure_controller_speed(controller, kbps);
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-				       CTRL_ACK | CTRL_ENI;
-	MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */
-
-	/* Enable interrupt */
-	MEC1322_I2C_CONFIG(controller) |= BIT(29); /* ENIDI */
-	MEC1322_INT_ENABLE(12) |= BIT(controller);
-	MEC1322_INT_BLK_EN |= BIT(12);
-}
-
-static void reset_controller(int controller)
-{
-	int i;
-
-	MEC1322_I2C_CONFIG(controller) |= BIT(9);
-	udelay(100);
-	MEC1322_I2C_CONFIG(controller) &= ~BIT(9);
-
-	for (i = 0; i < i2c_ports_used; ++i)
-		if (controller == i2c_port_to_controller(i2c_ports[i].port)) {
-			configure_controller(controller, i2c_ports[i].kbps);
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-			break;
-		}
-}
-
-static int wait_for_interrupt(int controller, int timeout)
-{
-	int event;
-
-	if (timeout <= 0)
-		return EC_ERROR_TIMEOUT;
-
-	cdata[controller].task_waiting = task_get_current();
-	task_enable_irq(MEC1322_IRQ_I2C_0 + controller);
-
-	/* Wait until I2C interrupt or timeout. */
-	event = task_wait_event_mask(TASK_EVENT_I2C_IDLE, timeout);
-
-	task_disable_irq(MEC1322_IRQ_I2C_0 + controller);
-	cdata[controller].task_waiting = TASK_ID_INVALID;
-
-	return (event & TASK_EVENT_TIMER) ? EC_ERROR_TIMEOUT : EC_SUCCESS;
-}
-
-static int wait_idle(int controller)
-{
-	uint8_t sts = MEC1322_I2C_STATUS(controller);
-	uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	uint64_t task_timeout = block_timeout + cdata[controller].timeout_us;
-	int rv = 0;
-
-	while (!(sts & STS_NBB)) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout)
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		sts = MEC1322_I2C_STATUS(controller);
-	}
-
-	if (sts & (STS_BER | STS_LAB))
-		return EC_ERROR_UNKNOWN;
-	return EC_SUCCESS;
-}
-
-static int wait_byte_done(int controller)
-{
-	uint8_t sts = MEC1322_I2C_STATUS(controller);
-	uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	uint64_t task_timeout = block_timeout + cdata[controller].timeout_us;
-	int rv = 0;
-
-	while (sts & STS_PIN) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout)
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		sts = MEC1322_I2C_STATUS(controller);
-	}
-
-	return sts & STS_LRB;
-}
-
-static void select_port(int port)
-{
-	/*
-	 * I2C0_1 uses port 1 of controller 0. All other I2C pin sets
-	 * use port 0.
-	 */
-	uint8_t port_sel = (port == MEC1322_I2C0_1) ? 1 : 0;
-	int controller = i2c_port_to_controller(port);
-
-	MEC1322_I2C_CONFIG(controller) &= ~0xf;
-	MEC1322_I2C_CONFIG(controller) |= port_sel;
-
-}
-
-static inline int get_line_level(int controller)
-{
-	int ret, ctrl;
-	/*
-	* We need to enable BB (Bit Bang) mode in order to read line level
-	* properly, othervise line levels return always idle (0x60).
-	*/
-	ctrl = MEC1322_I2C_BB_CTRL(controller);
-	MEC1322_I2C_BB_CTRL(controller) |= 1;
-	ret = (MEC1322_I2C_BB_CTRL(controller) >> 5) & 0x3;
-	MEC1322_I2C_BB_CTRL(controller) = ctrl;
-	return ret;
-}
-
-static inline void push_in_buf(uint8_t **in, uint8_t val, int skip)
-{
-	if (!skip) {
-		**in = val;
-		(*in)++;
-	}
-}
-
-int chip_i2c_xfer(const int port,
-		  const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	int i;
-	int controller;
-	int send_start = flags & I2C_XFER_START;
-	int send_stop = flags & I2C_XFER_STOP;
-	int skip = 0;
-	int bytes_to_read;
-	uint8_t reg;
-	int ret_done;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	select_port(port);
-	controller = i2c_port_to_controller(port);
-	if (send_start &&
-	    cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED)
-		wait_idle(controller);
-
-	reg = MEC1322_I2C_STATUS(controller);
-	if (send_start &&
-	    cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED &&
-	    (((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) ||
-			    (get_line_level(controller)
-			    != I2C_LINE_IDLE))) {
-		CPRINTS("i2c%s bad status 0x%02x, SCL=%d, SDA=%d",
-			i2c_port_names[port], reg,
-			get_line_level(controller) & I2C_LINE_SCL_HIGH,
-			get_line_level(controller) & I2C_LINE_SDA_HIGH);
-
-		/* Attempt to unwedge the port. */
-		i2c_unwedge(port);
-
-		/* Bus error, bus busy, or arbitration lost. Try reset. */
-		reset_controller(controller);
-		select_port(port);
-
-		/*
-		 * We don't know what edges the slave saw, so sleep long enough
-		 * that the slave will see the new start condition below.
-		 */
-		usleep(1000);
-	}
-
-	if (out_size) {
-		if (send_start) {
-			MEC1322_I2C_DATA(controller) =
-				(uint8_t)(I2C_STRIP_FLAGS(slave_addr_flags)
-					  << 1);
-
-			/* Clock out the slave address, sending START bit */
-			MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-						       CTRL_ENI | CTRL_ACK |
-						       CTRL_STA;
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_OPEN;
-		}
-
-		for (i = 0; i < out_size; ++i) {
-			ret_done = wait_byte_done(controller);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-			MEC1322_I2C_DATA(controller) = out[i];
-		}
-		ret_done = wait_byte_done(controller);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-
-		/*
-		 * Send STOP bit if the stop flag is on, and caller
-		 * doesn't expect to receive data.
-		 */
-		if (send_stop && in_size == 0) {
-			MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-						       CTRL_STO | CTRL_ACK;
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-		}
-	}
-
-	if (in_size) {
-		/* Resend start bit when changing direction */
-		if (out_size || send_start) {
-			/* Repeated start case */
-			if (cdata[controller].transaction_state ==
-			    I2C_TRANSACTION_OPEN)
-				MEC1322_I2C_CTRL(controller) = CTRL_ESO |
-							       CTRL_STA |
-							       CTRL_ACK |
-							       CTRL_ENI;
-
-			MEC1322_I2C_DATA(controller) =
-				(uint8_t)(I2C_STRIP_FLAGS(slave_addr_flags)
-					  << 1)
-				| 0x01;
-
-			/* New transaction case, clock out slave address. */
-			if (cdata[controller].transaction_state ==
-			    I2C_TRANSACTION_STOPPED)
-				MEC1322_I2C_CTRL(controller) = CTRL_ESO |
-							       CTRL_STA |
-							       CTRL_ACK |
-							       CTRL_ENI |
-							       CTRL_PIN;
-
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_OPEN;
-
-			/* Skip over the unused byte */
-			skip = 1;
-			in_size++;
-		}
-
-		/* Special flags need to be set for last two bytes */
-		bytes_to_read = send_stop ? in_size - 2 : in_size;
-
-		for (i = 0; i < bytes_to_read; ++i) {
-			ret_done = wait_byte_done(controller);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-			push_in_buf(&in, MEC1322_I2C_DATA(controller), skip);
-			skip = 0;
-		}
-		ret_done = wait_byte_done(controller);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-
-		if (send_stop) {
-			/*
-			 * De-assert ACK bit before reading the next to last
-			 * byte, so that the last byte is NACK'ed.
-			 */
-			MEC1322_I2C_CTRL(controller) = CTRL_ESO | CTRL_ENI;
-			push_in_buf(&in, MEC1322_I2C_DATA(controller), skip);
-			ret_done = wait_byte_done(controller);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-
-			/* Send STOP */
-			MEC1322_I2C_CTRL(controller) =
-				CTRL_PIN | CTRL_ESO | CTRL_ACK | CTRL_STO;
-
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-
-			/*
-			 * We need to know our stop point two bytes in
-			 * advance. If we don't know soon enough, we need
-			 * to do an extra read (to last_addr + 1) to
-			 * issue the stop.
-			 */
-			push_in_buf(&in, MEC1322_I2C_DATA(controller),
-				    in_size == 1);
-		}
-	}
-
-	/* Check for error conditions */
-	if (MEC1322_I2C_STATUS(controller) & (STS_LAB | STS_BER))
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-err_chip_i2c_xfer:
-	/* Send STOP and return error */
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-				       CTRL_STO | CTRL_ACK;
-	cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
-	if (ret_done == STS_LRB)
-		return EC_ERROR_BUSY;
-	else if (ret_done == EC_ERROR_TIMEOUT) {
-		/*
-		 * If our transaction timed out then our i2c controller
-		 * may be wedged without showing any other outward signs
-		 * of failure. Reset the controller so that future
-		 * transactions have a chance of success.
-		 */
-		reset_controller(controller);
-		return EC_ERROR_TIMEOUT;
-	}
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_get_line_levels(int port)
-{
-	int rv;
-
-	i2c_lock(port, 1);
-	select_port(port);
-	rv = get_line_level(i2c_port_to_controller(port));
-	i2c_lock(port, 0);
-	return rv;
-}
-
-int i2c_port_to_controller(int port)
-{
-	if (port < 0 || port >= MEC1322_I2C_PORT_COUNT)
-		return -1;
-	return (port == MEC1322_I2C0_0) ? 0 : port - 1;
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	/* Param is port, but timeout is stored by-controller. */
-	cdata[i2c_port_to_controller(port)].timeout_us =
-		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-void i2c_init(void)
-{
-	int i;
-	int controller;
-	int controller0_kbps = -1;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	for (i = 0; i < i2c_ports_used; ++i) {
-		/*
-		 * If this controller has multiple ports, check if we already
-		 * configured it. If so, ensure previously configured bitrate
-		 * matches.
-		 */
-		controller = i2c_port_to_controller(i2c_ports[i].port);
-		if (controller == 0) {
-			if (controller0_kbps != -1) {
-				ASSERT(controller0_kbps == i2c_ports[i].kbps);
-				continue;
-			}
-			controller0_kbps = i2c_ports[i].kbps;
-		}
-		configure_controller(controller, i2c_ports[i].kbps);
-		cdata[controller].task_waiting = TASK_ID_INVALID;
-		cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
-
-		/* Use default timeout. */
-		i2c_set_timeout(i2c_ports[i].port, 0);
-	}
-}
-
-static void handle_interrupt(int controller)
-{
-	int id = cdata[controller].task_waiting;
-
-	/* Clear the interrupt status */
-	MEC1322_I2C_COMPLETE(controller) &= (COMP_RW_BITS_MASK | COMP_IDLE);
-
-	/*
-	 * Write to control register interferes with I2C transaction.
-	 * Instead, let's disable IRQ from the core until the next time
-	 * we want to wait for STS_PIN/STS_NBB.
-	 */
-	task_disable_irq(MEC1322_IRQ_I2C_0 + controller);
-
-	/* Wake up the task which was waiting on the I2C interrupt, if any. */
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_I2C_IDLE);
-}
-
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
-
-DECLARE_IRQ(MEC1322_IRQ_I2C_0, i2c0_interrupt, 2);
-DECLARE_IRQ(MEC1322_IRQ_I2C_1, i2c1_interrupt, 2);
-DECLARE_IRQ(MEC1322_IRQ_I2C_2, i2c2_interrupt, 2);
-DECLARE_IRQ(MEC1322_IRQ_I2C_3, i2c3_interrupt, 2);
diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c
deleted file mode 100644
index 2c62ada9ac..0000000000
--- a/chip/mec1322/keyboard_raw.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for MEC1322
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void keyboard_raw_init(void)
-{
-	keyboard_raw_enable_interrupt(0);
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
-
-	/* Enable keyboard scan interrupt */
-	MEC1322_INT_ENABLE(17) |= BIT(21);
-	MEC1322_INT_BLK_EN |= BIT(17);
-	MEC1322_KS_KSI_INT_EN = 0xff;
-}
-
-void keyboard_raw_task_start(void)
-{
-	task_enable_irq(MEC1322_IRQ_KSC_INT);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	if (out == KEYBOARD_COLUMN_ALL) {
-		MEC1322_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 1);
-#endif
-	} else if (out == KEYBOARD_COLUMN_NONE) {
-		MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 0);
-#endif
-	} else {
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		if (out == 2) {
-			MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-			gpio_set_level(GPIO_KBD_KSO2, 1);
-		} else {
-			MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-			gpio_set_level(GPIO_KBD_KSO2, 0);
-		}
-#else
-		MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-#endif
-	}
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Invert it so 0=not pressed, 1=pressed */
-	return (MEC1322_KS_KSI_INPUT & 0xff) ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		task_clear_pending_irq(MEC1322_IRQ_KSC_INT);
-		task_enable_irq(MEC1322_IRQ_KSC_INT);
-	} else {
-		task_disable_irq(MEC1322_IRQ_KSC_INT);
-	}
-}
-
-void keyboard_raw_interrupt(void)
-{
-	/* Clear interrupt status bits */
-	MEC1322_KS_KSI_STATUS = 0xff;
-
-	/* Wake keyboard scan task to handle interrupt */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(MEC1322_IRQ_KSC_INT, keyboard_raw_interrupt, 1);
-
-int keyboard_raw_is_input_low(int port, int id)
-{
-	return (MEC1322_GPIO_CTL(port, id) & BIT(24)) == 0;
-}
diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c
deleted file mode 100644
index 1fb334e144..0000000000
--- a/chip/mec1322/lfw/ec_lfw.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MEC1322 SoC little FW
- *
- */
-
-#include <stdint.h>
-
-#include "config.h"
-#include "cros_version.h"
-#include "gpio.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "util.h"
-#include "timer.h"
-#include "dma.h"
-#include "registers.h"
-#include "cpu.h"
-#include "clock.h"
-#include "system.h"
-#include "hwtimer.h"
-#include "gpio_list.h"
-
-#include "ec_lfw.h"
-
-__attribute__ ((section(".intvector")))
-const struct int_vector_t hdr_int_vect = {
-			(void *)0x11FA00, /* init sp, unused,
-						set by MEC ROM loader*/
-			&lfw_main,	  /* reset vector */
-			&fault_handler,   /* NMI handler */
-			&fault_handler,   /* HardFault handler */
-			&fault_handler,   /* MPU fault handler */
-			&fault_handler    /* Bus fault handler */
-};
-
-/* SPI devices - from glados/board.c*/
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-
-void timer_init()
-{
-	uint32_t val = 0;
-
-	/* Ensure timer is not running */
-	MEC1322_TMR32_CTL(0) &= ~BIT(5);
-
-	/* Enable timer */
-	MEC1322_TMR32_CTL(0) |= BIT(0);
-
-	val = MEC1322_TMR32_CTL(0);
-
-	/* Pre-scale = 48 -> 1MHz -> Period = 1us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MEC1322_TMR32_CTL(0) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MEC1322_TMR32_PRE(0) = 0xffffffff;
-
-	/* Override the count */
-	MEC1322_TMR32_CNT(0) = 0xffffffff;
-
-	/* Auto restart */
-	MEC1322_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MEC1322_TMR32_CTL(0) |= BIT(5);
-
-}
-
-static int spi_flash_readloc(uint8_t *buf_usr,
-				unsigned int offset,
-				unsigned int bytes)
-{
-	uint8_t cmd[4] = {SPI_FLASH_READ,
-				(offset >> 16) & 0xFF,
-				(offset >> 8) & 0xFF,
-				offset & 0xFF};
-
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes);
-}
-
-int spi_image_load(uint32_t offset)
-{
-	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
-				    CONFIG_PROGRAM_MEMORY_BASE);
-	uint32_t i;
-
-	BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE);
-	memset((void *)buf, 0xFF, (CONFIG_RO_SIZE - 4));
-
-	for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE)
-		spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
-
-	return 0;
-
-}
-
-void udelay(unsigned us)
-{
-	uint32_t t0 = __hw_clock_source_read();
-	while (__hw_clock_source_read() - t0 < us)
-		;
-}
-
-void usleep(unsigned us)
-{
-	udelay(us);
-}
-
-int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
-{
-	timestamp_t now_val;
-
-	if (!now) {
-		now_val = get_time();
-		now = &now_val;
-	}
-
-	return now->le.lo >= deadline.le.lo;
-}
-
-
-timestamp_t get_time(void)
-{
-	timestamp_t ts;
-
-	ts.le.hi = 0;
-	ts.le.lo = __hw_clock_source_read();
-	return ts;
-}
-
-void uart_write_c(char c)
-{
-	/* Put in carriage return prior to newline to mimic uart_vprintf() */
-	if (c == '\n')
-		uart_write_c('\r');
-
-	/* Wait for space in transmit FIFO. */
-	while (!(MEC1322_UART_LSR & BIT(5)))
-		;
-	MEC1322_UART_TB = c;
-}
-
-void uart_puts(const char *str)
-{
-	if (!str || !*str)
-		return;
-
-	do {
-		uart_write_c(*str++);
-	} while (*str);
-}
-
-void fault_handler(void)
-{
-	uart_puts("EXCEPTION!\nTriggering watchdog reset\n");
-	/* trigger reset in 1 ms */
-	MEC1322_WDG_LOAD = 1;
-	MEC1322_WDG_CTL |= 1;
-	while (1)
-		;
-
-}
-
-void jump_to_image(uintptr_t init_addr)
-{
-	void (*resetvec)(void) = (void(*)(void))init_addr;
-	resetvec();
-}
-
-void uart_init(void)
-{
-	/* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */
-	MEC1322_UART_CFG &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MEC1322_UART_CFG &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MEC1322_UART_LCR |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MEC1322_UART_PBRG0 = 1;
-	MEC1322_UART_PBRG1 = 0;
-
-	/* Set DLAB = 0 */
-	MEC1322_UART_LCR &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MEC1322_UART_LCR |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MEC1322_UART_FCR = BIT(0);
-
-	/* Activate UART */
-	MEC1322_UART_ACT |= BIT(0);
-
-	gpio_config_module(MODULE_UART, 1);
-}
-
-void system_init(void)
-{
-
-	uint32_t wdt_sts = MEC1322_VBAT_STS & MEC1322_VBAT_STS_WDT;
-	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
-				MEC1322_PWR_RST_STS_VCC1;
-
-	if (rst_sts || wdt_sts)
-		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO;
-}
-
-enum ec_image system_get_image_copy(void)
-{
-	return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX);
-}
-
-void lfw_main()
-{
-
-	uintptr_t init_addr;
-
-	/* install vector table */
-	*((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect;
-
-	/* Use 48 MHz processor clock to power through boot */
-	MEC1322_PCR_PROC_CLK_CTL = 1;
-
-#ifdef CONFIG_WATCHDOG
-	/* Reload watchdog which may be running in case of sysjump */
-	MEC1322_WDG_KICK = 1;
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Stop aux timer */
-	MEC1322_TMR16_CTL(0) &= ~1;
-#endif
-#endif
-
-	timer_init();
-	clock_init();
-	cpu_init();
-	dma_init();
-	uart_init();
-	system_init();
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	uart_puts("littlefw ");
-	uart_puts(current_image_data.version);
-	uart_puts("\n");
-
-	switch (system_get_image_copy()) {
-	case EC_IMAGE_RW:
-		uart_puts("lfw-RW load\n");
-		init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-		spi_image_load(CONFIG_EC_WRITABLE_STORAGE_OFF +
-			       CONFIG_RW_STORAGE_OFF);
-		break;
-	case EC_IMAGE_RO:
-		uart_puts("lfw-RO load\n");
-		spi_image_load(CONFIG_EC_PROTECTED_STORAGE_OFF +
-			       CONFIG_RO_STORAGE_OFF);
-		/* fall through */
-	default:
-		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO;
-		init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-	}
-
-	jump_to_image(*(uintptr_t *)(init_addr + 4));
-
-	/* should never get here */
-	while (1)
-		;
-}
diff --git a/chip/mec1322/lfw/ec_lfw.h b/chip/mec1322/lfw/ec_lfw.h
deleted file mode 100644
index dd26fbd323..0000000000
--- a/chip/mec1322/lfw/ec_lfw.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MEC1322 SoC little FW
- *
- */
-
-#include <stdnoreturn.h>
-
-noreturn void lfw_main(void) __attribute__ ((naked));
-void fault_handler(void) __attribute__((naked));
-
-struct int_vector_t {
-	void   *stack_ptr;
-	void   *reset_vector;
-	void   *nmi;
-	void   *hard_fault;
-	void   *bus_fault;
-	void   *usage_fault;
-};
-
-#define SPI_CHUNK_SIZE			1024
diff --git a/chip/mec1322/lfw/ec_lfw.ld b/chip/mec1322/lfw/ec_lfw.ld
deleted file mode 100644
index 65e17e4941..0000000000
--- a/chip/mec1322/lfw/ec_lfw.ld
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MEC1322 SoC little FW
- *
- */
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-    VECTOR(r )  : ORIGIN =  0x100000, LENGTH = 0x18
-    SRAM (xrw)  : ORIGIN =  0x100018, LENGTH = 0xBE8
-}
-
-/*
- * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the
- * values here.
- */
-ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.")
-ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0xC00, "Invalid VECTOR+SRAM length.")
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(lfw_main)
-
-/* Sections Definitions */
-
-SECTIONS
-{
-
-    /*
-     * The vector table goes first
-     */
-    .intvector :
-    {
-        . = ALIGN(4);
-        KEEP(*(.intvector))
-    } > VECTOR
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to FLASH.
-     */
-
-    .text :
-    {
-        *(.text .text.*)                        /* all remaining code */
-        *(.rodata .rodata.*)            /* read-only data (constants) */
-    } >SRAM
-
-    . = ALIGN(4);
-
-    /* Padding */
-
-    .fill : {
-        FILL(0xFF);
-        . = ORIGIN(SRAM) + LENGTH(SRAM) - 1;
-        BYTE(0xFF);   /* emit at least a byte to make linker happy */
-    }
-
-    __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR);
-}
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c
deleted file mode 100644
index 020cd0e23e..0000000000
--- a/chip/mec1322/lpc.c
+++ /dev/null
@@ -1,520 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for MEC1322 */
-
-#include "acpi.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "port80.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "chipset.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align")));
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)mem_mapped;
-
-static void keyboard_irq_assert(void)
-{
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	udelay(4);
-
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-#else
-	/*
-	 * SERIRQ is automatically sent by KBC
-	 */
-#endif
-}
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-}
-
-static void lpc_generate_sci(void)
-{
-#ifdef CONFIG_SCI_GPIO
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#else
-	MEC1322_ACPI_PM_STS |= 1;
-	udelay(65);
-	MEC1322_ACPI_PM_STS &= ~1;
-#endif
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return mem_mapped + 0x100;
-}
-
-static uint8_t *lpc_get_hostcmd_data_range(void)
-{
-	return mem_mapped;
-}
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via PCH_SMI_L GPIO
- *   - SCI pulse via PCH_SCI_L GPIO
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_SMI_PENDING))
-			need_smi = 1;
-		MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SMI_PENDING;
-	} else {
-		MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SMI_PENDING;
-	}
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SCI_PENDING;
-	} else {
-		MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SCI_PENDING;
-	}
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte. */
-	MEC1322_ACPI_EC_EC2OS(1, 0) = pkt->driver_result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-}
-
-/*
- * Most registers in LPC module are reset when the host is off. We need to
- * set up LPC again when the host is starting up.
- */
-static void setup_lpc(void)
-{
-	gpio_config_module(MODULE_LPC, 1);
-
-	/* Set up interrupt on LRESET# deassert */
-	MEC1322_INT_SOURCE(19) = BIT(1);
-	MEC1322_INT_ENABLE(19) |= BIT(1);
-	MEC1322_INT_BLK_EN |= BIT(19);
-	task_enable_irq(MEC1322_IRQ_GIRQ19);
-
-	/* Set up ACPI0 for 0x62/0x66 */
-	MEC1322_LPC_ACPI_EC0_BAR = 0x00628304;
-	MEC1322_INT_ENABLE(15) |= BIT(6);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	/* Clear STATUS_PROCESSING bit in case it was set during sysjump */
-	MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
-	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-
-	/* Set up ACPI1 for 0x200/0x204 */
-	MEC1322_LPC_ACPI_EC1_BAR = 0x02008407;
-	MEC1322_INT_ENABLE(15) |= BIT(8);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF);
-
-	/* Set up 8042 interface at 0x60/0x64 */
-	MEC1322_LPC_8042_BAR = 0x00608104;
-
-	/* Set up indication of Auxiliary sts */
-	MEC1322_8042_KB_CTRL |= BIT(7);
-
-	MEC1322_8042_ACT |= 1;
-	MEC1322_INT_ENABLE(15) |= (BIT(13) | BIT(14));
-	MEC1322_INT_BLK_EN |= BIT(15);
-	task_enable_irq(MEC1322_IRQ_8042EM_IBF);
-	task_enable_irq(MEC1322_IRQ_8042EM_OBF);
-
-#ifndef CONFIG_KEYBOARD_IRQ_GPIO
-	/* Set up SERIRQ for keyboard */
-	MEC1322_8042_KB_CTRL |= BIT(5);
-	MEC1322_LPC_SIRQ(1) = 0x01;
-#endif
-
-	/* Set up EMI module for memory mapped region, base address 0x800 */
-	MEC1322_LPC_EMI_BAR = 0x0800800f;
-	MEC1322_INT_ENABLE(15) |= BIT(2);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	task_enable_irq(MEC1322_IRQ_EMI);
-
-	/* Access data RAM through alias address */
-	MEC1322_EMI_MBA0 = (uint32_t)mem_mapped - 0x118000 + 0x20000000;
-
-	/*
-	 * Limit EMI read / write range. First 256 bytes are RW for host
-	 * commands. Second 256 bytes are RO for mem-mapped data.
-	 */
-	MEC1322_EMI_MRL0 = 0x200;
-	MEC1322_EMI_MWL0 = 0x100;
-
-	/* Set up Mailbox for Port80 trapping */
-	MEC1322_MBX_INDEX = 0xff;
-	MEC1322_LPC_MAILBOX_BAR = 0x00808901;
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST);
-
-static void lpc_init(void)
-{
-	/* Activate LPC interface */
-	MEC1322_LPC_ACT |= 1;
-
-	/*
-	* Ring Oscillator not permitted to shut down
-	* until LPC activate bit is cleared
-	*/
-	MEC1322_LPC_CLK_CTRL |= 3;
-
-	/* Initialize host args and memory map to all zero */
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-
-	setup_lpc();
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-void girq19_interrupt(void)
-{
-	/* Check interrupt result for LRESET# trigger */
-	if (MEC1322_INT_RESULT(19) & BIT(1)) {
-		/* Initialize LPC module when LRESET# is deasserted */
-		if (!lpc_get_pltrst_asserted()) {
-			setup_lpc();
-		} else {
-			/* Store port 80 reset event */
-			port_80_write(PORT_80_EVENT_RESET);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-			/* Notify HOOK_CHIPSET_RESET */
-			hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-		}
-
-		CPRINTS("LPC RESET# %sasserted",
-			lpc_get_pltrst_asserted() ? "" : "de");
-
-		/* Clear interrupt source */
-		MEC1322_INT_SOURCE(19) = BIT(1);
-	}
-}
-DECLARE_IRQ(MEC1322_IRQ_GIRQ19, girq19_interrupt, 1);
-
-void emi_interrupt(void)
-{
-	port_80_write(MEC1322_EMI_H2E_MBX);
-}
-DECLARE_IRQ(MEC1322_IRQ_EMI, emi_interrupt, 1);
-
-/*
- * Port80 POST code polling limitation:
- * - POST code 0xFF is ignored.
- */
-int port_80_read(void)
-{
-	int data;
-
-	/* read MBX_INDEX for POST code */
-	data = MEC1322_MBX_INDEX;
-
-	/* clear MBX_INDEX for next POST code*/
-	MEC1322_MBX_INDEX = 0xff;
-
-	/* mark POST code 0xff as invalid */
-	if (data == 0xff)
-		data = PORT_80_IGNORE;
-
-	return data;
-}
-
-void acpi_0_interrupt(void)
-{
-	uint8_t value, result, is_cmd;
-
-	is_cmd = MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_LAST_CMD;
-
-	/* Set the bust bi */
-	MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_PROCESSING;
-
-	/* Read command/data; this clears the FRMH bit. */
-	value = MEC1322_ACPI_EC_OS2EC(0, 0);
-
-	/* Handle whatever this was. */
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		MEC1322_ACPI_EC_EC2OS(0, 0) = result;
-
-	/* Clear the busy bit */
-	MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
-	 * Full condition on the kernel channel.
-	 */
-	lpc_generate_sci();
-}
-DECLARE_IRQ(MEC1322_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1);
-
-void acpi_1_interrupt(void)
-{
-	uint8_t st = MEC1322_ACPI_EC_STATUS(1);
-	if (!(st & EC_LPC_STATUS_FROM_HOST) ||
-	    !(st & EC_LPC_STATUS_LAST_CMD))
-		return;
-
-	/* Set the busy bit */
-	MEC1322_ACPI_EC_STATUS(1) |= EC_LPC_STATUS_PROCESSING;
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = MEC1322_ACPI_EC_OS2EC(1, 0);
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* We only support new style command (v3) now */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)lpc_get_hostcmd_data_range();
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)lpc_get_hostcmd_data_range();
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-		host_packet_receive(&lpc_packet);
-		return;
-	} else {
-		/* Old style command unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-}
-DECLARE_IRQ(MEC1322_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1);
-
-#ifdef HAS_TASK_KEYPROTO
-void kb_ibf_interrupt(void)
-{
-	if (lpc_keyboard_input_pending())
-		keyboard_host_write(MEC1322_8042_H2E,
-				    MEC1322_8042_STS & BIT(3));
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MEC1322_IRQ_8042EM_IBF, kb_ibf_interrupt, 1);
-
-void kb_obf_interrupt(void)
-{
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MEC1322_IRQ_8042EM_OBF, kb_obf_interrupt, 1);
-#endif
-
-int lpc_keyboard_has_char(void)
-{
-	return (MEC1322_8042_STS & BIT(0)) ? 1 : 0;
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	return (MEC1322_8042_STS & BIT(1)) ? 1 : 0;
-}
-
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	MEC1322_8042_E2H = chr;
-	if (send_irq)
-		keyboard_irq_assert();
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	volatile char unused __attribute__((unused));
-
-	unused = MEC1322_8042_OBF_CLR;
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	MEC1322_ACPI_EC_STATUS(0) |= mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	MEC1322_ACPI_EC_STATUS(0) &= ~mask;
-}
-
-int lpc_get_pltrst_asserted(void)
-{
-	return (MEC1322_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0;
-}
-
-/* Enable LPC ACPI-EC0 interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-}
-
-/* Disable LPC ACPI-EC0 interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-}
-
-/* On boards without a host, this command is used to set up LPC */
-static int lpc_command_init(int argc, char **argv)
-{
-	lpc_init();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(lpcinit, lpc_command_init, NULL, NULL);
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c
deleted file mode 100644
index df4583ed8b..0000000000
--- a/chip/mec1322/port80.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Port 80 Timer Interrupt for MEC1322 */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "lpc.h"
-#include "port80.h"
-#include "registers.h"
-#include "task.h"
-
-/* Fire timer interrupt every 1000 usec to check for port80 data. */
-#define POLL_PERIOD_USEC 1000
-/* After 30 seconds of no port 80 data, disable the timer interrupt. */
-#define INTERRUPT_DISABLE_TIMEOUT_SEC 30
-#define INTERRUPT_DISABLE_IDLE_COUNT (INTERRUPT_DISABLE_TIMEOUT_SEC \
-				      * 1000000 \
-				      / POLL_PERIOD_USEC)
-
-/* Count the number of consecutive interrupts with no port 80 data. */
-static int idle_count;
-
-static void port_80_interrupt_enable(void)
-{
-	idle_count = 0;
-
-	/* Enable the interrupt. */
-	task_enable_irq(MEC1322_IRQ_TIMER16_1);
-	/* Enable and start the timer. */
-	MEC1322_TMR16_CTL(1) |= 1 | BIT(5);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, port_80_interrupt_enable, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, port_80_interrupt_enable, HOOK_PRIO_DEFAULT);
-
-static void port_80_interrupt_disable(void)
-{
-	/* Disable the timer block. */
-	MEC1322_TMR16_CTL(1) &= ~1;
-	/* Disable the interrupt. */
-	task_disable_irq(MEC1322_IRQ_TIMER16_1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, port_80_interrupt_disable,
-	     HOOK_PRIO_DEFAULT);
-
-/*
- * The port 80 interrupt will use TIMER16 instance 1 for a 1ms countdown
- * timer.  This timer is on GIRQ23, bit 1.
- */
-static void port_80_interrupt_init(void)
-{
-	uint32_t val = 0;
-
-	/*
-	 * The timers are driven by a 48MHz oscillator.  Prescale down to
-	 * 1MHz. 48MHz/48 -> 1MHz
-	 */
-	val = MEC1322_TMR16_CTL(1);
-	val = (val & 0xFFFF) | (47 << 16);
-	/* Automatically restart the timer. */
-	val |= BIT(3);
-	/* The counter should decrement. */
-	val &= ~BIT(2);
-	MEC1322_TMR16_CTL(1) = val;
-
-	/* Set the reload value(us). */
-	MEC1322_TMR16_PRE(1) = POLL_PERIOD_USEC;
-
-	/* Clear the status if any. */
-	MEC1322_TMR16_STS(1) |= 1;
-
-	/* Clear any pending interrupt. */
-	MEC1322_INT_SOURCE(23) = BIT(1);
-	/* Enable IRQ vector 23. */
-	MEC1322_INT_BLK_EN |= BIT(23);
-	/* Enable the interrupt. */
-	MEC1322_TMR16_IEN(1) |= 1;
-	MEC1322_INT_ENABLE(23) = BIT(1);
-
-	port_80_interrupt_enable();
-}
-DECLARE_HOOK(HOOK_INIT, port_80_interrupt_init, HOOK_PRIO_DEFAULT);
-
-void port_80_interrupt(void)
-{
-	int data;
-
-	MEC1322_TMR16_STS(1) = 1; /* Ack the interrupt */
-	if (BIT(1) & MEC1322_INT_RESULT(23)) {
-		data = port_80_read();
-
-		if (data != PORT_80_IGNORE) {
-			idle_count = 0;
-			port_80_write(data);
-		}
-	}
-
-	if (++idle_count >= INTERRUPT_DISABLE_IDLE_COUNT)
-		port_80_interrupt_disable();
-}
-DECLARE_IRQ(MEC1322_IRQ_TIMER16_1, port_80_interrupt, 2);
diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c
deleted file mode 100644
index ce94e50e7e..0000000000
--- a/chip/mec1322/pwm.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for MEC1322 */
-
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-
-/*
- * PWMs that must remain active in low-power idle - MEC1322_PCR_EC_SLP_EN
- * bit mask.
- */
-static uint32_t pwm_keep_awake_mask;
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (enabled) {
-		MEC1322_PWM_CFG(id) |= 0x1;
-		if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-			pwm_keep_awake_mask |=
-				MEC1322_PCR_EC_SLP_EN_PWM(id);
-	} else {
-		MEC1322_PWM_CFG(id) &= ~0x1;
-		pwm_keep_awake_mask &= ~MEC1322_PCR_EC_SLP_EN_PWM(id);
-	}
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return MEC1322_PWM_CFG(pwm_channels[ch].channel) & 0x1;
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	MEC1322_PWM_ON(id) = percent;
-	MEC1322_PWM_OFF(id) = 100 - percent;
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	return MEC1322_PWM_ON(pwm_channels[ch].channel);
-}
-
-uint32_t pwm_get_keep_awake_mask(void)
-{
-	return pwm_keep_awake_mask;
-}
-
-static void pwm_configure(int ch, int active_low, int clock_low)
-{
-	/*
-	 * clock_low=0 selects the 48MHz Ring Oscillator source
-	 * clock_low=1 selects the 100kHz_Clk source
-	 */
-	MEC1322_PWM_CFG(ch) = (15 << 3) |    /* Pre-divider = 16 */
-			      (active_low ? BIT(2) : 0) |
-			      (clock_low  ? BIT(1) : 0);
-}
-
-static void pwm_init(void)
-{
-	int i;
-
-	for (i = 0; i < PWM_CH_COUNT; ++i) {
-		pwm_configure(pwm_channels[i].channel,
-			      pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW,
-			      pwm_channels[i].flags & PWM_CONFIG_ALT_CLOCK);
-		pwm_set_duty(i, 0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/mec1322/pwm_chip.h b/chip/mec1322/pwm_chip.h
deleted file mode 100644
index 9c441aaecd..0000000000
--- a/chip/mec1322/pwm_chip.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1322-specific PWM module for Chrome EC */
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM Channel ID */
-	int channel;
-
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-/*
- * Returns PWMs that must remain active in low-power idle -
- * MEC1322_PCR_EC_SLP_EN bit mask.
- */
-uint32_t pwm_get_keep_awake_mask(void);
-#endif  /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h
deleted file mode 100644
index 7bbd9fb068..0000000000
--- a/chip/mec1322/registers.h
+++ /dev/null
@@ -1,510 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MEC1322 processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-/* Helper function for RAM address aliasing */
-#define MEC1322_RAM_ALIAS(x)   \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
-
-/* EC Chip Configuration */
-#define MEC1322_CHIP_BASE      0x400fff00
-#define MEC1322_CHIP_DEV_ID    REG8(MEC1322_CHIP_BASE + 0x20)
-#define MEC1322_CHIP_DEV_REV   REG8(MEC1322_CHIP_BASE + 0x21)
-
-
-/* Power/Clocks/Resets */
-#define MEC1322_PCR_BASE         0x40080100
-#define MEC1322_PCR_CHIP_SLP_EN  REG32(MEC1322_PCR_BASE + 0x0)
-#define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4)
-#define MEC1322_PCR_EC_SLP_EN    REG32(MEC1322_PCR_BASE + 0x8)
-/* Command all blocks to sleep */
-#define  MEC1322_PCR_EC_SLP_EN_SLEEP	0xe0700ff7
-#define  MEC1322_PCR_EC_SLP_EN_PWM(n)	(1 << ((n) ? (19 + (n)) : 4))
-#define  MEC1322_PCR_EC_SLP_EN_PWM3	BIT(22)
-#define  MEC1322_PCR_EC_SLP_EN_PWM2	BIT(21)
-#define  MEC1322_PCR_EC_SLP_EN_PWM1	BIT(20)
-#define  MEC1322_PCR_EC_SLP_EN_PWM0	BIT(4)
-/* Allow all blocks to request clocks */
-#define  MEC1322_PCR_EC_SLP_EN_WAKE	(~0xe0700ff7)
-#define MEC1322_PCR_EC_CLK_REQ   REG32(MEC1322_PCR_BASE + 0xc)
-#define MEC1322_PCR_HOST_SLP_EN  REG32(MEC1322_PCR_BASE + 0x10)
-/* Command all blocks to sleep */
-#define  MEC1322_PCR_HOST_SLP_EN_SLEEP	0x5f003
-/* Allow all blocks to request clocks */
-#define  MEC1322_PCR_HOST_SLP_EN_WAKE	(~0x5f003)
-#define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14)
-#define MEC1322_PCR_SYS_SLP_CTL  REG32(MEC1322_PCR_BASE + 0x18)
-#define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20)
-#define MEC1322_PCR_EC_SLP_EN2   REG32(MEC1322_PCR_BASE + 0x24)
-/* Mask to command all blocks to sleep */
-#define  MEC1322_PCR_EC_SLP_EN2_SLEEP	0x1ffffff8
-/* Allow all blocks to request clocks */
-#define  MEC1322_PCR_EC_SLP_EN2_WAKE	(~0x03fffff8)
-#define MEC1322_PCR_EC_CLK_REQ2  REG32(MEC1322_PCR_BASE + 0x28)
-#define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c)
-#define MEC1322_PCR_CHIP_OSC_ID  REG32(MEC1322_PCR_BASE + 0x30)
-#define MEC1322_PCR_CHIP_PWR_RST REG32(MEC1322_PCR_BASE + 0x34)
-#define MEC1322_PCR_CHIP_RST_EN  REG32(MEC1322_PCR_BASE + 0x38)
-#define MEC1322_PCR_HOST_RST_EN  REG32(MEC1322_PCR_BASE + 0x3c)
-#define MEC1322_PCR_EC_RST_EN    REG32(MEC1322_PCR_BASE + 0x40)
-#define MEC1322_PCR_EC_RST_EN2   REG32(MEC1322_PCR_BASE + 0x44)
-#define MEC1322_PCR_PWR_RST_CTL  REG32(MEC1322_PCR_BASE + 0x48)
-
-/* Bit defines for MEC1322_PCR_CHIP_PWR_RST */
-#define MEC1322_PWR_RST_STS_VCC1 BIT(6)
-#define MEC1322_PWR_RST_STS_VBAT BIT(5)
-
-/* EC Subsystem */
-#define MEC1322_EC_BASE        0x4000fc00
-#define MEC1322_EC_INT_CTRL    REG32(MEC1322_EC_BASE + 0x18)
-#define MEC1322_EC_TRACE_EN    REG32(MEC1322_EC_BASE + 0x1c)
-#define MEC1322_EC_JTAG_EN     REG32(MEC1322_EC_BASE + 0x20)
-#define MEC1322_EC_WDT_CNT     REG32(MEC1322_EC_BASE + 0x28)
-#define MEC1322_EC_ADC_VREF_PD REG32(MEC1322_EC_BASE + 0x38)
-
-/* Interrupt aggregator */
-#define MEC1322_INT_BASE       0x4000c000
-#define MEC1322_INTx_BASE(x)   (MEC1322_INT_BASE + ((x) - 8) * 0x14)
-#define MEC1322_INT_SOURCE(x)  REG32(MEC1322_INTx_BASE(x) + 0x0)
-#define MEC1322_INT_ENABLE(x)  REG32(MEC1322_INTx_BASE(x) + 0x4)
-#define MEC1322_INT_RESULT(x)  REG32(MEC1322_INTx_BASE(x) + 0x8)
-#define MEC1322_INT_DISABLE(x) REG32(MEC1322_INTx_BASE(x) + 0xc)
-#define MEC1322_INT_BLK_EN     REG32(MEC1322_INT_BASE + 0x200)
-#define MEC1322_INT_BLK_DIS    REG32(MEC1322_INT_BASE + 0x204)
-#define MEC1322_INT_BLK_IRQ    REG32(MEC1322_INT_BASE + 0x208)
-
-
-/* UART */
-#define MEC1322_UART_CONFIG_BASE  0x400f1f00
-#define MEC1322_UART_RUNTIME_BASE 0x400f1c00
-
-#define MEC1322_UART_ACT       REG8(MEC1322_UART_CONFIG_BASE + 0x30)
-#define MEC1322_UART_CFG       REG8(MEC1322_UART_CONFIG_BASE + 0xf0)
-
-/* DLAB=0 */
-#define MEC1322_UART_RB /*R*/  REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_TB /*W*/  REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_IER       REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
-/* DLAB=1 */
-#define MEC1322_UART_PBRG0     REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_PBRG1     REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
-
-#define MEC1322_UART_FCR /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
-#define MEC1322_UART_IIR /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
-#define MEC1322_UART_LCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x3)
-#define MEC1322_UART_MCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x4)
-#define MEC1322_UART_LSR       REG8(MEC1322_UART_RUNTIME_BASE + 0x5)
-#define MEC1322_UART_MSR       REG8(MEC1322_UART_RUNTIME_BASE + 0x6)
-#define MEC1322_UART_SCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x7)
-
-/* Bit defines for MEC1322_UART_LSR */
-#define MEC1322_LSR_TX_EMPTY     BIT(5)
-
-/* GPIO */
-#define MEC1322_GPIO_BASE      0x40081000
-
-static inline uintptr_t gpio_port_base(int port_id)
-{
-	int oct = (port_id / 10) * 8 + port_id % 10;
-	return MEC1322_GPIO_BASE + oct * 0x20;
-}
-#define MEC1322_GPIO_CTL(port, id) REG32(gpio_port_base(port) + (id << 2))
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-
-/* Timer */
-#define MEC1322_TMR16_BASE(x)  (0x40000c00 + (x) * 0x20)
-#define MEC1322_TMR32_BASE(x)  (0x40000c80 + (x) * 0x20)
-
-#define MEC1322_TMR16_CNT(x)   REG32(MEC1322_TMR16_BASE(x) + 0x0)
-#define MEC1322_TMR16_PRE(x)   REG32(MEC1322_TMR16_BASE(x) + 0x4)
-#define MEC1322_TMR16_STS(x)   REG32(MEC1322_TMR16_BASE(x) + 0x8)
-#define MEC1322_TMR16_IEN(x)   REG32(MEC1322_TMR16_BASE(x) + 0xc)
-#define MEC1322_TMR16_CTL(x)   REG32(MEC1322_TMR16_BASE(x) + 0x10)
-#define MEC1322_TMR32_CNT(x)   REG32(MEC1322_TMR32_BASE(x) + 0x0)
-#define MEC1322_TMR32_PRE(x)   REG32(MEC1322_TMR32_BASE(x) + 0x4)
-#define MEC1322_TMR32_STS(x)   REG32(MEC1322_TMR32_BASE(x) + 0x8)
-#define MEC1322_TMR32_IEN(x)   REG32(MEC1322_TMR32_BASE(x) + 0xc)
-#define MEC1322_TMR32_CTL(x)   REG32(MEC1322_TMR32_BASE(x) + 0x10)
-
-
-/* Watchdog */
-#define MEC1322_WDG_BASE       0x40000400
-#define MEC1322_WDG_LOAD       REG16(MEC1322_WDG_BASE + 0x0)
-#define MEC1322_WDG_CTL        REG8(MEC1322_WDG_BASE + 0x4)
-#define MEC1322_WDG_KICK       REG8(MEC1322_WDG_BASE + 0x8)
-#define MEC1322_WDG_CNT        REG16(MEC1322_WDG_BASE + 0xc)
-
-
-/* VBAT */
-#define MEC1322_VBAT_BASE      0x4000a400
-#define MEC1322_VBAT_STS       REG32(MEC1322_VBAT_BASE + 0x0)
-#define MEC1322_VBAT_CE        REG32(MEC1322_VBAT_BASE + 0x8)
-#define MEC1322_VBAT_RAM(x)    REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x))
-
-/* Bit definition for MEC1322_VBAT_STS */
-#define MEC1322_VBAT_STS_WDT	BIT(5)
-
-/* Miscellaneous firmware control fields
- * scratch pad index cannot be more than 16 as
- * mec has 64 bytes = 16 indexes of scratchpad RAM
- */
-#define MEC1322_IMAGETYPE_IDX     15
-
-/* LPC */
-#define MEC1322_LPC_CFG_BASE     0x400f3300
-#define MEC1322_LPC_ACT          REG8(MEC1322_LPC_CFG_BASE + 0x30)
-#define MEC1322_LPC_SIRQ(x)      REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x))
-#define MEC1322_LPC_CFG_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x60)
-#define MEC1322_LPC_EMI_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x64)
-#define MEC1322_LPC_UART_BAR     REG32(MEC1322_LPC_CFG_BASE + 0x68)
-#define MEC1322_LPC_8042_BAR     REG32(MEC1322_LPC_CFG_BASE + 0x78)
-#define MEC1322_LPC_ACPI_EC0_BAR REG32(MEC1322_LPC_CFG_BASE + 0x88)
-#define MEC1322_LPC_ACPI_EC1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x8c)
-#define MEC1322_LPC_ACPI_PM1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x90)
-#define MEC1322_LPC_PORT92_BAR   REG32(MEC1322_LPC_CFG_BASE + 0x94)
-#define MEC1322_LPC_MAILBOX_BAR  REG32(MEC1322_LPC_CFG_BASE + 0x98)
-#define MEC1322_LPC_RTC_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x9c)
-#define MEC1322_LPC_MEM_BAR      REG32(MEC1322_LPC_CFG_BASE + 0xa0)
-#define MEC1322_LPC_MEM_BAR_CFG  REG32(MEC1322_LPC_CFG_BASE + 0xa4)
-
-#define MEC1322_LPC_RT_BASE      0x400f3100
-#define MEC1322_LPC_BUS_MONITOR  REG32(MEC1322_LPC_RT_BASE + 0x4)
-#define MEC1322_LPC_CLK_CTRL     REG32(MEC1322_LPC_RT_BASE + 0x10)
-#define MEC1322_LPC_MEM_HOST_CFG REG32(MEC1322_LPC_RT_BASE + 0xfc)
-
-
-/* EMI */
-#define MEC1322_EMI_BASE       0x400f0100
-#define MEC1322_EMI_H2E_MBX    REG8(MEC1322_EMI_BASE + 0x0)
-#define MEC1322_EMI_E2H_MBX    REG8(MEC1322_EMI_BASE + 0x1)
-#define MEC1322_EMI_MBA0       REG32(MEC1322_EMI_BASE + 0x4)
-#define MEC1322_EMI_MRL0       REG16(MEC1322_EMI_BASE + 0x8)
-#define MEC1322_EMI_MWL0       REG16(MEC1322_EMI_BASE + 0xa)
-#define MEC1322_EMI_MBA1       REG32(MEC1322_EMI_BASE + 0xc)
-#define MEC1322_EMI_MRL1       REG16(MEC1322_EMI_BASE + 0x10)
-#define MEC1322_EMI_MWL1       REG16(MEC1322_EMI_BASE + 0x12)
-#define MEC1322_EMI_ISR        REG16(MEC1322_EMI_BASE + 0x14)
-#define MEC1322_EMI_HCE        REG16(MEC1322_EMI_BASE + 0x16)
-
-#define MEC1322_EMI_RT_BASE    0x400f0000
-#define MEC1322_EMI_ISR_B0     REG8(MEC1322_EMI_RT_BASE + 0x8)
-#define MEC1322_EMI_ISR_B1     REG8(MEC1322_EMI_RT_BASE + 0x9)
-#define MEC1322_EMI_IMR_B0     REG8(MEC1322_EMI_RT_BASE + 0xa)
-#define MEC1322_EMI_IMR_B1     REG8(MEC1322_EMI_RT_BASE + 0xb)
-
-
-/* Mailbox */
-#define MEC1322_MBX_RT_BASE    0x400f2400
-#define MEC1322_MBX_INDEX      REG8(MEC1322_MBX_RT_BASE + 0x0)
-#define MEC1322_MBX_DATA       REG8(MEC1322_MBX_RT_BASE + 0x1)
-
-#define MEC1322_MBX_BASE       0x400f2500
-#define MEC1322_MBX_H2E_MBX    REG8(MEC1322_MBX_BASE + 0x0)
-#define MEC1322_MBX_E2H_MBX    REG8(MEC1322_MBX_BASE + 0x4)
-#define MEC1322_MBX_ISR        REG8(MEC1322_MBX_BASE + 0x8)
-#define MEC1322_MBX_IMR        REG8(MEC1322_MBX_BASE + 0xc)
-#define MEC1322_MBX_REG(x)     REG8(MEC1322_MBX_BASE + 0x10 + (x))
-
-
-/* PWM */
-#define MEC1322_PWM_BASE(x)    (0x40005800 + (x) * 0x10)
-#define MEC1322_PWM_ON(x)      REG32(MEC1322_PWM_BASE(x) + 0x00)
-#define MEC1322_PWM_OFF(x)     REG32(MEC1322_PWM_BASE(x) + 0x04)
-#define MEC1322_PWM_CFG(x)     REG32(MEC1322_PWM_BASE(x) + 0x08)
-
-
-/* ACPI */
-#define MEC1322_ACPI_EC_BASE(x)     (0x400f0c00 + (x) * 0x400)
-#define MEC1322_ACPI_EC_EC2OS(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x100 + (y))
-#define MEC1322_ACPI_EC_STATUS(x)   REG8(MEC1322_ACPI_EC_BASE(x) + 0x104)
-#define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105)
-#define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y))
-
-#define MEC1322_ACPI_PM_RT_BASE     0x400f1400
-#define MEC1322_ACPI_PM1_STS1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x0)
-#define MEC1322_ACPI_PM1_STS2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x1)
-#define MEC1322_ACPI_PM1_EN1        REG8(MEC1322_ACPI_PM_RT_BASE + 0x2)
-#define MEC1322_ACPI_PM1_EN2        REG8(MEC1322_ACPI_PM_RT_BASE + 0x3)
-#define MEC1322_ACPI_PM1_CTL1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x4)
-#define MEC1322_ACPI_PM1_CTL2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x5)
-#define MEC1322_ACPI_PM2_CTL1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x6)
-#define MEC1322_ACPI_PM2_CTL2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x7)
-#define MEC1322_ACPI_PM_EC_BASE     0x400f1500
-#define MEC1322_ACPI_PM_STS         REG8(MEC1322_ACPI_PM_EC_BASE + 0x10)
-
-
-/* 8042 */
-#define MEC1322_8042_BASE      0x400f0400
-#define MEC1322_8042_OBF_CLR   REG8(MEC1322_8042_BASE + 0x0)
-#define MEC1322_8042_H2E       REG8(MEC1322_8042_BASE + 0x100)
-#define MEC1322_8042_E2H       REG8(MEC1322_8042_BASE + 0x100)
-#define MEC1322_8042_STS       REG8(MEC1322_8042_BASE + 0x104)
-#define MEC1322_8042_KB_CTRL   REG8(MEC1322_8042_BASE + 0x108)
-#define MEC1322_8042_PCOBF     REG8(MEC1322_8042_BASE + 0x114)
-#define MEC1322_8042_ACT       REG8(MEC1322_8042_BASE + 0x330)
-
-
-/* FAN */
-#define MEC1322_FAN_BASE       0x4000a000
-#define MEC1322_FAN_SETTING    REG8(MEC1322_FAN_BASE + 0x0)
-#define MEC1322_FAN_PWM_DIVIDE REG8(MEC1322_FAN_BASE + 0x1)
-#define MEC1322_FAN_CFG1       REG8(MEC1322_FAN_BASE + 0x2)
-#define MEC1322_FAN_CFG2       REG8(MEC1322_FAN_BASE + 0x3)
-#define MEC1322_FAN_GAIN       REG8(MEC1322_FAN_BASE + 0x5)
-#define MEC1322_FAN_SPIN_UP    REG8(MEC1322_FAN_BASE + 0x6)
-#define MEC1322_FAN_STEP       REG8(MEC1322_FAN_BASE + 0x7)
-#define MEC1322_FAN_MIN_DRV    REG8(MEC1322_FAN_BASE + 0x8)
-#define MEC1322_FAN_VALID_CNT  REG8(MEC1322_FAN_BASE + 0x9)
-#define MEC1322_FAN_DRV_FAIL   REG16(MEC1322_FAN_BASE + 0xa)
-#define MEC1322_FAN_TARGET     REG16(MEC1322_FAN_BASE + 0xc)
-#define MEC1322_FAN_READING    REG16(MEC1322_FAN_BASE + 0xe)
-#define MEC1322_FAN_BASE_FREQ  REG8(MEC1322_FAN_BASE + 0x10)
-#define MEC1322_FAN_STATUS     REG8(MEC1322_FAN_BASE + 0x11)
-
-
-/* I2C */
-#define MEC1322_I2C0_BASE      0x40001800
-#define MEC1322_I2C1_BASE      0x4000ac00
-#define MEC1322_I2C2_BASE      0x4000b000
-#define MEC1322_I2C3_BASE      0x4000b400
-#define MEC1322_I2C_BASESEP    0x00000400
-#define MEC1322_I2C_ADDR(controller, offset) \
-	(offset + (controller == 0 ? MEC1322_I2C0_BASE : \
-		   MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1)))
-
-/*
- * MEC1322 has five ports distributed among four controllers. Locking must
- * occur by-controller (not by-port).
- */
-enum mec1322_i2c_port {
-	MEC1322_I2C0_0 = 0,      /* Controller 0, port 0 */
-	MEC1322_I2C0_1 = 1,      /* Controller 0, port 1 */
-	MEC1322_I2C1   = 2,      /* Controller 1 */
-	MEC1322_I2C2   = 3,      /* Controller 2 */
-	MEC1322_I2C3   = 4,      /* Controller 3 */
-	MEC1322_I2C_PORT_COUNT,
-};
-
-#define MEC1322_I2C_CTRL(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
-#define MEC1322_I2C_STATUS(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
-#define MEC1322_I2C_OWN_ADDR(ctrl)      REG16(MEC1322_I2C_ADDR(ctrl, 0x4))
-#define MEC1322_I2C_DATA(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x8))
-#define MEC1322_I2C_MASTER_CMD(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0xc))
-#define MEC1322_I2C_SLAVE_CMD(ctrl)     REG32(MEC1322_I2C_ADDR(ctrl, 0x10))
-#define MEC1322_I2C_PEC(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x14))
-#define MEC1322_I2C_DATA_TIM_2(ctrl)    REG8(MEC1322_I2C_ADDR(ctrl, 0x18))
-#define MEC1322_I2C_COMPLETE(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x20))
-#define MEC1322_I2C_IDLE_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x24))
-#define MEC1322_I2C_CONFIG(ctrl)        REG32(MEC1322_I2C_ADDR(ctrl, 0x28))
-#define MEC1322_I2C_BUS_CLK(ctrl)       REG16(MEC1322_I2C_ADDR(ctrl, 0x2c))
-#define MEC1322_I2C_BLK_ID(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x30))
-#define MEC1322_I2C_REV(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x34))
-#define MEC1322_I2C_BB_CTRL(ctrl)       REG8(MEC1322_I2C_ADDR(ctrl, 0x38))
-#define MEC1322_I2C_DATA_TIM(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x40))
-#define MEC1322_I2C_TOUT_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x44))
-#define MEC1322_I2C_SLAVE_TX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x48))
-#define MEC1322_I2C_SLAVE_RX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x4c))
-#define MEC1322_I2C_MASTER_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x50))
-#define MEC1322_I2C_MASTER_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x54))
-
-
-/* Keyboard scan matrix */
-#define MEC1322_KS_BASE        0x40009c00
-#define MEC1322_KS_KSO_SEL     REG32(MEC1322_KS_BASE + 0x4)
-#define MEC1322_KS_KSI_INPUT   REG32(MEC1322_KS_BASE + 0x8)
-#define MEC1322_KS_KSI_STATUS  REG32(MEC1322_KS_BASE + 0xc)
-#define MEC1322_KS_KSI_INT_EN  REG32(MEC1322_KS_BASE + 0x10)
-#define MEC1322_KS_EXT_CTRL    REG32(MEC1322_KS_BASE + 0x14)
-
-
-/* ADC */
-#define MEC1322_ADC_BASE       0x40007c00
-#define MEC1322_ADC_CTRL       REG32(MEC1322_ADC_BASE + 0x0)
-#define MEC1322_ADC_DELAY      REG32(MEC1322_ADC_BASE + 0x4)
-#define MEC1322_ADC_STS        REG32(MEC1322_ADC_BASE + 0x8)
-#define MEC1322_ADC_SINGLE     REG32(MEC1322_ADC_BASE + 0xc)
-#define MEC1322_ADC_REPEAT     REG32(MEC1322_ADC_BASE + 0x10)
-#define MEC1322_ADC_READ(x)    REG32(MEC1322_ADC_BASE + 0x14 + (x) * 0x4)
-
-
-/* Hibernation timer */
-#define MEC1322_HTIMER_BASE    0x40009800
-#define MEC1322_HTIMER_PRELOAD REG16(MEC1322_HTIMER_BASE + 0x0)
-#define MEC1322_HTIMER_CONTROL REG16(MEC1322_HTIMER_BASE + 0x4)
-#define MEC1322_HTIMER_COUNT   REG16(MEC1322_HTIMER_BASE + 0x8)
-
-
-/* SPI */
-#define MEC1322_SPI_BASE(port) (0x40009400 + 0x80 * (port))
-#define MEC1322_SPI_AR(port)   REG8(MEC1322_SPI_BASE(port) + 0x00)
-#define MEC1322_SPI_CR(port)   REG8(MEC1322_SPI_BASE(port) + 0x04)
-#define MEC1322_SPI_SR(port)   REG8(MEC1322_SPI_BASE(port) + 0x08)
-#define MEC1322_SPI_TD(port)   REG8(MEC1322_SPI_BASE(port) + 0x0c)
-#define MEC1322_SPI_RD(port)   REG8(MEC1322_SPI_BASE(port) + 0x10)
-#define MEC1322_SPI_CC(port)   REG8(MEC1322_SPI_BASE(port) + 0x14)
-#define MEC1322_SPI_CG(port)   REG8(MEC1322_SPI_BASE(port) + 0x18)
-
-
-/* DMA */
-#define MEC1322_DMA_BASE            0x40002400
-
-/*
- * Available DMA channels.
- *
- * On MEC1322, any DMA channel may serve any device. Since we have
- * 12 channels and 12 devices, we make each channel dedicated to the
- * device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MEC1322_DMAC_I2C0_SLAVE =  0,
-	MEC1322_DMAC_I2C0_MASTER = 1,
-	MEC1322_DMAC_I2C1_SLAVE =  2,
-	MEC1322_DMAC_I2C1_MASTER = 3,
-	MEC1322_DMAC_I2C2_SLAVE =  4,
-	MEC1322_DMAC_I2C2_MASTER = 5,
-	MEC1322_DMAC_I2C3_SLAVE =  6,
-	MEC1322_DMAC_I2C3_MASTER = 7,
-	MEC1322_DMAC_SPI0_TX =     8,
-	MEC1322_DMAC_SPI0_RX =     9,
-	MEC1322_DMAC_SPI1_TX =    10,
-	MEC1322_DMAC_SPI1_RX =    11,
-
-	/* Channel count */
-	MEC1322_DMAC_COUNT =      12,
-};
-
-/* Registers for a single channel of the DMA controller */
-struct mec1322_dma_chan {
-	uint32_t act;         /* Activate */
-	uint32_t mem_start;   /* Memory start address */
-	uint32_t mem_end;     /* Memory end address */
-	uint32_t dev;         /* Device address */
-	uint32_t ctrl;        /* Control */
-	uint32_t int_status;  /* Interrupt status */
-	uint32_t int_enabled; /* Interrupt enabled */
-	uint32_t pad;
-};
-
-/* Always use mec1322_dma_chan_t so volatile keyword is included! */
-typedef volatile struct mec1322_dma_chan mec1322_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef mec1322_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct mec1322_dma_regs {
-	uint32_t ctrl;
-	uint32_t data;
-	uint32_t pad[2];
-	mec1322_dma_chan_t chan[MEC1322_DMAC_COUNT];
-};
-
-/* Always use mec1322_dma_regs_t so volatile keyword is included! */
-typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t;
-
-#define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE)
-
-/* Bits for DMA channel regs */
-#define MEC1322_DMA_ACT_EN		BIT(0)
-#define MEC1322_DMA_XFER_SIZE(x)	((x) << 20)
-#define MEC1322_DMA_INC_DEV		BIT(17)
-#define MEC1322_DMA_INC_MEM		BIT(16)
-#define MEC1322_DMA_DEV(x)		((x) << 9)
-#define MEC1322_DMA_TO_DEV		BIT(8)
-#define MEC1322_DMA_DONE		BIT(2)
-#define MEC1322_DMA_RUN			BIT(0)
-
-
-/* IRQ Numbers */
-#define MEC1322_IRQ_I2C_0        0
-#define MEC1322_IRQ_I2C_1        1
-#define MEC1322_IRQ_I2C_2        2
-#define MEC1322_IRQ_I2C_3        3
-#define MEC1322_IRQ_DMA_0        4
-#define MEC1322_IRQ_DMA_1        5
-#define MEC1322_IRQ_DMA_2        6
-#define MEC1322_IRQ_DMA_3        7
-#define MEC1322_IRQ_DMA_4        8
-#define MEC1322_IRQ_DMA_5        9
-#define MEC1322_IRQ_DMA_6        10
-#define MEC1322_IRQ_DMA_7        11
-#define MEC1322_IRQ_LPC          12
-#define MEC1322_IRQ_UART         13
-#define MEC1322_IRQ_EMI          14
-#define MEC1322_IRQ_ACPIEC0_IBF  15
-#define MEC1322_IRQ_ACPIEC0_OBF  16
-#define MEC1322_IRQ_ACPIEC1_IBF  17
-#define MEC1322_IRQ_ACPIEC1_OBF  18
-#define MEC1322_IRQ_ACPIPM1_CTL  19
-#define MEC1322_IRQ_ACPIPM1_EN   20
-#define MEC1322_IRQ_ACPIPM1_STS  21
-#define MEC1322_IRQ_8042EM_OBF   22
-#define MEC1322_IRQ_8042EM_IBF   23
-#define MEC1322_IRQ_MAILBOX      24
-#define MEC1322_IRQ_PECI_HOST    25
-#define MEC1322_IRQ_TACH_0       26
-#define MEC1322_IRQ_TACH_1       27
-#define MEC1322_IRQ_ADC_SNGL     28
-#define MEC1322_IRQ_ADC_RPT      29
-#define MEC1322_IRQ_PS2_0        32
-#define MEC1322_IRQ_PS2_1        33
-#define MEC1322_IRQ_PS2_2        34
-#define MEC1322_IRQ_PS2_3        35
-#define MEC1322_IRQ_SPI0_TX      36
-#define MEC1322_IRQ_SPI0_RX      37
-#define MEC1322_IRQ_HTIMER       38
-#define MEC1322_IRQ_KSC_INT      39
-#define MEC1322_IRQ_MAILBOX_DATA 40
-#define MEC1322_IRQ_TIMER16_0    49
-#define MEC1322_IRQ_TIMER16_1    50
-#define MEC1322_IRQ_TIMER16_2    51
-#define MEC1322_IRQ_TIMER16_3    52
-#define MEC1322_IRQ_TIMER32_0    53
-#define MEC1322_IRQ_TIMER32_1    54
-#define MEC1322_IRQ_SPI1_TX      55
-#define MEC1322_IRQ_SPI1_RX      56
-#define MEC1322_IRQ_GIRQ8        57
-#define MEC1322_IRQ_GIRQ9        58
-#define MEC1322_IRQ_GIRQ10       59
-#define MEC1322_IRQ_GIRQ11       60
-#define MEC1322_IRQ_GIRQ12       61
-#define MEC1322_IRQ_GIRQ13       62
-#define MEC1322_IRQ_GIRQ14       63
-#define MEC1322_IRQ_GIRQ15       64
-#define MEC1322_IRQ_GIRQ16       65
-#define MEC1322_IRQ_GIRQ17       66
-#define MEC1322_IRQ_GIRQ18       67
-#define MEC1322_IRQ_GIRQ19       68
-#define MEC1322_IRQ_GIRQ20       69
-#define MEC1322_IRQ_GIRQ21       70
-#define MEC1322_IRQ_GIRQ22       71
-#define MEC1322_IRQ_GIRQ23       72
-#define MEC1322_IRQ_DMA_8        81
-#define MEC1322_IRQ_DMA_9        82
-#define MEC1322_IRQ_DMA_10       83
-#define MEC1322_IRQ_DMA_11       84
-#define MEC1322_IRQ_PWM_WDT3     85
-#define MEC1322_IRQ_RTC          91
-#define MEC1322_IRQ_RTC_ALARM    92
-
-/* Wake pin definitions, defined at board-level */
-#ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-extern const enum gpio_signal hibernate_wake_pins[];
-extern const int hibernate_wake_pins_used;
-#else
-extern enum gpio_signal hibernate_wake_pins[];
-extern int hibernate_wake_pins_used;
-#endif
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c
deleted file mode 100644
index 0c4174cecd..0000000000
--- a/chip/mec1322/spi.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI master module for MEC1322 */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
-#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
-
-#define SPI_DMA_CHANNEL(port) (MEC1322_DMAC_SPI0_RX + (port) * 2)
-
-/* only regular image needs mutex, LFW does not have scheduling */
-/* TODO: Move SPI locking to common code */
-#ifndef LFW
-static struct mutex spi_mutex;
-#endif
-
-static const struct dma_option spi_rx_option[] = {
-	{
-		SPI_DMA_CHANNEL(0),
-		(void *)&MEC1322_SPI_RD(0),
-		MEC1322_DMA_XFER_SIZE(1)
-	},
-	{
-		SPI_DMA_CHANNEL(1),
-		(void *)&MEC1322_SPI_RD(1),
-		MEC1322_DMA_XFER_SIZE(1)
-	},
-};
-
-static int wait_byte(const int port)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	while ((MEC1322_SPI_SR(port) & 0x3) != 0x3) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-static int spi_tx(const int port, const uint8_t *txdata, int txlen)
-{
-	int i;
-	int ret = EC_SUCCESS;
-	uint8_t unused __attribute__((unused)) = 0;
-
-	for (i = 0; i < txlen; ++i) {
-		MEC1322_SPI_TD(port) = txdata[i];
-		ret = wait_byte(port);
-		if (ret != EC_SUCCESS)
-			return ret;
-		unused = MEC1322_SPI_RD(port);
-	}
-
-	return ret;
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
-{
-	int port = spi_device->port;
-	int ret = EC_SUCCESS;
-
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	/* Disable auto read */
-	MEC1322_SPI_CR(port) &= ~BIT(5);
-
-	ret = spi_tx(port, txdata, txlen);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Enable auto read */
-	MEC1322_SPI_CR(port) |= BIT(5);
-
-	if (rxlen != 0) {
-		dma_start_rx(&spi_rx_option[port], rxlen, rxdata);
-		MEC1322_SPI_TD(port) = 0;
-	}
-	return ret;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int port = spi_device->port;
-	int ret = dma_wait(SPI_DMA_CHANNEL(port));
-	uint8_t unused __attribute__((unused)) = 0;
-
-	timestamp_t deadline;
-
-	/* Disable auto read */
-	MEC1322_SPI_CR(port) &= ~BIT(5);
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	/* Wait for FIFO empty SPISR_TXBE */
-	while ((MEC1322_SPI_SR(port) & 0x01) != 0x1) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-
-	dma_disable(SPI_DMA_CHANNEL(port));
-	dma_clear_isr(SPI_DMA_CHANNEL(port));
-	if (MEC1322_SPI_SR(port) & 0x2)
-		unused = MEC1322_SPI_RD(port);
-
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return ret;
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int ret;
-
-#ifndef LFW
-	mutex_lock(&spi_mutex);
-#endif
-	ret = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	if (ret)
-		return ret;
-	ret = spi_transaction_flush(spi_device);
-
-#ifndef LFW
-	mutex_unlock(&spi_mutex);
-#endif
-	return ret;
-}
-
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	int port = spi_device->port;
-
-	if (enable) {
-		gpio_config_module(MODULE_SPI, 1);
-
-		/* Set enable bit in SPI_AR */
-		MEC1322_SPI_AR(port) |= 0x1;
-
-		/* Set SPDIN to 0 -> Full duplex */
-		MEC1322_SPI_CR(port) &= ~(0x3 << 2);
-
-		/* Set CLKPOL, TCLKPH, RCLKPH to 0 */
-		MEC1322_SPI_CC(port) &= ~0x7;
-
-		/* Set LSBF to 0 -> MSB first */
-		MEC1322_SPI_CR(port) &= ~0x1;
-	} else {
-		/* Clear enable bit in SPI_AR */
-		MEC1322_SPI_AR(port) &= ~0x1;
-
-		gpio_config_module(MODULE_SPI, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
deleted file mode 100644
index 6e482d3a78..0000000000
--- a/chip/mec1322/system.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : MEC1322 hardware specific implementation */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "hooks.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-#include "spi.h"
-
-/* Indices for hibernate data registers (RAM backed by VBAT) */
-enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD = 0,    /* General-purpose scratchpad */
-	HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
-	HIBDATA_INDEX_PD0,               /* USB-PD0 saved port state */
-	HIBDATA_INDEX_PD1,               /* USB-PD1 saved port state */
-	HIBDATA_INDEX_PD2,               /* USB-PD2 saved port state */
-};
-
-static void check_reset_cause(void)
-{
-	uint32_t status = MEC1322_VBAT_STS;
-	uint32_t flags = 0;
-	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
-				(MEC1322_PWR_RST_STS_VCC1 |
-				MEC1322_PWR_RST_STS_VBAT);
-
-	/* Clear the reset causes now that we've read them */
-	MEC1322_VBAT_STS |= status;
-	MEC1322_PCR_CHIP_PWR_RST |= rst_sts;
-
-	/*
-	* BIT[6] determine VCC1 reset
-	*/
-	if (rst_sts & MEC1322_PWR_RST_STS_VCC1)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-
-	flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-	MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0;
-
-	if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
-					    EC_RESET_FLAG_HARD |
-					    EC_RESET_FLAG_HIBERNATE)))
-		flags |= EC_RESET_FLAG_WATCHDOG;
-
-	system_set_reset_flags(flags);
-}
-
-int system_is_reboot_warm(void)
-{
-	uint32_t reset_flags;
-	/*
-	* Check reset cause here,
-	* gpio_pre_init is executed faster than system_pre_init
-	*/
-	check_reset_cause();
-	reset_flags = system_get_reset_flags();
-
-	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-		(reset_flags & EC_RESET_FLAG_POWER_ON) ||
-		(reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-		(reset_flags & EC_RESET_FLAG_HARD) ||
-		(reset_flags & EC_RESET_FLAG_SOFT) ||
-		(reset_flags & EC_RESET_FLAG_HIBERNATE))
-		return 0;
-	else
-		return 1;
-}
-
-void system_pre_init(void)
-{
-	/* Enable direct NVIC */
-	MEC1322_EC_INT_CTRL |= 1;
-
-	/* Disable ARM TRACE debug port */
-	MEC1322_EC_TRACE_EN &= ~1;
-
-	/* Deassert nSIO_RESET */
-	MEC1322_PCR_PWR_RST_CTL &= ~BIT(0);
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = flags;
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-noreturn
-void _system_reset(int flags, int wake_from_hibernate)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	if (wake_from_hibernate)
-		save_flags |= EC_RESET_FLAG_HIBERNATE;
-	else if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-	else
-		save_flags |= EC_RESET_FLAG_SOFT;
-
-	chip_save_reset_flags(save_flags);
-
-	/* Trigger watchdog in 1ms */
-	MEC1322_WDG_LOAD = 1;
-	MEC1322_WDG_CTL |= 1;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-void system_reset(int flags)
-{
-	_system_reset(flags, 0);
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "smsc";
-}
-
-const char *system_get_chip_name(void)
-{
-	switch (MEC1322_CHIP_DEV_ID) {
-	case 0x15:
-		return "mec1322";
-	default:
-		return "unknown";
-	}
-}
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char buf[3];
-	uint8_t rev = MEC1322_CHIP_DEV_REV;
-
-	buf[0] = to_hex(rev / 16);
-	buf[1] = to_hex(rev & 0xf);
-	buf[2] = '\0';
-	return buf;
-}
-
-static int bbram_idx_lookup(enum system_bbram_idx idx)
-{
-	switch (idx) {
-	case SYSTEM_BBRAM_IDX_PD0:
-		return HIBDATA_INDEX_PD0;
-	case SYSTEM_BBRAM_IDX_PD1:
-		return HIBDATA_INDEX_PD1;
-	case SYSTEM_BBRAM_IDX_PD2:
-		return HIBDATA_INDEX_PD2;
-	default:
-		return -1;
-	}
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	*value = MEC1322_VBAT_RAM(hibdata);
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	MEC1322_VBAT_RAM(hibdata) = value;
-	return EC_SUCCESS;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD) = value;
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-
-#ifdef CONFIG_HOSTCMD_PD
-	/* Inform the PD MCU that we are going to hibernate. */
-	host_command_pd_request_hibernate();
-	/* Wait to ensure exchange with PD before hibernating. */
-	msleep(100);
-#endif
-
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* Disable interrupts */
-	interrupt_disable();
-	for (i = 0; i <= 92; ++i) {
-		task_disable_irq(i);
-		task_clear_pending_irq(i);
-	}
-
-	for (i = 8; i <= 23; ++i)
-		MEC1322_INT_DISABLE(i) = 0xffffffff;
-
-	MEC1322_INT_BLK_DIS |= 0xffff00;
-
-	/* Power down ADC VREF */
-	MEC1322_EC_ADC_VREF_PD |= 1;
-
-	/* Assert nSIO_RESET */
-	MEC1322_PCR_PWR_RST_CTL |= 1;
-
-	/* Disable UART */
-	MEC1322_UART_ACT &= ~0x1;
-	MEC1322_LPC_ACT &= ~0x1;
-
-	/* Disable JTAG */
-	MEC1322_EC_JTAG_EN &= ~1;
-
-	/* Disable 32KHz clock */
-	MEC1322_VBAT_CE &= ~0x2;
-
-	/* Stop watchdog */
-	MEC1322_WDG_CTL &= ~1;
-
-	/* Stop timers */
-	MEC1322_TMR32_CTL(0) &= ~1;
-	MEC1322_TMR32_CTL(1) &= ~1;
-	MEC1322_TMR16_CTL(0) &= ~1;
-
-	/* Power down ADC */
-	MEC1322_ADC_CTRL &= ~1;
-
-	/* Disable blocks */
-	MEC1322_PCR_CHIP_SLP_EN |= 0x3;
-	MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP;
-	MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
-	MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
-	MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00;
-
-	/* Set sleep state */
-	MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2;
-	CPU_SCB_SYSCTRL |= 0x4;
-
-	/* Setup GPIOs for hibernate */
-	if (board_hibernate_late)
-		board_hibernate_late();
-
-#ifdef CONFIG_USB_PD_PORT_MAX_COUNT
-	/*
-	 * Leave USB-C charging enabled in hibernate, in order to
-	 * allow wake-on-plug. 5V enable must be pulled low.
-	 */
-	switch (board_get_usb_pd_port_count()) {
-#if CONFIG_USB_PD_PORT_MAX_COUNT >= 2
-	case 2:
-		gpio_set_flags(GPIO_USB_C1_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
-		gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 0);
-		/* Fall through */
-#endif
-#if CONFIG_USB_PD_PORT_MAX_COUNT >= 1
-	case 1:
-		gpio_set_flags(GPIO_USB_C0_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
-		gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0);
-		/* Fall through */
-#endif
-	case 0:
-		/* Nothing to do but break */
-		break;
-	default:
-		/* More ports needs to be defined */
-		ASSERT(false);
-		break;
-	}
-#endif /* CONFIG_USB_PD_PORT_MAX_COUNT */
-
-	if (hibernate_wake_pins_used > 0) {
-		for (i = 0; i < hibernate_wake_pins_used; ++i) {
-			const enum gpio_signal pin = hibernate_wake_pins[i];
-
-			gpio_reset(pin);
-			gpio_enable_interrupt(pin);
-		}
-
-		interrupt_enable();
-		task_enable_irq(MEC1322_IRQ_GIRQ8);
-		task_enable_irq(MEC1322_IRQ_GIRQ9);
-		task_enable_irq(MEC1322_IRQ_GIRQ10);
-		task_enable_irq(MEC1322_IRQ_GIRQ11);
-		task_enable_irq(MEC1322_IRQ_GIRQ20);
-	}
-
-	if (seconds || microseconds) {
-		MEC1322_INT_BLK_EN |= BIT(17);
-		MEC1322_INT_ENABLE(17) |= BIT(20);
-		interrupt_enable();
-		task_enable_irq(MEC1322_IRQ_HTIMER);
-		if (seconds > 2) {
-			ASSERT(seconds <= 0xffff / 8);
-			MEC1322_HTIMER_CONTROL = 1;
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 8 + microseconds / 125000);
-		} else {
-			MEC1322_HTIMER_CONTROL = 0;
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 1000000 + microseconds) * 2 / 71;
-		}
-	}
-
-	asm("wfi");
-
-	/* Use 48MHz clock to speed through wake-up */
-	MEC1322_PCR_PROC_CLK_CTL = 1;
-
-	/* Reboot */
-	_system_reset(0, 1);
-
-	/* We should never get here. */
-	while (1)
-		;
-}
-
-void htimer_interrupt(void)
-{
-	/* Time to wake up */
-}
-DECLARE_IRQ(MEC1322_IRQ_HTIMER, htimer_interrupt, 1);
-
-enum ec_image system_get_shrspi_image_copy(void)
-{
-	return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX);
-}
-
-uint32_t system_get_lfw_address(void)
-{
-	uint32_t * const lfw_vector =
-		(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
-
-	return *(lfw_vector + 1);
-}
-
-void system_set_image_copy(enum ec_image copy)
-{
-	MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ?
-				EC_IMAGE_RW : EC_IMAGE_RO;
-}
diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c
deleted file mode 100644
index 2c607d0b72..0000000000
--- a/chip/mec1322/uart.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for MEC1322 */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "lpc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#define TX_FIFO_SIZE 16
-
-static int init_done;
-static int tx_fifo_used;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (MEC1322_UART_IER & BIT(1))
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	MEC1322_UART_IER |= BIT(1);
-	task_trigger_irq(MEC1322_IRQ_UART);
-}
-
-void uart_tx_stop(void)
-{
-	MEC1322_UART_IER &= ~BIT(1);
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/* Wait for transmit FIFO empty */
-	while (!(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * We have no indication of free space in transmit FIFO. To work around
-	 * this, we check transmit FIFO empty bit every 16 characters written.
-	 */
-	return tx_fifo_used != 0 || (MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY);
-}
-
-int uart_tx_in_progress(void)
-{
-	/* return 0: FIFO is empty, 1: FIFO NOT Empty */
-	return !(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY);
-}
-
-int uart_rx_available(void)
-{
-	return MEC1322_UART_LSR & BIT(0);
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE;
-	MEC1322_UART_TB = c;
-}
-
-int uart_read_char(void)
-{
-	return MEC1322_UART_RB;
-}
-
-static void uart_clear_rx_fifo(int channel)
-{
-	MEC1322_UART_FCR = BIT(0) | BIT(1);
-}
-
-/**
- * Interrupt handler for UART
- */
-void uart_ec_interrupt(void)
-{
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-}
-DECLARE_IRQ(MEC1322_IRQ_UART, uart_ec_interrupt, 1);
-
-void uart_init(void)
-{
-	/* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */
-	MEC1322_UART_CFG &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MEC1322_UART_CFG &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MEC1322_UART_LCR |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MEC1322_UART_PBRG0 = 1;
-	MEC1322_UART_PBRG1 = 0;
-
-	/* Set DLAB = 0 */
-	MEC1322_UART_LCR &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MEC1322_UART_LCR |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MEC1322_UART_FCR = BIT(0);
-
-	/* Activate UART */
-	MEC1322_UART_ACT |= BIT(0);
-
-	/*
-	clock_enable_peripheral(CGC_OFFSET_UART, mask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);*/
-
-	gpio_config_module(MODULE_UART, 1);
-
-	/*
-	 * Enable interrupts for UART0.
-	 */
-	uart_clear_rx_fifo(0);
-	MEC1322_UART_IER |= BIT(0);
-	MEC1322_UART_MCR |= BIT(3);
-	MEC1322_INT_ENABLE(15) |= BIT(0);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	task_enable_irq(MEC1322_IRQ_UART);
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	/* Disable the UART interrupt. */
-	task_disable_irq(MEC1322_IRQ_UART);  /* NVIC interrupt for UART=13 */
-
-	/*
-	 * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt
-	 * with the flags defined in the gpio.inc file.
-	 */
-	gpio_reset(GPIO_UART0_RX);
-
-	/* power-down/de-activate UART0 */
-	MEC1322_UART_ACT &= ~BIT(0);
-
-	/* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */
-	MEC1322_INT_SOURCE(8) = (1<<18);
-
-	/* Enable GPIO interrupts on the UART0 RX pin. */
-	gpio_enable_interrupt(GPIO_UART0_RX);
-}
-
-
-void uart_exit_dsleep(void)
-{
-	/*
-	 * If the UART0 RX GPIO interrupt has not fired, then no edge has been
-	 * detected. Disable the GPIO interrupt so that switching the pin over
-	 * to a UART pin doesn't inadvertently cause a GPIO edge interrupt.
-	 * Note: we can't disable this interrupt if it has already fired
-	 * because then the IRQ will not run at all.
-	 */
-	if (!(BIT(18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */
-		gpio_disable_interrupt(GPIO_UART0_RX);
-
-	/* Configure UART0 pins for use in UART peripheral. */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Clear pending interrupts on UART peripheral and enable interrupts. */
-	uart_clear_rx_fifo(0);
-	task_enable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART = 13 */
-
-	/* power-up/activate UART0 */
-	MEC1322_UART_ACT |= BIT(0);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Activity seen on UART RX pin while UART was disabled for deep sleep.
-	 * The console won't see that character because the UART is disabled,
-	 * so we need to inform the clock module of UART activity ourselves.
-	 */
-	clock_refresh_console_in_use();
-
-	/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART0_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mec1322/util/pack_ec.py b/chip/mec1322/util/pack_ec.py
deleted file mode 100755
index 9783ffb2d5..0000000000
--- a/chip/mec1322/util/pack_ec.py
+++ /dev/null
@@ -1,248 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# A script to pack EC binary into SPI flash image for MEC1322
-# Based on MEC1322_ROM_Doc_Rev0.5.pdf.
-
-import argparse
-import hashlib
-import os
-import struct
-import subprocess
-import tempfile
-
-LOAD_ADDR = 0x100000
-HEADER_SIZE = 0x140
-SPI_CLOCK_LIST = [48, 24, 12, 8]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b]
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
-
-def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
-
-def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return struct.unpack('<I', s)[0]
-
-def GetPayloadFromOffset(payload_file,offset):
-  """Read payload and pad it to 64-byte aligned."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % 64
-  if rem_len:
-    payload += b'\0' * (64 - rem_len)
-  return payload
-
-def GetPayload(payload_file):
-  """Read payload and pad it to 64-byte aligned."""
-  return GetPayloadFromOffset(payload_file, 0)
-
-def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
-
-def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
-
-def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
-
-def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
-
-def BuildHeader(args, payload_len, rorofile):
-  # Identifier and header version
-  header = bytearray(b'CSMS\0')
-
-  PadZeroTo(header, 0x6)
-  header.append(GetSpiClockParameter(args))
-  header.append(GetSpiReadCmdParameter(args))
-
-  header.extend(struct.pack('<I', LOAD_ADDR))
-  header.extend(struct.pack('<I', GetEntryPoint(rorofile)))
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  header.extend(struct.pack('<I', args.payload_offset))
-
-  exp, modulus = GetPublicKey(args.payload_key)
-  PadZeroTo(header, 0x20)
-  header.extend(exp)
-  PadZeroTo(header, 0x30)
-  header.extend(modulus)
-  PadZeroTo(header, HEADER_SIZE)
-
-  return header
-
-def SignByteArray(data, pem_file):
-  hash_file = tempfile.mkstemp(prefix='pack_ec.')[1]
-  sign_file = tempfile.mkstemp(prefix='pack_ec.')[1]
-  try:
-      with open(hash_file, 'wb') as f:
-        hasher = hashlib.sha256()
-        hasher.update(data)
-        f.write(hasher.digest())
-      subprocess.run(['openssl', 'rsautl', '-sign', '-inkey', pem_file,
-                      '-keyform', 'PEM', '-in', hash_file, '-out', sign_file],
-                     check=True)
-      with open(sign_file, 'rb') as f:
-        signed = f.read()
-        return bytearray(reversed(signed))
-  finally:
-    os.remove(hash_file)
-    os.remove(sign_file)
-
-def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  if args.chip_select != 0:
-    tag[2] |= 0x80
-  tag.append(Crc8(0, tag))
-  return tag
-
-def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """TODO:Clean up to get rid of Temp file and just use memory
-  to save data"""
-  """Create a temp file with the
-  first image_size bytes from the rorw file and the
-  bytes from the loader_file appended
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1:
-    pro = fin1.read()
-  fo.write(pro)
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-  fo.write(ro)
-  fo.close()
-  return fo.name
-
-def parseargs():
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-                      help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-                      metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--header_key",
-                      help="PEM key file for signing header",
-                      default="rsakey_sign_header.pem")
-  parser.add_argument("--payload_key",
-                      help="PEM key file for signing payload",
-                      default="rsakey_sign_payload.pem")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in MB",
-                      default=4)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x170000)
-  parser.add_argument("-p", "--payload_offset", type=int,
-                      help="The offset of payload from the header",
-                      default=0x240)
-  parser.add_argument("-r", "--rwpayload_loc", type=int,
-                      help="The offset of payload from the header",
-                      default=0x190000)
-  parser.add_argument("-z", "--romstart", type=int,
-                      help="The first location to output of the rom",
-                      default=0)
-  parser.add_argument("-c", "--chip_select", type=int,
-                      help="Chip select signal to use, either 0 or 1.",
-                      default=0)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image.",
-                      default=(96 * 1024))
-  return parser.parse_args()
-
-def main():
-  args = parseargs()
-
-  spi_size = args.spi_size * 1024
-  args.header_loc = spi_size - (128 * 1024)
-  args.rwpayload_loc = spi_size - (256 * 1024)
-  args.romstart = spi_size - (256 * 1024)
-
-  spi_list = []
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  payload = GetPayload(rorofile)
-  payload_len = len(payload)
-  payload_signature = SignByteArray(payload, args.payload_key)
-  header = BuildHeader(args, payload_len, rorofile)
-  header_signature = SignByteArray(header, args.header_key)
-  tag = BuildTag(args)
-  # truncate the RW to 128k
-  payloadrw = GetPayloadFromOffset(args.input,args.image_size)[:128*1024]
-  os.remove(rorofile)           # clean up the temp file
-
-  spi_list.append((args.header_loc, header, "header"))
-  spi_list.append((args.header_loc + HEADER_SIZE, header_signature, "header_signature"))
-  spi_list.append((args.header_loc + args.payload_offset, payload, "payload"))
-  spi_list.append((args.header_loc + args.payload_offset + payload_len,
-                   payload_signature, "payload_signature"))
-  spi_list.append((spi_size - 256, tag, "tag"))
-  spi_list.append((args.rwpayload_loc, payloadrw, "payloadrw"))
-
-
-  spi_list = sorted(spi_list)
-
-  with open(args.output, 'wb') as f:
-    addr = args.romstart
-    for s in spi_list:
-      assert addr <= s[0]
-      if addr < s[0]:
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-      f.write(s[1])
-      addr += len(s[1])
-    if addr < spi_size:
-      f.write(b'\xff' * (spi_size - addr))
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/mec1322/util/rsakey_sign_header.pem b/chip/mec1322/util/rsakey_sign_header.pem
deleted file mode 100644
index 37799ebbec..0000000000
--- a/chip/mec1322/util/rsakey_sign_header.pem
+++ /dev/null
@@ -1,28 +0,0 @@
------BEGIN PRIVATE KEY-----
-MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQCd0knJ+sVzkO40
-g7VguqpqrmwqgYPfgq3m7GHGitWgxjM/JDpKaOvq4G9O+yYUD/75V5GZJkRY0iE8
-MJCCvSkyoFHcCP0jvma9G/c13wXfLPGUunrJnV+Wzwy5+S1MXdax532gK9qeUmOB
-HpIttkFRl3qhVHu9to2dbsx1S/AIA0GIPAINkcZxfRCAcheIoqK/oMqse+EDS9Zm
-6frha9oS1+iRlqMPYKrOgWTKnkY3H/4M/HFj90hVzxun3qQj0mo3EdYoSrbCnyjG
-JNjnuCdSEODmG5+FCTVWCfl/AolYmOWjMfCnfX7/HlfhOY+fOR91FKrgOjWHHf3a
-0FhdUZDNAgMBAAECggEBAJKea6j2jXu42GP3PIk5wdrMYnb2zeHXEOJpFskR8Dem
-CrQNXw4D/bC+gwo4Lv8SgUl6PiyurW5rAS9e2tJrFBwRbxthSnNrjxz/HyJwKI9W
-vLT0reAikUyU3Hjl8lxxDWVH76DfPQI6/nBVS26mVHaNqQK6bx8nutbYuZ/7RWra
-zatdjrl29D0E/xTva0S4AUPI7DmflwS6YbfVlTsyhnwphaEwD7eCDhD9h4nGQG8z
-0WKDN2X1F7CmjrK9fy7SCHO9SKc3WNSjp2Dc0ImF2k72Mfw5jtOs81lczktztPy0
-gv4x6Tg0ws4Et9eI6Ub80tAZ+wQ5Vj+wzExMOp4K5KECgYEA0jz5IsRmie6y/WRG
-6dI98nnyLoISIQue8xOA5J/OUyYfHn9CgJvGslRVg2mmSQ9GPkaMIN0dADvB6Tsh
-XelAZZjnAo8pSyahz3OdcdgP6xksMjtKReXiLqu0ntfQS42nQDYNvRd2/clrYYRN
-SlijT53QMqI4DSMz+0rLqUwvRskCgYEAwCyEEJ1Z/CI2ONN1tIEnJSuzZRYxlwNL
-mVXx03ZSVi+L2MOMJjiCoeUZ/MVSacW+Elg6aU3U1GdOhNfQaPZJNqISACtm314Y
-Xi9bMXegyQp3uBRnEah82ejm8hloOAOKZNgbqgt9o6FDrsccw3udIgzsgPY4koUK
-1fNrDPJ5x+UCgYBwlEH8whr+hZnHYqkukGynqXFsQi6fD3AATlNZGdIMaH+FfzQH
-VmNiHxLjmfF3cfx1YKWs+3qKI3XFBOrrNPpM7UHW9v5vxbIkOo725XIwvHwUMfel
-0mH6B+ximsJpkuMa2VcmCKipYfBkecpBo5FgEuvoEUHelxlA2V6Ru8AdMQKBgQC/
-uanoiZQFIHzIJPABrfjH9Nl9uK6w4vDBgiVJu3pZ0gXLtQxV9Xse2dsbfCHEtSv0
-UWG1PZlgb9C+aDHdBhn1D6y1zpdLsizNiqGIsLkQ2gim9nP+AgLNxLbkQsTfXWjt
-Q04WUHCAl5tW+/+OZ/1Uw2ARKZU3WNR+r+PVfvRQoQKBgQCjksWLe3Zx2yxnUenz
-vaY09UTt42rawbUkm+xpNzOt7K1TudRODe444XG9fFgkNa5HPiAENoZ91Jv223x8
-Fi2SjfGA6/r/J1ash4cDcJLogTEP27YyJyhwXZFKtjfFeD3e2hvcMFMDG4EBHHXd
-Bv/r6+6E+f30Y4bN3ZgK/rN6Tg==
------END PRIVATE KEY-----
diff --git a/chip/mec1322/util/rsakey_sign_payload.pem b/chip/mec1322/util/rsakey_sign_payload.pem
deleted file mode 100644
index 6845097749..0000000000
--- a/chip/mec1322/util/rsakey_sign_payload.pem
+++ /dev/null
@@ -1,28 +0,0 @@
------BEGIN PRIVATE KEY-----
-MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQDQaeNJ6+a/KXhs
-/0Xa2coG+4d+pc+4qs4O/6caxAtzr1YP155C4QxqfZw0DETreK7K/kgSgOJ6Q1gW
-Yo88Fb4foxVYJbV2Bb+mdNlaHP/o6TrvBmqdsIjP5u1FwtmjquaewL2E3T4rHCXl
-QgM7AQXAFzKt2HeaMeHvC2t+x/AganhfztOpqhGTL6lHiLC55SPNkWCb3GokotbL
-Ul7q+wLSTpKS0vNuigjGVBVuV7YrwWhehOoLuV5FDMXHlMTemYH6+V5j78ZtSrXm
-0RmKAKXoO+HbKbgALICUw5kzxXLSAoHx2rXLlou9I00olxsWir1lokxaWa1La3wA
-pr214pxXAgMBAAECggEAdsXxrz4OeaEDrXJpeAioNwR/unB6ie5lkmyl6f4R3LLu
-5AZofgrNTZ8aNxtK57sWOj9iCZGEAFOCzvcKVB68BEGnt11+Ja2vBAkRmWZvfWf1
-myTX+9gQkBM144zhBYIu/ggvuZlwhZb8DcRqHOU/RrKxwhtcRfbpoJasg0skkQO0
-bU2hwSu4kM+T2diyXp4V1PR4vrxZPNQ+B8sWxWKJs58+3NdWswwe9NcFQla0QTFz
-7MIlMJNlJgTXjSYC8TjDlBlevwE5HoikpfSSvFr4uouyfpfWBxNFd8Tm/yFSTUqY
-XO3oyU/NLK+BN7Sxj6Cs1Fx65yhMCmsqGQqCNOz2OQKBgQD4gIF6vVduyKfPV3EE
-4lhFktlFRXeR+z9LXpGth3vwNN0XpPql1jr8hYPQqpSKefZRF5r8hLjt2ZaLDbnb
-iVYwHxbXRuF5P6qsaSy1uVYG4og5LV5ddSBzf+/MhDInQk/O5tdvOrgQfcJzRJRg
-MSx5uzs66r8/AFKCVTB/ptNgzQKBgQDWs7qqaHNHGRRfegRhwkkDvhRAMQKWsgL7
-kTWw/qW+b8mRYhCC4JvbU+OeFkf5kejGpFgDuvB4eH+rsPRVU8jSWZXrMKjGdZN1
-T6fFa5vz1VsRNhiVU3F2jfXTY5t7qQ18jEoMQxGxdGJy52Py+3N34ZWNS4cifLNS
-rYjZnQmhswKBgD3rd1foGgMmyHmnpie7ZpdfcfgKyTJ80larZ80/dyhxY63ik/oC
-mYwWkLPL7Vtb7H5kTWAiihnqH9LiRq9nVyyCcqSNqt0VeiefxV46oi7w/1SP83WC
-G+XruQrS3dRed5hseL3kebzSOUOTkQ0u85AZkTarC6BdKjIDnCQSo5T5AoGAKNep
-087o1waTVJJOkRY3c4nOKmPoXShh3t9BunjGqNJ1Ir3n7C20GGX9783HRVeXU2ph
-/9uo8RHjH5Ma97xngHRgS4xHHvGw6mkLvkd5NEpK95w10vo7pFTfBaZ2JnEDSsUZ
-NPnxPLOqIreX0No6nfyAyY8rlsjoB/tRBCyWb3cCgYEAgzJCllzahDvgCbmjI9Km
-h7mUVc5U2fQR5B/WRa5iTSlQd+O4TXna7ZCxKDyYlesSBAiKanX0669Iri6cu4S6
-gMc7MJmm3VrnZGXoukSv3Zyot+hkaFrZTrXAIQiuYDK6YC5OK7kqM+DqtJOWUsfg
-itdiqPKeYtViDQkxqJ1nkSw=
------END PRIVATE KEY-----
diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c
deleted file mode 100644
index ad93fb1240..0000000000
--- a/chip/mec1322/watchdog.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "watchdog.h"
-
-void watchdog_reload(void)
-{
-	MEC1322_WDG_KICK = 1;
-
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Reload the auxiliary timer */
-	MEC1322_TMR16_CTL(0) &= ~BIT(5);
-	MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-	MEC1322_TMR16_CTL(0) |= BIT(5);
-#endif
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-#ifdef CONFIG_WATCHDOG_HELP
-	uint32_t val;
-
-	/*
-	 * Watchdog does not warn us before expiring. Let's use a 16-bit
-	 * timer as an auxiliary timer.
-	 */
-
-	/* Stop the auxiliary timer if it's running */
-	MEC1322_TMR16_CTL(0) &= ~BIT(5);
-
-	/* Enable auxiliary timer */
-	MEC1322_TMR16_CTL(0) |= BIT(0);
-
-	val = MEC1322_TMR16_CTL(0);
-
-	/* Pre-scale = 48000 -> 1kHz -> Period = 1ms */
-	val = (val & 0xffff) | (47999 << 16);
-
-	/* No auto restart */
-	val &= ~BIT(3);
-
-	/* Count down */
-	val &= ~BIT(2);
-
-	MEC1322_TMR16_CTL(0) = val;
-
-	/* Enable interrupt from auxiliary timer */
-	MEC1322_TMR16_IEN(0) |= 1;
-	task_enable_irq(MEC1322_IRQ_TIMER16_0);
-	MEC1322_INT_ENABLE(23) |= BIT(0);
-	MEC1322_INT_BLK_EN |= BIT(23);
-
-	/* Load and start the auxiliary timer */
-	MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-	MEC1322_TMR16_CNT(0) |= BIT(5);
-#endif
-
-	/* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */
-	MEC1322_WDG_LOAD = CONFIG_WATCHDOG_PERIOD_MS * 1000 / 1007;
-
-	/* Start watchdog */
-	MEC1322_WDG_CTL |= 1;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_WATCHDOG_HELP
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	/* Clear status */
-	MEC1322_TMR16_STS(0) |= 1;
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void) __attribute__((naked));
-void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveninently saves
-		      * R0=LR so we can pass it to task_resched_if_needed. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0, lr}\n"
-		     "b task_resched_if_needed\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(MEC1322_IRQ_TIMER16_0)
-	__attribute__((section(".rodata.irqprio")))
-		= {MEC1322_IRQ_TIMER16_0, 0}; /* put the watchdog at the
-						 highest priority */
-#endif
diff --git a/chip/mt_scp/build.mk b/chip/mt_scp/build.mk
deleted file mode 100644
index 3e8f63b5a2..0000000000
--- a/chip/mt_scp/build.mk
+++ /dev/null
@@ -1,21 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# SCP specific files build
-#
-
-# Required chip modules
-chip-y=
-
-CPPFLAGS+=-Ichip/$(CHIP)/$(CHIP_VARIANT)
-dirs-y+=chip/$(CHIP)/$(CHIP_VARIANT)
-# Each chip variant can provide specific build.mk if any
--include chip/$(CHIP)/$(CHIP_VARIANT)/build.mk
-
-ifeq ($(CHIP_VARIANT),$(filter $(CHIP_VARIANT),mt8192 mt8195))
-CPPFLAGS+=-Ichip/$(CHIP)/rv32i_common
-dirs-y+=chip/$(CHIP)/rv32i_common
-include chip/$(CHIP)/rv32i_common/build.mk
-endif
diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h
deleted file mode 100644
index 112920a4c6..0000000000
--- a/chip/mt_scp/config_chip.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifdef CHIP_VARIANT_MT8183
-#include "mt8183/config_chip.h"
-#endif
-
-#if defined(CHIP_VARIANT_MT8192) || defined(CHIP_VARIANT_MT8195)
-#include "rv32i_common/config_chip.h"
-#endif
diff --git a/chip/mt_scp/mt8183/audio_codec_wov.c b/chip/mt_scp/mt8183/audio_codec_wov.c
deleted file mode 100644
index 0a4684f909..0000000000
--- a/chip/mt_scp/mt8183/audio_codec_wov.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "hooks.h"
-#include "memmap.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/* VIF FIFO irq is triggered above this level */
-#define WOV_TRIGGER_LEVEL 160
-
-int audio_codec_wov_enable_notifier(void)
-{
-	SCP_VIF_FIFO_DATA_THRE = WOV_TRIGGER_LEVEL + 1;
-	SCP_VIF_FIFO_EN |= VIF_FIFO_IRQ_EN;
-
-	task_enable_irq(SCP_IRQ_MAD_FIFO);
-
-	return EC_SUCCESS;
-}
-
-int audio_codec_wov_disable_notifier(void)
-{
-	SCP_VIF_FIFO_EN &= ~VIF_FIFO_IRQ_EN;
-
-	task_disable_irq(SCP_IRQ_MAD_FIFO);
-
-	return EC_SUCCESS;
-}
-
-int audio_codec_wov_enable(void)
-{
-	SCP_VIF_FIFO_EN = 0;
-
-	SCP_RXIF_CFG0 = (RXIF_CFG0_RESET_VAL & ~RXIF_RGDL2_MASK) |
-			RXIF_RGDL2_DMIC_16K;
-	SCP_RXIF_CFG1 = RXIF_CFG1_RESET_VAL;
-
-	SCP_VIF_FIFO_EN |= VIF_FIFO_RSTN;
-
-	return EC_SUCCESS;
-}
-
-int audio_codec_wov_disable(void)
-{
-	SCP_VIF_FIFO_EN = 0;
-
-	return EC_SUCCESS;
-}
-
-static size_t wov_fifo_level(void)
-{
-	uint32_t fifo_status = SCP_VIF_FIFO_STATUS;
-
-	if (!(fifo_status & VIF_FIFO_VALID))
-		return 0;
-
-	if (fifo_status & VIF_FIFO_FULL)
-		return VIF_FIFO_MAX;
-
-	return VIF_FIFO_LEVEL(fifo_status);
-}
-
-int32_t audio_codec_wov_read(void *buf, uint32_t count)
-{
-	int16_t *out = buf;
-	uint8_t gain = 1;
-
-	if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN))
-		audio_codec_dmic_get_gain_idx(0, &gain);
-
-	count >>= 1;
-
-	while (count-- && wov_fifo_level()) {
-		if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN))
-			*out++ = audio_codec_s16_scale_and_clip(
-					SCP_VIF_FIFO_DATA, gain);
-		else
-			*out++ = SCP_VIF_FIFO_DATA;
-	}
-
-	return (void *)out - buf;
-}
-
-static void wov_fifo_interrupt_handler(void)
-{
-#ifdef HAS_TASK_WOV
-	task_wake(TASK_ID_WOV);
-#endif
-
-	audio_codec_wov_disable_notifier();
-
-	/* Read to clear */
-	SCP_VIF_FIFO_IRQ_STATUS;
-}
-DECLARE_IRQ(SCP_IRQ_MAD_FIFO, wov_fifo_interrupt_handler, 2);
-
-int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr)
-{
-	return memmap_ap_to_scp(ap_addr, ec_addr);
-}
diff --git a/chip/mt_scp/mt8183/build.mk b/chip/mt_scp/mt8183/build.mk
deleted file mode 100644
index 206563a7c5..0000000000
--- a/chip/mt_scp/mt8183/build.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CORE:=cortex-m
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# Required chip modules
-chip-y+=$(CHIP_VARIANT)/clock.o
-chip-y+=$(CHIP_VARIANT)/gpio.o
-chip-y+=$(CHIP_VARIANT)/memmap.o
-chip-y+=$(CHIP_VARIANT)/system.o
-chip-y+=$(CHIP_VARIANT)/uart.o
-
-# Optional chip modules
-chip-$(CONFIG_AUDIO_CODEC_WOV)+=$(CHIP_VARIANT)/audio_codec_wov.o
-chip-$(CONFIG_COMMON_TIMER)+=$(CHIP_VARIANT)/hrtimer.o
-chip-$(CONFIG_I2C)+=$(CHIP_VARIANT)/i2c.o
-chip-$(CONFIG_IPI)+=$(CHIP_VARIANT)/ipi.o $(CHIP_VARIANT)/ipi_table.o
-chip-$(CONFIG_SPI)+=$(CHIP_VARIANT)/spi.o
-chip-$(CONFIG_WATCHDOG)+=$(CHIP_VARIANT)/watchdog.o
-
-ifeq ($(CONFIG_IPI),y)
-$(out)/RO/chip/$(CHIP)/$(CHIP_VARIANT)/ipi_table.o: $(out)/ipi_table_gen.inc
-$(out)/RW/chip/$(CHIP)/$(CHIP_VARIANT)/ipi_table.o: $(out)/ipi_table_gen.inc
-endif
-
-ifeq ($(CONFIG_AUDIO_CODEC_WOV),y)
-HOTWORD_PRIVATE_LIB:=private/libkukui_scp_google_hotword_dsp_api.a
-ifneq ($(wildcard $(HOTWORD_PRIVATE_LIB)),)
-LDFLAGS_EXTRA+=$(HOTWORD_PRIVATE_LIB)
-HAVE_PRIVATE_AUDIO_CODEC_WOV_LIBS:=y
-endif
-endif
diff --git a/chip/mt_scp/mt8183/clock.c b/chip/mt_scp/mt8183/clock.c
deleted file mode 100644
index 3029a00a01..0000000000
--- a/chip/mt_scp/mt8183/clock.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-
-#define ULPOSC_DIV_MAX (1 << OSC_DIV_BITS)
-#define ULPOSC_CALI_MAX (1 << OSC_CALI_BITS)
-
-void clock_init(void)
-{
-	/* Set VREQ to HW mode */
-	SCP_CPU_VREQ = CPU_VREQ_HW_MODE;
-	SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
-
-	/* Set DDREN auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* Initialize 26MHz system clock counter reset value to 1. */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1);
-	/* Initialize high frequency ULPOSC counter reset value to 1. */
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1);
-	/* Initialize sleep mode control VREQ counter. */
-	SCP_CLK_SLEEP_CTRL =
-		(SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1);
-
-	/* Set normal wake clock */
-	SCP_WAKE_CKSW &= ~WAKE_CKSW_SEL_NORMAL_MASK;
-
-	/* Enable fast wakeup support */
-	SCP_CLK_SLEEP = 0;
-	SCP_CLK_ON_CTRL = (SCP_CLK_ON_CTRL & ~HIGH_FINAL_VAL_MASK) |
-			  HIGH_FINAL_VAL_DEFAULT;
-	SCP_FAST_WAKE_CNT_END =
-		(SCP_FAST_WAKE_CNT_END & ~FAST_WAKE_CNT_END_MASK) |
-		FAST_WAKE_CNT_END_DEFAULT;
-
-	/* Set slow wake clock */
-	SCP_WAKE_CKSW = (SCP_WAKE_CKSW & ~WAKE_CKSW_SEL_SLOW_MASK) |
-			WAKE_CKSW_SEL_SLOW_DEFAULT;
-
-	/* Select CLK_HIGH as wakeup clock */
-	SCP_CLK_SLOW_SEL = (SCP_CLK_SLOW_SEL &
-			    ~(CKSW_SEL_SLOW_MASK | CKSW_SEL_SLOW_DIV_MASK)) |
-			   CKSW_SEL_SLOW_ULPOSC2_CLK;
-
-	/*
-	 * Set legacy wakeup
-	 *   - disable SPM sleep control
-	 *   - disable SCP sleep mode
-	 */
-	SCP_CLK_SLEEP_CTRL &= ~(EN_SLEEP_CTRL | SPM_SLEEP_MODE);
-
-	task_enable_irq(SCP_IRQ_CLOCK);
-	task_enable_irq(SCP_IRQ_CLOCK2);
-}
-
-static void scp_ulposc_config(int osc, uint32_t osc_div, uint32_t osc_cali)
-{
-	uint32_t val;
-
-	/* Clear all bits */
-	val = 0;
-	/* Enable CP */
-	val |= OSC_CP_EN;
-	/* Set div */
-	val |= osc_div << 17;
-	/* F-band = 0, I-band = 4 */
-	val |= 4 << 6;
-	/* Set calibration */
-	val |= osc_cali;
-	/* Set control register 1 */
-	AP_ULPOSC_CON02(osc) = val;
-	/* Set control register 2, enable div2 */
-	AP_ULPOSC_CON13(osc) |= OSC_DIV2_EN;
-}
-
-static inline void busy_udelay(int usec)
-{
-	/*
-	 * Delaying by busy-looping, for place that can't use udelay because of
-	 * the clock not configured yet. The value 28 is chosen approximately
-	 * from experiment.
-	 */
-	volatile int i = usec * 28;
-
-	while (i--)
-		;
-}
-
-static unsigned int scp_measure_ulposc_freq(int osc)
-{
-	unsigned int result = 0;
-	int cnt;
-
-	/* Before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
-
-	/* Select source, bit[21:16] = clk_src */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
-
-	/* Set meter divisor to 1, bit[31:24] = b00000000 */
-	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
-			    MISC_METER_DIV_1;
-
-	/* Enable frequency meter, without start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
-
-	/* Trigger frequency meter start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
-
-	/*
-	 * Frequency meter counts cycles in 1 / (26 * 1024) second period.
-	 *   freq_in_hz = freq_counter * 26 * 1024
-	 *
-	 * The hardware takes 38us to count cycles. Delay up to 100us,
-	 * as busy_udelay may not be accurate when sysclk is not 26Mhz
-	 * (e.g. when recalibrating/measuring after boot).
-	 */
-	for (cnt = 100; cnt; cnt--) {
-		busy_udelay(1);
-		if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
-			result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
-			break;
-		}
-	}
-
-	/* Disable freq meter */
-	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
-	return result;
-}
-
-static inline int signum(int v)
-{
-	return (v > 0) - (v < 0);
-}
-
-static inline int abs(int v)
-{
-	return (v >= 0) ? v : -v;
-}
-
-static int scp_ulposc_config_measure(int osc, int div, int cali)
-{
-	int freq;
-
-	scp_ulposc_config(osc, div, cali);
-	freq = scp_measure_ulposc_freq(osc);
-	CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n",
-		osc + 1, div, cali, freq,
-		freq * 26 * 1000 / 1024);
-
-	return freq;
-}
-
-/**
- * Calibrate ULPOSC to target frequency.
- *
- * @param osc           0:ULPOSC1, 1:ULPOSC2
- * @param target_mhz    Target frequency to set
- * @return              Frequency counter output
- *
- */
-static int scp_calibrate_ulposc(int osc, int target_mhz)
-{
-	int target_freq = DIV_ROUND_NEAREST(target_mhz * 1024, 26);
-	struct ulposc {
-		int div;        /* frequency divisor/multiplier */
-		int cali;       /* variable resistor calibrator */
-		int freq;       /* frequency counter measure result */
-	} curr, prev = {0};
-	enum { STAGE_DIV, STAGE_CALI } stage = STAGE_DIV;
-	int param, param_max;
-
-	curr.div = ULPOSC_DIV_MAX / 2;
-	curr.cali = ULPOSC_CALI_MAX / 2;
-
-	param = curr.div;
-	param_max = ULPOSC_DIV_MAX;
-
-	/*
-	 * In the loop below, linear search closest div value to get desired
-	 * frequency counter value. Then adjust cali to get a better result.
-	 * Note that this doesn't give optimal output frequency, but it's
-	 * usually close enough.
-	 * TODO(b:120176040): See if we can efficiently calibrate the clock with
-	 * more precision by exploring more of the cali/div space.
-	 *
-	 * The frequency function follows. Note that f is positively correlated
-	 * with both div and cali:
-	 * f(div, cali) = k1 * (div + k2) / R(cali) * C
-	 * Where:
-	 *   R(cali) = k3 / (1 + k4 * (cali - k4))
-	 */
-	while (1) {
-		curr.freq = scp_ulposc_config_measure(osc, curr.div, curr.cali);
-
-		if (!curr.freq)
-			return 0;
-
-		/*
-		 * If previous and current are on either side of the desired
-		 * frequency, pick the closest one.
-		 */
-		if (prev.freq && signum(target_freq - curr.freq) !=
-				 signum(target_freq - prev.freq)) {
-			if (abs(target_freq - prev.freq) <
-					abs(target_freq - curr.freq))
-				curr = prev;
-
-			if (stage == STAGE_CALI)
-				break;
-
-			/* Switch to optimizing cali */
-			stage = STAGE_CALI;
-			param = curr.cali;
-			param_max = ULPOSC_CALI_MAX;
-		}
-
-		prev = curr;
-		param += signum(target_freq - curr.freq);
-
-		if (param < 0 || param >= param_max)
-			return 0;
-
-		if (stage == STAGE_DIV)
-			curr.div = param;
-		else
-			curr.cali = param;
-	}
-
-	/*
-	 * It's possible we end up using prev, so reset the configuration and
-	 * measure again.
-	 */
-	return scp_ulposc_config_measure(osc, curr.div, curr.cali);
-}
-
-static void scp_clock_high_enable(int osc)
-{
-	/* Enable high speed clock */
-	SCP_CLK_EN |= EN_CLK_HIGH;
-
-	switch (osc) {
-	case 0:
-		/* After 25ms, enable ULPOSC */
-		busy_udelay(25 * MSEC);
-		SCP_CLK_EN |= CG_CLK_HIGH;
-		break;
-	case 1:
-		/* Turn off ULPOSC2 high-core-disable switch */
-		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
-		/* After 25ms, turn on ULPOSC2 high core clock gate */
-		busy_udelay(25 * MSEC);
-		SCP_CLK_HIGH_CORE |= CLK_HIGH_CORE_CG;
-		break;
-	default:
-		break;
-	}
-}
-
-void scp_use_clock(enum scp_clock_source src)
-{
-	/*
-	 * DIV2 divider takes precedence over clock selection to prevent
-	 * over-clocking.
-	 */
-	if (src == SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV2;
-
-	SCP_CLK_SEL = src;
-
-	if (src != SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV1;
-}
-
-void scp_enable_clock(void)
-{
-	/* Select default CPU clock */
-	scp_use_clock(SCP_CLK_26M);
-
-	/* VREQ */
-	SCP_CPU_VREQ = 0x10001;
-	SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
-
-	/* DDREN auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* Set settle time */
-	SCP_CLK_SYS_VAL = 1;  /* System clock */
-	SCP_CLK_HIGH_VAL = 1; /* ULPOSC */
-	SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | 2;
-
-	/* Disable slow wake */
-	SCP_CLK_SLEEP = SLOW_WAKE_DISABLE;
-	/* Disable SPM sleep control, disable sleep mode */
-	SCP_CLK_SLEEP_CTRL &= ~(SPM_SLEEP_MODE | EN_SLEEP_CTRL);
-
-	/* Turn off ULPOSC2 */
-	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-	scp_ulposc_config(0, 12, 32);
-	scp_clock_high_enable(0); /* Turn on ULPOSC1 */
-	scp_ulposc_config(1, 16, 32);
-	scp_clock_high_enable(1); /* Turn on ULPOSC2 */
-
-	/* Calibrate ULPOSC */
-	scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
-	scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
-
-	/* Select ULPOSC2 high speed CPU clock */
-	scp_use_clock(SCP_CLK_ULPOSC2);
-
-	/* Enable default clock gate */
-	SCP_CLK_GATE |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
-			CG_I2C_M | CG_MAD_M | CG_AP2P_M;
-
-	/* Select pwrap_ulposc */
-	AP_CLK_CFG_5 = (AP_CLK_CFG_5 & ~PWRAP_ULPOSC_MASK) | OSC_D16;
-
-	/* Enable pwrap_ulposc clock gate */
-	AP_CLK_CFG_5_CLR = PWRAP_ULPOSC_CG;
-}
-
-DECLARE_IRQ(SCP_IRQ_CLOCK, clock_control_irq, 3);
-void clock_control_irq(void)
-{
-	/* Read ack CLK_IRQ */
-	(SCP_CLK_IRQ_ACK);
-	task_clear_pending_irq(SCP_IRQ_CLOCK);
-}
-
-DECLARE_IRQ(SCP_IRQ_CLOCK2, clock_fast_wakeup_irq, 3);
-void clock_fast_wakeup_irq(void)
-{
-	/* Ack fast wakeup */
-	SCP_SLEEP_IRQ2 = 1;
-	task_clear_pending_irq(SCP_IRQ_CLOCK2);
-}
-
-/* Console command */
-int command_ulposc(int argc, char *argv[])
-{
-	if (argc > 1 && !strncmp(argv[1], "cal", 3)) {
-		scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
-		scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
-	}
-
-	/* SCP clock meter counts every (26MHz / 1024) tick */
-	ccprintf("ULPOSC1 frequency: %u kHz\n",
-		 scp_measure_ulposc_freq(0) * 26 * 1000 / 1024);
-	ccprintf("ULPOSC2 frequency: %u kHz\n",
-		 scp_measure_ulposc_freq(1) * 26 * 1000 / 1024);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[calibrate]",
-			"Calibrate ULPOSC frequency");
diff --git a/chip/mt_scp/mt8183/clock_chip.h b/chip/mt_scp/mt8183/clock_chip.h
deleted file mode 100644
index a16bf2e54e..0000000000
--- a/chip/mt_scp/mt8183/clock_chip.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#ifndef __CROS_EC_CLOCK_CHIP_H
-#define __CROS_EC_CLOCK_CHIP_H
-
-#include "common.h"
-#include "registers.h"
-
-/* Default ULPOSC clock speed in MHz */
-#ifndef ULPOSC1_CLOCK_MHZ
-#define ULPOSC1_CLOCK_MHZ 240
-#endif
-#ifndef ULPOSC2_CLOCK_MHZ
-#define ULPOSC2_CLOCK_MHZ 330
-#endif
-
-void scp_enable_clock(void);
-
-enum scp_clock_source {
-	SCP_CLK_26M = CLK_SEL_SYS_26M,
-	SCP_CLK_32K = CLK_SEL_32K,
-	SCP_CLK_ULPOSC2 = CLK_SEL_ULPOSC_2,
-	SCP_CLK_ULPOSC1 = CLK_SEL_ULPOSC_1,
-};
-
-/* Switches to use 'src' clock */
-void scp_use_clock(enum scp_clock_source src);
-
-#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/chip/mt_scp/mt8183/config_chip.h b/chip/mt_scp/mt8183/config_chip.h
deleted file mode 100644
index e0710a908b..0000000000
--- a/chip/mt_scp/mt8183/config_chip.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/cortex-m/config_core.h"
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Default to UART 2 (AP UART) for EC console */
-#define CONFIG_UART_CONSOLE 2
-
-/* Number of IRQ vectors */
-#define CONFIG_IRQ_COUNT 56
-
-/*
- * Number of EINT can be 0 ~ 160. Change this to conditional macro
- * on adding other variants.
- */
-#define MAX_NUM_EINT 8
-#define MAX_EINT_PORT (MAX_NUM_EINT / 32)
-
-/* RW only, no flash */
-#undef  CONFIG_FW_INCLUDE_RO
-#define CONFIG_RO_MEM_OFF 0
-#define CONFIG_RO_SIZE 0
-#define CONFIG_RW_MEM_OFF 0
-#define CONFIG_RW_SIZE 0x40000 /* 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
-#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
-#define CONFIG_RO_STORAGE_OFF 0
-#define CONFIG_RW_STORAGE_OFF 0
-#define CONFIG_PROGRAM_MEMORY_BASE 0
-#define CONFIG_MAPPED_STORAGE_BASE 0
-/* Enable MPU to protect code RAM from writing, and data RAM from execution.*/
-#define CONFIG_MPU
-
-/* Unsupported features/commands */
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_FLASH_CROS
-#undef CONFIG_FLASH_PHYSICAL
-#undef CONFIG_FMAP
-#undef CONFIG_HIBERNATE
-
-/* Task stack size */
-#define CONFIG_STACK_SIZE 1024
-#define IDLE_TASK_STACK_SIZE 256
-#define SMALLER_TASK_STACK_SIZE 384
-#define TASK_STACK_SIZE 512
-#define LARGER_TASK_STACK_SIZE 640
-#define VENTI_TASK_STACK_SIZE 768
-
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mt_scp/mt8183/gpio.c b/chip/mt_scp/mt8183/gpio.c
deleted file mode 100644
index a4896aae72..0000000000
--- a/chip/mt_scp/mt8183/gpio.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module */
-
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int bit, mode_reg_index, shift;
-	uint32_t mode_bits, mode_mask;
-
-	/* Up to 8 alt functions per port */
-	if (func > GPIO_ALT_FUNC_7)
-		return;
-
-	if (func == GPIO_ALT_FUNC_NONE)
-		func = GPIO_ALT_FUNC_DEFAULT;
-
-	while (mask) {
-		/* 32 gpio per port */
-		bit = get_next_bit(&mask);
-		/* 8 gpio per mode reg */
-		mode_reg_index = (port << 2) | (bit >> 3);
-		/*
-		 * b[3]   - write enable(?)
-		 * b[2:0] - mode
-		 */
-		shift = (bit & 7) << 2;
-		mode_bits = func << shift;
-		mode_mask = ~(0xf << shift);
-		AP_GPIO_MODE(mode_reg_index) = (AP_GPIO_MODE(mode_reg_index) &
-						mode_mask) | mode_bits;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return !!(AP_GPIO_DIN(gpio_list[signal].port) &
-		  gpio_list[signal].mask);
-}
-
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	if (value)
-		AP_GPIO_DOUT(gpio_list[signal].port) |= gpio_list[signal].mask;
-	else
-		AP_GPIO_DOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask;
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/* Set input/output mode */
-	if (flags & GPIO_OUTPUT) {
-		/* Set level before changing to output mode */
-		if (flags & GPIO_HIGH)
-			AP_GPIO_DOUT(port) |= mask;
-		if (flags & GPIO_LOW)
-			AP_GPIO_DOUT(port) &= ~mask;
-		AP_GPIO_DIR(port) |= mask;
-	} else {
-		AP_GPIO_DIR(port) &= ~mask;
-	}
-
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH))
-		SCP_EINT_POLARITY_SET[port] = mask;
-
-	if (flags & (GPIO_INT_F_FALLING | GPIO_INT_F_LOW))
-		SCP_EINT_POLARITY_CLR[port] = mask;
-	else
-		SCP_EINT_POLARITY_SET[port] = mask;
-
-	/* Set sensitivity register on edge trigger */
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING))
-		SCP_EINT_SENS_SET[port] = mask;
-	else
-		SCP_EINT_SENS_CLR[port] = mask;
-}
-
-int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
-{
-	/* TODO(b/120167145): implement get flags */
-	return 0;
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (signal >= GPIO_IH_COUNT || !g->mask)
-		return EC_ERROR_INVAL;
-
-	SCP_EINT_MASK_CLR[g->port] = g->mask;
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (signal >= GPIO_IH_COUNT || !g->mask)
-		return EC_ERROR_INVAL;
-
-	SCP_EINT_MASK_SET[g->port] = g->mask;
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (signal >= GPIO_IH_COUNT || !g->mask)
-		return EC_ERROR_INVAL;
-
-	SCP_EINT_ACK[g->port] = g->mask;
-
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int i;
-	int is_warm = system_is_reboot_warm();
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-void gpio_init(void)
-{
-	/* Enable EINT IRQ */
-	task_enable_irq(SCP_IRQ_EINT);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/* Interrupt handler */
-void __keep gpio_interrupt(void)
-{
-	int bit, port;
-	uint32_t pending;
-	enum gpio_signal signal;
-
-	for (port = 0; port <= MAX_EINT_PORT; port++) {
-		pending = SCP_EINT_STATUS[port];
-
-		while (pending) {
-			bit = get_next_bit(&pending);
-			SCP_EINT_ACK[port] = BIT(bit);
-			/* Skip masked gpio */
-			if (SCP_EINT_MASK_GET[port] & BIT(bit))
-				continue;
-			/* Call handler */
-			signal = port * 32 + bit;
-			if (signal < GPIO_IH_COUNT)
-				gpio_irq_handlers[signal](signal);
-		}
-	}
-}
-DECLARE_IRQ(SCP_IRQ_EINT, gpio_interrupt, 1);
diff --git a/chip/mt_scp/mt8183/hrtimer.c b/chip/mt_scp/mt8183/hrtimer.c
deleted file mode 100644
index 92887af2a7..0000000000
--- a/chip/mt_scp/mt8183/hrtimer.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * High-res hardware timer
- *
- * SCP hardware 32bit count down timer can be configured to source clock from
- * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a
- * source, countdown mode and converts to micro second value matching common
- * timer.
- */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-#define IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n)
-
-#define TIMER_SYSTEM 5
-#define TIMER_EVENT 3
-
-/* ULPOSC1 should be a multiple of 8. */
-BUILD_ASSERT((ULPOSC1_CLOCK_MHZ % 8) == 0);
-#define TIMER_CLOCK_MHZ (ULPOSC1_CLOCK_MHZ / 8)
-
-/* Common timer overflows at 0x100000000 micro seconds */
-#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1)
-
-static uint8_t sys_high;
-static uint8_t event_high;
-
-/* Convert hardware countdown timer to 64bit countup ticks */
-static inline uint64_t timer_read_raw_system(void)
-{
-	uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(TIMER_SYSTEM);
-	uint32_t sys_high_adj = sys_high;
-
-	/*
-	 * If an IRQ is pending, but has not been serviced yet, adjust the
-	 * sys_high value.
-	 */
-	if (timer_ctrl & TIMER_IRQ_STATUS)
-		sys_high_adj = sys_high ? (sys_high - 1) : (TIMER_CLOCK_MHZ-1);
-
-	return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) |
-				 SCP_TIMER_VAL(TIMER_SYSTEM));
-}
-
-static inline uint64_t timer_read_raw_event(void)
-{
-	return OVERFLOW_TICKS - (((uint64_t)event_high << 32) |
-				 SCP_TIMER_VAL(TIMER_EVENT));
-}
-
-static inline void timer_set_clock(int n, uint32_t clock_source)
-{
-	SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) |
-			  clock_source;
-}
-
-static inline void timer_ack_irq(int n)
-{
-	SCP_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLEAR;
-}
-
-/* Set hardware countdown value */
-static inline void timer_set_reset_value(int n, uint32_t reset_value)
-{
-	SCP_TIMER_RESET_VAL(n) = reset_value;
-}
-
-static void timer_reset(int n)
-{
-	__hw_timer_enable_clock(n, 0);
-	timer_ack_irq(n);
-	timer_set_reset_value(n, 0xffffffff);
-	timer_set_clock(n, TIMER_CLK_32K);
-}
-
-/* Reload a new 32bit countdown value */
-static void timer_reload(int n, uint32_t value)
-{
-	__hw_timer_enable_clock(n, 0);
-	timer_set_reset_value(n, value);
-	__hw_timer_enable_clock(n, 1);
-}
-
-static int timer_reload_event_high(void)
-{
-	if (event_high) {
-		if (SCP_TIMER_RESET_VAL(TIMER_EVENT) == 0xffffffff)
-			__hw_timer_enable_clock(TIMER_EVENT, 1);
-		else
-			timer_reload(TIMER_EVENT, 0xffffffff);
-		event_high--;
-		return 1;
-	}
-
-	/* Disable event timer clock when done. */
-	__hw_timer_enable_clock(TIMER_EVENT, 0);
-	return 0;
-}
-
-void __hw_clock_event_clear(void)
-{
-	__hw_timer_enable_clock(TIMER_EVENT, 0);
-	timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4);
-	event_high = 0;
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ;
-	uint64_t now_raw = timer_read_raw_system();
-	uint32_t event_deadline;
-
-	if (deadline_raw > now_raw) {
-		deadline_raw -= now_raw;
-		event_deadline = (uint32_t)deadline_raw;
-		event_high = deadline_raw >> 32;
-	} else {
-		event_deadline = 1;
-		event_high = 0;
-	}
-
-	if (event_deadline)
-		timer_reload(TIMER_EVENT, event_deadline);
-	else
-		timer_reload_event_high();
-}
-
-void __hw_timer_enable_clock(int n, int enable)
-{
-	if (enable) {
-		SCP_TIMER_IRQ_CTRL(n) |= 1;
-		SCP_TIMER_EN(n) |= 1;
-	} else {
-		SCP_TIMER_EN(n) &= ~1;
-		SCP_TIMER_IRQ_CTRL(n) &= ~1;
-	}
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	int t;
-
-	/*
-	 * TODO(b/120169529): check clock tree to see if we need to turn on
-	 * MCLK and BCLK gate.
-	 */
-	SCP_CLK_GATE |= (CG_TIMER_M | CG_TIMER_B);
-
-	/* Reset all timer, select 32768Hz clock source */
-	for (t = 0; t < NUM_TIMERS; t++)
-		timer_reset(t);
-
-	/* Enable timer IRQ wake source */
-	SCP_INTC_IRQ_WAKEUP |= (1 << IRQ_TIMER(0)) | (1 << IRQ_TIMER(1)) |
-			       (1 << IRQ_TIMER(2)) | (1 << IRQ_TIMER(3)) |
-			       (1 << IRQ_TIMER(4)) | (1 << IRQ_TIMER(5));
-	/*
-	 * Timer configuration:
-	 *   OS TIMER    - count up @ 13MHz, 64bit value with latch.
-	 *   SYS TICK    - count down @ 26MHz
-	 *   EVENT TICK  - count down @ 26MHz
-	 */
-
-	/* Turn on OS TIMER, tick at 13MHz */
-	SCP_OSTIMER_CON |= 1;
-
-	/* System timestamp timer from BCLK (sourced from ULPOSC) */
-	SCP_CLK_BCLK = CLK_BCLK_SEL_ULPOSC1_DIV8;
-
-	timer_set_clock(TIMER_SYSTEM, TIMER_CLK_BCLK);
-	sys_high = TIMER_CLOCK_MHZ-1;
-	timer_set_reset_value(TIMER_SYSTEM, 0xffffffff);
-	__hw_timer_enable_clock(TIMER_SYSTEM, 1);
-	task_enable_irq(IRQ_TIMER(TIMER_SYSTEM));
-	/* Event tick timer */
-	timer_set_clock(TIMER_EVENT, TIMER_CLK_BCLK);
-	task_enable_irq(IRQ_TIMER(TIMER_EVENT));
-
-	return IRQ_TIMER(TIMER_SYSTEM);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return timer_read_raw_system() / TIMER_CLOCK_MHZ;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return (timer_read_raw_event() + timer_read_raw_system())
-			/ TIMER_CLOCK_MHZ;
-}
-
-static void __hw_clock_source_irq(int n)
-{
-	uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(n);
-
-	/* Ack if we're hardware interrupt */
-	if (timer_ctrl & TIMER_IRQ_STATUS)
-		timer_ack_irq(n);
-
-	switch (n) {
-	case TIMER_EVENT:
-		if (timer_ctrl & TIMER_IRQ_STATUS) {
-			if (timer_reload_event_high())
-				return;
-		}
-		process_timers(0);
-		break;
-	case TIMER_SYSTEM:
-		/* If this is a hardware irq, check overflow */
-		if (timer_ctrl & TIMER_IRQ_STATUS) {
-			if (sys_high) {
-				sys_high--;
-				process_timers(0);
-			} else {
-				/* Overflow, reload system timer */
-				sys_high = TIMER_CLOCK_MHZ-1;
-				process_timers(1);
-			}
-		} else {
-			process_timers(0);
-		}
-		break;
-	default:
-		return;
-	}
-
-}
-
-#define DECLARE_TIMER_IRQ(n) \
-	DECLARE_IRQ(IRQ_TIMER(n), __hw_clock_source_irq_##n, 2); \
-	void __hw_clock_source_irq_##n(void) { __hw_clock_source_irq(n); }
-
-DECLARE_TIMER_IRQ(0);
-DECLARE_TIMER_IRQ(1);
-DECLARE_TIMER_IRQ(2);
-DECLARE_TIMER_IRQ(3);
-DECLARE_TIMER_IRQ(4);
-DECLARE_TIMER_IRQ(5);
diff --git a/chip/mt_scp/mt8183/ipi.c b/chip/mt_scp/mt8183/ipi.c
deleted file mode 100644
index 8e13781db3..0000000000
--- a/chip/mt_scp/mt8183/ipi.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Inter-Processor Communication (IPC) and Inter-Processor Interrupt (IPI)
- *
- * IPC is a communication bridge between AP and SCP.  AP/SCP sends an IPC
- * interrupt to SCP/AP to inform to collect the commmunication mesesages in the
- * shared buffer.
- *
- * There are 4 IPCs in the current architecture, from IPC0 to IPC3.  The
- * priority of IPC is proportional to its IPC index. IPC3 has the highest
- * priority and IPC0 has the lowest one.
- *
- * IPC0 may contain zero or more IPIs.  Each IPI represents a task or a service,
- * e.g. host command, or video encoding.  IPIs are recognized by IPI ID, which
- * should sync across AP and SCP.  Shared buffer should designated which IPI
- * ID it talks to.
- *
- * Currently, we don't have IPC handlers for IPC1, IPC2, and IPC3.
- */
-
-#include "clock_chip.h"
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "ipi_chip.h"
-#include "mkbp_event.h"
-#include "power.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "hwtimer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-#define IPI_MAX_REQUEST_SIZE CONFIG_IPC_SHARED_OBJ_BUF_SIZE
-/* Reserve 1 extra byte for HOSTCMD_TYPE and 3 bytes for padding. */
-#define IPI_MAX_RESPONSE_SIZE (CONFIG_IPC_SHARED_OBJ_BUF_SIZE - 4)
-#define HOSTCMD_TYPE_HOSTCMD 1
-#define HOSTCMD_TYPE_HOSTEVENT 2
-
-static volatile int16_t ipc0_enabled_count;
-static struct mutex ipc0_lock;
-static struct mutex ipi_lock;
-/* IPC0 shared objects, including send object and receive object. */
-static struct ipc_shared_obj *const scp_send_obj =
-	(struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR;
-static struct ipc_shared_obj *const scp_recv_obj =
-	(struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR +
-				  sizeof(struct ipc_shared_obj));
-static char ipi_ready;
-
-#ifdef HAS_TASK_HOSTCMD
-/*
- * hostcmd and hostevent share the same IPI ID, and use first byte type to
- * indicate its type.
- */
-static struct hostcmd_data {
-	const uint8_t type;
-	/* To be compatible with CONFIG_HOSTCMD_ALIGNED */
-	uint8_t response[IPI_MAX_RESPONSE_SIZE] __aligned(4);
-} hc_cmd_obj = { .type = HOSTCMD_TYPE_HOSTCMD };
-BUILD_ASSERT(sizeof(struct hostcmd_data) == CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-static struct host_packet ipi_packet;
-#endif
-
-/* Check if SCP to AP IPI is in use. */
-static inline int is_ipi_busy(void)
-{
-	return SCP_HOST_INT & IPC_SCP2HOST_BIT;
-}
-
-/* If IPI is declared as a wake-up source, wake AP up. */
-static inline void try_to_wakeup_ap(int32_t id)
-{
-#ifdef CONFIG_RPMSG_NAME_SERVICE
-	if (id == IPI_NS_SERVICE)
-		return;
-#endif
-
-	if (*ipi_wakeup_table[id])
-		SCP_SPM_INT = SPM_INT_A2SPM;
-}
-
-void ipi_disable_irq(int irq)
-{
-	/* Only support SCP_IRQ_IPC0 for now. */
-	if (irq != SCP_IRQ_IPC0)
-		return;
-
-	mutex_lock(&ipc0_lock);
-
-	if ((--ipc0_enabled_count) == 0)
-		task_disable_irq(irq);
-
-	mutex_unlock(&ipc0_lock);
-}
-
-void ipi_enable_irq(int irq)
-{
-	/* Only support SCP_IRQ_IPC0 for now. */
-	if (irq != SCP_IRQ_IPC0)
-		return;
-
-	mutex_lock(&ipc0_lock);
-
-	if ((++ipc0_enabled_count) == 1) {
-		int pending_ipc = SCP_GIPC_IN & SCP_GPIC_IN_CLEAR_ALL;
-
-		task_enable_irq(irq);
-
-		if (ipi_ready && pending_ipc)
-			/*
-			 * IPC may be triggered while SCP_IRQ_IPC0 was disabled.
-			 * AP will still updates SCP_GIPC_IN.
-			 * Trigger the IRQ handler if it has a
-			 * pending IPC.
-			 */
-			task_trigger_irq(irq);
-	}
-
-	mutex_unlock(&ipc0_lock);
-}
-
-__override void
-power_chipset_handle_host_sleep_event(enum host_sleep_event state,
-				      struct host_sleep_event_context *ctx)
-{
-	int i;
-	const task_id_t s3_suspend_tasks[] = {
-#ifndef S3_SUSPEND_TASK_LIST
-#define S3_SUSPEND_TASK_LIST
-#endif
-#define TASK(n, ...) TASK_ID_##n,
-		S3_SUSPEND_TASK_LIST
-	};
-
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		ccprints("AP suspend");
-		/*
-		 * On AP suspend, Vcore is 0.6V, and we should not use ULPOSC2,
-		 * which needs at least 0.7V.  Switch to ULPOSC1 instead.
-		 */
-		scp_use_clock(SCP_CLK_ULPOSC1);
-
-		for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i)
-			task_disable_task(s3_suspend_tasks[i]);
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		ccprints("AP resume");
-		/* Vcore is raised to >=0.7V, switch back to ULPSOC2 */
-		scp_use_clock(SCP_CLK_ULPOSC2);
-
-		for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i)
-			task_enable_task(s3_suspend_tasks[i]);
-	}
-}
-
-/* Send data from SCP to AP. */
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait)
-{
-	if (!ipi_ready)
-		return EC_ERROR_BUSY;
-
-	/* TODO(b:117917141): Remove this check completely. */
-	if (in_interrupt_context()) {
-		CPRINTS("Err: invoke %s() in ISR CTX", __func__);
-		return EC_ERROR_BUSY;
-	}
-
-	if (len > sizeof(scp_send_obj->buffer))
-		return EC_ERROR_INVAL;
-
-	ipi_disable_irq(SCP_IRQ_IPC0);
-	mutex_lock(&ipi_lock);
-
-	/* Check if there is already an IPI pending in AP. */
-	if (is_ipi_busy()) {
-		/*
-		 * If the following conditions meet,
-		 *   1) There is an IPI pending in AP.
-		 *   2) The incoming IPI is a wakeup IPI.
-		 * then it assumes that AP is in suspend state.
-		 * Send a AP wakeup request to SPM.
-		 *
-		 * The incoming IPI will be checked if it's a wakeup source.
-		 */
-		try_to_wakeup_ap(id);
-
-		mutex_unlock(&ipi_lock);
-		ipi_enable_irq(SCP_IRQ_IPC0);
-		CPRINTS("Err: IPI Busy, %d", id);
-
-		return EC_ERROR_BUSY;
-	}
-
-
-	scp_send_obj->id = id;
-	scp_send_obj->len = len;
-	memcpy(scp_send_obj->buffer, buf, len);
-
-	/* Send IPI to AP: interrutp AP to receive IPI messages. */
-	try_to_wakeup_ap(id);
-	SCP_HOST_INT = IPC_SCP2HOST_BIT;
-
-	while (wait && is_ipi_busy())
-		;
-
-	mutex_unlock(&ipi_lock);
-	ipi_enable_irq(SCP_IRQ_IPC0);
-
-	return EC_SUCCESS;
-}
-
-static void ipi_handler(void)
-{
-	if (scp_recv_obj->id >= IPI_COUNT) {
-		CPRINTS("#ERR IPI %d", scp_recv_obj->id);
-		return;
-	}
-
-	/*
-	 * Only print IPI that is not host command channel, which will
-	 * be printed by host command driver.
-	 */
-	if (scp_recv_obj->id != IPI_HOST_COMMAND)
-		CPRINTS("IPI %d", scp_recv_obj->id);
-
-	/*
-	 * Pass the buffer to handler. Each handler should be in charge of
-	 * the buffer copying/reading before returning from handler.
-	 */
-	ipi_handler_table[scp_recv_obj->id](
-		scp_recv_obj->id, scp_recv_obj->buffer, scp_recv_obj->len);
-}
-
-void ipi_inform_ap(void)
-{
-	struct scp_run_t scp_run;
-	int ret;
-#ifdef CONFIG_RPMSG_NAME_SERVICE
-	struct rpmsg_ns_msg ns_msg;
-#endif
-
-	scp_run.signaled = 1;
-	strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW),
-		SCP_FW_VERSION_LEN);
-	scp_run.dec_capability = VCODEC_CAPABILITY_4K_DISABLED;
-	scp_run.enc_capability = 0;
-
-	ret = ipi_send(IPI_SCP_INIT, (void *)&scp_run, sizeof(scp_run), 1);
-
-	if (ret)
-		ccprintf("Failed to send initialization IPC messages.\n");
-
-#ifdef CONFIG_RPMSG_NAME_SERVICE
-	ns_msg.id = IPI_HOST_COMMAND;
-	strncpy(ns_msg.name, "cros-ec-rpmsg", RPMSG_NAME_SIZE);
-	ret = ipi_send(IPI_NS_SERVICE, &ns_msg, sizeof(ns_msg), 1);
-	if (ret)
-		ccprintf("Failed to announce host command channel.\n");
-#endif
-}
-
-#ifdef HAS_TASK_HOSTCMD
-#if defined(CONFIG_MKBP_USE_CUSTOM)
-int mkbp_set_host_active_via_custom(int active, uint32_t *timestamp)
-{
-	static const uint8_t hc_evt_obj = HOSTCMD_TYPE_HOSTEVENT;
-
-	/* This should be moved into ipi_send for more accuracy */
-	if (timestamp)
-		*timestamp = __hw_clock_source_read();
-
-	if (active)
-		return ipi_send(IPI_HOST_COMMAND, &hc_evt_obj,
-				sizeof(hc_evt_obj), 1);
-	return EC_SUCCESS;
-}
-#endif
-
-static void ipi_send_response_packet(struct host_packet *pkt)
-{
-	int ret;
-
-	ret = ipi_send(IPI_HOST_COMMAND, &hc_cmd_obj,
-		       pkt->response_size +
-			       offsetof(struct hostcmd_data, response),
-		       1);
-	if (ret)
-		CPRINTS("#ERR IPI HOSTCMD %d", ret);
-}
-
-static void ipi_hostcmd_handler(int32_t id, void *buf, uint32_t len)
-{
-	uint8_t *in_msg = buf;
-	struct ec_host_request *r = (struct ec_host_request *)in_msg;
-	int i;
-
-	if (in_msg[0] != EC_HOST_REQUEST_VERSION) {
-		CPRINTS("ERROR: Protocol V2 is not supported!");
-		CPRINTF("in_msg=[");
-		for (i = 0; i < len; i++)
-			CPRINTF("%02x ", in_msg[i]);
-		CPRINTF("]\n");
-		return;
-	}
-
-	/* Protocol version 3 */
-
-	ipi_packet.send_response = ipi_send_response_packet;
-
-	/*
-	 * Just assign the buffer to request, host_packet_receive
-	 * handles the buffer copy.
-	 */
-	ipi_packet.request = (void *)r;
-	ipi_packet.request_temp = NULL;
-	ipi_packet.request_max = IPI_MAX_REQUEST_SIZE;
-	ipi_packet.request_size = host_request_expected_size(r);
-
-	ipi_packet.response = hc_cmd_obj.response;
-	/* Reserve space for the preamble and trailing byte */
-	ipi_packet.response_max = IPI_MAX_RESPONSE_SIZE;
-	ipi_packet.response_size = 0;
-
-	ipi_packet.driver_result = EC_RES_SUCCESS;
-
-	host_packet_receive(&ipi_packet);
-}
-DECLARE_IPI(IPI_HOST_COMMAND, ipi_hostcmd_handler, 0);
-
-/*
- * Get protocol information
- */
-static enum ec_status ipi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions |= BIT(3);
-	r->max_request_packet_size = IPI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = IPI_MAX_RESPONSE_SIZE;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, ipi_get_protocol_info,
-		     EC_VER_MASK(0));
-#endif
-
-static void ipi_enable_ipc0_deferred(void)
-{
-	/* Clear IPC0 IRQs. */
-	SCP_GIPC_IN = SCP_GPIC_IN_CLEAR_ALL;
-
-	/* All tasks are up, we can safely enable IPC0 IRQ now. */
-	SCP_INTC_IRQ_ENABLE |= IPC0_IRQ_EN;
-	ipi_enable_irq(SCP_IRQ_IPC0);
-
-	ipi_ready = 1;
-
-	/* Inform AP that SCP is inited.  */
-	ipi_inform_ap();
-
-	CPRINTS("ipi init");
-}
-DECLARE_DEFERRED(ipi_enable_ipc0_deferred);
-
-/* Initialize IPI. */
-static void ipi_init(void)
-{
-	/* Clear send share buffer. */
-	memset(scp_send_obj, 0, sizeof(struct ipc_shared_obj));
-
-	/* Enable IRQ after all tasks are up.  */
-	hook_call_deferred(&ipi_enable_ipc0_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(SCP_IRQ_IPC0, ipc_handler, 4);
-void ipc_handler(void)
-{
-	/* TODO(b/117917141): We only support IPC_ID(0) for now. */
-	if (SCP_GIPC_IN & SCP_GIPC_IN_CLEAR_IPCN(0)) {
-		ipi_handler();
-		SCP_GIPC_IN &= SCP_GIPC_IN_CLEAR_IPCN(0);
-	}
-
-	SCP_GIPC_IN &= (SCP_GPIC_IN_CLEAR_ALL & ~SCP_GIPC_IN_CLEAR_IPCN(0));
-}
diff --git a/chip/mt_scp/mt8183/ipi_chip.h b/chip/mt_scp/mt8183/ipi_chip.h
deleted file mode 100644
index 758047951f..0000000000
--- a/chip/mt_scp/mt8183/ipi_chip.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_IPI_CHIP_H
-#define __CROS_EC_IPI_CHIP_H
-
-#include "common.h"
-#include "registers.h"
-
-#define IPC_MAX 1
-#define IPC_ID(n) (n)
-
-/*
- * Length of EC version string is at most 32 byte (NULL included), which
- * also aligns SCP fw_version length.
- */
-#define SCP_FW_VERSION_LEN 32
-
-/*
- * Video decoder supported capability:
- * BIT(4): 0 enable 4K
- *         1 disable 4K
- */
-#define VCODEC_CAPABILITY_4K_DISABLED BIT(4)
-
-#ifndef IPI_SCP_INIT
-#error If CONFIG_IPI is enabled, IPI_SCP_INIT must be defined.
-#endif
-
-/*
- * Share buffer layout for IPI_SCP_INIT response. This structure should sync
- * across kernel and EC.
- */
-struct scp_run_t {
-	uint32_t signaled;
-	int8_t fw_ver[SCP_FW_VERSION_LEN];
-	uint32_t dec_capability;
-	uint32_t enc_capability;
-};
-
-/*
- * The layout of the IPC0 AP/SCP shared buffer.
- * This should sync across kernel and EC.
- */
-struct ipc_shared_obj {
-	/* IPI ID */
-	int32_t id;
-	/* Length of the contents in buffer. */
-	uint32_t len;
-	/* Shared buffer contents. */
-	uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE];
-};
-
-/* Send a IPI contents to AP. This shouldn't be used in ISR context. */
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait);
-
-/* Size of the rpmsg device name, should sync across kernel and EC. */
-#define RPMSG_NAME_SIZE 32
-
-/*
- * The layout of name service message.
- * This should sync across kernel and EC.
- */
-struct rpmsg_ns_msg {
-	/* Name of the corresponding rpmsg_driver. */
-	char name[RPMSG_NAME_SIZE];
-	/* IPC ID */
-	uint32_t id;
-};
-
-/*
- * IPC Handler.
- */
-void ipc_handler(void);
-
-/*
- * An IPC IRQ could be shared across many IPI handlers.
- * Those handlers would usually operate on disabling or enabling the IPC IRQ.
- * This may disorder the actual timing to on/off the IRQ when there are many
- * tasks try to operate on it.  As a result, any access to the SCP_IRQ_*
- * should go through ipi_{en,dis}able_irq(), which support a counter to
- * enable/disable the IRQ at correct timeing.
- */
-/* Disable IPI IRQ. */
-void ipi_disable_irq(int irq);
-/* Enable IPI IRQ. */
-void ipi_enable_irq(int irq);
-
-/* IPI tables */
-extern void (*ipi_handler_table[])(int32_t, void *, uint32_t);
-extern int *ipi_wakeup_table[];
-
-/* Helper macros to build the IPI handler and wakeup functions. */
-#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler)
-#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup)
-
-/*
- * Macro to declare an IPI handler.
- * _id: The ID of the IPI
- * handler: The IPI handler function
- * is_wakeup_src: Declare IPI ID as a wake-up source or not
- */
-#define DECLARE_IPI(_id, handler, is_wakeup_src) \
-	struct ipi_num_check##_id { \
-		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
-		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
-	};  \
-	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
-	{ \
-		handler(id, buf, len); \
-	} \
-	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
-
-#endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt_scp/mt8183/ipi_table.c b/chip/mt_scp/mt8183/ipi_table.c
deleted file mode 100644
index 8569ab24a7..0000000000
--- a/chip/mt_scp/mt8183/ipi_table.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IPI handlers declaration
- */
-
-#include "common.h"
-#include "ipi_chip.h"
-
-typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#define ipi_arguments int32_t id, void *data, uint32_t len
-
-#if PASS == 1
-void ipi_handler_undefined(ipi_arguments) { }
-
-const int ipi_wakeup_undefined;
-
-#define table(type, name, x) x
-
-#define ipi_x_func(suffix, args, number)                                       \
-	extern void __attribute__(                                             \
-		(used, weak, alias(STRINGIFY(ipi_##suffix##_undefined))))      \
-		ipi_##number##_##suffix(args);
-
-#define ipi_x_var(suffix, number)                                              \
-	extern int __attribute__(                                              \
-		(weak, alias(STRINGIFY(ipi_##suffix##_undefined))))            \
-		ipi_##number##_##suffix;
-
-#endif /* PASS == 1 */
-
-#if PASS == 2
-
-#undef table
-#undef ipi_x_func
-#undef ipi_x_var
-
-#define table(type, name, x)                                                   \
-	type name[] __aligned(4)                                               \
-		__attribute__((section(".rodata.ipi, \"a\" @"))) = {x}
-
-#define ipi_x_var(suffix, number)                                              \
-	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
-
-#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
-
-#endif /* PASS == 2 */
-
-/*
- * Include generated IPI table (by util/gen_ipi_table). The contents originate
- * from IPI_COUNT definition in board.h
- */
-#include "ipi_table_gen.inc"
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "ipi_table.c"
-BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT);
-BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT);
-#endif
diff --git a/chip/mt_scp/mt8183/memmap.c b/chip/mt_scp/mt8183/memmap.c
deleted file mode 100644
index 6d8f2b0c87..0000000000
--- a/chip/mt_scp/mt8183/memmap.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SCP memory map
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "hooks.h"
-#include "memmap.h"
-#include "registers.h"
-#include "util.h"
-
-/*
- * Map SCP address (bits 31~28) to AP address
- *
- * SCP addr    :  AP addr
- * 0x20000000     0x40000000
- * 0x30000000     0x50000000
- * 0x60000000     0x60000000
- * 0x70000000     0x70000000
- * 0x80000000     0x80000000
- * 0x90000000     0x00000000
- * 0xA0000000     0x10000000
- * 0xB0000000     0x20000000
- * 0xC0000000     0x30000000
- * 0xD0000000     0x10000000
- * 0xE0000000     0xA0000000
- * 0xF0000000     0x90000000
- */
-
-#define MAP_INVALID 0xff
-
-static const uint8_t addr_map[16] = {
-	MAP_INVALID,			/* 0x0: SRAM */
-	MAP_INVALID,			/* 0x1: Cached access (see below) */
-	0x4, 0x5,			/* 0x2-0x3 */
-	MAP_INVALID, MAP_INVALID,	/* 0x4-0x5 (unmapped: registers) */
-	0x6, 0x7, 0x8,			/* 0x6-0x8 */
-	0x0, 0x1, 0x2, 0x3,		/* 0x9-0xc */
-	0x1, 0xa, 0x9			/* 0xd-0xf */
-};
-
-/*
- * AP addr     :  SCP cache addr
- * 0x50000000     0x10000000
- */
-#define CACHE_TRANS_AP_ADDR 0x50000000
-#define CACHE_TRANS_SCP_CACHE_ADDR 0x10000000
-/* FIXME: This should be configurable */
-#define CACHE_TRANS_AP_SIZE 0x00400000
-
-#ifdef CONFIG_DRAM_BASE
-BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
-BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
-#endif
-
-static void cpu_invalidate_icache(void)
-{
-	SCP_CACHE_OP(CACHE_ICACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_ICACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	asm volatile("dsb; isb");
-}
-
-void cpu_invalidate_dcache(void)
-{
-	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	/* Read is necessary to confirm the invalidation finish. */
-	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
-	asm volatile("dsb;");
-}
-
-void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length)
-{
-	size_t pos;
-	uintptr_t addr;
-
-	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
-		addr = base + pos;
-		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
-		SCP_CACHE_OP(CACHE_DCACHE) |=
-			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		/* Read necessary to confirm the invalidation finish. */
-		REG32(addr);
-	}
-	asm volatile("dsb;");
-}
-
-void cpu_clean_invalidate_dcache(void)
-{
-	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_CACHE_FLUSH_ALL_LINES | SCP_CACHE_OP_EN;
-	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	/* Read necessary to confirm the invalidation finish. */
-	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
-	asm volatile("dsb;");
-}
-
-void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length)
-{
-	size_t pos;
-	uintptr_t addr;
-
-	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
-		addr = base + pos;
-		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
-		SCP_CACHE_OP(CACHE_DCACHE) |=
-			OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
-		SCP_CACHE_OP(CACHE_DCACHE) |=
-			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		/* Read necessary to confirm the invalidation finish. */
-		REG32(addr);
-	}
-	asm volatile("dsb;");
-}
-
-static void scp_cache_init(void)
-{
-	int c;
-	const int region = 0;
-
-	/* First make sure all caches are disabled, and reset stats. */
-	for (c = 0; c < CACHE_COUNT; c++) {
-		/*
-		 * Changing cache-size config may change the SRAM logical
-		 * address in the mean time.  This may break the loaded
-		 * memory layout, and thus break the system.  Cache-size
-		 * should only be be configured in kernel driver before
-		 * laoding the firmware. b/137920815#comment18
-		 */
-		SCP_CACHE_CON(c) &= (SCP_CACHE_CON_CACHESIZE_MASK |
-				     SCP_CACHE_CON_WAYEN);
-		SCP_CACHE_REGION_EN(c) = 0;
-		SCP_CACHE_ENTRY(c, region) = 0;
-		SCP_CACHE_END_ENTRY(c, region) = 0;
-
-		/* Reset statistics. */
-		SCP_CACHE_HCNT0U(c) = 0;
-		SCP_CACHE_HCNT0L(c) = 0;
-		SCP_CACHE_CCNT0U(c) = 0;
-		SCP_CACHE_CCNT0L(c) = 0;
-	}
-
-	/* No "normal" remap. */
-	SCP_L1_REMAP_CFG0 = 0;
-	SCP_L1_REMAP_CFG1 = 0;
-	SCP_L1_REMAP_CFG2 = 0;
-	SCP_L1_REMAP_CFG3 = 0;
-	/*
-	 * Setup OTHER1: Remap register for addr msb 31 to 28 equal to 0x1 and
-	 * not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7.
-	 */
-	SCP_L1_REMAP_OTHER =
-		(CACHE_TRANS_AP_ADDR >> SCP_L1_EXT_ADDR_OTHER_SHIFT) << 8;
-
-	/* Disable sleep protect */
-	SCP_SLP_PROTECT_CFG = SCP_SLP_PROTECT_CFG &
-		~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN);
-
-	/* Enable region 0 for both I-cache and D-cache. */
-	for (c = 0; c < CACHE_COUNT; c++) {
-		SCP_CACHE_ENTRY(c, region) = CACHE_TRANS_SCP_CACHE_ADDR;
-		SCP_CACHE_END_ENTRY(c, region) =
-			CACHE_TRANS_SCP_CACHE_ADDR + CACHE_TRANS_AP_SIZE;
-		SCP_CACHE_ENTRY(c, region) |= SCP_CACHE_ENTRY_C;
-
-		SCP_CACHE_REGION_EN(c) |= 1 << region;
-
-		/*
-		 * Enable cache. Note that cache size setting should have been
-		 * done in kernel driver. b/137920815#comment18
-		 */
-		SCP_CACHE_CON(c) |= SCP_CACHE_CON_MCEN | SCP_CACHE_CON_CNTEN0;
-	}
-
-	cpu_invalidate_icache();
-	cpu_invalidate_dcache();
-}
-
-static int command_cacheinfo(int argc, char **argv)
-{
-	const char cache_name[] = {'I', 'D'};
-	int c;
-
-	for (c = 0; c < 2; c++) {
-		uint64_t hit = ((uint64_t)SCP_CACHE_HCNT0U(c) << 32) |
-			SCP_CACHE_HCNT0L(c);
-		uint64_t access = ((uint64_t)SCP_CACHE_CCNT0U(c) << 32) |
-			SCP_CACHE_CCNT0L(c);
-
-		ccprintf("%ccache hit count:    %llu\n", cache_name[c], hit);
-		ccprintf("%ccache access count: %llu\n", cache_name[c], access);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo,
-			     NULL,
-			     "Dump cache info");
-
-void scp_memmap_init(void)
-{
-	/*
-	 * Default config, LARGE DRAM not active:
-	 *   REG32(0xA0001F00) & 0x2000 != 0
-	 */
-
-	/*
-	 * SCP_REMAP_CFG1
-	 * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7
-	 * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6
-	 * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
-	 * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
-	 */
-	SCP_REMAP_CFG1 =
-		(uint32_t)addr_map[0x7] << 24 |
-		(uint32_t)addr_map[0x6] << 16 |
-		(uint32_t)addr_map[0x3] << 8 |
-		(uint32_t)addr_map[0x2];
-
-	/*
-	 * SCP_REMAP_CFG2
-	 * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
-	 * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
-	 * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
-	 * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
-	 */
-	SCP_REMAP_CFG2 =
-		(uint32_t)addr_map[0xb] << 24 |
-		(uint32_t)addr_map[0xa] << 16 |
-		(uint32_t)addr_map[0x9] << 8 |
-		(uint32_t)addr_map[0x8];
-	/*
-	 * SCP_REMAP_CFG3
-	 * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
-	 * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
-	 * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
-	 * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
-	 */
-	SCP_REMAP_CFG3 =
-		(uint32_t)addr_map[0xd] << 28 |
-		(uint32_t)addr_map[0xf] << 16 |
-		(uint32_t)addr_map[0xe] << 8 |
-		(uint32_t)addr_map[0xc];
-
-	/* Initialize cache remapping. */
-	scp_cache_init();
-}
-
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
-{
-	int i;
-	uint8_t msb = ap_addr >> SCP_REMAP_ADDR_SHIFT;
-
-	for (i = 0; i < ARRAY_SIZE(addr_map); i++) {
-		if (addr_map[i] != msb)
-			continue;
-
-		*scp_addr = (ap_addr & SCP_REMAP_ADDR_LSB_MASK) |
-			(i << SCP_REMAP_ADDR_SHIFT);
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
-{
-	int i = scp_addr >> SCP_REMAP_ADDR_SHIFT;
-
-	if (addr_map[i] == MAP_INVALID)
-		return EC_ERROR_INVAL;
-
-	*ap_addr = (scp_addr & SCP_REMAP_ADDR_LSB_MASK) |
-		(addr_map[i] << SCP_REMAP_ADDR_SHIFT);
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_DRAM_BASE
-BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
-BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
-#endif
-
-int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr)
-{
-	uintptr_t lsb;
-
-	if ((ap_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != CACHE_TRANS_AP_ADDR)
-		return EC_ERROR_INVAL;
-
-	lsb = ap_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
-	if (lsb > CACHE_TRANS_AP_SIZE)
-		return EC_ERROR_INVAL;
-
-	*scp_addr = CACHE_TRANS_SCP_CACHE_ADDR | lsb;
-	return EC_SUCCESS;
-}
-
-int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
-{
-	uintptr_t lsb;
-
-	if ((scp_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) !=
-			CACHE_TRANS_SCP_CACHE_ADDR)
-		return EC_ERROR_INVAL;
-
-	lsb = scp_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
-	if (lsb >= CACHE_TRANS_AP_SIZE)
-		return EC_ERROR_INVAL;
-
-	*ap_addr = CACHE_TRANS_AP_ADDR | lsb;
-	return EC_SUCCESS;
-}
diff --git a/chip/mt_scp/mt8183/memmap.h b/chip/mt_scp/mt8183/memmap.h
deleted file mode 100644
index fbecb5e8cf..0000000000
--- a/chip/mt_scp/mt8183/memmap.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SCP memory map
- */
-
-#ifndef __CROS_EC_MEMMAP_H
-#define __CROS_EC_MEMMAP_H
-
-void scp_memmap_init(void);
-
-/**
- * Translate AP addr to SCP addr.
- *
- * @param ap_addr		AP address to translate
- * @param scp_addr		Tranlated AP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr);
-
-/**
- * Translate SCP addr to AP addr.
- *
- * @param scp_addr		SCP address to tranlate
- * @param ap_addr		Translated SCP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
-
-/**
- * Translate AP addr to SCP cache addr.
- *
- * @param ap_addr		AP address to translate
- * @param scp_addr		Tranlated AP cache address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr);
-
-/**
- * Translate SCP addr to AP addr.
- *
- * @param scp_addr		SCP cache address to tranlate
- * @param ap_addr		Translated SCP cache address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
-
-#endif /* #ifndef __CROS_EC_MEMMAP_H */
diff --git a/chip/mt_scp/mt8183/registers.h b/chip/mt_scp/mt8183/registers.h
deleted file mode 100644
index 21270b452d..0000000000
--- a/chip/mt_scp/mt8183/registers.h
+++ /dev/null
@@ -1,645 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for SCP
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-/* IRQ numbers */
-#define SCP_IRQ_IPC0			0
-#define SCP_IRQ_IPC1			1
-#define SCP_IRQ_IPC2			2
-#define SCP_IRQ_IPC3			3
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-#define SCP_IRQ_UART0			8
-#define SCP_IRQ_UART1			9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1			11
-#define SCP_IRQ_I2C2			12
-#define SCP_IRQ_CLOCK			13
-#define SCP_IRQ_MAD_FIFO		14
-#define SCP_IRQ_TIMER0			15
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_TIMER_STATUS		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-#define SCP_IRQ_DMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD1_F216		26
-#define SCP_IRQ_MD1			27
-#define SCP_IRQ_C2K			28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-#define SCP_IRQ_AP_EINT			32
-#define SCP_IRQ_DEBUG			33
-#define SCP_CCIF0			34
-#define SCP_CCIF1			35
-#define SCP_CCIF2			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_USB0			38
-#define SCP_IRQ_USB1			39
-#define SCP_IRQ_TWAM			40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_HWDVFS_HIGH		42
-#define SCP_IRQ_HWDVFS_LOW		43
-#define SCP_IRQ_CLOCK2			44
-/* RESERVED 45-52 */
-#define SCP_IRQ_AP_EINT2		53
-#define SCP_IRQ_AP_EINT_EVT		54
-#define SCP_IRQ_MAD_DATA		55
-
-#define SCP_CFG_BASE			0x405C0000
-
-#define SCP_AP_RESOURCE			REG32(SCP_CFG_BASE + 0x04)
-#define SCP_BUS_RESOURCE		REG32(SCP_CFG_BASE + 0x08)
-
-/* SCP to host interrupt */
-#define SCP_HOST_INT			REG32(SCP_CFG_BASE + 0x1C)
-#define   IPC_SCP2HOST_SSHUB		0xff0000
-#define   WDT_INT			0x100
-#define   IPC_SCP2HOST                  0xff
-#define   IPC_SCP2HOST_BIT		0x1
-
-/* SCP to SPM interrupt */
-#define SCP_SPM_INT			REG32(SCP_CFG_BASE + 0x20)
-#define   SPM_INT_A2SPM			BIT(0)
-#define   SPM_INT_B2SPM			BIT(1)
-#define SCP_SPM_INT2			REG32(SCP_CFG_BASE + 0x24)
-
-/*
- * AP side to SCP IPC
- * APMCU writes 1 bit to trigger ith IPC to SCP.
- * SCP writes 1 bit to ith bit to clear ith IPC.
- */
-#define SCP_GIPC_IN			REG32(SCP_CFG_BASE + 0x28)
-  #define SCP_GIPC_IN_CLEAR_IPCN(n)	(1 << (n))
-  #define SCP_GPIC_IN_CLEAR_ALL		0x7FFFF
-#define SCP_CONN_INT			REG32(SCP_CFG_BASE + 0x2C)
-
-/* 8 general purpose registers, 0 ~ 7 */
-#define SCP_GPR				REG32_ADDR(SCP_CFG_BASE + 0x50)
-/*
- * SCP_GPR[0]
- *   b15-b0   : scratchpad
- *   b31-b16  : saved flags
- * SCP_GPR[1]
- *   b15-b0   : power on state
- */
-#define SCP_PWRON_STATE			SCP_GPR[1]
-#define   PWRON_DEFAULT			0xdee80000
-#define   PWRON_WATCHDOG		BIT(0)
-#define   PWRON_RESET			BIT(1)
-/* AP defined features */
-#define SCP_EXPECTED_FREQ		SCP_GPR[3]
-#define SCP_CURRENT_FREQ		SCP_GPR[4]
-#define SCP_REBOOT			SCP_GPR[5]
-#define  READY_TO_REBOOT		0x34
-#define  REBOOT_OK			1
-
-/* Miscellaneous */
-#define SCP_SEMAPHORE			REG32(SCP_CFG_BASE + 0x90)
-#define CORE_CONTROL			REG32(SCP_CFG_BASE + 0xA0)
-#define CORE_FPU_FLAGS			REG32(SCP_CFG_BASE + 0xA4)
-#define CORE_REG_SP			REG32(SCP_CFG_BASE + 0xA8)
-#define CORE_REG_LR			REG32(SCP_CFG_BASE + 0xAC)
-#define CORE_REG_PSP			REG32(SCP_CFG_BASE + 0xB0)
-#define CORE_REG_PC			REG32(SCP_CFG_BASE + 0xB4)
-#define SCP_SLP_PROTECT_CFG		REG32(SCP_CFG_BASE + 0xC8)
-#define   P_CACHE_SLP_PROT_EN		BIT(3)
-#define   D_CACHE_SLP_PROT_EN		BIT(4)
-#define SCP_ONE_TIME_LOCK		REG32(SCP_CFG_BASE + 0xDC)
-#define SCP_SECURE_CTRL			REG32(SCP_CFG_BASE + 0xE0)
-#define   ENABLE_SPM_MASK_VREQ		BIT(28)
-#define   DISABLE_REMAP			BIT(22)
-#define   DISABLE_JTAG			BIT(21)
-#define   DISABLE_AP_TCM		BIT(20)
-#define SCP_SYS_CTRL			REG32(SCP_CFG_BASE + 0xE4)
-#define   DDREN_FIX_VALUE		BIT(28)
-#define   AUTO_DDREN			BIT(18)
-
-/* Memory remap control */
-/*
- * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7
- * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6
- * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
- * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
- */
-#define SCP_REMAP_CFG1			REG32(SCP_CFG_BASE + 0x120)
-/*
- * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
- * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
- * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
- * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
- */
-#define SCP_REMAP_CFG2			REG32(SCP_CFG_BASE + 0x124)
-/*
- * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
- * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
- * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
- * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
- */
-#define SCP_REMAP_CFG3			REG32(SCP_CFG_BASE + 0x128)
-
-#define SCP_REMAP_ADDR_SHIFT		28
-#define SCP_REMAP_ADDR_LSB_MASK		(BIT(SCP_REMAP_ADDR_SHIFT) - 1)
-#define SCP_REMAP_ADDR_MSB_MASK		((~0) << SCP_REMAP_ADDR_SHIFT)
-
-/* Cached memory remap control */
-#define SCP_L1_REMAP_CFG0		REG32(SCP_CFG_BASE + 0x12C)
-/*
- * L1C_EXT_ADDR1[29:16] remap register for addr msb 31~20 equal to 0x401
- * L1C_EXT_ADDR0[13:0]  remap register for addr msb 31~20 equal to 0x400
- */
-#define SCP_L1_REMAP_CFG1		REG32(SCP_CFG_BASE + 0x130)
-/*
- * L1C_EXT_ADDR3[29:16] remap register for addr msb 31~20 equal to 0x403
- * L1C_EXT_ADDR2[13:0]  remap register for addr msb 31~20 equal to 0x402
- */
-#define SCP_L1_REMAP_CFG2		REG32(SCP_CFG_BASE + 0x134)
-/*
- * L1C_EXT_ADDR5[29:16] remap register for addr msb 31~20 equal to 0x405
- * L1C_EXT_ADDR4[13:0]  remap register for addr msb 31~20 equal to 0x404
- */
-#define SCP_L1_REMAP_CFG3		REG32(SCP_CFG_BASE + 0x138)
-/*
- * L1C_EXT_ADDR_OTHER1[13:8] Remap register for addr msb 31 to 28 equal to 0x1
- * L1C_EXT_ADDR_OTHER0[5:0] Remap register for addr msb 31 to 28 equal to 0x0
- * and not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7
- */
-#define SCP_L1_REMAP_OTHER		REG32(SCP_CFG_BASE + 0x13C)
-
-#define SCP_L1_EXT_ADDR_SHIFT		20
-#define SCP_L1_EXT_ADDR_OTHER_SHIFT	28
-#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK	(BIT(SCP_REMAP_ADDR_SHIFT) - 1)
-#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK	((~0) << SCP_REMAP_ADDR_SHIFT)
-
-/* Audio/voice FIFO */
-#define SCP_AUDIO_BASE			(SCP_CFG_BASE + 0x1000)
-#define SCP_VIF_FIFO_EN			REG32(SCP_AUDIO_BASE)
-#define   VIF_FIFO_RSTN			(1 << 0)
-#define   VIF_FIFO_IRQ_EN		(1 << 1)
-#define   VIF_FIFO_SRAM_PWR		(1 << 2)
-#define   VIF_FIFO_RSTN_STATUS		(1 << 4)
-#define SCP_VIF_FIFO_STATUS		REG32(SCP_AUDIO_BASE + 0x04)
-#define   VIF_FIFO_VALID		(1 << 0)
-#define   VIF_FIFO_FULL			(1 << 4)
-#define   VIF_FIFO_LEVEL(status)	(((status) >> 16) & 0xff)
-#define   VIF_FIFO_MAX			256
-#define SCP_VIF_FIFO_DATA		REG32(SCP_AUDIO_BASE + 0x08)
-#define SCP_VIF_FIFO_DATA_THRE		REG32(SCP_AUDIO_BASE + 0x0C)
-/* VIF IRQ status clears on read! */
-#define SCP_VIF_FIFO_IRQ_STATUS		REG32(SCP_AUDIO_BASE + 0x10)
-/* Audio/voice serial interface */
-#define SCP_RXIF_CFG0			REG32(SCP_AUDIO_BASE + 0x14)
-#define   RXIF_CFG0_RESET_VAL		0x2A130001
-#define   RXIF_AFE_ON			(1 << 0)
-#define   RXIF_SCKINV			(1 << 1)
-#define   RXIF_RG_DL_2_IN_MODE(mode)	(((mode) & 0xf) << 8)
-#define   RXIF_RGDL2_AMIC_16K		(0x1 << 8)
-#define   RXIF_RGDL2_DMIC_16K		(0x2 << 8)
-#define   RXIF_RGDL2_DMIC_LP_16K	(0x3 << 8)
-#define   RXIF_RGDL2_AMIC_32K		(0x5 << 8)
-#define   RXIF_RGDL2_MASK		(0xf << 8)
-#define   RXIF_UP8X_RSP(p)		(((p) & 0x7) << 16)
-#define   RXIF_RG_RX_READEN		(1 << 19)
-#define   RXIF_MONO			(1 << 20)
-#define   RXIF_RG_CLK_A16P7K_EN(cnt)	(((cnt) & 0xff) << 24)
-#define SCP_RXIF_CFG1			REG32(SCP_AUDIO_BASE + 0x18)
-#define   RXIF_CFG1_RESET_VAL		0x33180014
-#define   RXIF_RG_SYNC_CNT_TBL(t)	((t) & 0x1ff)
-#define   RXIF_RG_SYNC_SEARCH_TBL(t)	(((t) & 0x1f) << 16)
-#define   RXIF_RG_SYNC_CHECK_ROUND(r)	(((r) & 0xf) << 24)
-#define   RXIF_RG_INSYNC_CHECK_ROUND(r)	(((r) & 0xf) << 28)
-#define SCP_RXIF_CFG2			REG32(SCP_AUDIO_BASE + 0x1C)
-#define   RXIF_SYNC_WORD(w)		((w) & 0xffff)
-#define SCP_RXIF_OUT			REG32(SCP_AUDIO_BASE + 0x20)
-#define SCP_RXIF_STATUS			REG32(SCP_AUDIO_BASE + 0x24)
-#define SCP_RXIF_IRQ_EN			REG32(SCP_AUDIO_BASE + 0x28)
-
-/* INTC control */
-#define SCP_INTC_BASE			(SCP_CFG_BASE + 0x2000)
-#define SCP_INTC_IRQ_STATUS		REG32(SCP_INTC_BASE)
-#define SCP_INTC_IRQ_ENABLE		REG32(SCP_INTC_BASE + 0x04)
-#define   IPC0_IRQ_EN			BIT(0)
-#define SCP_INTC_IRQ_OUTPUT		REG32(SCP_INTC_BASE + 0x08)
-#define SCP_INTC_IRQ_WAKEUP		REG32(SCP_INTC_BASE + 0x0C)
-#define SCP_INTC_NMI			REG32(SCP_INTC_BASE + 0x10)
-#define SCP_INTC_SPM_WAKEUP		REG32(SCP_INTC_BASE + 0x14)
-#define SCP_INTC_SPM_WAKEUP_MSB		REG32(SCP_INTC_BASE + 0x18)
-#define SCP_INTC_UART_RX_IRQ		REG32(SCP_INTC_BASE + 0x1C)
-#define SCP_INTC_IRQ_STATUS_MSB		REG32(SCP_INTC_BASE + 0x80)
-#define SCP_INTC_IRQ_ENABLE_MSB		REG32(SCP_INTC_BASE + 0x84)
-#define SCP_INTC_IRQ_OUTPUT_MSB		REG32(SCP_INTC_BASE + 0x88)
-#define SCP_INTC_IRQ_WAKEUP_MSB		REG32(SCP_INTC_BASE + 0x8C)
-
-/* Timer */
-#define NUM_TIMERS			6
-#define SCP_TIMER_BASE(n)		(SCP_CFG_BASE + 0x3000 + (0x10 * (n)))
-#define SCP_TIMER_EN(n)			REG32(SCP_TIMER_BASE(n))
-#define SCP_TIMER_RESET_VAL(n)		REG32(SCP_TIMER_BASE(n) + 0x04)
-#define SCP_TIMER_VAL(n)		REG32(SCP_TIMER_BASE(n) + 0x08)
-#define SCP_TIMER_IRQ_CTRL(n)		REG32(SCP_TIMER_BASE(n) + 0x0C)
-#define   TIMER_IRQ_ENABLE		BIT(0)
-#define   TIMER_IRQ_STATUS		BIT(4)
-#define   TIMER_IRQ_CLEAR		BIT(5)
-#define SCP_TIMER_CLK_SEL(n)		REG32(SCP_TIMER_BASE(n) + 0x40)
-#define   TIMER_CLK_32K			(0 << 4)
-#define   TIMER_CLK_26M			BIT(4)
-#define   TIMER_CLK_BCLK		(2 << 4)
-#define   TIMER_CLK_PCLK		(3 << 4)
-#define   TIMER_CLK_MASK		(3 << 4)
-/* OS timer */
-#define SCP_OSTIMER_BASE		(SCP_CFG_BASE + 0x3080)
-#define SCP_OSTIMER_CON			REG32(SCP_OSTIMER_BASE)
-#define SCP_OSTIMER_INIT_L		REG32(SCP_OSTIMER_BASE + 0x04)
-#define SCP_OSTIMER_INIT_H		REG32(SCP_OSTIMER_BASE + 0x08)
-#define SCP_OSTIMER_VAL_L		REG32(SCP_OSTIMER_BASE + 0x0C)
-#define SCP_OSTIMER_VAL_H		REG32(SCP_OSTIMER_BASE + 0x10)
-#define SCP_OSTIMER_TVAL		REG32(SCP_OSTIMER_BASE + 0x14)
-#define SCP_OSTIMER_IRQ_ACK		REG32(SCP_OSTIMER_BASE + 0x18)
-#define   OSTIMER_LATCH0_EN		BIT(5)
-#define   OSTIMER_LATCH1_EN		BIT(13)
-#define   OSTIMER_LATCH2_EN		BIT(21)
-#define SCP_OSTIMER_LATCH_CTRL		REG32(SCP_OSTIMER_BASE + 0x20)
-#define SCP_OSTIMER_LATCH0_L		REG32(SCP_OSTIMER_BASE + 0x24)
-#define SCP_OSTIMER_LATCH0_H		REG32(SCP_OSTIMER_BASE + 0x28)
-#define SCP_OSTIMER_LATCH1_L		REG32(SCP_OSTIMER_BASE + 0x2C)
-#define SCP_OSTIMER_LATCH1_H		REG32(SCP_OSTIMER_BASE + 0x30)
-#define SCP_OSTIMER_LATCH2_L		REG32(SCP_OSTIMER_BASE + 0x34)
-#define SCP_OSTIMER_LATCH2_H		REG32(SCP_OSTIMER_BASE + 0x38)
-
-/* Clock, PMIC wrapper, etc. */
-#define SCP_CLK_BASE			(SCP_CFG_BASE + 0x4000)
-#define SCP_CLK_SEL			REG32(SCP_CLK_BASE)
-#define   CLK_SEL_SYS_26M		0
-#define   CLK_SEL_32K			1
-#define   CLK_SEL_ULPOSC_2		2
-#define   CLK_SEL_ULPOSC_1		3
-
-#define SCP_CLK_EN			REG32(SCP_CLK_BASE + 0x04)
-#define   EN_CLK_SYS			BIT(0) /* System clock */
-#define   EN_CLK_HIGH			BIT(1) /* ULPOSC */
-#define   CG_CLK_HIGH			BIT(2)
-#define   EN_SYS_IRQ			BIT(16)
-#define   EN_HIGH_IRQ			BIT(17)
-#define SCP_CLK_SAFE_ACK		REG32(SCP_CLK_BASE + 0x08)
-#define SCP_CLK_ACK			REG32(SCP_CLK_BASE + 0x0C)
-#define SCP_CLK_IRQ_ACK			REG32(SCP_CLK_BASE + 0x10)
-/*
- * System clock counter value.
- * CLK_SYS_VAL[9:0] System clock counter initial/reset value.
- */
-#define SCP_CLK_SYS_VAL			REG32(SCP_CLK_BASE + 0x14)
-#define   CLK_SYS_VAL_MASK		0x3ff /* 10 bits */
-#define   CLK_SYS_VAL(n)		((n) & CLK_SYS_VAL_MASK)
-/*
- * ULPOSC clock counter value.
- * CLK_HIGH_VAL[9:0] ULPOSC clock counter initial/reset value.
- */
-#define SCP_CLK_HIGH_VAL		REG32(SCP_CLK_BASE + 0x18)
-#define   CLK_HIGH_VAL_MASK		0x3ff /* 10 bits */
-#define   CLK_HIGH_VAL(n)		((n) & CLK_HIGH_VAL_MASK)
-#define SCP_CLK_SLOW_SEL		REG32(SCP_CLK_BASE + 0x1C)
-#define   CKSW_SEL_SLOW_MASK		0x3
-#define   CKSW_SEL_SLOW_DIV_MASK	0x30
-#define   CKSW_SEL_SLOW_SYS_CLK		0
-#define   CKSW_SEL_SLOW_32K_CLK		1
-#define   CKSW_SEL_SLOW_ULPOSC2_CLK	2
-#define   CKSW_SEL_SLOW_ULPOSC1_CLK	3
-/*
- * Sleep mode control.
- * VREQ_COUNT[7:1] Number of cycles to wait when requesting PMIC to raise the
- *     voltage after returning from  sleep mode.
- */
-#define SCP_CLK_SLEEP_CTRL		REG32(SCP_CLK_BASE + 0x20)
-#define   EN_SLEEP_CTRL			BIT(0)
-#define   VREQ_COUNTER_MASK		0xfe
-#define   VREQ_COUNTER_VAL(v)		(((v) << 1) & VREQ_COUNTER_MASK)
-#define   SPM_SLEEP_MODE		BIT(8)
-#define   SPM_SLEEP_MODE_CLK_AO		BIT(9)
-#define SCP_CLK_DIV_SEL			REG32(SCP_CLK_BASE + 0x24)
-#define   CLK_DIV1			0
-#define   CLK_DIV2			1
-#define   CLK_DIV4			2
-#define   CLK_DIV8			3
-#define SCP_CLK_DEBUG			REG32(SCP_CLK_BASE + 0x28)
-#define SCP_CLK_SRAM_POWERDOWN		REG32(SCP_CLK_BASE + 0x2C)
-#define SCP_CLK_GATE			REG32(SCP_CLK_BASE + 0x30)
-#define   CG_TIMER_M			BIT(0)
-#define   CG_TIMER_B			BIT(1)
-#define   CG_MAD_M			BIT(2)
-#define   CG_I2C_M			BIT(3)
-#define   CG_I2C_B			BIT(4)
-#define   CG_GPIO_M			BIT(5)
-#define   CG_AP2P_M			BIT(6)
-#define   CG_UART_M			BIT(7)
-#define   CG_UART_B			BIT(8)
-#define   CG_UART_RSTN			BIT(9)
-#define   CG_UART1_M			BIT(10)
-#define   CG_UART1_B			BIT(11)
-#define   CG_UART1_RSTN			BIT(12)
-#define   CG_SPI0			BIT(13)
-#define   CG_SPI1			BIT(14)
-#define   CG_SPI2			BIT(15)
-#define   CG_DMA_CH0			BIT(16)
-#define   CG_DMA_CH1			BIT(17)
-#define   CG_DMA_CH2			BIT(18)
-#define   CG_DMA_CH3			BIT(19)
-#define   CG_TWAM			BIT(20)
-#define   CG_CACHE_I_CTRL		BIT(21)
-#define   CG_CACHE_D_CTRL		BIT(22)
-#define SCP_PMICW_CTRL			REG32(SCP_CLK_BASE + 0x34)
-#define   PMICW_SLEEP_REQ		BIT(0)
-#define   PMICW_SLEEP_ACK		BIT(4)
-#define   PMICW_CLK_MUX			BIT(8)
-#define   PMICW_DCM			BIT(9)
-#define SCP_SLEEP_WAKE_DEBUG		REG32(SCP_CLK_BASE + 0x38)
-#define SCP_DCM_EN			REG32(SCP_CLK_BASE + 0x3C)
-#define SCP_WAKE_CKSW			REG32(SCP_CLK_BASE + 0x40)
-#define   WAKE_CKSW_SEL_NORMAL_MASK	0x3
-#define   WAKE_CKSW_SEL_SLOW_MASK	0x30
-#define   WAKE_CKSW_SEL_SLOW_DEFAULT	0x10
-#define SCP_CLK_UART			REG32(SCP_CLK_BASE + 0x44)
-#define   CLK_UART_SEL_MASK		0x3
-#define   CLK_UART_SEL_26M		0x0
-#define   CLK_UART_SEL_32K		0x1
-/* This is named ulposc_div_to_26m in datasheet */
-#define   CLK_UART_SEL_ULPOSC1_DIV10	0x2
-#define   CLK_UART1_SEL_MASK		(0x3 << 16)
-#define   CLK_UART1_SEL_26M		(0x0 << 16)
-#define   CLK_UART1_SEL_32K		(0x1 << 16)
-/* This is named ulposc_div_to_26m in datasheet */
-#define   CLK_UART1_SEL_ULPOSC1_DIV10	(0x2 << 16)
-#define SCP_CLK_BCLK			REG32(SCP_CLK_BASE + 0x48)
-#define   CLK_BCLK_SEL_MASK		0x3
-#define   CLK_BCLK_SEL_SYS_DIV8		0x0
-#define   CLK_BCLK_SEL_32K		0x1
-#define   CLK_BCLK_SEL_ULPOSC1_DIV8	0x2
-#define SCP_CLK_SPI_BCK			REG32(SCP_CLK_BASE + 0x4C)
-#define SCP_CLK_DIV_CNT			REG32(SCP_CLK_BASE + 0x50)
-#define SCP_CPU_VREQ			REG32(SCP_CLK_BASE + 0x54)
-#define   CPU_VREQ_HW_MODE		0x10001
-#define SCP_CLK_CLEAR			REG32(SCP_CLK_BASE + 0x58)
-#define SCP_CLK_HIGH_CORE		REG32(SCP_CLK_BASE + 0x5C)
-#define   CLK_HIGH_CORE_CG		(1 << 1)
-#define SCP_SLEEP_IRQ2			REG32(SCP_CLK_BASE + 0x64)
-#define SCP_CLK_ON_CTRL			REG32(SCP_CLK_BASE + 0x6C)
-#define   HIGH_AO			BIT(0)
-#define   HIGH_CG_AO			BIT(2)
-#define   HIGH_CORE_AO			BIT(4)
-#define   HIGH_CORE_DIS_SUB		BIT(5)
-#define   HIGH_CORE_CG_AO		BIT(6)
-#define   HIGH_FINAL_VAL_MASK		0x1f00
-#define   HIGH_FINAL_VAL_DEFAULT	0x300
-#define SCP_CLK_L1_SRAM_PD		REG32(SCP_CLK_BASE + 0x80)
-#define SCP_CLK_TCM_TAIL_SRAM_PD	REG32(SCP_CLK_BASE + 0x94)
-#define SCP_CLK_SLEEP			REG32(SCP_CLK_BASE + 0xA0)
-#define   SLOW_WAKE_DISABLE		1
-#define SCP_FAST_WAKE_CNT_END		REG32(SCP_CLK_BASE + 0xA4)
-#define   FAST_WAKE_CNT_END_MASK	0xfff
-#define   FAST_WAKE_CNT_END_DEFAULT	0x18
-#define   MEM_CK_CS_ISO_CNT_END_MASK	0x7f0000
-
-/* Peripherals */
-#define SCP_I2C0_BASE			(SCP_CFG_BASE + 0x5000)
-#define SCP_I2C1_BASE			(SCP_CFG_BASE + 0x6000)
-#define SCP_I2C2_BASE			(SCP_CFG_BASE + 0x7000)
-
-#define SCP_GPIO_BASE			(SCP_CFG_BASE + 0x8000)
-#define SCP_UART0_BASE			(SCP_CFG_BASE + 0x9000)
-#define SCP_UART1_BASE			(SCP_CFG_BASE + 0xE000)
-#define SCP_UART_COUNT			2
-
-/* External GPIO interrupt */
-#define SCP_EINT_BASE			(SCP_CFG_BASE + 0xA000)
-#define SCP_EINT_STATUS			REG32_ADDR(SCP_EINT_BASE)
-#define SCP_EINT_ACK			REG32_ADDR(SCP_EINT_BASE + 0x040)
-#define SCP_EINT_MASK_GET		REG32_ADDR(SCP_EINT_BASE + 0x080)
-#define SCP_EINT_MASK_SET		REG32_ADDR(SCP_EINT_BASE + 0x0C0)
-#define SCP_EINT_MASK_CLR		REG32_ADDR(SCP_EINT_BASE + 0x100)
-#define SCP_EINT_SENS_GET		REG32_ADDR(SCP_EINT_BASE + 0x140)
-#define SCP_EINT_SENS_SET		REG32_ADDR(SCP_EINT_BASE + 0x180)
-#define SCP_EINT_SENS_CLR		REG32_ADDR(SCP_EINT_BASE + 0x1C0)
-#define SCP_EINT_SOFT_GET		REG32_ADDR(SCP_EINT_BASE + 0x200)
-#define SCP_EINT_SOFT_SET		REG32_ADDR(SCP_EINT_BASE + 0x240)
-#define SCP_EINT_SOFT_CLR		REG32_ADDR(SCP_EINT_BASE + 0x280)
-#define SCP_EINT_POLARITY_GET		REG32_ADDR(SCP_EINT_BASE + 0x300)
-#define SCP_EINT_POLARITY_SET		REG32_ADDR(SCP_EINT_BASE + 0x340)
-#define SCP_EINT_POLARITY_CLR		REG32_ADDR(SCP_EINT_BASE + 0x380)
-#define SCP_EINT_D0_EN			REG32_ADDR(SCP_EINT_BASE + 0x400)
-#define SCP_EINT_D1_EN			REG32_ADDR(SCP_EINT_BASE + 0x420)
-#define SCP_EINT_DBNC_GET		REG32_ADDR(SCP_EINT_BASE + 0x500)
-#define SCP_EINT_DBNC_SET		REG32_ADDR(SCP_EINT_BASE + 0x600)
-#define SCP_EINT_DBNC_CLR		REG32_ADDR(SCP_EINT_BASE + 0x700)
-
-#define SCP_PMICWP2P_BASE		(SCP_CFG_BASE + 0xB000)
-#define   PMICW_WACS_CMD		REG32(SCP_PMICWP2P_BASE + 0x200)
-#define   PMICW_WACS_RDATA		REG32(SCP_PMICWP2P_BASE + 0x204)
-#define   PMICW_WACS_VLDCLR		REG32(SCP_PMICWP2P_BASE + 0x208)
-#define SCP_SPMP2P_BASE			(SCP_CFG_BASE + 0xC000)
-#define SCP_DMA_BASE			(SCP_CFG_BASE + 0xD000)
-#define   DMA_ACKINT_CHX		REG32(SCP_DMA_BASE + 0x20)
-#define SCP_SPI0_BASE			(SCP_CFG_BASE + 0xF000)
-#define SCP_SPI1_BASE			(SCP_CFG_BASE + 0x10000)
-#define SCP_SPI2_BASE			(SCP_CFG_BASE + 0x11000)
-
-#define CACHE_ICACHE 0
-#define CACHE_DCACHE 1
-#define CACHE_COUNT 2
-#define SCP_CACHE_BASE			(SCP_CFG_BASE + 0x14000)
-#define SCP_CACHE_SEL(x)		(SCP_CACHE_BASE + (x)*0x3000)
-#define SCP_CACHE_CON(x)		REG32(SCP_CACHE_SEL(x))
-#define SCP_CACHE_CON_MCEN		BIT(0)
-#define SCP_CACHE_CON_CNTEN0		BIT(2)
-#define SCP_CACHE_CON_CNTEN1		BIT(3)
-#define SCP_CACHE_CON_CACHESIZE_SHIFT	8
-#define SCP_CACHE_CON_CACHESIZE_MASK	(0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_0KB	(0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_8KB	(0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_16KB	(0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_32KB	(0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_WAYEN		BIT(10)
-
-#define SCP_CACHE_OP(x)			REG32(SCP_CACHE_SEL(x) + 0x04)
-#define SCP_CACHE_OP_EN			BIT(0)
-#define SCP_CACHE_OP_OP_SHIFT		1
-#define SCP_CACHE_OP_OP_MASK		(0xf << SCP_CACHE_OP_OP_SHIFT)
-
-#define   OP_INVALIDATE_ALL_LINES		(0x1 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_INVALIDATE_ONE_LINE_BY_ADDRESS	(0x2 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_INVALIDATE_ONE_LINE_BY_SET_WAY	(0x4 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ALL_LINES		(0x9 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS	(0xa << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY	(0xc << SCP_CACHE_OP_OP_SHIFT)
-
-#define SCP_CACHE_OP_TADDR_SHIFT	5
-#define SCP_CACHE_OP_TADDR_MASK		(0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT)
-#define SCP_CACHE_LINE_SIZE		BIT(SCP_CACHE_OP_TADDR_SHIFT)
-
-/* Cache statistics */
-#define SCP_CACHE_HCNT0L(x)		REG32(SCP_CACHE_SEL(x) + 0x08)
-#define SCP_CACHE_HCNT0U(x)		REG32(SCP_CACHE_SEL(x) + 0x0c)
-#define SCP_CACHE_CCNT0L(x)		REG32(SCP_CACHE_SEL(x) + 0x10)
-#define SCP_CACHE_CCNT0U(x)		REG32(SCP_CACHE_SEL(x) + 0x14)
-#define SCP_CACHE_HCNT1L(x)		REG32(SCP_CACHE_SEL(x) + 0x18)
-#define SCP_CACHE_HCNT1U(x)		REG32(SCP_CACHE_SEL(x) + 0x1c)
-#define SCP_CACHE_CCNT1L(x)		REG32(SCP_CACHE_SEL(x) + 0x20)
-#define SCP_CACHE_CCNT1U(x)		REG32(SCP_CACHE_SEL(x) + 0x24)
-
-#define SCP_CACHE_REGION_EN(x)		REG32(SCP_CACHE_SEL(x) + 0x2c)
-
-#define SCP_CACHE_ENTRY_BASE(x)		(SCP_CACHE_SEL(x) + 0x2000)
-#define SCP_CACHE_ENTRY(x, reg)		REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4)
-#define SCP_CACHE_END_ENTRY_BASE(x)	(SCP_CACHE_SEL(x) + 0x2040)
-#define SCP_CACHE_END_ENTRY(x, reg)	REG32(SCP_CACHE_END_ENTRY_BASE(x) + \
-						(reg)*4)
-#define SCP_CACHE_ENTRY_C		BIT(8)
-#define SCP_CACHE_ENTRY_BASEADDR_MASK	(0xfffff << 12)
-
-/* ARMV7 regs */
-#define ARM_SCB_SCR			REG32(0xE000ED10)
-#define   SCR_DEEPSLEEP			BIT(2)
-
-/* AP regs */
-#define AP_BASE				0xA0000000
-#define TOPCK_BASE			AP_BASE /* Top clock */
-#define SCP_UART2_BASE			(AP_BASE + 0x01002000) /* AP UART0 */
-
-/* CLK_CFG_5 regs */
-#define AP_CLK_CFG_5		REG32(TOPCK_BASE + 0x0090)
-#define   PWRAP_ULPOSC_MASK	(0x3000000)
-#define   CLK26M			(0 << 24)
-#define   OSC_D16			(1 << 24)
-#define   OSC_D4			(2 << 24)
-#define   OSC_D8			(3 << 24)
-#define AP_CLK_CFG_5_CLR	REG32(TOPCK_BASE + 0x0098)
-#define   PWRAP_ULPOSC_CG	BIT(31)
-
-/* OSC meter */
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x0104)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x010C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK            0
-#define   DBG_BIST_SOURCE_MASK		(0x3f << 16)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x26 << 16)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x25 << 16)
-#define AP_SCP_CFG_0			REG32(TOPCK_BASE + 0x0220)
-#define   CFG_FREQ_METER_RUN		(1 << 4)
-#define   CFG_FREQ_METER_ENABLE		(1 << 12)
-#define AP_SCP_CFG_1			REG32(TOPCK_BASE + 0x0224)
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
-
-/* GPIO */
-#define AP_GPIO_BASE			(AP_BASE + 0x00005000)
-/*
- * AP_GPIO_DIR
- * GPIO input/out direction, 1 bit per pin.
- * 0:input 1:output
- */
-#define AP_GPIO_DIR(n)			REG32(AP_GPIO_BASE + ((n) << 4))
-/*
- * AP_GPIO_DOUT, n in [0..5]
- * GPIO output level, 1 bit per pin
- * 0:low 1:high
- */
-#define AP_GPIO_DOUT(n)			REG32(AP_GPIO_BASE + 0x100 + ((n) << 4))
-/*
- * AP_GPIO_DIN, n in [0..5]
- * GPIO input level, 1 bit per pin
- * 0:low 1:high
- */
-#define AP_GPIO_DIN(n)			REG32(AP_GPIO_BASE + 0x200 + ((n) << 4))
-/*
- * AP_GPIO_MODE, n in [0..22]
- * Pin mode selection, 4 bit per pin
- * bit3   - write enable, set to 1 for hw to fetch bit2,1,0.
- * bit2-0 - mode 0 ~ 7
- */
-#define AP_GPIO_MODE(n)			REG32(AP_GPIO_BASE + 0x300 + ((n) << 4))
-#define AP_GPIO_TRAP			REG32(AP_GPIO_BASE + 0x6B0)
-#define AP_GPIO_UNIMPLEMENTED		REG32(AP_GPIO_BASE + 0x6C0)
-#define AP_GPIO_DBG			REG32(AP_GPIO_BASE + 0x6D0)
-#define AP_GPIO_BANK			REG32(AP_GPIO_BASE + 0x6E0)
-/* AP_GPIO_SEC, n in [0..5] */
-#define AP_GPIO_SEC(n)			REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4))
-
-/*
- * PLL ULPOSC
- * ULPOSC1:  AP_ULPOSC_CON[0] AP_ULPOSC_CON[1]
- * ULPOSC2:  AP_ULPOSC_CON[2] AP_ULPOSC_CON[3]
- * osc: 0 for ULPOSC1, 1 for ULPSOC2.
- */
-#define AP_ULPOSC_BASE0			(AP_BASE + 0xC700)
-#define AP_ULPOSC_BASE1			(AP_BASE + 0xC704)
-#define AP_ULPOSC_CON02(osc)		REG32(AP_ULPOSC_BASE0 + (osc) * 0x8)
-#define AP_ULPOSC_CON13(osc)		REG32(AP_ULPOSC_BASE1 + (osc) * 0x8)
-/*
- * AP_ULPOSC_CON[0,2]
- * bit0-5:   calibration
- * bit6-12:  I-band
- * bit13-16: F-band
- * bit17-22: div
- * bit23:    CP_EN
- * bit24-31: reserved
- */
-#define OSC_CALI_MSK			(0x3f << 0)
-#define OSC_CALI_BITS			6
-#define OSC_IBAND_MASK			(0x7f << 6)
-#define OSC_FBAND_MASK			(0x0f << 13)
-#define OSC_DIV_MASK			(0x1f << 17)
-#define OSC_DIV_BITS			5
-#define OSC_CP_EN			BIT(23)
-#define OSC_RESERVED_MASK		(0xff << 24)
-/* AP_ULPOSC_CON[1,3] */
-#define OSC_MOD_MASK			(0x03 << 0)
-#define OSC_DIV2_EN			BIT(2)
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-#ifndef __ASSEMBLER__
-
-/*
- * Cortex-M4 mod
- * Available power saving features:
- * 1. FPU freeze - freeze FPU operand when FPU is not used
- * 2. LSU gating - gate LSU clock when not LSU operation
- * 3. Trace clk disable - gate trace clock
- * 4. DCM for CPU stall - gate CPU clock when CPU stall
- */
-#define CM4_MODIFICATION		REG32(0xE00FE000)
-#define CM4_DCM_FEATURE			REG32(0xE00FE004)
-/* UART, 16550 compatible */
-#define SCP_UART_BASE(n)		CONCAT3(SCP_UART, n, _BASE)
-#define UART_REG(n, offset)		REG32_ADDR(SCP_UART_BASE(n))[offset]
-#define UART_IRQ(n)			CONCAT2(SCP_IRQ_UART, n)
-#define UART_RX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _RX)
-
-/* Watchdog */
-#define SCP_WDT_BASE			(SCP_CFG_BASE + 0x84)
-#define SCP_WDT_REG(offset)		REG32(SCP_WDT_BASE + offset)
-#define SCP_WDT_CFG			SCP_WDT_REG(0)
-#define   SCP_WDT_FREQ			33825
-#define   SCP_WDT_MAX_PERIOD		0xFFFFF /* 31 seconds */
-#define   SCP_WDT_PERIOD(ms)		(SCP_WDT_FREQ * (ms) / 1000)
-#define   SCP_WDT_ENABLE		BIT(31)
-#define SCP_WDT_RELOAD			SCP_WDT_REG(4)
-#define   SCP_WDT_RELOAD_VALUE		1
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt_scp/mt8183/serial_reg.h b/chip/mt_scp/mt8183/serial_reg.h
deleted file mode 100644
index 5344566272..0000000000
--- a/chip/mt_scp/mt8183/serial_reg.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * UART register map
- */
-
-#ifndef __CROS_EC_SERIAL_REG_H
-#define __CROS_EC_SERIAL_REG_H
-
-#include "registers.h"
-
-/* Number of hardware ports */
-#define HW_UART_PORTS 2
-
-/* DLAB (Divisor Latch Access Bit) == 0 */
-
-/* Data register
- *   (Read) Rcvr buffer register
- *   (Write) Xmit holding register
- */
-#define UART_DATA(n)			UART_REG(n, 0)
-/* (Write) Interrupt enable register */
-#define UART_IER(n)			UART_REG(n, 1)
-#define UART_IER_RDI			BIT(0) /* Recv data int */
-#define UART_IER_THRI			BIT(1) /* Xmit holding register int */
-#define UART_IER_RLSI			BIT(2) /* Rcvr line status int */
-#define UART_IER_MSI			BIT(3) /* Modem status int */
-/* (Read) Interrupt ID register */
-#define UART_IIR(n)			UART_REG(n, 2)
-#define UART_IIR_NO_INT			BIT(0) /* No int pending */
-#define UART_IIR_ID_MASK		0x0e /* Interrupt ID mask */
-#define UART_IIR_MSI			0x00
-#define UART_IIR_THRI			0x02
-#define UART_IIR_RDI			0x04
-#define UART_IIR_RLSI			0x06
-#define UART_IIR_BUSY			0x07 /* DW APB busy */
-/* (Write) FIFO control register */
-#define UART_FCR(n)			UART_REG(n, 2)
-#define UART_FCR_ENABLE_FIFO		BIT(0) /* Enable FIFO */
-#define UART_FCR_CLEAR_RCVR		BIT(1) /* Clear rcvr FIFO */
-#define UART_FCR_CLEAR_XMIT		BIT(2) /* Clear xmit FIFO */
-#define UART_FCR_DMA_SELECT		BIT(3)
-/* FIFO trigger levels */
-#define UART_FCR_T_TRIG_00		0x00
-#define UART_FCR_T_TRIG_01		0x10
-#define UART_FCR_T_TRIG_10		0x20
-#define UART_FCR_T_TRIG_11		0x30
-#define UART_FCR_R_TRIG_00		0x00
-#define UART_FCR_R_TRIG_01		0x40
-#define UART_FCR_R_TRIG_10		0x80
-#define UART_FCR_R_TRIG_11		0x80
-/* (Write) Line control register */
-#define UART_LCR(n)			UART_REG(n, 3)
-#define UART_LCR_WLEN5			0 /* Word length 5 bits */
-#define UART_LCR_WLEN6			1
-#define UART_LCR_WLEN7			2
-#define UART_LCR_WLEN8			3
-#define UART_LCR_STOP			BIT(2) /* Stop bits: 1bit, 2bits */
-#define UART_LCR_PARITY			BIT(3) /* Parity enable */
-#define UART_LCR_EPAR			BIT(4) /* Even parity */
-#define UART_LCR_SPAR			BIT(5) /* Stick parity */
-#define UART_LCR_SBC			BIT(6) /* Set break control */
-#define UART_LCR_DLAB			BIT(7) /* Divisor latch access */
-/* (Write) Modem control register */
-#define UART_MCR(n)			UART_REG(n, 4)
-/* (Read) Line status register */
-#define UART_LSR(n)			UART_REG(n, 5)
-#define UART_LSR_DR			BIT(0) /* Data ready */
-#define UART_LSR_OE			BIT(1) /* Overrun error */
-#define UART_LSR_PE			BIT(2) /* Parity error */
-#define UART_LSR_FE			BIT(3) /* Frame error */
-#define UART_LSR_BI			BIT(4) /* Break interrupt */
-#define UART_LSR_THRE			BIT(5) /* Xmit-hold-register empty */
-#define UART_LSR_TEMT			BIT(6) /* Xmit empty */
-#define UART_LSR_FIFOE			BIT(7) /* FIFO error */
-
-/* DLAB == 1 */
-
-/* (Write) Divisor latch */
-#define UART_DLL(n)			UART_REG(n, 0) /* Low */
-#define UART_DLH(n)			UART_REG(n, 1) /* High */
-
-/* MTK extension */
-#define UART_HIGHSPEED(n)		UART_REG(n, 9)
-#define UART_SAMPLE_COUNT(n)		UART_REG(n, 10)
-#define UART_SAMPLE_POINT(n)		UART_REG(n, 11)
-#define UART_RATE_FIX(n)		UART_REG(n, 13)
-
-#endif /* __CROS_EC_SERIAL_REG_H */
diff --git a/chip/mt_scp/mt8183/system.c b/chip/mt_scp/mt8183/system.c
deleted file mode 100644
index 03f39298c9..0000000000
--- a/chip/mt_scp/mt8183/system.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System : hardware specific implementation */
-
-#include "clock_chip.h"
-#include "console.h"
-#include "cpu.h"
-#include "cros_version.h"
-#include "flash.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "memmap.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * SCP_GPR[0] b15-b0  - scratchpad
- * SCP_GPR[0] b31-b16 - saved_flags
- */
-
-int system_set_scratchpad(uint32_t value)
-{
-	/* Check if value fits in 16 bits */
-	if (value & 0xffff0000)
-		return EC_ERROR_INVAL;
-
-	SCP_GPR[0] = (SCP_GPR[0] & 0xffff0000) | value;
-
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = SCP_GPR[0] & 0xffff;
-	return EC_SUCCESS;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "mtk";
-}
-
-const char *system_get_chip_name(void)
-{
-	/* Support only SCP_A for now */
-	return "scp_a";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-void chip_pre_init(void)
-{
-}
-
-static void scp_cm4_mod(void)
-{
-	CM4_MODIFICATION = 3;
-	CM4_DCM_FEATURE = 3;
-}
-
-static void scp_enable_pirq(void)
-{
-	/* Enable all peripheral to SCP IRQ, except IPC0. */
-	SCP_INTC_IRQ_ENABLE = 0xFFFFFFFE;
-	SCP_INTC_IRQ_ENABLE_MSB = 0xFFFFFFFF;
-}
-
-void system_pre_init(void)
-{
-	/* CM4 Modification */
-	scp_cm4_mod();
-	/* Clock */
-	scp_enable_clock();
-	/* Peripheral IRQ */
-	scp_enable_pirq();
-	/* Init dram mapping (and cache) */
-	scp_memmap_init();
-	/* Disable jump (mt_scp has only RW) and enable MPU. */
-	system_disable_jump();
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	/* Remember that the software asked us to hard reboot */
-	if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-
-	/* Reset flags are 32-bits, but save only 16 bits. */
-	ASSERT(!(save_flags >> 16));
-	SCP_GPR[0] = (save_flags << 16) | (SCP_GPR[0] & 0xffff);
-
-	/* SCP can not hard reset itself */
-	ASSERT(!(flags & SYSTEM_RESET_HARD));
-
-	if (flags & SYSTEM_RESET_WAIT_EXT) {
-		int i;
-
-		/* Wait 10 seconds for external reset */
-		for (i = 0; i < 1000; i++) {
-			watchdog_reload();
-			udelay(10000);
-		}
-	}
-
-	/* Set watchdog timer to small value, and spin wait for watchdog reset */
-	SCP_WDT_CFG = 0;
-	SCP_WDT_CFG = SCP_WDT_ENABLE | SCP_WDT_PERIOD(1);
-	watchdog_reload();
-	while (1)
-		;
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t flags = 0;
-	uint32_t raw_reset_cause = SCP_GPR[1];
-
-	/* Set state to power-on */
-	SCP_PWRON_STATE = PWRON_DEFAULT;
-
-	if ((raw_reset_cause & 0xffff0000) == PWRON_DEFAULT) {
-		/* Reboot */
-		if (raw_reset_cause & PWRON_WATCHDOG)
-			flags |= EC_RESET_FLAG_WATCHDOG;
-		else if (raw_reset_cause & PWRON_RESET)
-			flags |= EC_RESET_FLAG_POWER_ON;
-		else
-			flags |= EC_RESET_FLAG_OTHER;
-	} else {
-		/* Power lost restart */
-		flags |= EC_RESET_FLAG_POWER_ON;
-	}
-	system_set_reset_flags(SCP_GPR[0] >> 16);
-	SCP_GPR[0] &= 0xffff;
-}
-
-int system_is_reboot_warm(void)
-{
-	const uint32_t cold_flags =
-		EC_RESET_FLAG_RESET_PIN |
-		EC_RESET_FLAG_POWER_ON  |
-		EC_RESET_FLAG_WATCHDOG  |
-		EC_RESET_FLAG_HARD      |
-		EC_RESET_FLAG_SOFT      |
-		EC_RESET_FLAG_HIBERNATE;
-
-	check_reset_cause();
-
-	return !(system_get_reset_flags() & cold_flags);
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_INVAL;
-}
diff --git a/chip/mt_scp/mt8183/uart.c b/chip/mt_scp/mt8183/uart.c
deleted file mode 100644
index 7907f9537d..0000000000
--- a/chip/mt_scp/mt8183/uart.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module */
-
-#include "clock_chip.h"
-#include "console.h"
-#include "registers.h"
-#include "serial_reg.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console UART index */
-#define UARTN           CONFIG_UART_CONSOLE
-#define UART_IDLE_WAIT_US 500
-
-static uint8_t uart_done, tx_started;
-
-int uart_init_done(void)
-{
-	/*
-	 * TODO: AP UART support
-	 * When access AP UART port, wait for AP peripheral clock
-	 */
-	return uart_done;
-}
-
-void uart_tx_start(void)
-{
-	tx_started = 1;
-
-	/* AP UART mode doesn't support interrupt */
-	if (UARTN >= SCP_UART_COUNT)
-		return;
-
-	if (UART_IER(UARTN) & UART_IER_THRI)
-		return;
-	disable_sleep(SLEEP_MASK_UART);
-	UART_IER(UARTN) |= UART_IER_THRI;
-}
-
-void uart_tx_stop(void)
-{
-	tx_started = 0;
-
-	/* AP UART mode doesn't support interrupt */
-	if (UARTN >= SCP_UART_COUNT)
-		return;
-
-	UART_IER(UARTN) &= ~UART_IER_THRI;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/* Check xmit FIFO empty */
-	return UART_LSR(UARTN) & UART_LSR_THRE;
-}
-
-int uart_rx_available(void)
-{
-	/* Check rcvr data ready */
-	return UART_LSR(UARTN) & UART_LSR_DR;
-}
-
-void uart_write_char(char c)
-{
-	while (!uart_tx_ready())
-		;
-
-	UART_DATA(UARTN) = c;
-}
-
-int uart_read_char(void)
-{
-	return UART_DATA(UARTN);
-}
-
-void uart_process(void)
-{
-	uart_process_input();
-	uart_process_output();
-}
-
-#if (UARTN < SCP_UART_COUNT)
-DECLARE_IRQ(UART_IRQ(UARTN), uart_interrupt, 2);
-void uart_interrupt(void)
-{
-	uint8_t ier;
-
-	task_clear_pending_irq(UART_IRQ(UARTN));
-	uart_process();
-	ier = UART_IER(UARTN);
-	UART_IER(UARTN) = 0;
-	UART_IER(UARTN) = ier;
-}
-
-DECLARE_IRQ(UART_RX_IRQ(UARTN), uart_rx_interrupt, 2);
-void uart_rx_interrupt(void)
-{
-	uint8_t ier;
-
-	task_clear_pending_irq(UART_RX_IRQ(UARTN));
-	SCP_INTC_UART_RX_IRQ &= ~BIT(UARTN);
-	uart_process();
-	ier = UART_IER(UARTN);
-	UART_IER(UARTN) = 0;
-	UART_IER(UARTN) = ier;
-	SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
-}
-#endif
-
-void uart_task(void)
-{
-#if (UARTN >= SCP_UART_COUNT)
-	while (1) {
-		if (uart_rx_available() || tx_started)
-			uart_process();
-		else
-			task_wait_event(UART_IDLE_WAIT_US);
-	}
-#endif
-}
-
-void uart_init(void)
-{
-	const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
-	/*
-	 * UART clock source is set to ULPOSC1 / 10 below.
-	 *
-	 * TODO(b:134035444): We could get slightly more precise frequency by
-	 * using the _measured_ ULPOSC1 frequency (instead of the target).
-	 */
-	const uint32_t uart_clock = ULPOSC1_CLOCK_MHZ * 1000 / 10 * 1000;
-	const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
-
-	/* Init clock */
-#if UARTN == 0
-	SCP_CLK_UART = CLK_UART_SEL_ULPOSC1_DIV10;
-	SCP_CLK_GATE |= CG_UART_M | CG_UART_B | CG_UART_RSTN;
-#elif UARTN == 1
-	SCP_CLK_UART = CLK_UART1_SEL_ULPOSC1_DIV10;
-	SCP_CLK_GATE |= CG_UART1_M | CG_UART1_B | CG_UART1_RSTN;
-#endif
-
-	/* Init and clear FIFO */
-	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO
-		| UART_FCR_CLEAR_RCVR
-		| UART_FCR_CLEAR_XMIT;
-	/* Line control: parity none, 8 bit, 1 stop bit */
-	UART_LCR(UARTN) = UART_LCR_WLEN8;
-	/* For baud rate <= 115200 */
-	UART_HIGHSPEED(UARTN) = 0;
-	/* DLAB = 1 and update DLL DLH */
-	UART_LCR(UARTN) |= UART_LCR_DLAB;
-	UART_DLL(UARTN) = div & 0xff;
-	UART_DLH(UARTN) = (div >> 8) & 0xff;
-	UART_LCR(UARTN) &= ~UART_LCR_DLAB;
-	UART_IER(UARTN) |= UART_IER_RDI;
-
-#if (UARTN < SCP_UART_COUNT)
-	task_enable_irq(UART_IRQ(UARTN));
-	task_enable_irq(UART_RX_IRQ(UARTN));
-	/* UART RX IRQ needs an extra enable */
-	SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
-#endif
-	gpio_config_module(MODULE_UART, 1);
-	uart_done = 1;
-}
diff --git a/chip/mt_scp/mt8183/watchdog.c b/chip/mt_scp/mt8183/watchdog.c
deleted file mode 100644
index 74e2cad8e5..0000000000
--- a/chip/mt_scp/mt8183/watchdog.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "hooks.h"
-#include "panic.h"
-#include "registers.h"
-#include "watchdog.h"
-
-void watchdog_reload(void)
-{
-	SCP_WDT_RELOAD = SCP_WDT_RELOAD_VALUE;
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	const uint32_t watchdog_timeout =
-		SCP_WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS);
-
-	/* Disable watchdog */
-	SCP_WDT_CFG = 0;
-	/* Enable watchdog */
-	SCP_WDT_CFG = SCP_WDT_ENABLE | watchdog_timeout;
-	/* Reload watchdog */
-	watchdog_reload();
-
-	return EC_SUCCESS;
-}
diff --git a/chip/mt_scp/mt8192/build.mk b/chip/mt_scp/mt8192/build.mk
deleted file mode 100644
index c81bd83595..0000000000
--- a/chip/mt_scp/mt8192/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Required chip modules
-chip-y+=$(CHIP_VARIANT)/uart.o
-chip-y+=$(CHIP_VARIANT)/clock.o
-chip-y+=$(CHIP_VARIANT)/video.o
-
diff --git a/chip/mt_scp/mt8192/clock.c b/chip/mt_scp/mt8192/clock.c
deleted file mode 100644
index 43f570fc62..0000000000
--- a/chip/mt_scp/mt8192/clock.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include <assert.h>
-#include <string.h>
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "csr.h"
-#include "ec_commands.h"
-#include "power.h"
-#include "registers.h"
-#include "timer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
-
-enum scp_clock_source {
-	SCP_CLK_26M = CLK_SW_SEL_26M,
-	SCP_CLK_32K = CLK_SW_SEL_32K,
-	SCP_CLK_ULPOSC2 = CLK_SW_SEL_ULPOSC2,
-	SCP_CLK_ULPOSC1 = CLK_SW_SEL_ULPOSC1,
-};
-
-static struct opp_ulposc_cfg {
-	uint32_t osc;
-	uint32_t div;
-	uint32_t fband;
-	uint32_t mod;
-	uint32_t cali;
-	uint32_t target_mhz;
-} opp[] = {
-	{
-		.osc = 1, .target_mhz = 196, .div = 20, .fband = 10, .mod = 3,
-		.cali = 64,
-	},
-	{
-		.osc = 0, .target_mhz = 260, .div = 14, .fband = 2, .mod = 0,
-		.cali = 64,
-	},
-	{
-		.osc = 1, .target_mhz = 280, .div = 20, .fband = 2, .mod = 0,
-		.cali = 64,
-	},
-	{
-		.osc = 1, .target_mhz = 360, .div = 20, .fband = 10, .mod = 0,
-		.cali = 64,
-	},
-};
-
-static inline void clock_busy_udelay(int usec)
-{
-	/*
-	 * Delaying by busy-looping, for place that can't use udelay because of
-	 * the clock not configured yet. The value 28 is chosen approximately
-	 * from experiment.
-	 *
-	 * `volatile' in order to avoid compiler to optimize the function out
-	 * (otherwise, the function will be eliminated).
-	 */
-	volatile int i = usec * 28;
-
-	while (--i)
-		;
-}
-
-static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
-{
-	unsigned int val = 0;
-
-	/* set div */
-	val |= opp->div << OSC_DIV_SHIFT;
-	/* set F-band; I-band = 82 */
-	val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT);
-	/* set calibration */
-	val |= opp->cali;
-	/* set control register 0 */
-	AP_ULPOSC_CON0(opp->osc) = val;
-
-	/* set mod */
-	val = opp->mod << OSC_MOD_SHIFT;
-	/* rsv2 = 0, rsv1 = 41, cali_32k = 0 */
-	val |= 41 << OSC_RSV1_SHIFT;
-	/* set control register 1 */
-	AP_ULPOSC_CON1(opp->osc) = val;
-
-	/* bias = 64 */
-	AP_ULPOSC_CON2(opp->osc) = 64;
-}
-
-static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
-				     uint32_t cali_val)
-{
-	uint32_t val;
-
-	val = AP_ULPOSC_CON0(opp->osc);
-	val &= ~OSC_CALI_MASK;
-	val |= cali_val;
-	AP_ULPOSC_CON0(opp->osc) = val;
-
-	clock_busy_udelay(50);
-}
-
-static uint32_t clock_ulposc_measure_freq(uint32_t osc)
-{
-	uint32_t result = 0;
-	int cnt;
-
-	/* before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
-
-	/* select source, bit[21:16] = clk_src */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
-
-	/* set meter divisor to 1, bit[31:24] = b00000000 */
-	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
-			    MISC_METER_DIV_1;
-
-	/* enable frequency meter, without start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
-
-	/* trigger frequency meter start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
-
-	/*
-	 * Frequency meter counts cycles in 1 / (26 * 1024) second period.
-	 *   freq_in_hz = freq_counter * 26 * 1024
-	 *
-	 * The hardware takes 38us to count cycles. Delay up to 100us,
-	 * as clock_busy_udelay may not be accurate when sysclk is not 26Mhz
-	 * (e.g. when recalibrating/measuring after boot).
-	 */
-	for (cnt = 100; cnt > 0; --cnt) {
-		clock_busy_udelay(1);
-		if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
-			result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
-			break;
-		}
-	}
-
-	/* disable freq meter */
-	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
-
-	return result;
-}
-
-#define CAL_MIS_RATE	40
-static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
-{
-	uint32_t curr, target;
-
-	curr = clock_ulposc_measure_freq(opp->osc);
-	target = opp->target_mhz * 1024 / 26;
-
-	/* check if calibrated value is in the range of target value +- 4% */
-	if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
-	    curr < (target * (1000 + CAL_MIS_RATE) / 1000))
-		return 1;
-	else
-		return 0;
-}
-
-static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
-{
-	uint32_t current_val = 0;
-	uint32_t target_val = opp->target_mhz * 1024 / 26;
-	uint32_t middle, min = 0, max = OSC_CALI_MASK;
-	uint32_t diff_by_min, diff_by_max, cal_result;
-
-	do {
-		middle = (min + max) / 2;
-		if (middle == min)
-			break;
-
-		clock_ulposc_config_cali(opp, middle);
-		current_val = clock_ulposc_measure_freq(opp->osc);
-
-		if (current_val > target_val)
-			max = middle;
-		else
-			min = middle;
-	} while (min <= max);
-
-	clock_ulposc_config_cali(opp, min);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_min = current_val - target_val;
-	else
-		diff_by_min = target_val - current_val;
-
-	clock_ulposc_config_cali(opp, max);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_max = current_val - target_val;
-	else
-		diff_by_max = target_val - current_val;
-
-	if (diff_by_min < diff_by_max)
-		cal_result = min;
-	else
-		cal_result = max;
-
-	clock_ulposc_config_cali(opp, cal_result);
-	if (!clock_ulposc_is_calibrated(opp))
-		assert(0);
-
-	return cal_result;
-}
-
-static void clock_high_enable(int osc)
-{
-	/* enable high speed clock */
-	SCP_CLK_ENABLE |= CLK_HIGH_EN;
-
-	switch (osc) {
-	case 0:
-		/* after 150us, enable ULPOSC */
-		clock_busy_udelay(150);
-		SCP_CLK_ENABLE |= CLK_HIGH_CG;
-		break;
-	case 1:
-		/* turn off ULPOSC2 high-core-disable switch */
-		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
-		/* after 150us, turn on ULPOSC2 high core clock gate */
-		clock_busy_udelay(150);
-		SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_high_disable(int osc)
-{
-	switch (osc) {
-	case 0:
-		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ENABLE &= ~CLK_HIGH_EN;
-		clock_busy_udelay(50);
-		break;
-	case 1:
-		SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
-{
-	/*
-	 * ULPOSC1(osc=0) is already
-	 * - calibrated
-	 * - enabled in coreboot
-	 * - used by pmic wrapper
-	 */
-	if (opp->osc != 0) {
-		clock_high_disable(opp->osc);
-		clock_ulposc_config_default(opp);
-		clock_high_enable(opp->osc);
-	}
-
-	/* Calibrate only if it is not accurate enough. */
-	if (!clock_ulposc_is_calibrated(opp))
-		opp->cali = clock_ulposc_process_cali(opp);
-
-#ifdef DEBUG
-	CPRINTF("osc:%u, target=%uMHz, cal:%u\n",
-		opp->osc, opp->target_mhz, opp->cali);
-#endif
-}
-
-static void clock_select_clock(enum scp_clock_source src)
-{
-	/*
-	 * DIV2 divider takes precedence over clock selection to prevent
-	 * over-clocking.
-	 */
-	if (src == SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV_SEL2;
-
-	SCP_CLK_SW_SEL = src;
-
-	if (src != SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV_SEL1;
-}
-
-__override void
-power_chipset_handle_host_sleep_event(enum host_sleep_event state,
-				      struct host_sleep_event_context *ctx)
-{
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		CPRINTS("AP suspend");
-		clock_select_clock(SCP_CLK_ULPOSC1);
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		CPRINTS("AP resume");
-		clock_select_clock(SCP_CLK_ULPOSC2);
-	}
-}
-
-void clock_init(void)
-{
-	int i;
-
-	/* select default 26M system clock */
-	clock_select_clock(SCP_CLK_26M);
-
-	/* set VREQ to HW mode */
-	SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL;
-	SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
-	SCP_SEC_CTRL &= ~VREQ_SECURE_DIS;
-
-	/* set DDREN to auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* set settle time */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1);
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1);
-	SCP_SLEEP_CTRL =
-		(SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1);
-
-	/* turn off ULPOSC2 */
-	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-
-	/* calibrate ULPOSC */
-	for (i = 0; i < ARRAY_SIZE(opp); ++i)
-		clock_calibrate_ulposc(&opp[i]);
-
-	/* select ULPOSC2 high speed CPU clock */
-	clock_select_clock(SCP_CLK_ULPOSC2);
-
-	/* select BCLK to use ULPOSC1 / 8 = 260MHz / 8 = 32.5MHz */
-	SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8;
-
-	/* enable default clock gate */
-	SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
-		CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
-}
-
-#ifdef DEBUG
-int command_ulposc(int argc, char *argv[])
-{
-	int i;
-
-	for (i = 0; i <= 1; ++i)
-		ccprintf("ULPOSC%u frequency: %u kHz\n",
-			 i + 1,
-			 clock_ulposc_measure_freq(i) * 26 * 1000 / 1024);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]",
-			"Measure ULPOSC frequency");
-#endif
diff --git a/chip/mt_scp/mt8192/clock_regs.h b/chip/mt_scp/mt8192/clock_regs.h
deleted file mode 100644
index 5928ca0473..0000000000
--- a/chip/mt_scp/mt8192/clock_regs.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP clock module registers */
-
-#ifndef __CROS_EC_CLOCK_REGS_H
-#define __CROS_EC_CLOCK_REGS_H
-
-/* clock source select */
-#define SCP_CLK_SW_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0000)
-#define   CLK_SW_SEL_26M		0
-#define   CLK_SW_SEL_32K		1
-#define   CLK_SW_SEL_ULPOSC2		2
-#define   CLK_SW_SEL_ULPOSC1		3
-#define SCP_CLK_ENABLE			REG32(SCP_CLK_CTRL_BASE + 0x0004)
-#define   CLK_HIGH_EN			BIT(1) /* ULPOSC */
-#define   CLK_HIGH_CG			BIT(2)
-/* clock general control */
-#define SCP_CLK_CTRL_GENERAL_CTRL	REG32(SCP_CLK_CTRL_BASE + 0x009C)
-#define   VREQ_PMIC_WRAP_SEL		(0x2)
-
-/* TOPCK clk */
-#define TOPCK_BASE			AP_REG_BASE
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x0140)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
-/* OSC meter */
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x017C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK		0
-#define   DBG_BIST_SOURCE_MASK		(0x3f << 16)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x25 << 16)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x24 << 16)
-#define AP_SCP_CFG_0			REG32(TOPCK_BASE + 0x0220)
-#define   CFG_FREQ_METER_RUN		BIT(4)
-#define   CFG_FREQ_METER_ENABLE		BIT(12)
-#define AP_SCP_CFG_1			REG32(TOPCK_BASE + 0x0224)
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
-/*
- * ULPOSC
- * osc: 0 for ULPOSC1, 1 for ULPOSC2.
- */
-#define AP_ULPOSC_CON0_BASE		(AP_REG_BASE + 0xC2B0)
-#define AP_ULPOSC_CON1_BASE		(AP_REG_BASE + 0xC2B4)
-#define AP_ULPOSC_CON2_BASE		(AP_REG_BASE + 0xC2B8)
-#define AP_ULPOSC_CON0(osc) \
-		REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON1(osc) \
-		REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON2(osc) \
-		REG32(AP_ULPOSC_CON2_BASE + (osc) * 0x10)
-/*
- * AP_ULPOSC_CON0
- * bit0-6: calibration
- * bit7-13: iband
- * bit14-17: fband
- * bit18-23: div
- * bit24: cp_en
- * bit25-31: reserved
- */
-#define OSC_CALI_MASK			0x7f
-#define OSC_IBAND_SHIFT			7
-#define OSC_FBAND_SHIFT			14
-#define OSC_DIV_SHIFT			18
-#define OSC_CP_EN			BIT(24)
-/* AP_ULPOSC_CON1
- * bit0-7: 32K calibration
- * bit 8-15: rsv1
- * bit 16-23: rsv2
- * bit 24-25: mod
- * bit26: div2_en
- * bit27-31: reserved
- */
-#define OSC_RSV1_SHIFT			8
-#define OSC_RSV2_SHIFT			16
-#define OSC_MOD_SHIFT			24
-#define OSC_DIV2_EN			BIT(26)
-/* AP_ULPOSC_CON2
- * bit0-7: bias
- * bit8-31: reserved
- */
-
-#endif /* __CROS_EC_CLOCK_REGS_H */
diff --git a/chip/mt_scp/mt8192/intc.h b/chip/mt_scp/mt8192/intc.h
deleted file mode 100644
index 63eb1243b3..0000000000
--- a/chip/mt_scp/mt8192/intc.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INTC_H
-#define __CROS_EC_INTC_H
-
-/* INTC */
-#define SCP_INTC_IRQ_POL0		0xef001f20
-#define SCP_INTC_IRQ_POL1		0x0800001d
-#define SCP_INTC_IRQ_POL2		0x00000020
-#define SCP_INTC_GRP_LEN		3
-#define SCP_INTC_IRQ_COUNT		96
-
-/* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0		0
-#define SCP_IRQ_GIPC_IN1		1
-#define SCP_IRQ_GIPC_IN2		2
-#define SCP_IRQ_GIPC_IN3		3
-/* 4 */
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_AP_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-/* 8 */
-#define SCP_IRQ_UART0_TX		8
-#define SCP_IRQ_UART1_TX		9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1_0			11
-/* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER		12
-#define SCP_IRQ_CLK_CTRL		13
-#define SCP_IRQ_VOW			14
-#define SCP_IRQ_TIMER0			15
-/* 16 */
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-/* 20 */
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_OS_TIMER		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-/* 24 */
-#define SCP_IRQ_GDMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD_DSP			26
-#define SCP_IRQ_ADSP			27
-/* 28 */
-#define SCP_IRQ_CPU_TICK		28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-/* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
-#define SCP_IRQ_DBG			33
-#define SCP_IRQ_CCIF0			34
-#define SCP_IRQ_CCIF1			35
-/* 36 */
-#define SCP_IRQ_CCIF2			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_USB0			38
-#define SCP_IRQ_USB1			39
-/* 40 */
-#define SCP_IRQ_DPMAIF			40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_CLK_CTRL_CORE		42
-#define SCP_IRQ_CLK_CTRL2_CORE		43
-/* 44 */
-#define SCP_IRQ_CLK_CTRL2		44
-#define SCP_IRQ_GIPC_IN4		45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT		46
-#define SCP_IRQ_INFRABUS_TIMEOUT	47
-/* 48 */
-#define SCP_IRQ_MET0			48
-#define SCP_IRQ_MET1			49
-#define SCP_IRQ_MET2			50
-#define SCP_IRQ_MET3			51
-/* 52 */
-#define SCP_IRQ_AP_WDT			52
-#define SCP_IRQ_L2TCM_SEC_VIO		53
-#define SCP_IRQ_CPU_TICK1		54
-#define SCP_IRQ_MAD_DATAIN		55
-/* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE		56
-#define SCP_IRQ_I3C1_IBI_WAKE		57
-#define SCP_IRQ_I3C2_IBI_WAKE		58
-#define SCP_IRQ_APU_ENGINE		59
-/* 60 */
-#define SCP_IRQ_MBOX0			60
-#define SCP_IRQ_MBOX1			61
-#define SCP_IRQ_MBOX2			62
-#define SCP_IRQ_MBOX3			63
-/* 64 */
-#define SCP_IRQ_MBOX4			64
-#define SCP_IRQ_SYS_CLK_REQ		65
-#define SCP_IRQ_BUS_REQ			66
-#define SCP_IRQ_APSRC_REQ		67
-/* 68 */
-#define SCP_IRQ_APU_MBOX		68
-#define SCP_IRQ_DEVAPC_SECURE_VIO	69
-/* 72 */
-/* 76 */
-#define SCP_IRQ_I2C1_2			78
-#define SCP_IRQ_I2C2			79
-/* 80 */
-#define SCP_IRQ_AUD2AUDIODSP		80
-#define SCP_IRQ_AUD2AUDIODSP_2		81
-#define SCP_IRQ_CONN2ADSP_A2DPOL	82
-#define SCP_IRQ_CONN2ADSP_BTCVSD	83
-/* 84 */
-#define SCP_IRQ_CONN2ADSP_BLEISO	84
-#define SCP_IRQ_PCIE2ADSP		85
-#define SCP_IRQ_APU2ADSP_ENGINE		86
-#define SCP_IRQ_APU2ADSP_MBOX		87
-/* 88 */
-#define SCP_IRQ_CCIF3			88
-#define SCP_IRQ_I2C_DMA0		89
-#define SCP_IRQ_I2C_DMA1		90
-#define SCP_IRQ_I2C_DMA2		91
-/* 92 */
-#define SCP_IRQ_I2C_DMA3		92
-
-#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8192/uart.c b/chip/mt_scp/mt8192/uart.c
deleted file mode 100644
index 0ebb93cbb4..0000000000
--- a/chip/mt_scp/mt8192/uart.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module for MT8192 specific */
-
-#include "uart_regs.h"
-
-/*
- * UARTN == 0, SCP UART0
- * UARTN == 1, SCP UART1
- * UARTN == 2, AP UART1
- */
-#define UARTN CONFIG_UART_CONSOLE
-
-void uart_init_pinmux(void)
-{
-#if UARTN == 0
-	SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
-	SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
-	/* set AP GPIO164 and GPIO165 to alt func 3 */
-	AP_GPIO_MODE20_CLR = 0x00770000;
-	AP_GPIO_MODE20_SET = 0x00330000;
-#elif UARTN == 1
-	SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
-	SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST;
-#endif
-}
diff --git a/chip/mt_scp/mt8192/video.c b/chip/mt_scp/mt8192/video.c
deleted file mode 100644
index 2f9b9a7808..0000000000
--- a/chip/mt_scp/mt8192/video.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "video.h"
-
-uint32_t video_get_enc_capability(void)
-{
-	return VENC_CAP_4K;
-}
-
-uint32_t video_get_dec_capability(void)
-{
-	return VDEC_CAP_4K_DISABLED | VDEC_CAP_MM21 |
-		VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME |
-		VDEC_CAP_VP9_FRAME;
-}
diff --git a/chip/mt_scp/mt8195/build.mk b/chip/mt_scp/mt8195/build.mk
deleted file mode 100644
index c81bd83595..0000000000
--- a/chip/mt_scp/mt8195/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Required chip modules
-chip-y+=$(CHIP_VARIANT)/uart.o
-chip-y+=$(CHIP_VARIANT)/clock.o
-chip-y+=$(CHIP_VARIANT)/video.o
-
diff --git a/chip/mt_scp/mt8195/clock.c b/chip/mt_scp/mt8195/clock.c
deleted file mode 100644
index c6bf3cbc79..0000000000
--- a/chip/mt_scp/mt8195/clock.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include <assert.h>
-#include <string.h>
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "csr.h"
-#include "ec_commands.h"
-#include "power.h"
-#include "registers.h"
-#include "timer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
-
-enum scp_clock_source {
-	SCP_CLK_SYSTEM,
-	SCP_CLK_32K,
-	SCP_CLK_ULPOSC1,
-	SCP_CLK_ULPOSC2_LOW_SPEED,
-	SCP_CLK_ULPOSC2_HIGH_SPEED,
-};
-
-enum {
-	OPP_ULPOSC2_LOW_SPEED,
-	OPP_ULPOSC2_HIGH_SPEED,
-};
-
-static struct opp_ulposc_cfg {
-	uint32_t osc;
-	uint32_t div;
-	uint32_t fband;
-	uint32_t mod;
-	uint32_t cali;
-	uint32_t target_mhz;
-	uint32_t clk_div;
-} opp[] = {
-	[OPP_ULPOSC2_LOW_SPEED] = {
-		.osc = 1, .target_mhz = 326, .clk_div = CLK_DIV_SEL2, .div = 19,
-		.fband = 10, .mod = 0, .cali = 64, /* 326MHz / 2 = 163MHz */
-	},
-	[OPP_ULPOSC2_HIGH_SPEED] = {
-		.osc = 1, .target_mhz = 360, .clk_div = CLK_DIV_SEL1, .div = 21,
-		.fband = 10, .mod = 0, .cali = 64, /* 360MHz / 1 = 360MHz */
-	},
-};
-
-static inline void clock_busy_udelay(int usec)
-{
-	/*
-	 * Delaying by busy-looping, for place that can't use udelay because of
-	 * the clock not configured yet. The value 28 is chosen approximately
-	 * from experiment.
-	 *
-	 * `volatile' in order to avoid compiler to optimize the function out
-	 * (otherwise, the function will be eliminated).
-	 */
-	volatile int i = usec * 28;
-
-	while (--i)
-		;
-}
-
-static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
-{
-	uint32_t val = 0;
-
-	/* set mod, div2_en = 0, cp_en = 0 */
-	val |= opp->mod << OSC_MOD_SHIFT;
-	/* set div */
-	val |= opp->div << OSC_DIV_SHIFT;
-	/* set F-band, I-band = 82 */
-	val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT);
-	/* set calibration */
-	val |= opp->cali;
-	/* set control register 0 */
-	AP_ULPOSC_CON0(opp->osc) = val;
-
-	clock_busy_udelay(50);
-
-	/* bias = 65 */
-	val = 65 << OSC_BIAS_SHIFT;
-	/* rsv2 = 0, rsv1 = 41, cali_32k = 0 */
-	val |= 41 << OSC_RSV1_SHIFT;
-	/* set control register 1 */
-	AP_ULPOSC_CON1(opp->osc) = val;
-
-	/* set settle time */
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(2);
-}
-
-static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
-				     uint32_t cali_val)
-{
-	uint32_t val;
-
-	val = AP_ULPOSC_CON0(opp->osc);
-	val &= ~OSC_CALI_MASK;
-	val |= cali_val;
-	AP_ULPOSC_CON0(opp->osc) = val;
-	opp->cali = cali_val;
-
-	clock_busy_udelay(50);
-}
-
-static uint32_t clock_ulposc_measure_freq(uint32_t osc)
-{
-	uint32_t result = 0;
-	int cnt;
-	uint32_t cali_0 = AP_CLK26CALI_0;
-	uint32_t cali_1 = AP_CLK26CALI_1;
-	uint32_t dbg_cfg = AP_CLK_DBG_CFG;
-	uint32_t misc_cfg = AP_CLK_MISC_CFG_0;
-
-	/* Set ckgen_load_cnt: CLK26CALI_1[25:16] */
-	AP_CLK26CALI_1 = CFG_CKGEN_LOAD_CNT;
-
-	/* before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
-
-	/* select monclk_ext2fqmtr_sel: AP_CLK_DBG_CFG[14:8] */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
-
-	/* set meter divisor to 1, bit[31:24] = b00000000 */
-	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
-			    MISC_METER_DIV_1;
-
-	/* enable frequency meter, without start */
-	AP_CLK26CALI_0 |= CFG_FREQ_METER_ENABLE;
-
-	/* trigger frequency meter start */
-	AP_CLK26CALI_0 |= CFG_FREQ_METER_RUN;
-
-	clock_busy_udelay(45);
-
-	for (cnt = 10000; cnt > 0; --cnt) {
-		clock_busy_udelay(10);
-		if (!(AP_CLK26CALI_0 & CFG_FREQ_METER_RUN)) {
-			result = CFG_FREQ_COUNTER(AP_CLK26CALI_1);
-			break;
-		}
-	}
-
-	AP_CLK26CALI_0 = cali_0;
-	AP_CLK26CALI_1 = cali_1;
-	AP_CLK_DBG_CFG = dbg_cfg;
-	AP_CLK_MISC_CFG_0 = misc_cfg;
-
-	/* disable freq meter */
-	AP_CLK26CALI_0 &= ~CFG_FREQ_METER_ENABLE;
-
-	return result;
-}
-
-#define CAL_MIS_RATE	40
-static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
-{
-	uint32_t curr, target;
-
-	curr = clock_ulposc_measure_freq(opp->osc);
-	target = opp->target_mhz * 512 / 26;
-
-#ifdef DEBUG
-	CPRINTF("osc:%u, target=%uMHz, curr=%uMHz, cali:%u\n",
-		opp->osc, opp->target_mhz, (curr * 26) / 512, opp->cali);
-#endif
-
-	/* check if calibrated value is in the range of target value +- 4% */
-	if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
-	    curr < (target * (1000 + CAL_MIS_RATE) / 1000))
-		return 1;
-	else
-		return 0;
-}
-
-static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
-{
-	uint32_t current_val = 0;
-	uint32_t target_val = opp->target_mhz * 512 / 26;
-	uint32_t middle, min = 0, max = OSC_CALI_MASK;
-	uint32_t diff_by_min, diff_by_max, cal_result;
-
-	do {
-		middle = (min + max) / 2;
-		if (middle == min)
-			break;
-
-		clock_ulposc_config_cali(opp, middle);
-		current_val = clock_ulposc_measure_freq(opp->osc);
-
-		if (current_val > target_val)
-			max = middle;
-		else
-			min = middle;
-	} while (min <= max);
-
-	clock_ulposc_config_cali(opp, min);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_min = current_val - target_val;
-	else
-		diff_by_min = target_val - current_val;
-
-	clock_ulposc_config_cali(opp, max);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_max = current_val - target_val;
-	else
-		diff_by_max = target_val - current_val;
-
-	if (diff_by_min < diff_by_max)
-		cal_result = min;
-	else
-		cal_result = max;
-
-	clock_ulposc_config_cali(opp, cal_result);
-	if (!clock_ulposc_is_calibrated(opp))
-		assert(0);
-
-	return cal_result;
-}
-
-static void clock_high_enable(int osc)
-{
-	/* enable high speed clock */
-	SCP_CLK_ENABLE |= CLK_HIGH_EN;
-
-	switch (osc) {
-	case 0:
-		/* after 150us, enable ULPOSC */
-		clock_busy_udelay(150);
-		SCP_CLK_ENABLE |= CLK_HIGH_CG | CLK_HIGH_EN;
-
-		/* topck ulposc1 clk gating off */
-		AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CK;
-		/* select topck ulposc1 as scp clk parent */
-		AP_CLK_CFG_29_CLR = ULPOSC1_CLK_SEL;
-
-		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE;
-		clock_busy_udelay(50);
-		break;
-	case 1:
-		/* turn off ULPOSC2 high-core-disable switch */
-		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
-		/* after 150us, scp requests ULPOSC2 high core clock */
-		clock_busy_udelay(150);
-		SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG;
-		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
-		clock_busy_udelay(50);
-
-		/* topck ulposc2 clk gating off */
-		AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CORE_CK;
-		/* select topck ulposc2 as scp clk parent */
-		AP_CLK_CFG_29_CLR = ULPOSC2_CLK_SEL;
-
-		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_high_disable(int osc)
-{
-	switch (osc) {
-	case 0:
-		/* topck ulposc1 clk gating on */
-		AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CK;
-		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE;
-		clock_busy_udelay(50);
-
-		/* scp doesn't request ulposc1 clk */
-		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ENABLE &= ~CLK_HIGH_EN;
-		clock_busy_udelay(50);
-		break;
-	case 1:
-		/* topck ulposc2 clk gating on */
-		AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CORE_CK;
-		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE;
-		clock_busy_udelay(50);
-
-		/* scp doesn't request ulposc2 clk */
-		SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
-{
-	/*
-	 * ULPOSC1(osc=0) is already
-	 * - calibrated
-	 * - enabled in coreboot
-	 * - used by pmic wrapper
-	 */
-	if (opp->osc != 0) {
-		clock_high_disable(opp->osc);
-		clock_ulposc_config_default(opp);
-		clock_high_enable(opp->osc);
-	}
-
-	/* Calibrate only if it is not accurate enough. */
-	if (!clock_ulposc_is_calibrated(opp))
-		opp->cali = clock_ulposc_process_cali(opp);
-}
-
-static void clock_select_clock(enum scp_clock_source src)
-{
-	uint32_t sel;
-	uint32_t div;
-
-	switch (src) {
-	case SCP_CLK_SYSTEM:
-		div = CLK_DIV_SEL1;
-		sel = CLK_SW_SEL_SYSTEM;
-		break;
-	case SCP_CLK_32K:
-		div = CLK_DIV_SEL1;
-		sel = CLK_SW_SEL_32K;
-		break;
-	case SCP_CLK_ULPOSC1:
-		div = CLK_DIV_SEL1;
-		sel = CLK_SW_SEL_ULPOSC1;
-		break;
-	case SCP_CLK_ULPOSC2_LOW_SPEED:
-		/* parking at scp system clk until ulposc clk is ready */
-		clock_select_clock(SCP_CLK_SYSTEM);
-
-		clock_ulposc_config_cali(&opp[OPP_ULPOSC2_LOW_SPEED],
-					 opp[OPP_ULPOSC2_LOW_SPEED].cali);
-		div = opp[OPP_ULPOSC2_LOW_SPEED].clk_div;
-
-		sel = CLK_SW_SEL_ULPOSC2;
-		break;
-	case SCP_CLK_ULPOSC2_HIGH_SPEED:
-		/* parking at scp system clk until ulposc clk is ready */
-		clock_select_clock(SCP_CLK_SYSTEM);
-
-		clock_ulposc_config_cali(&opp[OPP_ULPOSC2_HIGH_SPEED],
-					 opp[OPP_ULPOSC2_HIGH_SPEED].cali);
-		div = opp[OPP_ULPOSC2_HIGH_SPEED].clk_div;
-
-		sel = CLK_SW_SEL_ULPOSC2;
-		break;
-	default:
-		div = CLK_DIV_SEL1;
-		sel = CLK_SW_SEL_SYSTEM;
-		break;
-	}
-
-	SCP_CLK_DIV_SEL = div;
-	SCP_CLK_SW_SEL = sel;
-}
-
-__override void
-power_chipset_handle_host_sleep_event(enum host_sleep_event state,
-				      struct host_sleep_event_context *ctx)
-{
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		CPRINTS("AP suspend");
-		clock_select_clock(SCP_CLK_32K);
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		CPRINTS("AP resume");
-		clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED);
-	}
-}
-
-void clock_init(void)
-{
-	uint32_t i;
-
-	/* select scp system clock (default 26MHz) */
-	clock_select_clock(SCP_CLK_SYSTEM);
-
-	/* set VREQ to HW mode */
-	SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL;
-	SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
-	SCP_SEC_CTRL &= ~VREQ_SECURE_DIS;
-
-	/* set DDREN to auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* set settle time */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1);
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1);
-	SCP_SLEEP_CTRL =
-		(SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1);
-
-	/* turn off ULPOSC2 */
-	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-
-	/* calibrate ULPOSC2 */
-	for (i = 0; i < ARRAY_SIZE(opp); ++i)
-		clock_calibrate_ulposc(&opp[i]);
-
-	/* select ULPOSC2 high speed SCP clock */
-	clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED);
-
-	/* select BCLK to use ULPOSC / 8 */
-	SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8;
-
-	/* enable default clock gate */
-	SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
-			  CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
-}
-
-#ifdef DEBUG
-int command_ulposc(int argc, char *argv[])
-{
-	uint32_t osc;
-
-	for (osc = 0; osc <= OPP_ULPOSC2_HIGH_SPEED; ++osc)
-		ccprintf("ULPOSC%u frequency: %u kHz\n", osc + 1,
-			 clock_ulposc_measure_freq(osc) * 26 * 1000 / 512);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]",
-			"Measure ULPOSC frequency");
-#endif
diff --git a/chip/mt_scp/mt8195/clock_regs.h b/chip/mt_scp/mt8195/clock_regs.h
deleted file mode 100644
index 6e7ec6bdbb..0000000000
--- a/chip/mt_scp/mt8195/clock_regs.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP clock module registers */
-
-#ifndef __CROS_EC_CLOCK_REGS_H
-#define __CROS_EC_CLOCK_REGS_H
-
-/* clock source select */
-#define SCP_CLK_SW_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0000)
-#define   CLK_SW_SEL_SYSTEM		0
-#define   CLK_SW_SEL_32K		1
-#define   CLK_SW_SEL_ULPOSC2		2
-#define   CLK_SW_SEL_ULPOSC1		3
-#define SCP_CLK_ENABLE			REG32(SCP_CLK_CTRL_BASE + 0x0004)
-#define   CLK_HIGH_EN			BIT(1) /* ULPOSC */
-#define   CLK_HIGH_CG			BIT(2)
-/* clock general control */
-#define SCP_CLK_CTRL_GENERAL_CTRL	REG32(SCP_CLK_CTRL_BASE + 0x009C)
-#define   VREQ_PMIC_WRAP_SEL		(0x3)
-
-/* TOPCK clk */
-#define TOPCK_BASE			AP_REG_BASE
-#define AP_CLK_CFG_UPDATE3		REG32(TOPCK_BASE + 0x0010)
-#define   F_ULPOSC_CK_UPDATE		BIT(21)
-#define   F_ULPOSC_CORE_CK_UPDATE	BIT(22)
-#define AP_CLK_CFG_29_SET		REG32(TOPCK_BASE + 0x0180)
-#define AP_CLK_CFG_29_CLR		REG32(TOPCK_BASE + 0x0184)
-#define   ULPOSC1_CLK_SEL		(0x3 << 8)
-#define   PDN_F_ULPOSC_CK		BIT(15)
-#define   ULPOSC2_CLK_SEL		(0x3 << 16)
-#define   PDN_F_ULPOSC_CORE_CK		BIT(23)
-/* OSC meter */
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x020C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK		0
-#define   DBG_BIST_SOURCE_MASK		(0x7f << 8)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x30 << 8)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x32 << 8)
-#define AP_CLK26CALI_0			REG32(TOPCK_BASE + 0x0218)
-#define   CFG_FREQ_METER_RUN		BIT(4)
-#define   CFG_FREQ_METER_ENABLE		BIT(7)
-#define AP_CLK26CALI_1			REG32(TOPCK_BASE + 0x021C)
-#define   CFG_CKGEN_LOAD_CNT		0x01ff0000
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x022C)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
-/*
- * ULPOSC
- * osc: 0 for ULPOSC1, 1 for ULPOSC2.
- */
-#define AP_ULPOSC_CON0_BASE		(AP_REG_BASE + 0xC2B0)
-#define AP_ULPOSC_CON1_BASE		(AP_REG_BASE + 0xC2B4)
-#define AP_ULPOSC_CON0(osc) \
-		REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON1(osc) \
-		REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10)
-/*
- * AP_ULPOSC_CON0
- * bit0-6: calibration
- * bit7-13: iband
- * bit14-17: fband
- * bit18-23: div
- * bit24: cp_en
- * bit25-26: mod
- * bit27: div2_en
- * bit28-31: reserved
- */
-#define OSC_CALI_SHIFT			0
-#define OSC_CALI_MASK			0x7f
-#define OSC_IBAND_SHIFT			7
-#define OSC_FBAND_SHIFT			14
-#define OSC_DIV_SHIFT			18
-#define OSC_CP_EN			BIT(24)
-#define OSC_MOD_SHIFT			25
-#define OSC_DIV2_EN			BIT(27)
-/*
- * AP_ULPOSC_CON1
- * bit0-7: rsv1
- * bit8-15: rsv2
- * bit16-23: 32K calibration
- * bit24-31: bias
- */
-#define OSC_RSV1_SHIFT			0
-#define OSC_RSV2_SHIFT			8
-#define OSC_32KCALI_SHIFT		16
-#define OSC_BIAS_SHIFT			24
-
-#endif /* __CROS_EC_CLOCK_REGS_H */
diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h
deleted file mode 100644
index 87181c46ca..0000000000
--- a/chip/mt_scp/mt8195/intc.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INTC_H
-#define __CROS_EC_INTC_H
-
-/* INTC */
-#define SCP_INTC_IRQ_POL0		0xef001f20
-#define SCP_INTC_IRQ_POL1		0x044001dd
-#define SCP_INTC_IRQ_POL2		0xffffdfe0
-#define SCP_INTC_IRQ_POL3		0xfffffff3
-#define SCP_INTC_GRP_LEN		4
-#define SCP_INTC_IRQ_COUNT		127
-
-/* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0		0
-#define SCP_IRQ_GIPC_IN1		1
-#define SCP_IRQ_GIPC_IN2		2
-#define SCP_IRQ_GIPC_IN3		3
-/* 4 */
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_AP_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-/* 8 */
-#define SCP_IRQ_UART0_TX		8
-#define SCP_IRQ_UART1_TX		9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1_0			11
-/* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER		12
-#define SCP_IRQ_CLK_CTRL		13
-#define SCP_IRQ_VOW			14
-#define SCP_IRQ_TIMER0			15
-/* 16 */
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-/* 20 */
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_OS_TIMER		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-/* 24 */
-#define SCP_IRQ_GDMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD_DSP			26
-#define SCP_IRQ_ADSP			27
-/* 28 */
-#define SCP_IRQ_CPU_TICK		28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-/* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
-#define SCP_IRQ_DBG			33
-#define SCP_IRQ_GCE			34
-#define SCP_IRQ_MDP_GCE			35
-/* 36 */
-#define SCP_IRQ_VDEC			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_VDEC_LAT		38
-#define SCP_IRQ_VDEC1			39
-/* 40 */
-#define SCP_IRQ_VDEC1_LAT		40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_CLK_CTRL_CORE		42
-#define SCP_IRQ_CLK_CTRL2_CORE		43
-/* 44 */
-#define SCP_IRQ_CLK_CTRL2		44
-#define SCP_IRQ_GIPC_IN4		45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT		46
-#define SCP_IRQ_INFRABUS_TIMEOUT	47
-/* 48 */
-#define SCP_IRQ_MET0			48
-#define SCP_IRQ_MET1			49
-#define SCP_IRQ_MET2			50
-#define SCP_IRQ_MET3			51
-/* 52 */
-#define SCP_IRQ_AP_WDT			52
-#define SCP_IRQ_L2TCM_SEC_VIO		53
-#define SCP_IRQ_VDEC_INT_LINE_CNT	54
-#define SCP_IRQ_VOW_DATAIN		55
-/* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE		56
-#define SCP_IRQ_I3C1_IBI_WAKE		57
-#define SCP_IRQ_VENC			58
-#define SCP_IRQ_APU_ENGINE		59
-/* 60 */
-#define SCP_IRQ_MBOX0			60
-#define SCP_IRQ_MBOX1			61
-#define SCP_IRQ_MBOX2			62
-#define SCP_IRQ_MBOX3			63
-/* 64 */
-#define SCP_IRQ_MBOX4			64
-#define SCP_IRQ_SYS_CLK_REQ		65
-#define SCP_IRQ_BUS_REQ			66
-#define SCP_IRQ_APSRC_REQ		67
-/* 68 */
-#define SCP_IRQ_APU_MBOX		68
-#define SCP_IRQ_DEVAPC_SECURE_VIO	69
-#define SCP_IRQ_CAMSYS_29		70
-#define SCP_IRQ_CAMSYS_28		71
-/* 72 */
-#define SCP_IRQ_CAMSYS_5		72
-#define SCP_IRQ_CAMSYS_4		73
-#define SCP_IRQ_CAMSYS_3		74
-#define SCP_IRQ_CAMSYS_2		75
-/* 76 */
-#define SCP_IRQ_HDMIRX_PM_DVI_SQH	76
-#define SCP_IRQ_HDMIRX_RESERVED		77
-#define SCP_IRQ_NNA0_0			78
-#define SCP_IRQ_NNA0_1			79
-/* 80 */
-#define SCP_IRQ_NNA0_2			80
-#define SCP_IRQ_NNA1_0			81
-#define SCP_IRQ_NNA1_1			82
-#define SCP_IRQ_NNA1_2			83
-/* 84 */
-#define SCP_IRQ_JPEGENC			84
-#define SCP_IRQ_JPEGDEC			85
-#define SCP_IRQ_JPEGDEC_C2		86
-#define SCP_IRQ_VENC_C1			87
-/* 88 */
-#define SCP_IRQ_JPEGENC_C1		88
-#define SCP_IRQ_JPEGDEC_C1		89
-#define SCP_IRQ_HDMITX			90
-#define SCP_IRQ_HDMI2			91
-/* 92 */
-#define SCP_IRQ_EARC			92
-#define SCP_IRQ_CEC			93
-#define SCP_IRQ_HDMI_DEV_DET		94
-#define SCP_IRQ_HDMIRX_OUT_ARM_PHY	95
-/* 96 */
-#define SCP_IRQ_I2C2			96
-#define SCP_IRQ_I2C3			97
-#define SCP_IRQ_I3C2_IBI_WAKE		98
-#define SCP_IRQ_I3C3_IBI_WAKE		99
-/* 100 */
-#define SCP_IRQ_SYS_I2C_0		100
-#define SCP_IRQ_SYS_I2C_1		101
-#define SCP_IRQ_SYS_I2C_2		102
-#define SCP_IRQ_SYS_I2C_3		103
-/* 104 */
-#define SCP_IRQ_SYS_I2C_4		104
-#define SCP_IRQ_SYS_I2C_5		105
-#define SCP_IRQ_SYS_I2C_6		106
-#define SCP_IRQ_SYS_I2C_7		107
-/* 108 */
-#define SCP_IRQ_DISP2ADSP_0		108
-#define SCP_IRQ_DISP2ADSP_1		109
-#define SCP_IRQ_DISP2ADSP_2		110
-#define SCP_IRQ_DISP2ADSP_3		111
-/* 112 */
-#define SCP_IRQ_DISP2ADSP_4		112
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_0	113
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_1	114
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_2	115
-/* 116 */
-#define SCP_IRQ_GCE1_SECURE		116
-#define SCP_IRQ_GCE_SECURE		117
-
-#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8195/uart.c b/chip/mt_scp/mt8195/uart.c
deleted file mode 100644
index 76674fa7d3..0000000000
--- a/chip/mt_scp/mt8195/uart.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module for MT8195 specific */
-
-#include "uart_regs.h"
-
-/*
- * UARTN == 0, SCP UART0
- * UARTN == 1, SCP UART1
- * UARTN == 2, AP UART1
- */
-#define UARTN CONFIG_UART_CONSOLE
-
-void uart_init_pinmux(void)
-{
-#if UARTN == 0
-	SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
-	SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
-	/* set AP GPIO102 and GPIO103 to alt func 5 */
-	AP_GPIO_MODE12_CLR = 0x77000000;
-	AP_GPIO_MODE12_SET = 0x55000000;
-#endif
-}
diff --git a/chip/mt_scp/mt8195/video.c b/chip/mt_scp/mt8195/video.c
deleted file mode 100644
index dc4b7b3397..0000000000
--- a/chip/mt_scp/mt8195/video.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "video.h"
-
-uint32_t video_get_enc_capability(void)
-{
-	return VENC_CAP_4K;
-}
-
-uint32_t video_get_dec_capability(void)
-{
-	return VDEC_CAP_MT21C | VDEC_CAP_MM21 |
-		VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME |
-		VDEC_CAP_VP9_FRAME;
-}
diff --git a/chip/mt_scp/rv32i_common/build.mk b/chip/mt_scp/rv32i_common/build.mk
deleted file mode 100644
index ac7e13db77..0000000000
--- a/chip/mt_scp/rv32i_common/build.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# SCP specific files build
-#
-
-CORE:=riscv-rv32i
-
-# Required chip modules
-chip-y+=rv32i_common/cache.o
-chip-y+=rv32i_common/gpio.o
-chip-y+=rv32i_common/intc.o
-chip-y+=rv32i_common/memmap.o
-chip-y+=rv32i_common/system.o
-chip-y+=rv32i_common/uart.o
-
-ifeq ($(CONFIG_IPI),y)
-$(out)/RW/chip/$(CHIP)/rv32i_common/ipi_table.o: $(out)/ipi_table_gen.inc
-endif
-
-# Optional chip modules
-chip-$(CONFIG_COMMON_TIMER)+=rv32i_common/hrtimer.o
-chip-$(CONFIG_IPI)+=rv32i_common/ipi.o rv32i_common/ipi_table.o
-chip-$(CONFIG_WATCHDOG)+=rv32i_common/watchdog.o
-chip-$(HAS_TASK_HOSTCMD)+=rv32i_common/hostcmd.o
diff --git a/chip/mt_scp/rv32i_common/cache.c b/chip/mt_scp/rv32i_common/cache.c
deleted file mode 100644
index 62147590fe..0000000000
--- a/chip/mt_scp/rv32i_common/cache.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cache.h"
-#include "console.h"
-#include "csr.h"
-
-extern struct mpu_entry mpu_entries[];
-
-void cache_init(void)
-{
-	int i;
-	uint32_t mpu_en = 0;
-
-	/* disable mpu */
-	clear_csr(CSR_MCTREN, CSR_MCTREN_MPU);
-
-	/* enable i$, d$ */
-	set_csr(CSR_MCTREN, CSR_MCTREN_ICACHE);
-	set_csr(CSR_MCTREN, CSR_MCTREN_DCACHE);
-
-	/* invalidate icache and dcache */
-	cache_invalidate_icache();
-	cache_invalidate_dcache();
-
-	/* set mpu entries
-	 *
-	 * The pragma is for force GCC unrolls the following loop.
-	 * See b/172886808
-	 */
-#pragma GCC unroll 16
-	for (i = 0; i < NR_MPU_ENTRIES; ++i) {
-		if (mpu_entries[i].end_addr - mpu_entries[i].start_addr) {
-			write_csr(CSR_MPU_L(i), mpu_entries[i].start_addr |
-						mpu_entries[i].attribute);
-			write_csr(CSR_MPU_H(i), mpu_entries[i].end_addr);
-			mpu_en |= BIT(i);
-		}
-	}
-
-	/* enable mpu entries */
-	write_csr(CSR_MPU_ENTRY_EN, mpu_en);
-
-	/* enable mpu */
-	set_csr(CSR_MCTREN, CSR_MCTREN_MPU);
-
-	/* fence */
-	asm volatile ("fence.i" ::: "memory");
-}
-
-#ifdef DEBUG
-/*
- * I for I-cache
- * D for D-cache
- * C for control transfer instructions (branch, jump, ret, interrupt, ...)
- */
-static enum {
-	PMU_SELECT_I = 0,
-	PMU_SELECT_D,
-	PMU_SELECT_C
-} pmu_select;
-
-int command_enable_pmu(int argc, char **argv)
-{
-	static const char * const selectors[] = {
-		[PMU_SELECT_I] = "I",
-		[PMU_SELECT_D] = "D",
-		[PMU_SELECT_C] = "C",
-	};
-	int i;
-
-	if (argc != 2)
-		return EC_ERROR_PARAM1;
-
-	for (i = 0; i < ARRAY_SIZE(selectors); ++i) {
-		if (strcasecmp(argv[1], selectors[i]) == 0) {
-			pmu_select = i;
-			break;
-		}
-	}
-	if (i >= ARRAY_SIZE(selectors))
-		return EC_ERROR_PARAM1;
-
-	ccprintf("select \"%s\"\n", selectors[pmu_select]);
-
-	/* disable all PMU */
-	clear_csr(CSR_PMU_MPMUCTR,
-		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I |
-		  CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 |
-		  CSR_PMU_MPMUCTR_H5);
-
-	/* reset cycle count */
-	write_csr(CSR_PMU_MCYCLE, 0);
-	write_csr(CSR_PMU_MCYCLEH, 0);
-	/* reset retired-instruction count */
-	write_csr(CSR_PMU_MINSTRET, 0);
-	write_csr(CSR_PMU_MINSTRETH, 0);
-	/* reset counter{3,4,5} */
-	write_csr(CSR_PMU_MHPMCOUNTER3, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER3H, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER4, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER4H, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER5, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER5H, 0);
-
-	/* select different event IDs for counter{3,4,5} */
-	switch (pmu_select) {
-	case PMU_SELECT_I:
-		/* I-cache access count */
-		write_csr(CSR_PMU_MHPMEVENT3, 1);
-		/* I-cache miss count */
-		write_csr(CSR_PMU_MHPMEVENT4, 3);
-		/* noncacheable I-AXI access count */
-		write_csr(CSR_PMU_MHPMEVENT5, 5);
-		break;
-	case PMU_SELECT_D:
-		/* D-cache access count */
-		write_csr(CSR_PMU_MHPMEVENT3, 11);
-		/* D-cache miss count */
-		write_csr(CSR_PMU_MHPMEVENT4, 12);
-		/* noncacheable D-AXI access count */
-		write_csr(CSR_PMU_MHPMEVENT5, 14);
-		break;
-	case PMU_SELECT_C:
-		/* control transfer instruction count */
-		write_csr(CSR_PMU_MHPMEVENT3, 27);
-		/* control transfer miss-predict count */
-		write_csr(CSR_PMU_MHPMEVENT4, 28);
-		/* interrupt count */
-		write_csr(CSR_PMU_MHPMEVENT5, 29);
-		break;
-	}
-
-	cache_invalidate_icache();
-	cache_flush_dcache();
-
-	/* enable all PMU */
-	set_csr(CSR_PMU_MPMUCTR,
-		CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I |
-		CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 |
-		CSR_PMU_MPMUCTR_H5);
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu,
-			     "[I | D | C]", "Enable PMU");
-
-int command_disable_pmu(int argc, char **argv)
-{
-	clear_csr(CSR_PMU_MPMUCTR,
-		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I |
-		  CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 |
-		  CSR_PMU_MPMUCTR_H5);
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu,
-			     NULL, "Disable PMU");
-
-int command_show_pmu(int argc, char **argv)
-{
-	uint64_t val3, val4, val5;
-	uint32_t p;
-
-	val3 = ((uint64_t)read_csr(CSR_PMU_MCYCLEH) << 32) |
-			read_csr(CSR_PMU_MCYCLE);
-	ccprintf("cycles: %lld\n", val3);
-
-	val3 = ((uint64_t)read_csr(CSR_PMU_MINSTRETH) << 32) |
-			read_csr(CSR_PMU_MINSTRET);
-	ccprintf("retired instructions: %lld\n", val3);
-
-	val3 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER3H) << 32) |
-			read_csr(CSR_PMU_MHPMCOUNTER3);
-	val4 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER4H) << 32) |
-			read_csr(CSR_PMU_MHPMCOUNTER4);
-	val5 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER5H) << 32) |
-			read_csr(CSR_PMU_MHPMCOUNTER5);
-
-	if (val3)
-		p = val4 * 10000 / val3;
-	else
-		p = 0;
-
-	switch (pmu_select) {
-	case PMU_SELECT_I:
-		ccprintf("I-cache:\n");
-		ccprintf("  access: %lld\n", val3);
-		ccprintf("  miss: %lld (%d.%d%%)\n", val4, p / 100, p % 100);
-		ccprintf("non-cacheable I: %lld\n", val5);
-		break;
-	case PMU_SELECT_D:
-		ccprintf("D-cache:\n");
-		ccprintf("  access: %lld\n", val3);
-		ccprintf("  miss: %lld (%d.%d%%)\n", val4, p / 100, p % 100);
-		ccprintf("non-cacheable D: %lld\n", val5);
-		break;
-	case PMU_SELECT_C:
-		ccprintf("control transfer instruction:\n");
-		ccprintf("  total: %lld\n", val3);
-		ccprintf("  miss-predict: %lld (%d.%d%%)\n",
-			 val4, p / 100, p % 100);
-		ccprintf("interrupts: %lld\n", val5);
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(show_pmu, command_show_pmu, NULL, "Show PMU");
-#endif
diff --git a/chip/mt_scp/rv32i_common/cache.h b/chip/mt_scp/rv32i_common/cache.h
deleted file mode 100644
index 13e5ad1a42..0000000000
--- a/chip/mt_scp/rv32i_common/cache.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CACHE_H
-#define __CROS_EC_CACHE_H
-
-#include "common.h"
-#include "csr.h"
-#include "stdint.h"
-#include "util.h"
-
-/* rs1 0~31 register X0~X31 */
-#define COP(rs1) (((rs1) << 15) | 0x400f)
-
-#define COP_OP_BARRIER_ICACHE		0x0
-#define COP_OP_INVALIDATE_ICACHE	0x8
-#define COP_OP_INVALIDATE_ICACHE_ADDR	0x9
-
-#define COP_OP_BARRIER_DCACHE		0x10
-#define COP_OP_WRITEBACK_DCACHE		0x14
-#define COP_OP_WRITEBACK_DCACHE_ADDR	0x15
-#define COP_OP_INVALIDATE_DCACHE	0x18
-#define COP_OP_INVALIDATE_DCACHE_ADDR	0x19
-/* FLUSH = WRITEBACK + INVALIDATE */
-#define COP_OP_FLUSH_DCACHE		0x1C
-#define COP_OP_FLUSH_DCACHE_ADDR	0x1D
-
-static inline void cache_op_all(uint32_t op)
-{
-	register int t0 asm("t0") = op;
-	asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
-}
-
-static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op)
-{
-	size_t offset;
-	register int t0 asm("t0");
-
-	/* NOTE: cache operations must use 32 byte aligned address */
-	if (addr & GENMASK(3, 0))
-		return EC_ERROR_INVAL;
-
-	for (offset = 0; offset < length; offset += 4) {
-		t0 = addr + offset + op;
-		asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
-	}
-
-	return EC_SUCCESS;
-}
-
-/* memory barrier of I$ */
-static inline void cache_barrier_icache(void)
-{
-	cache_op_all(COP_OP_BARRIER_ICACHE);
-}
-
-/* invalidate all I$ */
-static inline void cache_invalidate_icache(void)
-{
-	cache_op_all(COP_OP_INVALIDATE_ICACHE);
-}
-
-/* invalidate a range of I$ */
-static inline int cache_invalidate_icache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_INVALIDATE_ICACHE_ADDR);
-}
-
-/* memory barrier of D$ */
-static inline void cache_barrier_dcache(void)
-{
-	cache_op_all(COP_OP_BARRIER_DCACHE);
-}
-
-/* writeback all D$ */
-static inline void cache_writeback_dcache(void)
-{
-	cache_op_all(COP_OP_WRITEBACK_DCACHE);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-}
-
-/* writeback a range of D$ */
-static inline int cache_writeback_dcache_range(uintptr_t addr, uint32_t length)
-{
-	int ret = cache_op_addr(addr, length, COP_OP_WRITEBACK_DCACHE_ADDR);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-	return ret;
-}
-
-/* invalidate all D$ */
-static inline void cache_invalidate_dcache(void)
-{
-	cache_op_all(COP_OP_INVALIDATE_DCACHE);
-}
-
-/* invalidate a range of D$ */
-static inline int cache_invalidate_dcache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_INVALIDATE_DCACHE_ADDR);
-}
-
-/* writeback and invalidate all D$ */
-static inline void cache_flush_dcache(void)
-{
-	cache_op_all(COP_OP_FLUSH_DCACHE);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-}
-
-/* writeback and invalidate a range of D$ */
-static inline int cache_flush_dcache_range(uintptr_t addr, uint32_t length)
-{
-	int ret = cache_op_addr(addr, length, COP_OP_FLUSH_DCACHE_ADDR);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-	return ret;
-}
-
-struct mpu_entry {
-	/* 1k alignment and the address is inclusive */
-	uintptr_t start_addr;
-	/* 1k alignment in 4GB boundary and non-inclusive */
-	uintptr_t end_addr;
-	/* MPU_ATTR */
-	uint32_t attribute;
-};
-
-void cache_init(void);
-
-#ifdef DEBUG
-int command_enable_pmu(int argc, char **argv);
-int command_disable_pmu(int argc, char **argv);
-int command_show_pmu(int argc, char **argv);
-#endif
-
-#endif /* #ifndef __CROS_EC_CACHE_H */
diff --git a/chip/mt_scp/rv32i_common/config_chip.h b/chip/mt_scp/rv32i_common/config_chip.h
deleted file mode 100644
index ac53d51732..0000000000
--- a/chip/mt_scp/rv32i_common/config_chip.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/riscv-rv32i/config_core.h"
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* RW only, no flash */
-#undef  CONFIG_FW_INCLUDE_RO
-#define CONFIG_RO_MEM_OFF 0
-#define CONFIG_RO_SIZE 0
-#define CONFIG_RW_MEM_OFF 0
-#define CONFIG_RW_SIZE 0x40000 /* 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
-#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
-#define CONFIG_RO_STORAGE_OFF 0
-#define CONFIG_RW_STORAGE_OFF 0
-#define CONFIG_PROGRAM_MEMORY_BASE 0
-#define CONFIG_PROGRAM_MEMORY_BASE_LOAD 0x10500000
-#define CONFIG_MAPPED_STORAGE_BASE 0
-
-/* Unsupported features/commands */
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_FLASH_CROS
-#undef CONFIG_FLASH_PHYSICAL
-#undef CONFIG_FMAP
-#undef CONFIG_HIBERNATE
-#undef CONFIG_LID_SWITCH
-
-/* Task stack size */
-#define CONFIG_STACK_SIZE 1024
-#define IDLE_TASK_STACK_SIZE 640
-#define SMALLER_TASK_STACK_SIZE 384
-#define TASK_STACK_SIZE 488
-#define LARGER_TASK_STACK_SIZE 640
-#define VENTI_TASK_STACK_SIZE 768
-#define ULTRA_TASK_STACK_SIZE 1056
-#define TRENTA_TASK_STACK_SIZE 1184
-
-/* TODO: need to confirm, placeholder */
-#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-#undef CONFIG_TASK_PROFILING
-/* TODO: not yet supported */
-#undef CONFIG_MPU
-/* TODO: core/riscv-rv32i pollution */
-#define __ram_code
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mt_scp/rv32i_common/csr.h b/chip/mt_scp/rv32i_common/csr.h
deleted file mode 100644
index 7c767d0592..0000000000
--- a/chip/mt_scp/rv32i_common/csr.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Control and status register */
-
-/* TODO: move to core/riscv-rv32i? */
-
-#ifndef __CROS_EC_CSR_H
-#define __CROS_EC_CSR_H
-
-#include "common.h"
-
-static inline uint32_t read_csr(uint32_t reg)
-{
-	uint32_t val;
-
-	asm volatile("csrr %0, %1" : "=r"(val) : "i"(reg));
-	return val;
-}
-
-static inline void write_csr(uint32_t reg, uint32_t val)
-{
-	asm volatile ("csrw %0, %1" :: "i"(reg), "r"(val));
-}
-
-static inline uint32_t set_csr(uint32_t reg, uint32_t bit)
-{
-	uint32_t val;
-
-	asm volatile ("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
-	return val;
-}
-
-static inline uint32_t clear_csr(uint32_t reg, uint32_t bit)
-{
-	uint32_t val;
-
-	asm volatile ("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
-	return val;
-}
-
-/* VIC */
-#define CSR_VIC_MICAUSE		(0x5c0)
-#define CSR_VIC_MIEMS		(0x5c2)
-#define CSR_VIC_MIPEND_G0	(0x5d0)
-#define CSR_VIC_MIMASK_G0	(0x5d8)
-#define CSR_VIC_MIWAKEUP_G0	(0x5e0)
-#define CSR_VIC_MILSEL_G0	(0x5e8)
-#define CSR_VIC_MIEMASK_G0	(0x5f0)
-
-/* centralized control enable */
-#define CSR_MCTREN		(0x7c0)
-/* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */
-#define   CSR_MCTREN_ICACHE	BIT(0)
-#define   CSR_MCTREN_DCACHE	BIT(1)
-#define   CSR_MCTREN_ITCM	BIT(2)
-#define   CSR_MCTREN_DTCM	BIT(3)
-#define   CSR_MCTREN_BTB	BIT(4)
-#define   CSR_MCTREN_RAS	BIT(5)
-#define   CSR_MCTREN_VIC	BIT(6)
-#define   CSR_MCTREN_CG		BIT(7)
-#define   CSR_MCTREN_MPU	BIT(8)
-
-/* MPU */
-#define CSR_MPU_ENTRY_EN	(0x9c0)
-#define CSR_MPU_LITCM		(0x9dc)
-#define CSR_MPU_LDTCM		(0x9dd)
-#define CSR_MPU_HITCM		(0x9de)
-#define CSR_MPU_HDTCM		(0x9df)
-#define CSR_MPU_L(n)		(0x9e0 + (n))
-#define CSR_MPU_H(n)		(0x9f0 + (n))
-/* MPU attributes: set if permitted */
-/* Privilege, machine mode in RISC-V.  We don't use the flag because
- * we don't separate user / machine mode in EC OS. */
-#define   MPU_ATTR_P		BIT(5)
-/* Readable */
-#define   MPU_ATTR_R		BIT(6)
-/* Writable */
-#define   MPU_ATTR_W		BIT(7)
-/* Cacheable */
-#define   MPU_ATTR_C		BIT(8)
-/* Bufferable */
-#define   MPU_ATTR_B		BIT(9)
-
-/* PMU */
-#define CSR_PMU_MPMUCTR		(0xbc0)
-#define   CSR_PMU_MPMUCTR_C	BIT(0)
-#define   CSR_PMU_MPMUCTR_I	BIT(1)
-#define   CSR_PMU_MPMUCTR_H3	BIT(2)
-#define   CSR_PMU_MPMUCTR_H4	BIT(3)
-#define   CSR_PMU_MPMUCTR_H5	BIT(4)
-
-#define CSR_PMU_MCYCLE		(0xb00)
-#define CSR_PMU_MINSTRET	(0xb02)
-#define CSR_PMU_MHPMCOUNTER3	(0xb03)
-#define CSR_PMU_MHPMCOUNTER4	(0xb04)
-#define CSR_PMU_MHPMCOUNTER5	(0xb05)
-
-#define CSR_PMU_MCYCLEH		(0xb80)
-#define CSR_PMU_MINSTRETH	(0xb82)
-#define CSR_PMU_MHPMCOUNTER3H	(0xb83)
-#define CSR_PMU_MHPMCOUNTER4H	(0xb84)
-#define CSR_PMU_MHPMCOUNTER5H	(0xb85)
-
-#define CSR_PMU_MHPMEVENT3	(0x323)
-#define CSR_PMU_MHPMEVENT4	(0x324)
-#define CSR_PMU_MHPMEVENT5	(0x325)
-
-#endif /* __CROS_EC_CSR_H */
diff --git a/chip/mt_scp/rv32i_common/gpio.c b/chip/mt_scp/rv32i_common/gpio.c
deleted file mode 100644
index 0ca3e3ac25..0000000000
--- a/chip/mt_scp/rv32i_common/gpio.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module */
-
-#include "gpio.h"
-
-void gpio_pre_init(void)
-{
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-}
diff --git a/chip/mt_scp/rv32i_common/hostcmd.c b/chip/mt_scp/rv32i_common/hostcmd.c
deleted file mode 100644
index 42a463ee56..0000000000
--- a/chip/mt_scp/rv32i_common/hostcmd.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "host_command.h"
-#include "ipi_chip.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-#define HOSTCMD_MAX_REQUEST_SIZE CONFIG_IPC_SHARED_OBJ_BUF_SIZE
-/* Reserve 1 extra byte for HOSTCMD_TYPE and 3 bytes for padding. */
-#define HOSTCMD_MAX_RESPONSE_SIZE (CONFIG_IPC_SHARED_OBJ_BUF_SIZE - 4)
-#define HOSTCMD_TYPE_HOSTCMD 1
-#define HOSTCMD_TYPE_HOSTEVENT 2
-
-/*
- * hostcmd and hostevent share the same IPI ID, and use first byte type to
- * indicate its type.
- */
-static struct hostcmd_data {
-	const uint8_t type;
-	/* To be compatible with CONFIG_HOSTCMD_ALIGNED */
-	uint8_t response[HOSTCMD_MAX_RESPONSE_SIZE] __aligned(4);
-} hc_cmd_obj = { .type = HOSTCMD_TYPE_HOSTCMD };
-BUILD_ASSERT(sizeof(struct hostcmd_data) == CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Size of the rpmsg device name, should sync across kernel and EC. */
-#define RPMSG_NAME_SIZE 32
-
-/*
- * The layout of name service message.
- * This should sync across kernel and EC.
- */
-struct rpmsg_ns_msg {
-	/* Name of the corresponding rpmsg_driver. */
-	char name[RPMSG_NAME_SIZE];
-	/* IPC ID */
-	uint32_t addr;
-};
-
-static void hostcmd_send_response_packet(struct host_packet *pkt)
-{
-	int ret;
-
-	ret = ipi_send(SCP_IPI_HOST_COMMAND, &hc_cmd_obj,
-		       pkt->response_size +
-			       offsetof(struct hostcmd_data, response),
-		       1);
-	if (ret)
-		CPRINTS("failed to %s(), ret=%d", __func__, ret);
-}
-
-static void hostcmd_handler(int32_t id, void *buf, uint32_t len)
-{
-	static struct host_packet packet;
-	uint8_t *in_msg = buf;
-	struct ec_host_request *r = (struct ec_host_request *)in_msg;
-	int i;
-
-	if (in_msg[0] != EC_HOST_REQUEST_VERSION) {
-		CPRINTS("ERROR: Protocol V2 is not supported!");
-		CPRINTF("in_msg=[");
-		for (i = 0; i < len; i++)
-			CPRINTF("%02x ", in_msg[i]);
-		CPRINTF("]\n");
-		return;
-	}
-
-	/* Protocol version 3 */
-
-	packet.send_response = hostcmd_send_response_packet;
-
-	/*
-	 * Just assign the buffer to request, host_packet_receive
-	 * handles the buffer copy.
-	 */
-	packet.request = (void *)r;
-	packet.request_temp = NULL;
-	packet.request_max = HOSTCMD_MAX_REQUEST_SIZE;
-	packet.request_size = host_request_expected_size(r);
-
-	packet.response = hc_cmd_obj.response;
-	/* Reserve space for the preamble and trailing byte */
-	packet.response_max = HOSTCMD_MAX_RESPONSE_SIZE;
-	packet.response_size = 0;
-
-	packet.driver_result = EC_RES_SUCCESS;
-
-	host_packet_receive(&packet);
-}
-DECLARE_IPI(SCP_IPI_HOST_COMMAND, hostcmd_handler, 0);
-
-/*
- * Get protocol information
- */
-static enum ec_status hostcmd_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions |= BIT(3);
-	r->max_request_packet_size = HOSTCMD_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = HOSTCMD_MAX_RESPONSE_SIZE;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, hostcmd_get_protocol_info,
-		     EC_VER_MASK(0));
-
-void hostcmd_init(void)
-{
-	int ret;
-	struct rpmsg_ns_msg ns_msg;
-
-	if (IS_ENABLED(CONFIG_RPMSG_NAME_SERVICE)) {
-		ns_msg.addr = SCP_IPI_HOST_COMMAND;
-		strncpy(ns_msg.name, "cros-ec-rpmsg", RPMSG_NAME_SIZE);
-		ret = ipi_send(SCP_IPI_NS_SERVICE, &ns_msg, sizeof(ns_msg), 1);
-		if (ret)
-			CPRINTS("Failed to announce host command channel");
-	}
-}
diff --git a/chip/mt_scp/rv32i_common/hostcmd.h b/chip/mt_scp/rv32i_common/hostcmd.h
deleted file mode 100644
index b93f1e725d..0000000000
--- a/chip/mt_scp/rv32i_common/hostcmd.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_HOSTCMD_H
-#define __CROS_EC_HOSTCMD_H
-
-/* Initialize hostcmd. */
-void hostcmd_init(void);
-
-#endif /* __CROS_EC_HOSTCMD_H */
diff --git a/chip/mt_scp/rv32i_common/hrtimer.c b/chip/mt_scp/rv32i_common/hrtimer.c
deleted file mode 100644
index 89ffaa2fca..0000000000
--- a/chip/mt_scp/rv32i_common/hrtimer.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * High-res hardware timer
- *
- * SCP hardware 32bit count down timer can be configured to source clock from
- * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a
- * source, countdown mode and converts to micro second value matching common
- * timer.
- */
-
-#include "common.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-
-#define TIMER_SYSTEM 5
-#define TIMER_EVENT 3
-#define TIMER_CLOCK_MHZ 32.5
-#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1)
-
-/* High 32-bit for system timer. */
-static uint8_t sys_high;
-/* High 32-bit for event timer. */
-static uint8_t event_high;
-
-static void timer_enable(int n)
-{
-	/* cannot be changed when timer is enabled */
-	SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_EN;
-	SCP_CORE0_TIMER_EN(n) |= TIMER_EN;
-}
-
-static void timer_disable(int n)
-{
-	SCP_CORE0_TIMER_EN(n) &= ~TIMER_EN;
-	/* cannot be changed when timer is enabled */
-	SCP_CORE0_TIMER_IRQ_CTRL(n) &= ~TIMER_IRQ_EN;
-}
-
-static int timer_is_irq(int n)
-{
-	return SCP_CORE0_TIMER_IRQ_CTRL(n) & TIMER_IRQ_STATUS;
-}
-
-static void timer_ack_irq(int n)
-{
-	SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLR;
-}
-
-static void timer_set_reset_value(int n, uint32_t reset_value)
-{
-	/* cannot be changed when timer is enabled */
-	SCP_CORE0_TIMER_RST_VAL(n) = reset_value;
-}
-
-static void timer_set_clock(int n, uint32_t clock_source)
-{
-	SCP_CORE0_TIMER_EN(n) =
-		(SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) | clock_source;
-}
-
-static void timer_reset(int n)
-{
-	timer_disable(n);
-	timer_ack_irq(n);
-	timer_set_reset_value(n, 0xffffffff);
-	timer_set_clock(n, TIMER_CLK_SRC_32K);
-}
-
-/* Convert hardware countdown timer to 64bit countup ticks. */
-static uint64_t timer_read_raw_system(void)
-{
-	uint32_t timer_ctrl = SCP_CORE0_TIMER_IRQ_CTRL(TIMER_SYSTEM);
-	uint32_t sys_high_adj = sys_high;
-
-	/*
-	 * If an IRQ is pending, but has not been serviced yet, adjust the
-	 * sys_high value.
-	 */
-	if (timer_ctrl & TIMER_IRQ_STATUS)
-		sys_high_adj = sys_high ? (sys_high - 1)
-					: (TIMER_CLOCK_MHZ - 1);
-
-	return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) |
-				 SCP_CORE0_TIMER_CUR_VAL(TIMER_SYSTEM));
-}
-
-static uint64_t timer_read_raw_event(void)
-{
-	return OVERFLOW_TICKS - (((uint64_t)event_high << 32) |
-				 SCP_CORE0_TIMER_CUR_VAL(TIMER_EVENT));
-}
-
-static void timer_reload(int n, uint32_t value)
-{
-	timer_disable(n);
-	timer_set_reset_value(n, value);
-	timer_enable(n);
-}
-
-static int timer_reload_event_high(void)
-{
-	if (event_high) {
-		if (SCP_CORE0_TIMER_RST_VAL(TIMER_EVENT) == 0xffffffff)
-			timer_enable(TIMER_EVENT);
-		else
-			timer_reload(TIMER_EVENT, 0xffffffff);
-		event_high--;
-		return 1;
-	}
-
-	timer_disable(TIMER_EVENT);
-	return 0;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	int t;
-
-	/* enable clock gate */
-	SCP_SET_CLK_CG |= CG_TIMER_MCLK | CG_TIMER_BCLK;
-
-	/* reset all timer, select 32768Hz clock source */
-	for (t = 0; t < NUM_TIMERS; ++t)
-		timer_reset(t);
-
-	/* System timestamp timer */
-	timer_set_clock(TIMER_SYSTEM, TIMER_CLK_SRC_BCLK);
-	sys_high = TIMER_CLOCK_MHZ - 1;
-	timer_set_reset_value(TIMER_SYSTEM, 0xffffffff);
-	task_enable_irq(SCP_IRQ_TIMER(TIMER_SYSTEM));
-	timer_enable(TIMER_SYSTEM);
-
-	/* Event tick timer */
-	timer_set_clock(TIMER_EVENT, TIMER_CLK_SRC_BCLK);
-	task_enable_irq(SCP_IRQ_TIMER(TIMER_EVENT));
-
-	return SCP_IRQ_TIMER(TIMER_SYSTEM);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return timer_read_raw_system() / TIMER_CLOCK_MHZ;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return (timer_read_raw_event() + timer_read_raw_system())
-			/ TIMER_CLOCK_MHZ;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* c1ea4, magic number for clear state */
-	timer_disable(TIMER_EVENT);
-	timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4);
-	event_high = 0;
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ;
-	uint64_t now_raw = timer_read_raw_system();
-	uint32_t event_deadline;
-
-	if (deadline_raw > now_raw) {
-		deadline_raw -= now_raw;
-		event_deadline = (uint32_t)deadline_raw;
-		event_high = deadline_raw >> 32;
-	} else {
-		event_deadline = 1;
-		event_high = 0;
-	}
-
-	if (event_deadline)
-		timer_reload(TIMER_EVENT, event_deadline);
-	else
-		timer_reload_event_high();
-}
-
-static void irq_group6_handler(void)
-{
-	extern volatile int ec_int;
-
-	switch (ec_int) {
-	case SCP_IRQ_TIMER(TIMER_EVENT):
-		if (timer_is_irq(TIMER_EVENT)) {
-			timer_ack_irq(TIMER_EVENT);
-
-			if (!timer_reload_event_high())
-				process_timers(0);
-
-			task_clear_pending_irq(ec_int);
-		}
-		break;
-	case SCP_IRQ_TIMER(TIMER_SYSTEM):
-		/* If this is a hardware irq, check overflow */
-		if (!in_soft_interrupt_context()) {
-			timer_ack_irq(TIMER_SYSTEM);
-
-			if (sys_high) {
-				--sys_high;
-				process_timers(0);
-			} else {
-				/* Overflow, reload system timer */
-				sys_high = TIMER_CLOCK_MHZ - 1;
-				process_timers(1);
-			}
-
-			task_clear_pending_irq(ec_int);
-		} else {
-			process_timers(0);
-		}
-		break;
-	}
-}
-DECLARE_IRQ(6, irq_group6_handler, 0);
diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c
deleted file mode 100644
index 7e6b39e1f2..0000000000
--- a/chip/mt_scp/rv32i_common/intc.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* INTC control module */
-
-#include "console.h"
-#include "csr.h"
-#include "intc.h"
-#include "registers.h"
-
-/*
- * INTC_GRP_0 is reserved.  See swirq of syscall_handler() in
- * core/riscv-rv32i/task.c for more details.
- *
- * Lower group has higher priority.  Group 0 has highest priority.
- */
-enum INTC_GROUP {
-	INTC_GRP_0 = 0x0,
-	INTC_GRP_1,
-	INTC_GRP_2,
-	INTC_GRP_3,
-	INTC_GRP_4,
-	INTC_GRP_5,
-	INTC_GRP_6,
-	INTC_GRP_7,
-	INTC_GRP_8,
-	INTC_GRP_9,
-	INTC_GRP_10,
-	INTC_GRP_11,
-	INTC_GRP_12,
-	INTC_GRP_13,
-	INTC_GRP_14,
-};
-
-#ifdef BOARD_ASURADA_SCP
-static struct {
-	uint8_t group;
-} irqs[SCP_INTC_IRQ_COUNT] = {
-	/* 0 */
-	[SCP_IRQ_GIPC_IN0]		= { INTC_GRP_7 },
-	[SCP_IRQ_GIPC_IN1]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN3]		= { INTC_GRP_0 },
-	/* 4 */
-	[SCP_IRQ_SPM]			= { INTC_GRP_0 },
-	[SCP_IRQ_AP_CIRQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_EINT]			= { INTC_GRP_0 },
-	[SCP_IRQ_PMIC]			= { INTC_GRP_0 },
-	/* 8 */
-	[SCP_IRQ_UART0_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_I2C0]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C1_0]		= { INTC_GRP_0 },
-	/* 12 */
-	[SCP_IRQ_BUS_DBG_TRACKER]	= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL]		= { INTC_GRP_0 },
-	[SCP_IRQ_VOW]			= { INTC_GRP_0 },
-	[SCP_IRQ_TIMER0]		= { INTC_GRP_6 },
-	/* 16 */
-	[SCP_IRQ_TIMER1]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER2]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER3]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER4]		= { INTC_GRP_6 },
-	/* 20 */
-	[SCP_IRQ_TIMER5]		= { INTC_GRP_6 },
-	[SCP_IRQ_OS_TIMER]		= { INTC_GRP_0 },
-	[SCP_IRQ_UART0_RX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_RX]		= { INTC_GRP_12 },
-	/* 24 */
-	[SCP_IRQ_GDMA]			= { INTC_GRP_0 },
-	[SCP_IRQ_AUDIO]			= { INTC_GRP_0 },
-	[SCP_IRQ_MD_DSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_ADSP]			= { INTC_GRP_0 },
-	/* 28 */
-	[SCP_IRQ_CPU_TICK]		= { INTC_GRP_0 },
-	[SCP_IRQ_SPI0]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI1]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI2]			= { INTC_GRP_0 },
-	/* 32 */
-	[SCP_IRQ_NEW_INFRA_SYS_CIRQ]	= { INTC_GRP_0 },
-	[SCP_IRQ_DBG]			= { INTC_GRP_0 },
-	[SCP_IRQ_CCIF0]			= { INTC_GRP_0 },
-	[SCP_IRQ_CCIF1]			= { INTC_GRP_0 },
-	/* 36 */
-	[SCP_IRQ_CCIF2]			= { INTC_GRP_0 },
-	[SCP_IRQ_WDT]			= { INTC_GRP_0 },
-	[SCP_IRQ_USB0]			= { INTC_GRP_0 },
-	[SCP_IRQ_USB1]			= { INTC_GRP_0 },
-	/* 40 */
-	[SCP_IRQ_DPMAIF]		= { INTC_GRP_0 },
-	[SCP_IRQ_INFRA]			= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL_CORE]		= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL2_CORE]	= { INTC_GRP_0 },
-	/* 44 */
-	[SCP_IRQ_CLK_CTRL2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN4]		= { INTC_GRP_0 },
-	[SCP_IRQ_PERIBUS_TIMEOUT]	= { INTC_GRP_0 },
-	[SCP_IRQ_INFRABUS_TIMEOUT]	= { INTC_GRP_0 },
-	/* 48 */
-	[SCP_IRQ_MET0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET3]			= { INTC_GRP_0 },
-	/* 52 */
-	[SCP_IRQ_AP_WDT]		= { INTC_GRP_0 },
-	[SCP_IRQ_L2TCM_SEC_VIO]		= { INTC_GRP_0 },
-	[SCP_IRQ_CPU_TICK1]		= { INTC_GRP_0 },
-	[SCP_IRQ_MAD_DATAIN]		= { INTC_GRP_0 },
-	/* 56 */
-	[SCP_IRQ_I3C0_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C1_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C2_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_APU_ENGINE]		= { INTC_GRP_0 },
-	/* 60 */
-	[SCP_IRQ_MBOX0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX3]			= { INTC_GRP_0 },
-	/* 64 */
-	[SCP_IRQ_MBOX4]			= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_CLK_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_BUS_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_APSRC_REQ]		= { INTC_GRP_0 },
-	/* 68 */
-	[SCP_IRQ_APU_MBOX]		= { INTC_GRP_0 },
-	[SCP_IRQ_DEVAPC_SECURE_VIO]	= { INTC_GRP_0 },
-	/* 72 */
-	/* 76 */
-	[SCP_IRQ_I2C1_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C2]			= { INTC_GRP_0 },
-	/* 80 */
-	[SCP_IRQ_AUD2AUDIODSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_AUD2AUDIODSP_2]	= { INTC_GRP_0 },
-	[SCP_IRQ_CONN2ADSP_A2DPOL]	= { INTC_GRP_0 },
-	[SCP_IRQ_CONN2ADSP_BTCVSD]	= { INTC_GRP_0 },
-	/* 84 */
-	[SCP_IRQ_CONN2ADSP_BLEISO]	= { INTC_GRP_0 },
-	[SCP_IRQ_PCIE2ADSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_APU2ADSP_ENGINE]	= { INTC_GRP_0 },
-	[SCP_IRQ_APU2ADSP_MBOX]		= { INTC_GRP_0 },
-	/* 88 */
-	[SCP_IRQ_CCIF3]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA0]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA1]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA2]		= { INTC_GRP_0 },
-	/* 92 */
-	[SCP_IRQ_I2C_DMA3]		= { INTC_GRP_0 },
-};
-BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
-#endif
-
-#ifdef BOARD_CHERRY_SCP
-static struct {
-	uint8_t group;
-} irqs[SCP_INTC_IRQ_COUNT] = {
-	/* 0 */
-	[SCP_IRQ_GIPC_IN0]		= { INTC_GRP_7 },
-	[SCP_IRQ_GIPC_IN1]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN3]		= { INTC_GRP_0 },
-	/* 4 */
-	[SCP_IRQ_SPM]			= { INTC_GRP_0 },
-	[SCP_IRQ_AP_CIRQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_EINT]			= { INTC_GRP_0 },
-	[SCP_IRQ_PMIC]			= { INTC_GRP_0 },
-	/* 8 */
-	[SCP_IRQ_UART0_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_I2C0]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C1_0]		= { INTC_GRP_0 },
-	/* 12 */
-	[SCP_IRQ_BUS_DBG_TRACKER]	= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL]		= { INTC_GRP_0 },
-	[SCP_IRQ_VOW]			= { INTC_GRP_0 },
-	[SCP_IRQ_TIMER0]		= { INTC_GRP_6 },
-	/* 16 */
-	[SCP_IRQ_TIMER1]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER2]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER3]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER4]		= { INTC_GRP_6 },
-	/* 20 */
-	[SCP_IRQ_TIMER5]		= { INTC_GRP_6 },
-	[SCP_IRQ_OS_TIMER]		= { INTC_GRP_0 },
-	[SCP_IRQ_UART0_RX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_RX]		= { INTC_GRP_12 },
-	/* 24 */
-	[SCP_IRQ_GDMA]			= { INTC_GRP_0 },
-	[SCP_IRQ_AUDIO]			= { INTC_GRP_0 },
-	[SCP_IRQ_MD_DSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_ADSP]			= { INTC_GRP_0 },
-	/* 28 */
-	[SCP_IRQ_CPU_TICK]		= { INTC_GRP_0 },
-	[SCP_IRQ_SPI0]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI1]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI2]			= { INTC_GRP_0 },
-	/* 32 */
-	[SCP_IRQ_NEW_INFRA_SYS_CIRQ]	= { INTC_GRP_0 },
-	[SCP_IRQ_DBG]			= { INTC_GRP_0 },
-	[SCP_IRQ_GCE]			= { INTC_GRP_0 },
-	[SCP_IRQ_MDP_GCE]		= { INTC_GRP_0 },
-	/* 36 */
-	[SCP_IRQ_VDEC]			= { INTC_GRP_8 },
-	[SCP_IRQ_WDT]			= { INTC_GRP_0 },
-	[SCP_IRQ_VDEC_LAT]		= { INTC_GRP_8 },
-	[SCP_IRQ_VDEC1]			= { INTC_GRP_8 },
-	/* 40 */
-	[SCP_IRQ_VDEC1_LAT]		= { INTC_GRP_8 },
-	[SCP_IRQ_INFRA]			= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL_CORE]		= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL2_CORE]	= { INTC_GRP_0 },
-	/* 44 */
-	[SCP_IRQ_CLK_CTRL2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN4]		= { INTC_GRP_0 },
-	[SCP_IRQ_PERIBUS_TIMEOUT]	= { INTC_GRP_0 },
-	[SCP_IRQ_INFRABUS_TIMEOUT]	= { INTC_GRP_0 },
-	/* 48 */
-	[SCP_IRQ_MET0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET3]			= { INTC_GRP_0 },
-	/* 52 */
-	[SCP_IRQ_AP_WDT]		= { INTC_GRP_0 },
-	[SCP_IRQ_L2TCM_SEC_VIO]		= { INTC_GRP_0 },
-	[SCP_IRQ_VDEC_INT_LINE_CNT]	= { INTC_GRP_0 },
-	[SCP_IRQ_VOW_DATAIN]		= { INTC_GRP_0 },
-	/* 56 */
-	[SCP_IRQ_I3C0_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C1_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_VENC]			= { INTC_GRP_8 },
-	[SCP_IRQ_APU_ENGINE]		= { INTC_GRP_0 },
-	/* 60 */
-	[SCP_IRQ_MBOX0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX3]			= { INTC_GRP_0 },
-	/* 64 */
-	[SCP_IRQ_MBOX4]			= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_CLK_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_BUS_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_APSRC_REQ]		= { INTC_GRP_0 },
-	/* 68 */
-	[SCP_IRQ_APU_MBOX]		= { INTC_GRP_0 },
-	[SCP_IRQ_DEVAPC_SECURE_VIO]	= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_29]		= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_28]		= { INTC_GRP_0 },
-	/* 72 */
-	[SCP_IRQ_CAMSYS_5]		= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_4]		= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_3]		= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_2]		= { INTC_GRP_0 },
-	/* 76 */
-	[SCP_IRQ_HDMIRX_PM_DVI_SQH]	= { INTC_GRP_0 },
-	[SCP_IRQ_HDMIRX_RESERVED]	= { INTC_GRP_0 },
-	[SCP_IRQ_NNA0_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA0_1]		= { INTC_GRP_0 },
-	/* 80 */
-	[SCP_IRQ_NNA0_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA1_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA1_1]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA1_2]		= { INTC_GRP_0 },
-	/* 84 */
-	[SCP_IRQ_JPEGENC]		= { INTC_GRP_0 },
-	[SCP_IRQ_JPEGDEC]		= { INTC_GRP_0 },
-	[SCP_IRQ_JPEGDEC_C2]		= { INTC_GRP_0 },
-	[SCP_IRQ_VENC_C1]		= { INTC_GRP_8 },
-	/* 88 */
-	[SCP_IRQ_JPEGENC_C1]		= { INTC_GRP_0 },
-	[SCP_IRQ_JPEGDEC_C1]		= { INTC_GRP_0 },
-	[SCP_IRQ_HDMITX]		= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
-	/* 92 */
-	[SCP_IRQ_EARC]			= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
-	/* 96 */
-	[SCP_IRQ_I2C2]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C3]			= { INTC_GRP_0 },
-	[SCP_IRQ_I3C2_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C3_IBI_WAKE]		= { INTC_GRP_0 },
-	/* 100 */
-	[SCP_IRQ_SYS_I2C_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_1]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_3]		= { INTC_GRP_0 },
-	/* 104 */
-	[SCP_IRQ_SYS_I2C_4]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_5]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_6]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_7]		= { INTC_GRP_0 },
-	/* 108 */
-	[SCP_IRQ_DISP2ADSP_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_DISP2ADSP_1]		= { INTC_GRP_0 },
-	[SCP_IRQ_DISP2ADSP_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_DISP2ADSP_3]		= { INTC_GRP_0 },
-	/* 112 */
-	[SCP_IRQ_DISP2ADSP_4]		= { INTC_GRP_0 },
-	[SCP_IRQ_VDO1_DISP_MON2ADSP_0]	= { INTC_GRP_0 },
-	[SCP_IRQ_VDO1_DISP_MON2ADSP_1]	= { INTC_GRP_0 },
-	[SCP_IRQ_VDO1_DISP_MON2ADSP_2]	= { INTC_GRP_0 },
-	/* 116 */
-	[SCP_IRQ_GCE1_SECURE]		= { INTC_GRP_0 },
-	[SCP_IRQ_GCE_SECURE]		= { INTC_GRP_0 },
-};
-BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
-#endif
-
-/*
- * Find current interrupt source.
- *
- * Lower group has higher priority.
- * Higher INT number has higher priority.
- */
-int chip_get_ec_int(void)
-{
-	extern volatile int ec_int;
-	unsigned int group, sta;
-	int word;
-
-	if (!SCP_CORE0_INTC_IRQ_OUT)
-		goto error;
-
-	group = read_csr(CSR_VIC_MICAUSE);
-
-	for (word = SCP_INTC_GRP_LEN - 1; word >= 0; --word) {
-		sta = SCP_CORE0_INTC_IRQ_GRP_STA(group, word);
-		if (sta) {
-			ec_int = __fls(sta) + word * 32;
-			return ec_int;
-		}
-	}
-
-error:
-	/* unreachable, SCP crashes and dumps registers after returning */
-	return -1;
-}
-
-int chip_get_intc_group(int irq)
-{
-	return irqs[irq].group;
-}
-
-void chip_enable_irq(int irq)
-{
-	unsigned int word, group, mask;
-
-	word = SCP_INTC_WORD(irq);
-	group = irqs[irq].group;
-	mask = BIT(SCP_INTC_BIT(irq));
-
-	/* disable interrupt */
-	SCP_CORE0_INTC_IRQ_EN(word) &= ~mask;
-	/* set group */
-	SCP_CORE0_INTC_IRQ_GRP(group, word) |= mask;
-	/* set as a wakeup source */
-	SCP_CORE0_INTC_SLP_WAKE_EN(word) |= mask;
-	/* enable interrupt */
-	SCP_CORE0_INTC_IRQ_EN(word) |= mask;
-}
-
-void chip_disable_irq(int irq)
-{
-	/*
-	 * Disabling INTC IRQ in runtime is unstable in MT8192 SCP.
-	 * See b/163682416#comment17.
-	 *
-	 * Ideally, this function will be removed by LTO.
-	 */
-	ccprints("WARNING: %s is unsupported", __func__);
-}
-
-void chip_clear_pending_irq(int irq)
-{
-	unsigned int group = irqs[irq].group;
-
-	/* must clear interrupt source before writing this */
-	write_csr(CSR_VIC_MIEMS, group);
-}
-
-int chip_trigger_irq(int irq)
-{
-	extern volatile int ec_int;
-
-	ec_int = irq;
-	return irqs[irq].group;
-}
-
-void chip_init_irqs(void)
-{
-	unsigned int word, group;
-
-	/* INTC init */
-	/* clear enable and wakeup settings */
-	for (word = 0; word < SCP_INTC_GRP_LEN; ++word) {
-		SCP_CORE0_INTC_IRQ_EN(word) = 0x0;
-		SCP_CORE0_INTC_SLP_WAKE_EN(word) = 0x0;
-
-		/* clear group settings */
-		for (group = 0; group < SCP_INTC_GRP_COUNT; ++group)
-			SCP_CORE0_INTC_IRQ_GRP(group, word) = 0x0;
-	}
-	/* reset to default polarity */
-	SCP_CORE0_INTC_IRQ_POL(0) = SCP_INTC_IRQ_POL0;
-	SCP_CORE0_INTC_IRQ_POL(1) = SCP_INTC_IRQ_POL1;
-	SCP_CORE0_INTC_IRQ_POL(2) = SCP_INTC_IRQ_POL2;
-#if SCP_INTC_GRP_LEN > 3
-	SCP_CORE0_INTC_IRQ_POL(3) = SCP_INTC_IRQ_POL3;
-#endif
-
-	/* GVIC init */
-	/* enable all groups as interrupt sources */
-	write_csr(CSR_VIC_MIMASK_G0, 0xffffffff);
-	/* use level trigger */
-	write_csr(CSR_VIC_MILSEL_G0, 0xffffffff);
-	/* enable all groups as wakeup sources */
-	write_csr(CSR_VIC_MIWAKEUP_G0, 0xffffffff);
-
-	/* enable GVIC */
-	set_csr(CSR_MCTREN, CSR_MCTREN_VIC);
-}
diff --git a/chip/mt_scp/rv32i_common/ipi.c b/chip/mt_scp/rv32i_common/ipi.c
deleted file mode 100644
index cba5c65d0b..0000000000
--- a/chip/mt_scp/rv32i_common/ipi.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "cache.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hostcmd.h"
-#include "ipi_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "video.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-static uint8_t init_done;
-
-static struct mutex ipi_lock;
-static struct ipc_shared_obj *const ipi_send_buf =
-	(struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR;
-static struct ipc_shared_obj *const ipi_recv_buf =
-	(struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR +
-				  sizeof(struct ipc_shared_obj));
-
-static uint32_t disable_irq_count, saved_int_mask;
-
-void ipi_disable_irq(void)
-{
-	if (atomic_read_add(&disable_irq_count, 1) == 0)
-		saved_int_mask = read_clear_int_mask();
-}
-
-void ipi_enable_irq(void)
-{
-	if (atomic_read_sub(&disable_irq_count, 1) == 1)
-		set_int_mask(saved_int_mask);
-}
-
-static int ipi_is_busy(void)
-{
-	return SCP_SCP2APMCU_IPC_SET & IPC_SCP2HOST;
-}
-
-static void ipi_wake_ap(int32_t id)
-{
-	if (id >= IPI_COUNT)
-		return;
-
-	if (*ipi_wakeup_table[id])
-		SCP_SCP2SPM_IPC_SET = IPC_SCP2HOST;
-}
-
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait)
-{
-	int ret;
-
-	if (!init_done) {
-		CPRINTS("IPI has not initialized");
-		return EC_ERROR_BUSY;
-	}
-
-	if (in_interrupt_context()) {
-		CPRINTS("invoke %s() in ISR context", __func__);
-		return EC_ERROR_BUSY;
-	}
-
-	if (len > sizeof(ipi_send_buf->buffer)) {
-		CPRINTS("data length exceeds limitation");
-		return EC_ERROR_INVAL;
-	}
-
-	ipi_disable_irq();
-	mutex_lock(&ipi_lock);
-
-	if (ipi_is_busy()) {
-		/*
-		 * If the following conditions meet,
-		 *   1) There is an IPI pending in AP.
-		 *   2) The incoming IPI is a wakeup IPI.
-		 * then it assumes that AP is in suspend state.
-		 * Send a AP wakeup request to SPM.
-		 *
-		 * The incoming IPI will be checked if it's a wakeup source.
-		 */
-		ipi_wake_ap(id);
-
-		CPRINTS("IPI busy, id=%d", id);
-		ret = EC_ERROR_BUSY;
-		goto error;
-	}
-
-	ipi_send_buf->id = id;
-	ipi_send_buf->len = len;
-	memcpy(ipi_send_buf->buffer, buf, len);
-
-	/* flush memory cache (if any) */
-	cache_flush_dcache_range((uintptr_t)ipi_send_buf,
-				 sizeof(*ipi_send_buf));
-
-	/* interrupt AP to handle the message */
-	ipi_wake_ap(id);
-	SCP_SCP2APMCU_IPC_SET = IPC_SCP2HOST;
-
-	if (wait)
-		while (ipi_is_busy())
-			;
-
-	ret = EC_SUCCESS;
-error:
-	mutex_unlock(&ipi_lock);
-	ipi_enable_irq();
-	return ret;
-}
-
-static void ipi_enable_deferred(void)
-{
-	struct scp_run_t scp_run;
-	int ret;
-
-	init_done = 1;
-
-	/* inform AP that SCP is up */
-	scp_run.signaled = 1;
-	strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW),
-		SCP_FW_VERSION_LEN);
-	scp_run.dec_capability = video_get_dec_capability();
-	scp_run.enc_capability = video_get_enc_capability();
-
-	ret = ipi_send(SCP_IPI_INIT, (void *)&scp_run, sizeof(scp_run), 1);
-	if (ret) {
-		CPRINTS("failed to send initialization IPC messages");
-		init_done = 0;
-		return;
-	}
-
-#ifdef HAS_TASK_HOSTCMD
-	hostcmd_init();
-#endif
-
-	task_enable_irq(SCP_IRQ_GIPC_IN0);
-}
-DECLARE_DEFERRED(ipi_enable_deferred);
-
-static void ipi_init(void)
-{
-	memset(ipi_send_buf, 0, sizeof(struct ipc_shared_obj));
-	memset(ipi_recv_buf, 0, sizeof(struct ipc_shared_obj));
-
-	/* enable IRQ after all tasks are up */
-	hook_call_deferred(&ipi_enable_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT);
-
-static void ipi_handler(void)
-{
-	if (ipi_recv_buf->id >= IPI_COUNT) {
-		CPRINTS("invalid IPI, id=%d", ipi_recv_buf->id);
-		return;
-	}
-
-	CPRINTS("IPI %d", ipi_recv_buf->id);
-
-	ipi_handler_table[ipi_recv_buf->id](
-		ipi_recv_buf->id, ipi_recv_buf->buffer, ipi_recv_buf->len);
-}
-
-static void irq_group7_handler(void)
-{
-	extern volatile int ec_int;
-
-	if (SCP_GIPC_IN_SET & GIPC_IN(0)) {
-		ipi_handler();
-		SCP_GIPC_IN_CLR = GIPC_IN(0);
-		asm volatile ("fence.i" ::: "memory");
-		task_clear_pending_irq(ec_int);
-	}
-}
-DECLARE_IRQ(7, irq_group7_handler, 0);
diff --git a/chip/mt_scp/rv32i_common/ipi_chip.h b/chip/mt_scp/rv32i_common/ipi_chip.h
deleted file mode 100644
index 47a9434b09..0000000000
--- a/chip/mt_scp/rv32i_common/ipi_chip.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_IPI_CHIP_H
-#define __CROS_EC_IPI_CHIP_H
-
-#include "common.h"
-
-/*
- * Length of EC version string is at most 32 byte (NULL included), which
- * also aligns SCP fw_version length.
- */
-#define SCP_FW_VERSION_LEN 32
-
-#ifndef SCP_IPI_INIT
-#error If CONFIG_IPI is enabled, SCP_IPI_INIT must be defined.
-#endif
-
-/*
- * Share buffer layout for SCP_IPI_INIT response. This structure should sync
- * across kernel and EC.
- */
-struct scp_run_t {
-	uint32_t signaled;
-	int8_t fw_ver[SCP_FW_VERSION_LEN];
-	uint32_t dec_capability;
-	uint32_t enc_capability;
-};
-
-/*
- * The layout of the IPC0 AP/SCP shared buffer.
- * This should sync across kernel and EC.
- */
-struct ipc_shared_obj {
-	/* IPI ID */
-	int32_t id;
-	/* Length of the contents in buffer. */
-	uint32_t len;
-	/* Shared buffer contents. */
-	uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE];
-};
-
-/* Send a IPI contents to AP.  This shouldn't be used in ISR context. */
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait);
-
-/*
- * An IPC IRQ could be shared across many IPI handlers.
- * Those handlers would usually operate on disabling or enabling the IPC IRQ.
- * This may disorder the actual timing to on/off the IRQ when there are many
- * tasks try to operate on it.  As a result, any access to the SCP_IRQ_*
- * should go through ipi_{en,dis}able_irq(), which support a counter to
- * enable/disable the IRQ at correct timing.
- */
-/* Disable IPI IRQ. */
-void ipi_disable_irq(void);
-/* Enable IPI IRQ. */
-void ipi_enable_irq(void);
-
-/* IPI tables */
-extern void (*const ipi_handler_table[])(int32_t, void *, uint32_t);
-extern int *const ipi_wakeup_table[];
-
-/* Helper macros to build the IPI handler and wakeup functions. */
-#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler)
-#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup)
-
-/*
- * Macro to declare an IPI handler.
- * _id: The ID of the IPI
- * handler: The IPI handler function
- * is_wakeup_src: Declare IPI ID as a wake-up source or not
- */
-#define DECLARE_IPI(_id, handler, is_wakeup_src) \
-	struct ipi_num_check##_id { \
-		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
-		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
-	};  \
-	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
-	{ \
-		handler(id, buf, len); \
-	} \
-	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
-
-#endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt_scp/rv32i_common/ipi_table.c b/chip/mt_scp/rv32i_common/ipi_table.c
deleted file mode 100644
index 8fe3f1e598..0000000000
--- a/chip/mt_scp/rv32i_common/ipi_table.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IPI handlers declaration
- */
-
-#include "common.h"
-#include "ipi_chip.h"
-
-typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#define ipi_arguments int32_t id, void *data, uint32_t len
-
-#if PASS == 1
-void ipi_handler_undefined(ipi_arguments) { }
-
-const int ipi_wakeup_undefined;
-
-#define table(type, name, x) x
-
-#define ipi_x_func(suffix, args, number)                                       \
-	extern void __attribute__(                                             \
-		(used, weak, alias(STRINGIFY(ipi_##suffix##_undefined))))      \
-		ipi_##number##_##suffix(args);
-
-#define ipi_x_var(suffix, number)                                              \
-	extern int __attribute__(                                              \
-		(weak, alias(STRINGIFY(ipi_##suffix##_undefined))))            \
-		ipi_##number##_##suffix;
-
-#endif /* PASS == 1 */
-
-#if PASS == 2
-
-#undef table
-#undef ipi_x_func
-#undef ipi_x_var
-
-#define table(type, name, x)                                                   \
-	type const name[]                                                      \
-		__attribute__((aligned(4), used, section(".rodata.ipi"))) = {x}
-
-#define ipi_x_var(suffix, number)                                              \
-	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
-
-#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
-
-#endif /* PASS == 2 */
-
-/*
- * Include generated IPI table (by util/gen_ipi_table). The contents originate
- * from IPI_COUNT definition in board.h
- */
-#include "ipi_table_gen.inc"
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "ipi_table.c"
-BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT);
-BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT);
-#endif
diff --git a/chip/mt_scp/rv32i_common/memmap.c b/chip/mt_scp/rv32i_common/memmap.c
deleted file mode 100644
index a666bb23d7..0000000000
--- a/chip/mt_scp/rv32i_common/memmap.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cache.h"
-#include "registers.h"
-#include "stdint.h"
-
-/*
- * Map SCP address (bits 31~28) to AP address
- *
- * SCP address	AP address	Note
- *
- * 0x0000_0000			SRAM
- * 0x1000_0000	0x5000_0000	CPU DRAM
- * 0x2000_0000	0x7000_0000
- * 0x3000_0000
- *
- * 0x4000_0000
- * 0x5000_0000	0x0000_0000
- * 0x6000_0000	0x1000_0000
- * 0x7000_0000	0xa000_0000
- *
- * 0x8000_0000
- * 0x9000_0000	0x8000_0000
- * 0xa000_0000	0x9000_0000
- * 0xb000_0000
- *
- * 0xc000_0000	0x8000_0000
- * 0xd000_0000	0x2000_0000
- * 0xe000_0000	0x3000_0000
- * 0xf000_0000	0x6000_0000
- */
-
-#define REMAP_ADDR_SHIFT		28
-#define REMAP_ADDR_LSB_MASK		(BIT(REMAP_ADDR_SHIFT) - 1)
-#define REMAP_ADDR_MSB_MASK		((~0) << REMAP_ADDR_SHIFT)
-#define MAP_INVALID 0xff
-
-static const uint8_t addr_map[16] = {
-	MAP_INVALID,	/* SRAM */
-	0x5,		/* ext_addr_0x1 */
-	0x7,		/* ext_addr_0x2 */
-	MAP_INVALID,	/* no ext_addr_0x3 */
-
-	MAP_INVALID,	/* no ext_addr_0x4 */
-	0x0,		/* ext_addr_0x5 */
-	0x1,		/* ext_addr_0x6 */
-	0xa,		/* ext_addr_0x7 */
-
-	MAP_INVALID,	/* no ext_addr_0x8 */
-	0x8,		/* ext_addr_0x9 */
-	0x9,		/* ext_addr_0xa */
-	MAP_INVALID,	/* no ext_addr_0xb */
-
-	0x8,		/* ext_addr_0xc */
-	0x2,		/* ext_addr_0xd */
-	0x3,		/* ext_addr_0xe */
-	0x6,		/* ext_addr_0xf */
-};
-
-void memmap_init(void)
-{
-	SCP_R_REMAP_0X0123 =
-		(uint32_t)addr_map[0x1] << 8 |
-		(uint32_t)addr_map[0x2] << 16;
-
-	SCP_R_REMAP_0X4567 =
-		(uint32_t)addr_map[0x5] << 8 |
-		(uint32_t)addr_map[0x6] << 16 |
-		(uint32_t)addr_map[0x7] << 24;
-
-	SCP_R_REMAP_0X89AB =
-		(uint32_t)addr_map[0x9] << 8 |
-		(uint32_t)addr_map[0xa] << 16;
-
-	SCP_R_REMAP_0XCDEF =
-		(uint32_t)addr_map[0xc] |
-		(uint32_t)addr_map[0xd] << 8 |
-		(uint32_t)addr_map[0xe] << 16 |
-		(uint32_t)addr_map[0xf] << 24;
-
-	cache_init();
-}
-
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
-{
-	int i;
-	uint8_t msb = ap_addr >> REMAP_ADDR_SHIFT;
-
-	for (i = 0; i < ARRAY_SIZE(addr_map); ++i) {
-		if (addr_map[i] != msb)
-			continue;
-
-		*scp_addr = (ap_addr & REMAP_ADDR_LSB_MASK) |
-			(i << REMAP_ADDR_SHIFT);
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
-{
-	int i = scp_addr >> REMAP_ADDR_SHIFT;
-
-	if (addr_map[i] == MAP_INVALID)
-		return EC_ERROR_INVAL;
-
-	*ap_addr = (scp_addr & REMAP_ADDR_LSB_MASK) |
-		(addr_map[i] << REMAP_ADDR_SHIFT);
-	return EC_SUCCESS;
-}
diff --git a/chip/mt_scp/rv32i_common/memmap.h b/chip/mt_scp/rv32i_common/memmap.h
deleted file mode 100644
index 0857c9a89e..0000000000
--- a/chip/mt_scp/rv32i_common/memmap.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_MEMMAP_H
-#define __CROS_EC_MEMMAP_H
-
-#include "stdint.h"
-
-void memmap_init(void);
-
-/**
- * Translate AP addr to SCP addr.
- *
- * @param ap_addr		AP address to translate
- * @param scp_addr		Translated AP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr);
-
-/**
- * Translate SCP addr to AP addr.
- *
- * @param scp_addr		SCP address to translate
- * @param ap_addr		Translated SCP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
-
-#endif /* #ifndef __CROS_EC_MEMMAP_H */
diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h
deleted file mode 100644
index adbef5f98b..0000000000
--- a/chip/mt_scp/rv32i_common/registers.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Register map */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "intc.h"
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-#define SCP_REG_BASE			0x70000000
-
-/* clock control */
-#define SCP_CLK_CTRL_BASE		(SCP_REG_BASE + 0x21000)
-/* system clock counter value */
-#define SCP_CLK_SYS_VAL			REG32(SCP_CLK_CTRL_BASE + 0x0014)
-#define   CLK_SYS_VAL_MASK		(0x3ff << 0)
-#define   CLK_SYS_VAL_VAL(v)		((v) & CLK_SYS_VAL_MASK)
-/* ULPOSC clock counter value */
-#define SCP_CLK_HIGH_VAL		REG32(SCP_CLK_CTRL_BASE + 0x0018)
-#define   CLK_HIGH_VAL_MASK             (0x1f << 0)
-#define   CLK_HIGH_VAL_VAL(v)		((v) & CLK_HIGH_VAL_MASK)
-/* sleep mode control */
-#define SCP_SLEEP_CTRL                  REG32(SCP_CLK_CTRL_BASE + 0x0020)
-#define   SLP_CTRL_EN			BIT(0)
-#define   VREQ_COUNT_MASK		(0x7F << 1)
-#define   VREQ_COUNT_VAL(v)		(((v) << 1) & VREQ_COUNT_MASK)
-#define   SPM_SLP_MODE			BIT(8)
-/* clock divider select */
-#define SCP_CLK_DIV_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0024)
-#define   CLK_DIV_SEL1			0
-#define   CLK_DIV_SEL2			1
-#define   CLK_DIV_SEL4			2
-#define   CLK_DIV_SEL3			3
-/* clock gate */
-#define SCP_SET_CLK_CG			REG32(SCP_CLK_CTRL_BASE + 0x0030)
-#define   CG_TIMER_MCLK			BIT(0)
-#define   CG_TIMER_BCLK			BIT(1)
-#define   CG_MAD_MCLK			BIT(2)
-#define   CG_I2C_MCLK			BIT(3)
-#define   CG_I2C_BCLK			BIT(4)
-#define   CG_GPIO_MCLK			BIT(5)
-#define   CG_AP2P_MCLK			BIT(6)
-#define   CG_UART0_MCLK			BIT(7)
-#define   CG_UART0_BCLK			BIT(8)
-#define   CG_UART0_RST			BIT(9)
-#define   CG_UART1_MCLK			BIT(10)
-#define   CG_UART1_BCLK			BIT(11)
-#define   CG_UART1_RST			BIT(12)
-#define   CG_SPI0			BIT(13)
-#define   CG_SPI1			BIT(14)
-#define   CG_SPI2			BIT(15)
-#define   CG_DMA_CH0			BIT(16)
-#define   CG_DMA_CH1			BIT(17)
-#define   CG_DMA_CH2			BIT(18)
-#define   CG_DMA_CH3			BIT(19)
-#define   CG_I3C0			BIT(21)
-#define   CG_I3C1			BIT(22)
-#define   CG_DMA2_CH0			BIT(23)
-#define   CG_DMA2_CH1			BIT(24)
-#define   CG_DMA2_CH2			BIT(25)
-#define   CG_DMA2_CH3			BIT(26)
-/* UART clock select */
-#define SCP_UART_CK_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0044)
-#define   UART0_CK_SEL_SHIFT		0
-#define   UART0_CK_SEL_MASK		(0x3 << UART0_CK_SEL_SHIFT)
-#define   UART0_CK_SEL_VAL(v)		((v) & UART0_CK_SEL_MASK)
-#define   UART0_CK_SW_STATUS_MASK	(0xf << 8)
-#define   UART0_CK_SW_STATUS_VAL(v)	((v) & UART0_CK_SW_STATUS_MASK)
-#define   UART1_CK_SEL_SHIFT		16
-#define   UART1_CK_SEL_MASK		(0x3 << UART1_CK_SEL_SHIFT)
-#define   UART1_CK_SEL_VAL(v)		((v) & UART1_CK_SEL_MASK)
-#define   UART1_CK_SW_STATUS_MASK	(0xf << 24)
-#define   UART1_CK_SW_STATUS_VAL(v)	((v) & UART1_CK_SW_STATUS_MASK)
-#define     UART_CK_SEL_26M		0
-#define     UART_CK_SEL_32K		1
-#define     UART_CK_SEL_ULPOSC		2
-#define     UART_CK_SW_STATUS_26M	BIT(0)
-#define     UART_CK_SW_STATUS_32K	BIT(1)
-#define     UART_CK_SW_STATUS_ULPOS	BIT(2)
-/* BCLK clock select */
-#define SCP_BCLK_CK_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0048)
-#define   BCLK_CK_SEL_SYS_DIV8		0
-#define   BCLK_CK_SEL_32K		1
-#define   BCLK_CK_SEL_ULPOSC_DIV8	2
-/* VREQ control */
-#define SCP_CPU_VREQ_CTRL		REG32(SCP_CLK_CTRL_BASE + 0x0054)
-#define   VREQ_SEL			BIT(0)
-#define   VREQ_VALUE			BIT(4)
-#define   VREQ_EXT_SEL			BIT(8)
-#define   VREQ_DVFS_SEL			BIT(16)
-#define   VREQ_DVFS_VALUE		BIT(20)
-#define   VREQ_DVFS_EXT_SEL		BIT(24)
-#define   VREQ_SRCLKEN_SEL		BIT(27)
-#define   VREQ_SRCLKEN_VALUE		BIT(28)
-/* clock on control */
-#define SCP_CLK_HIGH_CORE_CG		REG32(SCP_CLK_CTRL_BASE + 0x005C)
-#define   HIGH_CORE_CG			BIT(1)
-#define SCP_CLK_ON_CTRL			REG32(SCP_CLK_CTRL_BASE + 0x006C)
-#define   HIGH_AO			BIT(0)
-#define   HIGH_DIS_SUB			BIT(1)
-#define   HIGH_CG_AO			BIT(2)
-#define   HIGH_CORE_AO			BIT(4)
-#define   HIGH_CORE_DIS_SUB		BIT(5)
-#define   HIGH_CORE_CG_AO		BIT(6)
-
-/* system control */
-#define SCP_SYS_CTRL			REG32(SCP_REG_BASE + 0x24000)
-#define   AUTO_DDREN			BIT(9)
-
-/* IPC */
-#define SCP_SCP2APMCU_IPC_SET		REG32(SCP_REG_BASE + 0x24080)
-#define SCP_SCP2SPM_IPC_SET		REG32(SCP_REG_BASE + 0x24090)
-#define   IPC_SCP2HOST			BIT(0)
-#define SCP_GIPC_IN_SET			REG32(SCP_REG_BASE + 0x24098)
-#define SCP_GIPC_IN_CLR			REG32(SCP_REG_BASE + 0x2409C)
-#define   GIPC_IN(n)			BIT(n)
-
-/* UART */
-#define SCP_UART_COUNT			2
-#define UART_TX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _TX)
-#define UART_RX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _RX)
-#define SCP_UART0_BASE			(SCP_REG_BASE + 0x26000)
-#define SCP_UART1_BASE			(SCP_REG_BASE + 0x27000)
-#define SCP_UART_BASE(n)		CONCAT3(SCP_UART, n, _BASE)
-#define UART_REG(n, offset)		REG32_ADDR(SCP_UART_BASE(n))[offset]
-
-/* WDT */
-#define SCP_CORE0_WDT_IRQ		REG32(SCP_REG_BASE + 0x30030)
-#define SCP_CORE0_WDT_CFG		REG32(SCP_REG_BASE + 0x30034)
-#define   WDT_FREQ			33825 /* 0xFFFFF / 31 */
-#define   WDT_MAX_PERIOD		0xFFFFF /* 31 seconds */
-#define   WDT_PERIOD(ms)		(WDT_FREQ * (ms) / 1000)
-#define   WDT_EN			BIT(31)
-#define SCP_CORE0_WDT_KICK		REG32(SCP_REG_BASE + 0x30038)
-#define SCP_CORE0_WDT_CUR_VAL		REG32(SCP_REG_BASE + 0x3003C)
-
-/* INTC */
-#define SCP_INTC_WORD(irq)		((irq) >> 5) /* word length = 2^5 */
-#define SCP_INTC_BIT(irq)		((irq) & 0x1F) /* bit shift =LSB[0:4] */
-#define SCP_INTC_GRP_COUNT		15
-#define SCP_INTC_GRP_GAP		4
-
-#define SCP_CORE0_INTC_IRQ_BASE		(SCP_REG_BASE + 0x32000)
-#define SCP_CORE0_INTC_IRQ_STA(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)]
-#define SCP_CORE0_INTC_IRQ_EN(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)]
-#define SCP_CORE0_INTC_IRQ_POL(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)]
-#define SCP_CORE0_INTC_IRQ_GRP(g, w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \
-			   ((g) << SCP_INTC_GRP_GAP))[(w)]
-#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \
-			   ((g) << SCP_INTC_GRP_GAP))[(w)]
-#define SCP_CORE0_INTC_SLP_WAKE_EN(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)]
-#define SCP_CORE0_INTC_IRQ_OUT		REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250)
-/* UART */
-#define SCP_CORE0_INTC_UART0_RX_IRQ	REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258)
-#define SCP_CORE0_INTC_UART1_RX_IRQ	REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C)
-#define SCP_CORE0_INTC_UART_RX_IRQ(n)	CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ)
-
-/* XGPT (general purpose timer) */
-#define NUM_TIMERS			6
-#define SCP_CORE0_TIMER_BASE(n)		(SCP_REG_BASE + 0x33000 + (0x10 * (n)))
-#define SCP_CORE0_TIMER_EN(n)		REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000)
-#define   TIMER_EN			BIT(0)
-#define   TIMER_CLK_SRC_32K		(0 << 4)
-#define   TIMER_CLK_SRC_26M		(1 << 4)
-#define   TIMER_CLK_SRC_BCLK		(2 << 4)
-#define   TIMER_CLK_SRC_MCLK		(3 << 4)
-#define   TIMER_CLK_SRC_MASK		(3 << 4)
-#define SCP_CORE0_TIMER_RST_VAL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004)
-#define SCP_CORE0_TIMER_CUR_VAL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008)
-#define SCP_CORE0_TIMER_IRQ_CTRL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C)
-#define   TIMER_IRQ_EN			BIT(0)
-#define   TIMER_IRQ_STATUS		BIT(4)
-#define   TIMER_IRQ_CLR			BIT(5)
-#define SCP_IRQ_TIMER(n)		CONCAT2(SCP_IRQ_TIMER, n)
-
-/* secure control */
-#define SCP_SEC_CTRL			REG32(SCP_REG_BASE + 0xA5000)
-#define   VREQ_SECURE_DIS		BIT(4)
-/* memory remap */
-#define SCP_R_REMAP_0X0123		REG32(SCP_REG_BASE + 0xA5060)
-#define SCP_R_REMAP_0X4567		REG32(SCP_REG_BASE + 0xA5064)
-#define SCP_R_REMAP_0X89AB		REG32(SCP_REG_BASE + 0xA5068)
-#define SCP_R_REMAP_0XCDEF		REG32(SCP_REG_BASE + 0xA506C)
-
-/* external address: AP */
-#define AP_REG_BASE			0x60000000 /* 0x10000000 remap to 0x6 */
-/* AP GPIO */
-#define AP_GPIO_BASE			(AP_REG_BASE + 0x5000)
-#define AP_GPIO_MODE11_SET		REG32(AP_GPIO_BASE + 0x03B4)
-#define AP_GPIO_MODE11_CLR		REG32(AP_GPIO_BASE + 0x03B8)
-#define AP_GPIO_MODE12_SET		REG32(AP_GPIO_BASE + 0x03C4)
-#define AP_GPIO_MODE12_CLR		REG32(AP_GPIO_BASE + 0x03C8)
-#define AP_GPIO_MODE20_SET		REG32(AP_GPIO_BASE + 0x0444)
-#define AP_GPIO_MODE20_CLR		REG32(AP_GPIO_BASE + 0x0448)
-
-#include "clock_regs.h"
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt_scp/rv32i_common/system.c b/chip/mt_scp/rv32i_common/system.c
deleted file mode 100644
index 0e12154f6d..0000000000
--- a/chip/mt_scp/rv32i_common/system.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System : hardware specific implementation */
-
-#include "csr.h"
-#include "memmap.h"
-#include "registers.h"
-#include "system.h"
-
-void system_pre_init(void)
-{
-	memmap_init();
-
-	/* enable CPU and platform low power CG */
-	/* enable CPU DCM */
-	set_csr(CSR_MCTREN, CSR_MCTREN_CG);
-
-	/* Disable jump (it has only RW) */
-	system_disable_jump();
-}
-
-void system_reset(int flags)
-{
-	while (1)
-		;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_INVAL;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "mtk";
-}
-
-const char *system_get_chip_name(void)
-{
-	/* Support only SCP_A for now */
-	return "scp_a";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
diff --git a/chip/mt_scp/rv32i_common/uart.c b/chip/mt_scp/rv32i_common/uart.c
deleted file mode 100644
index 35b4003c9f..0000000000
--- a/chip/mt_scp/rv32i_common/uart.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module */
-
-#include "csr.h"
-#include "system.h"
-#include "uart.h"
-#include "uart_regs.h"
-#include "util.h"
-
-/*
- * UARTN == 0, SCP UART0
- * UARTN == 1, SCP UART1
- * UARTN == 2, AP UART1
- */
-#define UARTN CONFIG_UART_CONSOLE
-#define UART_IDLE_WAIT_US 500
-#define UART_INTC_GROUP 12
-
-static uint8_t init_done, tx_started;
-
-void uart_init(void)
-{
-	const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
-	const uint32_t uart_clock = 26000000;
-	const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
-
-	uart_init_pinmux();
-
-	/* Clear FIFO */
-	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO
-		| UART_FCR_CLEAR_RCVR
-		| UART_FCR_CLEAR_XMIT;
-	/* Line control: parity none, 8 bit, 1 stop bit */
-	UART_LCR(UARTN) = UART_LCR_WLEN8;
-	/* For baud rate <= 115200 */
-	UART_HIGHSPEED(UARTN) = 0;
-
-	/* DLAB start */
-	UART_LCR(UARTN) |= UART_LCR_DLAB;
-	UART_DLL(UARTN) = div & 0xff;
-	UART_DLH(UARTN) = (div >> 8) & 0xff;
-	UART_LCR(UARTN) &= ~UART_LCR_DLAB;
-	/* DLAB end */
-
-	/* Enable received data interrupt */
-	UART_IER(UARTN) |= UART_IER_RDI;
-
-#if (UARTN < SCP_UART_COUNT)
-	task_enable_irq(UART_TX_IRQ(UARTN));
-	task_enable_irq(UART_RX_IRQ(UARTN));
-#endif
-
-	init_done = 1;
-}
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_flush(void)
-{
-	while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	return UART_LSR(UARTN) & UART_LSR_THRE;
-}
-
-int uart_rx_available(void)
-{
-	return UART_LSR(UARTN) & UART_LSR_DR;
-}
-
-void uart_write_char(char c)
-{
-	while (!uart_tx_ready())
-		;
-
-	UART_THR(UARTN) = c;
-}
-
-int uart_read_char(void)
-{
-	return UART_RBR(UARTN);
-}
-
-void uart_tx_start(void)
-{
-	tx_started = 1;
-	if (UART_IER(UARTN) & UART_IER_THRI)
-		return;
-	disable_sleep(SLEEP_MASK_UART);
-	UART_IER(UARTN) |= UART_IER_THRI;
-}
-
-void uart_tx_stop(void)
-{
-	/*
-	 * Workaround for b/157541273.
-	 * Don't unset the THRI flag unless we are in the UART ISR.
-	 *
-	 * Note:
-	 * MICAUSE denotes current INTC group number.
-	 */
-	if (in_interrupt_context() &&
-	    read_csr(CSR_VIC_MICAUSE) != UART_INTC_GROUP)
-		return;
-
-	tx_started = 0;
-	UART_IER(UARTN) &= ~UART_IER_THRI;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-static void uart_process(void)
-{
-	uart_process_input();
-	uart_process_output();
-}
-
-#if (UARTN < SCP_UART_COUNT)
-static void uart_irq_handler(void)
-{
-	extern volatile int ec_int;
-
-	switch (ec_int) {
-	case UART_TX_IRQ(UARTN):
-		uart_process();
-		task_clear_pending_irq(ec_int);
-		break;
-	case UART_RX_IRQ(UARTN):
-		uart_process();
-		SCP_CORE0_INTC_UART_RX_IRQ(UARTN) = BIT(0);
-		asm volatile ("fence.i" ::: "memory");
-		task_clear_pending_irq(ec_int);
-		break;
-	}
-}
-DECLARE_IRQ(UART_INTC_GROUP, uart_irq_handler, 0);
-#else
-
-#ifndef HAS_TASK_APUART
-#error "APUART task hasn't defined in ec.tasklist."
-#endif
-
-void uart_task(void)
-{
-	while (1) {
-		if (uart_rx_available() || tx_started)
-			uart_process();
-		else
-			task_wait_event(UART_IDLE_WAIT_US);
-	}
-}
-#endif
diff --git a/chip/mt_scp/rv32i_common/uart_regs.h b/chip/mt_scp/rv32i_common/uart_regs.h
deleted file mode 100644
index c88b9c758b..0000000000
--- a/chip/mt_scp/rv32i_common/uart_regs.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module registers */
-
-#ifndef __CROS_EC_UART_REGS_H
-#define __CROS_EC_UART_REGS_H
-
-#include "registers.h"
-
-/* Chip specific function for setting UART pinmux. */
-void uart_init_pinmux(void);
-
-/* DLAB (Divisor Latch Access Bit) == 0 */
-
-/* (Read) receiver buffer register */
-#define UART_RBR(n)			UART_REG(n, 0)
-/* (Write) transmitter holding register */
-#define UART_THR(n)			UART_REG(n, 0)
-/* (Write) interrupt enable register */
-#define UART_IER(n)			UART_REG(n, 1)
-#define   UART_IER_RDI			BIT(0) /* received data */
-#define   UART_IER_THRI			BIT(1) /* THR empty */
-#define   UART_IER_RLSI			BIT(2) /* receiver LSR change */
-#define   UART_IER_MSI			BIT(3) /* MSR change */
-/* (Read) interrupt identification register */
-#define UART_IIR(n)			UART_REG(n, 2)
-#define   UART_IIR_ID_MASK		0x0e
-#define   UART_IIR_MSI			0x00 /* modem status change */
-#define   UART_IIR_NO_INT		0x01 /* no int pending */
-#define   UART_IIR_THRI			0x02 /* THR empty */
-#define   UART_IIR_RDI			0x04 /* received data available */
-#define   UART_IIR_RLSI			0x06 /* line status change */
-/* (Write) FIFO control register */
-#define UART_FCR(n)			UART_REG(n, 2)
-#define   UART_FCR_ENABLE_FIFO		BIT(0) /* enable FIFO */
-#define   UART_FCR_CLEAR_RCVR		BIT(1) /* clear receive FIFO */
-#define   UART_FCR_CLEAR_XMIT		BIT(2) /* clear transmit FIFO */
-#define   UART_FCR_DMA_SELECT		BIT(3) /* select DMA mode */
-/* (Write) line control register */
-#define UART_LCR(n)			UART_REG(n, 3)
-#define   UART_LCR_WLEN5		0 /* word length 5 bits */
-#define   UART_LCR_WLEN6		1
-#define   UART_LCR_WLEN7		2
-#define   UART_LCR_WLEN8		3
-#define   UART_LCR_STOP			BIT(2) /* stop bits: 1bit, 2bits */
-#define   UART_LCR_PARITY		BIT(3) /* parity enable */
-#define   UART_LCR_EPAR			BIT(4) /* even parity */
-#define   UART_LCR_SPAR			BIT(5) /* stick parity */
-#define   UART_LCR_SBC			BIT(6) /* set break control */
-#define   UART_LCR_DLAB			BIT(7) /* divisor latch access */
-/* (Write) modem control register */
-#define UART_MCR(n)			UART_REG(n, 4)
-/* (Read) line status register */
-#define UART_LSR(n)			UART_REG(n, 5)
-#define   UART_LSR_DR			BIT(0) /* data ready */
-#define   UART_LSR_OE			BIT(1) /* overrun error */
-#define   UART_LSR_PE			BIT(2) /* parity error */
-#define   UART_LSR_FE			BIT(3) /* frame error */
-#define   UART_LSR_BI			BIT(4) /* break interrupt */
-#define   UART_LSR_THRE			BIT(5) /* THR empty */
-#define   UART_LSR_TEMT			BIT(6) /* THR empty, line idle */
-#define   UART_LSR_FIFOE		BIT(7) /* FIFO error */
-/* (Read) modem status register */
-#define UART_MSR(n)			UART_REG(n, 6)
-/* (Read/Write) scratch register */
-#define UART_SCR(n)			UART_REG(n, 7)
-
-/* DLAB == 1 */
-
-/* (Write) divisor latch */
-#define UART_DLL(n)			UART_REG(n, 0)
-#define UART_DLH(n)			UART_REG(n, 1)
-
-/* MTK extension */
-#define UART_HIGHSPEED(n)		UART_REG(n, 9)
-
-#endif /* __CROS_EC_UART_REGS_H */
diff --git a/chip/mt_scp/rv32i_common/video.h b/chip/mt_scp/rv32i_common/video.h
deleted file mode 100644
index e4538c4456..0000000000
--- a/chip/mt_scp/rv32i_common/video.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_VIDEO_H
-#define __CROS_EC_VIDEO_H
-
-#include "common.h"
-
-/*
- * Video decoder supported capability
- */
-#define VDEC_CAP_4K_DISABLED BIT(4)
-#define VDEC_CAP_MM21 BIT(5)
-#define VDEC_CAP_MT21C BIT(6)
-#define VDEC_CAP_H264_SLICE BIT(8)
-#define VDEC_CAP_VP8_FRAME BIT(9)
-#define VDEC_CAP_VP9_FRAME BIT(10)
-#define VDEC_CAP_IRQ_IN_SCP BIT(16)
-
-/*
- * Video encoder supported capability:
- * BIT(0): enable 4K
- */
-#define VENC_CAP_4K BIT(0)
-
-uint32_t video_get_enc_capability(void);
-uint32_t video_get_dec_capability(void);
-
-#endif /* #ifndef __CROS_EC_VIDEO_H */
diff --git a/chip/mt_scp/rv32i_common/watchdog.c b/chip/mt_scp/rv32i_common/watchdog.c
deleted file mode 100644
index 72ca5edad8..0000000000
--- a/chip/mt_scp/rv32i_common/watchdog.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "hooks.h"
-#include "registers.h"
-#include "watchdog.h"
-
-void watchdog_reload(void)
-{
-	SCP_CORE0_WDT_KICK = BIT(0);
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	const uint32_t timeout = WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS);
-
-	/* disable watchdog */
-	SCP_CORE0_WDT_CFG &= ~WDT_EN;
-	/* clear watchdog irq */
-	SCP_CORE0_WDT_IRQ |= BIT(0);
-	/* enable watchdog */
-	SCP_CORE0_WDT_CFG = WDT_EN | timeout;
-	/* reload watchdog */
-	watchdog_reload();
-
-	return EC_SUCCESS;
-}
diff --git a/chip/npcx/adc.c b/chip/npcx/adc.c
deleted file mode 100644
index ea16589d9b..0000000000
--- a/chip/npcx/adc.c
+++ /dev/null
@@ -1,390 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific ADC module for Chrome EC */
-
-#include "adc.h"
-#include "atomic.h"
-#include "clock.h"
-#include "clock_chip.h"
-#include "console.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Maximum time we allow for an ADC conversion */
-#define ADC_TIMEOUT_US            SECOND
-#define ADC_CLK                   2000000
-#define ADC_REGULAR_DLY           0x11
-#define ADC_REGULAR_ADCCNF2       0x8B07
-#define ADC_REGULAR_GENDLY        0x0100
-#define ADC_REGULAR_MEAST         0x0001
-
-/* ADC conversion mode */
-enum npcx_adc_conversion_mode {
-	ADC_CHN_CONVERSION_MODE   = 0,
-	ADC_SCAN_CONVERSION_MODE  = 1
-};
-
-/* Global variables */
-static volatile task_id_t task_waiting;
-
-struct mutex adc_lock;
-
-/**
- * Preset ADC operation clock.
- *
- * @param   none
- * @return  none
- * @notes   changed when initial or HOOK_FREQ_CHANGE command
- */
-void adc_freq_changed(void)
-{
-	uint8_t prescaler_divider    = 0;
-
-	/* Set clock prescaler divider to ADC module*/
-	prescaler_divider = (uint8_t)(clock_get_apb1_freq() / ADC_CLK);
-	if (prescaler_divider >= 1)
-		prescaler_divider = prescaler_divider - 1;
-	if (prescaler_divider > 0x3F)
-		prescaler_divider = 0x3F;
-
-	/* Set Core Clock Division Factor in order to obtain the ADC clock */
-	SET_FIELD(NPCX_ATCTL, NPCX_ATCTL_SCLKDIV_FIELD, prescaler_divider);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, adc_freq_changed, HOOK_PRIO_DEFAULT);
-
-/**
- * Flush an ADC sequencer and initiate a read.
- *
- * @param   input_ch    operation channel
- * @param   timeout		preset timeout
- * @return  TRUE/FALSE  success/fail
- * @notes   set SW-triggered interrupt conversion and one-shot mode in npcx chip
- */
-static int start_single_and_wait(enum npcx_adc_input_channel input_ch
-		, int timeout)
-{
-	int event;
-
-	task_waiting = task_get_current();
-
-	/* Stop ADC conversion first */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_STOP);
-
-	/* Set ADC conversion code to SW conversion mode */
-	SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-			ADC_CHN_CONVERSION_MODE);
-
-	/* Set conversion type to one-shot type */
-	CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
-
-	/* Update number of channel to be converted */
-	SET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD, input_ch);
-
-	/* Clear End-of-Conversion Event status */
-	SET_BIT(NPCX_ADCSTS, NPCX_ADCSTS_EOCEV);
-
-	/* Enable ADC End-of-Conversion Interrupt if applicable */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_INTECEN);
-
-	/* Start conversion */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
-
-	/* Wait for interrupt */
-	event = task_wait_event_mask(TASK_EVENT_ADC_DONE, timeout);
-
-	task_waiting = TASK_ID_INVALID;
-
-	return (event == TASK_EVENT_ADC_DONE);
-
-}
-
-static uint16_t repetitive_enabled;
-void npcx_set_adc_repetitive(enum npcx_adc_input_channel input_ch, int enable)
-{
-	mutex_lock(&adc_lock);
-
-	/* Stop ADC conversion */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_STOP);
-
-	if (enable) {
-		/* Forbid EC enter deep sleep during conversion. */
-		disable_sleep(SLEEP_MASK_ADC);
-		/* Turn on ADC */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCEN);
-		/* Set ADC conversion code to SW conversion mode */
-		SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-			  ADC_SCAN_CONVERSION_MODE);
-		/* Update number of channel to be converted */
-		SET_BIT(NPCX_ADCCS, input_ch);
-		/* Set conversion type to repetitive (runs continuously) */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
-		repetitive_enabled |= BIT(input_ch);
-
-		/* Start conversion */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
-	} else {
-		CLEAR_BIT(NPCX_ADCCS, input_ch);
-		repetitive_enabled &= ~BIT(input_ch);
-
-		if (!repetitive_enabled) {
-			/* Turn off ADC */
-			CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCEN);
-			/* Set ADC to one-shot mode */
-			CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
-			/* Allow ec enter deep sleep */
-			enable_sleep(SLEEP_MASK_ADC);
-		} else {
-			/* Start conversion again */
-			SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
-		}
-	}
-
-	mutex_unlock(&adc_lock);
-}
-
-/**
- * Return the ADC value from CHNDAT register directly.
- *
- * @param   input_ch    channel number
- * @return  ADC data
- */
-int adc_read_data(enum npcx_adc_input_channel input_ch)
-{
-	const struct adc_t *adc = adc_channels + input_ch;
-	int value;
-	uint16_t chn_data;
-
-	chn_data = NPCX_CHNDAT(adc->input_ch);
-	value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) *
-		 adc->factor_mul / adc->factor_div + adc->shift;
-	return value;
-}
-
-/**
- * Start a single conversion and return the result
- *
- * @param   ch    operation channel
- * @return  ADC converted voltage or error message
- */
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-	uint16_t chn_data;
-
-	mutex_lock(&adc_lock);
-
-	/* Forbid ec enter deep sleep during ADC conversion is proceeding. */
-	disable_sleep(SLEEP_MASK_ADC);
-
-	/* Turn on ADC */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCEN);
-
-	if (start_single_and_wait(adc->input_ch, ADC_TIMEOUT_US)) {
-		chn_data = NPCX_CHNDAT(adc->input_ch);
-		if ((adc->input_ch ==
-			GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD))
-			&& (IS_BIT_SET(chn_data,
-					NPCX_CHNDAT_NEW))) {
-			value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) *
-				adc->factor_mul / adc->factor_div + adc->shift;
-		} else {
-			value = ADC_READ_ERROR;
-		}
-	} else {
-		value = ADC_READ_ERROR;
-	}
-
-	if (!repetitive_enabled) {
-		/* Turn off ADC */
-		CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCEN);
-		/* Allow ec enter deep sleep */
-		enable_sleep(SLEEP_MASK_ADC);
-	} else {
-		/* Set ADC conversion code to SW conversion mode */
-		SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-		  ADC_SCAN_CONVERSION_MODE);
-		/* Set conversion type to repetitive (runs continuously) */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
-		/* Start conversion */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
-	}
-
-	mutex_unlock(&adc_lock);
-
-	return value;
-}
-
-/* Board should register these callbacks with npcx_adc_cfg_thresh_int(). */
-static void (*adc_thresh_irqs[NPCX_ADC_THRESH_CNT])(void);
-
-void npcx_adc_thresh_int_enable(int threshold_idx, int enable)
-{
-	uint16_t thrcts;
-
-	enable = !!enable;
-
-	if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) {
-		CPRINTS("Invalid ADC thresh index! (%d)",
-			threshold_idx);
-		return;
-	}
-	threshold_idx--; /* convert to 0-based */
-
-	/* avoid clearing other threshold status */
-	thrcts = NPCX_THRCTS & ~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0);
-
-	if (enable) {
-		/* clear threshold status */
-		SET_BIT(thrcts, threshold_idx);
-		/* set enable threshold status */
-		SET_BIT(thrcts, NPCX_THRCTS_THR1_IEN + threshold_idx);
-	} else {
-		CLEAR_BIT(thrcts, NPCX_THRCTS_THR1_IEN + threshold_idx);
-	}
-	NPCX_THRCTS = thrcts;
-}
-
-void npcx_adc_register_thresh_irq(int threshold_idx,
-				  const struct npcx_adc_thresh_t *thresh_cfg)
-{
-	int npcx_adc_ch;
-	int raw_val;
-	int mul;
-	int div;
-	int shift;
-
-	if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) {
-		CPRINTS("Invalid ADC thresh index! (%d)",
-			threshold_idx);
-		return;
-	}
-	npcx_adc_ch = adc_channels[thresh_cfg->adc_ch].input_ch;
-
-	if (!thresh_cfg->adc_thresh_cb) {
-		CPRINTS("No callback for ADC Threshold %d!",
-			threshold_idx);
-		return;
-	}
-
-	/* Fill in the table */
-	adc_thresh_irqs[threshold_idx-1] = thresh_cfg->adc_thresh_cb;
-
-	/* Select the channel */
-	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL,
-		  npcx_adc_ch);
-
-	if (thresh_cfg->lower_or_higher)
-		SET_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_L_H);
-	else
-		CLEAR_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_L_H);
-
-	/* Set the threshold value. */
-	mul = adc_channels[thresh_cfg->adc_ch].factor_mul;
-	div = adc_channels[thresh_cfg->adc_ch].factor_div;
-	shift = adc_channels[thresh_cfg->adc_ch].shift;
-
-	raw_val = (thresh_cfg->thresh_assert - shift) * div / mul;
-	CPRINTS("ADC THR%d: Setting THRVAL = %d, L_H: %d", threshold_idx,
-		raw_val, thresh_cfg->lower_or_higher);
-	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL,
-		  raw_val);
-
-#if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7
-	/* Disable deassertion threshold function */
-	CLEAR_BIT(NPCX_THR_DCTL(threshold_idx), NPCX_THR_DCTL_THRD_EN);
-#endif
-
-	/* Enable threshold detection */
-	SET_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THEN);
-}
-
-/**
- * ADC interrupt handler
- *
- * @param   none
- * @return  none
- * @notes   Only handle SW-triggered conversion in npcx chip
- */
-void adc_interrupt(void)
-{
-	int i;
-	uint16_t thrcts;
-
-	if (IS_BIT_SET(NPCX_ADCCNF, NPCX_ADCCNF_INTECEN) &&
-	    IS_BIT_SET(NPCX_ADCSTS, NPCX_ADCSTS_EOCEV)) {
-		/* Disable End-of-Conversion Interrupt */
-		CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_INTECEN);
-
-		/* Stop conversion for single-shot mode */
-		if (!repetitive_enabled)
-			SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_STOP);
-
-		/* Clear End-of-Conversion Event status */
-		SET_BIT(NPCX_ADCSTS, NPCX_ADCSTS_EOCEV);
-
-		/* Wake up the task which was waiting for the interrupt */
-		if (task_waiting != TASK_ID_INVALID)
-			task_set_event(task_waiting, TASK_EVENT_ADC_DONE);
-	}
-
-	for (i = NPCX_THRCTS_THR1_STS; i < NPCX_ADC_THRESH_CNT; i++) {
-		if (IS_BIT_SET(NPCX_THRCTS, NPCX_THRCTS_THR1_IEN + i) &&
-		    IS_BIT_SET(NPCX_THRCTS, i)) {
-			/* avoid clearing other threshold status */
-			thrcts = NPCX_THRCTS &
-					~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0);
-			/* Clear threshold status */
-			SET_BIT(thrcts, i);
-			NPCX_THRCTS = thrcts;
-			if (adc_thresh_irqs[i])
-				adc_thresh_irqs[i]();
-		}
-	}
-}
-DECLARE_IRQ(NPCX_IRQ_ADC, adc_interrupt, 4);
-
-/**
- * ADC initial.
- *
- * @param none
- * @return none
- */
-static void adc_init(void)
-{
-	/* Configure pins from GPIOs to ADCs */
-	gpio_config_module(MODULE_ADC, 1);
-
-	/* Enable ADC clock (bit4 mask = 0x10) */
-	clock_enable_peripheral(CGC_OFFSET_ADC, CGC_ADC_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Set Core Clock Division Factor in order to obtain the ADC clock */
-	adc_freq_changed();
-
-	/* Set regular speed */
-	SET_FIELD(NPCX_ATCTL, NPCX_ATCTL_DLY_FIELD, (ADC_REGULAR_DLY - 1));
-
-	/* Set the other ADC settings */
-	NPCX_ADCCNF2 = ADC_REGULAR_ADCCNF2;
-	NPCX_GENDLY = ADC_REGULAR_GENDLY;
-	NPCX_MEAST = ADC_REGULAR_MEAST;
-
-	task_waiting = TASK_ID_INVALID;
-
-	/* Enable IRQs */
-	task_enable_irq(NPCX_IRQ_ADC);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/npcx/adc_chip.h b/chip/npcx/adc_chip.h
deleted file mode 100644
index 300447df16..0000000000
--- a/chip/npcx/adc_chip.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-#include "common.h"
-
-/* Minimum and maximum values returned by raw ADC read. */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 1023
-#define ADC_MAX_VOLT 2816
-
-/* ADC input channel select */
-enum npcx_adc_input_channel {
-	NPCX_ADC_CH0 = 0,
-	NPCX_ADC_CH1,
-	NPCX_ADC_CH2,
-	NPCX_ADC_CH3,
-	NPCX_ADC_CH4,
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	NPCX_ADC_CH5,
-	NPCX_ADC_CH6,
-	NPCX_ADC_CH7,
-	NPCX_ADC_CH8,
-	NPCX_ADC_CH9,
-#endif
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	NPCX_ADC_CH10,
-	NPCX_ADC_CH11,
- #endif
-	NPCX_ADC_CH_COUNT
-};
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	enum npcx_adc_input_channel input_ch;
-	int factor_mul;
-	int factor_div;
-	int shift;
-};
-
-/*
- * Boards may configure a ADC channel for use with thershold interrupts.
- * The threshold levels may be set from 0 to ADC_MAX_VOLT inclusive.
- */
-struct npcx_adc_thresh_t {
-	/* The ADC channel to monitor to generate threshold interrupts. */
-	enum adc_channel adc_ch;
-
-	/* Called when the interrupt fires */
-	void (*adc_thresh_cb)(void);
-
-	/* If set, threshold event is asserted when <= threshold level */
-	int lower_or_higher;
-
-	/* Desired threshold level in mV to assert. */
-	int thresh_assert;
-};
-
-/**
- * Boards should call this function to register their threshold interrupt with
- * one of the threshold detectors. 'threshold_idx' is 1-based.
- *
- * @param threshold_idx - 1-based threshold detector index
- * @param thresh_cfg - Pointer to ADC threshold interrupt configuration
- */
-void npcx_adc_register_thresh_irq(int threshold_idx,
-				  const struct npcx_adc_thresh_t *thresh_cfg);
-
-/**
- * Configure an ADC channel for repetitive conversion.
- *
- * If you are using ADC threshold interrupts and the need is timing critical,
- * you will want to enable this on the ADC channels you have configured for
- * threshold interrupts.
- *
- * NOTE: Enabling this will prevent the EC from entering deep sleep and will
- * increase power consumption!
- *
- * @param input_ch - The ADC channel you wish to configure
- * @param enable   - 1 to enable, 0 to disable
- */
-void npcx_set_adc_repetitive(enum npcx_adc_input_channel input_ch, int enable);
-
-/**
- * Enable/Disable ADC threshold detector interrupt.
- *
- * @param threshold_idx - 1-based threshold detector index
- * @param enable         - 1 to enable, 0 to disable
- */
-void npcx_adc_thresh_int_enable(int threshold_idx, int enable);
-
-/**
- * Return the ADC value from CHNDAT register directly when the channel is
- * configured in the repetitive mode.
- *
- * @param   input_ch    channel number
- * @return  ADC data
- */
-int adc_read_data(enum npcx_adc_input_channel input_ch);
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/npcx/apm.c b/chip/npcx/apm.c
deleted file mode 100644
index 4ab64774c1..0000000000
--- a/chip/npcx/apm.c
+++ /dev/null
@@ -1,694 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific APM module for Chrome EC */
-
-#include "apm_chip.h"
-#include "common.h"
-#include "registers.h"
-#include "util.h"
-#include "wov_chip.h"
-
-static struct apm_config apm_conf;
-static struct apm_auto_gain_config	apm_gain_conf;
-
-
-static uint32_t apm_indirect_reg[][3] = {
-	{(NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038)},
-	{(NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050)},
-	{(NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060)}
-};
-
-#define APM_CNTRL_REG 0
-#define APM_DATA_REG 1
-
-/**
- * Reads data indirect register.
- *
- * @param   reg_offset    - Indirect register APM_MIX_REG, APM_ADC_AGC_REG or
- *                          APM_VAD_REG.
- * @param   indirect_addr - Indirect access address.
- * @return  The read data.
- */
-static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset,
-				      uint8_t indirect_addr)
-{
-	/* Set the indirect access address. */
-	SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_ADD, indirect_addr);
-
-	/* Read command. */
-	CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
-
-	/* Get the data. */
-	return REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]);
-}
-
-/**
- * Writes data indirect register.
- *
- * @param   reg_offset    - Indirect register APM_MIX_REG, APM_ADC_AGC_REG or
- *                          APM_VAD_REG.
- * @param   indirect_addr - Indirect access address.
- * @param   value         - Written value.
- * @return  None
- */
-static void apm_write_indirect_data(enum apm_indirect_reg_offset reg_offset,
-				uint8_t indirect_addr, uint8_t value)
-{
-	/* Set the data. */
-	REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]) = value;
-
-	/* Set the indirect access address. */
-	SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_ADD, indirect_addr);
-
-	/* Write command. */
-	SET_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
-	CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
-}
-
-/**
- * Sets the ADC DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_dmic_config_l(enum apm_dmic_rate rate)
-{
-	if (rate == APM_DMIC_RATE_0_75)
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			APM_DMIC_RATE_3_0);
-	else if (rate == APM_DMIC_RATE_1_2)
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			APM_DMIC_RATE_2_4);
-	else
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			rate);
-}
-
-/**
- * Sets VAD DMIC rate.
- *
- * @param   rate    - VAD DMIC rate
- *
- * @return  None
- */
-void apm_set_vad_dmic_rate_l(enum apm_dmic_rate rate)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG);
-
-	/* Set VAD_0 register. */
-	if (rate == APM_DMIC_RATE_0_75)
-		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ,
-				APM_DMIC_RATE_3_0);
-	else if (rate == APM_DMIC_RATE_1_2)
-		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ,
-			  APM_DMIC_RATE_2_4);
-	else
-		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ, rate);
-
-	apm_write_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG, vad_data);
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/**
- * Translates from ADC real value to frequency code
- *
- * @param   adc_freq_val   - ADC frequency.
- * @return  ADC frequency code, 0xFFFF in case of wrong value.
- */
-static enum apm_adc_frequency apm_adc_freq_val_2_code(uint32_t adc_freq_val)
-{
-	enum apm_adc_frequency freq_code;
-
-	switch (adc_freq_val) {
-	case 8000:
-		freq_code = APM_ADC_FREQ_8_000_KHZ;
-		break;
-	case 12000:
-		freq_code = APM_ADC_FREQ_12_000_KHZ;
-		break;
-	case 16000:
-		freq_code = APM_ADC_FREQ_16_000_KHZ;
-		break;
-	case 24000:
-		freq_code = APM_ADC_FREQ_24_000_KHZ;
-		break;
-	case 32000:
-		freq_code = APM_ADC_FREQ_32_000_KHZ;
-		break;
-	case 48000:
-		freq_code = APM_ADC_FREQ_48_000_KHZ;
-		break;
-	default:
-		freq_code = APM_ADC_FREQ_UNSUPPORTED;
-		break;
-	}
-
-	return freq_code;
-}
-
-/**
- * Initiate APM module local parameters..
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_init(void)
-{
-	apm_conf.adc_ram_dmic_rate = APM_DMIC_RATE_0_75;
-	apm_conf.adc_i2s_dmic_rate = APM_DMIC_RATE_3_0;
-	apm_conf.gain_coupling = APM_ADC_CHAN_GAINS_INDEPENDENT;
-	apm_conf.left_chan_gain = 0;
-	apm_conf.right_chan_gain = 0;
-
-	apm_gain_conf.stereo_enable	 = 0;
-	apm_gain_conf.agc_target	 = APM_ADC_MAX_TARGET_LEVEL_19_5;
-	apm_gain_conf.nois_gate_en	 = 0;
-	apm_gain_conf.nois_gate_thold = APM_MIN_NOISE_GET_THRESHOLD;
-	apm_gain_conf.hold_time	 = APM_HOLD_TIME_128;
-	apm_gain_conf.attack_time	 = APM_GAIN_RAMP_TIME_160;
-	apm_gain_conf.decay_time	 = APM_GAIN_RAMP_TIME_160;
-	apm_gain_conf.gain_max	 = APM_GAIN_VALUE_42_5;
-	apm_gain_conf.gain_min	 = APM_GAIN_VALUE_0_0;
-}
-
-/**
- * Enables/Disables APM  module.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_enable(int enable)
-{
-	if (enable) {
-		CLEAR_BIT(NPCX_APM_CR_APM, NPCX_APM_CR_APM_PD);
-
-		/* Work around that enable the AGC. */
-		SET_FIELD(NPCX_APM_CR_APM, NPCX_APM_CR_APM_AGC_DIS, 0x00);
-
-	} else
-		SET_BIT(NPCX_APM_CR_APM, NPCX_APM_CR_APM_PD);
-}
-
-/**
- * Enables/Disables voice activity detected interrupt.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  APM interrupt mode.
- */
-void apm_enable_vad_interrupt(int enable)
-{
-	wov_interrupt_enable(WOV_VAD_INT_INDX, enable);
-	wov_interrupt_enable(WOV_VAD_WAKE_INDX, enable);
-	if (enable)
-		CLEAR_BIT(NPCX_APM_IMR, NPCX_APM_IMR_VAD_DTC_MASK);
-	else
-		SET_BIT(NPCX_APM_IMR, NPCX_APM_IMR_VAD_DTC_MASK);
-}
-
-/**
- * Enable/Disable the WoV in the ADC.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_adc_wov_enable(int enable)
-{
-	if (enable) {
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00);
-	} else {
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03);
-	}
-}
-
-/**
- * Enables/Disables ADC.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_adc_enable(int enable)
-{
-	if (enable) {
-		CLEAR_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC);
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00);
-	} else {
-		SET_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC);
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03);
-	}
-}
-
-/**
- * sets the ADC frequency.
- *
- * @param   adc_freq    - ADC frequency.
- * @return  None
- */
-void apm_adc_set_freq(enum apm_adc_frequency adc_freq)
-{
-	SET_FIELD(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_FREQ, adc_freq);
-}
-
-/**
- * Configures the ADC.
- *
- * @param   hpf_enable  - High pass filter enabled flag, 1 means enable
- * @param   filter_mode - ADC wind noise filter mode.
- * @param   adc_freq    - ADC frequency.
- * @return  None
- */
-void apm_adc_config(int hpf_enable,
-		enum apm_adc_wind_noise_filter_mode filter_mode,
-		enum apm_adc_frequency adc_freq)
-{
-	if (hpf_enable)
-		SET_BIT(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_HPF);
-	else
-		CLEAR_BIT(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_HPF);
-
-	SET_FIELD(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_WNF, filter_mode);
-
-	SET_FIELD(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_FREQ, adc_freq);
-}
-
-/**
- * Enables/Disables Digital Microphone.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_dmic_enable(int enable)
-{
-	if (enable)
-		CLEAR_BIT(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_PD_DMIC);
-	else
-		SET_BIT(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_PD_DMIC);
-}
-
-/**
- * Sets the RAM ADC DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_ram_dmic_config(enum apm_dmic_rate rate)
-{
-	apm_conf.adc_ram_dmic_rate = rate;
-}
-
-/**
- * Gets the RAM ADC DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_ram_dmic_rate(void)
-{
-	return apm_conf.adc_ram_dmic_rate;
-}
-
-/**
- * Sets the ADC I2S DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_i2s_dmic_config(enum apm_dmic_rate rate)
-{
-	apm_conf.adc_i2s_dmic_rate = rate;
-}
-
-/**
- * Gets the ADC I2S DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_i2s_dmic_rate(void)
-{
-	return apm_conf.adc_i2s_dmic_rate;
-}
-/**
- * Configures Digital Mixer
- *
- * @param   mix_left  - Mixer left channel output selection on ADC path.
- * @param   mix_right - Mixer right channel output selection on ADC path.
- * @return  None
- */
-void apm_digital_mixer_config(enum apm_dig_mix mix_left,
-			      enum apm_dig_mix mix_right)
-{
-	uint8_t mix_2 = 0;
-
-	SET_FIELD(mix_2, NPCX_APM_MIX_2_AIADCL_SEL, mix_left);
-	SET_FIELD(mix_2, NPCX_APM_MIX_2_AIADCR_SEL, mix_right);
-
-	apm_write_indirect_data(APM_MIX_REG, APM_INDIRECT_MIX_2_REG, mix_2);
-}
-
-/**
- * Enables/Disables the VAD functionality.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_vad_enable(int enable)
-{
-	if (enable)
-		NPCX_APM_CR_VAD = 0x80;
-	else
-		NPCX_APM_CR_VAD = 0x00;
-}
-
-/**
- * Enables/Disables VAD ADC wakeup
- *
- * @param   enable - 1 enable, 0 disable.
- *
- * @return  None
- */
-void apm_vad_adc_wakeup_enable(int enable)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG);
-
-	if (enable)
-		SET_BIT(vad_data, NPCX_VAD_0_VAD_ADC_WAKEUP);
-	else
-		CLEAR_BIT(vad_data, NPCX_VAD_0_VAD_ADC_WAKEUP);
-
-	apm_write_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG, vad_data);
-}
-
-/**
- * Sets VAD DMIC rate.
- *
- * @param   rate    - VAD DMIC rate
- *
- * @return  None
- */
-void apm_set_vad_dmic_rate(enum apm_dmic_rate rate)
-{
-	apm_conf.vad_dmic_rate = rate;
-}
-
-/**
- * Gets VAD DMIC rate.
- *
- * @param   None
- *
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_vad_dmic_rate(void)
-{
-	return apm_conf.vad_dmic_rate;
-}
-
-/**
- * Sets VAD Input chanel.
- *
- * @param   chan_src                - Processed digital microphone channel
- *                                    selection.
- * @return  None
- */
-void apm_set_vad_input_channel(enum apm_vad_in_channel_src chan_src)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG);
-
-	SET_FIELD(vad_data, NPCX_VAD_0_VAD_INSEL, chan_src);
-
-	apm_write_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG, vad_data);
-}
-
-/**
- * Sets VAD sensitivity.
- *
- * @param   sensitivity_db - VAD sensitivity in db.
- * @return  None
- */
-void apm_set_vad_sensitivity(uint8_t sensitivity_db)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_1_REG);
-
-	SET_FIELD(vad_data, NPCX_VAD_1_VAD_POWER_SENS, sensitivity_db);
-
-	apm_write_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_1_REG, vad_data);
-}
-
-/**
- * Gets VAD sensitivity.
- *
- * @param   None.
- * @return  VAD sensitivity in db
- */
-uint8_t apm_get_vad_sensitivity(void)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_1_REG);
-
-	return GET_FIELD(vad_data, NPCX_VAD_1_VAD_POWER_SENS);
-}
-
-/**
- * Restarts VAD functionality.
- *
- * @param   None
- * @return  None
- */
-void apm_vad_restart(void)
-{
-	SET_BIT(NPCX_APM_CR_VAD_CMD, NPCX_APM_CR_VAD_CMD_VAD_RESTART);
-}
-
-/**
- * Restarts VAD functionality.
- *
- * @param   gain_coupling   - ADC digital gain coupling (independent or
- *                            rigth tracks left).
- * @param   left_chan_gain  - Left channel ADC digital gain programming value.
- * @param   right_chan_gain - Right channel ADC digital gain programming value.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling,
-		uint8_t left_chan_gain, uint8_t right_chan_gain)
-{
-	/* Check parameters validity. */
-	if ((left_chan_gain > 0x2B) || (right_chan_gain > 0x2B))
-		return EC_ERROR_INVAL;
-
-	/*
-	 * Store the parameters in order to use them in case the function
-	 * was called prioe calling to wov_set_mode.
-	 */
-	apm_conf.gain_coupling = gain_coupling;
-	apm_conf.left_chan_gain = left_chan_gain;
-	apm_conf.right_chan_gain = right_chan_gain;
-
-	/* Set gain coupling.*/
-	if (gain_coupling == APM_ADC_CHAN_GAINS_INDEPENDENT)
-		CLEAR_BIT(NPCX_APM_GCR_ADCL, NPCX_APM_GCR_ADCL_LRGID);
-	else
-		SET_BIT(NPCX_APM_GCR_ADCL, NPCX_APM_GCR_ADCL_LRGID);
-
-	/* set channels gains. */
-	SET_FIELD(NPCX_APM_GCR_ADCL, NPCX_APM_GCR_ADCL_GIDL, left_chan_gain);
-	SET_FIELD(NPCX_APM_GCR_ADCR, NPCX_APM_GCR_ADCR_GIDR, right_chan_gain);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_auto_gain_cntrl_enable(int enable)
-{
-	if (enable)
-		NPCX_APM_CR_ADC_AGC = 0x80;
-	else
-		NPCX_APM_CR_ADC_AGC = 0x00;
-}
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param   gain_cfg - struct of apm auto gain config
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list apm_adc_auto_gain_config(
-				struct apm_auto_gain_config *gain_cfg)
-{
-	uint8_t gain_data = 0;
-
-	/* Check parameters validity. */
-
-	if (gain_cfg->gain_min > gain_cfg->gain_max)
-		return EC_ERROR_INVAL;
-
-	/*
-	 * Store the parameters in order to use them in case the function
-	 * was called prioe calling to wov_set_mode.
-	 */
-	apm_gain_conf.stereo_enable = gain_cfg->stereo_enable;
-	apm_gain_conf.agc_target = gain_cfg->agc_target;
-	apm_gain_conf.nois_gate_en = gain_cfg->nois_gate_en;
-	apm_gain_conf.nois_gate_thold = gain_cfg->nois_gate_thold;
-	apm_gain_conf.hold_time = gain_cfg->hold_time;
-	apm_gain_conf.attack_time = gain_cfg->attack_time;
-	apm_gain_conf.decay_time = gain_cfg->decay_time;
-	apm_gain_conf.gain_max = gain_cfg->gain_max;
-	apm_gain_conf.gain_min = gain_cfg->gain_min;
-
-	/* Set the parameters. */
-
-	if (gain_cfg->stereo_enable)
-		CLEAR_BIT(gain_data, NPCX_ADC_AGC_0_AGC_STEREO);
-	else
-		SET_BIT(gain_data, NPCX_ADC_AGC_0_AGC_STEREO);
-
-	SET_FIELD(gain_data, NPCX_ADC_AGC_0_AGC_TARGET, gain_cfg->agc_target);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_0_REG,
-				gain_data);
-
-	gain_data = 0;
-
-	if (gain_cfg->nois_gate_en)
-		SET_BIT(gain_data, NPCX_ADC_AGC_1_NG_EN);
-	else
-		CLEAR_BIT(gain_data, NPCX_ADC_AGC_1_NG_EN);
-	SET_FIELD(gain_data, NPCX_ADC_AGC_1_NG_THR, gain_cfg->nois_gate_thold);
-	SET_FIELD(gain_data, NPCX_ADC_AGC_1_HOLD, gain_cfg->hold_time);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_1_REG,
-				gain_data);
-
-	gain_data = 0;
-
-	SET_FIELD(gain_data, NPCX_ADC_AGC_2_ATK, gain_cfg->attack_time);
-	SET_FIELD(gain_data, NPCX_ADC_AGC_2_DCY, gain_cfg->decay_time);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_2_REG,
-				gain_data);
-
-	gain_data = 0;
-
-	SET_FIELD(gain_data, NPCX_ADC_AGC_3_AGC_MAX, gain_cfg->gain_max);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_3_REG,
-				gain_data);
-
-	gain_data = 0;
-
-	SET_FIELD(gain_data, NPCX_ADC_AGC_4_AGC_MIN, gain_cfg->gain_min);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_4_REG,
-				gain_data);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Sets APM mode (enables & disables APN sub modules accordingly
- * to the APM mode).
- *
- * @param apm_mode - APM mode, DEFAULT, DETECTION, RECORD or INDEPENDENT modes.
- * @return  None
- */
-void apm_set_mode(enum wov_modes wov_mode)
-{
-	apm_enable(0);
-
-	switch (wov_mode) {
-	case WOV_MODE_OFF:
-		apm_enable_vad_interrupt(0);
-		apm_dmic_enable(0);
-		apm_adc_enable(0);
-		apm_vad_enable(0);
-		wov_apm_active(0);
-		break;
-
-	case WOV_MODE_VAD:
-		apm_clear_vad_detected_bit();
-		wov_apm_active(1);
-		apm_dmic_enable(1);
-		apm_adc_wov_enable(1);
-		apm_set_vad_dmic_rate_l(apm_conf.vad_dmic_rate);
-		apm_set_vad_sensitivity(wov_conf.sensitivity_db);
-		apm_enable_vad_interrupt(1);
-		apm_vad_restart();
-		apm_vad_enable(1);
-		break;
-
-	case WOV_MODE_RAM:
-	case WOV_MODE_I2S:
-	case WOV_MODE_RAM_AND_I2S:
-		wov_apm_active(1);
-		apm_vad_enable(0);
-		apm_enable_vad_interrupt(0);
-		if (wov_mode == WOV_MODE_RAM)
-			apm_set_adc_dmic_config_l(apm_conf.adc_ram_dmic_rate);
-		else
-			apm_set_adc_dmic_config_l(apm_conf.adc_i2s_dmic_rate);
-		apm_dmic_enable(1);
-		apm_adc_enable(1);
-		break;
-
-	default:
-		apm_set_vad_dmic_rate_l(APM_DMIC_RATE_1_0);
-		apm_set_adc_dmic_config_l(APM_DMIC_RATE_1_0);
-		apm_vad_enable(0);
-		apm_enable_vad_interrupt(0);
-		apm_dmic_enable(0);
-		apm_adc_enable(0);
-		wov_apm_active(0);
-		break;
-	}
-
-	apm_adc_gain_config(apm_conf.gain_coupling,
-				apm_conf.left_chan_gain,
-				apm_conf.right_chan_gain);
-
-	apm_adc_auto_gain_config(&apm_gain_conf);
-
-	apm_adc_set_freq(apm_adc_freq_val_2_code(wov_conf.sample_per_sec));
-
-	if (wov_mode != WOV_MODE_OFF)
-		apm_enable(1);
-}
-
-/**
- * Clears VAD detected bit in IFR register.
- *
- * @param   None
- * @return  None.
- */
-void apm_clear_vad_detected_bit(void)
-{
-	apm_vad_enable(0);
-
-	APM_CLEAR_VAD_INTERRUPT;
-}
diff --git a/chip/npcx/apm_chip.h b/chip/npcx/apm_chip.h
deleted file mode 100644
index ad62538374..0000000000
--- a/chip/npcx/apm_chip.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_APM_CHIP_H
-#define __CROS_EC_APM_CHIP_H
-
-#include "common.h"
-
-/* MIX indirect registers. */
-#define APM_INDIRECT_MIX_2_REG      0x02
-
-/* ADC_AGC indirect registers. */
-#define APM_INDIRECT_ADC_AGC_0_REG  0x00
-#define APM_INDIRECT_ADC_AGC_1_REG  0x01
-#define APM_INDIRECT_ADC_AGC_2_REG  0x02
-#define APM_INDIRECT_ADC_AGC_3_REG  0x03
-#define APM_INDIRECT_ADC_AGC_4_REG  0x04
-
-/* APM_VAD_REG indirect registers. */
-#define APM_INDIRECT_VAD_0_REG       0x00
-#define APM_INDIRECT_VAD_1_REG       0x01
-
-/* APM macros. */
-#define APM_IS_IRQ_PENDING    IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND)
-#define APM_IS_VOICE_ACTIVITY_DETECTED \
-	IS_BIT_SET(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
-#define APM_CLEAR_VAD_INTERRUPT    SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
-
-/* Indirect registers. */
-enum apm_indirect_reg_offset {
-	APM_MIX_REG = 0,
-	APM_ADC_AGC_REG,
-	APM_VAD_REG
-};
-
-/* ADC wind noise filter modes. */
-enum apm_adc_wind_noise_filter_mode {
-	APM_ADC_WIND_NOISE_FILTER_INACTIVE = 0,
-	APM_ADC_WIND_NOISE_FILTER_MODE_1_ACTIVE,
-	APM_ADC_WIND_NOISE_FILTER_MODE_2_ACTIVE,
-	APM_ADC_WIND_NOISE_FILTER_MODE_3_ACTIVE,
-};
-
-/* ADC frequency. */
-enum apm_adc_frequency {
-	APM_ADC_FREQ_8_000_KHZ = 0x00,
-	APM_ADC_FREQ_11_025_KHZ,
-	APM_ADC_FREQ_12_000_KHZ,
-	APM_ADC_FREQ_16_000_KHZ,
-	APM_ADC_FREQ_22_050_KHZ,
-	APM_ADC_FREQ_24_000_KHZ,
-	APM_ADC_FREQ_32_000_KHZ,
-	APM_ADC_FREQ_44_100_KHZ,
-	APM_ADC_FREQ_48_000_KHZ,
-	APM_ADC_FREQ_UNSUPPORTED = 0x0F
-};
-
-/* DMIC source. */
-enum apm_dmic_src {
-	APM_CURRENT_DMIC_CHANNEL = 0x01, /* Current channel, left or rigth. */
-	APM_AVERAGE_DMIC_CHANNEL = 0x02  /* Average between left & right.   */
-};
-
-/* ADC digital microphone rate. */
-enum apm_dmic_rate {
-	/* 3.0, 2.4 & 1.0 must be 0, 1 & 2 respectively */
-	APM_DMIC_RATE_3_0 = 0,   /* 3.0 -3.25 MHz (default). */
-	APM_DMIC_RATE_2_4,       /* 2.4 -2.6 MHz.            */
-	APM_DMIC_RATE_1_0,       /* 1.0 -1.08 MHz.           */
-	APM_DMIC_RATE_1_2,       /* 1.2 MHz.                        */
-	APM_DMIC_RATE_0_75       /* 750 KHz.                 */
-};
-
-/* Digitla mixer output. */
-enum apm_dig_mix {
-	APM_OUT_MIX_NORMAL_INPUT = 0,    /* Default. */
-	APM_OUT_MIX_CROSS_INPUT,
-	APM_OUT_MIX_MIXED_INPUT,
-	APM_OUT_MIX_NO_INPUT
-};
-
-/* VAD Input Channel Selection */
-enum apm_vad_in_channel_src {
-	APM_IN_LEFT = 0,
-	APM_IN_RIGHT,
-	APM_IN_AVERAGE_LEFT_RIGHT,
-	APM_IN_RESERVED
-};
-
-/* ADC digital gain coupling. */
-enum apm_adc_gain_coupling {
-	APM_ADC_CHAN_GAINS_INDEPENDENT = 0,
-	APM_ADC_RIGHT_CHAN_GAIN_TRACKS_LEFT
-};
-
-/* ADC target output level. */
-enum apm_adc_target_out_level {
-	APM_ADC_MAX_TARGET_LEVEL = 0,
-	APM_ADC_MAX_TARGET_LEVEL_1_5,
-	APM_ADC_MAX_TARGET_LEVEL_3_0,
-	APM_ADC_MAX_TARGET_LEVEL_4_5,
-	APM_ADC_MAX_TARGET_LEVEL_6_0,
-	APM_ADC_MAX_TARGET_LEVEL_7_5,
-	APM_ADC_MAX_TARGET_LEVEL_9_0,
-	APM_ADC_MAX_TARGET_LEVEL_10_5,
-	APM_ADC_MAX_TARGET_LEVEL_12_0,
-	APM_ADC_MAX_TARGET_LEVEL_13_5,
-	APM_ADC_MAX_TARGET_LEVEL_15_0,
-	APM_ADC_MAX_TARGET_LEVEL_16_5,
-	APM_ADC_MAX_TARGET_LEVEL_18_0,
-	APM_ADC_MAX_TARGET_LEVEL_19_5, /* Default. */
-	APM_ADC_MAX_TARGET_LEVEL_21_0,
-	APM_ADC_MAX_TARGET_LEVEL_22_5
-};
-
-/* Noise gate threshold values. */
-enum apm_noise_gate_threshold {
-	APM_MIN_NOISE_GET_THRESHOLD = 0,
-	APM_MIN_NOISE_GET_THRESHOLD_6,
-	APM_MIN_NOISE_GET_THRESHOLD_12,
-	APM_MIN_NOISE_GET_THRESHOLD_18,
-	APM_MIN_NOISE_GET_THRESHOLD_24,
-	APM_MIN_NOISE_GET_THRESHOLD_30,
-	APM_MIN_NOISE_GET_THRESHOLD_36,
-	APM_MIN_NOISE_GET_THRESHOLD_42
-};
-
-/* Hold time in msec before starting AGC adjustment to the TARGET value. */
-enum apm_agc_adj_hold_time {
-	APM_HOLD_TIME_0 = 0,
-	APM_HOLD_TIME_2,
-	APM_HOLD_TIME_4,
-	APM_HOLD_TIME_8,
-	APM_HOLD_TIME_16,
-	APM_HOLD_TIME_32,
-	APM_HOLD_TIME_64,
-	APM_HOLD_TIME_128, /* Default. */
-	APM_HOLD_TIME_256,
-	APM_HOLD_TIME_512,
-	APM_HOLD_TIME_1024,
-	APM_HOLD_TIME_2048,
-	APM_HOLD_TIME_4096,
-	APM_HOLD_TIME_8192,
-	APM_HOLD_TIME_16384,
-	APM_HOLD_TIME_32768
-};
-
-/* Attack time in msec - gain ramp down. */
-enum apm_gain_ramp_time {
-	APM_GAIN_RAMP_TIME_32 = 0,
-	APM_GAIN_RAMP_TIME_64,
-	APM_GAIN_RAMP_TIME_96,
-	APM_GAIN_RAMP_TIME_128,
-	APM_GAIN_RAMP_TIME_160, /* Default. */
-	APM_GAIN_RAMP_TIME_192,
-	APM_GAIN_RAMP_TIME_224,
-	APM_GAIN_RAMP_TIME_256,
-	APM_GAIN_RAMP_TIME_288,
-	APM_GAIN_RAMP_TIME_320,
-	APM_GAIN_RAMP_TIME_352,
-	APM_GAIN_RAMP_TIME_384,
-	APM_GAIN_RAMP_TIME_416,
-	APM_GAIN_RAMP_TIME_448,
-	APM_GAIN_RAMP_TIME_480,
-	APM_GAIN_RAMP_TIME_512
-};
-
-/* Minimum and Maximum gain values. */
-enum apm_gain_values {
-	APM_GAIN_VALUE_0_0 = 0,
-	APM_GAIN_VALUE_1_5,
-	APM_GAIN_VALUE_3_0,
-	APM_GAIN_VALUE_4_5,
-	APM_GAIN_VALUE_6_0,
-	APM_GAIN_VALUE_7_5,
-	APM_GAIN_VALUE_9_0,
-	APM_GAIN_VALUE_10_5,
-	APM_GAIN_VALUE_12_0,
-	APM_GAIN_VALUE_13_5,
-	APM_GAIN_VALUE_15_0,
-	APM_GAIN_VALUE_16_5,
-	APM_GAIN_VALUE_18_0,
-	APM_GAIN_VALUE_19_5,
-	APM_GAIN_VALUE_21_0,
-	APM_GAIN_VALUE_22_5,
-	APM_GAIN_VALUE_23_0_1ST,
-	APM_GAIN_VALUE_23_0_2ND,
-	APM_GAIN_VALUE_23_0_3RD,
-	APM_GAIN_VALUE_24_5,
-	APM_GAIN_VALUE_26_0,
-	APM_GAIN_VALUE_27_5,
-	APM_GAIN_VALUE_29_0,
-	APM_GAIN_VALUE_30_5,
-	APM_GAIN_VALUE_32_0,
-	APM_GAIN_VALUE_33_5,
-	APM_GAIN_VALUE_35_0,
-	APM_GAIN_VALUE_36_5,
-	APM_GAIN_VALUE_38_0,
-	APM_GAIN_VALUE_39_5,
-	APM_GAIN_VALUE_41_0,
-	APM_GAIN_VALUE_42_5
-};
-
-/* ADC Audio Data Word Length */
-enum apm_adc_data_length {
-	APM_ADC_DATA_LEN_16_BITS = 0x00,
-	APM_ADC_DATA_LEN_18_BITS,
-	APM_ADC_DATA_LEN_20_BITS,
-	APM_ADC_DATA_LEN_24_BITS
-};
-
-struct apm_config {
-	enum apm_dmic_rate vad_dmic_rate;
-	enum apm_dmic_rate adc_ram_dmic_rate;
-	enum apm_dmic_rate adc_i2s_dmic_rate;
-	enum apm_adc_gain_coupling gain_coupling;
-	uint8_t left_chan_gain;
-	uint8_t right_chan_gain;
-};
-struct apm_auto_gain_config {
-	int stereo_enable;
-	enum apm_adc_target_out_level agc_target;
-	int nois_gate_en;
-	enum apm_noise_gate_threshold nois_gate_thold;
-	enum apm_agc_adj_hold_time hold_time;
-	enum apm_gain_ramp_time attack_time;
-	enum apm_gain_ramp_time decay_time;
-	enum apm_gain_values gain_max;
-	enum apm_gain_values gain_min;
-};
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-enum wov_modes;
-/**
- * Sets the RAM ADC DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_ram_dmic_config(enum apm_dmic_rate rate);
-
-/**
- * Gets the RAM ADC DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_ram_dmic_rate(void);
-
-/**
- * Sets the ADC I2S DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_i2s_dmic_config(enum apm_dmic_rate rate);
-
-/**
- * Gets the ADC I2S DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_i2s_dmic_rate(void);
-
-/**
- * Sets VAD DMIC rate.
- *
- * @param   rate    - VAD DMIC rate
- *
- * @return  None
- */
-void apm_set_vad_dmic_rate(enum apm_dmic_rate rate);
-
-/**
- * Gets VAD DMIC rate.
- *
- * @param   None
- *
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_vad_dmic_rate(void);
-
-/**
- * Gets the ADC DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_dmic_rate(void);
-
-/**
- * Initiate APM module local parameters..
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_init(void);
-
-/**
- * Enables/Disables APM  module.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_enable(int enable);
-
-/**
- * Enables/Disables voice activity detected interrupt.
- *
- * @param   enable - enabled flag, true means enable
- * @return  APM interrupt mode.
- */
-void apm_enable_vad_interrupt(int enable);
-
-/**
- * Enables/Disables ADC.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_adc_enable(int enable);
-
-/**
- * sets the ADC frequency.
- *
- * @param   adc_freq    - ADC frequency.
- * @return  None
- */
-void apm_adc_set_freq(enum apm_adc_frequency adc_freq);
-
-/**
- * Configures the ADC.
- *
- * @param   hpf_enable  - High pass filter enabled flag, true means enable
- * @param   filter_mode - ADC wind noise filter mode.
- * @param   adc_freq    - ADC frequency.
- * @return  None
- */
-void apm_adc_config(int hpf_enable,
-		enum apm_adc_wind_noise_filter_mode filter_mode,
-		enum apm_adc_frequency adc_freq);
-
-/**
- * Enables/Disables Digital Microphone.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_dmic_enable(int enable);
-
-/**
- * Configures Digital Microphone.
- *
- * @param   mix_left  - Mixer left channel output selection on ADC path.
- * @param   mix_right - Mixer right channel output selection on ADC path.
- * @return  None
- */
-void apm_digital_mixer_config(enum apm_dig_mix mix_left,
-		enum apm_dig_mix mix_right);
-
-/**
- * Enables/Disables the VAD functionality.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_vad_enable(int enable);
-
-/**
- * Enables/Disables VAD ADC wakeup
- *
- * @param   enable - true enable, false disable.
- *
- * @return  None
- */
-void apm_vad_adc_wakeup_enable(int enable);
-
-/**
- * Sets VAD Input chanel.
- *
- * @param   chan_src	- Processed digital microphone channel
- *			  selection.
- * @return  None
- */
-void apm_set_vad_input_channel(enum apm_vad_in_channel_src chan_src);
-
-/**
- * Sets VAD sensitivity.
- *
- * @param   sensitivity_db - VAD sensitivity in db.
- * @return  None
- */
-void apm_set_vad_sensitivity(uint8_t sensitivity_db);
-
-/**
- * Gets VAD sensitivity.
- *
- * @param   None.
- * @return  VAD sensitivity in db
- */
-uint8_t apm_get_vad_sensitivity(void);
-
-/**
- * Restarts VAD functionality.
- *
- * @param   None
- * @return  None
- */
-void apm_vad_restart(void);
-
-/**
- * Restarts VAD functionality.
- *
- * @param   gain_coupling   - ADC digital gain coupling (independent or
- *                            rigth tracks left).
- * @param   left_chan_gain  - Left channel ADC digital gain programming value.
- * @param   right_chan_gain - Right channel ADC digital gain programming value.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling,
-			uint8_t left_chan_gain, uint8_t right_chan_gain);
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_auto_gain_cntrl_enable(int enable);
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param   gain_cfg - struct of apm auto gain config
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list apm_adc_auto_gain_config(
-				struct apm_auto_gain_config *gain_cfg);
-
-/**
- * Sets APM mode (enables & disables APN sub modules accordingly
- * to the APM mode).
- *
- * @param apm_mode - APM mode, DEFAULT, DETECTION, RECORD or INDEPENDENT modes.
- * @return  None
- */
-void apm_set_mode(enum wov_modes wov_mode);
-
-/**
- * Clears VAD detected bit in IFR register.
- *
- * @param   None
- * @return  None.
- */
-void apm_clear_vad_detected_bit(void);
-
-#endif /* __CROS_EC_APM_CHIP_H */
diff --git a/chip/npcx/audio_codec_dmic.c b/chip/npcx/audio_codec_dmic.c
deleted file mode 100644
index e242a8b2d2..0000000000
--- a/chip/npcx/audio_codec_dmic.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "ec_commands.h"
-#include "wov_chip.h"
-
-int audio_codec_dmic_get_max_gain(uint8_t *gain)
-{
-	*gain = 31;
-	return EC_SUCCESS;
-}
-
-int audio_codec_dmic_set_gain_idx(uint8_t channel, uint8_t gain)
-{
-	int left_gain, right_gain;
-
-	wov_get_gain(&left_gain, &right_gain);
-
-	switch (channel) {
-	case EC_CODEC_DMIC_CHANNEL_0:
-		left_gain = gain;
-		break;
-	case EC_CODEC_DMIC_CHANNEL_1:
-		right_gain = gain;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	wov_set_gain(left_gain, right_gain);
-	return EC_SUCCESS;
-}
-
-int audio_codec_dmic_get_gain_idx(uint8_t channel, uint8_t *gain)
-{
-	int left_gain, right_gain;
-
-	wov_get_gain(&left_gain, &right_gain);
-
-	switch (channel) {
-	case EC_CODEC_DMIC_CHANNEL_0:
-		*gain = left_gain;
-		break;
-	case EC_CODEC_DMIC_CHANNEL_1:
-		*gain = right_gain;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/chip/npcx/audio_codec_i2s_rx.c b/chip/npcx/audio_codec_i2s_rx.c
deleted file mode 100644
index 12c4173048..0000000000
--- a/chip/npcx/audio_codec_i2s_rx.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "ec_commands.h"
-#include "wov_chip.h"
-
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
-
-int audio_codec_i2s_rx_enable(void)
-{
-	/*
-	 * The mic source and sample rate don't need to be set each time
-	 * an i2s stream is started, but the audio codec does not
-	 * contain a method to select these as they must be the values
-	 * set below for proper i2s operation. Since the default values
-	 * set in wov.c are different than what's required, they are set
-	 * each time an i2s stream is started.
-	 */
-	wov_set_mic_source(WOV_SRC_STEREO);
-
-	/* Mode must be WOV_MODE_OFF to change sample rate */
-	wov_set_mode(WOV_MODE_OFF);
-	wov_set_sample_rate(48000);
-
-	return wov_set_mode(WOV_MODE_I2S);
-}
-
-int audio_codec_i2s_rx_disable(void)
-{
-	return wov_set_mode(WOV_MODE_OFF);
-}
-
-int audio_codec_i2s_rx_set_sample_depth(uint8_t depth)
-{
-	int bits_num;
-
-	if (depth == EC_CODEC_I2S_RX_SAMPLE_DEPTH_24)
-		bits_num = 24;
-	else
-		bits_num = 16;
-
-	/* Sample depth can only be changed when mode is WOV_MODE_OFF */
-	wov_set_mode(WOV_MODE_OFF);
-	return wov_set_sample_depth(bits_num);
-}
-
-int audio_codec_i2s_rx_set_daifmt(uint8_t daifmt)
-{
-	enum wov_dai_format fmt = WOV_DAI_FMT_I2S;
-
-	switch (daifmt) {
-	case EC_CODEC_I2S_RX_DAIFMT_I2S:
-		fmt = WOV_DAI_FMT_I2S;
-		break;
-	case EC_CODEC_I2S_RX_DAIFMT_RIGHT_J:
-		fmt = WOV_DAI_FMT_RIGHT_J;
-		break;
-	case EC_CODEC_I2S_RX_DAIFMT_LEFT_J:
-		fmt = WOV_DAI_FMT_LEFT_J;
-		break;
-	}
-
-	/* To change mode setting it must be set to WOV_MODE_OFF */
-	wov_set_mode(WOV_MODE_OFF);
-	wov_set_i2s_fmt(fmt);
-
-	return EC_SUCCESS;
-}
-
-int audio_codec_i2s_rx_set_bclk(uint32_t bclk)
-{
-	/* To change bclk setting it must be set to WOV_MODE_OFF */
-	wov_set_mode(WOV_MODE_OFF);
-	wov_set_i2s_bclk(bclk);
-	return EC_SUCCESS;
-}
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
deleted file mode 100644
index 4be1b2994f..0000000000
--- a/chip/npcx/build.mk
+++ /dev/null
@@ -1,92 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# NPCX chip specific files build
-#
-
-# NPCX SoC has a Cortex-M4F ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# Assign default CHIP_FAMILY as npcx5 for old boards used npcx5 series
-ifeq ($(CHIP_FAMILY),)
-CHIP_FAMILY:=npcx5
-endif
-
-# Required chip modules
-chip-y=header.o clock.o gpio.o hwtimer.o system.o uart.o uartn.o sib.o
-chip-y+=system-$(CHIP_FAMILY).o
-chip-y+=gpio-$(CHIP_FAMILY).o
-
-# Optional chip modules
-chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_AUDIO_CODEC)+=apm.o wov.o
-chip-$(CONFIG_AUDIO_CODEC_DMIC)+=audio_codec_dmic.o
-chip-$(CONFIG_AUDIO_CODEC_I2S_RX)+=audio_codec_i2s_rx.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o
-chip-$(CONFIG_HOSTCMD_X86)+=lpc.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
-chip-$(CONFIG_PECI)+=peci.o
-chip-$(CONFIG_HOSTCMD_SHI)+=shi.o
-chip-$(CONFIG_CEC)+=cec.o
-# pwm functions are implemented with the fan functions
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-
-chip-$(CONFIG_PS2)+=ps2.o
-# Only npcx9 or later chip family can support LCT module
-ifneq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),npcx5 npcx7))
-chip-y+=lct.o
-endif
-
-chip-$(CONFIG_SHA256_HW_ACCELERATE)+=sha256_chip.o
-
-# spi monitor program fw for openocd and UUT(UART Update Tool)
-npcx-monitor-fw=chip/npcx/spiflashfw/npcx_monitor
-npcx-monitor-fw-bin=${out}/$(npcx-monitor-fw).bin
-PROJECT_EXTRA+=${npcx-monitor-fw-bin}
-# Monitor header is only used for UUT which is not supported on npcx5.
-ifneq "$(CHIP_FAMILY)" "npcx5"
-npcx-monitor-hdr=chip/npcx/spiflashfw/monitor_hdr
-npcx-monitor-hdr-ro-bin=${out}/$(npcx-monitor-hdr)_ro.bin
-npcx-monitor-hdr-rw-bin=${out}/$(npcx-monitor-hdr)_rw.bin
-PROJECT_EXTRA+=${npcx-monitor-hdr-ro-bin} ${npcx-monitor-hdr-rw-bin}
-endif
-
-# ECST tool is for filling the header used by booter of npcx EC
-show_esct_cmd=$(if $(V),,echo '  ECST   ' $(subst $(out)/,,$@) ; )
-
-# Get the firmware length from the mapfile.  This can differ from the file
-# size when the CONFIG_CHIP_INIT_ROM_REGION is used. Note that the -fwlen
-# parameter for the ecst utility must be in hex.
-cmd_fwlen=$(shell awk '\
-  /__flash_used =/ {flash_used = strtonum($$1)} \
-  END {printf ("%x", flash_used)}' $(1))
-
-# ECST options for header
-bld_ecst=${out}/util/ecst -chip $(CHIP_VARIANT) \
-	-usearmrst -mode bt -ph -i $(1) -o $(2) -nohcrc -nofcrc -flashsize 8 \
-	-fwlen $(call cmd_fwlen, $(patsubst %.flat,%.map,$(2))) \
-	-spimaxclk 50 -spireadmode dual 1> /dev/null
-
-# Replace original one with the flat file including header
-moveflat=mv -f $(1) $(2)
-
-# Commands for ECST
-cmd_ecst=$(show_esct_cmd)$(call moveflat,$@,$@.tmp);$(call bld_ecst,$@.tmp,$@)
-
-# Commands to append npcx header in ec.RO.flat
-cmd_org_ec_elf_to_flat = $(OBJCOPY) --set-section-flags .roshared=share \
-                         -O binary $(patsubst %.flat,%.elf,$@) $@
-cmd_npcx_ro_elf_to_flat=$(cmd_org_ec_elf_to_flat);$(cmd_ecst)
-cmd_ec_elf_to_flat = $(if $(filter $(out)/RO/ec.RO.flat, $@), \
-                     $(cmd_npcx_ro_elf_to_flat), $(cmd_org_ec_elf_to_flat) )
diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c
deleted file mode 100644
index ebaefa551a..0000000000
--- a/chip/npcx/cec.c
+++ /dev/null
@@ -1,1040 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "cec.h"
-#include "clock_chip.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "mkbp_event.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#if !(DEBUG_CEC)
-#define CPRINTF(...)
-#define CPRINTS(...)
-#else
-#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args)
-#endif
-
-/* Time in us to timer clock ticks */
-#define APB1_TICKS(t) ((t) * apb1_freq_div_10k / 100)
-#if DEBUG_CEC
-/* Timer clock ticks to us */
-#define APB1_US(ticks) (100*(ticks)/apb1_freq_div_10k)
-#endif
-
-/* Notification from interrupt to CEC task that data has been received */
-#define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM_BIT(0)
-
-/* CEC broadcast address. Also the highest possible CEC address */
-#define CEC_BROADCAST_ADDR 15
-
-/* Address to indicate that no logical address has been set */
-#define CEC_UNREGISTERED_ADDR 255
-
-/*
- * The CEC specification requires at least one and a maximum of
- * five resends attempts
- */
-#define CEC_MAX_RESENDS 5
-
-/*
- * Free time timing (us). Our free-time is calculated from the end of
- * the last bit (not from the start). We compensate by having one
- * free-time period less than in the spec.
- */
-#define NOMINAL_BIT_TICKS APB1_TICKS(2400)
- /* Resend */
-#define FREE_TIME_RS_TICKS (2 * (NOMINAL_BIT_TICKS))
-/* New initiator */
-#define FREE_TIME_NI_TICKS (4 * (NOMINAL_BIT_TICKS))
-/* Present initiator */
-#define FREE_TIME_PI_TICKS (6 * (NOMINAL_BIT_TICKS))
-
-/* Start bit timing */
-#define START_BIT_LOW_TICKS		APB1_TICKS(3700)
-#define START_BIT_MIN_LOW_TICKS		APB1_TICKS(3500)
-#define START_BIT_MAX_LOW_TICKS		APB1_TICKS(3900)
-#define START_BIT_HIGH_TICKS		APB1_TICKS(800)
-#define START_BIT_MIN_DURATION_TICKS	APB1_TICKS(4300)
-#define START_BIT_MAX_DURATION_TICKS	APB1_TICKS(5700)
-
-/* Data bit timing */
-#define DATA_ZERO_LOW_TICKS		APB1_TICKS(1500)
-#define DATA_ZERO_MIN_LOW_TICKS		APB1_TICKS(1300)
-#define DATA_ZERO_MAX_LOW_TICKS		APB1_TICKS(1700)
-#define DATA_ZERO_HIGH_TICKS		APB1_TICKS(900)
-#define DATA_ZERO_MIN_DURATION_TICKS	APB1_TICKS(2050)
-#define DATA_ZERO_MAX_DURATION_TICKS	APB1_TICKS(2750)
-
-#define DATA_ONE_LOW_TICKS		APB1_TICKS(600)
-#define DATA_ONE_MIN_LOW_TICKS		APB1_TICKS(400)
-#define DATA_ONE_MAX_LOW_TICKS		APB1_TICKS(800)
-#define DATA_ONE_HIGH_TICKS		APB1_TICKS(1800)
-#define DATA_ONE_MIN_DURATION_TICKS	APB1_TICKS(2050)
-#define DATA_ONE_MAX_DURATION_TICKS	APB1_TICKS(2750)
-
-/* Time from low that it should be safe to sample an ACK */
-#define NOMINAL_SAMPLE_TIME_TICKS APB1_TICKS(1050)
-
-#define DATA_TIME(type, data) ((data) ? (DATA_ONE_ ## type ## _TICKS) : \
-					(DATA_ZERO_ ## type ## _TICKS))
-#define DATA_HIGH(data) DATA_TIME(HIGH, data)
-#define DATA_LOW(data) DATA_TIME(LOW, data)
-
-/*
- * Number of short pulses seen before the debounce logic goes into ignoring
- * the bus for DEBOUNCE_WAIT_LONG instead of DEBOUNCE_WAIT_SHORT
- */
-#define DEBOUNCE_CUTOFF 3
-
-/* The limit how short a start-bit can be to trigger debounce logic */
-#define DEBOUNCE_LIMIT_TICKS APB1_TICKS(200)
-/* The time we ignore the bus for the first three debounce cases */
-#define DEBOUNCE_WAIT_SHORT_TICKS APB1_TICKS(100)
-/* The time we ignore the bus after the three initial debounce cases */
-#define DEBOUNCE_WAIT_LONG_TICKS APB1_TICKS(500)
-
-/*
- * The variance in timing we allow outside of the CEC specification for
- * incoming signals. Our measurements aren't 100% accurate either, so this
- * gives some robustness.
- */
-#define VALID_TOLERANCE_TICKS APB1_TICKS(100)
-
-/*
- * Defines used for setting capture timers to a point where we are
- * sure that if we get a timeout, something is wrong.
- */
-#define CAP_START_LOW_TICKS (START_BIT_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
-#define CAP_START_HIGH_TICKS (START_BIT_MAX_DURATION_TICKS - \
-			      START_BIT_MIN_LOW_TICKS +	\
-			      VALID_TOLERANCE_TICKS)
-#define CAP_DATA_LOW_TICKS (DATA_ZERO_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
-#define CAP_DATA_HIGH_TICKS (DATA_ONE_MAX_DURATION_TICKS - \
-			     DATA_ONE_MIN_LOW_TICKS + \
-			     VALID_TOLERANCE_TICKS)
-
-#define VALID_TIME(type, bit, t) \
-	((t) >= ((bit ## _MIN_ ## type ## _TICKS) - (VALID_TOLERANCE_TICKS)) \
-	 && (t) <=  (bit ##_MAX_ ## type ## _TICKS) + (VALID_TOLERANCE_TICKS))
-#define VALID_LOW(bit, t) VALID_TIME(LOW, bit, t)
-#define VALID_HIGH(bit, low_time, high_time) \
-	(((low_time) + (high_time) <= \
-	  bit ## _MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \
-	 ((low_time) + (high_time) >= \
-	  bit ## _MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS))
-#define VALID_DATA_HIGH(data, low_time, high_time) ((data) ? \
-				VALID_HIGH(DATA_ONE, low_time, high_time) : \
-				VALID_HIGH(DATA_ZERO, low_time, high_time))
-
-/*
- * CEC state machine states. Each state typically takes action on entry and
- * timeouts. INITIATIOR states are used for sending, FOLLOWER states are used
- *  for receiving.
- */
-enum cec_state {
-	CEC_STATE_DISABLED = 0,
-	CEC_STATE_IDLE,
-	CEC_STATE_INITIATOR_FREE_TIME,
-	CEC_STATE_INITIATOR_START_LOW,
-	CEC_STATE_INITIATOR_START_HIGH,
-	CEC_STATE_INITIATOR_HEADER_INIT_LOW,
-	CEC_STATE_INITIATOR_HEADER_INIT_HIGH,
-	CEC_STATE_INITIATOR_HEADER_DEST_LOW,
-	CEC_STATE_INITIATOR_HEADER_DEST_HIGH,
-	CEC_STATE_INITIATOR_DATA_LOW,
-	CEC_STATE_INITIATOR_DATA_HIGH,
-	CEC_STATE_INITIATOR_EOM_LOW,
-	CEC_STATE_INITIATOR_EOM_HIGH,
-	CEC_STATE_INITIATOR_ACK_LOW,
-	CEC_STATE_INITIATOR_ACK_HIGH,
-	CEC_STATE_INITIATOR_ACK_VERIFY,
-	CEC_STATE_FOLLOWER_START_LOW,
-	CEC_STATE_FOLLOWER_START_HIGH,
-	CEC_STATE_FOLLOWER_DEBOUNCE,
-	CEC_STATE_FOLLOWER_HEADER_INIT_LOW,
-	CEC_STATE_FOLLOWER_HEADER_INIT_HIGH,
-	CEC_STATE_FOLLOWER_HEADER_DEST_LOW,
-	CEC_STATE_FOLLOWER_HEADER_DEST_HIGH,
-	CEC_STATE_FOLLOWER_EOM_LOW,
-	CEC_STATE_FOLLOWER_EOM_HIGH,
-	CEC_STATE_FOLLOWER_ACK_LOW,
-	CEC_STATE_FOLLOWER_ACK_VERIFY,
-	CEC_STATE_FOLLOWER_ACK_FINISH,
-	CEC_STATE_FOLLOWER_DATA_LOW,
-	CEC_STATE_FOLLOWER_DATA_HIGH,
-};
-
-/* Edge to trigger capture timer interrupt on */
-enum cap_edge {
-	CAP_EDGE_FALLING,
-	CAP_EDGE_RISING
-};
-
-/* Receive buffer and states */
-struct cec_rx {
-	/*
-	 * The current incoming message being parsed. Copied to
-	 * receive queue upon completion
-	 */
-	struct cec_msg_transfer transfer;
-	/* End of Message received from source? */
-	uint8_t eom;
-	/* A follower NAK:ed a broadcast transfer */
-	uint8_t broadcast_nak;
-	/*
-	 * Keep track of pulse low time to be able to verify
-	 * pulse duration
-	 */
-	int low_ticks;
-	/* Number of too short pulses seen in a row */
-	int debounce_count;
-};
-
-/* Transfer buffer and states */
-struct cec_tx {
-	/* Outgoing message */
-	struct cec_msg_transfer transfer;
-	/* Message length */
-	uint8_t len;
-	/* Number of resends attempted in current send */
-	uint8_t resends;
-	/* Acknowledge received from sink? */
-	uint8_t ack;
-	/*
-	 * When sending multiple concurrent frames,
-	 * the free-time is slightly higher
-	 */
-	int present_initiator;
-};
-
-/* Single state for CEC. We are INITIATOR, FOLLOWER or IDLE */
-static enum cec_state cec_state;
-
-/* Parameters and buffers for follower (receiver) state */
-static struct cec_rx cec_rx;
-
-/* Queue of completed incoming CEC messages */
-static struct cec_rx_queue cec_rx_queue;
-
-/* Parameters and buffer for initiator (sender) state */
-static struct cec_tx cec_tx;
-
-/*
- * Time between interrupt triggered and the next timer was
- * set when measuring pulse width
- */
-static int cap_delay;
-
-/* Value charged into the capture timer on last capture start */
-static int cap_charge;
-
-/*
- * CEC address of ourself. We ack incoming packages on this address.
- * However, the AP is responsible for writing the initiator address
- * on writes. UINT32_MAX means means that the address hasn't been
- * set by the AP yet.
- */
-static uint8_t cec_addr = UINT8_MAX;
-
-/* Events to send to AP */
-static uint32_t cec_events;
-
-/* APB1 frequency. Store divided by 10k to avoid some runtime divisions */
-static uint32_t apb1_freq_div_10k;
-
-static void send_mkbp_event(uint32_t event)
-{
-	atomic_or(&cec_events, event);
-	mkbp_send_event(EC_MKBP_EVENT_CEC_EVENT);
-}
-
-static void tmr_cap_start(enum cap_edge edge, int timeout)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	/* Select edge to trigger capture on */
-	UPDATE_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG,
-		   edge == CAP_EDGE_RISING);
-
-	/*
-	 * Set capture timeout. If we don't have a timeout, we
-	 * turn the timeout interrupt off and only care about
-	 * the edge change.
-	 */
-	if (timeout > 0) {
-		/*
-		 * Store the time it takes from the interrupts starts to when we
-		 * actually get here. This part of the pulse-width needs to be
-		 * taken into account
-		 */
-		cap_delay = (0xffff - NPCX_TCNT1(mdl));
-		cap_charge = timeout - cap_delay;
-		NPCX_TCNT1(mdl) = cap_charge;
-		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
-	} else {
-		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
-		NPCX_TCNT1(mdl) = 0;
-	}
-
-	/* Clear out old events */
-	SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TACLR);
-	SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TCCLR);
-	NPCX_TCRA(mdl) = 0;
-	/* Start the capture timer */
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 1);
-}
-
-static void tmr_cap_stop(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 0);
-}
-
-static int tmr_cap_get(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	return (cap_charge + cap_delay - NPCX_TCRA(mdl));
-}
-
-static void tmr_oneshot_start(int timeout)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	NPCX_TCNT1(mdl) = timeout;
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 1);
-}
-
-static void tmr2_start(int timeout)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	NPCX_TCNT2(mdl) = timeout;
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C2CSEL_FIELD, 1);
-}
-
-static void tmr2_stop(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C2CSEL_FIELD, 0);
-}
-
-void enter_state(enum cec_state new_state)
-{
-	int gpio = -1, timeout = -1;
-	enum cap_edge cap_edge = -1;
-	uint8_t addr;
-
-	cec_state = new_state;
-	switch (new_state) {
-	case CEC_STATE_DISABLED:
-		gpio = 1;
-		memset(&cec_rx, 0, sizeof(struct cec_rx));
-		memset(&cec_tx, 0, sizeof(struct cec_tx));
-		memset(&cec_rx_queue, 0, sizeof(struct cec_rx_queue));
-		cap_charge = 0;
-		cap_delay = 0;
-		cec_events = 0;
-		break;
-	case CEC_STATE_IDLE:
-		cec_tx.transfer.bit = 0;
-		cec_tx.transfer.byte = 0;
-		cec_rx.transfer.bit = 0;
-		cec_rx.transfer.byte = 0;
-		if (cec_tx.len > 0) {
-			/* Execute a postponed send */
-			enter_state(CEC_STATE_INITIATOR_FREE_TIME);
-		} else {
-			/* Wait for incoming command */
-			gpio = 1;
-			cap_edge = CAP_EDGE_FALLING;
-			timeout = 0;
-		}
-		break;
-	case CEC_STATE_INITIATOR_FREE_TIME:
-		gpio = 1;
-		cap_edge = CAP_EDGE_FALLING;
-		if (cec_tx.resends)
-			timeout = FREE_TIME_RS_TICKS;
-		else if (cec_tx.present_initiator)
-			timeout = FREE_TIME_PI_TICKS;
-		else
-			timeout = FREE_TIME_NI_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_START_LOW:
-		cec_tx.present_initiator = 1;
-		cec_tx.transfer.bit = 0;
-		cec_tx.transfer.byte = 0;
-		gpio = 0;
-		timeout = START_BIT_LOW_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_START_HIGH:
-		gpio = 1;
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = START_BIT_HIGH_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_LOW:
-	case CEC_STATE_INITIATOR_HEADER_DEST_LOW:
-	case CEC_STATE_INITIATOR_DATA_LOW:
-		gpio = 0;
-		timeout = DATA_LOW(cec_transfer_get_bit(&cec_tx.transfer));
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
-		gpio = 1;
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = DATA_HIGH(cec_transfer_get_bit(&cec_tx.transfer));
-		break;
-	case CEC_STATE_INITIATOR_HEADER_DEST_HIGH:
-	case CEC_STATE_INITIATOR_DATA_HIGH:
-		gpio = 1;
-		timeout = DATA_HIGH(cec_transfer_get_bit(&cec_tx.transfer));
-		break;
-	case CEC_STATE_INITIATOR_EOM_LOW:
-		gpio = 0;
-		timeout = DATA_LOW(cec_transfer_is_eom(&cec_tx.transfer,
-						       cec_tx.len));
-		break;
-	case CEC_STATE_INITIATOR_EOM_HIGH:
-		gpio = 1;
-		timeout = DATA_HIGH(cec_transfer_is_eom(&cec_tx.transfer,
-							cec_tx.len));
-		break;
-	case CEC_STATE_INITIATOR_ACK_LOW:
-		gpio = 0;
-		timeout = DATA_LOW(1);
-		break;
-	case CEC_STATE_INITIATOR_ACK_HIGH:
-		gpio = 1;
-		/* Aim for the middle of the safe sample time */
-		timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS)/2 -
-							DATA_ONE_LOW_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_ACK_VERIFY:
-		cec_tx.ack = !gpio_get_level(CEC_GPIO_OUT);
-		if ((cec_tx.transfer.buf[0] & 0x0f) == CEC_BROADCAST_ADDR) {
-			/*
-			 * We are sending a broadcast. Any follower can
-			 * can NAK a broadcast message the same way they
-			 * would ACK a direct message
-			 */
-			cec_tx.ack = !cec_tx.ack;
-		}
-		/*
-		 * We are at the safe sample time. Wait
-		 * until the end of this bit
-		 */
-		timeout = NOMINAL_BIT_TICKS - NOMINAL_SAMPLE_TIME_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_START_LOW:
-		cec_tx.present_initiator = 0;
-		cap_edge = CAP_EDGE_RISING;
-		timeout = CAP_START_LOW_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_START_HIGH:
-		cec_rx.debounce_count = 0;
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = CAP_START_HIGH_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_DEBOUNCE:
-		if (cec_rx.debounce_count >= DEBOUNCE_CUTOFF) {
-			timeout = DEBOUNCE_WAIT_LONG_TICKS;
-		} else {
-			timeout = DEBOUNCE_WAIT_SHORT_TICKS;
-			cec_rx.debounce_count++;
-		}
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
-	case CEC_STATE_FOLLOWER_EOM_LOW:
-		cap_edge = CAP_EDGE_RISING;
-		timeout = CAP_DATA_LOW_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
-	case CEC_STATE_FOLLOWER_EOM_HIGH:
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = CAP_DATA_HIGH_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_ACK_LOW:
-		addr = cec_rx.transfer.buf[0] & 0x0f;
-		if (addr == cec_addr) {
-			/* Destination is our address */
-			gpio = 0;
-			timeout = NOMINAL_SAMPLE_TIME_TICKS;
-		} else if (addr == CEC_BROADCAST_ADDR) {
-			/* Don't ack broadcast or packets which destination
-			 * are us, but continue reading
-			 */
-			timeout = NOMINAL_SAMPLE_TIME_TICKS;
-		}
-		break;
-	case CEC_STATE_FOLLOWER_ACK_VERIFY:
-		/*
-		 * We are at safe sample time. A broadcast frame is considered
-		 * lost if any follower pulls the line low
-		 */
-		if ((cec_rx.transfer.buf[0] & 0x0f) == CEC_BROADCAST_ADDR)
-			cec_rx.broadcast_nak = !gpio_get_level(CEC_GPIO_OUT);
-		else
-			cec_rx.broadcast_nak = 0;
-
-		/*
-		 * We release the ACK at the end of data zero low
-		 * period (ACK is technically a zero).
-		 */
-		timeout = DATA_ZERO_LOW_TICKS - NOMINAL_SAMPLE_TIME_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_ACK_FINISH:
-		gpio = 1;
-		if (cec_rx.eom || cec_rx.transfer.byte >= MAX_CEC_MSG_LEN) {
-			addr = cec_rx.transfer.buf[0] & 0x0f;
-			if (addr == cec_addr || addr == CEC_BROADCAST_ADDR) {
-				task_set_event(TASK_ID_CEC,
-					       TASK_EVENT_RECEIVED_DATA);
-			}
-			timeout = DATA_ZERO_HIGH_TICKS;
-		} else {
-			cap_edge = CAP_EDGE_FALLING;
-			timeout = CAP_DATA_HIGH_TICKS;
-		}
-		break;
-	case CEC_STATE_FOLLOWER_DATA_LOW:
-		cap_edge = CAP_EDGE_RISING;
-		timeout = CAP_DATA_LOW_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_DATA_HIGH:
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = CAP_DATA_HIGH_TICKS;
-		break;
-	/* No default case, since all states must be handled explicitly */
-	}
-
-	if (gpio >= 0)
-		gpio_set_level(CEC_GPIO_OUT, gpio);
-	if (timeout >= 0) {
-		if (cap_edge >= 0)
-			tmr_cap_start(cap_edge, timeout);
-		else
-			tmr_oneshot_start(timeout);
-	}
-}
-
-static void cec_event_timeout(void)
-{
-	switch (cec_state) {
-	case CEC_STATE_DISABLED:
-	case CEC_STATE_IDLE:
-		break;
-	case CEC_STATE_INITIATOR_FREE_TIME:
-		enter_state(CEC_STATE_INITIATOR_START_LOW);
-		break;
-	case CEC_STATE_INITIATOR_START_LOW:
-		enter_state(CEC_STATE_INITIATOR_START_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_START_HIGH:
-		enter_state(CEC_STATE_INITIATOR_HEADER_INIT_LOW);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_LOW:
-		enter_state(CEC_STATE_INITIATOR_HEADER_INIT_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
-		cec_transfer_inc_bit(&cec_tx.transfer);
-		if (cec_tx.transfer.bit == 4)
-			enter_state(CEC_STATE_INITIATOR_HEADER_DEST_LOW);
-		else
-			enter_state(CEC_STATE_INITIATOR_HEADER_INIT_LOW);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_DEST_LOW:
-		enter_state(CEC_STATE_INITIATOR_HEADER_DEST_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_DEST_HIGH:
-		cec_transfer_inc_bit(&cec_tx.transfer);
-		if (cec_tx.transfer.byte == 1)
-			enter_state(CEC_STATE_INITIATOR_EOM_LOW);
-		else
-			enter_state(CEC_STATE_INITIATOR_HEADER_DEST_LOW);
-		break;
-	case CEC_STATE_INITIATOR_EOM_LOW:
-		enter_state(CEC_STATE_INITIATOR_EOM_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_EOM_HIGH:
-		enter_state(CEC_STATE_INITIATOR_ACK_LOW);
-		break;
-	case CEC_STATE_INITIATOR_ACK_LOW:
-		enter_state(CEC_STATE_INITIATOR_ACK_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_ACK_HIGH:
-		enter_state(CEC_STATE_INITIATOR_ACK_VERIFY);
-		break;
-	case CEC_STATE_INITIATOR_ACK_VERIFY:
-		if (cec_tx.ack) {
-			if (!cec_transfer_is_eom(&cec_tx.transfer,
-						 cec_tx.len)) {
-				/* More data in this frame */
-				enter_state(CEC_STATE_INITIATOR_DATA_LOW);
-			} else {
-				/* Transfer completed successfully */
-				cec_tx.len = 0;
-				cec_tx.resends = 0;
-				enter_state(CEC_STATE_IDLE);
-				send_mkbp_event(EC_MKBP_CEC_SEND_OK);
-			}
-		} else {
-			if (cec_tx.resends < CEC_MAX_RESENDS) {
-				/* Resend */
-				cec_tx.resends++;
-				enter_state(CEC_STATE_INITIATOR_FREE_TIME);
-			} else {
-				/* Transfer failed */
-				cec_tx.len = 0;
-				cec_tx.resends = 0;
-				enter_state(CEC_STATE_IDLE);
-				send_mkbp_event(EC_MKBP_CEC_SEND_FAILED);
-			}
-		}
-		break;
-	case CEC_STATE_INITIATOR_DATA_LOW:
-		enter_state(CEC_STATE_INITIATOR_DATA_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_DATA_HIGH:
-		cec_transfer_inc_bit(&cec_tx.transfer);
-		if (cec_tx.transfer.bit == 0)
-			enter_state(CEC_STATE_INITIATOR_EOM_LOW);
-		else
-			enter_state(CEC_STATE_INITIATOR_DATA_LOW);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_LOW:
-		enter_state(CEC_STATE_FOLLOWER_ACK_VERIFY);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_VERIFY:
-		if (cec_rx.broadcast_nak)
-			enter_state(CEC_STATE_IDLE);
-		else
-			enter_state(CEC_STATE_FOLLOWER_ACK_FINISH);
-		break;
-	case CEC_STATE_FOLLOWER_START_LOW:
-	case CEC_STATE_FOLLOWER_START_HIGH:
-	case CEC_STATE_FOLLOWER_DEBOUNCE:
-	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
-	case CEC_STATE_FOLLOWER_EOM_LOW:
-	case CEC_STATE_FOLLOWER_EOM_HIGH:
-	case CEC_STATE_FOLLOWER_ACK_FINISH:
-	case CEC_STATE_FOLLOWER_DATA_LOW:
-	case CEC_STATE_FOLLOWER_DATA_HIGH:
-		enter_state(CEC_STATE_IDLE);
-		break;
-
-	}
-}
-
-static void cec_event_cap(void)
-{
-	int t;
-	int data;
-
-	switch (cec_state) {
-	case CEC_STATE_IDLE:
-		/* A falling edge during idle, likely a start bit */
-		enter_state(CEC_STATE_FOLLOWER_START_LOW);
-		break;
-	case CEC_STATE_INITIATOR_FREE_TIME:
-	case CEC_STATE_INITIATOR_START_HIGH:
-	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
-		/*
-		 * A falling edge during free-time, postpone
-		 * this send and listen
-		 */
-		cec_tx.transfer.bit = 0;
-		cec_tx.transfer.byte = 0;
-		enter_state(CEC_STATE_FOLLOWER_START_LOW);
-		break;
-	case CEC_STATE_FOLLOWER_START_LOW:
-		/* Rising edge of start bit, validate low time */
-		t =  tmr_cap_get();
-		if (VALID_LOW(START_BIT, t)) {
-			cec_rx.low_ticks = t;
-			enter_state(CEC_STATE_FOLLOWER_START_HIGH);
-		} else if (t < DEBOUNCE_LIMIT_TICKS) {
-			/* Wait a bit if start-pulses are really short */
-			enter_state(CEC_STATE_FOLLOWER_DEBOUNCE);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_START_HIGH:
-		if (VALID_HIGH(START_BIT, cec_rx.low_ticks, tmr_cap_get()))
-			enter_state(CEC_STATE_FOLLOWER_HEADER_INIT_LOW);
-		else
-			enter_state(CEC_STATE_IDLE);
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
-	case CEC_STATE_FOLLOWER_DATA_LOW:
-		t = tmr_cap_get();
-		if (VALID_LOW(DATA_ZERO, t)) {
-			cec_rx.low_ticks = t;
-			cec_transfer_set_bit(&cec_rx.transfer, 0);
-			enter_state(cec_state + 1);
-		} else if (VALID_LOW(DATA_ONE, t)) {
-			cec_rx.low_ticks = t;
-			cec_transfer_set_bit(&cec_rx.transfer, 1);
-			enter_state(cec_state + 1);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
-		t = tmr_cap_get();
-		data = cec_transfer_get_bit(&cec_rx.transfer);
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
-			cec_transfer_inc_bit(&cec_rx.transfer);
-			if (cec_rx.transfer.bit == 4)
-				enter_state(CEC_STATE_FOLLOWER_HEADER_DEST_LOW);
-			else
-				enter_state(CEC_STATE_FOLLOWER_HEADER_INIT_LOW);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
-		t = tmr_cap_get();
-		data = cec_transfer_get_bit(&cec_rx.transfer);
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
-			cec_transfer_inc_bit(&cec_rx.transfer);
-			if (cec_rx.transfer.bit == 0)
-				enter_state(CEC_STATE_FOLLOWER_EOM_LOW);
-			else
-				enter_state(CEC_STATE_FOLLOWER_HEADER_DEST_LOW);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_EOM_LOW:
-		t = tmr_cap_get();
-		if (VALID_LOW(DATA_ZERO, t)) {
-			cec_rx.low_ticks = t;
-			cec_rx.eom = 0;
-			enter_state(CEC_STATE_FOLLOWER_EOM_HIGH);
-		} else if (VALID_LOW(DATA_ONE, t)) {
-			cec_rx.low_ticks = t;
-			cec_rx.eom = 1;
-			enter_state(CEC_STATE_FOLLOWER_EOM_HIGH);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_EOM_HIGH:
-		t = tmr_cap_get();
-		data = cec_rx.eom;
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t))
-			enter_state(CEC_STATE_FOLLOWER_ACK_LOW);
-		else
-			enter_state(CEC_STATE_IDLE);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_LOW:
-		enter_state(CEC_STATE_FOLLOWER_ACK_FINISH);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_FINISH:
-		enter_state(CEC_STATE_FOLLOWER_DATA_LOW);
-		break;
-	case CEC_STATE_FOLLOWER_DATA_HIGH:
-		t = tmr_cap_get();
-		data = cec_transfer_get_bit(&cec_rx.transfer);
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
-			cec_transfer_inc_bit(&cec_rx.transfer);
-			if (cec_rx.transfer.bit == 0)
-				enter_state(CEC_STATE_FOLLOWER_EOM_LOW);
-			else
-				enter_state(CEC_STATE_FOLLOWER_DATA_LOW);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-static void cec_event_tx(void)
-{
-	/*
-	 * If we have an ongoing receive, this transfer
-	 * will start when transitioning to IDLE
-	 */
-	if (cec_state == CEC_STATE_IDLE)
-		enter_state(CEC_STATE_INITIATOR_FREE_TIME);
-}
-
-void cec_isr(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-	uint8_t events;
-
-	/* Retrieve events NPCX_TECTRL_TAXND */
-	events = GET_FIELD(NPCX_TECTRL(mdl), FIELD(0, 4));
-
-	if (events & BIT(NPCX_TECTRL_TAPND)) {
-		/* Capture event */
-		cec_event_cap();
-	} else {
-		/*
-		 * Capture timeout
-		 * We only care about this if the capture event is not
-		 * happening, since we will get both events in the
-		 * edge-trigger case
-		 */
-		if (events & BIT(NPCX_TECTRL_TCPND))
-			cec_event_timeout();
-	}
-	/* Oneshot timer, a transfer has been initiated from AP */
-	if (events & BIT(NPCX_TECTRL_TDPND)) {
-		tmr2_stop();
-		cec_event_tx();
-	}
-
-	/* Clear handled events */
-	SET_FIELD(NPCX_TECLR(mdl), FIELD(0, 4), events);
-}
-DECLARE_IRQ(NPCX_IRQ_MFT_1, cec_isr, 4);
-
-static int cec_send(const uint8_t *msg, uint8_t len)
-{
-	int i;
-
-	if (cec_tx.len != 0)
-		return -1;
-
-	cec_tx.len = len;
-
-	CPRINTS("Send CEC:");
-	for (i = 0; i < len && i < MAX_CEC_MSG_LEN; i++)
-		CPRINTS(" 0x%02x", msg[i]);
-
-	memcpy(cec_tx.transfer.buf, msg, len);
-
-	/* Elevate to interrupt context */
-	tmr2_start(0);
-
-	return 0;
-}
-
-static enum ec_status hc_cec_write(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_cec_write *params = args->params;
-
-	if (cec_state == CEC_STATE_DISABLED)
-		return EC_RES_UNAVAILABLE;
-
-	if (args->params_size == 0 || args->params_size > MAX_CEC_MSG_LEN)
-		return EC_RES_INVALID_PARAM;
-
-	if (cec_send(params->msg, args->params_size) != 0)
-		return EC_RES_BUSY;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CEC_WRITE_MSG, hc_cec_write, EC_VER_MASK(0));
-
-static int cec_set_enable(uint8_t enable)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	if (enable != 0 && enable != 1)
-		return EC_RES_INVALID_PARAM;
-
-	/* Enabling when already enabled? */
-	if (enable && cec_state != CEC_STATE_DISABLED)
-		return EC_RES_SUCCESS;
-
-	/* Disabling when already disabled? */
-	if (!enable && cec_state == CEC_STATE_DISABLED)
-		return EC_RES_SUCCESS;
-
-	if (enable) {
-		/* Configure GPIO40/TA1 as capture timer input (TA1) */
-		CLEAR_BIT(NPCX_DEVALT(0xC), NPCX_DEVALTC_TA1_SL2);
-		SET_BIT(NPCX_DEVALT(3), NPCX_DEVALT3_TA1_SL1);
-
-		enter_state(CEC_STATE_IDLE);
-
-		/*
-		 * Capture falling edge of first start
-		 * bit to get things going
-		 */
-		tmr_cap_start(CAP_EDGE_FALLING, 0);
-
-		/* Enable timer interrupts */
-		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
-		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TDIEN);
-
-		/* Enable multifunction timer interrupt */
-		task_enable_irq(NPCX_IRQ_MFT_1);
-
-		CPRINTF("CEC enabled\n");
-	} else {
-		/* Disable timer interrupts */
-		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
-		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TDIEN);
-
-		tmr2_stop();
-		tmr_cap_stop();
-
-		task_disable_irq(NPCX_IRQ_MFT_1);
-
-		/* Configure GPIO40/TA1 back to GPIO */
-		CLEAR_BIT(NPCX_DEVALT(3), NPCX_DEVALT3_TA1_SL1);
-		SET_BIT(NPCX_DEVALT(0xC), NPCX_DEVALTC_TA1_SL2);
-
-		enter_state(CEC_STATE_DISABLED);
-
-		CPRINTF("CEC disabled\n");
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-static int cec_set_logical_addr(uint8_t logical_addr)
-{
-	if (logical_addr >= CEC_BROADCAST_ADDR &&
-	    logical_addr != CEC_UNREGISTERED_ADDR)
-		return EC_RES_INVALID_PARAM;
-
-	cec_addr = logical_addr;
-	CPRINTF("CEC address set to: %u\n", cec_addr);
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status hc_cec_set(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_cec_set *params = args->params;
-
-	switch (params->cmd) {
-	case CEC_CMD_ENABLE:
-		return cec_set_enable(params->val);
-	case CEC_CMD_LOGICAL_ADDRESS:
-		return cec_set_logical_addr(params->val);
-	}
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CEC_SET, hc_cec_set, EC_VER_MASK(0));
-
-
-static enum ec_status hc_cec_get(struct host_cmd_handler_args *args)
-{
-	struct ec_response_cec_get *response = args->response;
-	const struct ec_params_cec_get *params = args->params;
-
-	switch (params->cmd) {
-	case CEC_CMD_ENABLE:
-		response->val = cec_state == CEC_STATE_DISABLED ? 0 : 1;
-		break;
-	case CEC_CMD_LOGICAL_ADDRESS:
-		response->val = cec_addr;
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	args->response_size = sizeof(*response);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CEC_GET, hc_cec_get, EC_VER_MASK(0));
-
-static int cec_get_next_event(uint8_t *out)
-{
-	uint32_t event_out = atomic_clear(&cec_events);
-
-	memcpy(out, &event_out, sizeof(event_out));
-
-	return sizeof(event_out);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_EVENT, cec_get_next_event);
-
-static int cec_get_next_msg(uint8_t *out)
-{
-	int rv;
-	uint8_t msg_len, msg[MAX_CEC_MSG_LEN];
-
-	rv = cec_rx_queue_pop(&cec_rx_queue, msg, &msg_len);
-	if (rv != 0)
-		return EC_RES_UNAVAILABLE;
-
-	memcpy(out, msg, msg_len);
-
-	return msg_len;
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_MESSAGE, cec_get_next_msg);
-
-
-static void cec_init(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	/* APB1 is the clock we base the timers on */
-	apb1_freq_div_10k = clock_get_apb1_freq()/10000;
-
-	/* Ensure Multi-Function timer is powered up. */
-	CLEAR_BIT(NPCX_PWDWN_CTL(mdl), NPCX_PWDWN_CTL1_MFT1_PD);
-
-	/* Mode 2 - Dual-input capture */
-	SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD, NPCX_MFT_MDSEL_2);
-
-	/* Enable capture TCNT1 into TCRA and preset TCNT1. */
-	SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEN);
-
-	/* If RO doesn't set it, RW needs to set it explicitly. */
-	gpio_set_level(CEC_GPIO_PULL_UP, 1);
-
-	/* Ensure the CEC bus is not pulled low by default on startup. */
-	gpio_set_level(CEC_GPIO_OUT, 1);
-
-	CPRINTS("CEC initialized");
-}
-DECLARE_HOOK(HOOK_INIT, cec_init, HOOK_PRIO_LAST);
-
-void cec_task(void *unused)
-{
-	int rv;
-	uint32_t events;
-
-	CPRINTF("CEC task starting\n");
-
-	while (1) {
-		events = task_wait_event(-1);
-		if (events & TASK_EVENT_RECEIVED_DATA) {
-			rv = cec_rx_queue_push(&cec_rx_queue,
-					       cec_rx.transfer.buf,
-					       cec_rx.transfer.byte);
-			if (rv == EC_ERROR_OVERFLOW) {
-				/* Queue full, prefer the most recent msg */
-				cec_rx_queue_flush(&cec_rx_queue);
-				rv = cec_rx_queue_push(&cec_rx_queue,
-						       cec_rx.transfer.buf,
-						       cec_rx.transfer.byte);
-			}
-			if (rv == EC_SUCCESS)
-				mkbp_send_event(EC_MKBP_EVENT_CEC_MESSAGE);
-		}
-	}
-}
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
deleted file mode 100644
index ad611973be..0000000000
--- a/chip/npcx/clock.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "uartn.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#define WAKE_INTERVAL   61        /* Unit: 61 usec */
-#define IDLE_PARAMS     0x7       /* Support deep idle, instant wake-up */
-
-/* Low power idle statistics */
-#ifdef CONFIG_LOW_POWER_IDLE
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the low speed clock is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-static int console_in_use_timeout_sec = 15;
-static timestamp_t console_expire_time;
-#endif
-
-/**
- * Enable clock to peripheral by setting the CGC register pertaining
- * to run, sleep, and/or deep sleep modes.
- *
- * @param offset  Offset of the peripheral. See enum clock_gate_offsets.
- * @param mask    Bit mask of the bits within CGC reg to set.
- * @param mode    no used
- */
-void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	/* Don't support for different mode */
-	uint8_t reg_mask = mask & 0xff;
-
-	/* Set PD bit to 0 */
-	NPCX_PWDWN_CTL(offset) &= ~reg_mask;
-	/* Wait for clock change to take affect. */
-	clock_wait_cycles(3);
-}
-
-/**
- * Disable clock to peripheral by setting the CGC register pertaining
- * to run, sleep, and/or deep sleep modes.
- *
- * @param offset  Offset of the peripheral. See enum clock_gate_offsets.
- * @param mask    Bit mask of the bits within CGC reg to clear.
- * @param mode    no used
- */
-void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	/* Don't support for different mode */
-	uint8_t reg_mask = mask & 0xff;
-
-	/* Set PD bit to 1 */
-	NPCX_PWDWN_CTL(offset) |= reg_mask;
-
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/**
- * Set the CPU clocks and PLLs.
- */
-void clock_init(void)
-{
-#if defined(CONFIG_CLOCK_SRC_EXTERNAL) && defined(NPCX_EXT32K_OSC_SUPPORT)
-	/* Select external 32kHz crystal oscillator as LFCLK source. */
-	SET_BIT(NPCX_LFCGCTL2, NPCX_LFCGCTL2_XT_OSC_SL_EN);
-#endif
-
-	/*
-	 * Resting the OSC_CLK (even to the same value) will make the clock
-	 * unstable for a little which can affect peripheral communication like
-	 * eSPI. Skip this if not needed (e.g. RW jump)
-	 */
-	if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML
-				|| NPCX_HFCGMH != HFCGMH) {
-		/*
-		 * Configure frequency multiplier M/N values according to
-		 * the requested OSC_CLK (Unit:Hz).
-		 */
-		NPCX_HFCGN  = HFCGN;
-		NPCX_HFCGML = HFCGML;
-		NPCX_HFCGMH = HFCGMH;
-
-		/* Load M and N values into the frequency multiplier */
-		SET_BIT(NPCX_HFCGCTRL, NPCX_HFCGCTRL_LOAD);
-		/* Wait for stable */
-		while (IS_BIT_SET(NPCX_HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
-			;
-	}
-
-	/* Set all clock prescalers of core and peripherals. */
-#if defined(CHIP_FAMILY_NPCX5)
-	NPCX_HFCGP  = (FPRED << 4);
-	NPCX_HFCBCD = (NPCX_HFCBCD & 0xF0) | (APB1DIV | (APB2DIV << 2));
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	NPCX_HFCGP   = ((FPRED << 4) | AHB6DIV);
-	NPCX_HFCBCD  = (FIUDIV << 4);
-	NPCX_HFCBCD1 = (APB1DIV | (APB2DIV << 4));
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	NPCX_HFCBCD2 = (APB3DIV | (APB4DIV << 4));
-#else
-	NPCX_HFCBCD2 = APB3DIV;
-#endif
-#endif
-
-	/* Notify modules of frequency change */
-	hook_notify(HOOK_FREQ_CHANGE);
-
-	/* Configure alt. clock GPIOs (eg. optional 32KHz clock) */
-	gpio_config_module(MODULE_CLOCK, 1);
-}
-
-#if defined(CHIP_FAMILY_NPCX5)
-void clock_turbo(void)
-{
-	/* Configure Frequency multiplier values to 50MHz */
-	NPCX_HFCGN  = 0x02;
-	NPCX_HFCGML = 0xEC;
-	NPCX_HFCGMH = 0x0B;
-
-	/* Load M and N values into the frequency multiplier */
-	SET_BIT(NPCX_HFCGCTRL, NPCX_HFCGCTRL_LOAD);
-
-	/* Wait for stable */
-	while (IS_BIT_SET(NPCX_HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
-		;
-
-	/* Keep Core CLK & FMCLK are the same if Core CLK exceed 33MHz */
-	NPCX_HFCGP = 0x00;
-
-	/*
-	 * Let APB2 equals Core CLK/2 if default APB2 clock is divisible
-	 * by 1MHz
-	 */
-	NPCX_HFCBCD = NPCX_HFCBCD & 0xF3;
-}
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-void clock_turbo(void)
-{
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	/* For NPCX9:
-	 * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
-	 * CORE_CLK > 66MHz, we also need to set FIUDIV as 1 but
-	 * can keep AHB6DIV to 0.
-	 */
-	NPCX_HFCGP = 0x00;
-#else
-	/* For NPCX7:
-	 * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
-	 * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1.
-	 */
-	NPCX_HFCGP = 0x01;
-#endif
-	NPCX_HFCBCD = BIT(4);
-}
-
-void clock_normal(void)
-{
-	/* Set CORE_CLK (CPU), AHB6_CLK and FIU_CLK back to original values. */
-	NPCX_HFCGP = ((FPRED << 4) | AHB6DIV);
-	NPCX_HFCBCD = (FIUDIV << 4);
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	/* Assume we have a single task using MODULE_FAST_CPU */
-	if (module == MODULE_FAST_CPU) {
-		if (enable)
-			clock_turbo();
-		else
-			clock_normal();
-	}
-}
-
-#endif
-
-/**
- * Return the current clock frequency in Hz.
- */
-int clock_get_freq(void)
-{
-	return CORE_CLK;
-}
-
-/**
- * Return the current FMUL clock frequency in Hz.
- */
-int clock_get_fm_freq(void)
-{
-	return FMCLK;
-}
-
-/**
- * Return the current APB1 clock frequency in Hz.
- */
-int clock_get_apb1_freq(void)
-{
-	return NPCX_APB_CLOCK(1);
-}
-
-/**
- * Return the current APB2 clock frequency in Hz.
- */
-int clock_get_apb2_freq(void)
-{
-	return NPCX_APB_CLOCK(2);
-}
-
-/**
- * Return the current APB3 clock frequency in Hz.
- */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-int clock_get_apb3_freq(void)
-{
-	return NPCX_APB_CLOCK(3);
-}
-#endif
-
-/**
- * Wait for a number of clock cycles.
- *
- * Simple busy waiting for use before clocks/timers are initialized.
- *
- * @param cycles	Number of cycles to wait.
- */
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void clock_refresh_console_in_use(void)
-{
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-	return;
-}
-
-#if defined(CHIP_FAMILY_NPCX5)
-void clock_uart2gpio(void)
-{
-	/* Is pimux to UART? */
-	if (npcx_is_uart()) {
-		/* Flush tx before enter deep idle */
-		uart_tx_flush();
-		/* Change pinmux to GPIO and disable UART IRQ */
-		task_disable_irq(NPCX_IRQ_UART);
-		/* Set to GPIO */
-		npcx_uart2gpio();
-		/* Clear pending wakeup */
-		uart_clear_pending_wakeup();
-		/* Enable MIWU for GPIO (UARTRX) */
-		uart_enable_wakeup(1);
-	}
-}
-
-void clock_gpio2uart(void)
-{
-	/* Is Pending bit of GPIO (UARTRX) */
-	if (uart_is_wakeup_from_gpio()) {
-		/* Refresh console in-use timer */
-		clock_refresh_console_in_use();
-		/* Disable MIWU for GPIO (UARTRX) */
-		uart_enable_wakeup(0);
-		/* Go back CR_SIN */
-		npcx_gpio2uart();
-		/* Enable uart again */
-		task_enable_irq(NPCX_IRQ_UART);
-	}
-}
-#endif
-
-/* Idle task.  Executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	timestamp_t t0, t1;
-	uint32_t next_evt;
-	uint32_t next_evt_us;
-	uint16_t evt_count;
-
-	/*
-	 * Initialize console in use to true and specify the console expire
-	 * time in order to give a fixed window on boot in which the low speed
-	 * clock will not be used in idle.
-	 */
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-
-	while (1) {
-		/*
-		 * Disable interrupts before going to deep sleep in order to
-		 * calculate the appropriate time to wake up. Note: the wfi
-		 * instruction waits until an interrupt is pending, so it
-		 * will still wake up even with interrupts disabled.
-		 */
-		interrupt_disable();
-
-		/* Compute event delay */
-		t0 = get_time();
-		next_evt = __hw_clock_event_get();
-
-		/* Do we have enough time before next event to deep sleep. */
-		if (DEEP_SLEEP_ALLOWED &&
-		    /*
-		     * Our HW timer doesn't tick in deep sleep - we do manual
-		     * adjustment based on sleep duration after wake. Avoid
-		     * the tricky overflow case by waiting out the period just
-		     * before overflow.
-		     */
-		    next_evt != EVT_MAX_EXPIRED_US &&
-		    /* Ensure event hasn't already expired */
-		    next_evt > t0.le.lo &&
-		    /* Ensure we have sufficient time before expiration */
-		    next_evt - t0.le.lo > WAKE_INTERVAL &&
-		    /* Make sure it's over console expired time */
-		    t0.val > console_expire_time.val) {
-#if DEBUG_CLK
-			/* Use GPIO to indicate SLEEP mode */
-			CLEAR_BIT(NPCX_PDOUT(0), 0);
-#endif
-			idle_dsleep_cnt++;
-
-			/* Enable Host access wakeup */
-			SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-
-#if defined(CHIP_FAMILY_NPCX5)
-			/* UART-rx(console) become to GPIO (NONE INT mode) */
-			clock_uart2gpio();
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-			uartn_wui_en(CONFIG_CONSOLE_UART);
-#endif
-
-			/*
-			 * Disable input buffer of all 1.8v i2c ports before
-			 * entering deep sleep for better power consumption.
-			 */
-			gpio_enable_1p8v_i2c_wake_up_input(0);
-
-			/* Set deep idle - instant wake-up mode */
-			NPCX_PMCSR = IDLE_PARAMS;
-
-			/* Get current counter value of event timer */
-			evt_count = __hw_clock_event_count();
-
-			/*
-			 * TODO (ML): We found the same symptom of idle occurs
-			 * after wake-up from deep idle. Please see task.c for
-			 * more detail.
-			 * Workaround: Apply the same bypass of idle.
-			 */
-			asm ("push {r0-r5}\n"
-			     "wfi\n"
-			     "ldm %0, {r0-r5}\n"
-			     "pop {r0-r5}\n"
-			     "isb\n" :: "r" (0x100A8000)
-			);
-
-			/* Get time delay cause of deep idle */
-			next_evt_us = __hw_clock_get_sleep_time(evt_count);
-
-			/*
-			 * Clear PMCSR manually in case there's wake-up between
-			 * setting it and wfi.
-			 */
-			NPCX_PMCSR = 0;
-#if defined(CHIP_FAMILY_NPCX5)
-			/* GPIO back to UART-rx (console) */
-			clock_gpio2uart();
-#endif
-
-			/* Enable input buffer of all 1.8v i2c ports. */
-			gpio_enable_1p8v_i2c_wake_up_input(1);
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += next_evt_us;
-
-			/* Fast forward timer according to wake-up timer. */
-			t1.val = t0.val + next_evt_us;
-			/* Leave overflow situation for ITIM32 */
-			if (t1.le.hi == t0.le.hi)
-				force_time(t1);
-		} else {
-#if DEBUG_CLK
-			/* Use GPIO to indicate NORMAL mode */
-			SET_BIT(NPCX_PDOUT(0), 0);
-#endif
-			idle_sleep_cnt++;
-
-			/*
-			 * Using host access to make sure M4 core clock will
-			 * return when the eSPI accesses the Host modules if
-			 * CSAE bit is set. Please notice this symptom only
-			 * occurs at npcx5.
-			 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
-			/* Enable Host access wakeup */
-			SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-#endif
-			/*
-			 * Normal idle : wait for interrupt
-			 * TODO (ML): Workaround method for wfi issue.
-			 * Please see task.c for more detail
-			 */
-			asm ("push {r0-r5}\n"
-			     "wfi\n"
-			     "ldm %0, {r0-r5}\n"
-			     "pop {r0-r5}\n"
-			     "isb\n" :: "r" (0x100A8000)
-			);
-		}
-
-		/*
-		 * Restore interrupt
-		 * RTOS will leave idle task to handle ISR which wakes up EC
-		 */
-		interrupt_enable();
-	}
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-		"",
-		"Print last idle stats");
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use low speed clock or
-			 * allow it to use the low speed clock.
-			 */
-			if (v)
-				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else
-				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-	ccprintf("PMCSR register:      0x%02x\n", NPCX_PMCSR);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-		"[ on | off | <timeout> sec]",
-		"Deep sleep clock settings:\nUse 'on' to force deep "
-		"sleep not to use low speed clock.\nUse 'off' to "
-		"allow deep sleep to auto-select using the low speed "
-		"clock.\n"
-		"Give a timeout value for the console in use timeout.\n"
-		"See also 'sleepmask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/npcx/clock_chip.h b/chip/npcx/clock_chip.h
deleted file mode 100644
index 702b55c52a..0000000000
--- a/chip/npcx/clock_chip.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific clock module for Chrome EC */
-
-#ifndef __CROS_EC_CLOCK_CHIP_H
-#define __CROS_EC_CLOCK_CHIP_H
-
-/*
- * EC clock tree plan: (Default OSC_CLK is 40MHz.)
- *
- * Target OSC_CLK for NPCX7 is 90MHz, FMCLK is 45MHz, CPU and APBs is 15MHz.
- * Target OSC_CLK for NPCX5 is 30MHz, FMCLK is 30MHz, CPU and APBs is 15MHz.
- */
-#if defined(CHIP_FAMILY_NPCX5)
-/*
- * NPCX5 clock tree: (Please refer Figure 55. for more information.)
- *
- * Suggestion:
- * - OSC_CLK >= 30MHz, FPRED should be 1, else 0.
- *   (Keep FMCLK in 30-50 MHz possibly which is tested strictly.)
- */
-/* Target OSC_CLK freq */
-#define OSC_CLK 30000000
-/* Core clock prescaler */
-#if (OSC_CLK >= 30000000)
-#define FPRED 1 /* CORE_CLK = OSC_CLK(FMCLK)/2 */
-#else
-#define FPRED 0 /* CORE_CLK = OSC_CLK(FMCLK) */
-#endif
-/* Core domain clock */
-#define CORE_CLK (OSC_CLK / (FPRED + 1))
-/* FMUL clock */
-#define FMCLK OSC_CLK
-/* APBs source clock */
-#define APBSRC_CLK CORE_CLK
-/* APB1 clock divider */
-#define APB1DIV 3 /* Default APB1 clock = CORE_CLK/4 */
-/* APB2 clock divider */
-#define APB2DIV 0 /* Let APB2 = CORE_CLK since UART baudrate tolerance */
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-/*
- * NPCX7 clock tree: (Please refer Figure 58. for more information.)
- *
- * Suggestion:
- * - OSC_CLK >= 80MHz, XF_RANGE should be 1, else 0.
- * - CORE_CLK > 66MHz, AHB6DIV should be 1, else 0.
- * - CORE_CLK > 50MHz, FIUDIV should be 1, else 0.
- */
-/* Target OSC_CLK freq */
-#define OSC_CLK 90000000
-/* Core clock prescaler */
-#define FPRED 5 /* CORE_CLK = OSC_CLK/6 */
-/* Core domain clock */
-#define CORE_CLK (OSC_CLK / (FPRED + 1))
-/* FMUL clock */
-#if (OSC_CLK >= 80000000)
-#define FMCLK (OSC_CLK / 2) /* FMUL clock = OSC_CLK/2 if OSC_CLK >= 80MHz */
-#else
-#define FMCLK OSC_CLK /* FMUL clock = OSC_CLK */
-#endif
-/* AHB6 clock */
-#if (CORE_CLK > 66000000)
-#define AHB6DIV 1 /* AHB6_CLK = CORE_CLK/2 if CORE_CLK > 66MHz */
-#else
-#define AHB6DIV 0 /* AHB6_CLK = CORE_CLK */
-#endif
-/* FIU clock divider */
-#if (CORE_CLK > 50000000)
-#define FIUDIV 1 /* FIU_CLK = CORE_CLK/2 */
-#else
-#define FIUDIV 0 /* FIU_CLK = CORE_CLK */
-#endif
-/* APBs source clock */
-#define APBSRC_CLK OSC_CLK
-/* APB1 clock divider */
-#define APB1DIV 5 /* APB1 clock = OSC_CLK/6 */
-/* APB2 clock divider */
-#define APB2DIV 5 /* APB2 clock = OSC_CLK/6 */
-/* APB3 clock divider */
-#define APB3DIV 5 /* APB3 clock = OSC_CLK/6 */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-/* APB4 clock divider */
-#define APB4DIV 5 /* APB4 clock = OSC_CLK/6 */
-#endif
-#endif
-
-/* Get APB clock freq */
-#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV + 1))
-
-/*
- * Frequency multiplier M/N value definitions according to the requested
- * OSC_CLK (Unit:Hz).
- */
-#if (OSC_CLK > 80000000)
-#define HFCGN    0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */
-#else
-#define HFCGN    0x02
-#endif
-#if   (OSC_CLK == 100000000)
-#define HFCGMH   0x0B
-#define HFCGML   0xEC
-#elif (OSC_CLK == 90000000)
-#define HFCGMH   0x0A
-#define HFCGML   0xBA
-#elif (OSC_CLK == 80000000)
-#define HFCGMH   0x09
-#define HFCGML   0x89
-#elif (OSC_CLK == 66000000)
-#define HFCGMH   0x0F
-#define HFCGML   0xBC
-#elif (OSC_CLK == 50000000)
-#define HFCGMH   0x0B
-#define HFCGML   0xEC
-#elif (OSC_CLK == 48000000)
-#define HFCGMH   0x0B
-#define HFCGML   0x72
-#elif (OSC_CLK == 40000000)
-#define HFCGMH   0x09
-#define HFCGML   0x89
-#elif (OSC_CLK == 33000000)
-#define HFCGMH   0x07
-#define HFCGML   0xDE
-#elif (OSC_CLK == 30000000)
-#define HFCGMH   0x07
-#define HFCGML   0x27
-#elif (OSC_CLK == 26000000)
-#define HFCGMH   0x06
-#define HFCGML   0x33
-#else
-#error "Unsupported OSC_CLK Frequency"
-#endif
-
-#if defined(CHIP_FAMILY_NPCX5)
-#if (OSC_CLK > 50000000)
-#error "Unsupported OSC_CLK on NPCX5 series!"
-#endif
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-#if (OSC_CLK > 100000000)
-#error "Unsupported OSC_CLK on NPCX series!"
-#endif
-#endif
-
-/**
- * Return the current FMUL clock frequency in Hz.
- */
-int clock_get_fm_freq(void);
-
-/**
- * Return the current APB1 clock frequency in Hz.
- */
-int clock_get_apb1_freq(void);
-
-/**
- * Return the current APB2 clock frequency in Hz.
- */
-int clock_get_apb2_freq(void);
-
-/**
- * Return the current APB3 clock frequency in Hz.
- */
-int clock_get_apb3_freq(void);
-
-/**
- * Set the CPU clock to maximum freq for better performance.
- */
-void clock_turbo(void);
-
-/**
- * Set the CPU clock back to normal freq.
- */
-void clock_turbo_disable(void);
-
-#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h
deleted file mode 100644
index 434caba1d8..0000000000
--- a/chip/npcx/config_chip-npcx5.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_CONFIG_CHIP_NPCX5_H
-#define __CROS_EC_CONFIG_CHIP_NPCX5_H
-
-/*
- * NPCX5 Series Device-Specific Information
- * Ex. NPCX5(M)(N)(G)
- * @param M: 7: 132-pins package, 8: 128-pins package
- * @param N: 5: 128KB RAM Size, 6: 256KB RAM Size
- * @param G: Google EC.
- */
-
-/* Chip ID for all variants */
-#define NPCX585G_CHIP_ID		0x12
-#define NPCX575G_CHIP_ID		0x13
-#define NPCX586G_CHIP_ID		0x16
-#define NPCX576G_CHIP_ID		0x17
-
-/*****************************************************************************/
-/* Hardware features */
-
-/* Number of UART modules. */
-#define UART_MODULE_COUNT 1
-
-/*
- * For NPCX5, PS2_3 pins also support other alternate functions (e.g., TA2).
- * PS2_3 should be Explicit defined.
- */
-#undef NPCX_PS2_MODULE_3
-
-/*
- * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
- * additional port.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-/* Number of I2C controllers */
-#define I2C_CONTROLLER_COUNT	4
-/* Number of I2C ports */
-#define I2C_PORT_COUNT		5
-
-/*****************************************************************************/
-/* Memory mapping */
-#define NPCX_BTRAM_SIZE		0x800 /* 2KB data ram used by booter. */
-#define CONFIG_RAM_BASE		0x200C0000 /* memory address of data ram */
-#define CONFIG_DATA_RAM_SIZE	0x00008000 /* Size of data RAM */
-#define CONFIG_RAM_SIZE		(CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
-#define CONFIG_LPRAM_BASE	0x40001600 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
-
-/* Use chip variant to specify the size and start address of program memory */
-#if defined(CHIP_VARIANT_NPCX5M5G)
-/* 96KB RAM for FW code */
-#define NPCX_PROGRAM_MEMORY_SIZE (96 * 1024)
-/* program memory base address for 96KB Code RAM (ie. 0x100C0000 - 96KB) */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000
-#elif defined(CHIP_VARIANT_NPCX5M6G)
-/* 224KB RAM for FW code */
-#define NPCX_PROGRAM_MEMORY_SIZE (224 * 1024)
-/* program memory base address for 224KB Code RAM (ie. 0x100C0000 - 224KB) */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x10088000
-#else
-#error "Unsupported chip variant"
-#endif
-
-/* Total RAM size checking for npcx ec */
-#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
-#if defined(CHIP_VARIANT_NPCX5M5G)
-/* 128KB RAM in NPCX5M5G */
-#if (NPCX_RAM_SIZE != 0x20000)
-#error "Wrong memory mapping layout for NPCX5M5G"
-#endif
-#elif defined(CHIP_VARIANT_NPCX5M6G)
-/* 256KB RAM in NPCX5M6G */
-#if (NPCX_RAM_SIZE != 0x40000)
-#error "Wrong memory mapping layout for NPCX5M6G"
-#endif
-#endif
-
-#endif /* __CROS_EC_CONFIG_CHIP_NPCX5_H */
diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h
deleted file mode 100644
index 434c3a7889..0000000000
--- a/chip/npcx/config_chip-npcx7.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_NPCX7_H
-#define __CROS_EC_CONFIG_CHIP_NPCX7_H
-
-/*
- * NPCX7 Series Device-Specific Information
- * Ex. NPCX7(M)(N)(G/K/F)(B/C)
- * @param M: 8: 128-pins package, 9: 144-pins package
- * @param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size
- * @param G/K/F/W: Google EC depends on specific features.
- * @param B/C: (Optional) Chip generation in the same series.
- */
-
-/* Chip ID for all variants */
-#define NPCX787G_CHIP_ID		0x1F
-#define NPCX796F_A_B_CHIP_ID		0x21
-#define NPCX796F_C_CHIP_ID		0x29
-#define NPCX797F_C_CHIP_ID		0x20
-#define NPCX797W_B_CHIP_ID		0x24
-#define NPCX797W_C_CHIP_ID		0x2C
-
-/*****************************************************************************/
-/* Hardware features */
-
-/* The optional hardware features depend on chip variant */
-#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
-#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
-#define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
-#endif
-
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
-	defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_UART_FIFO_SUPPORT
-/* Number of UART modules. */
-#define NPCX_SECOND_UART
-#define UART_MODULE_COUNT 2
-
-/*
- * For NPCX7, PS2_2 & PS2_3 pins also support other alternate functions
- * (e.g., ADC5, ADC6, TA2). PS2_2 & PS2_3 should be Explicit defined.
- */
-#undef NPCX_PS2_MODULE_2
-#undef NPCX_PS2_MODULE_3
-
-/* 64-bit timer support */
-#define NPCX_ITIM64_SUPPORT
-#else
-#define UART_MODULE_COUNT 1
-#endif
-
-#if defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_WOV_SUPPORT /* Audio front-end for Wake-on-Voice support */
-#endif
-
-/*
- * Number of I2C controllers. Controller 4/5/6 has 2 ports, so the chip has
- * three additional ports.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-/* Number of I2C controllers */
-#define I2C_CONTROLLER_COUNT 8
-/* Number of I2C ports */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define I2C_PORT_COUNT 10
-#else
-#define I2C_PORT_COUNT 11
-#endif
-
-#define NPCX_I2C_FIFO_SUPPORT
-
-/* Use SHI module version 2 supported by npcx7 family */
-#define NPCX_SHI_V2
-
-/*****************************************************************************/
-/* Memory mapping */
-#define NPCX_BTRAM_SIZE    0x800 /* 2KB data ram used by booter. */
-
-#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
-
-#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
-	/* 192KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* 62 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#elif defined(CHIP_VARIANT_NPCX7M7WB)
-	/* 256KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
-	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
-#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
-	/* 126 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00020000
-#elif defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
-	/*
-	 * Code RAM is normally assumed to be same as image size, but since
-	 * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we
-	 * need to explicitly configure it. This is the actual size of code
-	 * RAM on-chip.
-	 */
-#	define CONFIG_CODE_RAM_SIZE (256 * 1024)
-	/*
-	 * In npcx797wc and npcx797fc, the code RAM size is limited by the
-	 * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to
-	 * re-organize the memory to:
-	 * 1. the overall memory (RAM) layout is re-organized against the
-	 * datasheet:
-	 *     In datasheet: 320 KB code RAM + 64 KB data RAM
-	 *     After re-organization: 256 KB code RAM + 128 KB data RAM.
-	 * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the
-	 * -WB). After the boot header is added, a 256K image would be
-	 * too large to fit in either RO or RW sections of Flash (each
-	 * of which is half of it). Because other code assumes that
-	 * image size is a multiple of Flash erase granularity, we
-	 * sacrifice a whole sector.
-	 */
-#	define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000)
-	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
-#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
-	/* 126 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00020000
-
-	/*
-	 * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE
-	 * is not the actual size of code RAM.
-	 */
-#	undef NPCX_RAM_SIZE
-#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE)
-#else
-#	error "Unsupported chip variant"
-#endif
-
-#define CONFIG_RAM_SIZE         (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
-/* no low power ram in npcx7 series */
-
-#endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */
diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h
deleted file mode 100644
index 0248c40f86..0000000000
--- a/chip/npcx/config_chip-npcx9.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_NPCX9_H
-#define __CROS_EC_CONFIG_CHIP_NPCX9_H
-
-/*
- * NPCX9 Series Device-Specific Information
- * Ex. NPCX9(M)(N)(G/K/F)(B/C)
- * @param M: 9: 144-pins package
- * @param N: 3: 320KB RAM Size, 6: 256KB RAM Size.
- * @param F: Google EC.
- * @param B/C: (Optional) Chip generation in the same series.
- */
-
-/* Chip ID for all variants */
-#define NPCX996F_CHIP_ID		0x21
-#define NPCX993F_CHIP_ID		0x25
-
-/*****************************************************************************/
-/* Hardware features */
-
-#define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
-#define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
-#define NPCX_LCT_SUPPORT /* Long Countdown Timer support */
-#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
-
-#define NPCX_UART_FIFO_SUPPORT
-/* Number of UART modules. */
-#define NPCX_SECOND_UART
-#define UART_MODULE_COUNT 2
-
-/*
- * For NPCX9, PS2_2 & PS2_3 pins also support other alternate functions
- * (e.g., ADC5, ADC6, TA2). PS2_2 & PS2_3 should be Explicit defined.
- */
-#undef NPCX_PS2_MODULE_2
-#undef NPCX_PS2_MODULE_3
-
-/*
- * Number of I2C controllers. Controller 5/6 has 2 ports, so the chip has
- * two additional ports.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-/* Number of I2C controllers */
-#define I2C_CONTROLLER_COUNT 8
-#define I2C_PORT_COUNT 10
-
-#define NPCX_I2C_FIFO_SUPPORT
-
-/* Use SHI module version 2 supported by npcx7 and latter family */
-#define NPCX_SHI_V2
-
-/* PSL_OUT optional configuration */
-/* Set PSL_OUT mode to pulse mode */
-#define NPCX_PSL_CFG_PSL_OUT_PULSE	BIT(0)
-/* set PSL_OUT to open-drain */
-#define NPCX_PSL_CFG_PSL_OUT_OD		BIT(1)
-#define CONFIG_HIBERNATE_PSL_OUT_FLAGS	0
-
-
-#define CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-/*****************************************************************************/
-/* Memory mapping */
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-#define CONFIG_LPRAM_BASE	0x40001400 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
-#endif
-
-#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
-
-#if defined(CHIP_VARIANT_NPCX9M3F)
-	/*
-	 * 256KB program RAM, but only 512K of Flash. After the boot header is
-	 * added, a 256K image would be too large to fit in either RO or RW
-	 * sections of Flash (each of which is half of it). Because other code
-	 * assumes that image size is a multiple of Flash erase granularity, we
-	 * sacrifice a whole sector.
-	 */
-#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000)
-	/* program memory base address for Code RAM (0x100C0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10080000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
-
-	/* Override default NPCX_RAM_SIZE because we're excluding a block. */
-#	undef NPCX_RAM_SIZE
-#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \
-			      NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
-#elif defined(CHIP_VARIANT_NPCX9M6F)
-	/* 192KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
-#else
-#	error "Unsupported chip variant"
-#endif
-
-/* Internal spi-flash setting */
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */
-#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */
-
-
-#endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
deleted file mode 100644
index cee339206c..0000000000
--- a/chip/npcx/config_chip.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/*
- * Set the chip family version to 4 digits to keep the flexibility in case
- * we need the minor version for chip variants in a family.
- */
-#define NPCX_FAMILY_NPCX5        5000
-#define NPCX_FAMILY_NPCX7        7000
-#define NPCX_FAMILY_NPCX9        9000
-
-/* Features depend on chip family */
-#if defined(CHIP_FAMILY_NPCX5)
-#include "config_chip-npcx5.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX5
-#elif defined(CHIP_FAMILY_NPCX7)
-#include "config_chip-npcx7.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX7
-#elif defined(CHIP_FAMILY_NPCX9)
-#include "config_chip-npcx9.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX9
-#else
-#error "Unsupported chip family"
-#endif
-
-/* 32k hz internal oscillator frequency (FRCLK) */
-#define INT_32K_CLOCK 32768
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 64
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 1024
-
-/*
- * Interval between HOOK_TICK notifications
- * Notice instant wake-up from deep-idle cannot exceed 200 ms
- */
-#define HOOK_TICK_INTERVAL_MS 200
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* System stack size */
-#define CONFIG_STACK_SIZE       1024
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		672
-#define LARGER_TASK_STACK_SIZE		800
-#define VENTI_TASK_STACK_SIZE		928
-#define ULTRA_TASK_STACK_SIZE		1056
-#define TRENTA_TASK_STACK_SIZE		1184
-
-#define CHARGER_TASK_STACK_SIZE		800
-#define HOOKS_TASK_STACK_SIZE		800
-#define CONSOLE_TASK_STACK_SIZE		800
-
-/* Default task stack size */
-#define TASK_STACK_SIZE			672
-
-/* Address of RAM log used by Booter */
-#define ADDR_BOOT_RAMLOG        0x100C7FC0
-
-#include "config_flash_layout.h"
-
-/* Optional features present on this chip */
-#define CONFIG_ADC
-#define CONFIG_RTC
-#define CONFIG_SWITCH
-#define CONFIG_MPU
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-/* Default use UART1 as console */
-#define CONFIG_CONSOLE_UART    0
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
deleted file mode 100644
index 79961548c9..0000000000
--- a/chip/npcx/config_flash_layout.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
-#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
-
-/*
- * npcx flash layout:
- * - Memory-mapped external SPI.
- * - Image header at the beginning of protected region, followed by RO image.
- * - RW image starts at the second half of flash.
- */
-
-/* Memmapped, external SPI */
-#define CONFIG_EXTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-/* Storage is memory-mapped, but program runs from SRAM */
-#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
-#undef  CONFIG_FLASH_PSTATE
-
-#if defined(CHIP_VARIANT_NPCX5M5G)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
-#elif defined(CHIP_VARIANT_NPCX5M6G)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) || \
-	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-#elif defined(CHIP_VARIANT_NPCX7M7WB)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x80000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x80000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x80000
-#elif defined(CHIP_VARIANT_NPCX9M3F) || defined(CHIP_VARIANT_NPCX9M6F)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-#else
-#error "Unsupported chip variant"
-#endif
-
-/* Header support which is used by booter to copy FW from flash to code ram */
-#define NPCX_RO_HEADER
-#define CONFIG_RO_HDR_MEM_OFF	0x0
-#define CONFIG_RO_HDR_SIZE	0x40
-
-#define CONFIG_WP_STORAGE_OFF	CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE	CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* RO firmware in program memory - use all of program memory */
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		NPCX_PROGRAM_MEMORY_SIZE
-
-/*
- * ROM resident area in flash used to store data objects that are not copied
- * into code RAM. Enable using the CONFIG_CHIP_INIT_ROM_REGION option.
- */
-#define CONFIG_RO_ROM_RESIDENT_MEM_OFF	CONFIG_RO_SIZE
-#define CONFIG_RO_ROM_RESIDENT_SIZE \
-	(CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_RO_SIZE)
-
-/*
- * RW firmware in program memory - Identical to RO, only one image loaded at
- * a time.
- */
-#define CONFIG_RW_MEM_OFF	CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE		CONFIG_RO_SIZE
-
-#define CONFIG_RW_ROM_RESIDENT_MEM_OFF	CONFIG_RW_SIZE
-#define CONFIG_RW_ROM_RESIDENT_SIZE \
-	(CONFIG_EC_WRITABLE_STORAGE_SIZE - CONFIG_RW_SIZE)
-
-#if (CONFIG_RO_SIZE != CONFIG_RW_SIZE)
-#error "Unsupported.. FLASH_ERASE_SIZE assumes RO and RW size is same!"
-#endif
-
-#if (CONFIG_RO_MEM_OFF != 0)
-#error "Unsupported.. CONFIG_RO_MEM_OFF is assumed to be 0!"
-#endif
-
-/*
- * The common flash support requires that the CONFIG_WP_STORAGE_SIZE and
- * CONFIG_EC_WRITABLE_STORAGE_SIZE are both a multiple of
- * CONFIG_FLASH_ERASE_SIZE.
- *
- * THE NPCX supports erase sizes of 64 KiB, 32 KiB, and 4 KiB. The NPCX flash
- * driver does not currently support CONFIG_FLASH_MULTIPLE_REGION, so set
- * the erase size to the maximum (64 KiB) for the best performance.
- * Using smaller erase sizes increases boot time. If write protected and
- * writable flash regions are not a multiple of 64 KiB, then support
- * for CONFIG_FLASH_MULTIPLE_REGION must be added.
- */
-#define CONFIG_FLASH_ERASE_SIZE		0x10000
-#define NPCX_ERASE_COMMAND		CMD_BLOCK_64K_ERASE
-
-#if (CONFIG_WP_STORAGE_SIZE != CONFIG_EC_WRITABLE_STORAGE_SIZE)
-#error "NPCX flash support assumes CONFIG_WP_STORAGE_SIZE and " \
-	"CONFIG_EC_WRITABLE_STORAGE_SIZE are the same."
-#endif
-
-/*
- * If the total flash size is not a multiple of 64k, this slows the boot
- * time. CONFIG_FLASH_MULTIPLE_REGION should be enabled in this case to
- * optimize the erase block handling.
- */
-#if ((CONFIG_WP_STORAGE_SIZE % CONFIG_FLASH_ERASE_SIZE) != 0)
-#error "CONFIG_WP_STORAGE_SIZE is not a multiple of 64K. Correct the flash " \
-	"size or add support for CONFIG_FLASH_MULTIPLE_REGION."
-#endif
-
-#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
-#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
-
-/* Use 4k sector erase for NPCX monitor flash erase operations. */
-#define NPCX_MONITOR_FLASH_ERASE_SIZE	0x1000
-
-/* RO image resides at start of protected region, right after header */
-#define CONFIG_RO_STORAGE_OFF	CONFIG_RO_HDR_SIZE
-/* RW image resides at start of writable region */
-#define CONFIG_RW_STORAGE_OFF	0
-
-#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c
deleted file mode 100644
index c8976afed0..0000000000
--- a/chip/npcx/espi.c
+++ /dev/null
@@ -1,704 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ESPI module for Chrome EC */
-
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "chipset.h"
-#include "console.h"
-#include "uart.h"
-#include "util.h"
-#include "power.h"
-#include "espi.h"
-#include "lpc_chip.h"
-#include "hooks.h"
-#include "timer.h"
-
-/* Console output macros */
-#if !(DEBUG_ESPI)
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#endif
-
-/* Default eSPI configuration for VW events */
-struct vwevms_config_t {
-	uint8_t idx;        /* VW index */
-	uint8_t idx_en;     /* Index enable */
-	uint8_t pltrst_en;  /* Enable reset by PLTRST assert */
-	uint8_t espirst_en; /* Enable reset by eSPI_RST assert */
-	uint8_t int_en;     /* Interrupt/Wake-up enable */
-};
-
-struct vwevsm_config_t {
-	uint8_t idx;        /* VW index */
-	uint8_t idx_en;     /* Index enable */
-	uint8_t pltrst_en;  /* Enable reset by PLTRST assert */
-	uint8_t cdrst_en;   /* Enable cold reset */
-	uint8_t valid;      /* Valid VW mask */
-};
-
-/* Default MIWU configurations for VW events */
-struct host_wui_item {
-	uint16_t table : 2; /* MIWU table 0-2 */
-	uint16_t group : 3; /* MIWU group 0-7 */
-	uint16_t num   : 3; /* MIWU bit   0-7 */
-	uint16_t edge  : 4; /* MIWU edge trigger type rising/falling/any */
-};
-
-/* Mapping item between VW signal, index and value */
-struct vw_event_t {
-	uint16_t name;     /* Name of signal */
-	uint8_t  evt_idx;  /* VW index of signal */
-	uint8_t  evt_val;  /* VW value of signal */
-};
-
-/* Default settings of VWEVMS registers (Please refer Table.43/44) */
-static const struct vwevms_config_t espi_in_list[] = {
-	/* IDX EN ENPL ENESP IE/WE          VW Event Bit 0 - 3 (M->S)         */
-#ifdef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-	{0x02,  1,  0,  1,  1},  /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
-#else
-	{0x02,  1,  0,  0,  1},  /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
-#endif
-	{0x03,  1,  0,  1,  1},  /* SUS_STAT#, PLTRST#,    ORST_WARN, Reserve */
-	{0x07,  1,  1,  1,  1},  /* HRST_WARN, SMIOUT#,    NMIOUT#,   Reserve */
-	{0x41,  1,  0,  1,  1},  /* SUS_WARN#, SPWRDN_ACK, Reserve,   SLP_A#  */
-	{0x42,  1,  0,  0,  1},  /* SLP_LAN#,  SLP_WAN#,   Reserve,   Reserve */
-	{0x47,  1,  1,  1,  1},  /* HOST_C10,  Reserve,    Reserve,   Reserve */
-};
-
-/* Default settings of VWEVSM registers (Please refer Table.43/44) */
-static const struct vwevsm_config_t espi_out_list[] = {
-	/* IDX EN ENPL ENCDR VDMASK         VW Event Bit 0 - 3 (S->M)         */
-	{0x04,  1,  0,  0, 0x0D}, /* ORST_ACK,   Reserve, WAKE#,   PME#       */
-	{0x05,  1,  0,  0, 0x0F}, /* SLV_BL_DNE, ERR_F,   ERR_NF,  SLV_BL_STS */
-#ifdef CONFIG_SCI_GPIO
-	{0x06,  1,  1,  0, 0x0C}, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
-#else
-	{0x06,  1,  1,  0, 0x0F}, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
-#endif
-	{0x40,  1,  0,  0, 0x01}, /* SUS_ACK,    Reserve, Reserve, Reserve    */
-};
-
-/* eSPI interrupts used in MIWU */
-static const struct host_wui_item espi_vw_int_list[] = {
-	/* ESPI_RESET  */
-	{MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING},
-	/* SLP_S3 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING},
-	/* SLP_S4 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING},
-	/* SLP_S5 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING},
-	/* VW_WIRE_PLTRST */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING},
-	/* VW_WIRE_OOB_RST_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING},
-	/* VW_WIRE_HOST_RST_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING},
-	/* VW_WIRE_SUS_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING},
-};
-
-/* VW signals used in eSPI */
-static const struct vw_event_t vw_events_list[] = {
-	{VW_SLP_S3_L,                    0x02,   0x01},	/* index 02h (In)  */
-	{VW_SLP_S4_L,                    0x02,   0x02},
-	{VW_SLP_S5_L,                    0x02,   0x04},
-	{VW_SUS_STAT_L,                  0x03,   0x01},	/* index 03h (In)  */
-	{VW_PLTRST_L,                    0x03,   0x02},
-	{VW_OOB_RST_WARN,                0x03,   0x04},
-	{VW_OOB_RST_ACK,                 0x04,   0x01},	/* index 04h (Out) */
-	{VW_WAKE_L,                      0x04,   0x04},
-	{VW_PME_L,                       0x04,   0x08},
-	{VW_ERROR_FATAL,                 0x05,   0x02},	/* index 05h (Out) */
-	{VW_ERROR_NON_FATAL,             0x05,   0x04},
-	{VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05,   0x09},
-	{VW_SCI_L,                       0x06,   0x01},	/* index 06h (Out) */
-	{VW_SMI_L,                       0x06,   0x02},
-	{VW_RCIN_L,                      0x06,   0x04},
-	{VW_HOST_RST_ACK,                0x06,   0x08},
-	{VW_HOST_RST_WARN,               0x07,   0x01},	/* index 07h (In)  */
-	{VW_SUS_ACK,                     0x40,   0x01},	/* index 40h (Out) */
-	{VW_SUS_WARN_L,                  0x41,   0x01},	/* index 41h (In)  */
-	{VW_SUS_PWRDN_ACK_L,             0x41,   0x02},
-	{VW_SLP_A_L,                     0x41,   0x08},
-	{VW_SLP_LAN,                     0x42,   0x01},	/* index 42h (In)  */
-	{VW_SLP_WLAN,                    0x42,   0x02},
-};
-
-/* Flag for boot load signals */
-static uint8_t boot_load_done;
-
-/*****************************************************************************/
-/* eSPI internal utilities */
-
-/* Recovery utility for eSPI reset */
-static void espi_reset_recovery(void)
-{
-	/* TODO: Put recovery stuff related to eSPI reset here */
-
-	/* Clear boot load flag */
-	boot_load_done = 0;
-}
-
-/* Configure Controller-to-Peripheral virtual wire inputs */
-static void espi_vw_config_in(const struct vwevms_config_t *config)
-{
-	uint32_t val;
-	uint8_t  i, index;
-
-	switch (VM_TYPE(config->idx)) {
-	case ESPI_VW_TYPE_SYS_EV:
-	case ESPI_VW_TYPE_PLT:
-		for (i = 0; i < ESPI_VWEVMS_NUM; i++) {
-			index = VWEVMS_IDX_GET(NPCX_VWEVMS(i));
-			/* Set VW input register */
-			if (index == config->idx) {
-				/* Get Wire field */
-				val = NPCX_VWEVMS(i) & 0x0F;
-				val |= VWEVMS_FIELD(config->idx,
-						config->idx_en,
-						config->pltrst_en,
-						config->int_en,
-						config->espirst_en);
-				NPCX_VWEVMS(i) = val;
-				return;
-			}
-		}
-		CPRINTS("No match index of all VWEVMSs");
-		break;
-	default:
-		CPRINTS("No support type of VWEVMS");
-		break;
-	}
-}
-
-/* Configure Peripheral-to-Controller virtual wire outputs */
-static void espi_vw_config_out(const struct vwevsm_config_t *config)
-{
-	uint32_t val;
-	uint8_t i, index;
-
-	switch (VM_TYPE(config->idx)) {
-	case ESPI_VW_TYPE_SYS_EV:
-	case ESPI_VW_TYPE_PLT:
-		for (i = 0; i < ESPI_VWEVSM_NUM; i++) {
-			index = VWEVSM_IDX_GET(NPCX_VWEVSM(i));
-			/* Set VW output register */
-			if (index == config->idx) {
-				/* Preserve WIRE(3-0) and HW_WIRE (27-24). */
-				val = NPCX_VWEVSM(i) & 0x0F00000F;
-				val |= VWEVSM_FIELD(config->idx,
-						config->idx_en,
-						config->valid,
-						config->pltrst_en,
-						config->cdrst_en);
-				NPCX_VWEVSM(i) = val;
-				return;
-			}
-		}
-		CPRINTS("No match index of all VWEVSMs");
-		break;
-	default:
-		CPRINTS("No support type of VWEVSM");
-		break;
-	}
-}
-
-/* Config Controller-to-Peripheral VWire interrupt edge type and enable it */
-static void espi_enable_vw_int(const struct host_wui_item *vwire_int)
-{
-	uint8_t table = vwire_int->table;
-	uint8_t group = vwire_int->group;
-	uint8_t num   = vwire_int->num;
-	uint8_t edge  = vwire_int->edge;
-
-	/* Set detection mode to edge */
-	CLEAR_BIT(NPCX_WKMOD(table, group), num);
-
-	if (edge != MIWU_EDGE_ANYING) {
-		/* Disable Any Edge */
-		CLEAR_BIT(NPCX_WKAEDG(table, group), num);
-		/* Enable Rising Edge */
-		if (edge == MIWU_EDGE_RISING)
-			CLEAR_BIT(NPCX_WKEDG(table, group), num);
-		/* Enable Falling Edge */
-		else
-			SET_BIT(NPCX_WKEDG(table, group), num);
-	} else
-		/* enable Any Edge */
-		SET_BIT(NPCX_WKAEDG(table, group), num);
-
-	/* Clear the pending bit */
-	NPCX_WKPCL(table, group) = BIT(num);
-
-	/* Enable wake-up input sources */
-	SET_BIT(NPCX_WKEN(table, group), num);
-}
-
-/* Get vw index & value information by signal */
-static int espi_vw_get_signal_index(enum espi_vw_signal event)
-{
-	int index;
-
-	/* Find the vw index by signal name first */
-	for (index = 0; index < ARRAY_SIZE(vw_events_list); index++) {
-		if (vw_events_list[index].name == event)
-			break;
-	}
-	/* Cannot find the index */
-	if (index == ARRAY_SIZE(vw_events_list))
-		return -1;
-
-	return index;
-}
-
-/* The ISRs of VW signals which used for power sequences */
-void espi_vw_power_signal_interrupt(enum espi_vw_signal signal)
-{
-	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL))
-		/* TODO: Add VW handler in power/common.c */
-		power_signal_interrupt((enum gpio_signal) signal);
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/**
- * Set eSPI Virtual-Wire signal to Host
- *
- * @param signal vw signal needs to set
- * @param level  level of vw signal
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
-{
-	uint8_t offset, value;
-	int sig_idx;
-
-	/* Get index of vw signal list by signale name */
-	sig_idx = espi_vw_get_signal_index(signal);
-
-	/* Cannot find index by signal name */
-	if (sig_idx < 0)
-		return EC_ERROR_PARAM1;
-
-	/* Find the output register offset by vw index */
-	for (offset = 0; offset < ESPI_VWEVSM_NUM; offset++) {
-		uint8_t vw_idx = VWEVSM_IDX_GET(NPCX_VWEVSM(offset));
-		/* If index matches. break */
-		if (vw_idx == vw_events_list[sig_idx].evt_idx)
-			break;
-	}
-
-	/* Cannot match index */
-	if (offset == ESPI_VWEVSM_NUM)
-		return EC_ERROR_PARAM1;
-
-	value = GET_FIELD(NPCX_VWEVSM(offset), NPCX_VWEVSM_WIRE);
-	/* Set wire */
-	if (level)
-		value |= vw_events_list[sig_idx].evt_val;
-	else /* Clear wire */
-		value &= (~vw_events_list[sig_idx].evt_val);
-
-	SET_FIELD(NPCX_VWEVSM(offset), NPCX_VWEVSM_WIRE, value);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Get eSPI Virtual-Wire signal from host
- *
- * @param signal vw signal needs to get
- * @return      1: set by host, otherwise: no signal
- */
-int espi_vw_get_wire(enum espi_vw_signal signal)
-{
-	uint8_t offset, value;
-	int sig_idx;
-
-	/* Get index of vw signal list by signale name */
-	sig_idx = espi_vw_get_signal_index(signal);
-
-	/* Cannot find index by signal name */
-	if (sig_idx < 0)
-		return -1;
-
-	/* Find the input register offset by vw index */
-	for (offset = 0; offset < ESPI_VWEVMS_NUM; offset++) {
-		uint8_t vw_idx = VWEVMS_IDX_GET(NPCX_VWEVMS(offset));
-		/* If index matches. break */
-		if (vw_idx == vw_events_list[sig_idx].evt_idx)
-			break;
-	}
-
-	/* Cannot match index */
-	if (offset == ESPI_VWEVMS_NUM)
-		return -1;
-
-	/* Get wire & check with valid bits */
-	value = GET_FIELD(NPCX_VWEVMS(offset), NPCX_VWEVMS_WIRE);
-	value &= GET_FIELD(NPCX_VWEVMS(offset), NPCX_VWEVMS_VALID);
-
-	return !!(value & vw_events_list[sig_idx].evt_val);
-}
-
-/**
- * Enable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to enable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_enable_wire_int(enum espi_vw_signal signal)
-{
-	if (signal == VW_SLP_S3_L)
-		SET_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 0);
-	else if (signal == VW_SLP_S4_L)
-		SET_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 1);
-	else if (signal == VW_SLP_S5_L)
-		SET_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 2);
-	else
-		return EC_ERROR_PARAM1;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Disable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to disable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_disable_wire_int(enum espi_vw_signal signal)
-{
-	if (signal == VW_SLP_S3_L)
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 0);
-	else if (signal == VW_SLP_S4_L)
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 1);
-	else if (signal == VW_SLP_S5_L)
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 2);
-	else
-		return EC_ERROR_PARAM1;
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* VW event handlers */
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void espi_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(espi_chipset_reset);
-#endif
-
-/* PLTRST# event handler */
-void espi_vw_evt_pltrst(void)
-{
-	int pltrst = espi_vw_get_wire(VW_PLTRST_L);
-
-	CPRINTS("VW PLTRST: %d", pltrst);
-
-	if (pltrst) {
-		/* PLTRST# deasserted */
-#if defined(CHIP_FAMILY_NPCX5)
-		/* See errata 2.22 */
-
-		/* Disable eSPI peripheral channel support first */
-		CLEAR_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCCHN_SUPP);
-
-		/* Initialize host settings */
-		host_register_init();
-
-		/* Enable eSPI peripheral channel */
-		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCHANEN);
-
-		/* Re-enable eSPI peripheral channel support */
-		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCCHN_SUPP);
-#else
-		/* Initialize host settings */
-		host_register_init();
-
-		/* Enable eSPI peripheral channel */
-		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCHANEN);
-#endif
-	} else {
-		/* PLTRST# asserted */
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-		hook_call_deferred(&espi_chipset_reset_data, MSEC);
-#endif
-	}
-}
-
-/* SLP_Sx event handler */
-void espi_vw_evt_slp_s3(void)
-{
-	CPRINTS("VW SLP_S3: %d", espi_vw_get_wire(VW_SLP_S3_L));
-	espi_vw_power_signal_interrupt(VW_SLP_S3_L);
-}
-
-void espi_vw_evt_slp_s4(void)
-{
-	CPRINTS("VW SLP_S4: %d", espi_vw_get_wire(VW_SLP_S4_L));
-	espi_vw_power_signal_interrupt(VW_SLP_S4_L);
-}
-
-void espi_vw_evt_slp_s5(void)
-{
-	CPRINTS("VW SLP_S5: %d", espi_vw_get_wire(VW_SLP_S5_L));
-	espi_vw_power_signal_interrupt(VW_SLP_S5_L);
-}
-
-/* OOB Reset event handler */
-void espi_vw_evt_oobrst(void)
-{
-	CPRINTS("VW OOB_RST: %d", espi_vw_get_wire(VW_OOB_RST_WARN));
-
-	/* Send ACK to host by WARN#'s wire */
-	espi_vw_set_wire(VW_OOB_RST_ACK, espi_vw_get_wire(VW_OOB_RST_WARN));
-}
-
-/* SUS_WARN# event handler */
-void espi_vw_evt_sus_warn(void)
-{
-	CPRINTS("VW SUS_WARN#: %d", espi_vw_get_wire(VW_SUS_WARN_L));
-
-	udelay(100);
-
-	/* Send ACK to host by WARN#'s wire */
-	espi_vw_set_wire(VW_SUS_ACK, espi_vw_get_wire(VW_SUS_WARN_L));
-}
-
-/* HOSTRST WARN event handler */
-void espi_vw_evt_hostrst_warn(void)
-{
-	CPRINTS("VW HOST_RST_WARN#: %d", espi_vw_get_wire(VW_HOST_RST_WARN));
-
-	/* Send ACK to host by WARN#'s wire */
-	espi_vw_set_wire(VW_HOST_RST_ACK, espi_vw_get_wire(VW_HOST_RST_WARN));
-}
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/* eSPI reset assert/de-assert interrupt */
-void espi_espirst_handler(void)
-{
-	/* Clear pending bit of WUI */
-	SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 5);
-
-	CPRINTS("eSPI RST issued!");
-}
-
-/* Handle eSPI virtual wire interrupt 1 */
-void __espi_wk2a_interrupt(void)
-{
-	uint8_t pending_bits = NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_1);
-
-	/* Clear pending bits of MIWU */
-	NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_1) = pending_bits;
-
-	/* Handle events of virtual-wire */
-	if (IS_BIT_SET(pending_bits, 0))
-		espi_vw_evt_slp_s3();
-	if (IS_BIT_SET(pending_bits, 1))
-		espi_vw_evt_slp_s4();
-	if (IS_BIT_SET(pending_bits, 2))
-		espi_vw_evt_slp_s5();
-	if (IS_BIT_SET(pending_bits, 5))
-		espi_vw_evt_pltrst();
-	if (IS_BIT_SET(pending_bits, 6))
-		espi_vw_evt_oobrst();
-}
-DECLARE_IRQ(NPCX_IRQ_WKINTA_2, __espi_wk2a_interrupt, 3);
-
-/* Handle eSPI virtual wire interrupt 2 */
-void __espi_wk2b_interrupt(void)
-{
-	uint8_t pending_bits = NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_2);
-
-	/* Clear pending bits of MIWU */
-	NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_2) = pending_bits;
-
-	/* Handle events of virtual-wire */
-	if (IS_BIT_SET(pending_bits, 4))
-		espi_vw_evt_sus_warn();
-	if (IS_BIT_SET(pending_bits, 0))
-		espi_vw_evt_hostrst_warn();
-}
-DECLARE_IRQ(NPCX_IRQ_WKINTB_2, __espi_wk2b_interrupt, 3);
-
-/* Interrupt handler for eSPI status changed */
-void espi_interrupt(void)
-{
-	int chan;
-	uint32_t mask, status;
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	/*
-	 * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask
-	 * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR.
-	 */
-	mask = NPCX_ESPIIE | BIT(NPCX_ESPISTS_VWUPDW);
-#else
-	mask = NPCX_ESPIIE;
-#endif
-	status = NPCX_ESPISTS & mask;
-
-	while (status) {
-		/* Clear pending bits first */
-		NPCX_ESPISTS = status;
-
-		if (IS_BIT_SET(status, NPCX_ESPISTS_BERR))
-			/* Always print eSPI Bus Errors */
-			cprints(CC_LPC, "eSPI Bus Error");
-
-		/* eSPI inband reset(from VW) */
-		if (IS_BIT_SET(status, NPCX_ESPISTS_IBRST)) {
-			CPRINTS("eSPI RST inband RST");
-			espi_reset_recovery();
-
-		} /* eSPI reset (from eSPI_rst pin) */
-		else if (IS_BIT_SET(status, NPCX_ESPISTS_ESPIRST)) {
-			CPRINTS("eSPI RST");
-			chipset_handle_espi_reset_assert();
-			espi_reset_recovery();
-		}
-
-		/* eSPI configuration is updated */
-		if (IS_BIT_SET(status, NPCX_ESPISTS_CFGUPD)) {
-			/*
-			 * If host enable/disable channel for VW/OOB/FLASH, EC
-			 * should follow except Peripheral channel. It is
-			 * handled by PLTRST separately.
-			 */
-			for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT;
-					chan++) {
-				if (!IS_PERIPHERAL_CHAN_ENABLE(chan) &&
-						IS_HOST_CHAN_EN(chan))
-					ENABLE_ESPI_CHAN(chan);
-				else if (IS_PERIPHERAL_CHAN_ENABLE(chan) &&
-						!IS_HOST_CHAN_EN(chan))
-					DISABLE_ESPI_CHAN(chan);
-			}
-
-			/*
-			 * Send BOOTLOAD_DONE and BOOTLOAD_STATUS
-			 * events to host simultaneously. To indicate the
-			 * completion of EC firmware code loading.
-			 */
-			if (boot_load_done == 0 &&
-			    IS_PERIPHERAL_CHAN_ENABLE(NPCX_ESPI_CH_VW)) {
-
-				espi_vw_set_wire(
-					VW_PERIPHERAL_BTLD_STATUS_DONE, 1);
-				boot_load_done = 1;
-			}
-		}
-
-		/* Any VW signal sent by Host - leave it, handle in MIWU ISR */
-		if (IS_BIT_SET(status, NPCX_ESPISTS_VWUPD))
-			CPRINTS("VW Updated INT");
-
-		/* Get status again */
-		status = NPCX_ESPISTS & mask;
-	}
-}
-DECLARE_IRQ(NPCX_IRQ_ESPI, espi_interrupt, 4);
-
-/*****************************************************************************/
-/* eSPI Initialization functions */
-void espi_init(void)
-{
-	int i;
-
-	/* Support all channels */
-	NPCX_ESPICFG |= ESPI_SUPP_CH_ALL;
-
-	/* Support all I/O modes */
-	SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_IOMODE_FIELD,
-		NPCX_ESPI_IO_MODE_ALL);
-
-	/* Set eSPI speed to max supported */
-	SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD,
-		  NPCX_ESPI_MAXFREQ_MAX);
-
-	/* Configure Controller-to-Peripheral Virtual Wire indexes (Inputs) */
-	for (i = 0; i < ARRAY_SIZE(espi_in_list); i++)
-		espi_vw_config_in(&espi_in_list[i]);
-
-	/* Configure Peripheral-to-Controller Virtual Wire indexes (Outputs) */
-	for (i = 0; i < ARRAY_SIZE(espi_out_list); i++)
-		espi_vw_config_out(&espi_out_list[i]);
-
-	/* Configure MIWU for eSPI VW */
-	for (i = 0; i < ARRAY_SIZE(espi_vw_int_list); i++)
-		espi_enable_vw_int(&espi_vw_int_list[i]);
-}
-
-static int command_espi(int argc, char **argv)
-{
-	uint32_t chan;
-	char *e;
-
-	if (argc == 1) {
-		return EC_ERROR_INVAL;
-	/* Get value of eSPI registers */
-	} else if (argc == 2) {
-		int i;
-
-		if (strcasecmp(argv[1], "cfg") == 0) {
-			ccprintf("ESPICFG [0x%08x]\n", NPCX_ESPICFG);
-		} else if (strcasecmp(argv[1], "vsm") == 0) {
-			for (i = 0; i < ESPI_VWEVSM_NUM; i++) {
-				uint32_t val = NPCX_VWEVSM(i);
-				uint8_t  idx = VWEVSM_IDX_GET(val);
-
-				ccprintf("VWEVSM%d: %02x [0x%08x]\n", i, idx,
-						val);
-			}
-		} else if (strcasecmp(argv[1], "vms") == 0) {
-			for (i = 0; i < ESPI_VWEVMS_NUM; i++) {
-				uint32_t val = NPCX_VWEVMS(i);
-				uint8_t  idx = VWEVMS_IDX_GET(val);
-
-				ccprintf("VWEVMS%d: %02x [0x%08x]\n", i, idx,
-						val);
-			}
-		}
-	/* Enable/Disable the channels of eSPI */
-	} else if (argc == 3) {
-		uint32_t m = (uint32_t) strtoi(argv[2], &e, 0);
-
-		if (*e)
-			return EC_ERROR_PARAM2;
-		if (m > 4)
-			return EC_ERROR_PARAM2;
-		else if (m == 4)
-			chan = 0x0F;
-		else
-			chan = 0x01 << m;
-		if (strcasecmp(argv[1], "en") == 0)
-			NPCX_ESPICFG = NPCX_ESPICFG | chan;
-		else if (strcasecmp(argv[1], "dis") == 0)
-			NPCX_ESPICFG = NPCX_ESPICFG & ~chan;
-		else
-			return EC_ERROR_PARAM1;
-		ccprintf("ESPICFG [0x%08x]\n", NPCX_ESPICFG);
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(espi, command_espi,
-			"cfg/vms/vsm/en/dis [channel]",
-			"eSPI configurations");
diff --git a/chip/npcx/fan.c b/chip/npcx/fan.c
deleted file mode 100644
index f0b3215ce0..0000000000
--- a/chip/npcx/fan.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX fan control module. */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "util.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "console.h"
-#include "timer.h"
-#include "task.h"
-#include "hooks.h"
-#include "system.h"
-#include "math_util.h"
-
-#if !(DEBUG_FAN)
-#define CPRINTS(...)
-#else
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-#endif
-
-/* Tacho measurement state */
-enum tacho_measure_state {
-	/* Tacho normal state */
-	TACHO_NORMAL = 0,
-	/* Tacho underflow state */
-	TACHO_UNDERFLOW
-};
-
-/* Fan mode */
-enum tacho_fan_mode {
-	/* FAN rpm mode */
-	TACHO_FAN_RPM = 0,
-	/* FAN duty mode */
-	TACHO_FAN_DUTY,
-};
-
-/* Fan status data structure */
-struct fan_status_t {
-	/* Current state of the measurement */
-	enum tacho_measure_state cur_state;
-	/* Fan mode */
-	enum tacho_fan_mode fan_mode;
-	/* MFT sampling freq*/
-	uint32_t mft_freq;
-	/* Actual rpm */
-	int rpm_actual;
-	/* Target rpm */
-	int rpm_target;
-	/* Automatic fan status */
-	enum fan_status auto_status;
-};
-
-/* Global variables */
-static volatile struct fan_status_t fan_status[FAN_CH_COUNT];
-static int rpm_pre[FAN_CH_COUNT];
-
-/*
- * Fan specifications. If they (PULSES_ROUND and RPM_DEVIATION) cannot meet
- * the followings, please replace them with correct one in board-level driver.
- */
-
-/* Pulses per round */
-#ifndef PULSES_ROUND
-#define PULSES_ROUND 2 /* 4-phases pwm-type fan. (2-phases should be 1) */
-#endif
-
-/* Rpm deviation (Unit:percent) */
-#ifndef RPM_DEVIATION
-#define RPM_DEVIATION 7
-#endif
-
-/*
- * RPM = 60 * f / (n * TACH)
- *   n = Pulses per round
- *   f = Tachometer (MFT) operation freq
- *   TACH = Counts of tachometer
- */
-#define TACH_TO_RPM(ch, tach) \
-	((fan_status[ch].mft_freq * 60 / PULSES_ROUND) / MAX((tach), 1))
-
-/* MFT TCNT default count */
-#define TACHO_MAX_CNT (BIT(16) - 1)
-
-/* Margin of target rpm */
-#define RPM_MARGIN(rpm_target) (((rpm_target) * RPM_DEVIATION) / 100)
-
-/**
- * MFT get fan rpm value
- *
- * @param   ch      operation channel
- * @return  actual  rpm
- */
-static int mft_fan_rpm(int ch)
-{
-	volatile struct fan_status_t *p_status = fan_status + ch;
-	int mdl = mft_channels[ch].module;
-	int tacho;
-
-	/* Check whether MFT underflow flag is occurred */
-	if (IS_BIT_SET(NPCX_TECTRL(mdl), NPCX_TECTRL_TCPND)) {
-		/* Clear pending flags */
-		SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TCCLR);
-
-		/*
-		 * Flag TDPND means mft underflow happen,
-		 * but let MFT still can re-measure actual rpm
-		 * when user change pwm/fan duty during
-		 * TACHO_UNDERFLOW state.
-		 */
-		p_status->cur_state = TACHO_UNDERFLOW;
-		p_status->auto_status = FAN_STATUS_STOPPED;
-		CPRINTS("Tacho is underflow !");
-
-		return 0;
-	}
-
-	/* Check whether MFT capture flag is set, else return previous rpm */
-	if (IS_BIT_SET(NPCX_TECTRL(mdl), NPCX_TECTRL_TAPND))
-		/* Clear pending flags */
-		SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TACLR);
-	else
-		return p_status->rpm_actual;
-
-	p_status->cur_state = TACHO_NORMAL;
-	/*
-	 * Start of the last tacho cycle is detected -
-	 * calculated tacho cycle duration
-	 */
-	tacho = TACHO_MAX_CNT - NPCX_TCRA(mdl);
-	/* Transfer tacho to actual rpm */
-	return (tacho > 0) ? (TACH_TO_RPM(ch, tacho)) : 0;
-}
-
-/**
- * Set fan prescaler based on apb1 clock
- *
- * @param   none
- * @return  none
- * @notes   changed when initial or HOOK_FREQ_CHANGE command
- */
-void mft_set_apb1_prescaler(int ch)
-{
-	int mdl = mft_channels[ch].module;
-	uint16_t prescaler_divider = 0;
-
-	/* Set clock prescaler divider to MFT module*/
-	prescaler_divider = (uint16_t)(clock_get_apb1_freq()
-			/ fan_status[ch].mft_freq);
-	if (prescaler_divider >= 1)
-		prescaler_divider = prescaler_divider - 1;
-	if (prescaler_divider > 0xFF)
-		prescaler_divider = 0xFF;
-
-	NPCX_TPRSC(mdl) = (uint8_t) prescaler_divider;
-}
-
-/**
- * Fan configuration.
- *
- * @param ch                        operation channel
- * @param enable_mft_read_rpm       FAN_USE_RPM_MODE enable flag
- * @return none
- */
-static void fan_config(int ch, int enable_mft_read_rpm)
-{
-	int mdl = mft_channels[ch].module;
-	int pwm_id = mft_channels[ch].pwm_id;
-	enum npcx_mft_clk_src clk_src = mft_channels[ch].clk_src;
-
-	volatile struct fan_status_t *p_status = fan_status + ch;
-
-	/* Setup pwm with fan spec. */
-	pwm_config(pwm_id);
-
-	/* Need to initialize MFT or not */
-	if (enable_mft_read_rpm) {
-
-		/* Initialize tacho sampling rate */
-		if (clk_src == TCKC_LFCLK)
-			p_status->mft_freq = INT_32K_CLOCK;
-		else if (clk_src == TCKC_PRESCALE_APB1_CLK)
-			p_status->mft_freq = clock_get_apb1_freq();
-		else
-			p_status->mft_freq = 0;
-
-		/* Set mode 5 to MFT module */
-		SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD,
-				NPCX_MFT_MDSEL_5);
-
-		/* Set MFT operation frequency */
-		if (clk_src == TCKC_PRESCALE_APB1_CLK)
-			mft_set_apb1_prescaler(ch);
-
-		/* Set the low power mode or not. */
-		UPDATE_BIT(NPCX_TCKC(mdl), NPCX_TCKC_LOW_PWR,
-				clk_src == TCKC_LFCLK);
-
-		/* Set the default count-down timer. */
-		NPCX_TCNT1(mdl) = TACHO_MAX_CNT;
-		NPCX_TCRA(mdl)  = TACHO_MAX_CNT;
-
-		/* Set the edge polarity to rising. */
-		SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG);
-		/* Enable capture TCNT1 into TCRA and preset TCNT1. */
-		SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEN);
-		/* Enable input debounce logic into TA. */
-		SET_BIT(NPCX_TCFG(mdl), NPCX_TCFG_TADBEN);
-
-		/* Set the clock source type and start capturing */
-		SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, clk_src);
-	}
-
-	/* Set default fan states */
-	p_status->cur_state = TACHO_NORMAL;
-	p_status->fan_mode = TACHO_FAN_DUTY;
-	p_status->auto_status = FAN_STATUS_STOPPED;
-}
-
-/**
- * Check all fans are stopped
- *
- * @return   1: all fans are stopped. 0: else.
- */
-static int fan_all_disabled(void)
-{
-	int ch;
-
-	for (ch = 0; ch < fan_get_count(); ch++)
-		if (fan_status[ch].auto_status != FAN_STATUS_STOPPED)
-			return 0;
-	return 1;
-}
-
-/**
- * Adjust fan duty by difference between target and actual rpm
- *
- * @param   ch        operation channel
- * @param   rpm_diff  difference between target and actual rpm
- * @param   duty      current fan duty
- */
-static void fan_adjust_duty(int ch, int rpm_diff, int duty)
-{
-	int duty_step = 0;
-
-	/* Find suitable duty step */
-	if (ABS(rpm_diff) >= 2000)
-		duty_step = 20;
-	else if (ABS(rpm_diff) >= 1000)
-		duty_step = 10;
-	else if (ABS(rpm_diff) >= 500)
-		duty_step = 5;
-	else if (ABS(rpm_diff) >= 250)
-		duty_step = 3;
-	else
-		duty_step = 1;
-
-	/* Adjust fan duty step by step */
-	if (rpm_diff > 0)
-		duty = MIN(duty + duty_step, 100);
-	else
-		duty = MAX(duty - duty_step, 1);
-
-	fan_set_duty(ch, duty);
-
-	CPRINTS("fan%d: duty %d, rpm_diff %d", ch, duty, rpm_diff);
-}
-
-/**
- * Smart fan control function.
- *
- * @param   ch         operation channel
- * @param   rpm_actual actual operation rpm value
- * @param   rpm_target target operation rpm value
- * @return  current    fan control status
- */
-enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target)
-{
-	int duty, rpm_diff;
-
-	/* wait rpm is stable */
-	if (ABS(rpm_actual - rpm_pre[ch]) > RPM_MARGIN(rpm_actual)) {
-		rpm_pre[ch] = rpm_actual;
-		return FAN_STATUS_CHANGING;
-	}
-
-	/* Record previous rpm */
-	rpm_pre[ch] = rpm_actual;
-
-	/* Adjust PWM duty */
-	rpm_diff = rpm_target - rpm_actual;
-	duty = fan_get_duty(ch);
-	if (duty == 0 && rpm_target == 0)
-		return FAN_STATUS_STOPPED;
-
-	/* Increase PWM duty */
-	if (rpm_diff > RPM_MARGIN(rpm_target)) {
-		if (duty == 100)
-			return FAN_STATUS_FRUSTRATED;
-
-		fan_adjust_duty(ch, rpm_diff, duty);
-		return FAN_STATUS_CHANGING;
-	/* Decrease PWM duty */
-	} else if (rpm_diff < -RPM_MARGIN(rpm_target)) {
-		if (duty == 1 && rpm_target != 0)
-			return FAN_STATUS_FRUSTRATED;
-
-		fan_adjust_duty(ch, rpm_diff, duty);
-		return FAN_STATUS_CHANGING;
-	}
-
-	return FAN_STATUS_LOCKED;
-}
-
-/**
- * Tick function for fan control.
- *
- * @return  none
- */
-void fan_tick_func(void)
-{
-	int ch;
-
-	for (ch = 0; ch < FAN_CH_COUNT ; ch++) {
-		volatile struct fan_status_t *p_status = fan_status + ch;
-		/* Make sure rpm mode is enabled */
-		if (p_status->fan_mode != TACHO_FAN_RPM) {
-		/* Fan in duty mode still want rpm_actual being updated. */
-			p_status->rpm_actual = mft_fan_rpm(ch);
-			if (p_status->rpm_actual > 0)
-				p_status->auto_status = FAN_STATUS_LOCKED;
-			else
-				p_status->auto_status = FAN_STATUS_STOPPED;
-			continue;
-		}
-		if (!fan_get_enabled(ch))
-			continue;
-		/* Get actual rpm */
-		p_status->rpm_actual = mft_fan_rpm(ch);
-		/* Do smart fan stuff */
-		p_status->auto_status = fan_smart_control(ch,
-				p_status->rpm_actual, p_status->rpm_target);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, fan_tick_func, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/**
- * Set fan duty cycle.
- *
- * @param   ch      operation channel
- * @param   percent duty cycle percent
- * @return  none
- */
-void fan_set_duty(int ch, int percent)
-{
-	int pwm_id = mft_channels[ch].pwm_id;
-
-	/* duty is zero */
-	if (!percent) {
-		fan_status[ch].auto_status = FAN_STATUS_STOPPED;
-		if (fan_all_disabled())
-			enable_sleep(SLEEP_MASK_FAN);
-	} else
-		disable_sleep(SLEEP_MASK_FAN);
-
-	/* Set the duty cycle of PWM */
-	pwm_set_duty(pwm_id, percent);
-}
-
-/**
- * Get fan duty cycle.
- *
- * @param   ch  operation channel
- * @return  duty cycle
- */
-int fan_get_duty(int ch)
-{
-	int pwm_id = mft_channels[ch].pwm_id;
-
-	/* Return percent */
-	return pwm_get_duty(pwm_id);
-}
-/**
- * Check fan is rpm operation mode.
- *
- * @param   ch  operation channel
- * @return  rpm operation mode or not
- */
-int fan_get_rpm_mode(int ch)
-{
-	return fan_status[ch].fan_mode == TACHO_FAN_RPM ? 1 : 0;
-}
-
-/**
- * Set fan to rpm operation mode.
- *
- * @param   ch          operation channel
- * @param   rpm_mode    rpm operation mode flag
- * @return  none
- */
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	if (rpm_mode)
-		fan_status[ch].fan_mode = TACHO_FAN_RPM;
-	else
-		fan_status[ch].fan_mode = TACHO_FAN_DUTY;
-}
-
-/**
- * Get fan actual operation rpm.
- *
- * @param   ch  operation channel
- * @return  actual operation rpm value
- */
-int fan_get_rpm_actual(int ch)
-{
-	/* Check PWM is enabled first */
-	if (fan_get_duty(ch) == 0)
-		return 0;
-
-	CPRINTS("fan %d: get actual rpm = %d", ch, fan_status[ch].rpm_actual);
-	return fan_status[ch].rpm_actual;
-}
-
-/**
- * Check fan enabled.
- *
- * @param   ch  operation channel
- * @return  enabled or not
- */
-int fan_get_enabled(int ch)
-{
-	int pwm_id = mft_channels[ch].pwm_id;
-
-	return pwm_get_enabled(pwm_id);
-}
-/**
- * Set fan enabled.
- *
- * @param   ch      operation channel
- * @param   enabled enabled flag
- * @return  none
- */
-void fan_set_enabled(int ch, int enabled)
-{
-	int pwm_id = mft_channels[ch].pwm_id;
-
-	if (!enabled)
-		fan_status[ch].auto_status = FAN_STATUS_STOPPED;
-	pwm_enable(pwm_id, enabled);
-}
-
-/**
- * Get fan setting rpm.
- *
- * @param   ch  operation channel
- * @return  setting rpm value
- */
-int fan_get_rpm_target(int ch)
-{
-	return fan_status[ch].rpm_target;
-}
-
-/**
- * Set fan setting rpm.
- *
- * @param   ch  operation channel
- * @param   rpm setting rpm value
- * @return  none
- */
-void fan_set_rpm_target(int ch, int rpm)
-{
-	if (rpm == 0) {
-		/* If rpm = 0, disable PWM immediately. Why?*/
-		fan_set_duty(ch, 0);
-	} else {
-		/* This is the counterpart of disabling PWM above. */
-		if (!fan_get_enabled(ch))
-			fan_set_enabled(ch, 1);
-		if (rpm > fans[ch].rpm->rpm_max)
-			rpm = fans[ch].rpm->rpm_max;
-		else if (rpm < fans[ch].rpm->rpm_min)
-			rpm = fans[ch].rpm->rpm_min;
-	}
-
-	/* Set target rpm */
-	fan_status[ch].rpm_target = rpm;
-	CPRINTS("fan %d: set target rpm = %d", ch, fan_status[ch].rpm_target);
-}
-
-/**
- * Check fan operation status.
- *
- * @param   ch          operation channel
- * @return  fan_status  fan operation status
- */
-enum fan_status fan_get_status(int ch)
-{
-	return fan_status[ch].auto_status;
-}
-
-/**
- * Check fan is stall condition.
- *
- * @param   ch          operation channel
- * @return  non-zero    if fan is enabled but stalled
- */
-int fan_is_stalled(int ch)
-{
-	return fan_get_enabled(ch) && fan_get_duty(ch) &&
-			fan_status[ch].cur_state == TACHO_UNDERFLOW;
-}
-
-/**
- * Fan channel setup.
- *
- * @param ch        operation channel
- * @param flags     input flags
- * @return none
- */
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	fan_config(ch, (flags & FAN_USE_RPM_MODE));
-}
-
-/**
- * Fan initial.
- *
- * @param none
- * @return none
- */
-static void fan_init(void)
-{
-	/* Enable the fan module and delay a few clocks */
-	clock_enable_peripheral(CGC_OFFSET_FAN, CGC_FAN_MASK, CGC_MODE_ALL);
-}
-DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN);
diff --git a/chip/npcx/fan_chip.h b/chip/npcx/fan_chip.h
deleted file mode 100644
index 6fc228ec84..0000000000
--- a/chip/npcx/fan_chip.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific MFT module for Chrome EC */
-
-#ifndef __CROS_EC_FAN_CHIP_H
-#define __CROS_EC_FAN_CHIP_H
-
-/* MFT mode select */
-enum npcx_mft_mdsel {
-	NPCX_MFT_MDSEL_1,
-	NPCX_MFT_MDSEL_2,
-	NPCX_MFT_MDSEL_3,
-	NPCX_MFT_MDSEL_4,
-	NPCX_MFT_MDSEL_5,
-	/* Number of MFT modes */
-	NPCX_MFT_MDSEL_COUNT
-};
-
-/* MFT module select */
-enum npcx_mft_module {
-	NPCX_MFT_MODULE_1,
-	NPCX_MFT_MODULE_2,
-	NPCX_MFT_MODULE_3,
-	/* Number of MFT modules */
-	NPCX_MFT_MODULE_COUNT
-};
-
-/* MFT clock source */
-enum npcx_mft_clk_src {
-	TCKC_NOCLK = 0,
-	TCKC_PRESCALE_APB1_CLK = 1,
-	TCKC_LFCLK = 4,
-};
-
-/* Data structure to define MFT channels. */
-struct mft_t {
-	/* MFT module ID */
-	enum npcx_mft_module module;
-	/* MFT clock source */
-	enum npcx_mft_clk_src clk_src;
-	/* PWM id */
-	int pwm_id;
-};
-
-extern const struct mft_t mft_channels[];
-
-#endif /* __CROS_EC_FAN_CHIP_H */
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c
deleted file mode 100644
index 507b83714c..0000000000
--- a/chip/npcx/flash.c
+++ /dev/null
@@ -1,832 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC */
-
-#include "flash.h"
-#include "host_command.h"
-#include "registers.h"
-#include "spi_flash_reg.h"
-#include "switch.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "task.h"
-#include "watchdog.h"
-#include "console.h"
-#include "hwtimer_chip.h"
-
-static int all_protected; /* Has all-flash protection been requested? */
-static int addr_prot_start;
-static int addr_prot_length;
-static uint8_t flag_prot_inconsistent;
-
-/* SR regs aren't readable when UMA lock is on, so save a copy */
-static uint8_t saved_sr1;
-static uint8_t saved_sr2;
-
-#ifdef CONFIG_EXTERNAL_STORAGE
-#define TRISTATE_FLASH(x)
-#else
-#define TRISTATE_FLASH(x) flash_tristate(x)
-#endif
-
-/* Ensure only one task is accessing flash at a time. */
-static struct mutex flash_lock;
-
-/*****************************************************************************/
-/* flash internal functions */
-#if !defined(NPCX_INT_FLASH_SUPPORT)
-static void flash_pinmux(int enable)
-{
-	/* Select pin-mux for FIU*/
-	UPDATE_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI, !enable);
-
-	/* CS0/1 pinmux */
-	if (enable) {
-#if (FIU_CHIP_SELECT == 1)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-#elif (FIU_CHIP_SELECT == 2)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-#endif
-	} else {
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-	}
-}
-#endif
-
-static void flash_execute_cmd(uint8_t code, uint8_t cts)
-{
-	/*
-	 * Flash mutex must be held while executing UMA commands after
-	 * task_start().
-	 */
-	ASSERT(!task_start_called() || flash_lock.lock);
-
-	/* set UMA_CODE */
-	NPCX_UMA_CODE = code;
-	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
-	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-		;
-}
-
-static void flash_cs_level(int level)
-{
-	/* Set chip select to high/low level */
-	UPDATE_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1, level);
-}
-
-static int flash_wait_ready(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_BUSY;
-	const timestamp_t start = get_time();
-	const uint32_t timeout_us = 10 * SECOND;
-	const timestamp_t deadline = {
-		.val = start.val + timeout_us,
-	};
-
-	/* Chip Select down. */
-	flash_cs_level(0);
-	/* Command for Read status register */
-	flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
-	do {
-		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
-		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-			;
-		/* Busy bit is clear */
-		if ((NPCX_UMA_DB0 & mask) == 0)
-			break;
-		usleep(10);
-	} while (!timestamp_expired(deadline, NULL)); /* Wait for Busy clear */
-
-	/* Chip Select high. */
-	flash_cs_level(1);
-
-	if (timestamp_expired(deadline, NULL))
-		return EC_ERROR_TIMEOUT;
-
-	return EC_SUCCESS;
-}
-
-static int flash_write_enable(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_WEL;
-	int rv;
-	/* Wait for previous operation to complete */
-	rv = flash_wait_ready();
-	if (rv)
-		return rv;
-
-	/* Write enable command */
-	flash_execute_cmd(CMD_WRITE_EN, MASK_CMD_ONLY);
-
-	/* Wait for flash is not busy */
-	rv = flash_wait_ready();
-	if (rv)
-		return rv;
-
-	if (NPCX_UMA_DB0 & mask)
-		return EC_SUCCESS;
-	else
-		return EC_ERROR_BUSY;
-}
-
-static void flash_set_address(uint32_t dest_addr)
-{
-	uint8_t *addr = (uint8_t *)&dest_addr;
-	/* Write address */
-	NPCX_UMA_AB2 = addr[2];
-	NPCX_UMA_AB1 = addr[1];
-	NPCX_UMA_AB0 = addr[0];
-}
-
-static uint8_t flash_get_status1(void)
-{
-	uint8_t ret;
-
-	if (all_protected)
-		return saved_sr1;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Read status register1 */
-	flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_RD_1BYTE);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	ret = NPCX_UMA_DB0;
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return ret;
-}
-
-static uint8_t flash_get_status2(void)
-{
-	uint8_t ret;
-
-	if (all_protected)
-		return saved_sr2;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Read status register2 */
-	flash_execute_cmd(CMD_READ_STATUS_REG2, MASK_CMD_RD_1BYTE);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	ret = NPCX_UMA_DB0;
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return ret;
-}
-
-#ifdef NPCX_INT_FLASH_SUPPORT
-static int is_int_flash_protected(void)
-{
-	return IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF);
-}
-
-static void flash_protect_int_flash(int enable)
-{
-	/*
-	 * Please notice the type of WP_IF bit is R/W1S. Once it's set,
-	 * only rebooting EC can clear it.
-	 */
-	if (enable && !is_int_flash_protected())
-		SET_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF);
-}
-#endif
-
-#ifdef CONFIG_HOSTCMD_FLASH_SPI_INFO
-
-void flash_get_mfr_dev_id(uint8_t *dest)
-{
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Read manufacturer and device ID.  Send cmd=0x90 + 24-bit address=0 */
-	flash_set_address(0);
-	flash_execute_cmd(CMD_READ_MAN_DEV_ID,
-			  MASK_CMD_RD_2BYTE | MASK(A_SIZE));
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	dest[0] = NPCX_UMA_DB0;
-	dest[1] = NPCX_UMA_DB1;
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-}
-
-#endif /* CONFIG_HOSTCMD_FLASH_SPI_INFO */
-
-void flash_get_jedec_id(uint8_t *dest)
-{
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Read manufacturer and device ID */
-	flash_execute_cmd(CMD_READ_ID, MASK_CMD_RD_3BYTE);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	dest[0] = NPCX_UMA_DB0;
-	dest[1] = NPCX_UMA_DB1;
-	dest[2] = NPCX_UMA_DB2;
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-}
-
-static void flash_uma_lock(int enable)
-{
-	if (enable && !all_protected) {
-		/*
-		 * Store SR1 / SR2 for later use since we're about to lock
-		 * out all access (including read access) to these regs.
-		 */
-		saved_sr1 = flash_get_status1();
-		saved_sr2 = flash_get_status2();
-	}
-
-	all_protected = enable;
-	UPDATE_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK, enable);
-}
-
-static int flash_set_status_for_prot(int reg1, int reg2)
-{
-	/*
-	 * Writing SR regs will fail if our UMA lock is enabled. If WP
-	 * is deasserted then remove the lock and allow the write.
-	 */
-	if (all_protected) {
-#ifdef NPCX_INT_FLASH_SUPPORT
-		if (is_int_flash_protected())
-			return EC_ERROR_ACCESS_DENIED;
-#endif
-
-		if (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)
-			return EC_ERROR_ACCESS_DENIED;
-		flash_uma_lock(0);
-	}
-
-	/*
-	 * If WP# is active and ec doesn't protect the status registers of
-	 * internal spi-flash, protect it now before setting them.
-	 */
-#ifdef NPCX_INT_FLASH_SUPPORT
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
-#endif /*_CONFIG_WP_ACTIVE_HIGH_*/
-#endif
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Enable write */
-	flash_write_enable();
-
-	NPCX_UMA_DB0 = reg1;
-	NPCX_UMA_DB1 = reg2;
-
-	/* Write status register 1/2 */
-	flash_execute_cmd(CMD_WRITE_STATUS_REG, MASK_CMD_WR_2BYTE);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	spi_flash_reg_to_protect(reg1, reg2,
-				 &addr_prot_start, &addr_prot_length);
-
-	return EC_SUCCESS;
-}
-
-static int flash_check_prot_range(unsigned int offset, unsigned int bytes)
-{
-	/* Invalid value */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-	/* Check if ranges overlap */
-	if (MAX(addr_prot_start, offset) < MIN(addr_prot_start +
-		addr_prot_length, offset + bytes))
-		return EC_ERROR_ACCESS_DENIED;
-
-	return EC_SUCCESS;
-}
-
-static int flash_check_prot_reg(unsigned int offset, unsigned int bytes)
-{
-	unsigned int start;
-	unsigned int len;
-	uint8_t sr1, sr2;
-	int rv = EC_SUCCESS;
-
-	/*
-	 * If WP# is active and ec doesn't protect the status registers of
-	 * internal spi-flash, protect it now.
-	 */
-#ifdef NPCX_INT_FLASH_SUPPORT
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
-#endif /* CONFIG_WP_ACTIVE_HIGH */
-#endif
-
-	sr1 = flash_get_status1();
-	sr2 = flash_get_status2();
-
-	/* Invalid value */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Compute current protect range */
-	rv = spi_flash_reg_to_protect(sr1, sr2, &start, &len);
-	if (rv)
-		return rv;
-
-	/* Check if ranges overlap */
-	if (MAX(start, offset) < MIN(start + len, offset + bytes))
-		return EC_ERROR_ACCESS_DENIED;
-
-	return EC_SUCCESS;
-
-}
-
-static int flash_write_prot_reg(unsigned int offset, unsigned int bytes,
-				int hw_protect)
-{
-	int rv;
-	uint8_t sr1 = flash_get_status1();
-	uint8_t sr2 = flash_get_status2();
-
-	/* Invalid values */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Compute desired protect range */
-	rv = spi_flash_protect_to_reg(offset, bytes, &sr1, &sr2);
-	if (rv)
-		return rv;
-
-	if (hw_protect)
-		sr1 |= SPI_FLASH_SR1_SRP0;
-
-	return flash_set_status_for_prot(sr1, sr2);
-}
-
-static void flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
-{
-	unsigned int i;
-	/* Chip Select down */
-	flash_cs_level(0);
-	/* Set write address */
-	flash_set_address(dest_addr);
-	/* Start programming */
-	flash_execute_cmd(CMD_FLASH_PROGRAM, MASK_CMD_WR_ADR);
-	for (i = 0; i < bytes; i++) {
-		flash_execute_cmd(*data, MASK_CMD_WR_ONLY);
-		data++;
-	}
-	/* Chip Select up */
-	flash_cs_level(1);
-}
-
-static int flash_program_bytes(uint32_t offset, uint32_t bytes,
-	const uint8_t *data)
-{
-	int write_size;
-	int rv;
-
-	while (bytes > 0) {
-		/* Write length can not go beyond the end of the flash page */
-		write_size = MIN(bytes, CONFIG_FLASH_WRITE_IDEAL_SIZE -
-		(offset & (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1)));
-
-		/* Enable write */
-		rv = flash_write_enable();
-		if (rv)
-			return rv;
-
-		/* Burst UMA transaction */
-		flash_burst_write(offset, write_size, data);
-
-		/* Wait write completed */
-		rv = flash_wait_ready();
-		if (rv)
-			return rv;
-
-		data   += write_size;
-		offset += write_size;
-		bytes  -= write_size;
-	}
-
-	return rv;
-}
-
-/*****************************************************************************/
-
-int crec_flash_physical_read(int offset, int size, char *data)
-{
-	int dest_addr = offset;
-	uint32_t idx;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Chip Select down. */
-	flash_cs_level(0);
-
-	/* Set read address */
-	flash_set_address(dest_addr);
-	/* Start fast read - 1110 1001 - EXEC, WR, CMD, ADDR */
-	flash_execute_cmd(CMD_FAST_READ, MASK_CMD_ADR_WR);
-
-	/* Burst read transaction */
-	for (idx = 0; idx < size; idx++) {
-		/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
-		/* wait for UMA to complete */
-		while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE))
-			;
-		/* Get read transaction results*/
-		data[idx] = NPCX_UMA_DB0;
-	}
-
-	/* Chip Select up */
-	flash_cs_level(1);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int dest_addr = offset;
-	int write_len;
-	int rv;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size
-	     | (uint32_t)(uintptr_t)data) & (CONFIG_FLASH_WRITE_SIZE - 1))
-		return EC_ERROR_INVAL;
-
-	/* check protection */
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-
-	while (size > 0) {
-		/* First write multiples of 256, then (size % 256) last */
-		write_len = ((size % CONFIG_FLASH_WRITE_IDEAL_SIZE) == size) ?
-					size : CONFIG_FLASH_WRITE_IDEAL_SIZE;
-
-		/* check protection */
-		if (flash_check_prot_range(dest_addr, write_len)) {
-			rv = EC_ERROR_ACCESS_DENIED;
-			break;
-		}
-
-		rv = flash_program_bytes(dest_addr, write_len, data);
-		if (rv)
-			break;
-
-		data      += write_len;
-		dest_addr += write_len;
-		size      -= write_len;
-	}
-
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return rv;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int rv = EC_SUCCESS;
-	/* check protection */
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-
-	/* Alignment has been checked in upper layer */
-	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-		offset += CONFIG_FLASH_ERASE_SIZE) {
-		/* check protection */
-		if (flash_check_prot_range(offset, CONFIG_FLASH_ERASE_SIZE)) {
-			rv = EC_ERROR_ACCESS_DENIED;
-			break;
-		}
-
-		/*
-		 * Reload the watchdog timer, so that erasing many flash pages
-		 * doesn't cause a watchdog reset.  May not need this now that
-		 * we're using msleep() below.
-		 */
-		watchdog_reload();
-
-		/* Enable write */
-		rv = flash_write_enable();
-		if (rv)
-			break;
-
-		/* Set erase address */
-		flash_set_address(offset);
-		/* Start erase */
-		flash_execute_cmd(NPCX_ERASE_COMMAND, MASK_CMD_ADR);
-
-		/* Wait erase completed */
-		rv = flash_wait_ready();
-		if (rv)
-			break;
-	}
-
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return rv;
-}
-
-int crec_flash_physical_get_protect(int bank)
-{
-	uint32_t addr = bank * CONFIG_FLASH_BANK_SIZE;
-
-	return flash_check_prot_reg(addr, CONFIG_FLASH_BANK_SIZE);
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	/* Check if WP region is protected in status register */
-	if (flash_check_prot_reg(WP_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE,
-				 WP_BANK_COUNT*CONFIG_FLASH_BANK_SIZE))
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * TODO: If status register protects a range, but SRP0 is not set,
-	 * flags should indicate EC_FLASH_PROTECT_ERROR_INCONSISTENT.
-	 */
-	if (flag_prot_inconsistent)
-		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	/* Read all-protected state from our shadow copy */
-	if (all_protected)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		/*
-		 * Set UMA_LOCK bit for locking all UMA transaction.
-		 * But we still can read directly from flash mapping address
-		 */
-		flash_uma_lock(1);
-	} else {
-		/* TODO: Implement RO "now" protection */
-	}
-
-	return EC_SUCCESS;
-}
-
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int ret;
-
-	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
-			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
-		/* Clear protection bits in status register */
-		return flash_set_status_for_prot(0, 0);
-	}
-
-	ret = flash_write_prot_reg(CONFIG_WP_STORAGE_OFF,
-				   CONFIG_WP_STORAGE_SIZE,
-				   1);
-
-	/*
-	 * Set UMA_LOCK bit for locking all UMA transaction.
-	 * But we still can read directly from flash mapping address
-	 */
-	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-		flash_uma_lock(1);
-
-	return ret;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-			EC_FLASH_PROTECT_RO_NOW |
-			EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-			(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-/*****************************************************************************/
-/* High-level APIs */
-
-int crec_flash_pre_init(void)
-{
-	/*
-	 * Protect status registers of internal spi-flash if WP# is active
-	 * during ec initialization.
-	 */
-#ifdef NPCX_INT_FLASH_SUPPORT
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
-#endif /*CONFIG_WP_ACTIVE_HIGH */
-#endif
-
-#if !defined(NPCX_INT_FLASH_SUPPORT)
-	/* Enable FIU interface */
-	flash_pinmux(1);
-#endif
-
-#if defined(CONFIG_EXTERNAL_STORAGE) && !defined(NPCX_INT_FLASH_SUPPORT)
-	/* Disable tristate all the time */
-	CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-#endif
-
-	/* Initialize UMA to unlocked */
-	flash_uma_lock(0);
-	return EC_SUCCESS;
-}
-
-void crec_flash_lock_mapped_storage(int lock)
-{
-	if (lock)
-		mutex_lock(&flash_lock);
-	else
-		mutex_unlock(&flash_lock);
-}
-
-/*****************************************************************************/
-/* Host commands */
-
-#if defined(CONFIG_HOSTCMD_FLASH_SPI_INFO) && !defined(BOARD_NPCX_EVB)
-/* NPCX EVB uses implementation from spi_flash.c */
-
-static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_flash_spi_info *r = args->response;
-
-	flash_get_jedec_id(r->jedec);
-	r->reserved0 = 0;
-	flash_get_mfr_dev_id(r->mfr_dev_id);
-	r->sr1 = flash_get_status1();
-	r->sr2 = flash_get_status2();
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO,
-		     flash_command_spi_info,
-		     EC_VER_MASK(0));
-
-#endif
-
-#ifdef CONFIG_CMD_FLASH_TRISTATE
-#ifdef NPCX_INT_FLASH_SUPPORT
-#error "Flash tristate is not relevant when internal flash is used."
-#endif
-static void flash_tristate(int enable)
-{
-	/* Enable/Disable FIU pins to tri-state */
-	UPDATE_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS, enable);
-}
-
-static int flash_spi_sel_lock(int enable)
-{
-	/*
-	 * F_SPI_QUAD, F_SPI_CS1_1/2, F_SPI_TRIS become read-only
-	 * if this bit is set
-	 */
-	UPDATE_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_F_SPI_SLLK, enable);
-	return IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_F_SPI_SLLK);
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_flash_spi_sel_lock(int argc, char **argv)
-{
-	int ena;
-
-	if (argc > 1) {
-		if (!parse_bool(argv[1], &ena))
-			return EC_ERROR_PARAM1;
-		ena = flash_spi_sel_lock(ena);
-		ccprintf("Enabled: %d\n", ena);
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(flash_spi_lock, command_flash_spi_sel_lock,
-			"[on | off]",
-			"Lock spi flash interface selection");
-
-static int command_flash_tristate(int argc, char **argv)
-{
-	int ena;
-
-	if (argc > 1) {
-		if (!parse_bool(argv[1], &ena))
-			return EC_ERROR_PARAM1;
-		flash_tristate(ena);
-		ccprintf("Enabled: %d\n", ena);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate,
-			"[on | off]",
-			"Tristate spi flash pins");
-#endif /* CONFIG_CMD_FLASH_TRISTATE */
-
-static int command_flash_chip(int argc, char **argv)
-{
-	uint8_t jedec_id[3];
-
-	ccprintf("Status 1: 0x%02x, Status 2: 0x%02x\n", flash_get_status1(),
-			flash_get_status2());
-
-	flash_get_jedec_id(jedec_id);
-	ccprintf("Manufacturer: 0x%02x, DID: 0x%02x%02x\n", jedec_id[0],
-			jedec_id[1], jedec_id[2]);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip,
-			NULL,
-			"Print flash chip info");
diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c
deleted file mode 100644
index e1d13c98d1..0000000000
--- a/chip/npcx/gpio-npcx5.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lpc_chip.h"
-#include "registers.h"
-#include "task.h"
-
-/*
- * List of GPIO IRQs to enable. Don't automatically enable interrupts for
- * the keyboard input GPIO bank - that's handled separately. Of course the
- * bank is different for different systems.
- */
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0);
-	task_enable_irq(NPCX_IRQ_WKINTEFGH_0);
-	task_enable_irq(NPCX_IRQ_WKINTC_0);
-	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
-	task_enable_irq(NPCX_IRQ_WKINTA_1);
-	task_enable_irq(NPCX_IRQ_WKINTB_1);
-#ifndef HAS_TASK_KEYSCAN
-	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
-#endif
-	task_enable_irq(NPCX_IRQ_WKINTD_1);
-	task_enable_irq(NPCX_IRQ_WKINTE_1);
-	task_enable_irq(NPCX_IRQ_WKINTF_1);
-	task_enable_irq(NPCX_IRQ_WKINTG_1);
-	task_enable_irq(NPCX_IRQ_WKINTH_1);
-#if defined(CHIP_FAMILY_NPCX7)
-	task_enable_irq(NPCX_IRQ_WKINTFG_2);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Handlers for each GPIO port.  These read and clear the interrupt bits for
- * the port, then call the master handler above.
- */
-
-#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
-void _irq_func(void)					\
-{							\
-	gpio_interrupt(wui_int);			\
-}
-
-/* If we need to handle the other type interrupts except GPIO, add code here */
-void __gpio_wk0efgh_interrupt(void)
-{
-	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
-		/* Pending bit 7 or 6 or 5? */
-		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
-			/* Disable host wake-up */
-			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-			/* Clear pending bit of WUI */
-			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-			return;
-		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
-				&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
-				espi_espirst_handler();
-				return;
-			}
-		} else {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
-				&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
-				lpc_lreset_pltrst_handler();
-				return;
-			}
-		}
-	}
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5));
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6));
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-void __gpio_rtc_interrupt(void)
-{
-	/* Check pending bit 7 */
-#ifdef CONFIG_HOSTCMD_RTC
-	if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) {
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7);
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-		return;
-	}
-#endif
-#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
-	(CONFIG_CONSOLE_UART == 1)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-		return;
-	}
-#endif
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
-}
-
-void __gpio_wk1h_interrupt(void)
-{
-#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
-	(CONFIG_CONSOLE_UART == 0)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-	} else
-#endif
-		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
-}
-
-GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
-GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
-GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
-GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
-#ifndef HAS_TASK_KEYSCAN
-/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
-GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
-#endif
-GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
-GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
-GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
-GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
-#if defined(CHIP_FAMILY_NPCX7)
-GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
-#endif
-
-DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,  __gpio_wk0b_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,      __gpio_wk0c_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0,   __gpio_wk0efgh_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,      __gpio_wk1a_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,      __gpio_wk1b_interrupt, 3);
-#ifndef HAS_TASK_KEYSCAN
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,  __gpio_wk1c_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,      __gpio_wk1d_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,      __gpio_wk1e_interrupt, 3);
-#ifdef CONFIG_HOSTCMD_SHI
-/*
- * HACK: Make CS GPIO P2 to improve SHI reliability.
- * TODO: Increase CS-assertion-to-transaction-start delay on host to
- * accommodate P3 CS interrupt.
- */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 2);
-#else
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,      __gpio_wk1g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,      __gpio_wk1h_interrupt, 3);
-#if defined(CHIP_FAMILY_NPCX7)
-DECLARE_IRQ(NPCX_IRQ_WKINTFG_2,     __gpio_wk2fg_interrupt, 3);
-#endif
-
-#undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio-npcx7.c b/chip/npcx/gpio-npcx7.c
deleted file mode 120000
index 39b939f44c..0000000000
--- a/chip/npcx/gpio-npcx7.c
+++ /dev/null
@@ -1 +0,0 @@
-gpio-npcx5.c
\ No newline at end of file
diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c
deleted file mode 100644
index 2bb4ae085c..0000000000
--- a/chip/npcx/gpio-npcx9.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lct_chip.h"
-#include "lpc_chip.h"
-#include "registers.h"
-#include "task.h"
-
-/*
- * List of GPIO IRQs to enable. Don't automatically enable interrupts for
- * the keyboard input GPIO bank - that's handled separately. Of course the
- * bank is different for different systems.
- */
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(NPCX_IRQ_CR_SIN2_WKINTA_0);
-	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
-	task_enable_irq(NPCX_IRQ_WKINTC_0);
-	task_enable_irq(NPCX_IRQ_MTC_WKINTD_0);
-	task_enable_irq(NPCX_IRQ_WKINTE_0);
-	task_enable_irq(NPCX_IRQ_WKINTF_0);
-	task_enable_irq(NPCX_IRQ_WKINTG_0);
-	task_enable_irq(NPCX_IRQ_WKINTH_0);
-	task_enable_irq(NPCX_IRQ_WKINTA_1);
-	task_enable_irq(NPCX_IRQ_WKINTB_1);
-#ifndef HAS_TASK_KEYSCAN
-	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
-#endif
-	task_enable_irq(NPCX_IRQ_WKINTD_1);
-	task_enable_irq(NPCX_IRQ_WKINTE_1);
-	task_enable_irq(NPCX_IRQ_WKINTF_1);
-	task_enable_irq(NPCX_IRQ_WKINTG_1);
-	task_enable_irq(NPCX_IRQ_WKINTH_1);
-	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Handlers for each GPIO port.  These read and clear the interrupt bits for
- * the port, then call the master handler above.
- */
-
-#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
-void _irq_func(void)					\
-{							\
-	gpio_interrupt(wui_int);			\
-}
-
-/* If we need to handle the other type interrupts except GPIO, add code here */
-void __gpio_host_interrupt(void)
-{
-	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
-		/* Pending bit 7 or 6 or 5? */
-		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
-			/* Disable host wake-up */
-			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-			/* Clear pending bit of WUI */
-			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-			return;
-		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
-					&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
-				espi_espirst_handler();
-				return;
-			}
-		} else {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
-					&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
-				lpc_lreset_pltrst_handler();
-				return;
-			}
-		}
-	}
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5));
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-void __gpio_rtc_interrupt(void)
-{
-	/* Check pending bit 7 */
-#ifdef CONFIG_HOSTCMD_RTC
-	if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) {
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7);
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-		return;
-	}
-#endif
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
-}
-void __gpio_cr_sin2_interrupt(void)
-{
-#if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 1)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-		return;
-	}
-#endif
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
-
-}
-
-void __gpio_wk1h_interrupt(void)
-{
-#if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 0)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-	} else
-#endif
-		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
-}
-
-void __gpio_lct_interrupt(void)
-{
-	if (NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_6) & LCT_WUI_MASK) {
-		NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) |= LCT_WUI_MASK;
-		npcx_lct_clear_event();
-		return;
-	}
-	gpio_interrupt(WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
-}
-
-GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
-GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
-GPIO_IRQ_FUNC(__gpio_wk0f_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6));
-GPIO_IRQ_FUNC(__gpio_wk0g_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
-GPIO_IRQ_FUNC(__gpio_wk0h_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
-GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
-GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
-#ifndef HAS_TASK_KEYSCAN
-/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
-GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
-#endif
-GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
-GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
-GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
-GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
-GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
-
-DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,     __gpio_wk0b_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,         __gpio_wk0c_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0,     __gpio_rtc_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_0,         __gpio_host_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTF_0,         __gpio_wk0f_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTG_0,         __gpio_wk0g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_0,         __gpio_wk0h_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,         __gpio_wk1a_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,         __gpio_wk1b_interrupt, 3);
-#ifndef HAS_TASK_KEYSCAN
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,     __gpio_wk1c_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,         __gpio_wk1d_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,         __gpio_wk1e_interrupt, 3);
-#ifdef CONFIG_HOSTCMD_SHI
-/*
- * HACK: Make CS GPIO P2 to improve SHI reliability.
- * TODO: Increase CS-assertion-to-transaction-start delay on host to
- * accommodate P3 CS interrupt.
- */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 2);
-#else
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,         __gpio_wk1g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,         __gpio_wk1h_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2,     __gpio_lct_interrupt, 3);
-
-#undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
deleted file mode 100644
index e740f0aa9f..0000000000
--- a/chip/npcx/gpio.c
+++ /dev/null
@@ -1,765 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "common.h"
-#include "gpio.h"
-#include "gpio_chip.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "system.h"
-#include "system_chip.h"
-#include "ec_commands.h"
-#include "host_command.h"
-#include "hwtimer_chip.h"
-
-#if !(DEBUG_GPIO)
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_GPIO, outstr)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-#endif
-
-/* Constants for GPIO interrupt mapping */
-#define GPIO_INT(name, pin, flags, signal) NPCX_WUI_GPIO_##pin,
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Extend gpio_wui_table for the bypass of better power consumption */
-#define GPIO(name, pin, flags) NPCX_WUI_GPIO_##pin,
-#define UNIMPLEMENTED(name) WUI_NONE,
-#else
-/* Ignore GPIO and UNIMPLEMENTED definitions if not using lower power idle */
-#define GPIO(name, pin, flags)
-#define UNIMPLEMENTED(name)
-#endif
-static const struct npcx_wui gpio_wui_table[] = {
-	#include "gpio.wrap"
-};
-
-struct npcx_gpio {
-	uint8_t port  : 4;
-	uint8_t bit   : 3;
-	uint8_t valid : 1;
-};
-
-BUILD_ASSERT(sizeof(struct npcx_gpio) == 1);
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-struct npcx_alt {
-	uint8_t group;
-	uint8_t bit       : 3;
-	uint8_t inverted  : 1;
-	uint8_t reserved  : 4;
-};
-#else
-struct npcx_alt {
-	uint8_t group     : 4;
-	uint8_t bit       : 3;
-	uint8_t inverted  : 1;
-};
-#endif
-
-struct gpio_alt_map {
-	struct npcx_gpio gpio;
-	struct npcx_alt  alt;
-};
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-BUILD_ASSERT(sizeof(struct gpio_alt_map) == 3);
-#else
-BUILD_ASSERT(sizeof(struct gpio_alt_map) == 2);
-#endif
-
-/* Constants for GPIO alternative mapping */
-const __const_data struct gpio_alt_map gpio_alt_table[] = NPCX_ALT_TABLE;
-
-struct gpio_lvol_item {
-	struct npcx_gpio lvol_gpio[8];
-};
-
-/* Constants for GPIO low-voltage mapping */
-const struct gpio_lvol_item gpio_lvol_table[] = NPCX_LVOL_TABLE;
-
-/*****************************************************************************/
-/* Internal functions */
-
-static int gpio_match(uint8_t port, uint8_t bit, struct npcx_gpio gpio)
-{
-	return (gpio.valid && (gpio.port == port) && (gpio.bit == bit));
-}
-
-#ifdef CONFIG_CMD_GPIO_EXTENDED
-static uint8_t gpio_is_alt_sel(uint8_t port, uint8_t bit)
-{
-	struct gpio_alt_map const *map;
-	uint8_t alt_mask, devalt;
-
-	for (map = ARRAY_BEGIN(gpio_alt_table);
-	     map < ARRAY_END(gpio_alt_table);
-	     map++) {
-		if (gpio_match(port, bit, map->gpio)) {
-			alt_mask = 1 << map->alt.bit;
-			devalt = NPCX_DEVALT(map->alt.group);
-			/*
-			 * alt.inverted == 0:
-			 *   !!(devalt & alt_mask) == 0 -> GPIO
-			 *   !!(devalt & alt_mask) == 1 -> Alternate
-			 * alt.inverted == 1:
-			 *   !!(devalt & alt_mask) == 0 -> Alternate
-			 *   !!(devalt & alt_mask) == 1 -> GPIO
-			 */
-			return !!(devalt & alt_mask) ^ map->alt.inverted;
-		}
-	}
-	return 0;
-}
-#endif
-
-static int gpio_alt_sel(uint8_t port, uint8_t bit,
-			enum gpio_alternate_func func)
-{
-	struct gpio_alt_map const *map;
-
-	for (map = ARRAY_BEGIN(gpio_alt_table);
-	     map < ARRAY_END(gpio_alt_table);
-	     map++) {
-		if (gpio_match(port, bit, map->gpio)) {
-			uint8_t alt_mask = 1 << map->alt.bit;
-
-			/*
-			 * func < GPIO_ALT_FUNC_DEFAULT -> GPIO functionality
-			 * map->alt.inverted -> Set DEVALT bit for GPIO
-			 */
-			if ((func < GPIO_ALT_FUNC_DEFAULT) ^ map->alt.inverted)
-				NPCX_DEVALT(map->alt.group) &= ~alt_mask;
-			else
-				NPCX_DEVALT(map->alt.group) |=  alt_mask;
-
-			return 1;
-		}
-	}
-
-	if (func > GPIO_ALT_FUNC_DEFAULT)
-		CPRINTS("Warn! No alter func in port%d, pin%d", port, bit);
-
-	return -1;
-}
-
-/* Set interrupt type for GPIO input */
-static void gpio_interrupt_type_sel(enum gpio_signal signal, uint32_t flags)
-{
-	uint8_t table, group, pmask;
-
-	if (signal >= GPIO_IH_COUNT)
-		return;
-
-	table = gpio_wui_table[signal].table;
-	group = gpio_wui_table[signal].group;
-	pmask = 1 << gpio_wui_table[signal].bit;
-
-	ASSERT(flags & GPIO_INT_ANY);
-
-	/* Handle interrupt for level trigger */
-	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW)) {
-		/* Set detection mode to level */
-		NPCX_WKMOD(table, group) |= pmask;
-		/* Handle interrupting on level high */
-		if (flags & GPIO_INT_F_HIGH)
-			NPCX_WKEDG(table, group) &= ~pmask;
-		/* Handle interrupting on level low */
-		else if (flags & GPIO_INT_F_LOW)
-			NPCX_WKEDG(table, group) |= pmask;
-	}
-	/* Handle interrupt for edge trigger */
-	else {
-		/* Set detection mode to edge */
-		NPCX_WKMOD(table, group) &= ~pmask;
-		/* Handle interrupting on both edges */
-		if ((flags & GPIO_INT_F_RISING) &&
-			(flags & GPIO_INT_F_FALLING)) {
-			/* Enable any edge */
-			NPCX_WKAEDG(table, group) |= pmask;
-		}
-		/* Handle interrupting on rising edge */
-		else if (flags & GPIO_INT_F_RISING) {
-			/* Disable any edge */
-			NPCX_WKAEDG(table, group) &= ~pmask;
-			NPCX_WKEDG(table, group) &= ~pmask;
-		}
-		/* Handle interrupting on falling edge */
-		else if (flags & GPIO_INT_F_FALLING) {
-			/* Disable any edge */
-			NPCX_WKAEDG(table, group) &= ~pmask;
-			NPCX_WKEDG(table, group) |= pmask;
-		}
-	}
-
-	/* Enable wake-up input sources */
-	NPCX_WKINEN(table, group) |= pmask;
-	/*
-	 * Clear pending bit since it might be set
-	 * if WKINEN bit is changed.
-	 */
-	NPCX_WKPCL(table, group) |= pmask;
-
-	/* No support analog mode */
-}
-
-#ifdef CONFIG_CMD_GPIO_EXTENDED
-static uint8_t gpio_is_low_voltage_level_sel(uint8_t port, uint8_t bit)
-{
-	int i, j;
-
-	for (i = 0; i < ARRAY_SIZE(gpio_lvol_table); i++) {
-		const struct npcx_gpio *gpio = gpio_lvol_table[i].lvol_gpio;
-
-		for (j = 0; j < ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio); j++) {
-			if (gpio_match(port, bit, gpio[j]))
-				return IS_BIT_SET(NPCX_LV_GPIO_CTL(i), j);
-		}
-	}
-	return 0;
-}
-#endif
-
-/* Select low voltage detection level */
-void gpio_low_voltage_level_sel(uint8_t port, uint8_t bit, uint8_t low_voltage)
-{
-	int i, j;
-
-	for (i = 0; i < ARRAY_SIZE(gpio_lvol_table); i++) {
-		const struct npcx_gpio *gpio = gpio_lvol_table[i].lvol_gpio;
-
-		for (j = 0; j < ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio); j++) {
-			if (gpio_match(port, bit, gpio[j])) {
-				if (low_voltage)
-					/* Select vol-detect level for 1.8V */
-					SET_BIT(NPCX_LV_GPIO_CTL(i), j);
-				else
-					/* Select vol-detect level for 3.3V */
-					CLEAR_BIT(NPCX_LV_GPIO_CTL(i), j);
-				return;
-			}
-		}
-	}
-
-	if (low_voltage)
-		CPRINTS("Warn! No low voltage support in port:0x%x, bit:%d",
-								port, bit);
-}
-
-/* Set the low voltage detection level by mask */
-static void gpio_low_vol_sel_by_mask(uint8_t p, uint8_t mask, uint8_t low_vol)
-{
-	int bit;
-	uint32_t lv_mask = mask;
-
-	while (lv_mask) {
-		bit = get_next_bit(&lv_mask);
-		gpio_low_voltage_level_sel(p, bit, low_vol);
-	};
-}
-/* The bypass of low voltage IOs for better power consumption */
-#ifdef CONFIG_LOW_POWER_IDLE
-static int gpio_is_i2c_pin(enum gpio_signal signal)
-{
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++)
-		if (i2c_ports[i].scl == signal || i2c_ports[i].sda == signal)
-			return 1;
-
-	return 0;
-}
-
-static void gpio_enable_wake_up_input(enum gpio_signal signal, int enable)
-{
-	const struct npcx_wui *wui = gpio_wui_table + signal;
-
-	/* Is it a valid wui mapping item? */
-	if (wui->table != MIWU_TABLE_COUNT) {
-		/* Turn on/off input io buffer by WKINENx registers */
-		if (enable)
-			SET_BIT(NPCX_WKINEN(wui->table, wui->group), wui->bit);
-		else
-			CLEAR_BIT(NPCX_WKINEN(wui->table, wui->group),
-						wui->bit);
-	}
-}
-
-void gpio_enable_1p8v_i2c_wake_up_input(int enable)
-{
-	int i;
-
-	/* Set input buffer of 1.8V i2c ports. */
-	for (i = 0; i < i2c_ports_used; i++) {
-		if (gpio_list[i2c_ports[i].scl].flags & GPIO_SEL_1P8V)
-			gpio_enable_wake_up_input(i2c_ports[i].scl, enable);
-		if (gpio_list[i2c_ports[i].sda].flags & GPIO_SEL_1P8V)
-			gpio_enable_wake_up_input(i2c_ports[i].sda, enable);
-	}
-}
-#endif
-
-/*
- * Make sure the bit depth of low voltage register.
- */
-BUILD_ASSERT(ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio) == 8);
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	/* Enable alternative pins by func */
-	int pin;
-
-	/* check each bit from mask  */
-	for (pin = 0; pin < 8; pin++)
-		if (mask & BIT(pin))
-			gpio_alt_sel(port, pin, func);
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	ASSERT(signal_is_gpio(signal));
-
-	return !!(NPCX_PDIN(gpio_list[signal].port) & gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	ASSERT(signal_is_gpio(signal));
-
-	if (value)
-		NPCX_PDOUT(gpio_list[signal].port) |=  gpio_list[signal].mask;
-	else
-		NPCX_PDOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask;
-}
-
-#ifdef CONFIG_GPIO_GET_EXTENDED
-int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
-{
-	uint32_t flags = 0;
-
-	if (NPCX_PDIR(port) & mask)
-		flags |= GPIO_OUTPUT;
-	else
-		flags |= GPIO_INPUT;
-
-	if (NPCX_PDIN(port) & mask)
-		flags |= GPIO_HIGH;
-	else
-		flags |= GPIO_LOW;
-
-	if (NPCX_PTYPE(port) & mask)
-		flags |= GPIO_OPEN_DRAIN;
-
-	/* If internal pulling is enabled */
-	if (NPCX_PPULL(port) & mask) {
-		if (NPCX_PPUD(port) & mask)
-			flags |= GPIO_PULL_DOWN;
-		else
-			flags |= GPIO_PULL_UP;
-	}
-
-	if (gpio_is_alt_sel(port, GPIO_MASK_TO_NUM(mask)))
-		flags |= GPIO_ALTERNATE;
-
-	if (gpio_is_low_voltage_level_sel(port, GPIO_MASK_TO_NUM(mask)))
-		flags |= GPIO_SEL_1P8V;
-
-	if (NPCX_PLOCK_CTL(port) & mask)
-		flags |= GPIO_LOCKED;
-
-	return flags;
-}
-#endif
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/* If all GPIO pins are locked, return directly */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	if ((NPCX_PLOCK_CTL(port) & mask) == mask)
-		return;
-#endif
-
-	/*
-	 * Configure pin as input, if requested. Output is configured only
-	 * after setting all other attributes, so as not to create a
-	 * temporary incorrect logic state 0:input 1:output
-	 */
-	if (!(flags & GPIO_OUTPUT))
-		NPCX_PDIR(port) &= ~mask;
-
-	/* Select open drain 0:push-pull 1:open-drain */
-	if (flags & GPIO_OPEN_DRAIN)
-		NPCX_PTYPE(port) |= mask;
-	else
-		NPCX_PTYPE(port) &= ~mask;
-
-	/* Select pull-up/down of GPIO 0:pull-up 1:pull-down */
-	if (flags & GPIO_PULL_UP) {
-		if (flags & GPIO_SEL_1P8V) {
-			CPRINTS("Warn! enable internal PU and low voltage mode"
-					" at the same time is illegal. port 0x%x, mask 0x%x",
-					port, mask);
-		} else {
-			NPCX_PPUD(port)  &= ~mask;
-			NPCX_PPULL(port) |= mask; /* enable pull down/up */
-		}
-	} else if (flags & GPIO_PULL_DOWN) {
-		NPCX_PPUD(port)  |= mask;
-		NPCX_PPULL(port) |= mask; /* enable pull down/up */
-	} else {
-		/* No pull up/down */
-		NPCX_PPULL(port) &= ~mask; /* disable pull down/up */
-	}
-
-	/* 1.8V low voltage select */
-	if (flags & GPIO_SEL_1P8V) {
-		/*
-		 * Set IO type to open-drain before selecting low-voltage level
-		 */
-		NPCX_PTYPE(port) |= mask;
-		gpio_low_vol_sel_by_mask(port, mask, 1);
-	} else
-		gpio_low_vol_sel_by_mask(port, mask, 0);
-
-	/* Set up interrupt type */
-	if (flags & GPIO_INT_ANY) {
-		const struct gpio_info *g = gpio_list;
-		enum gpio_signal gpio_int;
-
-		/* Find gpio signal in GPIO_INTs by port and mask */
-		for (gpio_int = 0; gpio_int < GPIO_IH_COUNT; gpio_int++, g++)
-			if ((g->port == port) && (g->mask & mask))
-				gpio_interrupt_type_sel(gpio_int, flags);
-	}
-
-	/* Set level 0:low 1:high*/
-	if (flags & GPIO_HIGH)
-		NPCX_PDOUT(port) |= mask;
-	else if (flags & GPIO_LOW)
-		NPCX_PDOUT(port) &= ~mask;
-
-	/* Configure pin as output, if requested 0:input 1:output */
-	if (flags & GPIO_OUTPUT)
-		NPCX_PDIR(port) |= mask;
-
-	/* Lock GPIO output and configuration if need */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	if (flags & GPIO_LOCKED)
-		NPCX_PLOCK_CTL(port) |= mask;
-#endif
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	struct npcx_wui wui;
-
-	/* Fail if not an interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_PARAM1;
-
-	wui = gpio_wui_table[signal];
-	/* Set MIWU enable bit */
-	NPCX_WKEN(wui.table, wui.group) |= 1 << wui.bit;
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	struct npcx_wui wui;
-
-	/* Fail if not an interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_PARAM1;
-
-	wui = gpio_wui_table[signal];
-	NPCX_WKEN(wui.table, wui.group) &= ~(1 << wui.bit);
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	struct npcx_wui wui;
-
-	/* Fail if not an interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_PARAM1;
-
-	wui = gpio_wui_table[signal];
-	NPCX_WKPCL(wui.table, wui.group) |= 1 << wui.bit;
-
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	const struct unused_pin_info *u = unused_pin_list;
-	int is_warm;
-	int flags;
-	int i, j;
-
-	system_check_bbram_on_reset();
-	is_warm = system_is_reboot_warm();
-
-	/*
-	 * On power-on of some boards, H1 releases the EC from reset but then
-	 * quickly asserts and releases the reset a second time. This means the
-	 * EC sees 2 resets: (1) power-on reset, (2) reset-pin reset. If we add
-	 * a delay between reset (1) and configuring GPIO output levels, then
-	 * reset (2) will happen before the end of the delay so we avoid extra
-	 * output toggles.
-	 *
-	 * Make sure to set up the timer before using udelay().
-	 */
-	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-	    system_get_reset_flags() & EC_RESET_FLAG_INITIAL_PWR) {
-		__hw_early_init_hwtimer(0);
-		udelay(2 * SECOND);
-		/* Shouldn't get here, but proceeding anyway... */
-	}
-
-#ifdef CHIP_FAMILY_NPCX7
-	/*
-	 * TODO: Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
-	 * for more information. It will be fixed in next chip.
-	 */
-	SET_BIT(NPCX_DEVCNT, 7);
-#endif
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	/* Lock VCC_RST# alternative bit in case switch to GPO77 unexpectedly */
-	SET_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_VCC1_RST_LK);
-#endif
-
-	/* Pin_Mux for FIU/SPI (set to GPIO) */
-	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
-#if defined(NPCX_INT_FLASH_SUPPORT)
-	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-#endif
-
-	/* Pin_Mux for PWRGD */
-	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_NO_PWRGD);
-
-	/* Pin_Mux for PECI */
-#ifndef CONFIG_PECI
-	SET_BIT(NPCX_DEVALT(0xA), NPCX_DEVALTA_NO_PECI_EN);
-#endif
-
-	/* Pin_Mux for LPC & SHI */
-#ifdef CONFIG_HOSTCMD_SHI
-	/* Switching to eSPI mode for SHI interface */
-	NPCX_DEVCNT |= 0x08;
-	/* Alternate Intel bus interface LPC/eSPI to GPIOs first */
-	SET_BIT(NPCX_DEVALT(ALT_GROUP_1), NPCX_DEVALT1_NO_LPC_ESPI);
-#endif
-
-	/* Clear all interrupt pending and enable bits of GPIOS */
-	for (i = 0; i < 2; i++) {
-		for (j = 0; j < 8; j++) {
-			NPCX_WKPCL(i, j) = 0xFF;
-			NPCX_WKEN(i, j) = 0;
-		}
-	}
-
-	/* No support enable clock for the GPIO port in run and sleep. */
-	/* Set flag for each GPIO pin in gpio_list */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/*
-		 * Ensure that any GPIO defined in gpio.inc is actually
-		 * configured as a GPIO, and not left in its default state,
-		 * which may or may not be as a GPIO.
-		 */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-
-	/* The bypass of low voltage IOs for better power consumption */
-#ifdef CONFIG_LOW_POWER_IDLE
-	/* Disable input buffer of 1.8V GPIOs without ISR */
-	g = gpio_list + GPIO_IH_COUNT;
-	for (i = GPIO_IH_COUNT; i < GPIO_COUNT; i++, g++) {
-		/*
-		 * I2c ports are both alternate mode and normal gpio pin, but
-		 * the alternate mode needs the wake up input even though the
-		 * normal gpio definition doesn't have an ISR.
-		 */
-		if ((g->flags & GPIO_SEL_1P8V) && !gpio_is_i2c_pin(i))
-			gpio_enable_wake_up_input(i, 0);
-	}
-#endif
-
-	/* Configure unused pins as GPIO INPUT with PU to save power. */
-	for (i = 0; i < unused_pin_count; i++, u++) {
-		gpio_set_flags_by_mask(u->port, u->mask,
-				       GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_alternate_function(g->port, g->mask,
-					    GPIO_ALT_FUNC_NONE);
-	}
-}
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle a GPIO interrupt.
- *
- * @param wui_int wui table & group for GPIO interrupt no.
- */
-
-void gpio_interrupt(struct npcx_wui wui_int)
-{
-	int i;
-	uint8_t wui_mask;
-	uint8_t table = wui_int.table;
-	uint8_t group = wui_int.group;
-
-	/* Get pending mask */
-	wui_mask = NPCX_WKPND(table, group) & NPCX_WKEN(table, group);
-
-	/* Find GPIOs and execute interrupt service routine */
-	for (i = 0; i < GPIO_IH_COUNT && wui_mask; i++) {
-		uint8_t pin_mask = 1 << gpio_wui_table[i].bit;
-
-		if ((gpio_wui_table[i].table == table) &&
-			(gpio_wui_table[i].group == group) &&
-			(wui_mask & pin_mask)) {
-			/* Clear pending bit of GPIO */
-			NPCX_WKPCL(table, group) = pin_mask;
-			/* Execute GPIO's ISR */
-			gpio_irq_handlers[i](i);
-			/* In case declare the same GPIO in gpio_wui_table */
-			wui_mask &= ~pin_mask;
-		}
-	}
-
-	if (wui_mask)
-		/* No ISR for this interrupt, just clear it */
-		NPCX_WKPCL(table, group) = wui_mask;
-}
-
-#undef GPIO_IRQ_FUNC
-#if DEBUG_GPIO && defined(CONFIG_LOW_POWER_IDLE)
-/*
- * Command used to disable input buffer of gpios one by one to
- * investigate power consumption
- */
-static int command_gpiodisable(int argc, char **argv)
-{
-	uint8_t i;
-	uint8_t offset;
-	const uint8_t non_isr_gpio_num = GPIO_COUNT - GPIO_IH_COUNT;
-	const struct gpio_info *g_list;
-	int flags;
-	static uint8_t idx = 0;
-	int num = -1;
-	int enable;
-	char *e;
-
-	if (argc == 2) {
-		if (!strcasecmp(argv[1], "info")) {
-			offset = idx + GPIO_IH_COUNT;
-			g_list = gpio_list + offset;
-			flags = g_list->flags;
-
-			ccprintf("Total GPIO declaration: %d\n", GPIO_COUNT);
-			ccprintf("Total Non-ISR GPIO declaration: %d\n",
-						non_isr_gpio_num);
-			ccprintf("Next GPIO Num to check by ");
-			ccprintf("\"gpiodisable next\"\n");
-			ccprintf("  offset: %d\n", offset);
-			ccprintf("  current GPIO name: %s\n", g_list->name);
-			ccprintf("  current GPIO flags: 0x%08x\n", flags);
-			return EC_SUCCESS;
-		}
-		/* List all non-ISR GPIOs in gpio.inc */
-		if (!strcasecmp(argv[1], "list")) {
-			for (i = GPIO_IH_COUNT; i < GPIO_COUNT; i++)
-				ccprintf("%d: %s\n", i, gpio_get_name(i));
-			return EC_SUCCESS;
-		}
-
-		if (!strcasecmp(argv[1], "next")) {
-			while (1) {
-				if (idx == non_isr_gpio_num)
-					break;
-
-				offset = idx + GPIO_IH_COUNT;
-				g_list = gpio_list + offset;
-				flags = g_list->flags;
-				ccprintf("current GPIO : %d %s --> ",
-							offset, g_list->name);
-				if (gpio_is_i2c_pin(offset)) {
-					ccprintf("Ignore I2C pin!\n");
-					idx++;
-					continue;
-				} else if (flags & GPIO_SEL_1P8V) {
-					ccprintf("Ignore 1v8 pin!\n");
-					idx++;
-					continue;
-				} else {
-					if ((flags & GPIO_INPUT) ||
-						    (flags & GPIO_OPEN_DRAIN)) {
-						ccprintf("Disable WKINEN!\n");
-						gpio_enable_wake_up_input(
-								offset, 0);
-						idx++;
-						break;
-					}
-					ccprintf("Not Input or OpenDrain\n");
-					idx++;
-					continue;
-				}
-			};
-			if (idx == non_isr_gpio_num) {
-				ccprintf("End of GPIO list, reset index!\n");
-				idx = 0;
-			};
-			return EC_SUCCESS;
-		}
-	}
-	if (argc == 3) {
-		num = strtoi(argv[1], &e, 0);
-		if (*e || num < GPIO_IH_COUNT || num >= GPIO_COUNT)
-			return EC_ERROR_PARAM1;
-
-		if (parse_bool(argv[2], &enable))
-			gpio_enable_wake_up_input(num, enable ? 1 : 0);
-		else
-			return EC_ERROR_PARAM2;
-
-		return EC_SUCCESS;
-	}
-	return EC_ERROR_INVAL;
-}
-DECLARE_CONSOLE_COMMAND(gpiodisable, command_gpiodisable,
-		"info/list/next/<num> on|off",
-		"Disable GPIO input buffer to investigate power consumption");
-#endif
diff --git a/chip/npcx/gpio_chip-npcx5.h b/chip/npcx/gpio_chip-npcx5.h
deleted file mode 100644
index 83916a421b..0000000000
--- a/chip/npcx/gpio_chip-npcx5.h
+++ /dev/null
@@ -1,384 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GPIO_CHIP_NPCX5_H
-#define __CROS_EC_GPIO_CHIP_NPCX5_H
-
-/*****************************************************************************/
-/* Macro functions for MIWU mapping table */
-
-/* MIWU0 */
-/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_8_4 WUI(0, MIWU_GROUP_1, 4)
-#define NPCX_WUI_GPIO_8_5 WUI(0, MIWU_GROUP_1, 5)
-#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_TWD_WKINTB_0 */
-#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3)
-#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5)
-
-/* Group C: NPCX_IRQ_WKINTC_0 */
-#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5)
-#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6)
-
-/* Group E: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4)
-
-/* Group F: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3)
-
-/* Group H: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7)
-
-/* MIWU1 */
-/* Group A: NPCX_IRQ_WKINTA_1 */
-#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4)
-#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5)
-#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_WKINTB_1 */
-#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_1_3 WUI(1, MIWU_GROUP_2, 3)
-#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5)
-#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6)
-#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7)
-
-/* Group C: NPCX_IRQ_KSI_WKINTC_1 */
-#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_WKINTD_1 */
-#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3)
-#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4)
-#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6)
-#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7)
-
-/* Group E: NPCX_IRQ_WKINTE_1 */
-#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3)
-#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4)
-#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5)
-#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6)
-#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7)
-
-/* Group F: NPCX_IRQ_WKINTF_1 */
-#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTG_1 */
-#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
-#define NPCX_WUI_GPIO_6_5 WUI(1, MIWU_GROUP_7, 5)
-#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7)
-
-/* Group H: NPCX_IRQ_WKINTH_1 */
-#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6)
-
-/* Others GPO without MIWU functionality */
-#define NPCX_WUI_GPIO_1_2 WUI_NONE
-#define NPCX_WUI_GPIO_3_2 WUI_NONE
-#define NPCX_WUI_GPIO_3_5 WUI_NONE
-#define NPCX_WUI_GPIO_6_6 WUI_NONE
-#define NPCX_WUI_GPIO_7_7 WUI_NONE
-#define NPCX_WUI_GPIO_B_6 WUI_NONE
-#define NPCX_WUI_GPIO_D_6 WUI_NONE
-
-/* Others GPIO without MIWU functionality on npcx5 */
-#define NPCX_WUI_GPIO_D_4 WUI_NONE
-#define NPCX_WUI_GPIO_D_5 WUI_NONE
-#define NPCX_WUI_GPIO_D_7 WUI_NONE
-#define NPCX_WUI_GPIO_E_0 WUI_NONE
-#define NPCX_WUI_GPIO_E_1 WUI_NONE
-#define NPCX_WUI_GPIO_E_2 WUI_NONE
-#define NPCX_WUI_GPIO_E_3 WUI_NONE
-#define NPCX_WUI_GPIO_E_4 WUI_NONE
-#define NPCX_WUI_GPIO_E_5 WUI_NONE
-
-/*****************************************************************************/
-/* Macro functions for Alternative mapping table */
-
-/* I2C Module */
-#define NPCX_ALT_GPIO_B_2 ALT(B, 2, NPCX_ALT(2, I2C0_1_SL)) /* SMB0SDA1 */
-#define NPCX_ALT_GPIO_B_3 ALT(B, 3, NPCX_ALT(2, I2C0_1_SL)) /* SMB0SCL1 */
-#define NPCX_ALT_GPIO_B_4 ALT(B, 4, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SDA0 */
-#define NPCX_ALT_GPIO_B_5 ALT(B, 5, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SCL0 */
-#define NPCX_ALT_GPIO_8_7 ALT(8, 7, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SDA */
-#define NPCX_ALT_GPIO_9_0 ALT(9, 0, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SCL */
-#define NPCX_ALT_GPIO_9_1 ALT(9, 1, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SDA */
-#define NPCX_ALT_GPIO_9_2 ALT(9, 2, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SCL */
-#define NPCX_ALT_GPIO_D_0 ALT(D, 0, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SDA */
-#define NPCX_ALT_GPIO_D_1 ALT(D, 1, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SCL */
-
-/* ADC Module */
-#define NPCX_ALT_GPIO_4_5 ALT(4, 5, NPCX_ALT(6, ADC0_SL)) /* ADC0  */
-#define NPCX_ALT_GPIO_4_4 ALT(4, 4, NPCX_ALT(6, ADC1_SL)) /* ADC1  */
-#define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2  */
-#define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3  */
-#define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4  */
-
-/* UART Module */
-#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(C, UART_SL2)) /* CR_SIN SEL2 */
-#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(C, UART_SL2)) /* CR_SOUT SEL2 */
-
-/* SPI Module */
-#define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */
-#define NPCX_ALT_GPIO_A_5 ALT(A, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_CS1  */
-#define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
-#define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
-
-/* PWM Module */
-#define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */
-#define NPCX_ALT_GPIO_C_4 ALT(C, 4, NPCX_ALT(4, PWM2_SL)) /* PWM2 */
-#define NPCX_ALT_GPIO_8_0 ALT(8, 0, NPCX_ALT(4, PWM3_SL)) /* PWM3 */
-#define NPCX_ALT_GPIO_B_6 ALT(B, 6, NPCX_ALT(4, PWM4_SL)) /* PWM4 */
-#define NPCX_ALT_GPIO_B_7 ALT(B, 7, NPCX_ALT(4, PWM5_SL)) /* PWM5 */
-#define NPCX_ALT_GPIO_C_0 ALT(C, 0, NPCX_ALT(4, PWM6_SL)) /* PWM6 */
-#define NPCX_ALT_GPIO_6_0 ALT(6, 0, NPCX_ALT(4, PWM7_SL)) /* PWM7 */
-
-/* MFT Module */
-#define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
-#else
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
-#endif
-#define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */
-#define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */
-
-/* Keyboard Scan Module */
-#define NPCX_ALT_GPIO_3_1 ALT(3, 1, NPCX_ALT_INV(7, NO_KSI0_SL)) /* KSI0 */
-#define NPCX_ALT_GPIO_3_0 ALT(3, 0, NPCX_ALT_INV(7, NO_KSI1_SL)) /* KSI1 */
-#define NPCX_ALT_GPIO_2_7 ALT(2, 7, NPCX_ALT_INV(7, NO_KSI2_SL)) /* KSI2 */
-#define NPCX_ALT_GPIO_2_6 ALT(2, 6, NPCX_ALT_INV(7, NO_KSI3_SL)) /* KSI3 */
-#define NPCX_ALT_GPIO_2_5 ALT(2, 5, NPCX_ALT_INV(7, NO_KSI4_SL)) /* KSI4 */
-#define NPCX_ALT_GPIO_2_4 ALT(2, 4, NPCX_ALT_INV(7, NO_KSI5_SL)) /* KSI5 */
-#define NPCX_ALT_GPIO_2_3 ALT(2, 3, NPCX_ALT_INV(7, NO_KSI6_SL)) /* KSI6 */
-#define NPCX_ALT_GPIO_2_2 ALT(2, 2, NPCX_ALT_INV(7, NO_KSI7_SL)) /* KSI7 */
-#define NPCX_ALT_GPIO_2_1 ALT(2, 1, NPCX_ALT_INV(8, NO_KSO00_SL)) /* KSO00 */
-#define NPCX_ALT_GPIO_2_0 ALT(2, 0, NPCX_ALT_INV(8, NO_KSO01_SL)) /* KSO01 */
-#define NPCX_ALT_GPIO_1_7 ALT(1, 7, NPCX_ALT_INV(8, NO_KSO02_SL)) /* KSO02 */
-#define NPCX_ALT_GPIO_1_6 ALT(1, 6, NPCX_ALT_INV(8, NO_KSO03_SL)) /* KSO03 */
-#define NPCX_ALT_GPIO_1_5 ALT(1, 5, NPCX_ALT_INV(8, NO_KSO04_SL)) /* KSO04 */
-#define NPCX_ALT_GPIO_1_4 ALT(1, 4, NPCX_ALT_INV(8, NO_KSO05_SL)) /* KSO05 */
-#define NPCX_ALT_GPIO_1_3 ALT(1, 3, NPCX_ALT_INV(8, NO_KSO06_SL)) /* KSO06 */
-#define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
-/* KSO08 & CR_SIN */
-#define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
-/* KSO09 & CR_SOUT */
-#define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
-#define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
-#define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
-#define NPCX_ALT_GPIO_0_5 ALT(0, 5, NPCX_ALT_INV(9, NO_KSO12_SL)) /* KSO12 */
-#define NPCX_ALT_GPIO_0_4 ALT(0, 4, NPCX_ALT_INV(9, NO_KSO13_SL)) /* KSO13 */
-#define NPCX_ALT_GPIO_8_2 ALT(8, 2, NPCX_ALT_INV(9, NO_KSO14_SL)) /* KSO14 */
-#define NPCX_ALT_GPIO_8_3 ALT(8, 3, NPCX_ALT_INV(9, NO_KSO15_SL)) /* KSO15 */
-#define NPCX_ALT_GPIO_0_3 ALT(0, 3, NPCX_ALT_INV(A, NO_KSO16_SL)) /* KSO16 */
-#define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
-
-/* Clock module */
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL))  /* 32KHZ_OUT */
-#define NPCX_ALT_GPIO_E_7 ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */
-
-/* PS/2 module */
-#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */
-#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */
-#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */
-#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
-#else
-#define NPCX_ALT_GPIO_A_7
-#endif
-
-#define NPCX_ALT_TABLE { \
-	NPCX_ALT_GPIO_0_3  /* KSO16 */               \
-	NPCX_ALT_GPIO_0_4  /* KSO13 */               \
-	NPCX_ALT_GPIO_0_5  /* KSO12 */               \
-	NPCX_ALT_GPIO_0_6  /* KSO11 */               \
-	NPCX_ALT_GPIO_0_7  /* KSO10 */               \
-	NPCX_ALT_GPIO_1_0  /* KSO09 & CR_SOUT */     \
-	NPCX_ALT_GPIO_1_1  /* KSO08 & CR_SIN */      \
-	NPCX_ALT_GPIO_1_2  /* KSO07 */               \
-	NPCX_ALT_GPIO_1_3  /* KSO06 */               \
-	NPCX_ALT_GPIO_1_4  /* KSO05 */               \
-	NPCX_ALT_GPIO_1_5  /* KSO04 */               \
-	NPCX_ALT_GPIO_1_6  /* KSO03 */               \
-	NPCX_ALT_GPIO_1_7  /* KSO02 */               \
-	NPCX_ALT_GPIO_2_0  /* KSO01 */               \
-	NPCX_ALT_GPIO_2_1  /* KSO00 */               \
-	NPCX_ALT_GPIO_2_2  /* KSI7 */                \
-	NPCX_ALT_GPIO_2_3  /* KSI6 */                \
-	NPCX_ALT_GPIO_2_4  /* KSI5 */                \
-	NPCX_ALT_GPIO_2_5  /* KSI4 */                \
-	NPCX_ALT_GPIO_2_6  /* KSI3 */                \
-	NPCX_ALT_GPIO_2_7  /* KSI2 */                \
-	NPCX_ALT_GPIO_3_0  /* KSI1 */                \
-	NPCX_ALT_GPIO_3_1  /* KSI0 */                \
-	NPCX_ALT_GPIO_3_4  /* PS2_DAT2 */            \
-	NPCX_ALT_GPIO_3_7  /* PS2_CLK2 */            \
-	NPCX_ALT_GPIO_4_0  /* TA1_SEL1 */            \
-	NPCX_ALT_GPIO_4_1  /* ADC4 */                \
-	NPCX_ALT_GPIO_4_2  /* ADC3 */                \
-	NPCX_ALT_GPIO_4_4  /* ADC1 */                \
-	NPCX_ALT_GPIO_4_5  /* ADC0 */                \
-	NPCX_ALT_GPIO_4_3  /* ADC2 */                \
-	NPCX_ALT_GPIO_6_0  /* PWM7 */                \
-	NPCX_ALT_GPIO_6_2  /* PS2_CLK1 */            \
-	NPCX_ALT_GPIO_6_3  /* PS2_DAT1 */            \
-	NPCX_ALT_GPIO_6_4  /* CR_SIN2 */             \
-	NPCX_ALT_GPIO_6_5  /* CR_SOUT2 */            \
-	NPCX_ALT_GPIO_6_7  /* PS2_CLK0 */            \
-	NPCX_ALT_GPIO_7_0  /* PS2_DAT0 */            \
-	NPCX_ALT_GPIO_7_3  /* TA2_SEL1 */            \
-	NPCX_ALT_GPIO_7_5 /* 32KHZ_OUT */            \
-	NPCX_ALT_GPIO_8_0  /* PWM3 */                \
-	NPCX_ALT_GPIO_8_2  /* KSO14 */               \
-	NPCX_ALT_GPIO_8_3  /* KSO15 */               \
-	NPCX_ALT_GPIO_8_7  /* SMB1SDA */             \
-	NPCX_ALT_GPIO_9_0  /* SMB1SCL */             \
-	NPCX_ALT_GPIO_9_1  /* SMB2SDA */             \
-	NPCX_ALT_GPIO_9_2  /* SMB2SCL */             \
-	NPCX_ALT_GPIO_9_3  /* TA1_SEL2 */            \
-	NPCX_ALT_GPIO_9_5  /* SPIP_MISO */           \
-	NPCX_ALT_GPIO_A_1  /* SPIP_SCLK */           \
-	NPCX_ALT_GPIO_A_3  /* SPIP_MOSI */           \
-	NPCX_ALT_GPIO_A_5  /* SPIP_CS1  */           \
-	NPCX_ALT_GPIO_A_6  /* TA2_SEL2/PS2_CLK3 */   \
-	NPCX_ALT_GPIO_A_7  /* PS2_DAT3 */            \
-	NPCX_ALT_GPIO_B_1  /* KSO17 */               \
-	NPCX_ALT_GPIO_B_2  /* SMB0SDA1 */            \
-	NPCX_ALT_GPIO_B_3  /* SMB0SCL1 */            \
-	NPCX_ALT_GPIO_B_4  /* SMB0SDA0 */            \
-	NPCX_ALT_GPIO_B_5  /* SMB0SCL0 */            \
-	NPCX_ALT_GPIO_B_6  /* PWM4 */                \
-	NPCX_ALT_GPIO_B_7  /* PWM5 */                \
-	NPCX_ALT_GPIO_C_0  /* PWM6 */                \
-	NPCX_ALT_GPIO_C_2  /* PWM1 */                \
-	NPCX_ALT_GPIO_C_3  /* PWM0 */                \
-	NPCX_ALT_GPIO_C_4  /* PWM2 */                \
-	NPCX_ALT_GPIO_D_0  /* SMB3SDA */             \
-	NPCX_ALT_GPIO_D_1  /* SMB3SCL */             \
-	NPCX_ALT_GPIO_E_7  /* 32KCLKIN */            \
-}
-
-/*****************************************************************************/
-/* Macro functions for Low-Voltage mapping table */
-
-/* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
-
-/* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO(6, 5)
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
-
-/* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO(8, 4)
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO(8, 5)
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO(E, 7)
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
-
-/* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO(7, 1)
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
-
-/* 4 Low-Voltage Control Groups on npcx5 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, }
-
-#endif /* __CROS_EC_GPIO_CHIP_NPCX5_H */
diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h
deleted file mode 100644
index 7f815e6d30..0000000000
--- a/chip/npcx/gpio_chip-npcx7.h
+++ /dev/null
@@ -1,536 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GPIO_CHIP_NPCX7_H
-#define __CROS_EC_GPIO_CHIP_NPCX7_H
-
-/*****************************************************************************/
-/* Macro functions for MIWU mapping table */
-
-/* MIWU0 */
-/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3)
-#ifndef NPCX_PSL_MODE_SUPPORT
-#define NPCX_WUI_GPIO_8_4 WUI(0, MIWU_GROUP_1, 4) /* Used as VSBY in PSL */
-#define NPCX_WUI_GPIO_8_5 WUI(0, MIWU_GROUP_1, 5) /* Used as PSL_OUT in PSL */
-#endif
-#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_TWD_WKINTB_0 */
-#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3)
-#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5)
-
-/* Group C: NPCX_IRQ_WKINTC_0 */
-#define NPCX_WUI_GPIO_9_6 WUI(0, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_A_0 WUI(0, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_A_2 WUI(0, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_A_4 WUI(0, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5)
-#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6)
-
-/* Group E: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4)
-
-/* Group F: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_D_4 WUI(0, MIWU_GROUP_7, 4)
-#define NPCX_WUI_GPIO_D_5 WUI(0, MIWU_GROUP_7, 5)
-#define NPCX_WUI_GPIO_D_7 WUI(0, MIWU_GROUP_7, 6)
-#define NPCX_WUI_GPIO_E_0 WUI(0, MIWU_GROUP_7, 7)
-
-/* Group H: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_E_1 WUI(0, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_E_2 WUI(0, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_E_3 WUI(0, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_E_4 WUI(0, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_E_5 WUI(0, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6)
-#ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support */
-#endif
-
-/* MIWU1 */
-/* Group A: NPCX_IRQ_WKINTA_1 */
-#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4)
-#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5)
-#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_WKINTB_1 */
-#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_F_4 WUI(1, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5)
-#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6)
-#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7)
-
-/* Group C: NPCX_IRQ_KSI_WKINTC_1 */
-#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_WKINTD_1 */
-#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_F_5 WUI(1, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3)
-#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4)
-#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6)
-#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7)
-
-/* Group E: NPCX_IRQ_WKINTE_1 */
-#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3)
-#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4)
-#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5)
-#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6)
-#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7)
-
-/* Group F: NPCX_IRQ_WKINTF_1 */
-#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTG_1 */
-#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
-#ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if support*/
-#endif
-
-/* Group H: NPCX_IRQ_WKINTH_1 */
-#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6)
-
-/* MIWU2 */
-/* Group F: NPCX_IRQ_WKINTFG_2 */
-#define NPCX_WUI_GPIO_F_1 WUI(2, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_F_2 WUI(2, MIWU_GROUP_6, 2)
-
-/* Others GPO without MIWU functionality */
-#define NPCX_WUI_GPIO_1_2 WUI_NONE
-#define NPCX_WUI_GPIO_1_3 WUI_NONE /* Software strap pin GP_SEL1_L */
-#define NPCX_WUI_GPIO_3_2 WUI_NONE
-#define NPCX_WUI_GPIO_3_5 WUI_NONE
-#define NPCX_WUI_GPIO_6_5 WUI_NONE /* Software strap pin FLPRG_L */
-#define NPCX_WUI_GPIO_6_6 WUI_NONE
-#define NPCX_WUI_GPIO_7_7 WUI_NONE
-#define NPCX_WUI_GPIO_B_6 WUI_NONE /* Software strap pin GP_SEL0_L */
-#define NPCX_WUI_GPIO_D_6 WUI_NONE
-
-/*****************************************************************************/
-/* Macro functions for Alternative mapping table */
-
-/* I2C Module */
-#define NPCX_ALT_GPIO_B_4 ALT(B, 4, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SDA0 */
-#define NPCX_ALT_GPIO_B_5 ALT(B, 5, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SCL0 */
-#define NPCX_ALT_GPIO_8_7 ALT(8, 7, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SDA0 */
-#define NPCX_ALT_GPIO_9_0 ALT(9, 0, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SCL0 */
-#define NPCX_ALT_GPIO_9_1 ALT(9, 1, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SDA0 */
-#define NPCX_ALT_GPIO_9_2 ALT(9, 2, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SCL0 */
-#define NPCX_ALT_GPIO_D_0 ALT(D, 0, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SDA0 */
-#define NPCX_ALT_GPIO_D_1 ALT(D, 1, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SCL0 */
-/* Pin-Mux for PSL/UART2/SMB4_0 */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1)
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL))  /* CR_SOUT2 */
-#define NPCX_ALT_GPIO_8_5 /* Used as PSL_OUT */
-#else
-#define NPCX_ALT_GPIO_8_6 /* No I2CSDA since GPIO85 used as PSL_OUT */
-#define NPCX_ALT_GPIO_8_5 /* Used as PSL_OUT */
-#endif
-#else
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(2, I2C4_0_SL)) /* SMB4SDA0 */
-#define NPCX_ALT_GPIO_8_5 ALT(8, 5, NPCX_ALT(2, I2C4_0_SL)) /* SMB4SCL0 */
-#endif
-
-#define NPCX_ALT_GPIO_F_2 ALT(F, 2, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SDA1 */
-#define NPCX_ALT_GPIO_F_3 ALT(F, 3, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SCL1 */
-#define NPCX_ALT_GPIO_3_6 ALT(3, 6, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SDA0 */
-#define NPCX_ALT_GPIO_3_3 ALT(3, 3, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SCL0 */
-#define NPCX_ALT_GPIO_F_4 ALT(F, 4, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SDA1 */
-#define NPCX_ALT_GPIO_F_5 ALT(F, 5, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SCL1 */
-/* Pin-Mux for PWM1/SMB6_0 */
-#if NPCX7_PWM1_SEL
-#define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL))   /* PWM1 */
-#else
-#define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */
-#endif
-#define NPCX_ALT_GPIO_E_3 ALT(E, 3, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SDA1 */
-#define NPCX_ALT_GPIO_E_4 ALT(E, 4, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SCL1 */
-#define NPCX_ALT_GPIO_B_2 ALT(B, 2, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SDA0 */
-#define NPCX_ALT_GPIO_B_3 ALT(B, 3, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SCL0 */
-
-/* ADC Module */
-#define NPCX_ALT_GPIO_4_5 ALT(4, 5, NPCX_ALT(6, ADC0_SL)) /* ADC0  */
-#define NPCX_ALT_GPIO_4_4 ALT(4, 4, NPCX_ALT(6, ADC1_SL)) /* ADC1  */
-#define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2  */
-#define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3  */
-#define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4  */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_2)
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
-#else
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5  */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6  */
-#endif
-#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL)) /* ADC7  */
-#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL)) /* ADC8  */
-#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL)) /* ADC9  */
-
-/* PS/2 Module */
-#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */
-#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */
-#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */
-#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */
-
-/* UART Module */
-#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(C, UART_SL2)) /* CR_SIN SEL2 */
-#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(C, UART_SL2)) /* CR_SOUT SEL2 */
-
-/* PWM Module */
-#define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */
-#define NPCX_ALT_GPIO_C_4 ALT(C, 4, NPCX_ALT(4, PWM2_SL)) /* PWM2 */
-#define NPCX_ALT_GPIO_8_0 ALT(8, 0, NPCX_ALT(4, PWM3_SL)) /* PWM3 */
-#define NPCX_ALT_GPIO_B_6 ALT(B, 6, NPCX_ALT(4, PWM4_SL)) /* PWM4 */
-#define NPCX_ALT_GPIO_B_7 ALT(B, 7, NPCX_ALT(4, PWM5_SL)) /* PWM5 */
-#define NPCX_ALT_GPIO_C_0 ALT(C, 0, NPCX_ALT(4, PWM6_SL)) /* PWM6 */
-#define NPCX_ALT_GPIO_6_0 ALT(6, 0, NPCX_ALT(4, PWM7_SL)) /* PWM7 */
-
-/* MFT Module */
-#define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */
-#define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */
-#define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
-#else
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
-#endif
-
-/* Keyboard Scan Module */
-#define NPCX_ALT_GPIO_3_1 ALT(3, 1, NPCX_ALT_INV(7, NO_KSI0_SL)) /* KSI0 */
-#define NPCX_ALT_GPIO_3_0 ALT(3, 0, NPCX_ALT_INV(7, NO_KSI1_SL)) /* KSI1 */
-#define NPCX_ALT_GPIO_2_7 ALT(2, 7, NPCX_ALT_INV(7, NO_KSI2_SL)) /* KSI2 */
-#define NPCX_ALT_GPIO_2_6 ALT(2, 6, NPCX_ALT_INV(7, NO_KSI3_SL)) /* KSI3 */
-#define NPCX_ALT_GPIO_2_5 ALT(2, 5, NPCX_ALT_INV(7, NO_KSI4_SL)) /* KSI4 */
-#define NPCX_ALT_GPIO_2_4 ALT(2, 4, NPCX_ALT_INV(7, NO_KSI5_SL)) /* KSI5 */
-#define NPCX_ALT_GPIO_2_3 ALT(2, 3, NPCX_ALT_INV(7, NO_KSI6_SL)) /* KSI6 */
-#define NPCX_ALT_GPIO_2_2 ALT(2, 2, NPCX_ALT_INV(7, NO_KSI7_SL)) /* KSI7 */
-#define NPCX_ALT_GPIO_2_1 ALT(2, 1, NPCX_ALT_INV(8, NO_KSO00_SL)) /* KSO00 */
-#define NPCX_ALT_GPIO_2_0 ALT(2, 0, NPCX_ALT_INV(8, NO_KSO01_SL)) /* KSO01 */
-#define NPCX_ALT_GPIO_1_7 ALT(1, 7, NPCX_ALT_INV(8, NO_KSO02_SL)) /* KSO02 */
-#define NPCX_ALT_GPIO_1_6 ALT(1, 6, NPCX_ALT_INV(8, NO_KSO03_SL)) /* KSO03 */
-#define NPCX_ALT_GPIO_1_5 ALT(1, 5, NPCX_ALT_INV(8, NO_KSO04_SL)) /* KSO04 */
-#define NPCX_ALT_GPIO_1_4 ALT(1, 4, NPCX_ALT_INV(8, NO_KSO05_SL)) /* KSO05 */
-#define NPCX_ALT_GPIO_1_3 ALT(1, 3, NPCX_ALT_INV(8, NO_KSO06_SL)) /* KSO06 */
-#define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
-/* KSO08 & CR_SOUT */
-#define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
- /* KSO09 & CR_SIN */
-#define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
-#define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
-#define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
-#define NPCX_ALT_GPIO_0_5 ALT(0, 5, NPCX_ALT_INV(9, NO_KSO12_SL)) /* KSO12 */
-#define NPCX_ALT_GPIO_0_4 ALT(0, 4, NPCX_ALT_INV(9, NO_KSO13_SL)) /* KSO13 */
-#define NPCX_ALT_GPIO_8_2 ALT(8, 2, NPCX_ALT_INV(9, NO_KSO14_SL)) /* KSO14 */
-#define NPCX_ALT_GPIO_8_3 ALT(8, 3, NPCX_ALT_INV(9, NO_KSO15_SL)) /* KSO15 */
-#define NPCX_ALT_GPIO_0_3 ALT(0, 3, NPCX_ALT_INV(A, NO_KSO16_SL)) /* KSO16 */
-#define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
-
-/* Clock module (Optional) */
-#ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_ALT_GPIO_E_7 /* No 32KCLKIN */
-#else
-#define NPCX_ALT_GPIO_E_7 ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */
-#endif
-
-/* Pin-Mux for UART2/32KHZ_OUT */
-#if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1)
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL))    /* CR_SIN2 */
-#else
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL))  /* 32KHZ_OUT */
-#endif
-
-/* PSL module (Optional) */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */
-#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */
-#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL))      /* PSL_IN3 */
-#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL))      /* PSL_IN4 */
-#else
-#define NPCX_ALT_GPIO_D_2 /* NO PSL in NPCX7mnG series */
-#define NPCX_ALT_GPIO_0_0 /* NO PSL in NPCX7mnG series */
-#define NPCX_ALT_GPIO_0_1 /* NO PSL in NPCX7mnG series */
-#define NPCX_ALT_GPIO_0_2 /* NO PSL in NPCX7mnG series */
-#endif
-
-/* WOV module (Optional) */
-#if defined(NPCX_WOV_SUPPORT) && \
-	(defined(CONFIG_AUDIO_CODEC_I2S_RX) || defined(CONFIG_AUDIO_CODEC_WOV))
-#define NPCX_ALT_GPIO_9_5 /* Disable SPIP module if WOV is supported */
-#define NPCX_ALT_GPIO_A_3 /* Disable SPIP module if WOV is supported */
-#define NPCX_ALT_GPIO_A_1 /* Disable SPIP module if WOV is supported */
-
-#define NPCX_ALT_GPIO_A_5 ALT(A, 5, NPCX_ALT(E, I2S_SL)) /* I2S_SYNC */
-#define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(E, I2S_SL)) /* I2S_SCLK */
-#define NPCX_ALT_GPIO_B_0 ALT(B, 0, NPCX_ALT(E, I2S_SL)) /* I2S_DATA */
-#define NPCX_ALT_GPIO_9_4 ALT(9, 4, NPCX_ALT(E, WOV_SL)) /* DMIC_CLK */
-#define NPCX_ALT_GPIO_9_7 ALT(9, 7, NPCX_ALT(E, WOV_SL)) /* DMIC_IN  */
-#else
-/* SPI Module */
-#define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */
-#define NPCX_ALT_GPIO_A_5 ALT(A, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_CS1  */
-#define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
-#define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
-
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
-#else
-#define NPCX_ALT_GPIO_A_7
-#endif
-#define NPCX_ALT_GPIO_B_0
-#define NPCX_ALT_GPIO_9_4
-#define NPCX_ALT_GPIO_9_7
-#endif
-
-#define NPCX_ALT_TABLE { \
-	NPCX_ALT_GPIO_0_0 /* PSL_IN2 */               \
-	NPCX_ALT_GPIO_0_1 /* PSL_IN3 */               \
-	NPCX_ALT_GPIO_0_2 /* PSL_IN4 */               \
-	NPCX_ALT_GPIO_0_3 /* KSO16 */                 \
-	NPCX_ALT_GPIO_0_4 /* KSO13 */                 \
-	NPCX_ALT_GPIO_0_5 /* KSO12 */                 \
-	NPCX_ALT_GPIO_0_6 /* KSO11 */                 \
-	NPCX_ALT_GPIO_0_7 /* KSO10 */                 \
-	NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */        \
-	NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */       \
-	NPCX_ALT_GPIO_1_2 /* KSO07 */                 \
-	NPCX_ALT_GPIO_1_3 /* KSO06 */                 \
-	NPCX_ALT_GPIO_1_4 /* KSO05 */                 \
-	NPCX_ALT_GPIO_1_5 /* KSO04 */                 \
-	NPCX_ALT_GPIO_1_6 /* KSO03 */                 \
-	NPCX_ALT_GPIO_1_7 /* KSO02 */                 \
-	NPCX_ALT_GPIO_2_0 /* KSO01 */                 \
-	NPCX_ALT_GPIO_2_1 /* KSO00 */                 \
-	NPCX_ALT_GPIO_2_2 /* KSI7 */                  \
-	NPCX_ALT_GPIO_2_3 /* KSI6 */                  \
-	NPCX_ALT_GPIO_2_4 /* KSI5 */                  \
-	NPCX_ALT_GPIO_2_5 /* KSI4 */                  \
-	NPCX_ALT_GPIO_2_6 /* KSI3 */                  \
-	NPCX_ALT_GPIO_2_7 /* KSI2 */                  \
-	NPCX_ALT_GPIO_3_0 /* KSI1 */                  \
-	NPCX_ALT_GPIO_3_1 /* KSI0 */                  \
-	NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */              \
-	NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */         \
-	NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */              \
-	NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */         \
-	NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */              \
-	NPCX_ALT_GPIO_4_1 /* ADC4  */                 \
-	NPCX_ALT_GPIO_4_2 /* ADC3  */                 \
-	NPCX_ALT_GPIO_4_3 /* ADC2  */                 \
-	NPCX_ALT_GPIO_4_4 /* ADC1  */                 \
-	NPCX_ALT_GPIO_4_5 /* ADC0  */                 \
-	NPCX_ALT_GPIO_6_0 /* PWM7 */                  \
-	NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */              \
-	NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */              \
-	NPCX_ALT_GPIO_6_4 /* CR_SIN1 SEL2 */          \
-	NPCX_ALT_GPIO_6_5 /* CR_SOUT1 SEL2 */         \
-	NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */              \
-	NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */              \
-	NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */              \
-	NPCX_ALT_GPIO_7_5 /* CR_SIN2 & 32KHZ_OUT */   \
-	NPCX_ALT_GPIO_8_0 /* PWM3 */                  \
-	NPCX_ALT_GPIO_8_2 /* KSO14 */		      \
-	NPCX_ALT_GPIO_8_3 /* KSO15 */		      \
-	NPCX_ALT_GPIO_8_5 /* SMB4SCL0 */              \
-	NPCX_ALT_GPIO_8_6 /* CR_SOUT2 & SMB4SDA0 */   \
-	NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */              \
-	NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */              \
-	NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */              \
-	NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */              \
-	NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */              \
-	NPCX_ALT_GPIO_9_4 /* DMIC_CLK */              \
-	NPCX_ALT_GPIO_9_5 /* SPIP_MISO */             \
-	NPCX_ALT_GPIO_9_7 /* DMIC_IN */               \
-	NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */             \
-	NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */             \
-	NPCX_ALT_GPIO_A_5 /* SPIP_CS1 & I2S_SYNC */   \
-	NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */     \
-	NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */     \
-	NPCX_ALT_GPIO_B_0 /* I2S_DATA */              \
-	NPCX_ALT_GPIO_B_1 /* KSO17 */		      \
-	NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */              \
-	NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */              \
-	NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */              \
-	NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */              \
-	NPCX_ALT_GPIO_B_6 /* PWM4 */                  \
-	NPCX_ALT_GPIO_B_7 /* PWM5 */                  \
-	NPCX_ALT_GPIO_C_0 /* PWM6 */                  \
-	NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */              \
-	NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */       \
-	NPCX_ALT_GPIO_C_3 /* PWM0 */                  \
-	NPCX_ALT_GPIO_C_4 /* PWM2 */                  \
-	NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */              \
-	NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */              \
-	NPCX_ALT_GPIO_D_2 /* PSL_IN1 */               \
-	NPCX_ALT_GPIO_E_1 /* ADC7  */                 \
-	NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */              \
-	NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */              \
-	NPCX_ALT_GPIO_E_7 /* 32KCLKIN */              \
-	NPCX_ALT_GPIO_F_0 /* ADC9  */                 \
-	NPCX_ALT_GPIO_F_1 /* ADC8  */                 \
-	NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */              \
-	NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */              \
-	NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */              \
-	NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */              \
-}
-
-/*****************************************************************************/
-/* Macro functions for Low-Voltage mapping table */
-
-/* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
-
-/* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
-
-/* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
-#else
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO(8, 4)
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO(8, 5)
-#endif
-
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN */
-#else
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO(E, 7)
-#endif
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
-
-/* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO_NONE /* Remove 1.8V support since CLKOUT*/
-#else
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO(7, 1)
-#endif
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
-
-/* Low-Voltage GPIO Control 4 */
-#define NPCX_LVOL_CTRL_4_0  NPCX_GPIO(8, 6)
-#define NPCX_LVOL_CTRL_4_1  NPCX_GPIO(C, 2)
-#define NPCX_LVOL_CTRL_4_2  NPCX_GPIO(F, 3)
-#define NPCX_LVOL_CTRL_4_3  NPCX_GPIO(F, 2)
-#define NPCX_LVOL_CTRL_4_4  NPCX_GPIO(F, 5)
-#define NPCX_LVOL_CTRL_4_5  NPCX_GPIO(F, 4)
-#define NPCX_LVOL_CTRL_4_6  NPCX_GPIO(E, 4)
-#define NPCX_LVOL_CTRL_4_7  NPCX_GPIO(E, 3)
-
-/* Low-Voltage GPIO Control 5 */
-#define NPCX_LVOL_CTRL_5_0  NPCX_GPIO(7, 2)
-#define NPCX_LVOL_CTRL_5_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_3  NPCX_GPIO(5, 0)
-#define NPCX_LVOL_CTRL_5_4  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_5  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_7  NPCX_GPIO_NONE
-
-/* 6 Low-Voltage Control Groups on npcx7 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(4), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(5), }, }
-
-#endif /* __CROS_EC_GPIO_CHIP_NPCX7_H */
diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h
deleted file mode 100644
index 005a03d83e..0000000000
--- a/chip/npcx/gpio_chip-npcx9.h
+++ /dev/null
@@ -1,470 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GPIO_CHIP_NPCX9_H
-#define __CROS_EC_GPIO_CHIP_NPCX9_H
-
-#ifndef NPCX9_PWM1_SEL
-#define NPCX9_PWM1_SEL 0
-#endif /* NPCX9_PWM1_SEL */
-
-/*****************************************************************************/
-/* Macro functions for MIWU mapping table */
-
-/* MIWU0 */
-/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_TWD_WKINTB_0 */
-#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3)
-#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5)
-
-/* Group C: NPCX_IRQ_WKINTC_0 */
-#define NPCX_WUI_GPIO_9_6 WUI(0, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_A_0 WUI(0, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_A_2 WUI(0, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_A_4 WUI(0, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5)
-#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6)
-
-/* Group E: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4)
-
-/* Group F: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_D_4 WUI(0, MIWU_GROUP_7, 4)
-#define NPCX_WUI_GPIO_D_5 WUI(0, MIWU_GROUP_7, 5)
-#define NPCX_WUI_GPIO_E_0 WUI(0, MIWU_GROUP_7, 7)
-
-/* Group H: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_E_1 WUI(0, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_E_2 WUI(0, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_E_3 WUI(0, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_E_4 WUI(0, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_E_5 WUI(0, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6)
-
-/* MIWU1 */
-/* Group A: NPCX_IRQ_WKINTA_1 */
-#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4)
-#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5)
-#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_WKINTB_1 */
-#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_F_4 WUI(1, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5)
-#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6)
-#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7)
-
-/* Group C: NPCX_IRQ_KSI_WKINTC_1 */
-#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_WKINTD_1 */
-#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_F_5 WUI(1, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3)
-#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4)
-#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6)
-#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7)
-
-/* Group E: NPCX_IRQ_WKINTE_1 */
-#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3)
-#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4)
-#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5)
-#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6)
-#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7)
-
-/* Group F: NPCX_IRQ_WKINTF_1 */
-#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTG_1 */
-#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
-
-/* Group H: NPCX_IRQ_WKINTH_1 */
-#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6)
-
-/* MIWU2 */
-/* Group F: NPCX_IRQ_WKINTFG_2 */
-#define NPCX_WUI_GPIO_F_1 WUI(2, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_F_2 WUI(2, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_B_6 WUI(2, MIWU_GROUP_6, 6)
-
-/* Others GPO without MIWU functionality */
-#define NPCX_WUI_GPIO_1_2 WUI_NONE
-#define NPCX_WUI_GPIO_1_3 WUI_NONE /* Software strap pin GP_SEL1_L */
-#define NPCX_WUI_GPIO_3_2 WUI_NONE
-#define NPCX_WUI_GPIO_3_5 WUI_NONE
-#define NPCX_WUI_GPIO_6_5 WUI_NONE /* Software strap pin FLPRG_L */
-#define NPCX_WUI_GPIO_6_6 WUI_NONE
-#define NPCX_WUI_GPIO_7_7 WUI_NONE
-#define NPCX_WUI_GPIO_8_5 WUI_NONE /* PSL_OUT/GPO85 */
-#define NPCX_WUI_GPIO_D_6 WUI_NONE /* strap pin SHDF_ESPI */
-#define NPCX_WUI_GPIO_D_7 WUI_NONE /* PSL_GPO/GPOD7 */
-
-/*****************************************************************************/
-/* Macro functions for Alternative mapping table */
-
-/* I2C Module */
-#define NPCX_ALT_GPIO_B_4 ALT(B, 4, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SDA0 */
-#define NPCX_ALT_GPIO_B_5 ALT(B, 5, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SCL0 */
-#define NPCX_ALT_GPIO_B_2 ALT(B, 2, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SDA0 */
-#define NPCX_ALT_GPIO_B_3 ALT(B, 3, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SCL0 */
-#define NPCX_ALT_GPIO_8_7 ALT(8, 7, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SDA0 */
-#define NPCX_ALT_GPIO_9_0 ALT(9, 0, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SCL0 */
-#define NPCX_ALT_GPIO_9_1 ALT(9, 1, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SDA0 */
-#define NPCX_ALT_GPIO_9_2 ALT(9, 2, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SCL0 */
-#define NPCX_ALT_GPIO_3_6 ALT(3, 6, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SDA0 */
-#define NPCX_ALT_GPIO_3_3 ALT(3, 3, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SCL0 */
-#define NPCX_ALT_GPIO_D_0 ALT(D, 0, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SDA0 */
-#define NPCX_ALT_GPIO_D_1 ALT(D, 1, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SCL0 */
-
-#define NPCX_ALT_GPIO_F_2 ALT(F, 2, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SDA1 */
-#define NPCX_ALT_GPIO_F_3 ALT(F, 3, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SCL1 */
-#define NPCX_ALT_GPIO_F_4 ALT(F, 4, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SDA1 */
-#define NPCX_ALT_GPIO_F_5 ALT(F, 5, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SCL1 */
-#define NPCX_ALT_GPIO_E_3 ALT(E, 3, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SDA1 */
-#define NPCX_ALT_GPIO_E_4 ALT(E, 4, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SCL1 */
-/* Pin-Mux for PWM1/SMB6_0 */
-#if NPCX9_PWM1_SEL
-#define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL))   /* PWM1 */
-#else
-#define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */
-#endif
-
-/* ADC Module */
-#define NPCX_ALT_GPIO_4_5 ALT(4, 5, NPCX_ALT(6, ADC0_SL)) /* ADC0  */
-#define NPCX_ALT_GPIO_4_4 ALT(4, 4, NPCX_ALT(6, ADC1_SL)) /* ADC1  */
-#define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2  */
-#define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3  */
-#define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4  */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_2)
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
-#else
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5  */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6  */
-#endif
-#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL))  /* ADC8  */
-#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL))  /* ADC7  */
-#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL))  /* ADC9  */
-#define NPCX_ALT_GPIO_E_0 ALT(E, 0, NPCX_ALT(F, ADC10_SL)) /* AD10  */
-#define NPCX_ALT_GPIO_C_7 ALT(C, 7, NPCX_ALT(F, ADC11_SL)) /* AD11  */
-
-/* PS/2 Module */
-#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL))  /* PS2_CLK0 */
-#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL))  /* PS2_DATA0 */
-#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL))  /* PS2_CLK1 */
-#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL))  /* PS2_DATA1 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
-#else
-#define NPCX_ALT_GPIO_A_7
-#endif
-
-/* UART Module */
-#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 */
-#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2))/* CR_SOUT1_SL2 */
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL))  /* CR_SIN2_SL */
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL */
-#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL))  /* CR_SIN3_SL */
-#define NPCX_ALT_GPIO_D_6 ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL */
-
-/* PWM Module */
-#define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */
-#define NPCX_ALT_GPIO_C_4 ALT(C, 4, NPCX_ALT(4, PWM2_SL)) /* PWM2 */
-#define NPCX_ALT_GPIO_8_0 ALT(8, 0, NPCX_ALT(4, PWM3_SL)) /* PWM3 */
-#define NPCX_ALT_GPIO_B_6 ALT(B, 6, NPCX_ALT(4, PWM4_SL)) /* PWM4 */
-#define NPCX_ALT_GPIO_B_7 ALT(B, 7, NPCX_ALT(4, PWM5_SL)) /* PWM5 */
-#define NPCX_ALT_GPIO_C_0 ALT(C, 0, NPCX_ALT(4, PWM6_SL)) /* PWM6 */
-#define NPCX_ALT_GPIO_6_0 ALT(6, 0, NPCX_ALT(4, PWM7_SL)) /* PWM7 */
-
-/* MFT Module */
-#define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */
-#define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */
-#define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
-#else
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
-#endif
-
-/* Keyboard Scan Module */
-#define NPCX_ALT_GPIO_3_1 ALT(3, 1, NPCX_ALT_INV(7, NO_KSI0_SL)) /* KSI0 */
-#define NPCX_ALT_GPIO_3_0 ALT(3, 0, NPCX_ALT_INV(7, NO_KSI1_SL)) /* KSI1 */
-#define NPCX_ALT_GPIO_2_7 ALT(2, 7, NPCX_ALT_INV(7, NO_KSI2_SL)) /* KSI2 */
-#define NPCX_ALT_GPIO_2_6 ALT(2, 6, NPCX_ALT_INV(7, NO_KSI3_SL)) /* KSI3 */
-#define NPCX_ALT_GPIO_2_5 ALT(2, 5, NPCX_ALT_INV(7, NO_KSI4_SL)) /* KSI4 */
-#define NPCX_ALT_GPIO_2_4 ALT(2, 4, NPCX_ALT_INV(7, NO_KSI5_SL)) /* KSI5 */
-#define NPCX_ALT_GPIO_2_3 ALT(2, 3, NPCX_ALT_INV(7, NO_KSI6_SL)) /* KSI6 */
-#define NPCX_ALT_GPIO_2_2 ALT(2, 2, NPCX_ALT_INV(7, NO_KSI7_SL)) /* KSI7 */
-#define NPCX_ALT_GPIO_2_1 ALT(2, 1, NPCX_ALT_INV(8, NO_KSO00_SL)) /* KSO00 */
-#define NPCX_ALT_GPIO_2_0 ALT(2, 0, NPCX_ALT_INV(8, NO_KSO01_SL)) /* KSO01 */
-#define NPCX_ALT_GPIO_1_7 ALT(1, 7, NPCX_ALT_INV(8, NO_KSO02_SL)) /* KSO02 */
-#define NPCX_ALT_GPIO_1_6 ALT(1, 6, NPCX_ALT_INV(8, NO_KSO03_SL)) /* KSO03 */
-#define NPCX_ALT_GPIO_1_5 ALT(1, 5, NPCX_ALT_INV(8, NO_KSO04_SL)) /* KSO04 */
-#define NPCX_ALT_GPIO_1_4 ALT(1, 4, NPCX_ALT_INV(8, NO_KSO05_SL)) /* KSO05 */
-#define NPCX_ALT_GPIO_1_3 ALT(1, 3, NPCX_ALT_INV(8, NO_KSO06_SL)) /* KSO06 */
-#define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
-/* KSO08 & CR_SOUT */
-#define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
- /* KSO09 & CR_SIN */
-#define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
-#define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
-#define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
-#define NPCX_ALT_GPIO_0_5 ALT(0, 5, NPCX_ALT_INV(9, NO_KSO12_SL)) /* KSO12 */
-#define NPCX_ALT_GPIO_0_4 ALT(0, 4, NPCX_ALT_INV(9, NO_KSO13_SL)) /* KSO13 */
-#define NPCX_ALT_GPIO_8_2 ALT(8, 2, NPCX_ALT_INV(9, NO_KSO14_SL)) /* KSO14 */
-#define NPCX_ALT_GPIO_8_3 ALT(8, 3, NPCX_ALT_INV(9, NO_KSO15_SL)) /* KSO15 */
-#define NPCX_ALT_GPIO_0_3 ALT(0, 3, NPCX_ALT_INV(A, NO_KSO16_SL)) /* KSO16 */
-#define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
-
-/* PSL module */
-#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */
-#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */
-#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL))      /* PSL_IN3 */
-#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL))      /* PSL_IN4 */
-#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL))      /* PSL_GPO */
-
-/* SPI Module */
-#define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */
-#define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
-#define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
-
-#define NPCX_ALT_TABLE { \
-	NPCX_ALT_GPIO_0_0 /* PSL_IN2 */               \
-	NPCX_ALT_GPIO_0_1 /* PSL_IN3 */               \
-	NPCX_ALT_GPIO_0_2 /* PSL_IN4 */               \
-	NPCX_ALT_GPIO_0_3 /* KSO16 */                 \
-	NPCX_ALT_GPIO_0_4 /* KSO13 */                 \
-	NPCX_ALT_GPIO_0_5 /* KSO12 */                 \
-	NPCX_ALT_GPIO_0_6 /* KSO11 */                 \
-	NPCX_ALT_GPIO_0_7 /* KSO10 */                 \
-	NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */        \
-	NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */       \
-	NPCX_ALT_GPIO_1_2 /* KSO07 */                 \
-	NPCX_ALT_GPIO_1_3 /* KSO06 */                 \
-	NPCX_ALT_GPIO_1_4 /* KSO05 */                 \
-	NPCX_ALT_GPIO_1_5 /* KSO04 */                 \
-	NPCX_ALT_GPIO_1_6 /* KSO03 */                 \
-	NPCX_ALT_GPIO_1_7 /* KSO02 */                 \
-	NPCX_ALT_GPIO_2_0 /* KSO01 */                 \
-	NPCX_ALT_GPIO_2_1 /* KSO00 */                 \
-	NPCX_ALT_GPIO_2_2 /* KSI7 */                  \
-	NPCX_ALT_GPIO_2_3 /* KSI6 */                  \
-	NPCX_ALT_GPIO_2_4 /* KSI5 */                  \
-	NPCX_ALT_GPIO_2_5 /* KSI4 */                  \
-	NPCX_ALT_GPIO_2_6 /* KSI3 */                  \
-	NPCX_ALT_GPIO_2_7 /* KSI2 */                  \
-	NPCX_ALT_GPIO_3_0 /* KSI1 */                  \
-	NPCX_ALT_GPIO_3_1 /* KSI0 */                  \
-	NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */              \
-	NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */         \
-	NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */              \
-	NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */         \
-	NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */              \
-	NPCX_ALT_GPIO_4_1 /* ADC4  */                 \
-	NPCX_ALT_GPIO_4_2 /* ADC3  */                 \
-	NPCX_ALT_GPIO_4_3 /* ADC2  */                 \
-	NPCX_ALT_GPIO_4_4 /* ADC1  */                 \
-	NPCX_ALT_GPIO_4_5 /* ADC0  */                 \
-	NPCX_ALT_GPIO_6_0 /* PWM7 */                  \
-	NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */              \
-	NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */              \
-	NPCX_ALT_GPIO_6_4 /* CR_SIN1_SL2 */           \
-	NPCX_ALT_GPIO_6_5 /* CR_SOUT1_SL2 */          \
-	NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */              \
-	NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */              \
-	NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */              \
-	NPCX_ALT_GPIO_7_5 /* CR_SIN2_SL */            \
-	NPCX_ALT_GPIO_8_0 /* PWM3 */                  \
-	NPCX_ALT_GPIO_8_2 /* KSO14 */                 \
-	NPCX_ALT_GPIO_8_3 /* KSO15 */                 \
-	NPCX_ALT_GPIO_8_6 /* CR_SOUT2_SL */           \
-	NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */              \
-	NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */              \
-	NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */              \
-	NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */              \
-	NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */              \
-	NPCX_ALT_GPIO_9_5 /* SPIP_MISO */             \
-	NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */             \
-	NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */             \
-	NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */     \
-	NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */     \
-	NPCX_ALT_GPIO_B_1 /* KSO17 */                 \
-	NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */              \
-	NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */              \
-	NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */              \
-	NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */              \
-	NPCX_ALT_GPIO_B_6 /* PWM4 */                  \
-	NPCX_ALT_GPIO_B_7 /* PWM5 */                  \
-	NPCX_ALT_GPIO_C_0 /* PWM6 */                  \
-	NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */              \
-	NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */       \
-	NPCX_ALT_GPIO_C_3 /* PWM0 */                  \
-	NPCX_ALT_GPIO_C_4 /* PWM2 */                  \
-	NPCX_ALT_GPIO_C_7 /* ADC11 */                 \
-	NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */              \
-	NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */              \
-	NPCX_ALT_GPIO_D_2 /* PSL_IN1 */               \
-	NPCX_ALT_GPIO_D_4 /* CR_SIN3_SL */            \
-	NPCX_ALT_GPIO_D_6 /* CR_SOUT3_SL */           \
-	NPCX_ALT_GPIO_D_7 /* PSL_GPO */               \
-	NPCX_ALT_GPIO_E_0 /* ADC10 */                 \
-	NPCX_ALT_GPIO_E_1 /* ADC7  */                 \
-	NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */              \
-	NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */              \
-	NPCX_ALT_GPIO_F_0 /* ADC9  */                 \
-	NPCX_ALT_GPIO_F_1 /* ADC8  */                 \
-	NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */              \
-	NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */              \
-	NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */              \
-	NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */              \
-}
-
-/*****************************************************************************/
-/* Macro functions for Low-Voltage mapping table */
-
-/* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
-
-/* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
-
-/* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
-
-/* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
-
-/* Low-Voltage GPIO Control 4 */
-#define NPCX_LVOL_CTRL_4_0  NPCX_GPIO(8, 6)
-#define NPCX_LVOL_CTRL_4_1  NPCX_GPIO(C, 2)
-#define NPCX_LVOL_CTRL_4_2  NPCX_GPIO(F, 3)
-#define NPCX_LVOL_CTRL_4_3  NPCX_GPIO(F, 2)
-#define NPCX_LVOL_CTRL_4_4  NPCX_GPIO(F, 5)
-#define NPCX_LVOL_CTRL_4_5  NPCX_GPIO(F, 4)
-#define NPCX_LVOL_CTRL_4_6  NPCX_GPIO(E, 4)
-#define NPCX_LVOL_CTRL_4_7  NPCX_GPIO(E, 3)
-
-/* Low-Voltage GPIO Control 5 */
-#define NPCX_LVOL_CTRL_5_0  NPCX_GPIO(7, 2)
-#define NPCX_LVOL_CTRL_5_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_3  NPCX_GPIO(5, 0)
-#define NPCX_LVOL_CTRL_5_4  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_5  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_7  NPCX_GPIO_NONE
-
-/* 6 Low-Voltage Control Groups on npcx7 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(4), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(5), }, }
-
-#endif /* __CROS_EC_GPIO_CHIP_NPCX9_H */
diff --git a/chip/npcx/gpio_chip.h b/chip/npcx/gpio_chip.h
deleted file mode 100644
index 2d0b2b4e9b..0000000000
--- a/chip/npcx/gpio_chip.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GPIO_CHIP_H
-#define __CROS_EC_GPIO_CHIP_H
-
-struct npcx_wui {
-	uint8_t table : 2;
-	uint8_t group : 3;
-	uint8_t bit   : 3;
-};
-
-/* Macros to initialize the MIWU mapping table. */
-#define NPCX_WUI_GPIO_PIN(port, index) NPCX_WUI_GPIO_##port##_##index
-#define WUI(tbl, grp, idx) ((struct npcx_wui) { .table = tbl, .group = grp, \
-						.bit = idx })
-#define WUI_INT(tbl, grp)  WUI(tbl, grp, 0)
-#define WUI_NONE ((struct npcx_wui) { .table = MIWU_TABLE_COUNT, .group = 0, \
-				      .bit = 0 })
-
-/* Macros to initialize the alternative and low voltage mapping table. */
-#define NPCX_GPIO_NONE ((struct npcx_gpio) {.port = 0, .bit = 0, .valid = 0})
-#define NPCX_GPIO(grp, pin) ((struct npcx_gpio) {.port = GPIO_PORT_##grp, \
-							.bit = pin, .valid = 1})
-
-#define NPCX_ALT(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
-			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 0 })
-#define NPCX_ALT_INV(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
-			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 1 })
-#define ALT(port, index, _alt) { .gpio = NPCX_GPIO(port, index), \
-			.alt = (_alt) },
-
-#define NPCX_LVOL_CTRL_ITEMS(ctrl) { NPCX_LVOL_CTRL_##ctrl##_0, \
-				     NPCX_LVOL_CTRL_##ctrl##_1, \
-				     NPCX_LVOL_CTRL_##ctrl##_2, \
-				     NPCX_LVOL_CTRL_##ctrl##_3, \
-				     NPCX_LVOL_CTRL_##ctrl##_4, \
-				     NPCX_LVOL_CTRL_##ctrl##_5, \
-				     NPCX_LVOL_CTRL_##ctrl##_6, \
-				     NPCX_LVOL_CTRL_##ctrl##_7, }
-
-/**
- * Switch NPCX UART pins back to normal GPIOs.
- */
-void npcx_uart2gpio(void);
-
-/**
- * Switch NPCX UART pins to UART mode (depending on the currently selected
- * pad, see uart.c).
- */
-void npcx_gpio2uart(void);
-
-/* Set input buffer of all 1.8v i2c ports. */
-void gpio_enable_1p8v_i2c_wake_up_input(int enable);
-
-void gpio_interrupt(struct npcx_wui wui_int);
-
-/*
- * Include the MIWU, alternative and low-Voltage macro functions for GPIOs
- * depends on Nuvoton chip series.
- */
-#if defined(CHIP_FAMILY_NPCX5)
-#include "gpio_chip-npcx5.h"
-#elif defined(CHIP_FAMILY_NPCX7)
-#include "gpio_chip-npcx7.h"
-#elif defined(CHIP_FAMILY_NPCX9)
-#include "gpio_chip-npcx9.h"
-#else
-#error "Unsupported chip family"
-#endif
-
-#endif /* __CROS_EC_GPIO_CHIP_H */
diff --git a/chip/npcx/header.c b/chip/npcx/header.c
deleted file mode 100644
index 0ba3ee59d6..0000000000
--- a/chip/npcx/header.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Booter header for Chrome EC.
- *
- * This header is used by Nuvoton EC Booter.
- */
-
-#include <stdint.h>
-
-#include "config.h"
-#include "registers.h"
-
-/* Signature used by fw header */
-#define SIG_FW_EC           0x2A3B4D5E
-
-/* Definition used by error detection configuration */
-#define CHECK_CRC	    0x00
-#define CHECK_CHECKSUM	    0x01
-#define ERROR_DETECTION_EN  0x02
-#define ERROR_DETECTION_DIS 0x00
-
-/* Code RAM addresses use by header */
-/* Put FW at the begin of CODE RAM */
-#define FW_START_ADDR  CONFIG_PROGRAM_MEMORY_BASE
-
-/* TODO: It will be filled automatically by ECST */
-/* The entry point of reset handler (filled by ECST tool)*/
-#define FW_ENTRY_ADDR  0x100A8169
-
-/* Error detection addresses use by header (A offset relative to flash image) */
-#define ERRCHK_START_ADDR  0x0
-#define ERRCHK_END_ADDR    0x0
-
-/* Firmware Size -> Booter loads RO region after hard reset (16 bytes aligned)*/
-#define FW_SIZE            CONFIG_RO_SIZE
-
-/* FW Header used by NPCX5M5G Booter */
-struct __packed fw_header_t {
-	uint32_t anchor;         /* A constant used to verify FW header       */
-	uint16_t ext_anchor;     /* Enable/disable firmware header CRC check  */
-	uint8_t  spi_max_freq;   /* Spi maximum allowable clock frequency     */
-	uint8_t  spi_read_mode;  /* Spi read mode used for firmware loading   */
-	uint8_t  cfg_err_detect; /* FW load error detection configuration     */
-	uint32_t fw_load_addr;   /* Firmware load start address               */
-	uint32_t fw_entry;       /* Firmware entry point                      */
-	uint32_t err_detect_start_addr; /* FW error detect start address      */
-	uint32_t err_detect_end_addr;   /* FW error detect end address        */
-	uint32_t fw_length;      /* Firmware length in bytes                  */
-	uint8_t  flash_size;     /* Indicate SPI flash size                   */
-	uint8_t  reserved[26];   /* Reserved bytes                            */
-	uint32_t sig_header;     /* The CRC signature of the firmware header  */
-	uint32_t sig_fw_image;   /* The CRC or Checksum of the firmware image */
-} __aligned(1);
-
-__keep  __attribute__ ((section(".header")))
-const struct fw_header_t fw_header = {
-	/* 00 */ SIG_FW_EC,
-	/* 04 */ 0x54E1, /* Header CRC check Enable/Disable -> AB1Eh/54E1h    */
-	/* 06 */ 0x04,   /* 20/25/33/40/50 MHz -> 00/01/02/03/04h             */
-	/* 07 */ 0x03,   /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
-	/* 08 */ 0x00,   /* Disable CRC check functionality */
-	/* 09 */ FW_START_ADDR,
-	/* 0D */ FW_ENTRY_ADDR,/* Filling by ECST tool with -usearmrst option */
-	/* 11 */ ERRCHK_START_ADDR,
-	/* 15 */ ERRCHK_END_ADDR,
-	/* 19 */ FW_SIZE,/* Filling by ECST tool */
-	/* 1D */ 0x0F,   /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh   */
-	/* 1E-3F Other fields are filled by ECST tool or reserved         */
-};
diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c
deleted file mode 100644
index 92f9843d09..0000000000
--- a/chip/npcx/hwtimer.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "math_util.h"
-#include "registers.h"
-#include "console.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Depth of event timer */
-#define TICK_EVT_DEPTH         16 /* Depth of event timer Unit: bits */
-#define TICK_EVT_INTERVAL      BIT(TICK_EVT_DEPTH) /* Unit: us */
-#define TICK_EVT_INTERVAL_MASK (TICK_EVT_INTERVAL - 1) /* Mask of interval */
-#define TICK_EVT_MAX_CNT     (TICK_EVT_INTERVAL - 1) /* Maximum event counter */
-
-/* Time when event will be expired unit:us */
-static volatile uint32_t evt_expired_us;
-/* 32-bits event counter */
-static volatile uint32_t evt_cnt;
-/* Debugger information */
-#if DEBUG_TMR
-static volatile uint32_t evt_cnt_us_dbg;
-static volatile uint32_t cur_cnt_us_dbg;
-#endif
-
-#if !(DEBUG_TMR)
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-#endif
-
-/*****************************************************************************/
-/* Internal functions */
-void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source)
-{
-	/* Select which clock to use for this timer */
-	UPDATE_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_CKSEL,
-			source != ITIM_SOURCE_CLOCK_APB2);
-
-	/* Clear timeout status */
-	SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_STS);
-
-	/* ITIM timeout interrupt enable */
-	SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_IE);
-
-	/* ITIM timeout wake-up enable */
-	SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_WUE);
-}
-
-/*****************************************************************************/
-/* HWTimer event handlers */
-void __hw_clock_event_set(uint32_t deadline)
-{
-	fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK/(float)SECOND);
-	int32_t  evt_cnt_us;
-	/* Is deadline min value? */
-	if (evt_expired_us != 0 && evt_expired_us < deadline)
-		return;
-
-	/* mark min event value */
-	evt_expired_us = deadline;
-	evt_cnt_us = deadline - __hw_clock_source_read();
-#if DEBUG_TMR
-	evt_cnt_us_dbg = deadline - __hw_clock_source_read();
-#endif
-	/* Deadline is behind current timer */
-	if (evt_cnt_us < 0)
-		evt_cnt_us = 1;
-
-	/* Event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-
-	/*
-	 * ITIM count down : event expired : Unit: 1/32768 sec
-	 * It must exceed evt_expired_us for process_timers function
-	 */
-	evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us) * inv_evt_tick);
-	if (evt_cnt > TICK_EVT_MAX_CNT) {
-		CPRINTS("Event overflow! 0x%08x, us is %d",
-				evt_cnt, evt_cnt_us);
-		evt_cnt = TICK_EVT_MAX_CNT;
-	}
-
-	/* Wait for module disable to take effect before updating count */
-	while (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN))
-		;
-
-	NPCX_ITCNT(ITIM_EVENT_NO) = MAX(evt_cnt, 1);
-
-	/* Event module enable */
-	SET_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-
-	/* Wait for module enable */
-	while (!IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN))
-		;
-
-	/* Enable interrupt of ITIM */
-	task_enable_irq(ITIM_INT(ITIM_EVENT_NO));
-}
-
-/* Returns the time-stamp of the next programmed event */
-uint32_t __hw_clock_event_get(void)
-{
-	if (evt_expired_us)
-		return evt_expired_us;
-	else /* No events. Give maximum deadline */
-		return EVT_MAX_EXPIRED_US;
-}
-
-/* Get current counter value of event timer */
-uint16_t __hw_clock_event_count(void)
-{
-	uint16_t cnt, cnt2;
-
-	cnt = NPCX_ITCNT(ITIM_EVENT_NO);
-	/* Wait for two consecutive equal values are read */
-	while ((cnt2 = NPCX_ITCNT(ITIM_EVENT_NO)) != cnt)
-		cnt = cnt2;
-
-	return cnt;
-}
-
-/* Returns time delay cause of deep idle */
-uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt)
-{
-	fp_t evt_tick = FLOAT_TO_FP(SECOND/(float)INT_32K_CLOCK);
-	uint32_t sleep_time;
-	uint16_t cnt = __hw_clock_event_count();
-
-	/* Event has been triggered but timer ISR doesn't handle it */
-	if (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS))
-		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1) * evt_tick);
-	/* Event hasn't been triggered */
-	else
-		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1 - cnt) *
-				       evt_tick);
-
-	return sleep_time;
-}
-
-/* Cancel the next event programmed by __hw_clock_event_set */
-void __hw_clock_event_clear(void)
-{
-	/* ITIM event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-
-	/* Disable interrupt of Event */
-	task_disable_irq(ITIM_INT(ITIM_EVENT_NO));
-
-	/* Clear event parameters */
-	evt_expired_us = 0;
-	evt_cnt = 0;
-}
-
-/* Irq for hwtimer event */
-void __hw_clock_event_irq(void)
-{
-	/* ITIM event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-
-	/* Disable interrupt of event */
-	task_disable_irq(ITIM_INT(ITIM_EVENT_NO));
-
-	/* Clear timeout status for event */
-	SET_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS);
-
-	/* Clear event parameters */
-	evt_expired_us = 0;
-	evt_cnt = 0;
-
-	/* handle upper driver */
-	process_timers(0);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * Set event for ITIM32 after process_timers() since no events set if
-	 * event's deadline is over 32 bits but current source clock isn't.
-	 * ITIM32 is based on apb2 and ec won't wake-up in deep-idle even if it
-	 * expires.
-	 */
-	if (evt_expired_us == 0)
-		__hw_clock_event_set(EVT_MAX_EXPIRED_US);
-#endif
-
-}
-DECLARE_IRQ(ITIM_INT(ITIM_EVENT_NO), __hw_clock_event_irq, 3);
-
-/*****************************************************************************/
-/* HWTimer tick handlers */
-
-/* Modify preload counter of source clock. */
-void hw_clock_source_set_preload(uint32_t ts, uint8_t clear)
-{
-	/* ITIM32 module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_ITEN);
-	CLEAR_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_CKSEL);
-
-	/* Set preload counter to current time */
-	NPCX_ITCNT_SYSTEM = TICK_ITIM32_MAX_CNT - ts;
-	/* Clear timeout status or not */
-	if (clear)
-		SET_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_TO_STS);
-	/* ITIM32 module enable */
-	SET_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_ITEN);
-}
-
-/* Returns the value of the free-running counter used as clock. */
-uint32_t __hw_clock_source_read(void)
-{
-	uint32_t cnt, cnt2;
-
-	cnt = NPCX_ITCNT_SYSTEM;
-	/*
-	 * Wait for two consecutive equal values are read no matter
-	 * ITIM's source clock is APB2 or 32K since mux's delay.
-	 */
-	while ((cnt2 = NPCX_ITCNT_SYSTEM) != cnt)
-		cnt = cnt2;
-
-#if DEBUG_TMR
-	cur_cnt_us_dbg = TICK_ITIM32_MAX_CNT - cnt;
-#endif
-	return TICK_ITIM32_MAX_CNT - cnt;
-}
-
-/* Override the current value of the hardware counter */
-void __hw_clock_source_set(uint32_t ts)
-{
-#if DEBUG_TMR
-	cur_cnt_us_dbg = TICK_ITIM32_MAX_CNT - ts;
-#endif
-	hw_clock_source_set_preload(ts, 0);
-}
-
-/* Irq for hwtimer tick */
-void __hw_clock_source_irq(void)
-{
-	/* Is timeout trigger trigger? */
-	if (IS_BIT_SET(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_TO_STS)) {
-		/* Restore ITIM32 preload counter value to maximum value */
-		hw_clock_source_set_preload(0, 1);
-		/* 32-bits timer count overflow */
-		process_timers(1);
-
-	} else { /* Handle soft trigger */
-		process_timers(0);
-#ifdef CONFIG_LOW_POWER_IDLE
-		/* Set event for ITIM32. Please see above for detail */
-		if (evt_expired_us == 0)
-			__hw_clock_event_set(EVT_MAX_EXPIRED_US);
-#endif
-	}
-}
-DECLARE_IRQ(ITIM_INT(ITIM_SYSTEM_NO), __hw_clock_source_irq, 3);
-
-/* Handle ITIM32 overflow if interrupt is disabled */
-void __hw_clock_handle_overflow(uint32_t clksrc_high)
-{
-	timestamp_t newtime;
-
-	/* Overflow occurred? */
-	if (!IS_BIT_SET(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_TO_STS))
-		return;
-
-	/* Clear timeout status */
-	SET_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_TO_STS);
-
-	/*
-	 * Restore ITIM32 preload counter value to maximum and execute
-	 * process_timers() later in ISR by trigger software interrupt in
-	 * force_time().
-	 */
-	newtime.le.hi = clksrc_high + 1;
-	newtime.le.lo = 0;
-	force_time(newtime);
-}
-
-static void update_prescaler(void)
-{
-	/*
-	 * prescaler to time tick
-	 * Ttick_unit = (PRE_8+1) * Tapb2_clk
-	 * PRE_8 = (Ttick_unit/Tapb2_clk) -1
-	 */
-	NPCX_ITPRE(ITIM_SYSTEM_NO)  = (clock_get_apb2_freq() / SECOND) - 1;
-	/* Set event tick unit = 1/32768 sec */
-	NPCX_ITPRE(ITIM_EVENT_NO) = 0;
-
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-
-void __hw_early_init_hwtimer(uint32_t start_t)
-{
-	/*
-	 * 1. Use ITIM16-1 as internal time reading
-	 * 2. Use ITIM16-2 for event handling
-	 */
-
-	/* Enable clock for ITIM peripheral */
-	clock_enable_peripheral(CGC_OFFSET_TIMER, CGC_TIMER_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* init tick & event timer first */
-	init_hw_timer(ITIM_SYSTEM_NO,  ITIM_SOURCE_CLOCK_APB2);
-	init_hw_timer(ITIM_EVENT_NO, ITIM_SOURCE_CLOCK_32K);
-
-	/* Set initial prescaler */
-	update_prescaler();
-
-	hw_clock_source_set_preload(start_t, 1);
-}
-
-/* Note that early_init_hwtimer() has already executed by this point */
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * Override the count with the start value now that counting has
-	 * started. Note that we may have already called this function from
-	 * gpio_pre_init(), but only in the case where we expected a reset, so
-	 * we should not get here in that case.
-	 */
-	__hw_early_init_hwtimer(start_t);
-
-	/* Enable interrupt of ITIM */
-	task_enable_irq(ITIM_INT(ITIM_SYSTEM_NO));
-
-	return ITIM_INT(ITIM_SYSTEM_NO);
-}
diff --git a/chip/npcx/hwtimer_chip.h b/chip/npcx/hwtimer_chip.h
deleted file mode 100644
index 987f3b52bd..0000000000
--- a/chip/npcx/hwtimer_chip.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific hwtimer module for Chrome EC */
-
-#ifndef __CROS_EC_HWTIMER_CHIP_H
-#define __CROS_EC_HWTIMER_CHIP_H
-
-/* Use ITIM32 as main hardware timer */
-#define TICK_ITIM32_MAX_CNT  0xFFFFFFFF
-/* Maximum deadline of event */
-#define EVT_MAX_EXPIRED_US   TICK_ITIM32_MAX_CNT
-
-/* Clock source for ITIM16 */
-enum ITIM_SOURCE_CLOCK_T {
-	ITIM_SOURCE_CLOCK_APB2 = 0,
-	ITIM_SOURCE_CLOCK_32K  = 1,
-};
-
-/**
- * Initialise a hardware timer
- *
- * Select the source clock for a timer and prepare it for use.
- *
- * @param itim_no	Timer number to init (enum ITIM_MODULE_T)
- * @param source	Source for timer clock (enum ITIM_SOURCE_CLOCK_T)
- */
-void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source);
-
-/* Returns the counter value of event timer */
-uint16_t __hw_clock_event_count(void);
-
-/* Returns time delay because of deep idle */
-uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt);
-
-/* Handle ITIM32 overflow if interrupt is disabled */
-void __hw_clock_handle_overflow(uint32_t clksrc_high);
-
-/**
- * Set up the timer for use before the task system is available
- *
- * @param start_t	Value to assign to the counter
- */
-void __hw_early_init_hwtimer(uint32_t start_t);
-
-#endif /* __CROS_EC_HWTIMER_CHIP_H */
diff --git a/chip/npcx/i2c-npcx5.c b/chip/npcx/i2c-npcx5.c
deleted file mode 100644
index 6b78fd53f9..0000000000
--- a/chip/npcx/i2c-npcx5.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C module driver depends on chip series for Chrome EC */
-
-#include "i2c.h"
-#include "i2c_chip.h"
-#include "registers.h"
-#include "util.h"
-
-/*****************************************************************************/
-/* IC specific low-level driver depends on chip series */
-
-int i2c_port_to_controller(int port)
-{
-	if (port < 0 || port >= I2C_PORT_COUNT)
-		return -1;
-
-	return (port == NPCX_I2C_PORT0_0) ? 0 : port - 1;
-}
-
-void i2c_select_port(int port)
-{
-	/*
-	 * I2C0_1 uses port 1 of controller 0. All other I2C pin sets
-	 * use port 0.
-	 */
-	if (port > NPCX_I2C_PORT0_1)
-		return;
-
-	/* Select IO pins for multi-ports I2C controllers */
-	UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB0SEL,
-			(port == NPCX_I2C_PORT0_1));
-}
-
-int i2c_is_raw_mode(int port)
-{
-	int bit = (port > NPCX_I2C_PORT0_1) ? ((port - 1) * 2) : port;
-
-	if (IS_BIT_SET(NPCX_DEVALT(2), bit))
-		return 0;
-	else
-		return 1;
-}
-
diff --git a/chip/npcx/i2c-npcx7.c b/chip/npcx/i2c-npcx7.c
deleted file mode 100644
index 3f27aff49e..0000000000
--- a/chip/npcx/i2c-npcx7.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C module driver depends on chip series for Chrome EC */
-
-#include "common.h"
-#include "i2c.h"
-#include "i2c_chip.h"
-#include "registers.h"
-#include "util.h"
-
-/*****************************************************************************/
-/* IC specific low-level driver depends on chip series */
-
-int i2c_port_to_controller(int port)
-{
-	if (port < 0 || port >= I2C_PORT_COUNT)
-		return -1;
-
-	if (port <= NPCX_I2C_PORT3_0)
-		return port;
-#ifndef NPCX_PSL_MODE_SUPPORT
-	else if (port == NPCX_I2C_PORT4_0)
-		return 4;
-#endif
-	else /* If port >= NPCX_I2C_PORT4_1 */
-		return 4 + ((port - NPCX_I2C_PORT4_1 + 1) / 2);
-}
-
-void i2c_select_port(int port)
-{
-	/* Only I2C 4/5/6 have multiple ports in series npcx7 */
-	if (port <= NPCX_I2C_PORT3_0 || port >= NPCX_I2C_PORT7_0)
-		return;
-	/* Select I2C ports for the same controller */
-	else if (port <= NPCX_I2C_PORT4_1) {
-		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL,
-			(port == NPCX_I2C_PORT4_1));
-	} else if (port <= NPCX_I2C_PORT5_1) {
-		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL,
-			(port == NPCX_I2C_PORT5_1));
-	} else {
-		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL,
-			(port == NPCX_I2C_PORT6_1));
-	}
-}
-
-int i2c_is_raw_mode(int port)
-{
-	int group, bit;
-
-	if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 ||
-			port == NPCX_I2C_PORT6_1) {
-		group = 6;
-		bit = 7 - (port - NPCX_I2C_PORT4_1) / 2;
-	} else {
-		group = 2;
-		if (port <= NPCX_I2C_PORT3_0)
-			bit = 2 * port;
-		else
-			bit = I2C_PORT_COUNT - port;
-	}
-
-	if (IS_BIT_SET(NPCX_DEVALT(group), bit))
-		return 0;
-	else
-		return 1;
-}
diff --git a/chip/npcx/i2c-npcx9.c b/chip/npcx/i2c-npcx9.c
deleted file mode 120000
index b1b16a3198..0000000000
--- a/chip/npcx/i2c-npcx9.c
+++ /dev/null
@@ -1 +0,0 @@
-i2c-npcx7.c
\ No newline at end of file
diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c
deleted file mode 100644
index 26935f778f..0000000000
--- a/chip/npcx/i2c.c
+++ /dev/null
@@ -1,1224 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for Chrome EC */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "i2c_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#if !(DEBUG_I2C)
-#define CPUTS(...)
-#define CPRINTS(...)
-#define CPRINTF(...)
-#else
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#endif
-
-/* Timeout for device should be available after reset (SMBus spec. unit:ms) */
-#define I2C_MAX_TIMEOUT 35
-/*
- * Timeout for SCL held to low by peripheral device. (SMBus spec. unit:ms).
- * Some I2C devices may violate this timing and clock stretch for longer.
- * TODO: Consider increasing this timeout.
- */
-#define I2C_MIN_TIMEOUT 25
-
-/*
- * I2C module that supports FIFO mode has 32 bytes Tx FIFO and
- * 32 bytes Rx FIFO.
- */
-#define NPCX_I2C_FIFO_MAX_SIZE    32
-
-/* Macro functions of I2C */
-#define I2C_START(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_START)
-#define I2C_STOP(ctrl)  SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP)
-#define I2C_NACK(ctrl)  SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK)
-/* I2C module automatically stall bus after sending peripheral address */
-#define I2C_STALL(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STASTRE)
-#define I2C_WRITE_BYTE(ctrl, data) (NPCX_SMBSDA(ctrl) = data)
-#define I2C_READ_BYTE(ctrl, data)  (data = NPCX_SMBSDA(ctrl))
-#define I2C_TX_FIFO_OCCUPIED(ctrl) (NPCX_SMBTXF_STS(ctrl) & 0x3F)
-#define I2C_TX_FIFO_AVAILABLE(ctrl) \
-		(NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl))
-
-#define I2C_RX_FIFO_OCCUPIED(ctrl) (NPCX_SMBRXF_STS(ctrl) & 0x3F)
-#define I2C_RX_FIFO_AVAILABLE(ctrl) \
-			(NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl))
-/* Drive the SCL signal to low */
-#define I2C_SCL_STALL(ctrl) \
-		(NPCX_SMBCTL3(ctrl) = \
-			(NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \
-			 BIT(NPCX_SMBCTL3_SDA_LVL))
-/*
- * Release the SCL signal to be pulled up to high level.
- * Note: The SCL might be still driven low either by I2C module or external
- * devices connected to ths bus.
- */
-#define I2C_SCL_FREE(ctrl) \
-		(NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \
-			 BIT(NPCX_SMBCTL3_SDA_LVL))
-
-/* Error values that functions can return */
-enum smb_error {
-	SMB_OK = 0,                 /* No error                           */
-	SMB_CH_OCCUPIED,            /* Channel is already occupied        */
-	SMB_MEM_POOL_INIT_ERROR,    /* Memory pool initialization error   */
-	SMB_BUS_FREQ_ERROR,         /* SMbus freq was not valid           */
-	SMB_INVLAID_REGVALUE,       /* Invalid SMbus register value       */
-	SMB_UNEXIST_CH_ERROR,       /* Channel does not exist             */
-	SMB_NO_SUPPORT_PTL,         /* Not support SMBus Protocol         */
-	SMB_BUS_ERROR,              /* Encounter bus error                */
-	SMB_NO_ADDRESS_MATCH,       /* No peripheral address match        */
-				    /*  (Controller Mode)                 */
-	SMB_READ_DATA_ERROR,        /* Read data for SDA error            */
-	SMB_READ_OVERFLOW_ERROR,    /* Read data over than we predict     */
-	SMB_TIMEOUT_ERROR,          /* Timeout expired                    */
-	SMB_MODULE_ISBUSY,          /* Module is occupied by other device */
-	SMB_BUS_BUSY,               /* SMBus is occupied by other device  */
-};
-
-/*
- * Internal SMBus Interface driver states values, which reflect events
- * which occurred on the bus
- */
-enum smb_oper_state_t {
-	SMB_IDLE,
-	SMB_CONTROLLER_START,
-	SMB_WRITE_OPER,
-	SMB_READ_OPER,
-	SMB_FAKE_READ_OPER,
-	SMB_REPEAT_START,
-	SMB_WRITE_SUSPEND,
-	SMB_READ_SUSPEND,
-};
-
-/* I2C controller state data */
-struct i2c_status {
-	int                   flags;     /* Flags (I2C_XFER_*) */
-	const uint8_t        *tx_buf;    /* Entry pointer of transmit buffer */
-	uint8_t              *rx_buf;    /* Entry pointer of receive buffer  */
-	uint16_t              sz_txbuf;  /* Size of Tx buffer in bytes */
-	uint16_t              sz_rxbuf;  /* Size of rx buffer in bytes */
-	uint16_t              idx_buf;   /* Current index of Tx/Rx buffer */
-	uint16_t              addr_flags;/* Target address */
-	enum smb_oper_state_t oper_state;/* Smbus operation state */
-	enum smb_error        err_code;  /* Error code */
-	int                   task_waiting; /* Task waiting on controller */
-	uint32_t              timeout_us;/* Transaction timeout */
-	uint16_t              kbps;      /* Speed */
-};
-/* I2C controller state data array */
-static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT];
-
-/* I2C timing setting */
-struct i2c_timing {
-	uint8_t clock; /* I2C source clock. (Unit: MHz)*/
-	uint8_t HLDT;  /* I2C hold-time. (Unit: clocks) */
-	uint8_t k1;    /* k1 = SCL low-time (Unit: clocks) */
-	uint8_t k2;    /* k2 = SCL high-time (Unit: clocks) */
-};
-
-/* I2C timing setting array of 400K & 1M Hz */
-static const struct i2c_timing i2c_400k_timings[] = {
-	{20,  7, 32, 22},
-	{15,  7, 24, 18},};
-const unsigned int i2c_400k_timing_used = ARRAY_SIZE(i2c_400k_timings);
-
-static const struct i2c_timing i2c_1m_timings[] = {
-	{20, 7, 16, 10},
-	{15, 7, 14, 10},};
-const unsigned int i2c_1m_timing_used = ARRAY_SIZE(i2c_1m_timings);
-
-/* IRQ for each port */
-const uint32_t i2c_irqs[I2C_CONTROLLER_COUNT] = {
-		NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4,
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-		NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_CONTROLLER_COUNT);
-
-static void i2c_init_bus(int controller)
-{
-	/* Enable FIFO mode */
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-		SET_BIT(NPCX_SMBFIF_CTL(controller), NPCX_SMBFIF_CTL_FIFO_EN);
-
-	/* Enable module - before configuring CTL1 */
-	SET_BIT(NPCX_SMBCTL2(controller), NPCX_SMBCTL2_ENABLE);
-
-	/* Enable SMB interrupt and New Address Match interrupt source */
-	SET_BIT(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_NMINTE);
-	SET_BIT(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_INTEN);
-}
-
-int i2c_bus_busy(int controller)
-{
-	return IS_BIT_SET(NPCX_SMBCST(controller), NPCX_SMBCST_BB) ? 1 : 0;
-}
-
-static int i2c_wait_stop_completed(int controller, int timeout)
-{
-	if (timeout <= 0)
-		return EC_ERROR_INVAL;
-
-	/* Wait till STOP condition is generated. ie. I2C bus is idle. */
-	while (timeout > 0) {
-		if (!IS_BIT_SET(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_STOP))
-			break;
-		if (--timeout > 0)
-			msleep(1);
-	}
-
-	if (timeout)
-		return EC_SUCCESS;
-	else
-		return EC_ERROR_TIMEOUT;
-}
-
-static void i2c_abort_data(int controller)
-{
-	/* Clear NEGACK, STASTR and BER bits */
-	SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_BER);
-	SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_STASTR);
-	SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK);
-
-	/* Wait till STOP condition is generated */
-	if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT)
-			!= EC_SUCCESS) {
-		cprintf(CC_I2C, "Abort i2c %02x fail!\n", controller);
-		/* Clear BB (BUS BUSY) bit */
-		SET_BIT(NPCX_SMBCST(controller), NPCX_SMBCST_BB);
-		return;
-	}
-
-	/* Clear BB (BUS BUSY) bit */
-	SET_BIT(NPCX_SMBCST(controller), NPCX_SMBCST_BB);
-}
-
-static int i2c_reset(int controller)
-{
-	uint16_t timeout = I2C_MAX_TIMEOUT;
-
-	/* Disable the SMB module */
-	CLEAR_BIT(NPCX_SMBCTL2(controller), NPCX_SMBCTL2_ENABLE);
-
-	while (--timeout) {
-		/* WAIT FOR SCL & SDA IS HIGH */
-		if (IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SCL_LVL)
-		  && IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL))
-			break;
-		msleep(1);
-	}
-
-	if (timeout == 0) {
-		cprintf(CC_I2C, "Reset i2c %02x fail!\n", controller);
-		return 0;
-	}
-
-	/* Init the SMB module again */
-	i2c_init_bus(controller);
-	return 1;
-}
-
-static void i2c_select_bank(int controller, int bank)
-{
-	if (bank)
-		SET_BIT(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_BNK_SEL);
-	else
-		CLEAR_BIT(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_BNK_SEL);
-}
-
-static void i2c_stall_bus(int controller, int stall)
-{
-	i2c_select_bank(controller, 0);
-	/*
-	 * Enable the writing to SCL_LVL and SDA_LVL bit in
-	 * SMBnCTL3 register. Then, firmware can set SCL_LVL to 0 to
-	 * stall the bus when needed. Note: this register should be
-	 * accessed when bank = 0.
-	 */
-	SET_BIT(NPCX_SMBCTL4(controller), NPCX_SMBCTL4_LVL_WE);
-	if (stall)
-		I2C_SCL_STALL(controller);
-	else
-		I2C_SCL_FREE(controller);
-	/*
-	 * Disable the writing to SCL_LVL and SDA_LVL bit in
-	 * SMBnCTL3 register. It will prevent form changing the level of
-	 * SCL/SDA when touching other bits in SMBnCTL3 register.
-	 */
-	CLEAR_BIT(NPCX_SMBCTL4(controller), NPCX_SMBCTL4_LVL_WE);
-	i2c_select_bank(controller, 1);
-}
-
-static void i2c_recovery(int controller, volatile struct i2c_status *p_status)
-{
-	cprintf(CC_I2C,
-		"i2c %d recovery! error code is %d, current state is %d\n",
-		controller, p_status->err_code, p_status->oper_state);
-
-	/* Make sure the bus is not stalled before exit. */
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-		i2c_stall_bus(controller, 0);
-
-	/* Abort data, wait for STOP condition completed. */
-	i2c_abort_data(controller);
-
-	/* Reset i2c controller by re-enable i2c controller*/
-	if (!i2c_reset(controller))
-		return;
-
-	/* Restore to idle status */
-	p_status->oper_state = SMB_IDLE;
-}
-
-/*
- * This function can be called in either single-byte mode or FIFO mode.
- * In single-byte mode - it always write 1 byte to SMBSDA register at one time.
- * In FIFO mode - write as many as available bytes in FIFO at one time.
- */
-static void i2c_fifo_write_data(int controller)
-{
-	int len, fifo_avail, i;
-
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	len = 1;
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-		len = p_status->sz_txbuf - p_status->idx_buf;
-		fifo_avail = I2C_TX_FIFO_AVAILABLE(controller);
-		len = MIN(len, fifo_avail);
-	}
-	for (i = 0; i < len; i++) {
-		I2C_WRITE_BYTE(controller,
-				p_status->tx_buf[p_status->idx_buf++]);
-		CPRINTF("%02x ",
-				p_status->tx_buf[p_status->idx_buf - 1]);
-	}
-	CPRINTF("\n");
-}
-
-enum smb_error i2c_controller_transaction(int controller)
-{
-	/* Set i2c mode to object */
-	int events = 0;
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/* Switch to bank 1 to access I2C FIO registers */
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-		i2c_select_bank(controller, 1);
-
-	/* Assign current SMB status of controller */
-	if (p_status->oper_state == SMB_IDLE) {
-		/* New transaction */
-		p_status->oper_state = SMB_CONTROLLER_START;
-		/* Clear FIFO and status bit */
-		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-			NPCX_SMBFIF_CTS(controller) =
-				BIT(NPCX_SMBFIF_CTS_RXF_TXE) |
-				BIT(NPCX_SMBFIF_CTS_CLR_FIFO);
-		}
-	} else if (p_status->oper_state == SMB_WRITE_SUSPEND) {
-		if (p_status->sz_txbuf == 0) {
-			/* Read bytes from next transaction */
-			p_status->oper_state = SMB_REPEAT_START;
-			CPUTS("R");
-		} else {
-			/* Continue to write the other bytes */
-			p_status->oper_state = SMB_WRITE_OPER;
-			CPRINTS("-W");
-			/*
-			 * This function can be called in either single-byte
-			 * mode or FIFO mode.
-			 */
-			i2c_fifo_write_data(controller);
-		}
-	} else if (p_status->oper_state == SMB_READ_SUSPEND) {
-		if (!IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-			/*
-			 * Do extra read if read length is 1 and I2C_XFER_STOP
-			 * is set simultaneously.
-			 */
-			if (p_status->sz_rxbuf == 1 &&
-					(p_status->flags & I2C_XFER_STOP)) {
-				/*
-				 * Since SCL is released after reading last
-				 * byte from previous transaction, adding a
-				 * extra byte for next transaction which let
-				 * ec sets NACK bit in time is necessary.
-				 * Or i2c controller cannot generate STOP
-				 * when the last byte is ACK during receiving.
-				 */
-				p_status->sz_rxbuf++;
-				p_status->oper_state = SMB_FAKE_READ_OPER;
-			} else
-				/*
-				 * Need to read the other bytes from
-				 * next transaction
-				 */
-				p_status->oper_state = SMB_READ_OPER;
-		}
-	} else
-		cprintf(CC_I2C, "Unexpected i2c state machine! %d\n",
-				p_status->oper_state);
-
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-		if (p_status->sz_rxbuf > 0) {
-			if (p_status->sz_rxbuf > NPCX_I2C_FIFO_MAX_SIZE) {
-				/* Set RX threshold = FIFO_MAX_SIZE */
-				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						NPCX_I2C_FIFO_MAX_SIZE);
-			} else {
-				/*
-				 * set RX threshold = remaining data bytes
-				 * (it should be <= FIFO_MAX_SIZE)
-				 */
-				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						p_status->sz_rxbuf);
-				/*
-				 * Set LAST bit generate the NACK at the
-				 * last byte of the data group in FIFO
-				 */
-				if (p_status->flags & I2C_XFER_STOP) {
-					SET_BIT(NPCX_SMBRXF_CTL(controller),
-							NPCX_SMBRXF_CTL_LAST);
-				}
-			}
-
-			/* Free the stalled SCL signal */
-			if (p_status->oper_state == SMB_READ_SUSPEND) {
-				p_status->oper_state = SMB_READ_OPER;
-				i2c_stall_bus(controller, 0);
-			}
-		}
-	}
-
-	/* Generate a START condition */
-	if (p_status->oper_state == SMB_CONTROLLER_START ||
-			p_status->oper_state == SMB_REPEAT_START) {
-		I2C_START(controller);
-		CPUTS("ST");
-	}
-
-	/* Enable event and error interrupts */
-	task_enable_irq(i2c_irqs[controller]);
-
-	/* Wait for transfer complete or timeout */
-	events = task_wait_event_mask(TASK_EVENT_I2C_IDLE,
-			p_status->timeout_us);
-
-	/* Disable event and error interrupts */
-	task_disable_irq(i2c_irqs[controller]);
-
-	/*
-	 * Accessing FIFO register is only needed during transaction.
-	 * Switch back to bank 0 at the end of transaction
-	 */
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-		i2c_select_bank(controller, 0);
-
-	/*
-	 * If Stall-After-Start mode is still enabled since NACK or BUS error
-	 * occurs, disable it.
-	 */
-	if (IS_BIT_SET(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_STASTRE))
-		CLEAR_BIT(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_STASTRE);
-
-	/* Handle bus timeout */
-	if ((events & TASK_EVENT_I2C_IDLE) == 0) {
-		p_status->err_code = SMB_TIMEOUT_ERROR;
-		/* Recovery I2C controller */
-		i2c_recovery(controller, p_status);
-	}
-	/* Recovery bus if we encounter bus error */
-	else if (p_status->err_code == SMB_BUS_ERROR)
-		i2c_recovery(controller, p_status);
-
-	/* Wait till STOP condition is generated for normal transaction */
-	if (p_status->err_code == SMB_OK && i2c_wait_stop_completed(controller,
-			I2C_MIN_TIMEOUT) != EC_SUCCESS) {
-		cprintf(CC_I2C,
-			"STOP fail! scl %02x is held by slave device!\n",
-			controller);
-		p_status->err_code = SMB_TIMEOUT_ERROR;
-	}
-
-	return p_status->err_code;
-}
-
-/* Issue stop condition if necessary and end transaction */
-void i2c_done(int controller)
-{
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/* need to STOP or not */
-	if (p_status->flags & I2C_XFER_STOP) {
-		/* Issue a STOP condition on the bus */
-		I2C_STOP(controller);
-		CPUTS("-SP");
-		/* Clear RXF_TXE bit (RX FIFO full/TX FIFO empty) */
-		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-			NPCX_SMBFIF_CTS(controller) =
-						BIT(NPCX_SMBFIF_CTS_RXF_TXE);
-
-		/* Clear SDAST by writing mock byte */
-		I2C_WRITE_BYTE(controller, 0xFF);
-	}
-
-	/* Set error code */
-	p_status->err_code = SMB_OK;
-	/* Set SMB status if we need stall bus */
-	p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_WRITE_SUSPEND;
-	/*
-	 * Disable interrupt for i2c controller stall SCL
-	 * and forbid SDAST generate interrupt
-	 * until common layer start other transactions
-	 */
-	if (p_status->oper_state == SMB_WRITE_SUSPEND)
-		task_disable_irq(i2c_irqs[controller]);
-
-	/* Notify upper layer */
-	task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-	CPUTS("-END");
-}
-
-static void i2c_handle_receive(int controller)
-{
-	uint8_t data;
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/* last byte is about to be read - end of transaction */
-	if (p_status->idx_buf == (p_status->sz_rxbuf - 1)) {
-		/* need to STOP or not */
-		if (p_status->flags & I2C_XFER_STOP) {
-			/* Stop should set before reading last byte */
-			I2C_STOP(controller);
-			CPUTS("-SP");
-		} else {
-			/*
-			 * Disable interrupt before i2c controller read SDA
-			 * reg (stall SCL) and forbid SDAST generate
-			 * interrupt until starting other transactions
-			 */
-			task_disable_irq(i2c_irqs[controller]);
-		}
-	}
-	/* Check if byte-before-last is about to be read */
-	else if (p_status->idx_buf == (p_status->sz_rxbuf - 2)) {
-		/*
-		 * Set nack before reading byte-before-last,
-		 * so that nack will be generated after receive
-		 * of last byte
-		 */
-		if (p_status->flags & I2C_XFER_STOP) {
-			I2C_NACK(controller);
-			CPUTS("-GNA");
-		}
-	}
-
-	/* Read data for SMBSDA */
-	I2C_READ_BYTE(controller, data);
-	CPRINTS("-R(%02x)", data);
-
-	/* Read to buf. Skip last byte if meet SMB_FAKE_READ_OPER */
-	if (p_status->oper_state == SMB_FAKE_READ_OPER &&
-			p_status->idx_buf == (p_status->sz_rxbuf - 1))
-		p_status->idx_buf++;
-	else
-		p_status->rx_buf[p_status->idx_buf++] = data;
-
-	/* last byte is read - end of transaction */
-	if (p_status->idx_buf == p_status->sz_rxbuf) {
-		/* Set current status */
-		p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_READ_SUSPEND;
-		/* Set error code */
-		p_status->err_code = SMB_OK;
-		/* Notify upper layer of missing data */
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-		CPUTS("-END");
-	}
-}
-
-static void i2c_fifo_read_data(int controller, uint8_t bytes_in_fifo)
-{
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	while (bytes_in_fifo--) {
-		uint8_t data;
-
-		data = NPCX_SMBSDA(controller);
-		p_status->rx_buf[p_status->idx_buf++] = data;
-		CPRINTF("%02x ", data);
-	}
-	CPRINTF("\n");
-}
-
-static void i2c_fifo_handle_receive(int controller)
-{
-	uint8_t bytes_in_fifo, remaining_bytes;
-
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/*
-	 * Clear RX_THST bit (RX-FIFO Threshold Status).
-	 * It is set when RX_BYTES = RX_THR after being RX_BYTES < RX_THR
-	 */
-	SET_BIT(NPCX_SMBRXF_STS(controller), NPCX_SMBRXF_STS_RX_THST);
-	SET_BIT(NPCX_SMBFIF_CTS(controller), NPCX_SMBFIF_CTS_RXF_TXE);
-
-	bytes_in_fifo = I2C_RX_FIFO_OCCUPIED(controller);
-	remaining_bytes = p_status->sz_rxbuf - p_status->idx_buf;
-	if (remaining_bytes - bytes_in_fifo <= 0) {
-		/*
-		 * Last byte is about to be read - end of transaction.
-		 * Stop should be set before reading last byte.
-		 */
-		if (p_status->flags & I2C_XFER_STOP) {
-			I2C_STOP(controller);
-			CPUTS("-FSP");
-		} else {
-			task_disable_irq(i2c_irqs[controller]);
-			/*
-			 * The I2C bus will be freed from stalled and continue
-			 * to recevie data when reading data from FIFO.
-			 * Pull SCL signal down to stall the bus manually.
-			 * SCL signal will be freed when it gets a new I2C
-			 * transaction call from common layer.
-			 */
-			i2c_stall_bus(controller, 1);
-		}
-
-		CPRINTS("-LFR");
-		i2c_fifo_read_data(controller, remaining_bytes);
-	} else {
-		CPRINTS("-FR");
-		/*
-		 * The I2C bus will be freed from stalled and continue to
-		 * recevie data when reading data from FIFO.
-		 * This may caue driver cannot set the new Rx threshold in time.
-		 * Manually stall SCL signal until the new Rx threshold is set.
-		 */
-		i2c_stall_bus(controller, 1);
-		i2c_fifo_read_data(controller, bytes_in_fifo);
-		remaining_bytes = p_status->sz_rxbuf - p_status->idx_buf;
-		if (remaining_bytes > 0) {
-			if (remaining_bytes > NPCX_I2C_FIFO_MAX_SIZE) {
-				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						NPCX_I2C_FIFO_MAX_SIZE);
-			} else {
-				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						remaining_bytes);
-				if (p_status->flags & I2C_XFER_STOP) {
-					SET_BIT(NPCX_SMBRXF_CTL(controller),
-							NPCX_SMBRXF_CTL_LAST);
-					CPRINTS("-FGNA");
-				}
-			}
-
-		}
-		i2c_stall_bus(controller, 0);
-
-	}
-	/* last byte is read - end of transaction */
-	if (p_status->idx_buf == p_status->sz_rxbuf) {
-		/* Set current status */
-		p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_READ_SUSPEND;
-		/* Set error code */
-		p_status->err_code = SMB_OK;
-		/* Notify upper layer of missing data */
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-		CPUTS("-END");
-	}
-
-}
-
-static void i2c_handle_sda_irq(int controller)
-{
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-	uint8_t addr_8bit = I2C_STRIP_FLAGS(p_status->addr_flags) << 1;
-
-	/* 1 Issue Start is successful ie. write address byte */
-	if (p_status->oper_state == SMB_CONTROLLER_START
-			|| p_status->oper_state == SMB_REPEAT_START) {
-		/* Prepare address byte */
-		if (p_status->sz_txbuf == 0) {/* Receive mode */
-			p_status->oper_state = SMB_READ_OPER;
-			/*
-			 * Receiving one or zero bytes - stall bus after
-			 * START condition. If there's no peripheral
-			 * devices on bus, FW needn't to set ACK bit.
-			 */
-			if (p_status->sz_rxbuf < 2)
-				I2C_STALL(controller);
-
-			/* Write the address to the bus R bit*/
-			I2C_WRITE_BYTE(controller, (addr_8bit | 0x1));
-			CPRINTS("-ARR-0x%02x", addr_8bit);
-		} else {/* Transmit mode */
-			p_status->oper_state = SMB_WRITE_OPER;
-			/* Write the address to the bus W bit*/
-			I2C_WRITE_BYTE(controller, addr_8bit);
-			CPRINTS("-ARW-0x%02x", addr_8bit);
-		}
-		/* Completed handling START condition */
-		return;
-	}
-	/* 2 Handle controller write operation */
-	else if (p_status->oper_state == SMB_WRITE_OPER) {
-		/* all bytes have been written, in a pure write operation */
-		if (p_status->idx_buf == p_status->sz_txbuf) {
-			/*  no more message */
-			if (p_status->sz_rxbuf == 0)
-				i2c_done(controller);
-			/*
-			 * need to restart & send peripheral address
-			 * immediately
-			 */
-			else {
-				/*
-				 * Prepare address byte
-				 * and start to receive bytes
-				 */
-				p_status->oper_state = SMB_READ_OPER;
-				/* Reset index of buffer */
-				p_status->idx_buf = 0;
-
-				/*
-				 * Generate (Repeated) Start
-				 * upon next write to SDA
-				 */
-				I2C_START(controller);
-				CPUTS("-RST");
-				/*
-				 * Receiving one byte only - set NACK just
-				 * before writing address byte.
-				 * Set NACK (ACK bit in the SMBnCTL1 register)
-				 * only in the single-byte mode.
-				 * In FIFO mode, NACK is set via LAST bit
-				 * in the SMBnTXF_CTL register.
-				 */
-				if (p_status->sz_rxbuf == 1 &&
-					(p_status->flags & I2C_XFER_STOP) &&
-					!IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-					I2C_NACK(controller);
-					CPUTS("-GNA");
-				}
-				/* Write the address to the bus R bit*/
-				I2C_WRITE_BYTE(controller,
-					       (addr_8bit | 0x1));
-				CPUTS("-ARR");
-			}
-		}
-		/*
-		 * write next byte (not last byte and not peripheral
-		 * address)
-		 */
-		else {
-			/*
-			 * This function can be called in either single-byte
-			 * mode or FIFO mode.
-			 */
-			CPRINTS("-W");
-			i2c_fifo_write_data(controller);
-		}
-	}
-	/*
-	 * 3 Handle controller read operation (read or after a write
-	 * operation)
-	 */
-	else if (p_status->oper_state == SMB_READ_OPER ||
-			p_status->oper_state == SMB_FAKE_READ_OPER) {
-		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-			i2c_fifo_handle_receive(controller);
-		else
-			i2c_handle_receive(controller);
-	}
-}
-
-static void i2c_controller_int_handler(int controller)
-{
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/* Condition 1 : A Bus Error has been identified */
-	if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_BER)) {
-		uint8_t __attribute__((unused)) data;
-		/* Generate a STOP condition */
-		I2C_STOP(controller);
-		CPUTS("-SP");
-		/* Clear BER Bit */
-		SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_BER);
-		/* Make sure peripheral doesn't hold bus by reading */
-		I2C_READ_BYTE(controller, data);
-
-		/* Set error code */
-		p_status->err_code = SMB_BUS_ERROR;
-		/* Notify upper layer */
-		p_status->oper_state = SMB_IDLE;
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-		CPUTS("-BER");
-
-		/*
-		 * Disable smb's interrupts to forbid ec to enter ISR again
-		 * before executing error recovery.
-		 */
-		task_disable_irq(i2c_irqs[controller]);
-
-		/* return for executing error recovery immediately */
-		return;
-	}
-
-	/* Condition 2: A negative acknowledge has occurred */
-	if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_NEGACK)) {
-		/* Generate a STOP condition */
-		I2C_STOP(controller);
-		CPUTS("-SP");
-		/* Clear NEGACK Bit */
-		SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK);
-		/* Set error code */
-		p_status->err_code = SMB_NO_ADDRESS_MATCH;
-		/* Notify upper layer */
-		p_status->oper_state = SMB_IDLE;
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-		CPUTS("-NA");
-	}
-
-	/* Condition 3: A Stall after START has occurred for READ-BYTE */
-	if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_STASTR)) {
-		CPUTS("-STL");
-
-		/* Disable Stall-After-Start mode first */
-		CLEAR_BIT(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_STASTRE);
-
-		/*
-		 * Generate stop condition and return success status since
-		 * ACK received on zero-byte transaction.
-		 */
-		if (p_status->sz_rxbuf == 0)
-			i2c_done(controller);
-		/*
-		 * Otherwise we have a one-byte transaction, so NACK after
-		 * receiving next byte, if requested.
-		 * Set NACK (ACK bit in the SMBnCTL1 register) only in the
-		 * single-byte mode.
-		 * In FIFO mode, NACK is set via LAST bit in the SMBnTXF_CTL
-		 * register.
-		 */
-		else if ((p_status->flags & I2C_XFER_STOP) &&
-				 !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-			I2C_NACK(controller);
-		}
-
-		/* Clear STASTR to release SCL after setting NACK/STOP bits */
-		SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_STASTR);
-	}
-
-	/* Condition 4: SDA status is set - transmit or receive */
-	if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_SDAST)) {
-		i2c_handle_sda_irq(controller);
-#if DEBUG_I2C
-		/* SDAST still issued with unexpected state machine */
-		if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_SDAST) &&
-				p_status->oper_state != SMB_WRITE_SUSPEND) {
-			cprints(CC_I2C, "i2c %d unknown state %d, error %d\n",
-			  controller, p_status->oper_state, p_status->err_code);
-		}
-#endif
-	}
-}
-
-/**
- * Handle an interrupt on the specified controller.
- *
- * @param controller   I2C controller generating interrupt
- */
-void handle_interrupt(int controller)
-{
-	i2c_controller_int_handler(controller);
-}
-
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-void i2c4_interrupt(void) { handle_interrupt(4); }
-void i2c5_interrupt(void) { handle_interrupt(5); }
-void i2c6_interrupt(void) { handle_interrupt(6); }
-void i2c7_interrupt(void) { handle_interrupt(7); }
-#endif
-
-DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB2, i2c1_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB3, i2c2_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB4, i2c3_interrupt, 4);
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-DECLARE_IRQ(NPCX_IRQ_SMB5, i2c4_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB6, i2c5_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB7, i2c6_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB8, i2c7_interrupt, 4);
-#endif
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	int ctrl = i2c_port_to_controller(port);
-
-	/* Return if i2c_port_to_controller() returned an error */
-	if (ctrl < 0)
-		return;
-
-	/* Param is port, but timeout is stored by-controller. */
-	i2c_stsobjs[ctrl].timeout_us =
-		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-int chip_i2c_xfer(const int port,
-		  const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	volatile struct i2c_status *p_status;
-	int ctrl = i2c_port_to_controller(port);
-
-	/* Return error if i2c_port_to_controller() returned an error */
-	if (ctrl < 0)
-		return EC_ERROR_INVAL;
-
-	/* Skip unnecessary transaction */
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	p_status = i2c_stsobjs + ctrl;
-
-	/* Assign current task ID */
-	p_status->task_waiting = task_get_current();
-
-	/* Select port for multi-ports i2c controller */
-	i2c_select_port(port);
-
-	/* Copy data to controller struct */
-	p_status->flags      = flags;
-	p_status->tx_buf     = out;
-	p_status->sz_txbuf   = out_size;
-	p_status->rx_buf     = in;
-	p_status->sz_rxbuf   = in_size;
-	p_status->addr_flags = addr_flags;
-
-	/* Reset index & error */
-	p_status->idx_buf     = 0;
-	p_status->err_code    = SMB_OK;
-
-	/* Make sure we're in a good state to start */
-	if ((flags & I2C_XFER_START) &&
-	     /* Ignore busy bus for repeated start */
-	     p_status->oper_state != SMB_WRITE_SUSPEND &&
-	     (i2c_bus_busy(ctrl)
-	     || (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
-		int ret;
-
-		/* Attempt to unwedge the i2c port */
-		ret = i2c_unwedge(port);
-		if (ret)
-			return ret;
-		p_status->err_code = SMB_BUS_BUSY;
-		/* recover i2c controller */
-		i2c_recovery(ctrl, p_status);
-		/* Select port again for recovery */
-		i2c_select_port(port);
-	}
-
-	CPUTS("\n");
-
-	/* Start controller transaction */
-	i2c_controller_transaction(ctrl);
-
-	/* Reset task ID */
-	p_status->task_waiting = TASK_ID_INVALID;
-
-	CPRINTS("-Err:0x%02x", p_status->err_code);
-
-	return (p_status->err_code == SMB_OK) ? EC_SUCCESS : EC_ERROR_UNKNOWN;
-}
-
-/**
- * Return raw I/O line levels (I2C_LINE_*) for a port when port is in alternate
- * function mode.
- *
- * @param port  Port to check
- * @return      State of SCL/SDA bit 0/1
- */
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		   (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	/*
-	 * Check do we support this port of i2c and return gpio number of scl.
-	 * Please notice we cannot read voltage level from GPIO in M4 EC
-	 */
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) {
-		if (i2c_is_raw_mode(port))
-			return gpio_get_level(g);
-		else
-			return IS_BIT_SET(NPCX_SMBCTL3(
-			i2c_port_to_controller(port)), NPCX_SMBCTL3_SCL_LVL);
-	}
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	/*
-	 * Check do we support this port of i2c and return gpio number of scl.
-	 * Please notice we cannot read voltage level from GPIO in M4 EC
-	 */
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) {
-		if (i2c_is_raw_mode(port))
-			return gpio_get_level(g);
-		else
-			return IS_BIT_SET(NPCX_SMBCTL3(
-			i2c_port_to_controller(port)), NPCX_SMBCTL3_SDA_LVL);
-	}
-
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle */
-	return 1;
-}
-
-/*****************************************************************************/
-
-static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps)
-{
-	int freq, j;
-	int scl_freq;
-	const struct i2c_timing *pTiming;
-	int i2c_timing_used;
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	/*
-	 * SMB0/1/4/5/6/7 use APB3 clock
-	 * SMB2/3 use APB2 clock
-	 */
-	freq = (ctrl < 2 || ctrl > 3) ?
-		clock_get_apb3_freq() : clock_get_apb2_freq();
-#else /* CHIP_FAMILY_NPCX5 */
-	/*
-	 * SMB0/1 use core clock
-	 * SMB2/3 use APB2 clock
-	 */
-	freq = (ctrl < 2) ? clock_get_freq() : clock_get_apb2_freq();
-#endif
-
-	if (bus_freq_kbps == i2c_stsobjs[ctrl].kbps)
-		return;
-
-	/*
-	 * Set SCL frequency by formula:
-	 * tSCL = 4 * SCLFRQ * tCLK
-	 * fSCL = fCLK / (4*SCLFRQ)
-	 * SCLFRQ = ceil(fCLK/(4*fSCL))
-	 */
-	scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps*4000); /* Unit in bps */
-
-	/* Normal mode if I2C freq is under 100kHz */
-	if (bus_freq_kbps <= 100) {
-		i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
-		/* Set divider value of SCL */
-		SET_FIELD(NPCX_SMBCTL2(ctrl), NPCX_SMBCTL2_SCLFRQ7_FIELD,
-			  (scl_freq & 0x7F));
-		SET_FIELD(NPCX_SMBCTL3(ctrl), NPCX_SMBCTL3_SCLFRQ2_FIELD,
-			  (scl_freq >> 7));
-		return;
-	}
-
-	/* use Fast Mode */
-	SET_BIT(NPCX_SMBCTL3(ctrl), NPCX_SMBCTL3_400K);
-	/*
-	 * Set SCLH(L)T and hold-time directly for best I2C
-	 * timing condition for all source clocks. Please refer
-	 * Section 7.5.9 "SMBus Timing - Fast Mode" for detail.
-	 */
-	if (bus_freq_kbps == 400) {
-		pTiming = i2c_400k_timings;
-		i2c_timing_used = i2c_400k_timing_used;
-	} else if (bus_freq_kbps == 1000) {
-		pTiming = i2c_1m_timings;
-		i2c_timing_used = i2c_1m_timing_used;
-	} else {
-		i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
-		/* Set value from formula */
-		NPCX_SMBSCLLT(ctrl) = scl_freq;
-		NPCX_SMBSCLHT(ctrl) = scl_freq;
-		cprints(CC_I2C,
-			"Warning: I2C %d: Use 400kHz or 1MHz for better timing",
-			ctrl);
-		return;
-	}
-
-	for (j = 0; j < i2c_timing_used; j++, pTiming++) {
-		if (pTiming->clock == (freq/SECOND)) {
-			i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
-			/* Set SCLH(L)T and hold-time */
-			NPCX_SMBSCLLT(ctrl) = pTiming->k1/2;
-			NPCX_SMBSCLHT(ctrl) = pTiming->k2/2;
-			SET_FIELD(NPCX_SMBCTL4(ctrl),
-				  NPCX_SMBCTL4_HLDT_FIELD, pTiming->HLDT);
-			break;
-		}
-	}
-	if (j == i2c_timing_used)
-		cprints(CC_I2C, "Error: I2C %d: src clk %d not supported",
-			ctrl, freq / SECOND);
-}
-
-/* Hooks */
-
-static void i2c_freq_changed(void)
-{
-	int i;
-
-	for (i = 0; i < I2C_CONTROLLER_COUNT; ++i) {
-		/* No bus speed configured */
-		i2c_stsobjs[i].kbps = 0;
-	}
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		const struct i2c_port_t *p;
-		int ctrl;
-
-		p = &i2c_ports[i];
-		ctrl = i2c_port_to_controller(p->port);
-		if (ctrl < 0)
-			continue;
-		i2c_port_set_freq(ctrl, p->kbps);
-	}
-}
-
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT);
-
-enum i2c_freq chip_i2c_get_freq(int chip_i2c_port)
-{
-	int ctrl;
-	int kbps;
-
-	ctrl = i2c_port_to_controller(chip_i2c_port);
-	if (ctrl < 0)
-		return I2C_FREQ_COUNT;
-
-	kbps = i2c_stsobjs[ctrl].kbps;
-
-	if (kbps > 400)
-		return I2C_FREQ_1000KHZ;
-	if (kbps > 100)
-		return I2C_FREQ_400KHZ;
-
-	if (kbps == 100)
-		return I2C_FREQ_100KHZ;
-
-	return I2C_FREQ_COUNT;
-}
-
-int chip_i2c_set_freq(int chip_i2c_port, enum i2c_freq freq)
-{
-	int ctrl;
-	int bus_freq_kbps;
-
-	ctrl = i2c_port_to_controller(chip_i2c_port);
-	if (ctrl < 0)
-		return EC_ERROR_INVAL;
-
-	switch (freq) {
-	case I2C_FREQ_100KHZ:
-		bus_freq_kbps = 100;
-		break;
-	case I2C_FREQ_400KHZ:
-		bus_freq_kbps = 400;
-		break;
-	case I2C_FREQ_1000KHZ:
-		bus_freq_kbps = 1000;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	i2c_port_set_freq(ctrl, bus_freq_kbps);
-	return EC_SUCCESS;
-}
-
-void i2c_init(void)
-{
-	int i;
-
-	/* Configure pins from GPIOs to I2Cs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Enable clock for I2C peripheral */
-	clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	clock_enable_peripheral(CGC_OFFSET_I2C2, CGC_I2C_MASK2,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-#endif
-
-	/* Set I2C freq */
-	i2c_freq_changed();
-	/*
-	 * initialize smb status and register
-	 */
-	for (i = 0; i < i2c_ports_used; i++) {
-		volatile struct i2c_status *p_status;
-		int port = i2c_ports[i].port;
-		int ctrl = i2c_port_to_controller(port);
-
-		/* ignore the port if i2c_port_to_controller() failed */
-		if (ctrl < 0)
-			continue;
-
-		p_status = i2c_stsobjs + ctrl;
-
-		/* status init */
-		p_status->oper_state = SMB_IDLE;
-
-		/* Reset task ID */
-		p_status->task_waiting = TASK_ID_INVALID;
-
-		/* Use default timeout. */
-		i2c_set_timeout(port, 0);
-
-		/* Init the SMB module */
-		i2c_init_bus(ctrl);
-	}
-}
diff --git a/chip/npcx/i2c_chip.h b/chip/npcx/i2c_chip.h
deleted file mode 100644
index 014e6cddf2..0000000000
--- a/chip/npcx/i2c_chip.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific I2C module for Chrome EC */
-
-#ifndef __CROS_EC_I2C_CHIP_H
-#define __CROS_EC_I2C_CHIP_H
-
-/**
- * Select specific i2c port connected to i2c controller.
- *
- * @parm port I2C port
- */
-void i2c_select_port(int port);
-
-/*
- * Due to we couldn't support GPIO reading when IO is selected I2C, we need
- * to distingulish which mode we used currently.
- *
- * @parm port I2C port
- *
- * @return 0: i2c ports are selected to pins. 1: GPIOs are selected to pins.
- */
-int i2c_is_raw_mode(int port);
-
-#endif /* __CROS_EC_I2C_CHIP_H */
diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c
deleted file mode 100644
index e6b8cad7bd..0000000000
--- a/chip/npcx/keyboard_raw.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions needed by keyboard scanner module for Chrome EC */
-
-#include "common.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "clock.h"
-#include "gpio.h"
-#include "registers.h"
-#include "task.h"
-
-/**
- * Initialize the raw keyboard interface.
- */
-void keyboard_raw_init(void)
-{
-	/* Enable clock for KBS peripheral */
-	clock_enable_peripheral(CGC_OFFSET_KBS, CGC_KBS_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Ensure top-level interrupt is disabled */
-	keyboard_raw_enable_interrupt(0);
-
-	/*
-	 * Select quasi-bidirectional buffers for KSO pins. It reduces the
-	 * low-to-high transition time. This feature only supports in npcx7.
-	 */
-#ifdef CONFIG_KEYBOARD_KSO_HIGH_DRIVE
-	SET_FIELD(NPCX_KBSCTL, NPCX_KBHDRV_FIELD, 0x01);
-#endif
-
-	/* pull-up KBSIN 0-7 internally */
-	NPCX_KBSINPU = 0xFF;
-
-	/* Disable automatic scan mode */
-	CLEAR_BIT(NPCX_KBSCTL, NPCX_KBSMODE);
-
-	/* Disable automatic interrupt enable */
-	CLEAR_BIT(NPCX_KBSCTL, NPCX_KBSIEN);
-
-	/* Disable increment enable */
-	CLEAR_BIT(NPCX_KBSCTL, NPCX_KBSINC);
-
-	/* Set KBSOUT to zero to detect key-press */
-	NPCX_KBSOUT0 = 0x00;
-	NPCX_KBSOUT1 = 0x00;
-
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
-
-	/*
-	 * Enable interrupts for the inputs.  The top-level interrupt is still
-	 * masked off, so this won't trigger interrupts yet.
-	 */
-
-	/* Clear pending input sources used by scanner */
-	NPCX_WKPCL(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
-
-	/* Enable Wake-up Button */
-	NPCX_WKEN(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
-
-	/* Select high to low transition (falling edge) */
-	NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) =  0xFF;
-
-	/* Enable interrupt of WK KBS */
-	keyboard_raw_enable_interrupt(1);
-}
-
-/**
- * Finish initialization after task scheduling has started.
- */
-void keyboard_raw_task_start(void)
-{
-	/* Enable MIWU to trigger KBS interrupt */
-	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
-}
-
-/**
- * Drive the specified column low.
- */
-test_mockable void keyboard_raw_drive_column(int col)
-{
-	/*
-	 * Nuvoton Keyboard Scan IP supports 18x8 Matrix
-	 * It also support automatic scan functionality
-	 */
-	uint32_t mask, col_out;
-
-	/* Add support for CONFIG_KEYBOARD_KSO_BASE shifting */
-	col_out = col + CONFIG_KEYBOARD_KSO_BASE;
-
-	/* Drive all lines to high */
-	if (col == KEYBOARD_COLUMN_NONE) {
-		mask = ~0;
-#if defined(CONFIG_KEYBOARD_CUSTOMIZATION)
-		board_keyboard_drive_col(col);
-#elif defined(CONFIG_KEYBOARD_COL2_INVERTED)
-		gpio_set_level(GPIO_KBD_KSO2, 0);
-#endif
-	}
-	/* Set KBSOUT to zero to detect key-press */
-	else if (col == KEYBOARD_COLUMN_ALL) {
-		mask = ~(BIT(keyboard_cols) - 1);
-#if defined(CONFIG_KEYBOARD_CUSTOMIZATION)
-		board_keyboard_drive_col(col);
-#elif defined(CONFIG_KEYBOARD_COL2_INVERTED)
-		gpio_set_level(GPIO_KBD_KSO2, 1);
-#endif
-	}
-	/* Drive one line for detection */
-	else {
-#if defined(CONFIG_KEYBOARD_CUSTOMIZATION)
-		board_keyboard_drive_col(col);
-#elif defined(CONFIG_KEYBOARD_COL2_INVERTED)
-		if (col == 2)
-			gpio_set_level(GPIO_KBD_KSO2, 1);
-		else
-			gpio_set_level(GPIO_KBD_KSO2, 0);
-#endif
-		mask = ~BIT(col_out);
-	}
-
-	/* Set KBSOUT */
-	NPCX_KBSOUT0 = (mask & 0xFFFF);
-	NPCX_KBSOUT1 = ((mask >> 16) & 0x03);
-}
-
-/**
- * Read raw row state.
- * Bits are 1 if signal is present, 0 if not present.
- */
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Bits are active-low, so invert returned levels */
-	return (~NPCX_KBSIN) & KB_ROW_MASK;
-}
-
-/**
- * Enable or disable keyboard interrupts.
- */
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable)
-		task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
-	else
-		task_disable_irq(NPCX_IRQ_KSI_WKINTC_1);
-}
-
-/*
- * Interrupt handler for the entire GPIO bank of keyboard rows.
- */
-void keyboard_raw_interrupt(void)
-{
-	/* Clear pending input sources used by scanner */
-	NPCX_WKPCL(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
-
-	/* Wake the scan task */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, keyboard_raw_interrupt, 5);
-
-int keyboard_raw_is_input_low(int port, int id)
-{
-	return (NPCX_PDIN(port) & BIT(id)) == 0;
-}
-
diff --git a/chip/npcx/lct.c b/chip/npcx/lct.c
deleted file mode 100644
index e23fa3bf6a..0000000000
--- a/chip/npcx/lct.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LCT (Long Countdown Timer) module for Chrome EC */
-#include "lct_chip.h"
-#include "console.h"
-#include "hooks.h"
-#include "registers.h"
-#include "rtc.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define LCT_CLK_ENABLE_DELAY_USEC    150
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-void npcx_lct_sel_power_src(enum NPCX_LCT_PWR_SRC pwr_src)
-{
-	if (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_EN)) {
-		CPRINTS("Don't set power source when LCT is enabled");
-		return;
-	}
-
-	if (pwr_src == NPCX_LCT_PWR_SRC_VSBY)
-		SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_VSBY_PWR);
-	else
-		CLEAR_BIT(NPCX_LCTCONT, NPCX_LCTCONT_VSBY_PWR);
-}
-
-void npcx_lct_enable_clk(uint8_t enable)
-{
-	if (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_EN)) {
-		CPRINTS("Don't set/unset clock when LCT is enabled");
-		return;
-	}
-
-	if (enable) {
-		SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_CLK_EN);
-		/*
-		 * This bit must be set to 1 at least tLCTCKEN (150 us)
-		 * before the LCT is enabled.
-		 */
-		udelay(LCT_CLK_ENABLE_DELAY_USEC);
-	} else {
-		CLEAR_BIT(NPCX_LCTCONT, NPCX_LCTCONT_CLK_EN);
-	}
-}
-
-void npcx_lct_enable(uint8_t enable)
-{
-	enable = !!enable;
-	SET_FIELD(NPCX_LCTCONT, NPCX_LCTCONT_EN_FIELD, enable);
-	/* Wait until the bit value equals to what is set */
-	while (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_EN) != enable)
-		;
-}
-
-void npcx_lct_config(int seconds, int psl_ena, int int_ena)
-{
-	if (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_EN)) {
-		CPRINTS("Don't config LCT when LCT is enabled");
-		return;
-	}
-
-	/* LCT can count max to (16 weeks - 1 second) */
-	if (seconds > NPCX_LCT_MAX) {
-		CPRINTS("LCT time is out of range");
-		return;
-	}
-
-	/* Clear pending LCT event first */
-	NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST);
-
-	NPCX_LCTWEEK = seconds / SECS_PER_WEEK;
-	seconds %= SECS_PER_WEEK;
-	NPCX_LCTDAY = seconds / SECS_PER_DAY;
-	seconds %= SECS_PER_DAY;
-	NPCX_LCTHOUR = seconds / SECS_PER_HOUR;
-	seconds %= SECS_PER_HOUR;
-	NPCX_LCTMINUTE = seconds / SECS_PER_MINUTE;
-	NPCX_LCTSECOND = seconds % SECS_PER_MINUTE;
-
-	if (psl_ena) {
-		if (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_VSBY_PWR))
-			SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_PSL_EN);
-		else
-			CPRINTS("LCT must source VSBY to support PSL wakeup");
-	}
-
-	if (int_ena)
-		SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_EVEN);
-
-}
-
-uint32_t npcx_lct_get_time(void)
-{
-	uint32_t second;
-	uint8_t week, day, hour, minute;
-
-	do {
-		week   = NPCX_LCTWEEK;
-		day    = NPCX_LCTDAY;
-		hour   = NPCX_LCTHOUR;
-		minute = NPCX_LCTMINUTE;
-		second = NPCX_LCTSECOND;
-	} while (week   != NPCX_LCTWEEK   ||
-		 day    != NPCX_LCTDAY    ||
-		 hour   != NPCX_LCTHOUR   ||
-		 minute != NPCX_LCTMINUTE ||
-		 second != NPCX_LCTSECOND);
-
-	second += minute * SECS_PER_MINUTE +
-		  hour * SECS_PER_HOUR +
-		  day * SECS_PER_DAY +
-		  week * SECS_PER_WEEK;
-
-	return second;
-}
-
-void npcx_lct_clear_event(void)
-{
-	NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST);
-}
-
-int npcx_lct_is_event_set(void)
-{
-	return IS_BIT_SET(NPCX_LCTSTAT, NPCX_LCTSTAT_EVST);
-}
-
-static void npcx_lct_init(void)
-{
-	/* Disable LCT */
-	npcx_lct_enable(0);
-	/* Clear control and status registers */
-	NPCX_LCTCONT = 0x0;
-	npcx_lct_clear_event();
-	/* Clear all timer registers */
-	NPCX_LCTSECOND = 0x0;
-	NPCX_LCTMINUTE = 0x0;
-	NPCX_LCTHOUR = 0x0;
-	NPCX_LCTDAY = 0x0;
-	NPCX_LCTWEEK = 0x0;
-}
-DECLARE_HOOK(HOOK_INIT, npcx_lct_init, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CMD_RTC_ALARM
-static int command_lctalarm(int argc, char **argv)
-{
-	char *e;
-	int seconds;
-
-	seconds = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	npcx_lct_enable(0);
-	npcx_lct_sel_power_src(NPCX_LCT_PWR_SRC_VSBY);
-	npcx_lct_enable_clk(1);
-	/* Enable LCT event interrupt and MIWU */
-	npcx_lct_config(seconds, 0, 1);
-	task_disable_irq(NPCX_IRQ_LCT_WKINTF_2);
-	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP)  |= LCT_WUI_MASK;
-	NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP)   |= LCT_WUI_MASK;
-	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
-	npcx_lct_enable(1);
-
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(lctalarm, command_lctalarm, "", "");
-#endif
diff --git a/chip/npcx/lct_chip.h b/chip/npcx/lct_chip.h
deleted file mode 100644
index 197c189f43..0000000000
--- a/chip/npcx/lct_chip.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_LCT_CHIP_H
-#define __CROS_EC_LCT_CHIP_H
-#include "registers.h"
-#include "rtc.h"
-
-#define NPCX_LCT_MAX (16 * SECS_PER_WEEK - 1)
-
-enum NPCX_LCT_PWR_SRC {
-	NPCX_LCT_PWR_SRC_VCC1,
-	NPCX_LCT_PWR_SRC_VSBY
-};
-
-void npcx_lct_config(int seconds, int psl_ena, int int_ena);
-void npcx_lct_enable(uint8_t enable);
-void npcx_lct_enable_clk(uint8_t enable);
-void npcx_lct_sel_power_src(enum NPCX_LCT_PWR_SRC pwr_src);
-void npcx_lct_clear_event(void);
-int npcx_lct_is_event_set(void);
-
-/* return the current time of LCT in second */
-uint32_t npcx_lct_get_time(void);
-
-#endif  /* __CROS_EC_LCT_CHIP_H */
diff --git a/chip/npcx/lfw/ec_lfw.h b/chip/npcx/lfw/ec_lfw.h
deleted file mode 100644
index 88c0a9ed83..0000000000
--- a/chip/npcx/lfw/ec_lfw.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX5M5G SoC little FW used by booter
- */
-
-#ifndef __CROS_EC_EC_LFW_H
-#define __CROS_EC_EC_LFW_H
-
-/* Begin address for the .iram section; defined in linker script */
-extern unsigned int __iram_fw_start;
-/* End address for the .iram section; defined in linker script */
-extern unsigned int __iram_fw_end;
-/* Begin address for the iram codes; defined in linker script */
-extern unsigned int __flash_fw_start;
-
-#endif /* __CROS_EC_EC_LFW_H */
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
deleted file mode 100644
index adf78b642d..0000000000
--- a/chip/npcx/lpc.c
+++ /dev/null
@@ -1,991 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for Chrome EC */
-
-#include "acpi.h"
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i8042_protocol.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "lpc_chip.h"
-#include "port80.h"
-#include "registers.h"
-#include "system.h"
-#include "sib_chip.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-#include "system_chip.h"
-
-/* Console output macros */
-#if !(DEBUG_LPC)
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#endif
-
-/* PM channel definitions */
-#define PMC_ACPI     PM_CHAN_1
-#define PMC_HOST_CMD PM_CHAN_2
-
-#define PORT80_MAX_BUF_SIZE    16
-static uint16_t port80_buf[PORT80_MAX_BUF_SIZE];
-
-static struct	host_packet lpc_packet;
-static struct	host_cmd_handler_args host_cmd_args;
-static uint8_t	host_cmd_flags;         /* Flags from host command */
-static uint8_t	shm_mem_host_cmd[256] __aligned(8);
-static uint8_t	shm_memmap[256] __aligned(8);
-/* Params must be 32-bit aligned */
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static struct ec_lpc_host_args * const lpc_host_args =
-		(struct ec_lpc_host_args *)shm_mem_host_cmd;
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-static void keyboard_irq_assert(void)
-{
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	udelay(4);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-#else
-	/*
-	 * SERIRQ is automatically sent by KBC
-	 */
-#endif
-}
-
-static void lpc_task_enable_irq(void)
-{
-#ifdef HAS_TASK_KEYPROTO
-	task_enable_irq(NPCX_IRQ_KBC_IBF);
-#endif
-	task_enable_irq(NPCX_IRQ_PM_CHAN_IBF);
-	task_enable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
-	task_enable_irq(NPCX_IRQ_ESPI);
-	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
-	task_enable_irq(NPCX_IRQ_WKINTA_2);
-	/* Virtual Wire: HOST_RST_WARN, SUS_WARN, SUS_PWRDN_ACK, SLP_A */
-	task_enable_irq(NPCX_IRQ_WKINTB_2);
-	/* Enable eSPI module interrupts and wake-up functionalities */
-	NPCX_ESPIIE |= (ESPIIE_GENERIC | ESPIIE_VW);
-	NPCX_ESPIWE |= (ESPIWE_GENERIC | ESPIWE_VW);
-#endif
-}
-
-static void lpc_task_disable_irq(void)
-{
-#ifdef HAS_TASK_KEYPROTO
-	task_disable_irq(NPCX_IRQ_KBC_IBF);
-#endif
-	task_disable_irq(NPCX_IRQ_PM_CHAN_IBF);
-	task_disable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
-	task_disable_irq(NPCX_IRQ_ESPI);
-	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
-	task_disable_irq(NPCX_IRQ_WKINTA_2);
-	/* Virtual Wire: HOST_RST_WARN,SUS_WARN, SUS_PWRDN_ACK, SLP_A */
-	task_disable_irq(NPCX_IRQ_WKINTB_2);
-	/* Disable eSPI module interrupts and wake-up functionalities */
-	NPCX_ESPIIE &= ~(ESPIIE_GENERIC | ESPIIE_VW);
-	NPCX_ESPIWE &= ~(ESPIWE_GENERIC | ESPIWE_VW);
-#endif
-}
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-	host_event_t smi;
-
-#ifdef CONFIG_SCI_GPIO
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
-	/*
-	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
-	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
-	 * The reason is - if GPIOC6/CPIO76 are not selected as SMI/SCI, reading
-	 * from SMIB/SCIB doesn't really reflect the SMI/SCI status. SMI/SCI
-	 * status should be read from bit 1/0 in eSPI VMEVSM(2) register.
-	 */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(1);
-	udelay(65);
-	/* Generate a falling edge */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(0);
-	udelay(65);
-	/* Set signal high */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(1);
-#else
-	/* SET SMIB bit to pull SMI_L to high.*/
-	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-	udelay(65);
-	/* Generate a falling edge */
-	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-	udelay(65);
-	/* Set signal high */
-	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-#endif
-	smi = lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI);
-	if (smi)
-		HOST_EVENT_CPRINTS("smi", smi);
-}
-
-/**
- * Generate SCI pulse to the host chipset via LPC0SCI.
- */
-static void lpc_generate_sci(void)
-{
-	host_event_t sci;
-
-#ifdef CONFIG_SCI_GPIO
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
-	/*
-	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
-	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
-	 * The reason is - if GPIOC6/CPIO76 are not selected as SMI/SCI, reading
-	 * from SMIB/SCIB doesn't really reflect the SMI/SCI status. SMI/SCI
-	 * status should be read from bit 1/0 in eSPI VMEVSM(2) register.
-	 */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(1);
-	udelay(65);
-	/* Generate a falling edge */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(0);
-	udelay(65);
-	/* Set signal high */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(1);
-#else
-	/* Set SCIB bit to pull SCI_L to high.*/
-	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-	udelay(65);
-	/* Generate a falling edge */
-	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-	udelay(65);
-	/* Set signal high */
-	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-#endif
-
-	sci = lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI);
-	if (sci)
-		HOST_EVENT_CPRINTS("sci", sci);
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return (uint8_t *)shm_memmap;
-}
-
-static void lpc_send_response(struct host_cmd_handler_args *args)
-{
-	uint8_t *out;
-	int size = args->response_size;
-	int csum;
-	int i;
-
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (args->result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Handle negative size */
-	if (size < 0) {
-		args->result = EC_RES_INVALID_RESPONSE;
-		size = 0;
-	}
-
-	/* New-style response */
-	lpc_host_args->flags =
-			(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-			EC_HOST_ARGS_FLAG_TO_HOST;
-
-	lpc_host_args->data_size = size;
-
-	csum = args->command + lpc_host_args->flags +
-			lpc_host_args->command_version +
-			lpc_host_args->data_size;
-
-	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
-		csum += *out;
-
-	lpc_host_args->checksum = (uint8_t)csum;
-
-	/* Fail if response doesn't fit in the param buffer */
-	if (size > EC_PROTO2_MAX_PARAM_SIZE)
-		args->result = EC_RES_INVALID_RESPONSE;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	NPCX_HIPMDO(PMC_HOST_CMD) = args->result;
-	/* Clear processing flag */
-	CLEAR_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	NPCX_HIPMDO(PMC_HOST_CMD) = pkt->driver_result;
-	/* Clear processing flag */
-	CLEAR_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-}
-
-int lpc_keyboard_has_char(void)
-{
-	/* if OBF bit is '1', that mean still have a data in DBBOUT */
-	return (NPCX_HIKMST&0x01) ? 1 : 0;
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	/* if IBF bit is '1', that mean still have a data in DBBIN */
-	return (NPCX_HIKMST&0x02) ? 1 : 0;
-}
-
-/* Put a char to host buffer by HIKDO and send IRQ if specified. */
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	NPCX_HIKDO = chr;
-	CPRINTS("KB put %02x", chr);
-
-	/* Enable OBE interrupt to detect host read data out */
-	SET_BIT(NPCX_HICTRL, NPCX_HICTRL_OBECIE);
-	task_enable_irq(NPCX_IRQ_KBC_OBE);
-	if (send_irq) {
-		keyboard_irq_assert();
-	}
-}
-
-/* Put an aux char to host buffer by HIMDO and assert status bit 5. */
-void lpc_aux_put_char(uint8_t chr, int send_irq)
-{
-	if (send_irq)
-		SET_BIT(NPCX_HICTRL, NPCX_HICTRL_OBFMIE);
-	else
-		CLEAR_BIT(NPCX_HICTRL, NPCX_HICTRL_OBFMIE);
-
-	NPCX_HIKMST |= I8042_AUX_DATA;
-	NPCX_HIMDO = chr;
-	CPRINTS("AUX put %02x", chr);
-
-	/* Enable OBE interrupt to detect host read data out */
-	SET_BIT(NPCX_HICTRL, NPCX_HICTRL_OBECIE);
-	task_enable_irq(NPCX_IRQ_KBC_OBE);
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	/*
-	 * Only npcx5 series need this bypass. The bug of FW_OBF is fixed in
-	 * npcx7 series and later npcx ec.
-	 */
-#ifdef CHIP_FAMILY_NPCX5
-	/* Clear OBF flag in host STATUS and HIKMST regs */
-	if (IS_BIT_SET(NPCX_HIKMST, NPCX_HIKMST_OBF)) {
-		/*
-		 * Setting HICTRL.FW_OBF clears the HIKMST.OBF and STATUS.OBF
-		 * but it does not deassert IRQ1 when it was already asserted.
-		 * Emulate a host read to clear these two flags and also
-		 * deassert IRQ1
-		 */
-		sib_read_kbc_reg(0x0);
-	}
-#else
-	/* Make sure the previous TOH and IRQ has been sent out. */
-	udelay(4);
-	/* Clear OBE flag in host STATUS  and HIKMST regs*/
-	SET_BIT(NPCX_HICTRL, NPCX_HICTRL_FW_OBF);
-	/* Ensure there is no TOH set in this period. */
-	udelay(4);
-#endif
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via EC_SMI_L GPIO
- *   - SCI pulse via LPC0SCI
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	lpc_task_disable_irq();
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(NPCX_HIPMST(PMC_ACPI) & NPCX_HIPMST_ST2))
-			need_smi = 1;
-		SET_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_ST2);
-	} else
-		CLEAR_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_ST2);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		SET_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_ST1);
-	} else
-		CLEAR_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_ST1);
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	lpc_task_enable_irq();
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	NPCX_HIPMST(PMC_ACPI) |= mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	NPCX_HIPMST(PMC_ACPI) &= ~mask;
-}
-
-/* Enable LPC ACPI-EC interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	SET_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_IBFIE);
-}
-
-/* Disable LPC ACPI-EC interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	CLEAR_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_IBFIE);
-}
-
-/**
- * Handle write to ACPI I/O port
- *
- * @param is_cmd	Is write command (is_cmd=1) or data (is_cmd=0)
- */
-static void handle_acpi_write(int is_cmd)
-{
-	uint8_t value, result;
-
-	/* Set processing flag before reading command byte */
-	SET_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_F0);
-
-	/* Read command/data; this clears the FRMH status bit. */
-	value = NPCX_HIPMDI(PMC_ACPI);
-
-	/* Handle whatever this was. */
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		NPCX_HIPMDO(PMC_ACPI) = result;
-
-	/* Clear processing flag */
-	CLEAR_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_F0);
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
-	 * Full condition on the kernel channel.
-	 */
-	lpc_generate_sci();
-}
-
-/**
- * Handle write to host command I/O ports.
- *
- * @param is_cmd	Is write command (1) or data (0)?
- */
-static void handle_host_write(int is_cmd)
-{
-	/* Set processing flag before reading command byte */
-	SET_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = NPCX_HIPMDI(PMC_HOST_CMD);
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_args.send_response = lpc_send_response;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* See if we have an old or new style command */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)shm_mem_host_cmd;
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)shm_mem_host_cmd;
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-
-		host_packet_receive(&lpc_packet);
-		return;
-
-	} else {
-		/* Old style command, now unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-}
-
-/*****************************************************************************/
-/* Interrupt handlers */
-#ifdef HAS_TASK_KEYPROTO
-/* KB controller input buffer full ISR */
-void lpc_kbc_ibf_interrupt(void)
-{
-	uint8_t status;
-	uint8_t ibf;
-	/* If "command" input 0, else 1*/
-	if (lpc_keyboard_input_pending()) {
-		/*
-		 * Reading HIKMDI causes the IBF flag to deassert and allows
-		 * the host to write a new byte into the input buffer. So if we
-		 * don't capture the status before reading HIKMDI we will race
-		 * with the host and get an invalid value for HIKMST.A20.
-		 */
-		status = NPCX_HIKMST;
-		ibf = NPCX_HIKMDI;
-		keyboard_host_write(ibf, (status & 0x08) ? 1 : 0);
-		CPRINTS("ibf isr %02x", ibf);
-		task_wake(TASK_ID_KEYPROTO);
-	} else {
-		CPRINTS("ibf isr spurious");
-	}
-}
-DECLARE_IRQ(NPCX_IRQ_KBC_IBF, lpc_kbc_ibf_interrupt, 4);
-
-/* KB controller output buffer empty ISR */
-void lpc_kbc_obe_interrupt(void)
-{
-	/* Disable KBC OBE interrupt */
-	CLEAR_BIT(NPCX_HICTRL, NPCX_HICTRL_OBECIE);
-	task_disable_irq(NPCX_IRQ_KBC_OBE);
-
-	CPRINTS("obe isr %02x", NPCX_HIKMST);
-
-	NPCX_HIKMST &= ~I8042_AUX_DATA;
-
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(NPCX_IRQ_KBC_OBE, lpc_kbc_obe_interrupt, 4);
-#endif
-
-/* PM channel input buffer full ISR */
-void lpc_pmc_ibf_interrupt(void)
-{
-	/* Channel-1 for ACPI usage*/
-	/* Channel-2 for Host Command usage , so the argument data had been
-	 * put on the share memory firstly*/
-	if (NPCX_HIPMST(PMC_ACPI) & 0x02)
-		handle_acpi_write((NPCX_HIPMST(PMC_ACPI)&0x08) ? 1 : 0);
-	else if (NPCX_HIPMST(PMC_HOST_CMD) & 0x02)
-		handle_host_write((NPCX_HIPMST(PMC_HOST_CMD)&0x08) ? 1 : 0);
-}
-DECLARE_IRQ(NPCX_IRQ_PM_CHAN_IBF, lpc_pmc_ibf_interrupt, 4);
-
-/* PM channel output buffer empty ISR */
-void lpc_pmc_obe_interrupt(void)
-{
-}
-DECLARE_IRQ(NPCX_IRQ_PM_CHAN_OBE, lpc_pmc_obe_interrupt, 4);
-
-void lpc_port80_interrupt(void)
-{
-	uint8_t i;
-	uint8_t count = 0;
-	uint32_t code = 0;
-
-	/* buffer Port80 data to the local buffer if FIFO is not empty */
-	while (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FNE))
-		port80_buf[count++] = NPCX_DP80BUF;
-
-	for (i = 0; i < count; i++) {
-		uint8_t offset;
-		uint32_t buf_data;
-
-		buf_data = port80_buf[i];
-		offset = GET_FIELD(buf_data, NPCX_DP80BUF_OFFS_FIELD);
-		code |= (buf_data & 0xFF) << (8 * offset);
-
-		if (i == count - 1) {
-			port_80_write(code);
-			break;
-		}
-
-		/* peek the offset of the next byte */
-		buf_data = port80_buf[i + 1];
-		offset = GET_FIELD(buf_data, NPCX_DP80BUF_OFFS_FIELD);
-		/*
-		 * If the peeked next byte's offset is 0 means it is the start
-		 * of the new code. Pass the current code to Port80
-		 * common layer.
-		 */
-		if (offset == 0) {
-			port_80_write(code);
-			code = 0;
-		}
-	}
-
-	/* If FIFO is overflow */
-	if (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FOR)) {
-		SET_BIT(NPCX_DP80STS, NPCX_DP80STS_FOR);
-		CPRINTS("DP80 FIFO Overflow!");
-	}
-
-	/* Clear pending bit of host writing */
-	SET_BIT(NPCX_DP80STS, NPCX_DP80STS_FWR);
-}
-DECLARE_IRQ(NPCX_IRQ_PORT80, lpc_port80_interrupt, 4);
-
-/**
- * Preserve event masks across a sysjump.
- */
-static void lpc_sysjump(void)
-{
-	lpc_task_disable_irq();
-
-	/* Disable protect for Win 1 and 2. */
-	NPCX_WIN_WR_PROT(0) = 0;
-	NPCX_WIN_WR_PROT(1) = 0;
-	NPCX_WIN_RD_PROT(0) = 0;
-	NPCX_WIN_RD_PROT(1) = 0;
-
-	/* Reset base address for Win 1 and 2. */
-	NPCX_WIN_BASE(0) = 0xfffffff8;
-	NPCX_WIN_BASE(1) = 0xfffffff8;
-}
-DECLARE_HOOK(HOOK_SYSJUMP, lpc_sysjump, HOOK_PRIO_DEFAULT);
-
-/* For LPC host register initial via SIB module */
-void host_register_init(void)
-{
-	/* Enable Core-to-Host Modules Access */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
-
-	/* enable ACPI*/
-	sib_write_reg(SIO_OFFSET, 0x07, 0x11);
-	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-
-	/* Enable kbc and mouse */
-#ifdef HAS_TASK_KEYPROTO
-	/* LDN = 0x06 : keyboard */
-	sib_write_reg(SIO_OFFSET, 0x07, 0x06);
-	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-
-	/* LDN = 0x05 : mouse */
-	if (IS_ENABLED(CONFIG_PS2)) {
-		sib_write_reg(SIO_OFFSET, 0x07, 0x05);
-		sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-	}
-#endif
-
-	/* Setting PMC2 */
-	/* LDN register = 0x12(PMC2) */
-	sib_write_reg(SIO_OFFSET, 0x07, 0x12);
-	/* CMD port is 0x200 */
-	sib_write_reg(SIO_OFFSET, 0x60, 0x02);
-	sib_write_reg(SIO_OFFSET, 0x61, 0x00);
-	/* Data port is 0x204 */
-	sib_write_reg(SIO_OFFSET, 0x62, 0x02);
-	sib_write_reg(SIO_OFFSET, 0x63, 0x04);
-	/* enable PMC2 */
-	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-
-	/* Setting SHM */
-	/* LDN register = 0x0F(SHM) */
-	sib_write_reg(SIO_OFFSET, 0x07, 0x0F);
-	/* WIN1&2 mapping to IO */
-	sib_write_reg(SIO_OFFSET, 0xF1,
-			sib_read_reg(SIO_OFFSET, 0xF1) | 0x30);
-	/* WIN1 as Host Command on the IO:0x0800 */
-	sib_write_reg(SIO_OFFSET, 0xF5, 0x08);
-	sib_write_reg(SIO_OFFSET, 0xF4, 0x00);
-	/* WIN2 as MEMMAP on the IO:0x900 */
-	sib_write_reg(SIO_OFFSET, 0xF9, 0x09);
-	sib_write_reg(SIO_OFFSET, 0xF8, 0x00);
-
-	/*
-	 * eSPI allows sending 4 bytes of Port80 code in a single PUT_IOWR_SHORT
-	 * transaction. When setting OFS0_SEL~OFS3_SEL in DPAR1 register to 1,
-	 * EC hardware will put those 4 bytes of Port80 code to DP80BUF FIFO.
-	 * This is only supported when CHIP_FAMILY >= NPCX9.
-	 */
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI))
-		sib_write_reg(SIO_OFFSET, 0xFD, 0x0F);
-	/* enable SHM */
-	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-
-	CPRINTS("Host settings are done!");
-
-}
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-int lpc_get_pltrst_asserted(void)
-{
-	/* Read current PLTRST status */
-	return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT);
-}
-
-#ifndef CONFIG_HOSTCMD_ESPI
-/* Initialize host settings by interrupt */
-void lpc_lreset_pltrst_handler(void)
-{
-	int pltrst_asserted;
-
-	/* Clear pending bit of WUI */
-	SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7);
-
-	/* Ignore PLTRST# from SOC if it is not valid */
-	if (chipset_pltrst_is_valid && !chipset_pltrst_is_valid())
-		return;
-
-	pltrst_asserted = lpc_get_pltrst_asserted();
-
-	CPRINTS("LPC RESET# %sasserted", pltrst_asserted ? "" : "de");
-
-	/*
-	 * Once LRESET is de-asserted (low -> high), we need to initialize lpc
-	 * settings once. If RSTCTL_LRESET_PLTRST_MODE is active, LPC registers
-	 * won't be reset by Host domain reset but Core domain does.
-	 */
-	if (!pltrst_asserted)
-		host_register_init();
-	else {
-		/* Clear processing flag when LRESET is asserted */
-		CLEAR_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-		/* Notify HOOK_CHIPSET_RESET */
-		hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-	}
-}
-#endif
-
-/*****************************************************************************/
-/* LPC/eSPI Initialization functions */
-
-static void lpc_init(void)
-{
-	/* Enable clock for LPC peripheral */
-	clock_enable_peripheral(CGC_OFFSET_LPC, CGC_LPC_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	/*
-	 * In npcx5/7, the host interface type (HIF_TYP_SEL in the DEVCNT
-	 * register) is updated by booter after VCC1 Power-Up reset according to
-	 * VHIF voltage.
-	 * In npcx9, the booter will not do this anymore. The HIF_TYP_SEL
-	 * field should be set by firmware.
-	 */
-#ifdef CONFIG_HOSTCMD_ESPI
-	/* Initialize eSPI module */
-	NPCX_DEVCNT |= 0x08;
-	espi_init();
-#else
-	/* Switching to LPC interface */
-	NPCX_DEVCNT |= 0x04;
-#endif
-	/* Enable 4E/4F */
-	if (!IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_VHCFGA)) {
-		NPCX_HCBAL = 0x4E;
-		NPCX_HCBAH = 0x0;
-	}
-	/* Clear Host Access Hold state */
-	NPCX_SMC_CTL = 0xC0;
-
-#ifndef CONFIG_HOSTCMD_ESPI
-	/*
-	 * Set alternative pin from GPIO to CLKRUN no matter SERIRQ is under
-	 * continuous or quiet mode.
-	 */
-	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_CLKRN_SL);
-#endif
-
-	/*
-	 * Set pin-mux from GPIOs to SCL/SMI to make sure toggling SCIB/SMIB is
-	 * valid if CONFIG_SCI_GPIO isn't defined. eSPI sends SMI/SCI through VW
-	 * automatically by toggling them, too. It's unnecessary to set pin mux.
-	 */
-#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOSTCMD_ESPI)
-	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_EC_SCI_SL);
-	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_SMI_SL);
-#endif
-
-	/* Initialize Hardware for UART Host */
-#ifdef CONFIG_UART_HOST
-	/* Init COMx LPC UART */
-	/* FMCLK have to using 50MHz */
-	NPCX_DEVALT(0xB) = 0xFF;
-	/* Make sure Host Access unlock */
-	CLEAR_BIT(NPCX_LKSIOHA, 2);
-	/* Clear Host Access Lock Violation */
-	SET_BIT(NPCX_SIOLV, 2);
-#endif
-
-	/* Don't stall SHM transactions */
-	NPCX_SHM_CTL = NPCX_SHM_CTL & ~0x40;
-	/* Disable Protect Win1&2*/
-	NPCX_WIN_WR_PROT(0) = 0;
-	NPCX_WIN_WR_PROT(1) = 0;
-	NPCX_WIN_RD_PROT(0) = 0;
-	NPCX_WIN_RD_PROT(1) = 0;
-	/* Open Win1 256 byte for Host CMD, Win2 256 for MEMMAP*/
-	NPCX_WIN_SIZE = 0x88;
-	NPCX_WIN_BASE(0) = (uint32_t)shm_mem_host_cmd;
-	NPCX_WIN_BASE(1) = (uint32_t)shm_memmap;
-	/* Write protect of Share memory */
-	NPCX_WIN_WR_PROT(1) = 0xFF;
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-			EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-			EC_HOST_CMD_FLAG_VERSION_3;
-
-	/*
-	 * Clear processing flag before enabling lpc's interrupts in case
-	 * it's set by the other command during sysjump.
-	 */
-	CLEAR_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-
-	/* Turn on PMC2 for Host Command usage */
-	SET_BIT(NPCX_HIPMCTL(PMC_HOST_CMD), 0);
-
-	/*
-	 * Set required control value (avoid setting HOSTWAIT bit at this stage)
-	 */
-	NPCX_SMC_CTL = NPCX_SMC_CTL&~0x7F;
-	/* Clear status */
-	NPCX_SMC_STS = NPCX_SMC_STS;
-
-	/* Create mailbox */
-
-	/*
-	 * Init KBC
-	 * Clear OBF status flag,
-	 * IBF(K&M) INT enable,
-	 * OBF Mouse Full INT enable and OBF KB Full INT enable
-	 */
-#ifdef HAS_TASK_KEYPROTO
-	lpc_keyboard_clear_buffer();
-	NPCX_HICTRL = 0x0B;
-#endif
-
-	/*
-	 * Turn on enhance mode on PM channel-1,
-	 * enable IBF core interrupt
-	 */
-	NPCX_HIPMCTL(PMC_ACPI) |= 0x81;
-	/* Normally Polarity IRQ1,12 type (level + high) setting */
-	NPCX_HIIRQC = 0x00;
-
-	/*
-	 * Init PORT80
-	 * Enable Port80, Enable Port80 function & Interrupt & Read auto
-	 */
-#ifdef CONFIG_HOSTCMD_ESPI
-	NPCX_DP80CTL = 0x2b;
-#else
-	NPCX_DP80CTL = 0x29;
-#endif
-	SET_BIT(NPCX_GLUE_SDP_CTS, 3);
-#if SUPPORT_P80_SEG
-	SET_BIT(NPCX_GLUE_SDP_CTS, 0);
-#endif
-
-	/*
-	 * Use SMI/SCI postive polarity as default.
-	 * Negative polarity must be enabled in the case that SMI/SCI is
-	 * generated automatically by hardware. In current design,
-	 * SMI/SCI is conntrolled by FW. Use postive polarity is more
-	 * intuitive.
-	 */
-	CLEAR_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_SCIPOL);
-	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIPOL);
-	/* Set SMIB/SCIB to make sure SMI/SCI are high at init */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI)
-			| BIT(NPCX_HIPMIC_SMIB) | BIT(NPCX_HIPMIC_SCIB);
-#ifndef CONFIG_SCI_GPIO
-	/*
-	 * Allow SMI/SCI generated from PM module.
-	 * Either hardware autimatically generates,
-	 * or set SCIB/SMIB bit in HIPMIC register.
-	 */
-	SET_BIT(NPCX_HIPMIE(PMC_ACPI), NPCX_HIPMIE_SCIE);
-	SET_BIT(NPCX_HIPMIE(PMC_ACPI), NPCX_HIPMIE_SMIE);
-#endif
-	lpc_task_enable_irq();
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-
-	/*
-	 * TODO: For testing LPC with Chromebox, please make sure LPC_CLK is
-	 * generated before executing this function. EC needs LPC_CLK to access
-	 * LPC register through SIB module. For Chromebook platform, this
-	 * functionality should be done by BIOS or executed in hook function of
-	 * HOOK_CHIPSET_STARTUP
-	 */
-#ifdef BOARD_NPCX_EVB
-	/* initial IO port address via SIB-write modules */
-	host_register_init();
-#else
-#ifndef CONFIG_HOSTCMD_ESPI
-	/*
-	 * Initialize LRESET# interrupt only in case of LPC. For eSPI, there is
-	 * no dedicated GPIO pin for LRESET/PLTRST. PLTRST is indicated as a VW
-	 * signal instead. WUI57 of table 0 is set when EC receives
-	 * LRESET/PLTRST from either VW or GPIO. Since WUI57 of table 0 and
-	 * WUI15 of table 2 are issued at the same time in case of eSPI, there
-	 * is no need to indicate LRESET/PLTRST via two sources. Thus, do not
-	 * initialize LRESET# interrupt in case of eSPI.
-	 */
-	/* Set detection mode to edge */
-	CLEAR_BIT(NPCX_WKMOD(MIWU_TABLE_0, MIWU_GROUP_5), 7);
-	/* Handle interrupting on any edge */
-	SET_BIT(NPCX_WKAEDG(MIWU_TABLE_0, MIWU_GROUP_5), 7);
-	/* Enable wake-up input sources */
-	SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7);
-#endif
-#endif
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
-
-#if DEBUG_LPC
-static int command_lpc(int argc, char **argv)
-{
-	if (argc == 1)
-		return EC_ERROR_PARAM1;
-
-	if (!strcasecmp(argv[1], "sci"))
-		lpc_generate_sci();
-	else if (!strcasecmp(argv[1], "smi"))
-		lpc_generate_smi();
-	else if (!strcasecmp(argv[1], "wake"))
-		lpc_update_wake(-1);
-	else
-		return EC_ERROR_PARAM1;
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]", "Trigger SCI/SMI");
-
-#endif
diff --git a/chip/npcx/lpc_chip.h b/chip/npcx/lpc_chip.h
deleted file mode 100644
index 607fdde5fa..0000000000
--- a/chip/npcx/lpc_chip.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific hwtimer module for Chrome EC */
-
-#ifndef __CROS_EC_LPC_CHIP_H
-#define __CROS_EC_LPC_CHIP_H
-
-/* For host registers initialization via SIB module */
-void host_register_init(void);
-
-/* eSPI Initialization functions */
-void espi_init(void);
-/* eSPI reset assert/de-assert interrupt */
-void espi_espirst_handler(void);
-/* LPC PLTRST assert/de-assert interrupt */
-void lpc_lreset_pltrst_handler(void);
-#endif /* __CROS_EC_LPC_CHIP_H */
diff --git a/chip/npcx/peci.c b/chip/npcx/peci.c
deleted file mode 100644
index badfbd87d9..0000000000
--- a/chip/npcx/peci.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PECI interface for Chrome EC */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "peci.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "temp_sensor.h"
-#include "util.h"
-
-
-/* Initial PECI baud rate */
-#define PECI_BAUD_RATE        750000
-
-#define TEMP_AVG_LENGTH       4  /* Should be power of 2 */
-
-
-/* PECI Time-out */
-#define PECI_DONE_TIMEOUT_US  (10*MSEC)
-
-#define NULL_PENDING_TASK_ID  0xFFFFFFFF
-#define PECI_MAX_FIFO_SIZE    16
-#define PROC_SOCKET           0x30
-/* PECI Command Code */
-enum peci_command_t {
-	PECI_COMMAND_PING               = 0x00,
-	PECI_COMMAND_GET_DIB            = 0xF7,
-	PECI_COMMAND_GET_TEMP           = 0x01,
-	PECI_COMMAND_RD_PKG_CFG         = 0xA1,
-	PECI_COMMAND_WR_PKG_CFG         = 0xA5,
-	PECI_COMMAND_RD_IAMSR           = 0xB1,
-	PECI_COMMAND_RD_PCI_CFG         = 0x61,
-	PECI_COMMAND_RD_PCI_CFG_LOCAL   = 0xE1,
-	PECI_COMMAND_WR_PCI_CFG_LOCAL   = 0xE5,
-	PECI_COMMAND_NONE               = 0xFF
-};
-
-#define PECI_COMMAND_GET_TEMP_WR_LENS 0x00
-#define PECI_COMMAND_GET_TEMP_RD_LENS 0x02
-
-/* PECI Domain Number */
-static int temp_vals[TEMP_AVG_LENGTH];
-static int temp_idx;
-static uint8_t peci_sts;
-/* For PECI Done interrupt usage */
-static int peci_pending_task_id;
-
-/*****************************************************************************/
-/* Internal functions */
-
-/**
- * This routine initiates the parameters of a PECI transaction
- *
- * @param   wr_length How many byte of *wr_data went to be send
- * @param   rd_length How many byte went to received (not include FCS)
- * @param   cmd_code  Command code
- * @param   *wr_data  Buffer pointer of write data
- * @return  TASK_EVENT_PECI_DONE that mean slave had a response
- */
-static uint32_t peci_trans(
-		uint8_t             wr_length,
-		uint8_t             rd_length,
-		enum peci_command_t cmd_code,
-		uint8_t            *wr_data
-)
-{
-	uint32_t events;
-	/* Ensure no PECI transaction is in progress */
-	if (IS_BIT_SET(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_START_BUSY)) {
-		/*
-		 * PECI transaction is in progress -
-		 * can not initiate a new one
-		 */
-		return 0;
-	}
-	/* Set basic transaction parameters */
-	NPCX_PECI_ADDR = PROC_SOCKET;
-	NPCX_PECI_CMD = cmd_code;
-	/* Aviod over space */
-	if (rd_length > PECI_MAX_FIFO_SIZE)
-		rd_length = PECI_MAX_FIFO_SIZE;
-	/* Read-Length */
-	NPCX_PECI_RD_LENGTH = rd_length;
-	if (wr_length > PECI_MAX_FIFO_SIZE)
-		wr_length = PECI_MAX_FIFO_SIZE;
-	/* copy of data */
-	for (events = 0; events < wr_length; events++)
-		NPCX_PECI_DATA_OUT(events) = wr_data[events];
-	/* Write-Length */
-	if (cmd_code != PECI_COMMAND_PING) {
-		if ((cmd_code == PECI_COMMAND_WR_PKG_CFG) ||
-				(cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) {
-			/*CMD+AWFCS*/
-			NPCX_PECI_WR_LENGTH = wr_length + 2;
-			/* Enable AWFCS */
-			SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_AWFCS_EN);
-		} else {
-			/*CMD*/
-			NPCX_PECI_WR_LENGTH = wr_length + 1;
-			/* Enable AWFCS */
-			CLEAR_BIT(NPCX_PECI_CTL_STS,
-					NPCX_PECI_CTL_STS_AWFCS_EN);
-		}
-	}
-
-	/* Start the PECI transaction */
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_START_BUSY);
-
-	/* It should be using a interrupt , don't waste cpu computing power */
-	peci_pending_task_id = task_get_current();
-	return task_wait_event_mask(TASK_EVENT_PECI_DONE,
-					PECI_DONE_TIMEOUT_US);
-
-}
-
-/**
- * PECI transaction error status.
- *
- * @return  Bit3 - CRC error Bit4 - ABRT error
- */
-static uint8_t peci_check_error_state(void)
-{
-	return peci_sts;
-}
-
-/*****************************************************************************/
-/* PECI drivers */
-int peci_get_cpu_temp(void)
-{
-	uint32_t events;
-	int16_t cpu_temp = -1;
-
-	/* Start PECI trans */
-	events = peci_trans(PECI_COMMAND_GET_TEMP_WR_LENS,
-				PECI_COMMAND_GET_TEMP_RD_LENS,
-				PECI_COMMAND_GET_TEMP, NULL);
-	/* if return DONE , that mean slave had a PECI response */
-	if ((events & TASK_EVENT_PECI_DONE) == TASK_EVENT_PECI_DONE) {
-		/* check CRC & ABRT */
-		events = peci_check_error_state();
-		if (events) {
-			;
-		} else {
-			uint16_t *ptr;
-			ptr = (uint16_t *)&cpu_temp;
-			ptr[0] = (NPCX_PECI_DATA_IN(1) << 8) |
-				 (NPCX_PECI_DATA_IN(0) << 0);
-		}
-	}
-	return (int)cpu_temp;
-}
-
-int peci_temp_sensor_get_val(int idx, int *temp_ptr)
-{
-	int sum = 0;
-	int success_cnt = 0;
-	int i;
-
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return EC_ERROR_NOT_POWERED;
-
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i) {
-		if (temp_vals[i] >= 0) {
-			success_cnt++;
-			sum += temp_vals[i];
-		}
-	}
-
-	/*
-	 * Require at least two valid samples. When the AP transitions into S0,
-	 * it is possible, depending on the timing of the PECI sample, to read
-	 * an invalid temperature. This is very rare, but when it does happen
-	 * the temperature returned is CONFIG_PECI_TJMAX. Requiring two valid
-	 * samples here assures us that one bad maximum temperature reading
-	 * when entering S0 won't cause us to trigger an over temperature.
-	 */
-	if (success_cnt < 2)
-		return EC_ERROR_UNKNOWN;
-
-	*temp_ptr = sum / success_cnt;
-	return EC_SUCCESS;
-}
-
-static void peci_temp_sensor_poll(void)
-{
-	int val;
-
-	val = peci_get_cpu_temp();
-	if (val != -1) {
-		temp_vals[temp_idx] = val;
-		temp_idx = (temp_idx + 1) & (TEMP_AVG_LENGTH - 1);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, peci_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-static void peci_freq_changed(void)
-{
-	/* PECI's clock source is FMCLK */
-	int freq = clock_get_fm_freq();
-	int baud = 0xF;
-
-	/* Disable polling while reconfiguring */
-	NPCX_PECI_CTL_STS = 0;
-
-	/*
-	 * Set the maximum bit rate used by the PECI module during both
-	 * Address Timing Negotiation and Data Timing Negotiation.
-	 * The resulting maximum bit rate MAX_BIT_RATE in decimal is
-	 * according to the following formula:
-	 *
-	 * MAX_BIT_RATE [d] = (freq / (4 * baudrate)) - 1
-	 * Maximum bit rate should not extend the field's boundaries.
-	 */
-	if (freq != 0) {
-		baud = (uint8_t)(freq  / (4 * PECI_BAUD_RATE)) - 1;
-		/* Set maximum PECI baud rate (bit0 - bit4) */
-		if (baud > 0x1F)
-			baud = 0x1F;
-	}
-	/* Enhanced High-Speed */
-	if (baud >= 7) {
-		CLEAR_BIT(NPCX_PECI_RATE, 6);
-		CLEAR_BIT(NPCX_PECI_CFG, 3);
-	} else {
-		SET_BIT(NPCX_PECI_RATE, 6);
-		SET_BIT(NPCX_PECI_CFG, 3);
-	}
-	/* Setting Rate */
-	NPCX_PECI_RATE = baud;
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, peci_freq_changed, HOOK_PRIO_DEFAULT);
-
-static void peci_init(void)
-{
-	int i;
-
-	/* Enable clock for PECI peripheral */
-	clock_enable_peripheral(CGC_OFFSET_PECI, CGC_PECI_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	/* Set PECI freq */
-	peci_freq_changed();
-
-	/* make sure PECI_DATA function pin enable */
-	CLEAR_BIT(NPCX_DEVALT(0x0A), 6);
-	/* Set initial clock frequency */
-	peci_freq_changed();
-	/* Initialize temperature reading buffer to a valid value. */
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i)
-		temp_vals[i] = 300; /* 27 C */
-
-	/* init Pending task id */
-	peci_pending_task_id = NULL_PENDING_TASK_ID;
-	/* Enable PECI Done interrupt */
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_DONE_EN);
-
-	task_enable_irq(NPCX_IRQ_PECI);
-}
-DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT);
-
-/* If received a PECI DONE interrupt, post the event to PECI task */
-void peci_done_interrupt(void){
-	if (peci_pending_task_id != NULL_PENDING_TASK_ID)
-		task_set_event(peci_pending_task_id, TASK_EVENT_PECI_DONE);
-	peci_sts = NPCX_PECI_CTL_STS & 0x18;
-	/* no matter what, clear status bit again */
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_DONE);
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_CRC_ERR);
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_ABRT_ERR);
-}
-DECLARE_IRQ(NPCX_IRQ_PECI, peci_done_interrupt, 4);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_peci_temp(int argc, char **argv)
-{
-	int t = peci_get_cpu_temp();
-	if (t == -1) {
-		ccprintf("PECI response timeout\n");
-		return EC_ERROR_UNKNOWN;
-	}
-	ccprintf("CPU temp = %d K = %d\n", t, K_TO_C(t));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-		NULL,
-		"Print CPU temperature");
diff --git a/chip/npcx/ps2.c b/chip/npcx/ps2.c
deleted file mode 100644
index 7b8086cbcd..0000000000
--- a/chip/npcx/ps2.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PS/2 module for Chrome EC */
-#include "atomic.h"
-#include "clock.h"
-#include "console.h"
-#include "hooks.h"
-#include "gpio.h"
-#include "ps2_chip.h"
-#include "task.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_PS2, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_PS2, format, ## args)
-
-#if !(DEBUG_PS2)
-#define DEBUG_CPRINTS(...)
-#define DEBUG_CPRINTF(...)
-#else
-#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ## args)
-#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ## args)
-#endif
-
-/*
- * Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to
- * reset the shift mechanism.
- */
-#define PS2_SHIFT_MECH_RESET       0x47
-
-#define PS2_TRANSACTION_TIMEOUT    (20 * MSEC)
-#define PS2_BUSY_RETRY             10
-
-enum ps2_input_debounce_cycle {
-	PS2_IDB_1_CYCLE,
-	PS2_IDB_2_CYCLE,
-	PS2_IDB_4_CYCLE,
-	PS2_IDB_8_CYCLE,
-	PS2_IDB_16_CYCLE,
-	PS2_IDB_32_CYCLE,
-};
-
-enum ps2_opr_mode {
-	PS2_TX_MODE,
-	PS2_RX_MODE,
-};
-
-struct ps2_data {
-	/* PS/2 module operation mode */
-	uint8_t opr_mode;
-	/*
-	 * The callback function to process data received from PS/2 device.
-	 * Note: this is called in the PS/2 interrupt handler
-	 */
-	void (*rx_handler_cb)(uint8_t data);
-};
-static struct ps2_data ps2_ch_data[NPCX_PS2_CH_COUNT] = {
-	 [0 ... (NPCX_PS2_CH_COUNT - 1)] =  { PS2_RX_MODE, NULL }
-};
-
-/*
- * Bitmap to record the enabled PS/2 channel by upper layer.
- * Only bit[7 and bit[5:3] are used
- * (i.e. the bit position of CLK3-0 in the PS2_PSOSIG register)
- */
-static uint32_t channel_enabled_mask;
-static struct mutex ps2_lock;
-static volatile task_id_t task_waiting = TASK_ID_INVALID;
-
-static void ps2_init(void)
-{
-	/* Disable the power down bit of PS/2 */
-	clock_enable_peripheral(CGC_OFFSET_PS2, CGC_PS2_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Disable shift mechanism and configure PS/2 to received mode. */
-	NPCX_PS2_PSCON = 0x0;
-	/* Set WDAT3-0 and clear CLK3-0 before enabling shift mechanism */
-	NPCX_PS2_PSOSIG = PS2_SHIFT_MECH_RESET;
-
-	/*
-	 * PS/2 interrupt enable register
-	 * [0] - : SOTIE   = 1: Start Of Transaction Interrupt Enable
-	 * [1] - : EOTIE   = 1: End Of Transaction Interrupt Enable
-	 * [4] - : WUE     = 1: Wake-Up Enable
-	 * [7] - : CLK_SEL = 1: Select Free-Run clock as the basic clock
-	 */
-	NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) |
-				BIT(NPCX_PS2_PSIEN_EOTIE) |
-				BIT(NPCX_PS2_PSIEN_PS2_WUE) |
-				BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL);
-
-	/* Enable weak internal pull-up */
-	SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_WPUED);
-	/* Enable shift mechanism */
-	SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_EN);
-
-	/* Configure pins from GPIOs to PS/2 interface */
-	gpio_config_module(MODULE_PS2, 1);
-	task_enable_irq(NPCX_IRQ_PS2);
-}
-DECLARE_HOOK(HOOK_INIT, ps2_init, HOOK_PRIO_DEFAULT);
-
-void ps2_enable_channel(int channel, int enable,
-					void (*callback)(uint8_t data))
-{
-	if (channel >= NPCX_PS2_CH_COUNT) {
-		CPRINTS("Err:PS/2 CH exceed %d", NPCX_PS2_CH_COUNT);
-		return;
-	}
-
-	/*
-	 * Disable the interrupt during changing the enabled channel mask to
-	 * prevent from preemption
-	 */
-	interrupt_disable();
-	if (enable) {
-		ps2_ch_data[channel].rx_handler_cb = callback;
-		channel_enabled_mask |= BIT(NPCX_PS2_PSOSIG_CLK(channel));
-		/* Enable the relevant channel clock */
-		SET_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
-	} else {
-		channel_enabled_mask &=  ~BIT(NPCX_PS2_PSOSIG_CLK(channel));
-		/* Disable the relevant channel clock */
-		CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
-		ps2_ch_data[channel].rx_handler_cb = NULL;
-	}
-	interrupt_enable();
-}
-
-/* Check if the shift mechanism is busy */
-static int ps2_is_busy(void)
-{
-	/*
-	 * The driver pulls the CLK for non-active channels to low when Start
-	 * bit is detected and pull the CLK of the active channel low after
-	 * Stop bit detected. The EOT bit is set when Stop bit is detected,
-	 * but both SOT and EOT are cleared when all CLKs are pull low
-	 * (due to Shift Mechanism is reset)
-	 */
-	return (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) |
-		IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ? 1 : 0;
-}
-
-int ps2_transmit_byte(int channel, uint8_t data)
-{
-	int event;
-
-	uint8_t busy_retry = PS2_BUSY_RETRY;
-
-	if (channel >= NPCX_PS2_CH_COUNT) {
-		CPRINTS("Err:PS/2 CH exceed %d", NPCX_PS2_CH_COUNT);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!(BIT(NPCX_PS2_PSOSIG_CLK(channel)) & channel_enabled_mask)) {
-		CPRINTS("Err: PS/2 Tx w/o enabling CH");
-		return EC_ERROR_INVAL;
-	}
-
-	mutex_lock(&ps2_lock);
-	while (ps2_is_busy()) {
-		usleep(PS2_TRANSACTION_TIMEOUT);
-		if (busy_retry == 0) {
-			mutex_unlock(&ps2_lock);
-			return EC_ERROR_BUSY;
-		}
-		busy_retry--;
-	}
-
-	task_waiting = task_get_current();
-	ps2_ch_data[channel].opr_mode = PS2_TX_MODE;
-
-	/* Set PS/2 in transmit mode */
-	SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_XMT);
-	/* Enable Start Of Transaction interrupt */
-	SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE);
-
-	/* Reset the shift mechanism */
-	NPCX_PS2_PSOSIG = PS2_SHIFT_MECH_RESET;
-	/* Inhibit communication should last at least 100 micro-seconds */
-	udelay(100);
-
-	/* Write the data to be transmitted */
-	NPCX_PS2_PSDAT = data;
-	/* Apply the Request-to-send */
-	CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_WDAT(channel));
-	SET_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
-
-	/* Wait for interrupt */
-	event = task_wait_event_mask(TASK_EVENT_PS2_DONE,
-					PS2_TRANSACTION_TIMEOUT);
-	task_waiting = TASK_ID_INVALID;
-
-	if (event == TASK_EVENT_TIMER) {
-		task_disable_irq(NPCX_IRQ_PS2);
-		CPRINTS("PS/2 Tx timeout");
-		/* Reset the shift mechanism */
-		NPCX_PS2_PSOSIG = PS2_SHIFT_MECH_RESET;
-		/* Change the PS/2 module to receive mode */
-		CLEAR_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_XMT);
-		/* Restore the channel to Receive mode */
-		ps2_ch_data[channel].opr_mode = PS2_RX_MODE;
-		/*
-		 * Restore the enabled channel according to channel_enabled_mask
-		 */
-		NPCX_PS2_PSOSIG |= channel_enabled_mask;
-		task_enable_irq(NPCX_IRQ_PS2);
-	}
-	mutex_unlock(&ps2_lock);
-
-	DEBUG_CPRINTF("Evt:0x%08x\n", event);
-	return (event == TASK_EVENT_PS2_DONE) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-
-}
-
-static void ps2_stop_inactive_ch_clk(uint8_t active_ch)
-{
-	uint8_t mask;
-
-	mask = ~NPCX_PS2_PSOSIG_CLK_MASK_ALL |
-					BIT(NPCX_PS2_PSOSIG_CLK(active_ch));
-	NPCX_PS2_PSOSIG &= mask;
-
-}
-
-static int ps2_is_rx_error(uint8_t ch)
-{
-	uint8_t	status;
-
-	status = NPCX_PS2_PSTAT &
-				(BIT(NPCX_PS2_PSTAT_PERR) |
-				 BIT(NPCX_PS2_PSTAT_RFERR));
-	if (status) {
-
-		if (status & BIT(NPCX_PS2_PSTAT_PERR))
-			CPRINTF("PS2 CH %d RX parity error\n", ch);
-		if (status & BIT(NPCX_PS2_PSTAT_RFERR))
-			CPRINTF("PS2 CH %d RX Frame error\n", ch);
-		return 1;
-	} else
-		return 0;
-}
-
-void ps2_int_handler(void)
-{
-	uint8_t active_ch;
-
-	DEBUG_CPRINTS("PS2 INT");
-	/*
-	 * ACH = 1 : CHannel 0
-	 * ACH = 2 : CHannel 1
-	 * ACH = 4 : CHannel 2
-	 * ACH = 5 : CHannel 3
-	 */
-	active_ch = GET_FIELD(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_ACH);
-	active_ch = active_ch > 2 ? (active_ch - 2) : (active_ch - 1);
-	DEBUG_CPRINTF("ACH:%0d-", active_ch);
-
-	/*
-	 * Inhibit PS/2 transaction of the other non-active channels by
-	 * pulling down the clock signal
-	 */
-	ps2_stop_inactive_ch_clk(active_ch);
-
-	/* PS/2 Start of Transaction */
-	if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) &&
-			IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) {
-		DEBUG_CPRINTF("SOT-");
-		/*
-		 * Once set, SOT is not cleared until the shift mechanism
-		 * is reset. Therefore, SOTIE should be cleared on the
-		 * first occurrence of an SOT interrupt.
-		 */
-		CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE);
-	/* PS/2 End of Transaction */
-	} else if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) {
-		DEBUG_CPRINTF("EOT-");
-		CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE);
-
-		/*
-		 * Clear the CLK of active channel to reset
-		 * the shift mechanism
-		 */
-		CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(active_ch));
-
-		if (ps2_ch_data[active_ch].opr_mode == PS2_TX_MODE) {
-			/* Change the PS/2 module to receive mode */
-			CLEAR_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_XMT);
-			ps2_ch_data[active_ch].opr_mode = PS2_RX_MODE;
-			task_set_event(task_waiting, TASK_EVENT_PS2_DONE);
-		} else {
-			if (!ps2_is_rx_error(active_ch)) {
-				uint8_t data_read = NPCX_PS2_PSDAT;
-				struct ps2_data *ps2_ptr =
-							&ps2_ch_data[active_ch];
-
-				DEBUG_CPRINTF("Recv:0x%02x", data_read);
-				if (ps2_ptr->rx_handler_cb)
-					ps2_ptr->rx_handler_cb(data_read);
-			}
-		}
-
-		/* Restore the enabled channel */
-		NPCX_PS2_PSOSIG |= channel_enabled_mask;
-		/*
-		 * Re-enable the Start Of Transaction interrupt when
-		 * the shift mechanism is reset
-		 */
-		SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE);
-		SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE);
-	}
-	DEBUG_CPRINTF("\n");
-
-}
-DECLARE_IRQ(NPCX_IRQ_PS2, ps2_int_handler, 5);
-
-#ifdef CONFIG_CMD_PS2
-static int command_ps2ench(int argc, char **argv)
-{
-	uint8_t ch;
-	uint8_t enable;
-	char *e;
-
-	ch = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	enable = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	if (enable)
-		ps2_enable_channel(ch, 1, NULL);
-	else
-		ps2_enable_channel(ch, 0, NULL);
-
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench,
-			"ps2_ench channel 1|0",
-			"Enable/Disable PS/2 channel");
-
-static int command_ps2write(int argc, char **argv)
-{
-	uint8_t ch, data;
-	char *e;
-
-	ch = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	data = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	ps2_transmit_byte(ch, data);
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write,
-		"ps2_write channel data",
-		"Write data byte to PS/2 channel ");
-#endif
diff --git a/chip/npcx/ps2_chip.h b/chip/npcx/ps2_chip.h
deleted file mode 100644
index d88e6791ad..0000000000
--- a/chip/npcx/ps2_chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PS2_CHIP_H
-#define __CROS_EC_PS2_CHIP_H
-
-#include "common.h"
-
-enum npcx_ps2_channel {
-	NPCX_PS2_CH0,
-	NPCX_PS2_CH1,
-	NPCX_PS2_CH2,
-	NPCX_PS2_CH3,
-	NPCX_PS2_CH_COUNT
-};
-
-void ps2_enable_channel(int channel, int enable,
-			void (*callback)(uint8_t data));
-int ps2_transmit_byte(int channel, uint8_t data);
-
-#endif  /* __CROS_EC_PS2_CHIP_H */
diff --git a/chip/npcx/pwm.c b/chip/npcx/pwm.c
deleted file mode 100644
index b2016906b3..0000000000
--- a/chip/npcx/pwm.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for NPCX.
- *
- * On this chip, the PWM logic is implemented by the hardware FAN modules.
- */
-
-#include "assert.h"
-#include "clock.h"
-#include "clock_chip.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-
-#if !(DEBUG_PWM)
-#define CPRINTS(...)
-#else
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-#endif
-
-/* pwm resolution for each channel */
-static uint32_t pwm_res[PWM_CH_COUNT];
-
-/* PWM clock source */
-enum npcx_pwm_source_clock {
-	NPCX_PWM_CLOCK_APB2_LFCLK  = 0,
-	NPCX_PWM_CLOCK_FX          = 1,
-	NPCX_PWM_CLOCK_FR          = 2,
-	NPCX_PWM_CLOCK_RESERVED    = 3,
-	NPCX_PWM_CLOCK_UNDEF       = 0xFF
-};
-
-/* PWM heartbeat mode */
-enum npcx_pwm_heartbeat_mode {
-	NPCX_PWM_HBM_NORMAL    = 0,
-	NPCX_PWM_HBM_25        = 1,
-	NPCX_PWM_HBM_50        = 2,
-	NPCX_PWM_HBM_100       = 3,
-	NPCX_PWM_HBM_UNDEF     = 0xFF
-};
-
-/**
- * Set PWM operation clock.
- *
- * @param   ch      operation channel
- * @param   freq    desired PWM frequency
- * @notes   changed when initialization
- */
-static void pwm_set_freq(enum pwm_channel ch, uint32_t freq)
-{
-	int mdl = pwm_channels[ch].channel;
-	uint32_t clock;
-	uint32_t pre;
-
-	assert(freq != 0);
-
-	/* Disable PWM for module configuration */
-	pwm_enable(ch, 0);
-
-	/*
-	 * Get PWM clock frequency. Use internal 32K as PWM clock source if
-	 * the PWM must be active during low-power idle.
-	 */
-	if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-		clock = INT_32K_CLOCK;
-	else
-		clock = clock_get_apb2_freq();
-
-	/* Calculate prescaler */
-	pre = DIV_ROUND_UP(clock, (0xffff * freq));
-
-	/*
-	 * Calculate maximum resolution for the given freq. and prescaler. And
-	 * prevent it exceed the resolution of CTR/DCR registers.
-	 */
-	pwm_res[ch] = MIN((clock / pre) / freq, NPCX_PWM_MAX_RAW_DUTY);
-
-	/* Set PWM prescaler. */
-	NPCX_PRSC(mdl) = pre - 1;
-
-	/* Set PWM cycle time */
-	NPCX_CTR(mdl) = pwm_res[ch];
-
-	/* Set the duty cycle to 100% since DCR == CTR */
-	NPCX_DCR(mdl) = pwm_res[ch];
-}
-
-/**
- * Set PWM enabled.
- *
- * @param   ch      operation channel
- * @param   enabled enabled flag
- */
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	int mdl = pwm_channels[ch].channel;
-
-	/* Start or close PWM module */
-	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_PWR, enabled);
-}
-
-/**
- * Check PWM enabled.
- *
- * @param   ch  operation channel
- * @return  enabled or not
- */
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	int mdl = pwm_channels[ch].channel;
-	return IS_BIT_SET(NPCX_PWMCTL(mdl), NPCX_PWMCTL_PWR);
-}
-
-/**
- * Set PWM duty cycle.
- *
- * @param   ch      operation channel
- * @param   percent duty cycle percent
- */
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	/* Convert percent on [0, 100] to 16 bit duty */
-	pwm_set_raw_duty(ch, (percent * EC_PWM_MAX_DUTY) / 100);
-}
-
-/**
- * Set PWM duty cycle.
- *
- * @param   ch      operation channel
- * @param   duty    cycle duty
- */
-void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty)
-{
-	int mdl = pwm_channels[ch].channel;
-	uint32_t sd;
-
-	CPRINTS("pwm%d, set duty=%d", mdl, duty);
-
-	/* Assume the fan control is active high and invert it ourselves */
-	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP,
-			(pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW));
-
-	CPRINTS("initial freq=0x%x", pwm_channels[ch].freq);
-	CPRINTS("duty_cycle_cnt=%d", duty);
-
-	/* duty ranges from 0 - 0xffff, so scale down to 0 - pwm_res[ch] */
-	sd = DIV_ROUND_NEAREST(duty * pwm_res[ch], EC_PWM_MAX_DUTY);
-
-	/* Set the duty cycle. If it is zero, set DCR > CTR */
-	NPCX_DCR(mdl) = sd ? sd : NPCX_PWM_MAX_RAW_DUTY + 1;
-}
-
-/**
- * Get PWM duty cycle.
- *
- * @param   ch  operation channel
- * @return  duty cycle percent
- */
-int pwm_get_duty(enum pwm_channel ch)
-{
-	/* duty ranges from 0 - 0xffff, so scale to 0 - 100 */
-	return DIV_ROUND_NEAREST(pwm_get_raw_duty(ch) * 100, EC_PWM_MAX_DUTY);
-}
-
-/**
- * Get PWM duty cycle.
- *
- * @param   ch  operation channel
- * @return  duty cycle
- */
-uint16_t pwm_get_raw_duty(enum pwm_channel ch)
-{
-	int mdl = pwm_channels[ch].channel;
-
-	/* Return duty */
-	if (NPCX_DCR(mdl) > NPCX_CTR(mdl))
-		return 0;
-	else
-		/*
-		 * NPCX_DCR ranges from 0 - pwm_res[ch],
-		 * so scale to 0 - 0xffff
-		 */
-		return DIV_ROUND_NEAREST(NPCX_DCR(mdl) * EC_PWM_MAX_DUTY,
-						pwm_res[ch]);
-}
-
-/**
- * PWM configuration.
- *
- * @param  ch    operation channel
- */
-void pwm_config(enum pwm_channel ch)
-{
-	int mdl = pwm_channels[ch].channel;
-
-	/* Disable PWM for module configuration */
-	pwm_enable(ch, 0);
-
-	/* Set PWM heartbeat mode is no heartbeat */
-	SET_FIELD(NPCX_PWMCTL(mdl), NPCX_PWMCTL_HB_DC_CTL_FIELD,
-			NPCX_PWM_HBM_NORMAL);
-
-	/* Select default CLK or LFCLK clock input to PWM module */
-	SET_FIELD(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_FCK_SEL_FIELD,
-			NPCX_PWM_CLOCK_APB2_LFCLK);
-
-	/* Set PWM polarity normal first */
-	CLEAR_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP);
-
-	/* Select PWM clock source */
-	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_CKSEL,
-			(pwm_channels[ch].flags & PWM_CONFIG_DSLEEP));
-
-	/* Select PWM IO type */
-	UPDATE_BIT(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_OD_OUT,
-			(pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN));
-
-	/* Set PWM operation frequency */
-	pwm_set_freq(ch, pwm_channels[ch].freq);
-}
-
-/**
- * PWM initial.
- */
-static void pwm_init(void)
-{
-	int i;
-	uint8_t pd_mask = 0;
-
-	/* Take enabled PWMs out of power-down state */
-	for (i = 0; i < PWM_CH_COUNT; i++) {
-		pd_mask |= (1 << pwm_channels[i].channel);
-		pwm_res[i] = 0;
-	}
-
-	clock_enable_peripheral(CGC_OFFSET_PWM, pd_mask, CGC_MODE_ALL);
-
-	for (i = 0; i < PWM_CH_COUNT; i++)
-		pwm_config(i);
-}
-
-/* The chip-specific fan module initializes before this. */
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/npcx/pwm_chip.h b/chip/npcx/pwm_chip.h
deleted file mode 100644
index 7acfef81e5..0000000000
--- a/chip/npcx/pwm_chip.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific PWM module for Chrome EC */
-
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM channel ID */
-	int channel;
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-	/* PWM freq. */
-	uint32_t freq;
-};
-
-extern const struct pwm_t pwm_channels[];
-void pwm_config(enum pwm_channel ch);
-
-/* Npcx PWM maximum duty cycle value */
-#define NPCX_PWM_MAX_RAW_DUTY (UINT16_MAX - 1)
-
-#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/npcx/registers-npcx5.h b/chip/npcx/registers-npcx5.h
deleted file mode 100644
index c441c1c926..0000000000
--- a/chip/npcx/registers-npcx5.h
+++ /dev/null
@@ -1,388 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Specific register map for NPCX5 family of chips.
- *
- * Support chip variant:
- * - npcx5m5g
- * - npcx5m6g
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#define NPCX_IRQ5_NOUSED		NPCX_IRQ_5
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_MTC_WKINTAD_0		NPCX_IRQ_7
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTAD_0
-#define NPCX_IRQ8_NOUSED		NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTEFGH_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ16_NOUSED		NPCX_IRQ_16
-#define NPCX_IRQ_ITIM16_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ19_NOUSED		NPCX_IRQ_19
-#define NPCX_IRQ20_NOUSED		NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM16_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM16_1		NPCX_IRQ_28
-#define NPCX_IRQ29_NOUSED		NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ32_NOUSED		NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ35_NOUSED		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ38_NOUSED		NPCX_IRQ_38
-#define NPCX_IRQ39_NOUSED		NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ42_NOUSED		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM16_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM16_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM16_6		NPCX_IRQ_45
-#define NPCX_IRQ_ITIM32			NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_IRQ55_NOUSED		NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#define NPCX_IRQ58_NOUSED		NPCX_IRQ_58
-#define NPCX_IRQ_WKINTFG_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
-
-/* Modules Map */
-
-/* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL			REG8(NPCX_MDC_BASE_ADDR + 0x007)
-
-/* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION		0
-#define NPCX_FWCTRL_FW_SLOT		1
-
-#define NPCX_ITIM32_BASE_ADDR		0x400BC000
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400C4000 + ((mdl) * 0x2000L))
-#define NPCX_SMB_BASE_ADDR(mdl)	(((mdl) < 2) ? \
-				(0x40009000 + ((mdl) * 0x2000L)) : \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)))
-
-enum {
-	NPCX_UART_PORT0 = 0, /* UART port 0 */
-	NPCX_UART_COUNT
-};
-
-/* System Configuration (SCFG) Registers */
-
-/* SCFG enumeration */
-enum {
-	ALT_GROUP_0,
-	ALT_GROUP_1,
-	ALT_GROUP_2,
-	ALT_GROUP_3,
-	ALT_GROUP_4,
-	ALT_GROUP_5,
-	ALT_GROUP_6,
-	ALT_GROUP_7,
-	ALT_GROUP_8,
-	ALT_GROUP_9,
-	ALT_GROUP_A,
-	ALT_GROUP_B,
-	ALT_GROUP_C,
-	ALT_GROUP_D,
-	ALT_GROUP_E,
-	ALT_GROUP_F,
-	ALT_GROUP_COUNT
-};
-
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
-
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n))
-
-/* pin-mux for JTAG */
-#define NPCX_DEVALT5_NJEN1_EN		1
-#define NPCX_DEVALT5_NJEN0_EN		2
-
-/* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C0_1_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C3_0_SL		6
-
-/* pin-mux for UART */
-#define NPCX_DEVALTA_UART_SL1		7
-#define NPCX_DEVALTC_UART_SL2		0
-
-/* pin-mux for Misc. */
-/* External 32KHz crytal osc. input support */
-#define NPCX_DEVALTA_32KCLKIN_SL	3
-
-/* SMBus register fields */
-#define NPCX_SMBSEL_SMB0SEL		0
-
-/* SMB enumeration: I2C port definitions. */
-enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT0_1,	/* I2C port 0, bus 1 */
-	NPCX_I2C_PORT1,		/* I2C port 1 */
-	NPCX_I2C_PORT2,		/* I2C port 2 */
-	NPCX_I2C_PORT3,		/* I2C port 3 */
-	NPCX_I2C_COUNT,
-};
-
-/*
- * PMC enumeration:
- * Offsets from CGC_BASE registers for each peripheral.
- */
-enum {
-	CGC_OFFSET_KBS = 0,
-	CGC_OFFSET_UART = 0,
-	CGC_OFFSET_FAN = 0,
-	CGC_OFFSET_FIU = 0,
-	CGC_OFFSET_PS2 = 0,
-	CGC_OFFSET_PWM = 1,
-	CGC_OFFSET_I2C = 2,
-	CGC_OFFSET_ADC = 3,
-	CGC_OFFSET_PECI = 3,
-	CGC_OFFSET_SPI = 3,
-	CGC_OFFSET_TIMER = 3,
-	CGC_OFFSET_LPC = 4,
-	CGC_OFFSET_ESPI = 5,
-};
-
-enum NPCX_PMC_PWDWN_CTL_T {
-	NPCX_PMC_PWDWN_1 = 0,
-	NPCX_PMC_PWDWN_2 = 1,
-	NPCX_PMC_PWDWN_3 = 2,
-	NPCX_PMC_PWDWN_4 = 3,
-	NPCX_PMC_PWDWN_5 = 4,
-	NPCX_PMC_PWDWN_6 = 5,
-	NPCX_PMC_PWDWN_CNT,
-};
-
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD))
-
-/* BBRAM register fields */
-#define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR)
-#define NPCX_BBRAM_SIZE			64 /* Size of BBRAM */
-
-/* ITIM registers */
-#define NPCX_ITCNT8(n)			REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
-#define NPCX_ITCNT16(n)			REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
-/* ITIM32 registers */
-#define NPCX_ITCNT32			REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
-
-/* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32
-/* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT16
-
-/* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM16_1
-/* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO			ITIM16_5
-/* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32
-
-/* ITIM enumeration */
-enum ITIM_MODULE_T {
-	ITIM16_1,
-	ITIM16_2,
-	ITIM16_3,
-	ITIM16_4,
-	ITIM16_5,
-	ITIM16_6,
-	ITIM32,
-	ITIM_MODULE_COUNT,
-};
-
-/* Serial Host Interface (SHI) Registers */
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n))
-
-/* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_INTWK_EN			VWEVMS_INT_EN
-
-/* eSPI max supported frequency */
-enum {
-	NPCX_ESPI_MAXFREQ_20 = 0,
-	NPCX_ESPI_MAXFREQ_25 = 1,
-	NPCX_ESPI_MAXFREQ_33 = 2,
-	NPCX_ESPI_MAXFREQ_50 = 3,
-	NPCX_ESPI_MAXFREQ_66 = 4,
-	NPCX_ESPI_MAXFREQ_NONE = 0xFF
-};
-
-/* eSPI max frequency support per FMCLK */
-#if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
-#elif (FMCLK <= 48000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
-#else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_66
-#endif
-
-/* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x1E + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
-
-/* UART registers and functions */
-#if NPCX_UART_MODULE2
-/*
- * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
- * always 1 == MIWU_TABLE_1.
- */
-#define NPCX_UART_WK_GROUP		6
-#define NPCX_UART_WK_BIT		4
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#else /* !NPCX_UART_MODULE2 */
-
-#define NPCX_UART_WK_GROUP		1
-#define NPCX_UART_WK_BIT		0
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#endif /* NPCX_UART_MODULE2 */
-
-/* This routine checks pending bit of GPIO wake-up functionality */
-static inline int uart_is_wakeup_from_gpio(void)
-{
-	return IS_BIT_SET(NPCX_WKPND(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT);
-}
-
-/* This routine checks wake-up functionality from GPIO is enabled or not */
-static inline int uart_is_enable_wakeup(void)
-{
-	return IS_BIT_SET(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT);
-}
-
-/* This routine clears the pending wake-up from GPIO on UART rx pin */
-static inline void uart_clear_pending_wakeup(void)
-{
-	SET_BIT(NPCX_WKPCL(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT);
-}
-
-/* This routine enables wake-up functionality from GPIO on UART rx pin */
-static inline void uart_enable_wakeup(int enable)
-{
-	UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT,
-		enable);
-}
-
-/* This routine checks functionality is UART rx or not */
-static inline int npcx_is_uart(void)
-{
-	return IS_BIT_SET(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL);
-}
-
-/* ADC Registers */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
-/* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n)))
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_THR_DCTL(n)	REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n)))
-/* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
-
-/* ADC register fields */
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_THR_DCTL_THRD_EN		15
-#define NPCX_THR_DCTL_THR_DVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH_CNT		3
diff --git a/chip/npcx/registers-npcx7.h b/chip/npcx/registers-npcx7.h
deleted file mode 100644
index 535abfbf0f..0000000000
--- a/chip/npcx/registers-npcx7.h
+++ /dev/null
@@ -1,571 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Specific register map for NPCX7 family of chips.
- *
- * Support chip variant:
- * - npcx7m6g
- * - npcx7m6f
- * - npcx7m6fb
- * - npcx7m6fc
- * - npcx7m7fc
- * - npcx7m7wb
- * - npcx7m7wc
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#ifdef NPCX_WOV_SUPPORT
-#define NPCX_IRQ4_NOUSED		NPCX_IRQ_4
-#else
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#endif
-#define NPCX_IRQ5_NOUSED		NPCX_IRQ_5
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_MTC_WKINTAD_0		NPCX_IRQ_7
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTAD_0
-#define NPCX_IRQ_SMB8			NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTEFGH_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ_SMB7			NPCX_IRQ_16
-#define NPCX_IRQ_ITIM16_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ_SMB5			NPCX_IRQ_19
-#define NPCX_IRQ_SMB6			NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#ifdef NPCX_WOV_SUPPORT
-#define NPCX_IRQ_WOV			NPCX_IRQ_22
-#else
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#endif
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM16_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM16_1		NPCX_IRQ_28
-#define NPCX_IRQ29_NOUSED		NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ_UART2			NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ35_NOUSED		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ38_NOUSED		NPCX_IRQ_38
-#define NPCX_IRQ39_NOUSED		NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ42_NOUSED		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM16_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM16_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM16_6		NPCX_IRQ_45
-#define NPCX_IRQ_ITIM32			NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_IRQ55_NOUSED		NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#ifdef NPCX_ITIM64_SUPPORT
-#define NPCX_IRQ_ITIM64			NPCX_IRQ_58
-#else
-#define NPCX_IRQ58_NOUSED		NPCX_IRQ_58
-#endif
-#define NPCX_IRQ_WKINTFG_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
-
-/* Modules Map */
-
-/* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL			REG8(NPCX_MDC_BASE_ADDR + 0x007)
-
-/* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION		0
-#define NPCX_FWCTRL_FW_SLOT		1
-
-#define NPCX_ITIM32_BASE_ADDR		0x400BC000
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400C4000 + ((mdl) * 0x2000L))
-#define NPCX_SMB_BASE_ADDR(mdl)		(((mdl) < 2) ? \
-				(0x40009000 +	((mdl) * 0x2000L)) : \
-				((mdl) < 4) ? \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)) : \
-				((mdl) == 4) ? \
-				(0x40008000) : \
-				(0x40017000 + (((mdl) - 5) * 0x1000L)))
-
-#define NPCX_HFCBCD1			REG8(NPCX_HFCG_BASE_ADDR + 0x012)
-#define NPCX_HFCBCD2			REG8(NPCX_HFCG_BASE_ADDR + 0x014)
-
-enum {
-	NPCX_UART_PORT0 = 0, /* UART port 0 */
-#ifdef NPCX_SECOND_UART
-	NPCX_UART_PORT1 = 1, /* UART port 1 */
-#endif
-	NPCX_UART_COUNT
-};
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-/* UART registers only used for FIFO mode */
-#define NPCX_UFTSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
-#define NPCX_UFRSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
-#define NPCX_UFTCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
-#define NPCX_UFRCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
-
-/* UART FIFO register fields */
-#define NPCX_UMDSL_FIFO_MD		0
-
-#define NPCX_UFTSTS_TEMPTY_LVL		FIELD(0, 5)
-#define NPCX_UFTSTS_TEMPTY_LVL_STS	5
-#define NPCX_UFTSTS_TFIFO_EMPTY_STS	6
-#define NPCX_UFTSTS_NXMIP		7
-
-#define NPCX_UFRSTS_RFULL_LVL_STS	5
-#define NPCX_UFRSTS_RFIFO_NEMPTY_STS	6
-#define NPCX_UFRSTS_ERR			7
-
-#define NPCX_UFTCTL_TEMPTY_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFTCTL_TEMPTY_LVL_EN	5
-#define NPCX_UFTCTL_TEMPTY_EN		6
-#define NPCX_UFTCTL_NXMIPEN		7
-
-#define NPCX_UFRCTL_RFULL_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFRCTL_RFULL_LVL_EN	5
-#define NPCX_UFRCTL_RNEMPTY_EN		6
-#define NPCX_UFRCTL_ERR_EN		7
-#endif
-
-/* KBSCAN register fields */
-#define NPCX_KBHDRV_FIELD		FIELD(6, 2)
-
-/* GLUE registers */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_GLUE_PSL_CTS		REG8(NPCX_GLUE_REGS_BASE + 0x027)
-#endif
-
-/* GPIO registers */
-#define NPCX_PLOCK_CTL(n)		REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
-
-/* System Configuration (SCFG) Registers */
-
-/* SCFG enumeration */
-enum {
-	ALT_GROUP_0,
-	ALT_GROUP_1,
-	ALT_GROUP_2,
-	ALT_GROUP_3,
-	ALT_GROUP_4,
-	ALT_GROUP_5,
-	ALT_GROUP_6,
-	ALT_GROUP_7,
-	ALT_GROUP_8,
-	ALT_GROUP_9,
-	ALT_GROUP_A,
-	ALT_GROUP_B,
-	ALT_GROUP_C,
-	ALT_GROUP_D,
-	ALT_GROUP_E,
-	ALT_GROUP_F,
-	ALT_GROUP_COUNT
-};
-
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
-
-#define NPCX_LV_GPIO_CTL_ADDR(n)	(((n) < 5) ? \
-					(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\
-					(NPCX_SCFG_BASE_ADDR + 0x026))
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_LV_GPIO_CTL_ADDR(n))
-
-/* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C7_0_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C6_0_SL		3
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C5_0_SL		5
-#define NPCX_DEVALT2_I2C3_0_SL		6
-#define NPCX_DEVALT2_I2C4_0_SL		7
-#define NPCX_DEVALT6_I2C6_1_SL		5
-#define NPCX_DEVALT6_I2C5_1_SL		6
-#define NPCX_DEVALT6_I2C4_1_SL		7
-
-/* pin-mux for JTAG */
-#define NPCX_DEVALT5_NJEN1_EN		1
-#define NPCX_DEVALT5_NJEN0_EN		2
-
-/* pin-mux for ADC */
-#define NPCX_DEVALTF_ADC5_SL		0
-#define NPCX_DEVALTF_ADC6_SL		1
-#define NPCX_DEVALTF_ADC7_SL		2
-#define NPCX_DEVALTF_ADC8_SL		3
-#define NPCX_DEVALTF_ADC9_SL		4
-
-/* pin-mux for PSL */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_DEVALTD_PSL_IN1_AHI	0
-#define NPCX_DEVALTD_NPSL_IN1_SL	1
-#define NPCX_DEVALTD_PSL_IN2_AHI	2
-#define NPCX_DEVALTD_NPSL_IN2_SL	3
-#define NPCX_DEVALTD_PSL_IN3_AHI	4
-#define NPCX_DEVALTD_PSL_IN3_SL		5
-#define NPCX_DEVALTD_PSL_IN4_AHI	6
-#define NPCX_DEVALTD_PSL_IN4_SL		7
-#endif
-
-#ifdef CHIP_VARIANT_NPCX7M6G
-/* External 32KHz crytal osc. input support */
-#define NPCX_DEVALTA_32KCLKIN_SL	3
-#endif
-
-/* pin-mux for UART */
-#define NPCX_DEVALTA_UART_SL1		7
-#define NPCX_DEVALTC_UART_SL2		0
-#ifdef NPCX_SECOND_UART
-/* Secondary UART selection */
-#define NPCX_DEVALTA_UART2_SL		5
-#endif
-
-/* SHI module version 2 enable bit */
-#define NPCX_DEVALTF_SHI_NEW		7
-
-#ifdef NPCX_WOV_SUPPORT
-/* pin-mux for WoV */
-#define NPCX_DEVALTE_WOV_SL		0
-#define NPCX_DEVALTE_I2S_SL		1
-#define NPCX_DEVALTE_DMCLK_FAST		2
-#endif
-
-/* SMBus register fields */
-#define NPCX_SMBSEL_SMB4SEL		4
-#define NPCX_SMBSEL_SMB5SEL		5
-#define NPCX_SMBSEL_SMB6SEL		6
-
-/* SMB enumeration: I2C port definitions */
-enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT1_0,	/* I2C port 1, bus 0 */
-	NPCX_I2C_PORT2_0,	/* I2C port 2, bus 0 */
-	NPCX_I2C_PORT3_0,	/* I2C port 3, bus 0 */
-#ifdef CHIP_VARIANT_NPCX7M6G
-	NPCX_I2C_PORT4_0,	/* I2C port 4, bus 0 */
-#endif
-	NPCX_I2C_PORT4_1,	/* I2C port 4, bus 1 */
-	NPCX_I2C_PORT5_0,	/* I2C port 5, bus 0 */
-	NPCX_I2C_PORT5_1,	/* I2C port 5, bus 1 */
-	NPCX_I2C_PORT6_0,	/* I2C port 6, bus 0 */
-	NPCX_I2C_PORT6_1,	/* I2C port 6, bus 1 */
-	NPCX_I2C_PORT7_0,	/* I2C port 7, bus 0 */
-	NPCX_I2C_COUNT,
-};
-
-/* Power Management Controller (PMC) Registers */
-#define NPCX_FMUL_WIN_DLY	REG8(NPCX_PMC_BASE_ADDR + 0x010)
-#define NPCX_RAM_PD(offset)	REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
-
-/* PMC register fields */
-#define NPCX_PWDWN_CTL3_SMB4_PD		4
-#define NPCX_PWDWN_CTL7_SMB5_PD		0
-#define NPCX_PWDWN_CTL7_SMB6_PD		1
-#define NPCX_PWDWN_CTL7_SMB7_PD		2
-#ifdef NPCX_ITIM64_SUPPORT
-#define NPCX_PWDWN_CTL7_ITIM64_PD	5
-#endif
-#ifdef NPCX_SECOND_UART
-#define NPCX_PWDWN_CTL7_UART2_PD	6
-#endif
-#ifdef NPCX_WOV_SUPPORT
-#define NPCX_PWDWN_CTL7_WOV_PD		7
-#endif
-
-/*
- * PMC enumeration:
- * Offsets from CGC_BASE registers for each peripheral.
- */
-enum {
-	CGC_OFFSET_KBS = 0,
-	CGC_OFFSET_UART = 0,
-	CGC_OFFSET_FAN = 0,
-	CGC_OFFSET_FIU = 0,
-	CGC_OFFSET_PS2 = 0,
-	CGC_OFFSET_PWM = 1,
-	CGC_OFFSET_I2C = 2,
-	CGC_OFFSET_ADC = 3,
-	CGC_OFFSET_PECI = 3,
-	CGC_OFFSET_SPI = 3,
-	CGC_OFFSET_TIMER = 3,
-	CGC_OFFSET_LPC = 4,
-	CGC_OFFSET_ESPI = 5,
-	CGC_OFFSET_I2C2 = 6,
-#ifdef NPCX_SECOND_UART
-	CGC_OFFSET_UART2 = 6,
-#endif
-#ifdef NPCX_WOV_SUPPORT
-	CGC_OFFSET_WOV	= 6,
-#endif
-};
-
-enum NPCX_PMC_PWDWN_CTL_T {
-	NPCX_PMC_PWDWN_1 = 0,
-	NPCX_PMC_PWDWN_2 = 1,
-	NPCX_PMC_PWDWN_3 = 2,
-	NPCX_PMC_PWDWN_4 = 3,
-	NPCX_PMC_PWDWN_5 = 4,
-	NPCX_PMC_PWDWN_6 = 5,
-	NPCX_PMC_PWDWN_7 = 6,
-	NPCX_PMC_PWDWN_CNT,
-};
-
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB4_PD))
-#define CGC_I2C_MASK2			(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB7_PD))
-#ifdef NPCX_SECOND_UART
-#define CGC_UART2_MASK			BIT(NPCX_PWDWN_CTL7_UART2_PD)
-#endif
-#ifdef NPCX_WOV_SUPPORT
-#define CGC_WOV_MASK			BIT(NPCX_PWDWN_CTL7_WOV_PD)
-#endif
-
-/* BBRAM register fields */
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
-	defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_BKUP_STS_VSBY_STS		1
-#define NPCX_BKUP_STS_VCC1_STS		0
-#define NPCX_BKUP_STS_ALL_MASK \
-	(BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \
-	BIT(NPCX_BKUP_STS_VCC1_STS))
-#define NPCX_BBRAM_SIZE			128 /* Size of BBRAM */
-#else
-#define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR)
-#define NPCX_BBRAM_SIZE			64 /* Size of BBRAM */
-#endif
-
-/* ITIM16 registers */
-#define NPCX_ITCNT8(n)			REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
-#define NPCX_ITCNT16(n)			REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
-/* ITIM32 registers */
-#define NPCX_ITCNT32			REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
-
-/* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32
-/* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT16
-
-/* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM16_1
-/* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO			ITIM16_5
-/* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32
-
-/* ITIM enumeration */
-enum ITIM_MODULE_T {
-	ITIM16_1,
-	ITIM16_2,
-	ITIM16_3,
-	ITIM16_4,
-	ITIM16_5,
-	ITIM16_6,
-	ITIM32,
-	ITIM_MODULE_COUNT,
-};
-
-/* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */
-#define NPCX_SHICFG3			REG8(NPCX_SHI_BASE_ADDR + 0x00C)
-#define NPCX_SHICFG4			REG8(NPCX_SHI_BASE_ADDR + 0x00D)
-#define NPCX_SHICFG5			REG8(NPCX_SHI_BASE_ADDR + 0x00E)
-#define NPCX_EVSTAT2			REG8(NPCX_SHI_BASE_ADDR + 0x00F)
-#define NPCX_EVENABLE2			REG8(NPCX_SHI_BASE_ADDR + 0x010)
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
-
-/* SHI register fields */
-#define NPCX_SHICFG3_OBUFLVLDIS		7
-#define NPCX_SHICFG4_IBUFLVLDIS		7
-#define NPCX_SHICFG5_IBUFLVL2		FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS	7
-#define NPCX_EVSTAT2_IBHF2		0
-#define NPCX_EVSTAT2_CSNRE		1
-#define NPCX_EVSTAT2_CSNFE		2
-#define NPCX_EVENABLE2_IBHF2EN		0
-#define NPCX_EVENABLE2_CSNREEN		1
-#define NPCX_EVENABLE2_CSNFEEN		2
-
-/* eSPI register fields */
-#define NPCX_ESPIIE_BMTXDONEIE		19
-#define NPCX_ESPIIE_PBMRXIE		20
-#define NPCX_ESPIIE_PMSGRXIE		21
-#define NPCX_ESPIIE_BMBURSTERRIE	22
-#define NPCX_ESPIIE_BMBURSTDONEIE	23
-
-#define NPCX_ESPIWE_PBMRXWE		20
-#define NPCX_ESPIWE_PMSGRXWE		21
-
-#define NPCX_ESPISTS_VWUPDW		17
-#define NPCX_ESPISTS_BMTXDONE		19
-#define NPCX_ESPISTS_PBMRX		20
-#define NPCX_ESPISTS_PMSGRX		21
-#define NPCX_ESPISTS_BMBURSTERR		22
-#define NPCX_ESPISTS_BMBURSTDONE	23
-#define NPCX_ESPISTS_ESPIRST_LVL	24
-
-#define ESPIIE_BMTXDONE			BIT(NPCX_ESPIIE_BMTXDONEIE)
-#define ESPIIE_PBMRX			BIT(NPCX_ESPIIE_PBMRXIE)
-#define ESPIIE_PMSGRX			BIT(NPCX_ESPIIE_PMSGRXIE)
-#define ESPIIE_BMBURSTERR		BIT(NPCX_ESPIIE_BMBURSTERRIE)
-#define ESPIIE_BMBURSTDONE		BIT(NPCX_ESPIIE_BMBURSTDONEIE)
-
-#define ESPIWE_PBMRX			BIT(NPCX_ESPIWE_PBMRXWE)
-#define ESPIWE_PMSGRX			BIT(NPCX_ESPIWE_PMSGRXWE)
-
-/* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_WK_EN(e)			(((e)<<20) & 0x00100000)
-#define VWEVMS_INTWK_EN(e)		(VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
-
-/* eSPI max supported frequency */
-enum {
-	NPCX_ESPI_MAXFREQ_20 = 0,
-	NPCX_ESPI_MAXFREQ_25 = 1,
-	NPCX_ESPI_MAXFREQ_33 = 2,
-	NPCX_ESPI_MAXFREQ_50 = 3,
-	NPCX_ESPI_MAXFREQ_NONE = 0xFF
-};
-
-/* eSPI max frequency support per FMCLK */
-#if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
-#else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
-#endif
-
-/* UART registers */
-#define NPCX_UART_WK_GROUP		MIWU_GROUP_8
-#define NPCX_UART_WK_BIT		7
-#ifdef NPCX_SECOND_UART
-#define NPCX_UART2_WK_GROUP		MIWU_GROUP_1
-#define NPCX_UART2_WK_BIT		6
-#endif
-
-/* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x1E + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
-
-/* UART registers and functions */
-#if NPCX_UART_MODULE2
-/*
- * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
- * always 1 == MIWU_TABLE_1.
- */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#else /* !NPCX_UART_MODULE2 */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#endif /* NPCX_UART_MODULE2 */
-
-/* ADC Registers */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
-/* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n)))
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_THR_DCTL(n)	REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n)))
-/* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
-
-/* ADC register fields */
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_THR_DCTL_THRD_EN		15
-#define NPCX_THR_DCTL_THR_DVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH_CNT		3
diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h
deleted file mode 100644
index 1d2a02084c..0000000000
--- a/chip/npcx/registers-npcx9.h
+++ /dev/null
@@ -1,583 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Specific register map for NPCX9 family of chips.
- *
- * Support chip variant:
- * - npcx993f
- * - npcx996f
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#define NPCX_IRQ_MTC_WKINTD_0		NPCX_IRQ_5
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTD_0
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_CR_SIN2_WKINTA_0	NPCX_IRQ_7
-#define NPCX_IRQ_SMB8			NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTE_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ_SMB7			NPCX_IRQ_16
-#define NPCX_IRQ_ITIM32_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ_SMB5			NPCX_IRQ_19
-#define NPCX_IRQ_SMB6			NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM32_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM32_1		NPCX_IRQ_28
-#define NPCX_I3C_MDMA5			NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ_UART2			NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ_WKINTF_0		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ_UART3			NPCX_IRQ_38
-#define NPCX_IRQ_UART4			NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ_WKINTG_0		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM32_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM32_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM32_6		NPCX_IRQ_45
-#define NPCX_IRQ_WKINTH_0		NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_WKINTG_2			NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#define NPCX_IRQ_ITIM64			NPCX_IRQ_58
-#define NPCX_IRQ_LCT_WKINTF_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
-/* MIWU definition */
-#define LCT_WUI_GROUP			MIWU_GROUP_6
-#define LCT_WUI_MASK			MASK_PIN7
-
-/* Modules Map */
-
-/* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL			REG8(NPCX_MDC_BASE_ADDR + 0x009)
-
-/* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION		6
-#define NPCX_FWCTRL_FW_SLOT		7
-
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400E0000 + ((mdl) * 0x2000L))
-#define NPCX_LCT_BASE_ADDR		0x400D7000
-#define NPCX_SMB_BASE_ADDR(mdl)		(((mdl) < 2) ? \
-				(0x40009000 + ((mdl) * 0x2000L)) : \
-				((mdl) < 4) ? \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)) : \
-				((mdl) == 4) ? \
-				(0x40008000) : \
-				(0x40017000 + (((mdl) - 5) * 0x1000L)))
-
-#define NPCX_HFCBCD1			REG8(NPCX_HFCG_BASE_ADDR + 0x012)
-#define NPCX_HFCBCD2			REG8(NPCX_HFCG_BASE_ADDR + 0x014)
-
-enum {
-	NPCX_UART_PORT0 = 0,	/* UART port 0 */
-	NPCX_UART_PORT1 = 1,	/* UART port 1 */
-	NPCX_UART_PORT2 = 2,	/* UART port 2 */
-	NPCX_UART_PORT3 = 3,	/* UART port 3 */
-	NPCX_UART_COUNT
-};
-
- /* UART registers only used for FIFO mode */
-#define NPCX_UFTSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
-#define NPCX_UFRSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
-#define NPCX_UFTCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
-#define NPCX_UFRCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
-
-/* UART FIFO register fields */
-#define NPCX_UMDSL_FIFO_MD		0
-
-#define NPCX_UFTSTS_TEMPTY_LVL		FIELD(0, 5)
-#define NPCX_UFTSTS_TEMPTY_LVL_STS	5
-#define NPCX_UFTSTS_TFIFO_EMPTY_STS	6
-#define NPCX_UFTSTS_NXMIP		7
-
-#define NPCX_UFRSTS_RFULL_LVL_STS	5
-#define NPCX_UFRSTS_RFIFO_NEMPTY_STS	6
-#define NPCX_UFRSTS_ERR			7
-
-#define NPCX_UFTCTL_TEMPTY_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFTCTL_TEMPTY_LVL_EN	5
-#define NPCX_UFTCTL_TEMPTY_EN		6
-#define NPCX_UFTCTL_NXMIPEN		7
-
-#define NPCX_UFRCTL_RFULL_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFRCTL_RFULL_LVL_EN	5
-#define NPCX_UFRCTL_RNEMPTY_EN		6
-#define NPCX_UFRCTL_ERR_EN		7
-
-/* KBSCAN register fields */
-#define NPCX_KBHDRV_FIELD		FIELD(6, 2)
-
-/* GLUE registers */
-#define NPCX_GLUE_PSL_CTS		REG8(NPCX_GLUE_REGS_BASE + 0x027)
-#define NPCX_GLUE_PSL_MCTL1		REG8(NPCX_GLUE_REGS_BASE + 0x034)
-#define NPCX_GLUE_PSL_MCTL2		REG8(NPCX_GLUE_REGS_BASE + 0x038)
-
-/* PSL register fields */
-#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL	7
-#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL		6
-#define NPCX_GLUE_PSL_MCTL1_LCT_EV		4
-#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV		3
-#define NPCX_GLUE_PSL_MCTL1_PLS_EN		1
-#define NPCX_GLUE_PSL_MCTL1_OD_EN		0
-
-#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK	7
-#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN		6
-#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN	3
-#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL		FIELD(0, 1)
-
-/* GPIO registers */
-#define NPCX_PLOCK_CTL(n)		REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
-
-/* System Configuration (SCFG) Registers */
-
-/* SCFG enumeration */
-enum {
-	ALT_GROUP_0,
-	ALT_GROUP_1,
-	ALT_GROUP_2,
-	ALT_GROUP_3,
-	ALT_GROUP_4,
-	ALT_GROUP_5,
-	ALT_GROUP_6,
-	ALT_GROUP_7,
-	ALT_GROUP_8,
-	ALT_GROUP_9,
-	ALT_GROUP_A,
-	ALT_GROUP_B,
-	ALT_GROUP_C,
-	ALT_GROUP_D,
-	ALT_GROUP_E,
-	ALT_GROUP_F,
-	ALT_GROUP_G,
-	ALT_GROUP_H,
-	ALT_GROUP_J,
-	ALT_GROUP_COUNT
-};
-
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
-
-#define NPCX_LV_GPIO_CTL_ADDR(n)	(((n) < 5) ? \
-					(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\
-					(NPCX_SCFG_BASE_ADDR + 0x026))
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_LV_GPIO_CTL_ADDR(n))
-/* Device Alternate Function Lock */
-#define NPCX_DEVALT_LK(n)		REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n))
-
-/* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C7_0_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C6_0_SL		3
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C5_0_SL		5
-#define NPCX_DEVALT2_I2C3_0_SL		6
-#define NPCX_DEVALT6_I2C6_1_SL		5
-#define NPCX_DEVALT6_I2C5_1_SL		6
-#define NPCX_DEVALT6_I2C4_1_SL		7
-
-/* pin-mux for ADC */
-#define NPCX_DEVALTF_ADC5_SL		0
-#define NPCX_DEVALTF_ADC6_SL		1
-#define NPCX_DEVALTF_ADC7_SL		2
-#define NPCX_DEVALTF_ADC8_SL		3
-#define NPCX_DEVALTF_ADC9_SL		4
-#define NPCX_DEVALTF_ADC10_SL		5
-#define NPCX_DEVALTF_ADC11_SL		6
-
-/* pin-mux for PSL */
-#define NPCX_DEVALTD_PSL_IN1_AHI	0
-#define NPCX_DEVALTD_NPSL_IN1_SL	1
-#define NPCX_DEVALTD_PSL_IN2_AHI	2
-#define NPCX_DEVALTD_NPSL_IN2_SL	3
-#define NPCX_DEVALTD_PSL_IN3_AHI	4
-#define NPCX_DEVALTD_PSL_IN3_SL		5
-#define NPCX_DEVALTD_PSL_IN4_AHI	6
-#define NPCX_DEVALTD_PSL_IN4_SL		7
-
-/* pin-mux for Misc. */
-
-/* pin-mux for UART */
-#define NPCX_DEVALTJ_CR_SIN1_SL1	0
-#define NPCX_DEVALTJ_CR_SOUT1_SL1	1
-#define NPCX_DEVALTJ_CR_SIN1_SL2	2
-#define NPCX_DEVALTJ_CR_SOUT1_SL2	3
-#define NPCX_DEVALTJ_CR_SIN2_SL		4
-#define NPCX_DEVALTJ_CR_SOUT2_SL	5
-#define NPCX_DEVALTJ_CR_SIN3_SL		6
-#define NPCX_DEVALTJ_CR_SOUT3_SL	7
-#define NPCX_DEVALTE_CR_SIN4_SL		6
-#define NPCX_DEVALTE_CR_SOUT4_SL	7
-
-/* SHI module version 2 enable bit */
-#define NPCX_DEVALTF_SHI_NEW		7
-
-/* VCC_RST Pull-Up Disable */
-#define NPCX_DEVALTG_VCC1_RST_PUD	5
-#define NPCX_DEVALTG_PSL_OUT_SL		6
-#define NPCX_DEVALTG_PSL_GPO_SL		7
-
-/* SMBus register fields */
-#define NPCX_SMBSEL_SMB4SEL		4
-#define NPCX_SMBSEL_SMB5SEL		5
-#define NPCX_SMBSEL_SMB6SEL		6
-
-/* pin-mux for JTAG */
-#define NPCX_JEN_CTL1			REG8(NPCX_SCFG_BASE_ADDR + 0x120)
-#define NPCX_JEN_CTL1_JEN_EN_FIELD	FIELD(0, 4)
-#define NPCX_JEN_CTL1_JEN_EN_DIS	0x06
-#define NPCX_JEN_CTL1_JEN_EN_ENA	0x09
-
-/* SMB enumeration: I2C port definitions. */
-enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT1_0,	/* I2C port 1, bus 0 */
-	NPCX_I2C_PORT2_0,	/* I2C port 2, bus 0 */
-	NPCX_I2C_PORT3_0,	/* I2C port 3, bus 0 */
-	NPCX_I2C_PORT4_1,	/* I2C port 4, bus 1 */
-	NPCX_I2C_PORT5_0,	/* I2C port 5, bus 0 */
-	NPCX_I2C_PORT5_1,	/* I2C port 5, bus 1 */
-	NPCX_I2C_PORT6_0,	/* I2C port 6, bus 0 */
-	NPCX_I2C_PORT6_1,	/* I2C port 6, bus 1 */
-	NPCX_I2C_PORT7_0,	/* I2C port 7, bus 0 */
-	NPCX_I2C_COUNT,
-};
-
-/* Power Management Controller (PMC) Registers */
-#define NPCX_FMUL_WIN_DLY	REG8(NPCX_PMC_BASE_ADDR + 0x010)
-#define NPCX_RAM_PD(offset)	REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
-
-/* PMC register fields */
-#define NPCX_PWDWN_CTL3_SMB4_PD		4
-#define NPCX_PWDWN_CTL7_SMB5_PD		0
-#define NPCX_PWDWN_CTL7_SMB6_PD		1
-#define NPCX_PWDWN_CTL7_SMB7_PD		2
-#define NPCX_PWDWN_CTL7_ITIM64_PD	5
-#define NPCX_PWDWN_CTL7_UART2_PD	6
-
-/*
- * PMC enumeration:
- * Offsets from CGC_BASE registers for each peripheral.
- */
-enum {
-	CGC_OFFSET_KBS = 0,
-	CGC_OFFSET_UART = 0,
-	CGC_OFFSET_FAN = 0,
-	CGC_OFFSET_FIU = 0,
-	CGC_OFFSET_PS2 = 0,
-	CGC_OFFSET_PWM = 1,
-	CGC_OFFSET_I2C = 2,
-	CGC_OFFSET_ADC = 3,
-	CGC_OFFSET_PECI = 3,
-	CGC_OFFSET_SPI = 3,
-	CGC_OFFSET_TIMER = 3,
-	CGC_OFFSET_LPC = 4,
-	CGC_OFFSET_ESPI = 5,
-	CGC_OFFSET_I2C2 = 6,
-	CGC_OFFSET_UART2 = 6,
-};
-
-enum NPCX_PMC_PWDWN_CTL_T {
-	NPCX_PMC_PWDWN_1 = 0,
-	NPCX_PMC_PWDWN_2 = 1,
-	NPCX_PMC_PWDWN_3 = 2,
-	NPCX_PMC_PWDWN_4 = 3,
-	NPCX_PMC_PWDWN_5 = 4,
-	NPCX_PMC_PWDWN_6 = 5,
-	NPCX_PMC_PWDWN_7 = 6,
-	NPCX_PMC_PWDWN_CNT,
-};
-
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB4_PD))
-#define CGC_I2C_MASK2			(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB7_PD))
-#define CGC_UART2_MASK			BIT(NPCX_PWDWN_CTL7_UART2_PD)
-
-/* BBRAM register fields */
-#define NPCX_BKUP_STS_VSBY_STS		1
-#define NPCX_BKUP_STS_VCC1_STS		0
-#define NPCX_BKUP_STS_ALL_MASK \
-	(BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \
-	BIT(NPCX_BKUP_STS_VCC1_STS))
-#define NPCX_BBRAM_SIZE			128 /* Size of BBRAM */
-
-/* ITIM registers */
-#define NPCX_ITCNT32(n)			REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008)
-
-/* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32(ITIM32_6)
-/* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT32
-
-/* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM32_1
-/* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO				ITIM32_5
-/* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32_6
-
-/* ITIM enumeration */
-enum ITIM_MODULE_T {
-	ITIM32_1,
-	ITIM32_2,
-	ITIM32_3,
-	ITIM32_4,
-	ITIM32_5,
-	ITIM32_6,
-	ITIM_MODULE_COUNT,
-};
-
-/* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */
-#define NPCX_SHICFG3			REG8(NPCX_SHI_BASE_ADDR + 0x00C)
-#define NPCX_SHICFG4			REG8(NPCX_SHI_BASE_ADDR + 0x00D)
-#define NPCX_SHICFG5			REG8(NPCX_SHI_BASE_ADDR + 0x00E)
-#define NPCX_EVSTAT2			REG8(NPCX_SHI_BASE_ADDR + 0x00F)
-#define NPCX_EVENABLE2			REG8(NPCX_SHI_BASE_ADDR + 0x010)
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
-
-/* SHI register fields */
-#define NPCX_SHICFG3_OBUFLVLDIS		7
-#define NPCX_SHICFG4_IBUFLVLDIS		7
-#define NPCX_SHICFG5_IBUFLVL2		FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS	7
-#define NPCX_EVSTAT2_IBHF2		0
-#define NPCX_EVSTAT2_CSNRE		1
-#define NPCX_EVSTAT2_CSNFE		2
-#define NPCX_EVENABLE2_IBHF2EN		0
-#define NPCX_EVENABLE2_CSNREEN		1
-#define NPCX_EVENABLE2_CSNFEEN		2
-
-/* eSPI register fields */
-#define NPCX_ESPIIE_BMTXDONEIE		19
-#define NPCX_ESPIIE_PBMRXIE		20
-#define NPCX_ESPIIE_PMSGRXIE		21
-#define NPCX_ESPIIE_BMBURSTERRIE	22
-#define NPCX_ESPIIE_BMBURSTDONEIE	23
-
-#define NPCX_ESPIWE_PBMRXWE		20
-#define NPCX_ESPIWE_PMSGRXWE		21
-
-#define NPCX_ESPISTS_VWUPDW		17
-#define NPCX_ESPISTS_BMTXDONE		19
-#define NPCX_ESPISTS_PBMRX		20
-#define NPCX_ESPISTS_PMSGRX		21
-#define NPCX_ESPISTS_BMBURSTERR		22
-#define NPCX_ESPISTS_BMBURSTDONE	23
-#define NPCX_ESPISTS_ESPIRST_LVL	24
-
-#define ESPIIE_BMTXDONE			BIT(NPCX_ESPIIE_BMTXDONEIE)
-#define ESPIIE_PBMRX			BIT(NPCX_ESPIIE_PBMRXIE)
-#define ESPIIE_PMSGRX			BIT(NPCX_ESPIIE_PMSGRXIE)
-#define ESPIIE_BMBURSTERR		BIT(NPCX_ESPIIE_BMBURSTERRIE)
-#define ESPIIE_BMBURSTDONE		BIT(NPCX_ESPIIE_BMBURSTDONEIE)
-
-#define ESPIWE_PBMRX			BIT(NPCX_ESPIWE_PBMRXWE)
-#define ESPIWE_PMSGRX			BIT(NPCX_ESPIWE_PMSGRXWE)
-
-/* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_WK_EN(e)			(((e)<<20) & 0x00100000)
-#define VWEVMS_INTWK_EN(e)		(VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
-
-/* eSPI max supported frequency */
-enum {
-	NPCX_ESPI_MAXFREQ_20 = 0,
-	NPCX_ESPI_MAXFREQ_25 = 1,
-	NPCX_ESPI_MAXFREQ_33 = 2,
-	NPCX_ESPI_MAXFREQ_50 = 3,
-	NPCX_ESPI_MAXFREQ_66 = 4,
-	NPCX_ESPI_MAXFREQ_NONE = 0xFF
-};
-
-/* eSPI Operating Frequency */
-enum {
-	NPCX_ESPI_OPFREQ_20 = 0,
-	NPCX_ESPI_OPFREQ_25 = 1,
-	NPCX_ESPI_OPFREQ_33 = 2,
-	NPCX_ESPI_OPFREQ_50 = 3,
-	NPCX_ESPI_OPFREQ_66 = 4,
-	NPCX_ESPI_OPFREQ_NONE = 0xFF
-};
-
-/* eSPI max frequency support per FMCLK */
-#if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
-#else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
-#endif
-
-/* UART registers */
-#define NPCX_UART_WK_GROUP		MIWU_GROUP_8
-#define NPCX_UART_WK_BIT		7
-#define NPCX_UART2_WK_GROUP		MIWU_GROUP_1
-#define NPCX_UART2_WK_BIT		6
-
-/* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 0x10))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 0x10))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x02 + \
-					((n) * 0x10))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x03 + \
-					((n) * 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x04 + \
-					((n) * 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x05 + \
-					((n) * 0x10))
-#define NPCX_WKST_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x06 + \
-					((n) * 0x10))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x07 + \
-					((n) * 0x10))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKST(port, n)		REG8(NPCX_WKST_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
-
-/* LCT register */
-#define NPCX_LCTCONT			REG8(NPCX_LCT_BASE_ADDR + 0x002)
-#define NPCX_LCTSTAT			REG8(NPCX_LCT_BASE_ADDR + 0x004)
-#define NPCX_LCTSECOND			REG8(NPCX_LCT_BASE_ADDR + 0x005)
-#define NPCX_LCTMINUTE			REG8(NPCX_LCT_BASE_ADDR + 0x006)
-#define NPCX_LCTHOUR			REG8(NPCX_LCT_BASE_ADDR + 0x008)
-#define NPCX_LCTDAY			REG8(NPCX_LCT_BASE_ADDR + 0x00A)
-#define NPCX_LCTWEEK			REG8(NPCX_LCT_BASE_ADDR + 0x00C)
-/* LCTCONT fields */
-#define NPCX_LCTCONT_EN			0
-#define NPCX_LCTCONT_EN_FIELD		FIELD(0, 1)
-#define NPCX_LCTCONT_EVEN		1
-#define NPCX_LCTCONT_PSL_EN		2
-#define NPCX_LCTCONT_CLK_EN		6
-#define NPCX_LCTCONT_VSBY_PWR		7
-/* LCTSTAT fields */
-#define NPCX_LCTSTAT_EVST		0
-
-/* UART registers and functions */
-#if NPCX_UART_MODULE2
-/*
- * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
- * always 1 == MIWU_TABLE_1.
- */
-#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_DEVALT_SIN_SL		NPCX_DEVALTJ_CR_SIN1_SL2
-#define NPCX_UART_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_ALT_DEVALT_SIN_SL	NPCX_DEVALTJ_CR_SIN1_SL1
-#define NPCX_UART_ALT_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL1
-#else /* !NPCX_UART_MODULE2 */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_DEVALT_SIN_SL		NPCX_DEVALTJ_CR_SIN1_SL1
-#define NPCX_UART_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_ALT_DEVALT_SIN_SL	NPCX_DEVALTJ_CR_SIN1_SL2
-#define NPCX_UART_ALT_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL2
-#endif /* NPCX_UART_MODULE2 */
-
-/* ADC register */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
-/* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-/* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L*(n)))
-
-/* ADC register fields */
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR6_IEN		13
-#define NPCX_THRCTS_THR5_IEN		12
-#define NPCX_THRCTS_THR4_IEN		11
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR6_STS		5
-#define NPCX_THRCTS_THR5_STS		4
-#define NPCX_THRCTS_THR4_STS		3
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH4		4
-#define NPCX_ADC_THRESH5		5
-#define NPCX_ADC_THRESH6		6
-#define NPCX_ADC_THRESH_CNT		6
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
deleted file mode 100644
index f0c241e7f9..0000000000
--- a/chip/npcx/registers.h
+++ /dev/null
@@ -1,1693 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for NPCX processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "clock_chip.h"
-
-/******************************************************************************/
-/*
- * Macro Functions
- */
-/* Bit functions */
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
-#define UPDATE_BIT(reg, bit, cond)  {	if (cond) \
-						SET_BIT(reg, bit); \
-					else \
-						CLEAR_BIT(reg, bit); }
-/* Field functions */
-#define GET_POS_FIELD(pos, size)    pos
-#define GET_SIZE_FIELD(pos, size)   size
-#define FIELD_POS(field)            GET_POS_##field
-#define FIELD_SIZE(field)           GET_SIZE_##field
-/* Read field functions */
-#define GET_FIELD(reg, field) \
-	_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
-#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
-/* Write field functions */
-#define SET_FIELD(reg, field, value) \
-	_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
-#define _SET_FIELD_(reg, f_pos, f_size, value) \
-	((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
-			| ((value) << (f_pos)))
-
-/******************************************************************************/
-/*
- * NPCX (Nuvoton M4 EC) Register Definitions
- */
-
-/* Global Definition */
-#define I2C_7BITS_ADDR                   0
-/* Switcher of features */
-#define SUPPORT_LCT                      1
-#define SUPPORT_WDG                      1
-#define SUPPORT_P80_SEG                  0 /* Note: it uses KSO10 & KSO11 */
-/* Switcher of debugging */
-#define DEBUG_GPIO                       0
-#define DEBUG_I2C                        0
-#define DEBUG_TMR                        0
-#define DEBUG_WDG                        0
-#define DEBUG_FAN                        0
-#define DEBUG_PWM                        0
-#define DEBUG_SPI                        0
-#define DEBUG_FLH                        0
-#define DEBUG_PECI                       0
-#define DEBUG_SHI                        0
-#define DEBUG_CLK                        0
-#define DEBUG_LPC                        0
-#define DEBUG_ESPI                       0
-#define DEBUG_CEC                        0
-#define DEBUG_SIB                        0
-#define DEBUG_PS2                        0
-
-/* Modules Map */
-#define NPCX_ESPI_BASE_ADDR              0x4000A000
-#define NPCX_MDC_BASE_ADDR               0x4000C000
-#define NPCX_PMC_BASE_ADDR               0x4000D000
-#define NPCX_SIB_BASE_ADDR               0x4000E000
-#define NPCX_SHI_BASE_ADDR               0x4000F000
-#define NPCX_SHM_BASE_ADDR               0x40010000
-#define NPCX_GDMA_BASE_ADDR              0x40011000
-#define NPCX_FIU_BASE_ADDR               0x40020000
-#define NPCX_KBSCAN_REGS_BASE            0x400A3000
-#define NPCX_WOV_BASE_ADDR               0x400A4000
-#define NPCX_APM_BASE_ADDR               0x400A4800
-#define NPCX_GLUE_REGS_BASE              0x400A5000
-#define NPCX_BBRAM_BASE_ADDR             0x400AF000
-#define NPCX_PS2_BASE_ADDR               0x400B1000
-#define NPCX_HFCG_BASE_ADDR              0x400B5000
-#define NPCX_LFCG_BASE_ADDR              0x400B5100
-#define NPCX_FMUL2_BASE_ADDR             0x400B5200
-#define NPCX_MTC_BASE_ADDR               0x400B7000
-#define NPCX_MSWC_BASE_ADDR              0x400C1000
-#define NPCX_SCFG_BASE_ADDR              0x400C3000
-#define NPCX_KBC_BASE_ADDR               0x400C7000
-#define NPCX_ADC_BASE_ADDR               0x400D1000
-#define NPCX_SPI_BASE_ADDR               0x400D2000
-#define NPCX_PECI_BASE_ADDR              0x400D4000
-#define NPCX_TWD_BASE_ADDR               0x400D8000
-
-/* Multi-Modules Map */
-#define NPCX_PWM_BASE_ADDR(mdl)          (0x40080000 + ((mdl) * 0x2000L))
-#define NPCX_GPIO_BASE_ADDR(mdl)         (0x40081000 + ((mdl) * 0x2000L))
-#define NPCX_ITIM_BASE_ADDR(mdl)         (0x400B0000 + ((mdl) * 0x2000L))
-#define NPCX_MIWU_BASE_ADDR(mdl)         (0x400BB000 + ((mdl) * 0x2000L))
-#define NPCX_MFT_BASE_ADDR(mdl)          (0x400E1000 + ((mdl) * 0x2000L))
-#define NPCX_PM_CH_BASE_ADDR(mdl)        (0x400C9000 + ((mdl) * 0x2000L))
-
-/*
- * NPCX-IRQ numbers
- */
-#define NPCX_IRQ_0                       0
-#define NPCX_IRQ_1                       1
-#define NPCX_IRQ_2                       2
-#define NPCX_IRQ_3                       3
-#define NPCX_IRQ_4                       4
-#define NPCX_IRQ_5                       5
-#define NPCX_IRQ_6                       6
-#define NPCX_IRQ_7                       7
-#define NPCX_IRQ_8                       8
-#define NPCX_IRQ_9                       9
-#define NPCX_IRQ_10                      10
-#define NPCX_IRQ_11                      11
-#define NPCX_IRQ_12                      12
-#define NPCX_IRQ_13                      13
-#define NPCX_IRQ_14                      14
-#define NPCX_IRQ_15                      15
-#define NPCX_IRQ_16                      16
-#define NPCX_IRQ_17                      17
-#define NPCX_IRQ_18                      18
-#define NPCX_IRQ_19                      19
-#define NPCX_IRQ_20                      20
-#define NPCX_IRQ_21                      21
-#define NPCX_IRQ_22                      22
-#define NPCX_IRQ_23                      23
-#define NPCX_IRQ_24                      24
-#define NPCX_IRQ_25                      25
-#define NPCX_IRQ_26                      26
-#define NPCX_IRQ_27                      27
-#define NPCX_IRQ_28                      28
-#define NPCX_IRQ_29                      29
-#define NPCX_IRQ_30                      30
-#define NPCX_IRQ_31                      31
-#define NPCX_IRQ_32                      32
-#define NPCX_IRQ_33                      33
-#define NPCX_IRQ_34                      34
-#define NPCX_IRQ_35                      35
-#define NPCX_IRQ_36                      36
-#define NPCX_IRQ_37                      37
-#define NPCX_IRQ_38                      38
-#define NPCX_IRQ_39                      39
-#define NPCX_IRQ_40                      40
-#define NPCX_IRQ_41                      41
-#define NPCX_IRQ_42                      42
-#define NPCX_IRQ_43                      43
-#define NPCX_IRQ_44                      44
-#define NPCX_IRQ_45                      45
-#define NPCX_IRQ_46                      46
-#define NPCX_IRQ_47                      47
-#define NPCX_IRQ_48                      48
-#define NPCX_IRQ_49                      49
-#define NPCX_IRQ_50                      50
-#define NPCX_IRQ_51                      51
-#define NPCX_IRQ_52                      52
-#define NPCX_IRQ_53                      53
-#define NPCX_IRQ_54                      54
-#define NPCX_IRQ_55                      55
-#define NPCX_IRQ_56                      56
-#define NPCX_IRQ_57                      57
-#define NPCX_IRQ_58                      58
-#define NPCX_IRQ_59                      59
-#define NPCX_IRQ_60                      60
-#define NPCX_IRQ_61                      61
-#define NPCX_IRQ_62                      62
-#define NPCX_IRQ_63                      63
-
-#define NPCX_IRQ_COUNT                   64
-
-/******************************************************************************/
-/* High Frequency Clock Generator (HFCG) registers */
-#define NPCX_HFCGCTRL                     REG8(NPCX_HFCG_BASE_ADDR + 0x000)
-#define NPCX_HFCGML                       REG8(NPCX_HFCG_BASE_ADDR + 0x002)
-#define NPCX_HFCGMH                       REG8(NPCX_HFCG_BASE_ADDR + 0x004)
-#define NPCX_HFCGN                        REG8(NPCX_HFCG_BASE_ADDR + 0x006)
-#define NPCX_HFCGP                        REG8(NPCX_HFCG_BASE_ADDR + 0x008)
-#define NPCX_HFCBCD                       REG8(NPCX_HFCG_BASE_ADDR + 0x010)
-
-/* HFCG register fields */
-#define NPCX_HFCGCTRL_LOAD               0
-#define NPCX_HFCGCTRL_LOCK               2
-#define NPCX_HFCGCTRL_CLK_CHNG           7
-
-/******************************************************************************/
-/* Low Frequency Clock Generator (LFCG) registers */
-#define NPCX_LFCGCTL                      REG8(NPCX_LFCG_BASE_ADDR + 0x000)
-#define NPCX_HFRDI                       REG16(NPCX_LFCG_BASE_ADDR + 0x002)
-#define NPCX_HFRDF                       REG16(NPCX_LFCG_BASE_ADDR + 0x004)
-#define NPCX_FRCDIV                      REG16(NPCX_LFCG_BASE_ADDR + 0x006)
-#define NPCX_DIVCOR1                     REG16(NPCX_LFCG_BASE_ADDR + 0x008)
-#define NPCX_DIVCOR2                     REG16(NPCX_LFCG_BASE_ADDR + 0x00A)
-#define NPCX_LFCGCTL2                     REG8(NPCX_LFCG_BASE_ADDR + 0x014)
-
-/* LFCG register fields */
-#define NPCX_LFCGCTL_XTCLK_VAL            7
-#define NPCX_LFCGCTL2_XT_OSC_SL_EN        6
-
-/******************************************************************************/
-/* CR UART Register */
-#define NPCX_UTBUF(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000)
-#define NPCX_URBUF(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002)
-#define NPCX_UICTRL(n)                   REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004)
-#define NPCX_USTAT(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006)
-#define NPCX_UFRS(n)                     REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008)
-#define NPCX_UMDSL(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A)
-#define NPCX_UBAUD(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C)
-#define NPCX_UPSR(n)                     REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E)
-
-/******************************************************************************/
-/* KBSCAN registers */
-#define NPCX_KBSIN                        REG8(NPCX_KBSCAN_REGS_BASE + 0x04)
-#define NPCX_KBSINPU                      REG8(NPCX_KBSCAN_REGS_BASE + 0x05)
-#define NPCX_KBSOUT0                     REG16(NPCX_KBSCAN_REGS_BASE + 0x06)
-#define NPCX_KBSOUT1                     REG16(NPCX_KBSCAN_REGS_BASE + 0x08)
-#define NPCX_KBS_BUF_INDX                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0A)
-#define NPCX_KBS_BUF_DATA                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0B)
-#define NPCX_KBSEVT                       REG8(NPCX_KBSCAN_REGS_BASE + 0x0C)
-#define NPCX_KBSCTL                       REG8(NPCX_KBSCAN_REGS_BASE + 0x0D)
-#define NPCX_KBS_CFG_INDX                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0E)
-#define NPCX_KBS_CFG_DATA                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0F)
-
-/* KBSCAN register fields */
-#define NPCX_KBSBUFINDX                  0
-#define NPCX_KBSDONE                     0
-#define NPCX_KBSERR                      1
-#define NPCX_KBSSTART                    0
-#define NPCX_KBSMODE                     1
-#define NPCX_KBSIEN                      2
-#define NPCX_KBSINC                      3
-#define NPCX_KBSCFGINDX                  0
-
-/* KBSCAN definitions */
-#define KB_ROW_NUM  8  /* Rows numbers of keyboard matrix */
-#define KB_COL_NUM  18 /* Columns numbers of keyboard matrix */
-#define KB_ROW_MASK ((1<<KB_ROW_NUM) - 1) /* Mask of rows of keyboard matrix */
-
-/******************************************************************************/
-/* GLUE registers */
-#define NPCX_GLUE_SDPD0                   REG8(NPCX_GLUE_REGS_BASE + 0x010)
-#define NPCX_GLUE_SDPD1                   REG8(NPCX_GLUE_REGS_BASE + 0x012)
-#define NPCX_GLUE_SDP_CTS                 REG8(NPCX_GLUE_REGS_BASE + 0x014)
-#define NPCX_GLUE_SMBSEL                  REG8(NPCX_GLUE_REGS_BASE + 0x021)
-/******************************************************************************/
-
-/* MIWU enumeration */
-enum {
-	MIWU_TABLE_0,
-	MIWU_TABLE_1,
-	MIWU_TABLE_2,
-	MIWU_TABLE_COUNT
-};
-
-enum {
-	MIWU_GROUP_1,
-	MIWU_GROUP_2,
-	MIWU_GROUP_3,
-	MIWU_GROUP_4,
-	MIWU_GROUP_5,
-	MIWU_GROUP_6,
-	MIWU_GROUP_7,
-	MIWU_GROUP_8,
-	MIWU_GROUP_COUNT
-};
-
-enum {
-	MIWU_EDGE_RISING,
-	MIWU_EDGE_FALLING,
-	MIWU_EDGE_ANYING,
-};
-
-/* MIWU utilities */
-#define MIWU_TABLE_WKKEY MIWU_TABLE_1
-#define MIWU_GROUP_WKKEY MIWU_GROUP_3
-
-/******************************************************************************/
-/* GPIO registers */
-#define NPCX_PDOUT(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x000)
-#define NPCX_PDIN(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x001)
-#define NPCX_PDIR(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x002)
-#define NPCX_PPULL(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x003)
-#define NPCX_PPUD(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004)
-#define NPCX_PENVDD(n)                    REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005)
-#define NPCX_PTYPE(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006)
-
-/* GPIO enumeration */
-enum {
-	GPIO_PORT_0,
-	GPIO_PORT_1,
-	GPIO_PORT_2,
-	GPIO_PORT_3,
-	GPIO_PORT_4,
-	GPIO_PORT_5,
-	GPIO_PORT_6,
-	GPIO_PORT_7,
-	GPIO_PORT_8,
-	GPIO_PORT_9,
-	GPIO_PORT_A,
-	GPIO_PORT_B,
-	GPIO_PORT_C,
-	GPIO_PORT_D,
-	GPIO_PORT_E,
-	GPIO_PORT_F,
-	GPIO_PORT_COUNT
-};
-
-enum {
-	MASK_PIN0 = BIT(0),
-	MASK_PIN1 = BIT(1),
-	MASK_PIN2 = BIT(2),
-	MASK_PIN3 = BIT(3),
-	MASK_PIN4 = BIT(4),
-	MASK_PIN5 = BIT(5),
-	MASK_PIN6 = BIT(6),
-	MASK_PIN7 = BIT(7),
-};
-
-/* Chip-independent aliases for port base group */
-#define GPIO_0 GPIO_PORT_0
-#define GPIO_1 GPIO_PORT_1
-#define GPIO_2 GPIO_PORT_2
-#define GPIO_3 GPIO_PORT_3
-#define GPIO_4 GPIO_PORT_4
-#define GPIO_5 GPIO_PORT_5
-#define GPIO_6 GPIO_PORT_6
-#define GPIO_7 GPIO_PORT_7
-#define GPIO_8 GPIO_PORT_8
-#define GPIO_9 GPIO_PORT_9
-#define GPIO_A GPIO_PORT_A
-#define GPIO_B GPIO_PORT_B
-#define GPIO_C GPIO_PORT_C
-#define GPIO_D GPIO_PORT_D
-#define GPIO_E GPIO_PORT_E
-#define GPIO_F GPIO_PORT_F
-#define UNIMPLEMENTED_GPIO_BANK GPIO_PORT_0
-
-/******************************************************************************/
-/* MSWC Registers */
-#define NPCX_MSWCTL1                      REG8(NPCX_MSWC_BASE_ADDR + 0x000)
-#define NPCX_MSWCTL2                      REG8(NPCX_MSWC_BASE_ADDR + 0x002)
-#define NPCX_HCBAL                        REG8(NPCX_MSWC_BASE_ADDR + 0x008)
-#define NPCX_HCBAH                        REG8(NPCX_MSWC_BASE_ADDR + 0x00A)
-#define NPCX_SRID_CR                      REG8(NPCX_MSWC_BASE_ADDR + 0x01C)
-#define NPCX_SID_CR                       REG8(NPCX_MSWC_BASE_ADDR + 0x020)
-#define NPCX_DEVICE_ID_CR                 REG8(NPCX_MSWC_BASE_ADDR + 0x022)
-
-/* MSWC register fields */
-#define NPCX_MSWCTL1_HRSTOB              0
-#define NPCS_MSWCTL1_HWPRON              1
-#define NPCX_MSWCTL1_PLTRST_ACT          2
-#define NPCX_MSWCTL1_VHCFGA              3
-#define NPCX_MSWCTL1_HCFGLK              4
-#define NPCX_MSWCTL1_PWROFFB             6
-#define NPCX_MSWCTL1_A20MB               7
-
-/******************************************************************************/
-/* System Configuration (SCFG) Registers */
-#define NPCX_DEVCNT                       REG8(NPCX_SCFG_BASE_ADDR + 0x000)
-#define NPCX_STRPST                       REG8(NPCX_SCFG_BASE_ADDR + 0x001)
-#define NPCX_RSTCTL                       REG8(NPCX_SCFG_BASE_ADDR + 0x002)
-#define NPCX_DEV_CTL4                     REG8(NPCX_SCFG_BASE_ADDR + 0x006)
-#define NPCX_LFCGCALCNT                   REG8(NPCX_SCFG_BASE_ADDR + 0x021)
-#define NPCX_PUPD_EN0                     REG8(NPCX_SCFG_BASE_ADDR + 0x028)
-#define NPCX_PUPD_EN1                     REG8(NPCX_SCFG_BASE_ADDR + 0x029)
-#define NPCX_SCFG_VER                     REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
-
-#define TEST_BKSL                         REG8(NPCX_SCFG_BASE_ADDR + 0x037)
-#define TEST0                             REG8(NPCX_SCFG_BASE_ADDR + 0x038)
-#define BLKSEL                           0
-
-/* SCFG register fields */
-#define NPCX_DEVCNT_F_SPI_TRIS           6
-#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD    FIELD(2, 2)
-#define NPCX_DEVCNT_JEN1_HEN             5
-#define NPCX_DEVCNT_JEN0_HEN             4
-#define NPCX_STRPST_TRIST                1
-#define NPCX_STRPST_TEST                 2
-#define NPCX_STRPST_JEN1                 4
-#define NPCX_STRPST_JEN0                 5
-#define NPCX_STRPST_SPI_COMP             7
-#define NPCX_RSTCTL_VCC1_RST_STS         0
-#define NPCX_RSTCTL_DBGRST_STS           1
-#define NPCX_RSTCTL_VCC1_RST_SCRATCH     3
-#define NPCX_RSTCTL_LRESET_PLTRST_MODE   5
-#define NPCX_RSTCTL_HIPRST_MODE          6
-#define NPCX_DEV_CTL4_F_SPI_SLLK         2
-#define NPCX_DEV_CTL4_SPI_SP_SEL         4
-#define NPCX_DEV_CTL4_WP_IF              5
-#define NPCX_DEV_CTL4_VCC1_RST_LK        6
-#define NPCX_DEVPU0_I2C0_0_PUE           0
-#define NPCX_DEVPU0_I2C0_1_PUE           1
-#define NPCX_DEVPU0_I2C1_0_PUE           2
-#define NPCX_DEVPU0_I2C2_0_PUE           4
-#define NPCX_DEVPU0_I2C3_0_PUE           6
-#define NPCX_DEVPU1_F_SPI_PUD_EN         7
-
-/* DEVALT */
-/* pin-mux for SPI/FIU */
-#define NPCX_DEVALT0_SPIP_SL             0
-#define NPCX_DEVALT0_GPIO_NO_SPIP        3
-#define NPCX_DEVALT0_F_SPI_CS1_2         4
-#define NPCX_DEVALT0_F_SPI_CS1_1         5
-#define NPCX_DEVALT0_F_SPI_QUAD          6
-#define NPCX_DEVALT0_NO_F_SPI            7
-
-/* pin-mux for LPC/eSPI */
-#define NPCX_DEVALT1_KBRST_SL            0
-#define NPCX_DEVALT1_A20M_SL             1
-#define NPCX_DEVALT1_SMI_SL              2
-#define NPCX_DEVALT1_EC_SCI_SL           3
-#define NPCX_DEVALT1_NO_PWRGD            4
-#define NPCX_DEVALT1_RST_OUT_SL          5
-#define NPCX_DEVALT1_CLKRN_SL            6
-#define NPCX_DEVALT1_NO_LPC_ESPI         7
-
-/* pin-mux for PS2 */
-#define NPCX_DEVALT3_PS2_0_SL            0
-#define NPCX_DEVALT3_PS2_1_SL            1
-#define NPCX_DEVALT3_PS2_2_SL            2
-#define NPCX_DEVALT3_PS2_3_SL            3
-#define NPCX_DEVALTC_PS2_3_SL2           3
-
-/* pin-mux for Tacho */
-#define NPCX_DEVALT3_TA1_SL1             4
-#define NPCX_DEVALT3_TB1_SL1             5
-#define NPCX_DEVALT3_TA2_SL1             6
-#define NPCX_DEVALT3_TB2_SL1             7
-#define NPCX_DEVALTC_TA1_SL2             4
-#define NPCX_DEVALTC_TB1_SL2             5
-#define NPCX_DEVALTC_TA2_SL2             6
-#define NPCX_DEVALTC_TB2_SL2             7
-
-/* pin-mux for PWM */
-#define NPCX_DEVALT4_PWM0_SL             0
-#define NPCX_DEVALT4_PWM1_SL             1
-#define NPCX_DEVALT4_PWM2_SL             2
-#define NPCX_DEVALT4_PWM3_SL             3
-#define NPCX_DEVALT4_PWM4_SL             4
-#define NPCX_DEVALT4_PWM5_SL             5
-#define NPCX_DEVALT4_PWM6_SL             6
-#define NPCX_DEVALT4_PWM7_SL             7
-
-/* pin-mux for JTAG */
-#define NPCX_DEVALT5_TRACE_EN            0
-
-/* pin-mux for ADC */
-#define NPCX_DEVALT6_ADC0_SL             0
-#define NPCX_DEVALT6_ADC1_SL             1
-#define NPCX_DEVALT6_ADC2_SL             2
-#define NPCX_DEVALT6_ADC3_SL             3
-#define NPCX_DEVALT6_ADC4_SL             4
-
-/* pin-mux for Keyboard */
-#define NPCX_DEVALT7_NO_KSI0_SL          0
-#define NPCX_DEVALT7_NO_KSI1_SL          1
-#define NPCX_DEVALT7_NO_KSI2_SL          2
-#define NPCX_DEVALT7_NO_KSI3_SL          3
-#define NPCX_DEVALT7_NO_KSI4_SL          4
-#define NPCX_DEVALT7_NO_KSI5_SL          5
-#define NPCX_DEVALT7_NO_KSI6_SL          6
-#define NPCX_DEVALT7_NO_KSI7_SL          7
-#define NPCX_DEVALT8_NO_KSO00_SL         0
-#define NPCX_DEVALT8_NO_KSO01_SL         1
-#define NPCX_DEVALT8_NO_KSO02_SL         2
-#define NPCX_DEVALT8_NO_KSO03_SL         3
-#define NPCX_DEVALT8_NO_KSO04_SL         4
-#define NPCX_DEVALT8_NO_KSO05_SL         5
-#define NPCX_DEVALT8_NO_KSO06_SL         6
-#define NPCX_DEVALT8_NO_KSO07_SL         7
-#define NPCX_DEVALT9_NO_KSO08_SL         0
-#define NPCX_DEVALT9_NO_KSO09_SL         1
-#define NPCX_DEVALT9_NO_KSO10_SL         2
-#define NPCX_DEVALT9_NO_KSO11_SL         3
-#define NPCX_DEVALT9_NO_KSO12_SL         4
-#define NPCX_DEVALT9_NO_KSO13_SL         5
-#define NPCX_DEVALT9_NO_KSO14_SL         6
-#define NPCX_DEVALT9_NO_KSO15_SL         7
-#define NPCX_DEVALTA_NO_KSO16_SL         0
-#define NPCX_DEVALTA_NO_KSO17_SL         1
-
-/* pin-mux for Others */
-#define NPCX_DEVALTA_32K_OUT_SL          2
-#define NPCX_DEVALTA_NO_VCC1_RST         4
-#define NPCX_DEVALTA_NO_PECI_EN          6
-#define NPCX_DEVALTC_SHI_SL              1
-
-/* Others bit definitions */
-#define NPCX_LFCGCALCNT_LPREG_CTL_EN     1
-
-/******************************************************************************/
-/* Development and Debug Support (DBG) Registers */
-#define NPCX_DBGCTRL                      REG8(NPCX_SCFG_BASE_ADDR + 0x074)
-#define NPCX_DBGFRZEN1                    REG8(NPCX_SCFG_BASE_ADDR + 0x076)
-#define NPCX_DBGFRZEN2                    REG8(NPCX_SCFG_BASE_ADDR + 0x077)
-#define NPCX_DBGFRZEN3                    REG8(NPCX_SCFG_BASE_ADDR + 0x078)
-/* DBG register fields */
-#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS      7
-
-/******************************************************************************/
-/* SMBus Registers */
-#define NPCX_SMBSDA(n)                    REG8(NPCX_SMB_BASE_ADDR(n) + 0x000)
-#define NPCX_SMBST(n)                     REG8(NPCX_SMB_BASE_ADDR(n) + 0x002)
-#define NPCX_SMBCST(n)                    REG8(NPCX_SMB_BASE_ADDR(n) + 0x004)
-#define NPCX_SMBCTL1(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x006)
-#define NPCX_SMBADDR1(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x008)
-#define NPCX_SMBTMR_ST(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x009)
-#define NPCX_SMBCTL2(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x00A)
-#define NPCX_SMBTMR_EN(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x00B)
-#define NPCX_SMBADDR2(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x00C)
-#define NPCX_SMBCTL3(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x00E)
-/* SMB Registers in bank 0 */
-#define NPCX_SMBADDR3(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
-#define NPCX_SMBADDR7(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x011)
-#define NPCX_SMBADDR4(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
-#define NPCX_SMBADDR8(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x013)
-#define NPCX_SMBADDR5(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
-#define NPCX_SMBADDR6(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x016)
-#define NPCX_SMBCST2(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
-#define NPCX_SMBCST3(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
-#define NPCX_SMBCTL4(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
-#define NPCX_SMBSCLLT(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
-#define NPCX_SMBFIF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01D)
-#define NPCX_SMBSCLHT(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
-/* SMB Registers in bank 1 */
-#define NPCX_SMBFIF_CTS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
-#define NPCX_SMBTXF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
-#define NPCX_SMB_T_OUT(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
-/*
- * These two registers are the same as in bank 0
- * #define NPCX_SMBCST2(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
- * #define NPCX_SMBCST3(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
- */
-#define NPCX_SMBTXF_STS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
-#define NPCX_SMBRXF_STS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
-#define NPCX_SMBRXF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
-
-/* SMBus register fields */
-#define NPCX_SMBST_XMIT                  0
-#define NPCX_SMBST_MASTER                1
-#define NPCX_SMBST_NMATCH                2
-#define NPCX_SMBST_STASTR                3
-#define NPCX_SMBST_NEGACK                4
-#define NPCX_SMBST_BER                   5
-#define NPCX_SMBST_SDAST                 6
-#define NPCX_SMBST_SLVSTP                7
-#define NPCX_SMBCST_BUSY                 0
-#define NPCX_SMBCST_BB                   1
-#define NPCX_SMBCST_MATCH                2
-#define NPCX_SMBCST_GCMATCH              3
-#define NPCX_SMBCST_TSDA                 4
-#define NPCX_SMBCST_TGSCL                5
-#define NPCX_SMBCST_MATCHAF              6
-#define NPCX_SMBCST_ARPMATCH             7
-#define NPCX_SMBCST2_MATCHA1F            0
-#define NPCX_SMBCST2_MATCHA2F            1
-#define NPCX_SMBCST2_MATCHA3F            2
-#define NPCX_SMBCST2_MATCHA4F            3
-#define NPCX_SMBCST2_MATCHA5F            4
-#define NPCX_SMBCST2_MATCHA6F            5
-#define NPCX_SMBCST2_MATCHA7F            6
-#define NPCX_SMBCST2_INTSTS              7
-#define NPCX_SMBCST3_MATCHA8F            0
-#define NPCX_SMBCST3_MATCHA9F            1
-#define NPCX_SMBCST3_MATCHA10F           2
-#define NPCX_SMBCTL1_START               0
-#define NPCX_SMBCTL1_STOP                1
-#define NPCX_SMBCTL1_INTEN               2
-#define NPCX_SMBCTL1_ACK                 4
-#define NPCX_SMBCTL1_GCMEN               5
-#define NPCX_SMBCTL1_NMINTE              6
-#define NPCX_SMBCTL1_STASTRE             7
-#define NPCX_SMBCTL2_ENABLE              0
-#define NPCX_SMBCTL2_SCLFRQ7_FIELD       FIELD(1, 7)
-#define NPCX_SMBCTL3_ARPMEN              2
-#define NPCX_SMBCTL3_SCLFRQ2_FIELD       FIELD(0, 2)
-#define NPCX_SMBCTL3_IDL_START           3
-#define NPCX_SMBCTL3_400K                4
-#define NPCX_SMBCTL3_BNK_SEL             5
-#define NPCX_SMBCTL3_SDA_LVL             6
-#define NPCX_SMBCTL3_SCL_LVL             7
-#define NPCX_SMBCTL4_HLDT_FIELD          FIELD(0, 6)
-#define NPCX_SMBCTL4_LVL_WE              7
-#define NPCX_SMBADDR1_SAEN               7
-#define NPCX_SMBADDR2_SAEN               7
-#define NPCX_SMBADDR3_SAEN               7
-#define NPCX_SMBADDR4_SAEN               7
-#define NPCX_SMBADDR5_SAEN               7
-#define NPCX_SMBADDR6_SAEN               7
-#define NPCX_SMBADDR7_SAEN               7
-#define NPCX_SMBADDR8_SAEN               7
-#define NPCX_SMBFIF_CTS_RXF_TXE          1
-#define NPCX_SMBFIF_CTS_CLR_FIFO         6
-
-#define NPCX_SMBFIF_CTL_FIFO_EN          4
-
-#define NPCX_SMBRXF_STS_RX_THST          6
-
-/* RX FIFO threshold */
-#define NPCX_SMBRXF_CTL_RX_THR           FIELD(0, 6)
-/*
- * In controller receiving mode, last byte in FIFO should send ACK or NACK
- */
-#define NPCX_SMBRXF_CTL_LAST             7
-
-/******************************************************************************/
-/* Power Management Controller (PMC) Registers */
-#define NPCX_PMCSR                     REG8(NPCX_PMC_BASE_ADDR + 0x000)
-#define NPCX_ENIDL_CTL                 REG8(NPCX_PMC_BASE_ADDR + 0x003)
-#define NPCX_DISIDL_CTL                REG8(NPCX_PMC_BASE_ADDR + 0x004)
-#define NPCX_DISIDL_CTL1               REG8(NPCX_PMC_BASE_ADDR + 0x005)
-#define NPCX_PWDWN_CTL_ADDR(offset)    (((offset) < 6) ? \
-			(NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \
-			(NPCX_PMC_BASE_ADDR + 0x024))
-#define NPCX_PWDWN_CTL(offset)         REG8(NPCX_PWDWN_CTL_ADDR(offset))
-
-/* PMC register fields */
-#define NPCX_PMCSR_DI_INSTW              0
-#define NPCX_PMCSR_DHF                   1
-#define NPCX_PMCSR_IDLE                  2
-#define NPCX_PMCSR_NWBI                  3
-#define NPCX_PMCSR_OHFC                  6
-#define NPCX_PMCSR_OLFC                  7
-#define NPCX_DISIDL_CTL_RAM_DID          5
-#define NPCX_ENIDL_CTL_ADC_LFSL          7
-#define NPCX_ENIDL_CTL_LP_WK_CTL         6
-#define NPCX_ENIDL_CTL_PECI_ENI          2
-#define NPCX_ENIDL_CTL_ADC_ACC_DIS       1
-#define NPCX_PWDWN_CTL1_KBS_PD           0
-#define NPCX_PWDWN_CTL1_SDP_PD           1
-#define NPCX_PWDWN_CTL1_FIU_PD           2
-#define NPCX_PWDWN_CTL1_PS2_PD           3
-#define NPCX_PWDWN_CTL1_UART_PD          4
-#define NPCX_PWDWN_CTL1_MFT1_PD          5
-#define NPCX_PWDWN_CTL1_MFT2_PD          6
-#define NPCX_PWDWN_CTL1_MFT3_PD          7
-#define NPCX_PWDWN_CTL2_PWM0_PD          0
-#define NPCX_PWDWN_CTL2_PWM1_PD          1
-#define NPCX_PWDWN_CTL2_PWM2_PD          2
-#define NPCX_PWDWN_CTL2_PWM3_PD          3
-#define NPCX_PWDWN_CTL2_PWM4_PD          4
-#define NPCX_PWDWN_CTL2_PWM5_PD          5
-#define NPCX_PWDWN_CTL2_PWM6_PD          6
-#define NPCX_PWDWN_CTL2_PWM7_PD          7
-#define NPCX_PWDWN_CTL3_SMB0_PD          0
-#define NPCX_PWDWN_CTL3_SMB1_PD          1
-#define NPCX_PWDWN_CTL3_SMB2_PD          2
-#define NPCX_PWDWN_CTL3_SMB3_PD          3
-#define NPCX_PWDWN_CTL3_GMDA_PD          7
-#define NPCX_PWDWN_CTL4_ITIM1_PD         0
-#define NPCX_PWDWN_CTL4_ITIM2_PD         1
-#define NPCX_PWDWN_CTL4_ITIM3_PD         2
-#define NPCX_PWDWN_CTL4_ADC_PD           4
-#define NPCX_PWDWN_CTL4_PECI_PD          5
-#define NPCX_PWDWN_CTL4_PWM6_PD          6
-#define NPCX_PWDWN_CTL4_SPIP_PD          7
-#define NPCX_PWDWN_CTL5_SHI_PD           1
-#define NPCX_PWDWN_CTL5_MRFSH_DIS        2
-#define NPCX_PWDWN_CTL5_C2HACC_PD        3
-#define NPCX_PWDWN_CTL5_SHM_REG_PD       4
-#define NPCX_PWDWN_CTL5_SHM_PD           5
-#define NPCX_PWDWN_CTL5_DP80_PD          6
-#define NPCX_PWDWN_CTL5_MSWC_PD          7
-#define NPCX_PWDWN_CTL6_ITIM4_PD         0
-#define NPCX_PWDWN_CTL6_ITIM5_PD         1
-#define NPCX_PWDWN_CTL6_ITIM6_PD         2
-#define NPCX_PWDWN_CTL6_ESPI_PD          7
-
-/* TODO: set PD masks based upon actual peripheral usage */
-#define CGC_KBS_MASK     BIT(NPCX_PWDWN_CTL1_KBS_PD)
-#define CGC_UART_MASK    BIT(NPCX_PWDWN_CTL1_UART_PD)
-#define CGC_FAN_MASK     (BIT(NPCX_PWDWN_CTL1_MFT1_PD) | \
-			 BIT(NPCX_PWDWN_CTL1_MFT2_PD))
-#define CGC_FIU_MASK     BIT(NPCX_PWDWN_CTL1_FIU_PD)
-#define CGC_PS2_MASK     BIT(NPCX_PWDWN_CTL1_PS2_PD)
-#define CGC_ADC_MASK     BIT(NPCX_PWDWN_CTL4_ADC_PD)
-#define CGC_PECI_MASK    BIT(NPCX_PWDWN_CTL4_PECI_PD)
-#define CGC_SPI_MASK     BIT(NPCX_PWDWN_CTL4_SPIP_PD)
-#define CGC_TIMER_MASK   (BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | \
-			 BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \
-			 BIT(NPCX_PWDWN_CTL4_ITIM3_PD))
-#define CGC_LPC_MASK     (BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_SHM_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_DP80_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_MSWC_PD))
-#define CGC_ESPI_MASK    BIT(NPCX_PWDWN_CTL6_ESPI_PD)
-
-/******************************************************************************/
-/* Flash Interface Unit (FIU) Registers */
-#define NPCX_FIU_CFG                      REG8(NPCX_FIU_BASE_ADDR + 0x000)
-#define NPCX_BURST_CFG                    REG8(NPCX_FIU_BASE_ADDR + 0x001)
-#define NPCX_RESP_CFG                     REG8(NPCX_FIU_BASE_ADDR + 0x002)
-#define NPCX_SPI_FL_CFG                   REG8(NPCX_FIU_BASE_ADDR + 0x014)
-#define NPCX_UMA_CODE                     REG8(NPCX_FIU_BASE_ADDR + 0x016)
-#define NPCX_UMA_AB0                      REG8(NPCX_FIU_BASE_ADDR + 0x017)
-#define NPCX_UMA_AB1                      REG8(NPCX_FIU_BASE_ADDR + 0x018)
-#define NPCX_UMA_AB2                      REG8(NPCX_FIU_BASE_ADDR + 0x019)
-#define NPCX_UMA_DB0                      REG8(NPCX_FIU_BASE_ADDR + 0x01A)
-#define NPCX_UMA_DB1                      REG8(NPCX_FIU_BASE_ADDR + 0x01B)
-#define NPCX_UMA_DB2                      REG8(NPCX_FIU_BASE_ADDR + 0x01C)
-#define NPCX_UMA_DB3                      REG8(NPCX_FIU_BASE_ADDR + 0x01D)
-#define NPCX_UMA_CTS                      REG8(NPCX_FIU_BASE_ADDR + 0x01E)
-#define NPCX_UMA_ECTS                     REG8(NPCX_FIU_BASE_ADDR + 0x01F)
-#define NPCX_UMA_DB0_3                   REG32(NPCX_FIU_BASE_ADDR + 0x020)
-#define NPCX_FIU_RD_CMD                   REG8(NPCX_FIU_BASE_ADDR + 0x030)
-#define NPCX_FIU_DMM_CYC                  REG8(NPCX_FIU_BASE_ADDR + 0x032)
-#define NPCX_FIU_EXT_CFG                  REG8(NPCX_FIU_BASE_ADDR + 0x033)
-#define NPCX_FIU_UMA_AB0_3               REG32(NPCX_FIU_BASE_ADDR + 0x034)
-
-/* FIU register fields */
-#define NPCX_RESP_CFG_IAD_EN             0
-#define NPCX_RESP_CFG_DEV_SIZE_EX        2
-#define NPCX_UMA_CTS_A_SIZE              3
-#define NPCX_UMA_CTS_C_SIZE              4
-#define NPCX_UMA_CTS_RD_WR               5
-#define NPCX_UMA_CTS_DEV_NUM             6
-#define NPCX_UMA_CTS_EXEC_DONE           7
-#define NPCX_UMA_ECTS_SW_CS0             0
-#define NPCX_UMA_ECTS_SW_CS1             1
-#define NPCX_UMA_ECTS_SEC_CS             2
-#define NPCX_UMA_ECTS_UMA_LOCK           3
-
-/******************************************************************************/
-/* Shared Memory (SHM) Registers */
-#define NPCX_SMC_STS                REG8(NPCX_SHM_BASE_ADDR + 0x000)
-#define NPCX_SMC_CTL                REG8(NPCX_SHM_BASE_ADDR + 0x001)
-#define NPCX_SHM_CTL                REG8(NPCX_SHM_BASE_ADDR + 0x002)
-#define NPCX_IMA_WIN_SIZE           REG8(NPCX_SHM_BASE_ADDR + 0x005)
-#define NPCX_WIN_SIZE               REG8(NPCX_SHM_BASE_ADDR + 0x007)
-#define NPCX_SHAW_SEM(win)          REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win))
-#define NPCX_IMA_SEM                REG8(NPCX_SHM_BASE_ADDR + 0x00B)
-#define NPCX_SHCFG                  REG8(NPCX_SHM_BASE_ADDR + 0x00E)
-#define NPCX_WIN_WR_PROT(win)       REG8(NPCX_SHM_BASE_ADDR + 0x010 + (win*2L))
-#define NPCX_WIN_RD_PROT(win)       REG8(NPCX_SHM_BASE_ADDR + 0x011 + (win*2L))
-#define NPCX_IMA_WR_PROT            REG8(NPCX_SHM_BASE_ADDR + 0x016)
-#define NPCX_IMA_RD_PROT            REG8(NPCX_SHM_BASE_ADDR + 0x017)
-#define NPCX_WIN_BASE(win)         REG32(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L))
-
-#define NPCX_PWIN_BASEI(win)       REG16(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L))
-#define NPCX_PWIN_SIZEI(win)       REG16(NPCX_SHM_BASE_ADDR + 0x022 + (win*4L))
-
-#define NPCX_IMA_BASE              REG32(NPCX_SHM_BASE_ADDR + 0x02C)
-#define NPCX_RST_CFG                REG8(NPCX_SHM_BASE_ADDR + 0x03A)
-#define NPCX_DP80BUF               REG16(NPCX_SHM_BASE_ADDR + 0x040)
-#define NPCX_DP80STS                REG8(NPCX_SHM_BASE_ADDR + 0x042)
-#define NPCX_DP80CTL                REG8(NPCX_SHM_BASE_ADDR + 0x044)
-#define NPCX_HOFS_STS               REG8(NPCX_SHM_BASE_ADDR + 0x048)
-#define NPCX_HOFS_CTL               REG8(NPCX_SHM_BASE_ADDR + 0x049)
-#define NPCX_COFS2                 REG16(NPCX_SHM_BASE_ADDR + 0x04A)
-#define NPCX_COFS1                 REG16(NPCX_SHM_BASE_ADDR + 0x04C)
-#define NPCX_IHOFS2                REG16(NPCX_SHM_BASE_ADDR + 0x050)
-#define NPCX_IHOFS1                REG16(NPCX_SHM_BASE_ADDR + 0x052)
-#define NPCX_SHM_VER                REG8(NPCX_SHM_BASE_ADDR + 0x07F)
-
-/* SHM register fields */
-#define NPCX_SMC_STS_HRERR               0
-#define NPCX_SMC_STS_HWERR               1
-#define NPCX_SMC_STS_HSEM1W              4
-#define NPCX_SMC_STS_HSEM2W              5
-#define NPCX_SMC_STS_SHM_ACC             6
-#define NPCX_SMC_CTL_HERR_IE             2
-#define NPCX_SMC_CTL_HSEM1_IE            3
-#define NPCX_SMC_CTL_HSEM2_IE            4
-#define NPCX_SMC_CTL_ACC_IE              5
-#define NPCX_SMC_CTL_PREF_EN             6
-#define NPCX_SMC_CTL_HOSTWAIT            7
-#define NPCX_FLASH_SIZE_STALL_HOST       6
-#define NPCX_FLASH_SIZE_RD_BURST         7
-#define NPCX_WIN_PROT_RW1L_RP            0
-#define NPCX_WIN_PROT_RW1L_WP            1
-#define NPCX_WIN_PROT_RW1H_RP            2
-#define NPCX_WIN_PROT_RW1H_WP            3
-#define NPCX_WIN_PROT_RW2L_RP            4
-#define NPCX_WIN_PROT_RW2L_WP            5
-#define NPCX_WIN_PROT_RW2H_RP            6
-#define NPCX_WIN_PROT_RW2H_WP            7
-#define NPCX_PWIN_SIZEI_RPROT            13
-#define NPCX_PWIN_SIZEI_WPROT            14
-#define NPCX_CSEM2                       6
-#define NPCX_CSEM3                       7
-#define NPCX_DP80BUF_OFFS_FIELD          FIELD(8, 3)
-#define NPCX_DP80STS_FWR                 5
-#define NPCX_DP80STS_FNE                 6
-#define NPCX_DP80STS_FOR                 7
-#define NPCX_DP80CTL_DP80EN              0
-#define NPCX_DP80CTL_SYNCEN              1
-#define NPCX_DP80CTL_RFIFO               4
-#define NPCX_DP80CTL_CIEN                5
-
-/******************************************************************************/
-/* KBC Registers */
-#define NPCX_HICTRL                       REG8(NPCX_KBC_BASE_ADDR + 0x000)
-#define NPCX_HIIRQC                       REG8(NPCX_KBC_BASE_ADDR + 0x002)
-#define NPCX_HIKMST                       REG8(NPCX_KBC_BASE_ADDR + 0x004)
-#define NPCX_HIKDO                        REG8(NPCX_KBC_BASE_ADDR + 0x006)
-#define NPCX_HIMDO                        REG8(NPCX_KBC_BASE_ADDR + 0x008)
-#define NPCX_KBCVER                       REG8(NPCX_KBC_BASE_ADDR + 0x009)
-#define NPCX_HIKMDI                       REG8(NPCX_KBC_BASE_ADDR + 0x00A)
-#define NPCX_SHIKMDI                      REG8(NPCX_KBC_BASE_ADDR + 0x00B)
-
-/* KBC register field */
-#define NPCX_HICTRL_OBFKIE               0 /* Automatic Serial IRQ1 for KBC */
-#define NPCX_HICTRL_OBFMIE               1 /* Automatic Serial IRQ12 for Mouse*/
-#define NPCX_HICTRL_OBECIE               2 /* KBC OBE interrupt enable */
-#define NPCX_HICTRL_IBFCIE               3 /* KBC IBF interrupt enable */
-#define NPCX_HICTRL_PMIHIE               4 /* Automatic Serial IRQ11 for PMC1 */
-#define NPCX_HICTRL_PMIOCIE              5 /* PMC1 OBE interrupt enable */
-#define NPCX_HICTRL_PMICIE               6 /* PMC1 IBF interrupt enable */
-#define NPCX_HICTRL_FW_OBF               7 /* Firmware control over OBF */
-
-#define NPCX_HIKMST_OBF                  0 /* KB output buffer is full */
-/******************************************************************************/
-/* PM Channel Registers */
-#define NPCX_HIPMST(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x000)
-#define NPCX_HIPMDO(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x002)
-#define NPCX_HIPMDI(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x004)
-#define NPCX_SHIPMDI(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x005)
-#define NPCX_HIPMDOC(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x006)
-#define NPCX_HIPMDOM(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x008)
-#define NPCX_HIPMDIC(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00A)
-#define NPCX_HIPMCTL(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00C)
-#define NPCX_HIPMCTL2(n)                  REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00D)
-#define NPCX_HIPMIC(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00E)
-#define NPCX_HIPMIE(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x010)
-
-/* PM Channel register field */
-
-/* NPCX_HIPMIE */
-#define NPCX_HIPMIE_SCIE                 1
-#define NPCX_HIPMIE_SMIE                 2
-
-/* NPCX_HIPMCTL */
-#define NPCX_HIPMCTL_IBFIE               0
-#define NPCX_HIPMCTL_SCIPOL              6
-
-/* NPCX_HIPMST */
-#define NPCX_HIPMST_F0                   2 /* EC_LPC_CMDR_BUSY */
-#define NPCX_HIPMST_ST0                  4 /* EC_LPC_CMDR_ACPI_BRST */
-#define NPCX_HIPMST_ST1                  5 /* EC_LPC_CMDR_SCI */
-#define NPCX_HIPMST_ST2                  6 /* EC_LPC_CMDR_SMI */
-
-/* NPCX_HIPMIC */
-#define NPCX_HIPMIC_SMIB                 1
-#define NPCX_HIPMIC_SCIB                 2
-#define NPCX_HIPMIC_SMIPOL               6
-
-/*
- * PM Channel enumeration
- */
-enum PM_CHANNEL_T {
-	PM_CHAN_1,
-	PM_CHAN_2,
-	PM_CHAN_3,
-	PM_CHAN_4
-};
-
-/******************************************************************************/
-/* SuperI/O Internal Bus (SIB) Registers */
-#define NPCX_IHIOA                       REG16(NPCX_SIB_BASE_ADDR + 0x000)
-#define NPCX_IHD                          REG8(NPCX_SIB_BASE_ADDR + 0x002)
-#define NPCX_LKSIOHA                     REG16(NPCX_SIB_BASE_ADDR + 0x004)
-#define NPCX_SIOLV                       REG16(NPCX_SIB_BASE_ADDR + 0x006)
-#define NPCX_CRSMAE                      REG16(NPCX_SIB_BASE_ADDR + 0x008)
-#define NPCX_SIBCTRL                      REG8(NPCX_SIB_BASE_ADDR + 0x00A)
-#define NPCX_C2H_VER                      REG8(NPCX_SIB_BASE_ADDR + 0x00E)
-/* SIB register fields  */
-#define NPCX_SIBCTRL_CSAE                0
-#define NPCX_SIBCTRL_CSRD                1
-#define NPCX_SIBCTRL_CSWR                2
-#define NPCX_LKSIOHA_LKCFG               0
-#define NPCX_LKSIOHA_LKHIKBD            11
-#define NPCX_CRSMAE_CFGAE                0
-#define NPCX_CRSMAE_HIKBDAE             11
-
-/******************************************************************************/
-/* Battery-Backed RAM (BBRAM) Registers */
-#define NPCX_BKUP_STS                REG8(NPCX_BBRAM_BASE_ADDR + 0x100)
-#define NPCX_BBRAM(offset)           REG8(NPCX_BBRAM_BASE_ADDR + offset)
-
-/* BBRAM register fields */
-#define NPCX_BKUP_STS_IBBR               7
-
-/******************************************************************************/
-/* Timer Watch Dog (TWD) Registers */
-#define NPCX_TWCFG                        REG8(NPCX_TWD_BASE_ADDR + 0x000)
-#define NPCX_TWCP                         REG8(NPCX_TWD_BASE_ADDR + 0x002)
-#define NPCX_TWDT0                       REG16(NPCX_TWD_BASE_ADDR + 0x004)
-#define NPCX_T0CSR                        REG8(NPCX_TWD_BASE_ADDR + 0x006)
-#define NPCX_WDCNT                        REG8(NPCX_TWD_BASE_ADDR + 0x008)
-#define NPCX_WDSDM                        REG8(NPCX_TWD_BASE_ADDR + 0x00A)
-#define NPCX_TWMT0                       REG16(NPCX_TWD_BASE_ADDR + 0x00C)
-#define NPCX_TWMWD                        REG8(NPCX_TWD_BASE_ADDR + 0x00E)
-#define NPCX_WDCP                         REG8(NPCX_TWD_BASE_ADDR + 0x010)
-
-/* TWD register fields */
-#define NPCX_TWCFG_LTWCFG                0
-#define NPCX_TWCFG_LTWCP                 1
-#define NPCX_TWCFG_LTWDT0                2
-#define NPCX_TWCFG_LWDCNT                3
-#define NPCX_TWCFG_WDCT0I                4
-#define NPCX_TWCFG_WDSDME                5
-#define NPCX_TWCFG_WDRST_MODE            6
-#define NPCX_TWCFG_WDC2POR               7
-#define NPCX_T0CSR_RST                   0
-#define NPCX_T0CSR_TC                    1
-#define NPCX_T0CSR_WDLTD                 3
-#define NPCX_T0CSR_WDRST_STS             4
-#define NPCX_T0CSR_WD_RUN                5
-#define NPCX_T0CSR_TESDIS                7
-
-/******************************************************************************/
-/* SPI Register */
-#define NPCX_SPI_DATA                    REG16(NPCX_SPI_BASE_ADDR + 0x00)
-#define NPCX_SPI_CTL1                    REG16(NPCX_SPI_BASE_ADDR + 0x02)
-#define NPCX_SPI_STAT                     REG8(NPCX_SPI_BASE_ADDR + 0x04)
-
-/* SPI register fields */
-#define NPCX_SPI_CTL1_SPIEN              0
-#define NPCX_SPI_CTL1_SNM                1
-#define NPCX_SPI_CTL1_MOD                2
-#define NPCX_SPI_CTL1_EIR                5
-#define NPCX_SPI_CTL1_EIW                6
-#define NPCX_SPI_CTL1_SCM                7
-#define NPCX_SPI_CTL1_SCIDL              8
-#define NPCX_SPI_CTL1_SCDV               9
-#define NPCX_SPI_STAT_BSY                0
-#define NPCX_SPI_STAT_RBF                1
-
-/******************************************************************************/
-/* PECI Registers */
-
-#define NPCX_PECI_CTL_STS                REG8(NPCX_PECI_BASE_ADDR + 0x000)
-#define NPCX_PECI_RD_LENGTH              REG8(NPCX_PECI_BASE_ADDR + 0x001)
-#define NPCX_PECI_ADDR                   REG8(NPCX_PECI_BASE_ADDR + 0x002)
-#define NPCX_PECI_CMD                    REG8(NPCX_PECI_BASE_ADDR + 0x003)
-#define NPCX_PECI_CTL2                   REG8(NPCX_PECI_BASE_ADDR + 0x004)
-#define NPCX_PECI_INDEX                  REG8(NPCX_PECI_BASE_ADDR + 0x005)
-#define NPCX_PECI_IDATA                  REG8(NPCX_PECI_BASE_ADDR + 0x006)
-#define NPCX_PECI_WR_LENGTH              REG8(NPCX_PECI_BASE_ADDR + 0x007)
-#define NPCX_PECI_CFG                    REG8(NPCX_PECI_BASE_ADDR + 0x009)
-#define NPCX_PECI_RATE                   REG8(NPCX_PECI_BASE_ADDR + 0x00F)
-#define NPCX_PECI_DATA_IN(i)             REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
-#define NPCX_PECI_DATA_OUT(i)            REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
-
-/* PECI register fields */
-#define NPCX_PECI_CTL_STS_START_BUSY     0
-#define NPCX_PECI_CTL_STS_DONE           1
-#define NPCX_PECI_CTL_STS_AVL_ERR        2
-#define NPCX_PECI_CTL_STS_CRC_ERR        3
-#define NPCX_PECI_CTL_STS_ABRT_ERR       4
-#define NPCX_PECI_CTL_STS_AWFCS_EN       5
-#define NPCX_PECI_CTL_STS_DONE_EN        6
-#define NPCX_ESTRPST_PECIST              0
-#define SFT_STRP_CFG_CK50                5
-
-/******************************************************************************/
-/* PWM Registers */
-#define NPCX_PRSC(n)                     REG16(NPCX_PWM_BASE_ADDR(n) + 0x000)
-#define NPCX_CTR(n)                      REG16(NPCX_PWM_BASE_ADDR(n) + 0x002)
-#define NPCX_PWMCTL(n)                    REG8(NPCX_PWM_BASE_ADDR(n) + 0x004)
-#define NPCX_DCR(n)                      REG16(NPCX_PWM_BASE_ADDR(n) + 0x006)
-#define NPCX_PWMCTLEX(n)                  REG8(NPCX_PWM_BASE_ADDR(n) + 0x00C)
-
-/* PWM register fields */
-#define NPCX_PWMCTL_INVP                 0
-#define NPCX_PWMCTL_CKSEL                1
-#define NPCX_PWMCTL_HB_DC_CTL_FIELD      FIELD(2, 2)
-#define NPCX_PWMCTL_PWR                  7
-#define NPCX_PWMCTLEX_FCK_SEL_FIELD      FIELD(4, 2)
-#define NPCX_PWMCTLEX_OD_OUT             7
-/******************************************************************************/
-/* MFT Registers */
-#define NPCX_TCNT1(n)                    REG16(NPCX_MFT_BASE_ADDR(n) + 0x000)
-#define NPCX_TCRA(n)                     REG16(NPCX_MFT_BASE_ADDR(n) + 0x002)
-#define NPCX_TCRB(n)                     REG16(NPCX_MFT_BASE_ADDR(n) + 0x004)
-#define NPCX_TCNT2(n)                    REG16(NPCX_MFT_BASE_ADDR(n) + 0x006)
-#define NPCX_TPRSC(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x008)
-#define NPCX_TCKC(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x00A)
-#define NPCX_TMCTRL(n)                    REG8(NPCX_MFT_BASE_ADDR(n) + 0x00C)
-#define NPCX_TECTRL(n)                    REG8(NPCX_MFT_BASE_ADDR(n) + 0x00E)
-#define NPCX_TECLR(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x010)
-#define NPCX_TIEN(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x012)
-#define NPCX_TWUEN(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x01A)
-#define NPCX_TCFG(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x01C)
-
-/* MFT register fields */
-#define NPCX_TMCTRL_MDSEL_FIELD          FIELD(0, 3)
-#define NPCX_TCKC_LOW_PWR                7
-#define NPCX_TCKC_PLS_ACC_CLK            6
-#define NPCX_TCKC_C1CSEL_FIELD           FIELD(0, 3)
-#define NPCX_TCKC_C2CSEL_FIELD           FIELD(3, 3)
-#define NPCX_TMCTRL_TAEN                 5
-#define NPCX_TMCTRL_TBEN                 6
-#define NPCX_TMCTRL_TAEDG                3
-#define NPCX_TMCTRL_TBEDG                4
-#define NPCX_TCFG_TADBEN                 6
-#define NPCX_TCFG_TBDBEN                 7
-#define NPCX_TECTRL_TAPND                0
-#define NPCX_TECTRL_TBPND                1
-#define NPCX_TECTRL_TCPND                2
-#define NPCX_TECTRL_TDPND                3
-#define NPCX_TECLR_TACLR                 0
-#define NPCX_TECLR_TBCLR                 1
-#define NPCX_TECLR_TCCLR                 2
-#define NPCX_TECLR_TDCLR                 3
-#define NPCX_TIEN_TAIEN                  0
-#define NPCX_TIEN_TBIEN                  1
-#define NPCX_TIEN_TCIEN                  2
-#define NPCX_TIEN_TDIEN                  3
-#define NPCX_TWUEN_TAWEN                 0
-#define NPCX_TWUEN_TBWEN                 1
-#define NPCX_TWUEN_TCWEN                 2
-#define NPCX_TWUEN_TDWEN                 3
-/******************************************************************************/
-/* ITIM16/32 Define */
-#define ITIM_INT(module)               CONCAT2(NPCX_IRQ_, module)
-
-/* ITIM16/32 register */
-#define NPCX_ITPRE(n)                    REG8(NPCX_ITIM_BASE_ADDR(n) + 0x001)
-#define NPCX_ITCTS(n)                    REG8(NPCX_ITIM_BASE_ADDR(n) + 0x004)
-
-/* ITIM16 register fields */
-#define NPCX_ITCTS_TO_STS                0
-#define NPCX_ITCTS_TO_IE                 2
-#define NPCX_ITCTS_TO_WUE                3
-#define NPCX_ITCTS_CKSEL                 4
-#define NPCX_ITCTS_ITEN                  7
-
-/******************************************************************************/
-/* Serial Host Interface (SHI) Registers */
-#define NPCX_SHICFG1                      REG8(NPCX_SHI_BASE_ADDR + 0x001)
-#define NPCX_SHICFG2                      REG8(NPCX_SHI_BASE_ADDR + 0x002)
-#define NPCX_I2CADDR1                     REG8(NPCX_SHI_BASE_ADDR + 0x003)
-#define NPCX_I2CADDR2                     REG8(NPCX_SHI_BASE_ADDR + 0x004)
-#define NPCX_EVENABLE                     REG8(NPCX_SHI_BASE_ADDR + 0x005)
-#define NPCX_EVSTAT                       REG8(NPCX_SHI_BASE_ADDR + 0x006)
-#define NPCX_SHI_CAPABILITY               REG8(NPCX_SHI_BASE_ADDR + 0x007)
-#define NPCX_STATUS                       REG8(NPCX_SHI_BASE_ADDR + 0x008)
-#define NPCX_IBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00A)
-#define NPCX_OBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00B)
-
-/* SHI register fields */
-#define NPCX_SHICFG1_EN                  0
-#define NPCX_SHICFG1_MODE                1
-#define NPCX_SHICFG1_WEN                 2
-#define NPCX_SHICFG1_AUTIBF              3
-#define NPCX_SHICFG1_AUTOBE              4
-#define NPCX_SHICFG1_DAS                 5
-#define NPCX_SHICFG1_CPOL                6
-#define NPCX_SHICFG1_IWRAP               7
-#define NPCX_SHICFG2_SIMUL               0
-#define NPCX_SHICFG2_BUSY                1
-#define NPCX_SHICFG2_ONESHOT             2
-#define NPCX_SHICFG2_SLWU                3
-#define NPCX_SHICFG2_REEN                4
-#define NPCX_SHICFG2_RESTART             5
-#define NPCX_SHICFG2_REEVEN              6
-#define NPCX_EVENABLE_OBEEN              0
-#define NPCX_EVENABLE_OBHEEN             1
-#define NPCX_EVENABLE_IBFEN              2
-#define NPCX_EVENABLE_IBHFEN             3
-#define NPCX_EVENABLE_EOREN              4
-#define NPCX_EVENABLE_EOWEN              5
-#define NPCX_EVENABLE_STSREN             6
-#define NPCX_EVENABLE_IBOREN             7
-#define NPCX_EVSTAT_OBE                  0
-#define NPCX_EVSTAT_OBHE                 1
-#define NPCX_EVSTAT_IBF                  2
-#define NPCX_EVSTAT_IBHF                 3
-#define NPCX_EVSTAT_EOR                  4
-#define NPCX_EVSTAT_EOW                  5
-#define NPCX_EVSTAT_STSR                 6
-#define NPCX_EVSTAT_IBOR                 7
-#define NPCX_STATUS_OBES                 6
-#define NPCX_STATUS_IBFS                 7
-
-/******************************************************************************/
-/* Monotonic Counter (MTC) Registers */
-#define NPCX_TTC                         REG32(NPCX_MTC_BASE_ADDR + 0x000)
-#define NPCX_WTC                         REG32(NPCX_MTC_BASE_ADDR + 0x004)
-#define NPCX_MTCTST                       REG8(NPCX_MTC_BASE_ADDR + 0x008)
-#define NPCX_MTCVER                       REG8(NPCX_MTC_BASE_ADDR + 0x00C)
-
-/* MTC register fields */
-#define NPCX_WTC_PTO                     30
-#define NPCX_WTC_WIE                     31
-
-/******************************************************************************/
-/* Low Power RAM definitions */
-#define NPCX_LPRAM_CTRL                  REG32(0x40001044)
-
-/******************************************************************************/
-/*  eSPI Registers */
-#define NPCX_ESPIID                 REG32(NPCX_ESPI_BASE_ADDR + 0X00)
-#define NPCX_ESPICFG                REG32(NPCX_ESPI_BASE_ADDR + 0X04)
-#define NPCX_ESPISTS                REG32(NPCX_ESPI_BASE_ADDR + 0X08)
-#define NPCX_ESPIIE                 REG32(NPCX_ESPI_BASE_ADDR + 0X0C)
-#define NPCX_ESPIWE                 REG32(NPCX_ESPI_BASE_ADDR + 0X10)
-#define NPCX_VWREGIDX               REG32(NPCX_ESPI_BASE_ADDR + 0X14)
-#define NPCX_VWREGDATA              REG32(NPCX_ESPI_BASE_ADDR + 0X18)
-#define NPCX_OOBCTL                 REG32(NPCX_ESPI_BASE_ADDR + 0X24)
-#define NPCX_FLASHRXRDHEAD          REG32(NPCX_ESPI_BASE_ADDR + 0X28)
-#define NPCX_FLASHTXWRHEAD          REG32(NPCX_ESPI_BASE_ADDR + 0X2C)
-#define NPCX_FLASHCFG               REG32(NPCX_ESPI_BASE_ADDR + 0X34)
-#define NPCX_FLASHCTL               REG32(NPCX_ESPI_BASE_ADDR + 0X38)
-#define NPCX_ESPIERR                REG32(NPCX_ESPI_BASE_ADDR + 0X3C)
-
-/* eSPI Virtual Wire channel registers */
-#define NPCX_VWEVSM(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4*(n)))
-#define NPCX_VWEVMS(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x140 + (4*(n)))
-#define NPCX_VWCTL                  REG32(NPCX_ESPI_BASE_ADDR + 0x2FC)
-
-/* eSPI register fields */
-#define NPCX_ESPICFG_PCHANEN             0
-#define NPCX_ESPICFG_VWCHANEN            1
-#define NPCX_ESPICFG_OOBCHANEN           2
-#define NPCX_ESPICFG_FLASHCHANEN         3
-#define NPCX_ESPICFG_HPCHANEN            4
-#define NPCX_ESPICFG_HVWCHANEN           5
-#define NPCX_ESPICFG_HOOBCHANEN          6
-#define NPCX_ESPICFG_HFLASHCHANEN        7
-#define NPCX_ESPICFG_IOMODE_FIELD        FIELD(8, 2)
-#define NPCX_ESPICFG_MAXFREQ_FIELD       FIELD(10, 3)
-#define NPCX_ESPICFG_OPFREQ_FIELD        FIELD(17, 3)
-#define NPCX_ESPICFG_IOMODESEL_FIELD     FIELD(20, 2)
-#define NPCX_ESPICFG_ALERT_MODE          22
-#define NPCX_ESPICFG_CRC_CHK             23
-#define NPCX_ESPICFG_PCCHN_SUPP          24
-#define NPCX_ESPICFG_VWCHN_SUPP          25
-#define NPCX_ESPICFG_OOBCHN_SUPP         26
-#define NPCX_ESPICFG_FLASHCHN_SUPP       27
-#define NPCX_ESPIERR_INVCMD              0 /* Invalid Command Type */
-#define NPCX_ESPIERR_INVCYC              1 /* Invalid Cycle Type */
-#define NPCX_ESPIERR_CRCERR              2 /* Transaction CRC Error */
-#define NPCX_ESPIERR_ABCOMP              3 /* Abnormal Completion */
-#define NPCX_ESPIERR_PROTERR             4 /* Protocol Error */
-#define NPCX_ESPIERR_BADSIZE             5 /* Bad Size */
-#define NPCX_ESPIERR_NPBADALN            6 /* NPPC Bad Address Alignment */
-#define NPCX_ESPIERR_PCBADALN            7 /* PPC Bad Address Alignment */
-#define NPCX_ESPIERR_UNCMD               9 /* Unsupported Command */
-#define NPCX_ESPIERR_EXTRACYC            10 /* Extra eSPI Clock Cycles */
-#define NPCX_ESPIERR_VWERR               11 /* Virtual Channel Access Error */
-#define NPCX_ESPIERR_UNPBM               14 /* Unsuccessful Bus Completion */
-#define NPCX_ESPIERR_UNFLASH             15 /* Unsuccessful Flash Completion */
-#define NPCX_ESPIIE_IBRSTIE              0
-#define NPCX_ESPIIE_CFGUPDIE             1
-#define NPCX_ESPIIE_BERRIE               2
-#define NPCX_ESPIIE_OOBRXIE              3
-#define NPCX_ESPIIE_FLASHRXIE            4
-#define NPCX_ESPIIE_SFLASHRDIE           5
-#define NPCX_ESPIIE_PERACCIE             6
-#define NPCX_ESPIIE_DFRDIE               7
-#define NPCX_ESPIIE_VWUPDIE              8
-#define NPCX_ESPIIE_ESPIRSTIE            9
-#define NPCX_ESPIIE_PLTRSTIE             10
-#define NPCX_ESPIIE_AMERRIE              15
-#define NPCX_ESPIIE_AMDONEIE             16
-#define NPCX_ESPIWE_IBRSTWE              0
-#define NPCX_ESPIWE_CFGUPDWE             1
-#define NPCX_ESPIWE_BERRWE               2
-#define NPCX_ESPIWE_OOBRXWE              3
-#define NPCX_ESPIWE_FLASHRXWE            4
-#define NPCX_ESPIWE_PERACCWE             6
-#define NPCX_ESPIWE_DFRDWE               7
-#define NPCX_ESPIWE_VWUPDWE              8
-#define NPCX_ESPIWE_ESPIRSTWE            9
-#define NPCX_ESPISTS_IBRST               0
-#define NPCX_ESPISTS_CFGUPD              1
-#define NPCX_ESPISTS_BERR                2
-#define NPCX_ESPISTS_OOBRX               3
-#define NPCX_ESPISTS_FLASHRX             4
-#define NPCX_ESPISTS_SFLASHRD            5
-#define NPCX_ESPISTS_PERACC              6
-#define NPCX_ESPISTS_DFRD                7
-#define NPCX_ESPISTS_VWUPD               8
-#define NPCX_ESPISTS_ESPIRST             9
-#define NPCX_ESPISTS_PLTRST              10
-#define NPCX_ESPISTS_AMERR               15
-#define NPCX_ESPISTS_AMDONE              16
-/* eSPI Virtual Wire channel register fields */
-#define NPCX_VWEVSM_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVMS_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVSM_VALID                FIELD(4, 4)
-#define NPCX_VWEVMS_VALID                FIELD(4, 4)
-
-/* Macro functions for eSPI CFG & IE */
-#define IS_PERIPHERAL_CHAN_ENABLE(ch)    IS_BIT_SET(NPCX_ESPICFG, ch)
-#define IS_HOST_CHAN_EN(ch)              IS_BIT_SET(NPCX_ESPICFG, (ch+4))
-#define ENABLE_ESPI_CHAN(ch)             SET_BIT(NPCX_ESPICFG, ch)
-#define DISABLE_ESPI_CHAN(ch)            CLEAR_BIT(NPCX_ESPICFG, ch)
-/* ESPI Peripheral Channel Support Definitions */
-#define ESPI_SUPP_CH_PC                  BIT(NPCX_ESPICFG_PCCHN_SUPP)
-#define ESPI_SUPP_CH_VM                  BIT(NPCX_ESPICFG_VWCHN_SUPP)
-#define ESPI_SUPP_CH_OOB                 BIT(NPCX_ESPICFG_OOBCHN_SUPP)
-#define ESPI_SUPP_CH_FLASH               BIT(NPCX_ESPICFG_FLASHCHN_SUPP)
-#define ESPI_SUPP_CH_ALL                 (ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | \
-					  ESPI_SUPP_CH_OOB | ESPI_SUPP_CH_FLASH)
-/* ESPI Interrupts Enable Definitions */
-#define ESPIIE_IBRST                     BIT(NPCX_ESPIIE_IBRSTIE)
-#define ESPIIE_CFGUPD                    BIT(NPCX_ESPIIE_CFGUPDIE)
-#define ESPIIE_BERR                      BIT(NPCX_ESPIIE_BERRIE)
-#define ESPIIE_OOBRX                     BIT(NPCX_ESPIIE_OOBRXIE)
-#define ESPIIE_FLASHRX                   BIT(NPCX_ESPIIE_FLASHRXIE)
-#define ESPIIE_SFLASHRD                  BIT(NPCX_ESPIIE_SFLASHRDIE)
-#define ESPIIE_PERACC                    BIT(NPCX_ESPIIE_PERACCIE)
-#define ESPIIE_DFRD                      BIT(NPCX_ESPIIE_DFRDIE)
-#define ESPIIE_VWUPD                     BIT(NPCX_ESPIIE_VWUPDIE)
-#define ESPIIE_ESPIRST                   BIT(NPCX_ESPIIE_ESPIRSTIE)
-#define ESPIIE_PLTRST                    BIT(NPCX_ESPIIE_PLTRSTIE)
-#define ESPIIE_AMERR                     BIT(NPCX_ESPIIE_AMERRIE)
-#define ESPIIE_AMDONE                    BIT(NPCX_ESPIIE_AMDONEIE)
-/* eSPI Interrupts for VW */
-#define ESPIIE_VW                        (ESPIIE_VWUPD | ESPIIE_PLTRST)
-/* eSPI Interrupts for Generic */
-#define ESPIIE_GENERIC                   (ESPIIE_IBRST | ESPIIE_CFGUPD | \
-					  ESPIIE_BERR | ESPIIE_ESPIRST)
-/* ESPI Wake-up Enable Definitions */
-#define ESPIWE_IBRST                     BIT(NPCX_ESPIWE_IBRSTWE)
-#define ESPIWE_CFGUPD                    BIT(NPCX_ESPIWE_CFGUPDWE)
-#define ESPIWE_BERR                      BIT(NPCX_ESPIWE_BERRWE)
-#define ESPIWE_OOBRX                     BIT(NPCX_ESPIWE_OOBRXWE)
-#define ESPIWE_FLASHRX                   BIT(NPCX_ESPIWE_FLASHRXWE)
-#define ESPIWE_PERACC                    BIT(NPCX_ESPIWE_PERACCWE)
-#define ESPIWE_DFRD                      BIT(NPCX_ESPIWE_DFRDWE)
-#define ESPIWE_VWUPD                     BIT(NPCX_ESPIWE_VWUPDWE)
-#define ESPIWE_ESPIRST                   BIT(NPCX_ESPIWE_ESPIRSTWE)
-/* eSPI  Wake-up enable for VW */
-#define ESPIWE_VW                        ESPIWE_VWUPD
-/* eSPI  Wake-up enable for Generic */
-#define ESPIWE_GENERIC                   (ESPIWE_IBRST | ESPIWE_CFGUPD | \
-					  ESPIWE_BERR)
-/* Macro functions for eSPI VW */
-#define ESPI_VWEVMS_NUM                  12
-#define ESPI_VWEVSM_NUM                  10
-#define ESPI_VW_IDX_WIRE_NUM             4
-/* Determine Virtual Wire type */
-#define VM_TYPE(i)              ((i >= 0   && i <=  1) ? ESPI_VW_TYPE_INT_EV : \
-				 (i >= 2   && i <=  7) ? ESPI_VW_TYPE_SYS_EV : \
-				 (i >= 64  && i <= 127) ? ESPI_VW_TYPE_PLT : \
-				 (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \
-							ESPI_VW_TYPE_NONE)
-
-/* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_INX(i)                ((i<<8)  & 0x00007F00)
-#define VWEVMS_INX_EN(n)             ((n<<15) & 0x00008000)
-#define VWEVMS_PLTRST_EN(p)          ((p<<17) & 0x00020000)
-#define VWEVMS_INT_EN(e)             ((e<<18) & 0x00040000)
-#define VWEVMS_ESPIRST_EN(r)         ((r<<19) & 0x00080000)
-#define VWEVMS_FIELD(i, n, p, e, r)  (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | \
-				VWEVMS_PLTRST_EN(p) | VWEVMS_INTWK_EN(e) | \
-				VWEVMS_ESPIRST_EN(r))
-#define VWEVMS_IDX_GET(reg)          (((reg & 0x00007F00)>>8))
-
-/* Bit field manipulation for VWEVSM Value */
-#define VWEVSM_VALID_N(v)            ((v<<4)  & 0x000000F0)
-#define VWEVSM_INX(i)                ((i<<8)  & 0x00007F00)
-#define VWEVSM_INX_EN(n)             ((n<<15) & 0x00008000)
-#define VWEVSM_DIRTY(d)              ((d<<16) & 0x00010000)
-#define VWEVSM_PLTRST_EN(p)          ((p<<17) & 0x00020000)
-#define VWEVSM_CDRST_EN(c)           ((c<<19) & 0x00080000)
-#define VWEVSM_FIELD(i, n, v, p, c)  (VWEVSM_INX(i) | VWEVSM_INX_EN(n) | \
-				VWEVSM_VALID_N(v) | VWEVSM_PLTRST_EN(p) |\
-				VWEVSM_CDRST_EN(c))
-#define VWEVSM_IDX_GET(reg)          (((reg & 0x00007F00)>>8))
-
-/* define macro to handle SMI/SCI Virtual Wire */
-/* Read SMI VWire status from VWEVSM(offset 2) register. */
-#define SMI_STATUS_MASK    ((uint8_t) (NPCX_VWEVSM(2) & 0x00000002))
-/*
- * Read SCI VWire status from VWEVSM(offset 2) register.
- * Left shift 2 to meet the SCIB field in HIPMIC register.
- */
-#define SCI_STATUS_MASK    (((uint8_t) (NPCX_VWEVSM(2) & 0x00000001)) << 2)
-#define SCIB_MASK(v)       (v << NPCX_HIPMIC_SCIB)
-#define SMIB_MASK(v)       (v << NPCX_HIPMIC_SMIB)
-#define NPCX_VW_SCI(level)  ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \
-				SMI_STATUS_MASK | SCIB_MASK(level))
-#define NPCX_VW_SMI(level)  ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \
-				SCI_STATUS_MASK | SMIB_MASK(level))
-
-/* eSPI enumeration */
-/* eSPI channels */
-enum {
-	NPCX_ESPI_CH_PC = 0,
-	NPCX_ESPI_CH_VW,
-	NPCX_ESPI_CH_OOB,
-	NPCX_ESPI_CH_FLASH,
-	NPCX_ESPI_CH_COUNT,
-	NPCX_ESPI_CH_GENERIC,
-	NPCX_ESPI_CH_NONE = 0xFF
-};
-
-/* eSPI IO modes */
-enum {
-	NPCX_ESPI_IO_MODE_SINGLE = 0,
-	NPCX_ESPI_IO_MODE_DUAL   = 1,
-	NPCX_ESPI_IO_MODE_QUAD   = 2,
-	NPCX_ESPI_IO_MODE_ALL    = 3,
-	NPCX_ESPI_IO_MODE_NONE   = 0xFF
-};
-
-/* eSPI IO mode selected */
-enum {
-	NPCX_ESPI_IO_MODE_SEL_SINGLE = 0,
-	NPCX_ESPI_IO_MODE_SEL_DUAL   = 1,
-	NPCX_ESPI_IO_MODE_SEL_QUARD  = 2,
-	NPCX_ESPI_IO_MODE_SEL_NONE   = 0xFF
-};
-
-/* VW types */
-enum {
-	ESPI_VW_TYPE_INT_EV,            /* Interrupt event */
-	ESPI_VW_TYPE_SYS_EV,            /* System Event */
-	ESPI_VW_TYPE_PLT,               /* Platform specific */
-	ESPI_VW_TYPE_GPIO,              /* General Purpose I/O Expander */
-	ESPI_VW_TYPE_NUM,
-	ESPI_VW_TYPE_NONE = 0xFF
-};
-
-/******************************************************************************/
-/* GDMA (General DMA) Registers */
-#define NPCX_GDMA_CTL                    REG32(NPCX_GDMA_BASE_ADDR + 0x000)
-#define NPCX_GDMA_SRCB                   REG32(NPCX_GDMA_BASE_ADDR + 0x004)
-#define NPCX_GDMA_DSTB                   REG32(NPCX_GDMA_BASE_ADDR + 0x008)
-#define NPCX_GDMA_TCNT                   REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
-#define NPCX_GDMA_CSRC                   REG32(NPCX_GDMA_BASE_ADDR + 0x010)
-#define NPCX_GDMA_CDST                   REG32(NPCX_GDMA_BASE_ADDR + 0x014)
-#define NPCX_GDMA_CTCNT                  REG32(NPCX_GDMA_BASE_ADDR + 0x018)
-
-
-/******************************************************************************/
-/* GDMA register fields */
-#define NPCX_GDMA_CTL_GDMAEN                         0
-#define NPCX_GDMA_CTL_GDMAMS                         FIELD(2,   2)
-#define NPCX_GDMA_CTL_DADIR                          4
-#define NPCX_GDMA_CTL_SADIR                          5
-#define NPCX_GDMA_CTL_SAFIX                          7
-#define NPCX_GDMA_CTL_SIEN                           8
-#define NPCX_GDMA_CTL_BME                            9
-#define NPCX_GDMA_CTL_SBMS                           11
-#define NPCX_GDMA_CTL_TWS                            FIELD(12,  2)
-#define NPCX_GDMA_CTL_DM                             15
-#define NPCX_GDMA_CTL_SOFTREQ                        16
-#define NPCX_GDMA_CTL_TC                             18
-#define NPCX_GDMA_CTL_GDMAERR                        20
-#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE   26
-
-/******************************************************************************/
-/* Nuvoton internal used only registers */
-#define NPCX_INTERNAL_CTRL1               REG8(0x400DB000)
-#define NPCX_INTERNAL_CTRL2               REG8(0x400DD000)
-#define NPCX_INTERNAL_CTRL3               REG8(0x400DF000)
-
-/******************************************************************************/
-/* Optional M4 Registers */
-#define CPU_DHCSR                        REG32(0xE000EDF0)
-#define CPU_MPU_CTRL                     REG32(0xE000ED94)
-#define CPU_MPU_RNR                      REG32(0xE000ED98)
-#define CPU_MPU_RBAR                     REG32(0xE000ED9C)
-#define CPU_MPU_RASR                     REG32(0xE000EDA0)
-
-
-/******************************************************************************/
-/* Flash Utiltiy definition */
-/*
- *  Flash commands for the W25Q16CV SPI flash
- */
-#define CMD_READ_ID                      0x9F
-#define CMD_READ_MAN_DEV_ID              0x90
-#define CMD_WRITE_EN                     0x06
-#define CMD_WRITE_STATUS                 0x50
-#define CMD_READ_STATUS_REG              0x05
-#define CMD_READ_STATUS_REG2             0x35
-#define CMD_WRITE_STATUS_REG             0x01
-#define CMD_FLASH_PROGRAM                0x02
-#define CMD_SECTOR_ERASE                 0x20
-#define CMD_BLOCK_32K_ERASE              0x52
-#define CMD_BLOCK_64K_ERASE              0xd8
-#define CMD_PROGRAM_UINT_SIZE            0x08
-#define CMD_PAGE_SIZE                    0x00
-#define CMD_READ_ID_TYPE                 0x47
-#define CMD_FAST_READ                    0x0B
-
-/*
- * Status registers for the W25Q16CV SPI flash
- */
-#define SPI_FLASH_SR2_SUS               BIT(7)
-#define SPI_FLASH_SR2_CMP               BIT(6)
-#define SPI_FLASH_SR2_LB3               BIT(5)
-#define SPI_FLASH_SR2_LB2               BIT(4)
-#define SPI_FLASH_SR2_LB1               BIT(3)
-#define SPI_FLASH_SR2_QE                BIT(1)
-#define SPI_FLASH_SR2_SRP1              BIT(0)
-#define SPI_FLASH_SR1_SRP0              BIT(7)
-#define SPI_FLASH_SR1_SEC               BIT(6)
-#define SPI_FLASH_SR1_TB                BIT(5)
-#define SPI_FLASH_SR1_BP2               BIT(4)
-#define SPI_FLASH_SR1_BP1               BIT(3)
-#define SPI_FLASH_SR1_BP0               BIT(2)
-#define SPI_FLASH_SR1_WEL               BIT(1)
-#define SPI_FLASH_SR1_BUSY              BIT(0)
-
-
-/* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */
-#define FIU_CHIP_SELECT		0
-/* Create UMA control mask */
-#define MASK(bit)       (0x1 << (bit))
-#define A_SIZE          0x03	/* 0: No ADR field 1: 3-bytes ADR field */
-#define C_SIZE          0x04	/* 0: 1-Byte CMD field 1:No CMD field */
-#define RD_WR           0x05	/* 0: Read 1: Write */
-#define DEV_NUM         0x06	/* 0: PVT is used 1: SHD is used */
-#define EXEC_DONE       0x07
-#define D_SIZE_1        0x01
-#define D_SIZE_2        0x02
-#define D_SIZE_3        0x03
-#define D_SIZE_4        0x04
-#define FLASH_SEL       MASK(DEV_NUM)
-
-#define MASK_CMD_ONLY   (MASK(EXEC_DONE) | FLASH_SEL)
-#define MASK_CMD_ADR    (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
-#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)  \
-			|MASK(A_SIZE) | D_SIZE_1)
-#define MASK_RD_1BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
-#define MASK_RD_2BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
-#define MASK_RD_3BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
-#define MASK_RD_4BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
-#define MASK_CMD_RD_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
-#define MASK_CMD_RD_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
-#define MASK_CMD_RD_3BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
-#define MASK_CMD_RD_4BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
-#define MASK_CMD_WR_ONLY        (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
-#define MASK_CMD_WR_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_1)
-#define MASK_CMD_WR_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_2)
-#define MASK_CMD_WR_ADR         (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(A_SIZE))
-
-/******************************************************************************/
-/* APM (Audio Processing Module) Registers */
-#define NPCX_APM_SR                 REG8(NPCX_APM_BASE_ADDR + 0x000)
-#define NPCX_APM_SR2                REG8(NPCX_APM_BASE_ADDR + 0x004)
-#define NPCX_APM_ICR                REG8(NPCX_APM_BASE_ADDR + 0x008)
-#define NPCX_APM_IMR                REG8(NPCX_APM_BASE_ADDR + 0x00C)
-#define NPCX_APM_IFR                REG8(NPCX_APM_BASE_ADDR + 0x010)
-#define NPCX_APM_CR_APM             REG8(NPCX_APM_BASE_ADDR + 0x014)
-#define NPCX_APM_CR_CK              REG8(NPCX_APM_BASE_ADDR + 0x018)
-#define NPCX_APM_AICR_ADC           REG8(NPCX_APM_BASE_ADDR + 0x01C)
-#define NPCX_APM_FCR_ADC            REG8(NPCX_APM_BASE_ADDR + 0x020)
-#define NPCX_APM_CR_DMIC            REG8(NPCX_APM_BASE_ADDR + 0x02C)
-#define NPCX_APM_CR_ADC             REG8(NPCX_APM_BASE_ADDR + 0x030)
-#define NPCX_APM_CR_MIX             REG8(NPCX_APM_BASE_ADDR + 0x034)
-#define NPCX_APM_DR_MIX             REG8(NPCX_APM_BASE_ADDR + 0x038)
-#define NPCX_APM_GCR_ADCL           REG8(NPCX_APM_BASE_ADDR + 0x03C)
-#define NPCX_APM_GCR_ADCR           REG8(NPCX_APM_BASE_ADDR + 0x040)
-#define NPCX_APM_GCR_MIXADCL        REG8(NPCX_APM_BASE_ADDR + 0x044)
-#define NPCX_APM_GCR_MIXADCR        REG8(NPCX_APM_BASE_ADDR + 0x048)
-#define NPCX_APM_CR_ADC_AGC         REG8(NPCX_APM_BASE_ADDR + 0x04C)
-#define NPCX_APM_DR_ADC_AGC         REG8(NPCX_APM_BASE_ADDR + 0x050)
-#define NPCX_APM_SR_ADC_AGCDGL      REG8(NPCX_APM_BASE_ADDR + 0x054)
-#define NPCX_APM_SR_ADC_AGCDGR      REG8(NPCX_APM_BASE_ADDR + 0x058)
-#define NPCX_APM_CR_VAD             REG8(NPCX_APM_BASE_ADDR + 0x05C)
-#define NPCX_APM_DR_VAD             REG8(NPCX_APM_BASE_ADDR + 0x060)
-#define NPCX_APM_CR_VAD_CMD         REG8(NPCX_APM_BASE_ADDR + 0x064)
-#define NPCX_APM_CR_TR              REG8(NPCX_APM_BASE_ADDR + 0x068)
-#define NPCX_APM_DR_TR              REG8(NPCX_APM_BASE_ADDR + 0x06C)
-#define NPCX_APM_SR_TR1             REG8(NPCX_APM_BASE_ADDR + 0x070)
-#define NPCX_APM_SR_TR_SRCADC       REG8(NPCX_APM_BASE_ADDR + 0x074)
-
-/******************************************************************************/
-/* APM register fields */
-#define NPCX_APM_SR_IRQ_PEND                    6
-#define NPCX_APM_SR2_SMUTEIP                    6
-#define NPCX_APM_ICR_INTR_MODE                  FIELD(6, 2)
-#define NPCX_APM_IMR_VAD_DTC_MASK               6
-#define NPCX_APM_IFR_VAD_DTC                    6
-#define NPCX_APM_CR_APM_PD                      0
-#define NPCX_APM_CR_APM_AGC_DIS                 FIELD(1, 2)
-#define NPCX_APM_CR_CK_MCLK_FREQ                FIELD(0, 2)
-#define NPCX_APM_AICR_ADC_ADC_AUDIOIF           FIELD(0, 2)
-#define NPCX_APM_AICR_ADC_PD_AICR_ADC           4
-#define NPCX_APM_AICR_ADC_ADC_ADWL              FIELD(6, 2)
-#define NPCX_APM_FCR_ADC_ADC_FREQ               FIELD(0, 4)
-#define NPCX_APM_FCR_ADC_ADC_WNF                FIELD(4, 2)
-#define NPCX_APM_FCR_ADC_ADC_HPF                6
-#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT     FIELD(0, 2)
-#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT      FIELD(2, 2)
-#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE          FIELD(4, 3)
-#define NPCX_APM_CR_DMIC_PD_DMIC                7
-#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE           7
-#define NPCX_APM_CR_MIX_MIX_ADD                 FIELD(0, 6)
-#define NPCX_APM_CR_MIX_MIX_LOAD                6
-#define NPCX_APM_DR_MIX_MIX_DATA                FIELD(0, 8)
-#define NPCX_APM_MIX_2_AIADCR_SEL               FIELD(4, 2)
-#define NPCX_APM_MIX_2_AIADCL_SEL               FIELD(6, 2)
-#define NPCX_APM_GCR_ADCL_GIDL                  FIELD(0, 6)
-#define NPCX_APM_GCR_ADCL_LRGID                 7
-#define NPCX_APM_GCR_ADCR_GIDR                  FIELD(0, 6)
-#define NPCX_APM_GCR_MIXADCL_GIMIXL             FIELD(0, 6)
-#define NPCX_APM_GCR_MIXADCR_GIMIXR             FIELD(0, 6)
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD         FIELD(0, 6)
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD        6
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN          7
-#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA        FIELD(0, 8)
-#define NPCX_ADC_AGC_0_AGC_TARGET               FIELD(2, 4)
-#define NPCX_ADC_AGC_0_AGC_STEREO               6
-#define NPCX_ADC_AGC_1_HOLD                     FIELD(0, 4)
-#define NPCX_ADC_AGC_1_NG_THR                   FIELD(4, 3)
-#define NPCX_ADC_AGC_1_NG_EN                    7
-#define NPCX_ADC_AGC_2_DCY                      FIELD(0, 4)
-#define NPCX_ADC_AGC_2_ATK                      FIELD(4, 4)
-#define NPCX_ADC_AGC_3_AGC_MAX                  FIELD(0, 5)
-#define NPCX_ADC_AGC_4_AGC_MIN                  FIELD(0, 5)
-#define NPCX_APM_CR_VAD_VAD_ADD                 FIELD(0, 6)
-#define NPCX_APM_CR_VAD_VAD_LOAD                6
-#define NPCX_APM_CR_VAD_VAD_EN                  7
-#define NPCX_APM_DR_VAD_VAD_DATA                FIELD(0, 8)
-#define NPCX_APM_CR_VAD_CMD_VAD_RESTART         0
-#define NPCX_APM_CR_TR_FAST_ON                  7
-#define NPCX_VAD_0_VAD_INSEL                    FIELD(0, 2)
-#define NPCX_VAD_0_VAD_DMIC_FREQ                FIELD(2, 3)
-#define NPCX_VAD_0_VAD_ADC_WAKEUP               5
-#define NPCX_VAD_0_ZCD_EN                       6
-#define NPCX_VAD_1_VAD_POWER_SENS               FIELD(0, 5)
-#define NPCX_APM_CONTROL_ADD                    FIELD(0, 6)
-#define NPCX_APM_CONTROL_LOAD                   6
-
-/******************************************************************************/
-/* FMUL2 (Frequency Multiplier Module 2) Registers */
-#define NPCX_FMUL2_FM2CTRL          REG8(NPCX_FMUL2_BASE_ADDR + 0x000)
-#define NPCX_FMUL2_FM2ML            REG8(NPCX_FMUL2_BASE_ADDR + 0x002)
-#define NPCX_FMUL2_FM2MH            REG8(NPCX_FMUL2_BASE_ADDR + 0x004)
-#define NPCX_FMUL2_FM2N             REG8(NPCX_FMUL2_BASE_ADDR + 0x006)
-#define NPCX_FMUL2_FM2P             REG8(NPCX_FMUL2_BASE_ADDR + 0x008)
-#define NPCX_FMUL2_FM2_VER          REG8(NPCX_FMUL2_BASE_ADDR + 0x00A)
-
-/******************************************************************************/
-/* FMUL2 register fields */
-#define NPCX_FMUL2_FM2CTRL_LOAD2                0
-#define NPCX_FMUL2_FM2CTRL_LOCK2                2
-#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS            5
-#define NPCX_FMUL2_FM2CTRL_TUNE_DIS             6
-#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG            7
-#define NPCX_FMUL2_FM2N_FM2N                    FIELD(0, 6)
-#define NPCX_FMUL2_FM2P_WFPRED                  FIELD(4, 4)
-
-/******************************************************************************/
-/* WOV (Wake-on-Voice) Registers */
-#define NPCX_WOV_CLOCK_CNTL         REG32(NPCX_WOV_BASE_ADDR + 0x000)
-#define NPCX_WOV_PLL_CNTL1          REG32(NPCX_WOV_BASE_ADDR + 0x004)
-#define NPCX_WOV_PLL_CNTL2          REG32(NPCX_WOV_BASE_ADDR + 0x008)
-#define NPCX_WOV_FIFO_CNT           REG32(NPCX_WOV_BASE_ADDR + 0x00C)
-#define NPCX_WOV_FIFO_OUT           REG32(NPCX_WOV_BASE_ADDR + 0x010)
-#define NPCX_WOV_STATUS             REG32(NPCX_WOV_BASE_ADDR + 0x014)
-#define NPCX_WOV_WOV_INTEN          REG32(NPCX_WOV_BASE_ADDR + 0x018)
-#define NPCX_WOV_APM_CTRL           REG32(NPCX_WOV_BASE_ADDR + 0x01C)
-#define NPCX_WOV_I2S_CNTL(n)        REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4*n))
-#define NPCX_WOV_VERSION            REG32(NPCX_WOV_BASE_ADDR + 0x030)
-
-/******************************************************************************/
-/* WOV register fields */
-#define NPCX_WOV_CLOCK_CNT_CLK_SEL              0
-#define NPCX_WOV_CLOCK_CNT_DMIC_EN              3
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL         7
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV             FIELD(8, 7)
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC          FIELD(16, 7)
-#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN        24
-#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL       25
-#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH           FIELD(0, 6)
-#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH           FIELD(6, 6)
-#define NPCX_WOV_FIFO_CNT_I2S_FFRST             13
-#define NPCX_WOV_FIFO_CNT_CORE_FFRST            14
-#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL            FIELD(16, 3)
-#define NPCX_WOV_STATUS_CFIFO_CNT               FIELD(0, 8)
-#define NPCX_WOV_STATUS_CFIFO_NE                8
-#define NPCX_WOV_STATUS_CFIFO_OIT               9
-#define NPCX_WOV_STATUS_CFIFO_OWT               10
-#define NPCX_WOV_STATUS_CFIFO_OVRN              11
-#define NPCX_WOV_STATUS_I2S_FIFO_OVRN           12
-#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN          13
-#define NPCX_WOV_STATUS_BITS			FIELD(9, 6)
-#define NPCX_WOV_INTEN_VAD_INTEN                0
-#define NPCX_WOV_INTEN_VAD_WKEN                 1
-#define NPCX_WOV_INTEN_CFIFO_NE_IE              8
-#define NPCX_WOV_INTEN_CFIFO_OIT_IE             9
-#define NPCX_WOV_INTEN_CFIFO_OWT_WE             10
-#define NPCX_WOV_INTEN_CFIFO_OVRN_IE            11
-#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE         12
-#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE        13
-#define NPCX_WOV_APM_CTRL_APM_RST               0
-#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN            0
-#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1            FIELD(4, 4)
-#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2            FIELD(8, 4)
-#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI            15
-#define NPCX_WOV_PLL_CNTL2_PLL_FBDV             FIELD(0, 12)
-#define NPCX_WOV_PLL_CNTL2_PLL_INDV             FIELD(12, 4)
-#define NPCX_WOV_I2S_CNTL_I2S_BCNT              FIELD(0, 5)
-#define NPCX_WOV_I2S_CNTL_I2S_TRIG              5
-#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ             6
-#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL            FIELD(7, 9)
-#define NPCX_WOV_I2S_CNTL_I2S_CHAN              FIELD(0, 16)
-#define NPCX_WOV_I2S_CNTL0_I2S_HIZD             16
-#define NPCX_WOV_I2S_CNTL0_I2S_HIZ              17
-#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV         18
-#define NPCX_WOV_I2S_CNTL0_I2S_OPS              19
-#define NPCX_WOV_I2S_CNTL0_I2S_OPE              20
-#define NPCX_WOV_I2S_CNTL0_I2S_IPS              21
-#define NPCX_WOV_I2S_CNTL0_I2S_IPE              22
-#define NPCX_WOV_I2S_CNTL0_I2S_TST              23
-#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS         24
-
-/******************************************************************************/
-/* PS/2 registers */
-#define NPCX_PS2_PSDAT                   REG8(NPCX_PS2_BASE_ADDR + 0x000)
-#define NPCX_PS2_PSTAT                   REG8(NPCX_PS2_BASE_ADDR + 0x002)
-#define NPCX_PS2_PSCON                   REG8(NPCX_PS2_BASE_ADDR + 0x004)
-#define NPCX_PS2_PSOSIG                  REG8(NPCX_PS2_BASE_ADDR + 0x006)
-#define NPCX_PS2_PSISIG                  REG8(NPCX_PS2_BASE_ADDR + 0x008)
-#define NPCX_PS2_PSIEN                   REG8(NPCX_PS2_BASE_ADDR + 0x00A)
-
-/* PS/2 register field */
-#define NPCX_PS2_PSTAT_SOT               0
-#define NPCX_PS2_PSTAT_EOT               1
-#define NPCX_PS2_PSTAT_PERR              2
-#define NPCX_PS2_PSTAT_ACH               FIELD(3, 3)
-#define NPCX_PS2_PSTAT_RFERR             6
-
-#define NPCX_PS2_PSCON_EN                0
-#define NPCX_PS2_PSCON_XMT               1
-#define NPCX_PS2_PSCON_HDRV              FIELD(2, 2)
-#define NPCX_PS2_PSCON_IDB               FIELD(4, 3)
-#define NPCX_PS2_PSCON_WPUED             7
-
-#define NPCX_PS2_PSOSIG_WDAT0            0
-#define NPCX_PS2_PSOSIG_WDAT1            1
-#define NPCX_PS2_PSOSIG_WDAT2            2
-#define NPCX_PS2_PSOSIG_CLK0             3
-#define NPCX_PS2_PSOSIG_CLK1             4
-#define NPCX_PS2_PSOSIG_CLK2             5
-#define NPCX_PS2_PSOSIG_WDAT3            6
-#define NPCX_PS2_PSOSIG_CLK3             7
-#define NPCX_PS2_PSOSIG_CLK(n)      (((n) < NPCX_PS2_CH3) ? \
-					((n) + 3) : 7)
-#define NPCX_PS2_PSOSIG_WDAT(n)     (((n) < NPCX_PS2_CH3) ? \
-					((n) + 0) : 6)
-#define NPCX_PS2_PSOSIG_CLK_MASK_ALL \
-					(BIT(NPCX_PS2_PSOSIG_CLK0) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK1) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK2) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK3))
-
-#define NPCX_PS2_PSISIG_RDAT0            0
-#define NPCX_PS2_PSISIG_RDAT1            1
-#define NPCX_PS2_PSISIG_RDAT2            2
-#define NPCX_PS2_PSISIG_RCLK0            3
-#define NPCX_PS2_PSISIG_RCLK1            4
-#define NPCX_PS2_PSISIG_RCLK2            5
-#define NPCX_PS2_PSISIG_RDAT3            6
-#define NPCX_PS2_PSISIG_RCLK3            7
-#define NPCX_PS2_PSIEN_SOTIE             0
-#define NPCX_PS2_PSIEN_EOTIE             1
-#define NPCX_PS2_PSIEN_PS2_WUE           4
-#define NPCX_PS2_PSIEN_PS2_CLK_SEL	     7
-
-#ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-extern const enum gpio_signal hibernate_wake_pins[];
-extern const int hibernate_wake_pins_used;
-#else
-extern enum gpio_signal hibernate_wake_pins[];
-extern int hibernate_wake_pins_used;
-#endif
-
-#ifndef NPCX_UART_MODULE2
-#define NPCX_UART_MODULE2 0
-#endif /* NPCX_UART_MODULE2 */
-
-#if defined(CHIP_FAMILY_NPCX5)
-#include "registers-npcx5.h"
-#elif defined(CHIP_FAMILY_NPCX7)
-#include "registers-npcx7.h"
-#elif defined(CHIP_FAMILY_NPCX9)
-#include "registers-npcx9.h"
-#else
-#error "Unsupported chip family"
-#endif
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/npcx/rom_chip.h b/chip/npcx/rom_chip.h
deleted file mode 100644
index bb66f95e88..0000000000
--- a/chip/npcx/rom_chip.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ROM_CHIP_H_
-#define __CROS_EC_ROM_CHIP_H_
-
-/******************************************************************************/
-/*
- * Enumerations of ROM api functions
- */
-enum API_SIGN_OPTIONS_T {
-	SIGN_NO_CHECK = 0,
-	SIGN_CRC_CHECK = 1,
-};
-
-enum API_RETURN_STATUS_T {
-	/* Successful download */
-	API_RET_STATUS_OK = 0,
-	/* Address is outside of flash or not 4 bytes aligned. */
-	API_RET_STATUS_INVALID_SRC_ADDR = 1,
-	/* Address is outside of RAM or not 4 bytes aligned. */
-	API_RET_STATUS_INVALID_DST_ADDR = 2,
-	/* Size is 0 or not 4 bytes aligned. */
-	API_RET_STATUS_INVALID_SIZE = 3,
-	/* Flash Address + Size is out of flash. */
-	API_RET_STATUS_INVALID_SIZE_OUT_OF_FLASH = 4,
-	/* RAM Address + Size is out of RAM. */
-	API_RET_STATUS_INVALID_SIZE_OUT_OF_RAM = 5,
-	/* Wrong sign option. */
-	API_RET_STATUS_INVALID_SIGN = 6,
-	/* Error during Code copy. */
-	API_RET_STATUS_COPY_FAILED = 7,
-	/* Execution Address is outside of RAM */
-	API_RET_STATUS_INVALID_EXE_ADDR = 8,
-	/* Bad CRC value */
-	API_RET_STATUS_INVALID_SIGNATURE = 9,
-};
-
-/******************************************************************************/
-/*
- * Macro functions of ROM api functions
- */
-#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40)
-#define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \
-	status) \
-	(((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \
-	(src_offset, dest_addr, size, sign, exe_addr, status))
-
-/******************************************************************************/
-/*
- * Declarations of ROM api functions
- */
-typedef void (*download_from_flash_ptr) (
-	uint32_t src_offset, /* The offset of the data to be downloaded */
-	uint32_t dest_addr,  /* The address of the downloaded data in the RAM*/
-	uint32_t size,       /* Number of bytes to download */
-	enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */
-	uint32_t exe_addr, /* jump to this address after download if not zero */
-	enum API_RETURN_STATUS_T *status /* Status fo download */
-);
-
-
-
-#endif /* __CROS_EC_ROM_CHIP_H_ */
diff --git a/chip/npcx/sha256_chip.c b/chip/npcx/sha256_chip.c
deleted file mode 100644
index 6d2d938895..0000000000
--- a/chip/npcx/sha256_chip.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SHA256 module for Chrome EC */
-#include "common.h"
-#include "sha256.h"
-#include "util.h"
-
-enum ncl_status {
-	NCL_STATUS_OK,
-	NCL_STATUS_FAIL,
-	NCL_STATUS_INVALID_PARAM,
-	NCL_STATUS_PARAM_NOT_SUPPORTED,
-	NCL_STATUS_SYSTEM_BUSY,
-	NCL_STATUS_AUTHENTICATION_FAIL,
-	NCL_STATUS_NO_RESPONSE,
-	NCL_STATUS_HARDWARE_ERROR,
-};
-
-enum ncl_sha_type {
-	NCL_SHA_TYPE_2_256 = 0,
-	NCL_SHA_TYPE_2_384 = 1,
-	NCL_SHA_TYPE_2_512 = 2,
-	NCL_SHA_TYPE_NUM
-};
-
-/*
- * The base address of the table that holds the function pointer for each
- * SHA256 API in ROM.
- */
-#define NCL_SHA_BASE_ADDR          0x00000100UL
-struct ncl_sha {
-	/* Get the SHA context size required by SHA APIs. */
-	uint32_t (*get_context_size)(void);
-	/* Initial SHA context. */
-	enum ncl_status (*init_context)(void *ctx);
-	/* Finalize SHA context. */
-	enum ncl_status (*finalize_context)(void *ctx);
-	/* Initiate the SHA hardware module and setups needed parameters. */
-	enum ncl_status (*init)(void *ctx);
-	/*
-	 * Prepare the context buffer for a SHA calculation -  by loading the
-	 * initial SHA-256/384/512 parameters.
-	 */
-	enum ncl_status (*start)(void *ctx, enum ncl_sha_type type);
-	/*
-	 * Updates the SHA calculation with the additional data. When the
-	 * function returns, the hardware and memory buffer shall be ready to
-	 * accept new data * buffers for SHA calculation and changes to the data
-	 * in data buffer should no longer effect the SHA calculation.
-	 */
-	enum ncl_status (*update)(void *ctx, const uint8_t *data, uint32_t Len);
-	/* Return the SHA result (digest.) */
-	enum ncl_status (*finish)(void *ctx, uint8_t *hashDigest);
-	/* Perform a complete SHA calculation */
-	enum ncl_status (*calc)(void *ctx, enum ncl_sha_type type,
-			const uint8_t *data, uint32_t Len, uint8_t *hashDigest);
-	/* Power on/off the SHA module. */
-	enum ncl_status (*power)(void *ctx, uint8_t enable);
-	/* Reset the SHA hardware and terminate any in-progress operations. */
-	enum ncl_status (*reset)(void *ctx);
-};
-
-#define NCL_SHA ((const struct ncl_sha *)NCL_SHA_BASE_ADDR)
-
-void SHA256_init(struct sha256_ctx *ctx)
-{
-	NCL_SHA->init_context(ctx->handle);
-	NCL_SHA->power(ctx->handle, 1);
-	NCL_SHA->init(ctx->handle);
-	NCL_SHA->reset(ctx->handle);
-	NCL_SHA->start(ctx->handle, NCL_SHA_TYPE_2_256);
-}
-
-void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len)
-{
-	NCL_SHA->update(ctx->handle, data, len);
-}
-
-void SHA256_abort(struct sha256_ctx *ctx)
-{
-	NCL_SHA->reset(ctx->handle);
-	NCL_SHA->power(ctx->handle, 0);
-	NCL_SHA->finalize_context(ctx->handle);
-}
-
-uint8_t *SHA256_final(struct sha256_ctx *ctx)
-{
-	NCL_SHA->finish(ctx->handle, ctx->buf);
-	NCL_SHA->power(ctx->handle, 0);
-	NCL_SHA->finalize_context(ctx->handle);
-	return ctx->buf;
-}
-
-static void hmac_SHA256_step(uint8_t *output, uint8_t mask,
-			const uint8_t *key, const int key_len,
-			const uint8_t *data, const int data_len)
-{
-	struct sha256_ctx hmac_ctx;
-	uint8_t *key_pad = hmac_ctx.buf;
-	uint8_t *tmp;
-	int i;
-
-	memset(key_pad, mask, SHA256_BLOCK_SIZE);
-	for (i = 0; i < key_len; i++)
-		key_pad[i] ^= key[i];
-
-	SHA256_init(&hmac_ctx);
-	SHA256_update(&hmac_ctx, key_pad, SHA256_BLOCK_SIZE);
-	SHA256_update(&hmac_ctx, data, data_len);
-	tmp = SHA256_final(&hmac_ctx);
-	memcpy(output, tmp, SHA256_DIGEST_SIZE);
-}
-/*
- * Note: When the API is called, it will consume about half of TASK_STACK_SIZE
- * because a variable of structure sha256_ctx is declared in the function
- * hmac_SHA256_step.
- */
-void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
-		const uint8_t *message, const int message_len)
-{
-	/* This code does not support key_len > block_size. */
-	ASSERT(key_len <= SHA256_BLOCK_SIZE);
-
-	/*
-	 * i_key_pad = key (zero-padded) ^ 0x36
-	 * output = hash(i_key_pad || message)
-	 * (Use output as temporary buffer)
-	 */
-	hmac_SHA256_step(output, 0x36, key, key_len, message, message_len);
-
-	/*
-	 * o_key_pad = key (zero-padded) ^ 0x5c
-	 * output = hash(o_key_pad || output)
-	 */
-	hmac_SHA256_step(output, 0x5c, key, key_len, output,
-				SHA256_DIGEST_SIZE);
-}
diff --git a/chip/npcx/sha256_chip.h b/chip/npcx/sha256_chip.h
deleted file mode 100644
index 3b9586d962..0000000000
--- a/chip/npcx/sha256_chip.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SHA256_CHIP_H
-#define __CROS_EC_SHA256_CHIP_H
-
-#include "common.h"
-
-#define NPCX_SHA256_HANDLE_SIZE    212
-struct sha256_ctx {
-	/* the context handle required for SHA256 API */
-	uint8_t handle[NPCX_SHA256_HANDLE_SIZE];
-	/*
-	 * This is used to buffer:
-	 *   1. the result (digest) of the SHA256 computation.
-	 *   2. the 1st block input data (the key padding) for hmac_SHA256_step.
-	 */
-	uint8_t buf[SHA256_BLOCK_SIZE];
-} __aligned(4);
-
-void SHA256_abort(struct sha256_ctx *ctx);
-
-#endif  /* __CROS_EC_SHA256_CHIP_H */
diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c
deleted file mode 100644
index 503a52807e..0000000000
--- a/chip/npcx/shi.c
+++ /dev/null
@@ -1,1082 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * SHI driver for Chrome EC.
- *
- * This uses Input/Output buffer to handle SPI transmission and reception.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "task.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-
-#if !(DEBUG_SHI)
-#define DEBUG_CPUTS(...)
-#define DEBUG_CPRINTS(...)
-#define DEBUG_CPRINTF(...)
-#else
-#define DEBUG_CPUTS(outstr) cputs(CC_SPI, outstr)
-#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-#endif
-
-/* SHI Bus definition */
-#ifdef NPCX_SHI_V2
-#define SHI_OBUF_FULL_SIZE  128                    /* Full output buffer size */
-#define SHI_IBUF_FULL_SIZE  128                    /* Full input buffer size  */
-/* Configure the IBUFLVL2 = the size of V3 protocol header */
-#define SHI_IBUFLVL2_THRESHOLD (sizeof(struct ec_host_request))
-#else
-#define SHI_OBUF_FULL_SIZE  64                     /* Full output buffer size */
-#define SHI_IBUF_FULL_SIZE  64                     /* Full input buffer size  */
-#endif
-#define SHI_OBUF_HALF_SIZE  (SHI_OBUF_FULL_SIZE/2) /* Half output buffer size */
-#define SHI_IBUF_HALF_SIZE  (SHI_IBUF_FULL_SIZE/2) /* Half input buffer size  */
-
-/* Start address of SHI output buffer */
-#define SHI_OBUF_START_ADDR  (volatile uint8_t  *)(NPCX_SHI_BASE_ADDR + 0x020)
-/* Middle address of SHI output buffer */
-#define SHI_OBUF_HALF_ADDR   (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE)
-/* Top address of SHI output buffer */
-#define SHI_OBUF_FULL_ADDR   (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE)
-/*
- * Valid offset of SHI output buffer to write.
- * When SIMUL bit is set, IBUFPTR can be used instead of OBUFPTR
- */
-#define SHI_OBUF_VALID_OFFSET ((shi_read_buf_pointer() + \
-			SHI_OUT_PREAMBLE_LENGTH) % SHI_OBUF_FULL_SIZE)
-/* Start address of SHI input buffer */
-#define SHI_IBUF_START_ADDR  (&NPCX_IBUF(0))
-/* Current address of SHI input buffer */
-#define SHI_IBUF_CUR_ADDR    (SHI_IBUF_START_ADDR + shi_read_buf_pointer())
-
-/*
- * Timeout to wait for SHI request packet
- *
- * This affects the slowest SPI clock we can support.  A delay of 8192
- * us permits a 512-byte request at 500 KHz, assuming the controller
- * starts sending bytes as soon as it asserts chip select.  That's as
- * slow as we would practically want to run the SHI interface, since
- * running it slower significantly impacts firmware update times.
- */
-#define SHI_CMD_RX_TIMEOUT_US 8192
-
-/* Timeout for glitch case. Make sure it will exceed 8 SPI clocks */
-#define SHI_GLITCH_TIMEOUT_US 10000
-
-/*
- * The AP blindly clocks back bytes over the SPI interface looking for a
- * framing byte.  So this preamble must always precede the actual response
- * packet.
- */
-
-#define SHI_OUT_PREAMBLE_LENGTH 2
-/*
- * Space allocation of the past-end status byte (EC_SPI_PAST_END) in the out_msg
- * buffer.
- */
-#define EC_SPI_PAST_END_LENGTH 1
-/*
- * Space allocation of the frame status byte (EC_SPI_FRAME_START) in the out_msg
- * buffer.
- */
-#define EC_SPI_FRAME_START_LENGTH 1
-
-/*
- * Offset of output parameters needs to account for pad and framing bytes and
- * one last past-end byte at the end so any additional bytes clocked out by
- * the AP will have a known and identifiable value.
- */
-#define SHI_PROTO3_OVERHEAD (EC_SPI_PAST_END_LENGTH + EC_SPI_FRAME_START_LENGTH)
-
-
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-/* The boundary which SHI will output invalid data on MISO. */
-#define SHI_BYPASS_BOUNDARY 256
-/* Increase FRAME_START_LENGTH in case shi outputs invalid FRAME_START byte */
-#undef  EC_SPI_FRAME_START_LENGTH
-#define EC_SPI_FRAME_START_LENGTH 2
-#endif
-
-/*
- * Max data size for a version 3 request/response packet.  This is big enough
- * to handle a request/response header, flash write offset/size, and 512 bytes
- * of flash data:
- *  sizeof(ec_host_request):          8
- *  sizoef(ec_params_flash_write):    8
- *  payload                         512
- *
- */
-#define SHI_MAX_REQUEST_SIZE 0x220
-
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-/* Make sure SHI_MAX_RESPONSE_SIZE won't exceed 256 bytes */
-#define SHI_MAX_RESPONSE_SIZE (160 + sizeof(struct ec_host_response))
-BUILD_ASSERT(SHI_MAX_RESPONSE_SIZE <= SHI_BYPASS_BOUNDARY);
-#else
-#define SHI_MAX_RESPONSE_SIZE 0x220
-#endif
-
-/*
- * Our input and output msg buffers. These must be large enough for our largest
- * message, including protocol overhead.  The pointers after the protocol
- * overhead, as passed to the host command handler, must be 32-bit aligned.
- */
-#define SHI_OUT_START_PAD (4 * (EC_SPI_FRAME_START_LENGTH / 4 + 1))
-#define SHI_OUT_END_PAD (4 * (EC_SPI_PAST_END_LENGTH / 4 + 1))
-static uint8_t out_msg_padded[SHI_OUT_START_PAD +
-			      SHI_MAX_RESPONSE_SIZE +
-			      SHI_OUT_END_PAD] __aligned(4);
-static uint8_t * const out_msg =
-	out_msg_padded + SHI_OUT_START_PAD - EC_SPI_FRAME_START_LENGTH;
-static uint8_t in_msg[SHI_MAX_REQUEST_SIZE] __aligned(4);
-
-/* Parameters used by host protocols */
-static struct host_packet shi_packet;
-
-enum shi_state {
-	/* SHI not enabled (initial state, and when chipset is off) */
-	SHI_STATE_DISABLED = 0,
-	/* Ready to receive next request */
-	SHI_STATE_READY_TO_RECV,
-	/* Receiving request */
-	SHI_STATE_RECEIVING,
-	/* Processing request */
-	SHI_STATE_PROCESSING,
-	/* Canceling response since CS deasserted and output NOT_READY byte */
-	SHI_STATE_CNL_RESP_NOT_RDY,
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	/* Keep output buffer as PROCESSING byte until reaching 256B boundary */
-	SHI_STATE_WAIT_ALIGNMENT,
-#endif
-	/* Sending response */
-	SHI_STATE_SENDING,
-	/* Received data is valid. */
-	SHI_STATE_BAD_RECEIVED_DATA,
-};
-
-volatile enum shi_state state;
-
-/* SHI bus parameters */
-struct shi_bus_parameters {
-	uint8_t *rx_msg;          /* Entry pointer of msg rx buffer   */
-	uint8_t *tx_msg;          /* Entry pointer of msg tx buffer   */
-	volatile uint8_t *rx_buf; /* Entry pointer of receive buffer  */
-	volatile uint8_t *tx_buf; /* Entry pointer of transmit buffer */
-	uint16_t sz_received;     /* Size of received data in bytes   */
-	uint16_t sz_sending;      /* Size of sending data in bytes    */
-	uint16_t sz_request;      /* request bytes need to receive    */
-	uint16_t sz_response;     /* response bytes need to receive   */
-	timestamp_t rx_deadline;  /* deadline of receiving            */
-	uint8_t  pre_ibufstat;    /* Previous IBUFSTAT value          */
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	uint16_t bytes_in_256b;   /* Sent bytes in 256 bytes boundary */
-#endif
-} shi_params;
-
-/* Forward declaration */
-static void shi_reset_prepare(void);
-static void shi_bad_received_data(void);
-static void shi_fill_out_status(uint8_t status);
-static void shi_write_half_outbuf(void);
-static void shi_write_first_pkg_outbuf(uint16_t szbytes);
-static int shi_read_inbuf_wait(uint16_t szbytes);
-static uint8_t shi_read_buf_pointer(void);
-
-/*****************************************************************************/
-/* V3 protocol layer functions */
-
-/**
- * Called to send a response back to the host.
- *
- * Some commands can continue for a while. This function is called by
- * host_command when it completes.
- *
- */
-static void shi_send_response_packet(struct host_packet *pkt)
-{
-	/*
-	 * Disable interrupts. This routine is not called from interrupt
-	 * context and buffer underrun will likely occur if it is
-	 * preempted after writing its initial reply byte. Also, we must be
-	 * sure our state doesn't unexpectedly change, in case we're expected
-	 * to take RESP_NOT_RDY actions.
-	 */
-	interrupt_disable();
-	if (state == SHI_STATE_PROCESSING) {
-		/* Append our past-end byte, which we reserved space for. */
-		((uint8_t *) pkt->response)[pkt->response_size + 0] =
-			EC_SPI_PAST_END;
-
-		/* Computing sending bytes of response */
-		shi_params.sz_response =
-			pkt->response_size + SHI_PROTO3_OVERHEAD;
-
-		/* Start to fill output buffer with msg buffer */
-		shi_write_first_pkg_outbuf(shi_params.sz_response);
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-		/*
-		 * If response package is over 256B boundary,
-		 * keep sending PROCESSING byte
-		 */
-		if (state != SHI_STATE_WAIT_ALIGNMENT) {
-#endif
-			/* Transmit the reply */
-			state = SHI_STATE_SENDING;
-			DEBUG_CPRINTF("SND-");
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-		}
-#endif
-	}
-	/*
-	 * If we're not processing, then the AP has already terminated the
-	 * transaction, and won't be listening for a response.
-	 * Reset state machine for next transaction.
-	 */
-	else if (state == SHI_STATE_CNL_RESP_NOT_RDY) {
-		shi_reset_prepare();
-		DEBUG_CPRINTF("END\n");
-	} else
-		DEBUG_CPRINTS("Unexpected state %d in response handler", state);
-	interrupt_enable();
-}
-
-void shi_handle_host_package(void)
-{
-	uint16_t sz_inbuf_int = shi_params.sz_request / SHI_IBUF_HALF_SIZE;
-	uint16_t cnt_inbuf_int = shi_params.sz_received / SHI_IBUF_HALF_SIZE;
-	if (sz_inbuf_int - cnt_inbuf_int)
-		/* Need to receive data from buffer */
-		return;
-	else {
-		uint16_t remain_bytes = shi_params.sz_request
-					- shi_params.sz_received;
-
-		/* Read remaining bytes from input buffer directly */
-		if (!shi_read_inbuf_wait(remain_bytes))
-			return shi_bad_received_data();
-		/* Move to processing state immediately */
-		state = SHI_STATE_PROCESSING;
-		DEBUG_CPRINTF("PRC-");
-	}
-	/* Fill output buffer to indicate we`re processing request */
-	shi_fill_out_status(EC_SPI_PROCESSING);
-
-	/* Set up parameters for host request */
-	shi_packet.send_response = shi_send_response_packet;
-
-	shi_packet.request = in_msg;
-	shi_packet.request_temp = NULL;
-	shi_packet.request_max = sizeof(in_msg);
-	shi_packet.request_size = shi_params.sz_request;
-
-
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	/* Move FRAME_START to second byte */
-	out_msg[0] = EC_SPI_PROCESSING;
-	out_msg[1] = EC_SPI_FRAME_START;
-#else
-	/* Put FRAME_START in first byte */
-	out_msg[0] = EC_SPI_FRAME_START;
-#endif
-	shi_packet.response = out_msg + EC_SPI_FRAME_START_LENGTH;
-
-	/* Reserve space for frame start and trailing past-end byte */
-	shi_packet.response_max = SHI_MAX_RESPONSE_SIZE;
-	shi_packet.response_size = 0;
-	shi_packet.driver_result = EC_RES_SUCCESS;
-
-	/* Go to common-layer to handle request */
-	host_packet_receive(&shi_packet);
-}
-
-/* Parse header for version of spi-protocol */
-static void shi_parse_header(void)
-{
-	/* We're now inside a transaction */
-	state = SHI_STATE_RECEIVING;
-	DEBUG_CPRINTF("RV-");
-
-	/* Setup deadline time for receiving */
-	shi_params.rx_deadline = get_time();
-	shi_params.rx_deadline.val += SHI_CMD_RX_TIMEOUT_US;
-
-	/* Wait for version, command, length bytes */
-	if (!shi_read_inbuf_wait(3))
-		return shi_bad_received_data();
-
-	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
-		/* Protocol version 3 */
-		struct ec_host_request *r = (struct ec_host_request *) in_msg;
-		int pkt_size;
-		/*
-		 * If request is over 32 bytes,
-		 * we need to modified the algorithm again.
-		 */
-		ASSERT(sizeof(*r) < SHI_IBUF_HALF_SIZE);
-
-		/* Wait for the rest of the command header */
-		if (!shi_read_inbuf_wait(sizeof(*r) - 3))
-			return shi_bad_received_data();
-
-		/* Check how big the packet should be */
-		pkt_size = host_request_expected_size(r);
-		if (pkt_size == 0 || pkt_size > sizeof(in_msg))
-			return shi_bad_received_data();
-
-		/* Computing total bytes need to receive */
-		shi_params.sz_request = pkt_size;
-
-		shi_handle_host_package();
-	} else {
-		/* Invalid version number */
-		return shi_bad_received_data();
-	}
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/* This routine fills out all SHI output buffer with status byte */
-static void shi_fill_out_status(uint8_t status)
-{
-	uint8_t start, end;
-	uint8_t *fill_ptr;
-	uint8_t *fill_end;
-	uint8_t *obuf_end;
-
-	/* Disable interrupts in case the interfere by the other interrupts */
-	interrupt_disable();
-
-	/*
-	 * Fill out output buffer with status byte and leave a gap for PREAMBLE.
-	 * The gap guarantees the synchronization. The critical section should
-	 * be done within this gap. No racing happens.
-	 */
-	start = SHI_OBUF_VALID_OFFSET;
-	end = ((start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH)
-	       % SHI_OBUF_FULL_SIZE);
-
-	fill_ptr = (uint8_t *)SHI_OBUF_START_ADDR + start;
-	fill_end = (uint8_t *)SHI_OBUF_START_ADDR + end;
-	obuf_end = (uint8_t *)SHI_OBUF_START_ADDR + SHI_OBUF_FULL_SIZE;
-	while (fill_ptr != fill_end) {
-		*(fill_ptr++) = status;
-		if (fill_ptr == obuf_end)
-			fill_ptr = (uint8_t *)SHI_OBUF_START_ADDR;
-	}
-
-	/* End of critical section */
-	interrupt_enable();
-}
-
-#ifdef NPCX_SHI_V2
- /*
-  * This routine configures at which level the Input Buffer Half Full 2(IBHF2))
-  * event triggers an interrupt to core.
-  */
-static void shi_sec_ibf_int_enable(int enable)
-{
-	if (enable) {
-		/* Setup IBUFLVL2 threshold and enable it */
-		SET_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
-		SET_FIELD(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2,
-				SHI_IBUFLVL2_THRESHOLD);
-		CLEAR_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
-		/* Enable IBHF2 event */
-		SET_BIT(NPCX_EVENABLE2, NPCX_EVENABLE2_IBHF2EN);
-	} else {
-		/* Disable IBHF2 event first */
-		CLEAR_BIT(NPCX_EVENABLE2, NPCX_EVENABLE2_IBHF2EN);
-		/* Disable IBUFLVL2 and set threshold back to zero */
-		SET_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
-		SET_FIELD(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2, 0);
-	}
-}
-#else
-/*
- * This routine makes sure it's valid transaction or glitch on CS bus.
- */
-static int shi_is_cs_glitch(void)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + SHI_GLITCH_TIMEOUT_US;
-	/*
-	 * If input buffer pointer is no changed after timeout, it will
-	 * return true
-	 */
-	while (shi_params.pre_ibufstat == shi_read_buf_pointer())
-		if (timestamp_expired(deadline, NULL))
-			return 1;
-	/* valid package */
-	return 0;
-}
-#endif
-
-/*
- * This routine write SHI next half output buffer from msg buffer
- */
-static void shi_write_half_outbuf(void)
-{
-	const uint8_t size = MIN(SHI_OBUF_HALF_SIZE,
-				 shi_params.sz_response -
-				 shi_params.sz_sending);
-	uint8_t *obuf_ptr = (uint8_t *)shi_params.tx_buf;
-	const uint8_t *obuf_end = obuf_ptr + size;
-	uint8_t *msg_ptr = shi_params.tx_msg;
-
-	/* Fill half output buffer */
-	while (obuf_ptr != obuf_end)
-		*(obuf_ptr++) = *(msg_ptr++);
-
-	shi_params.sz_sending += size;
-	shi_params.tx_buf = obuf_ptr;
-	shi_params.tx_msg = msg_ptr;
-}
-
-/*
- * This routine write SHI output buffer from msg buffer over halt of it.
- * It make sure we have enought time to handle next operations.
- */
-static void shi_write_first_pkg_outbuf(uint16_t szbytes)
-{
-	uint8_t size, offset;
-	uint8_t *obuf_ptr;
-	uint8_t *obuf_end;
-	uint8_t *msg_ptr;
-
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	/*
-	 * If response package is across 256 bytes boundary,
-	 * bypass needs to extend PROCESSING bytes after reaching the boundary.
-	 */
-	if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes
-	    > SHI_BYPASS_BOUNDARY) {
-		state = SHI_STATE_WAIT_ALIGNMENT;
-		/* Set pointer of output buffer to the start address */
-		shi_params.tx_buf = SHI_OBUF_START_ADDR;
-		DEBUG_CPRINTF("WAT-");
-		return;
-	}
-#endif
-
-	/* Start writing at our current OBUF position */
-	offset = SHI_OBUF_VALID_OFFSET;
-	obuf_ptr = (uint8_t *)SHI_OBUF_START_ADDR + offset;
-	msg_ptr = shi_params.tx_msg;
-
-	/* Fill up to OBUF mid point, or OBUF end */
-	size = MIN(SHI_OBUF_HALF_SIZE - (offset % SHI_OBUF_HALF_SIZE),
-					szbytes - shi_params.sz_sending);
-	obuf_end = obuf_ptr + size;
-	while (obuf_ptr != obuf_end)
-		*(obuf_ptr++) = *(msg_ptr++);
-
-	/* Track bytes sent for later accounting */
-	shi_params.sz_sending += size;
-
-	/* Write data to beginning of OBUF if we've reached the end */
-	if (obuf_ptr == SHI_OBUF_FULL_ADDR)
-		obuf_ptr = (uint8_t *)SHI_OBUF_START_ADDR;
-
-	/* Fill next half output buffer */
-	size = MIN(SHI_OBUF_HALF_SIZE, szbytes - shi_params.sz_sending);
-	obuf_end = obuf_ptr + size;
-	while (obuf_ptr != obuf_end)
-		*(obuf_ptr++) = *(msg_ptr++);
-
-	/* Track bytes sent / last OBUF position written for later accounting */
-	shi_params.sz_sending += size;
-	shi_params.tx_buf = obuf_ptr;
-	shi_params.tx_msg = msg_ptr;
-}
-
-/* This routine copies SHI half input buffer data to msg buffer */
-static void shi_read_half_inbuf(void)
-{
-	/*
-	 * Copy to read buffer until reaching middle/top address of
-	 * input buffer or completing receiving data
-	 */
-	do {
-		/* Restore data to msg buffer */
-		*(shi_params.rx_msg++) = *(shi_params.rx_buf++);
-		shi_params.sz_received++;
-	} while (shi_params.sz_received % SHI_IBUF_HALF_SIZE
-		&& shi_params.sz_received != shi_params.sz_request);
-}
-
-/*
- * This routine read SHI input buffer to msg buffer until
- * we have received a certain number of bytes
- */
-static int shi_read_inbuf_wait(uint16_t szbytes)
-{
-	uint16_t i;
-
-	/* Copy data to msg buffer from input buffer */
-	for (i = 0; i < szbytes; i++, shi_params.sz_received++) {
-		/*
-		 * If input buffer pointer equals pointer which wants to read,
-		 * it means data is not ready.
-		 */
-		while (shi_params.rx_buf == SHI_IBUF_CUR_ADDR)
-			if (timestamp_expired(shi_params.rx_deadline, NULL))
-				return 0;
-		/* Restore data to msg buffer */
-		*(shi_params.rx_msg++) = *(shi_params.rx_buf++);
-	}
-	return 1;
-}
-
-/* Read pointer of input or output buffer by consecutive reading */
-static uint8_t shi_read_buf_pointer(void)
-{
-	uint8_t stat;
-	/* Wait for two consecutive equal values are read */
-	do {
-		stat = NPCX_IBUFSTAT;
-	} while (stat != NPCX_IBUFSTAT);
-
-	return stat;
-}
-
-/* This routine handles shi recevied unexcepted data */
-static void shi_bad_received_data(void)
-{
-	uint16_t i;
-
-	/* State machine mismatch, timeout, or protocol we can't handle. */
-	shi_fill_out_status(EC_SPI_RX_BAD_DATA);
-	state = SHI_STATE_BAD_RECEIVED_DATA;
-
-	CPRINTF("BAD-");
-	CPRINTF("in_msg=[");
-	for (i = 0; i < shi_params.sz_received; i++)
-		CPRINTF("%02x ", in_msg[i]);
-	CPRINTF("]\n");
-
-	/* Reset shi's state machine for error recovery */
-	shi_reset_prepare();
-
-	DEBUG_CPRINTF("END\n");
-}
-
-/*
- * Avoid spamming the console with prints every IBF / IBHF interrupt, if
- * we find ourselves in an unexpected state.
- */
-static int last_error_state = -1;
-
-static void log_unexpected_state(char *isr_name)
-{
-#if !(DEBUG_SHI)
-	if (state != last_error_state)
-		CPRINTS("Unexpected state %d in %s ISR", state, isr_name);
-#endif
-	last_error_state = state;
-}
-
-static void shi_handle_cs_assert(void)
-{
-	/* If not enabled, ignore glitches on SHI_CS_L */
-	if (state == SHI_STATE_DISABLED)
-		return;
-
-	/* SHI V2 module filters cs glitch by hardware automatically */
-#ifndef NPCX_SHI_V2
-	/*
-	 * IBUFSTAT resets on the 7th clock cycle after CS assertion, which
-	 * may not have happened yet. We use NPCX_IBUFSTAT for calculating
-	 * buffer fill depth, so make sure it's valid before proceeding.
-	 */
-	if (shi_is_cs_glitch()) {
-		CPRINTS("ERR-GTH");
-		shi_reset_prepare();
-		DEBUG_CPRINTF("END\n");
-		return;
-	}
-#endif
-
-	/* NOT_READY should be sent and there're no spi transaction now. */
-	if (state == SHI_STATE_CNL_RESP_NOT_RDY)
-		return;
-
-	/* Chip select is low = asserted */
-	if (state != SHI_STATE_READY_TO_RECV) {
-		/* State machine should be reset in EVSTAT_EOR ISR */
-		CPRINTS("Unexpected state %d in CS ISR", state);
-		return;
-	}
-
-	DEBUG_CPRINTF("CSL-");
-
-	/*
-	 * Clear possible EOR event from previous transaction since it's
-	 * irrelevant now that CS is re-asserted.
-	 */
-	NPCX_EVSTAT = 1 << NPCX_EVSTAT_EOR;
-
-	/* Do not deep sleep during SHI transaction */
-	disable_sleep(SLEEP_MASK_SPI);
-
-#ifndef NPCX_SHI_V2
-	/*
-	 * Enable SHI interrupt - we will either succeed to parse our host
-	 * command or reset on failure from here.
-	 */
-	task_enable_irq(NPCX_IRQ_SHI);
-
-	/* Read first three bytes to parse which protocol is receiving */
-	shi_parse_header();
-#endif
-}
-
-/* This routine handles all interrupts of this module */
-void shi_int_handler(void)
-{
-	uint8_t stat_reg;
-#ifdef NPCX_SHI_V2
-	uint8_t stat2_reg;
-#endif
-
-	/* Read status register and clear interrupt status early */
-	stat_reg = NPCX_EVSTAT;
-	NPCX_EVSTAT = stat_reg;
-#ifdef NPCX_SHI_V2
-	stat2_reg = NPCX_EVSTAT2;
-
-	/* SHI CS pin is asserted in EVSTAT2 */
-	if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_CSNFE)) {
-		/* clear CSNFE bit */
-		NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_CSNFE);
-		DEBUG_CPRINTF("CSNFE-");
-		/*
-		 * BUSY bit is set when SHI_CS is asserted. If not, leave it for
-		 * SHI_CS de-asserted event.
-		 */
-		if (!IS_BIT_SET(NPCX_SHICFG2, NPCX_SHICFG2_BUSY)) {
-			DEBUG_CPRINTF("CSNB-");
-			return;
-		}
-		shi_handle_cs_assert();
-	}
-#endif
-
-	/*
-	 * End of data for read/write transaction. ie SHI_CS is deasserted.
-	 * Host completed or aborted transaction
-	 */
-#ifdef NPCX_SHI_V2
-	/*
-	 * EOR has the limitation that it will not be set even if the SHI_CS is
-	 * deasserted without SPI clocks. The new SHI module introduce the
-	 * CSNRE bit which will be set when SHI_CS is deasserted regardless of
-	 * SPI clocks.
-	 */
-	if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_CSNRE)) {
-		/* Clear pending bit of CSNRE */
-		NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_CSNRE);
-#else
-	if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_EOR)) {
-#endif
-		/*
-		 * We're not in proper state.
-		 * Mark not ready to abort next transaction
-		 */
-		DEBUG_CPRINTF("CSH-");
-		/*
-		 * If the buffer is still used by the host command.
-		 * Change state machine for response handler.
-		 */
-		if (state == SHI_STATE_PROCESSING) {
-			/*
-			 * Mark not ready to prevent the other
-			 * transaction immediately
-			 */
-			shi_fill_out_status(EC_SPI_NOT_READY);
-
-			state = SHI_STATE_CNL_RESP_NOT_RDY;
-
-			/*
-			 * Disable SHI interrupt, it will remain disabled
-			 * until shi_send_response_packet() is called and
-			 * CS is asserted for a new transaction.
-			 */
-			task_disable_irq(NPCX_IRQ_SHI);
-
-			DEBUG_CPRINTF("CNL-");
-			return;
-		/* Next transaction but we're not ready */
-		} else if (state == SHI_STATE_CNL_RESP_NOT_RDY)
-			return;
-
-		/* Error state for checking*/
-		if (state != SHI_STATE_SENDING)
-#ifdef NPCX_SHI_V2
-			log_unexpected_state("CSNRE");
-#else
-			log_unexpected_state("IBEOR");
-#endif
-
-		/* reset SHI and prepare to next transaction again */
-		shi_reset_prepare();
-		DEBUG_CPRINTF("END\n");
-		return;
-	}
-
-	/*
-	 * Indicate input/output buffer pointer reaches the half buffer size.
-	 * Transaction is processing.
-	 */
-	if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_IBHF)) {
-		if (state == SHI_STATE_RECEIVING) {
-			/* Read data from input to msg buffer */
-			shi_read_half_inbuf();
-			return shi_handle_host_package();
-		} else if (state == SHI_STATE_SENDING) {
-			/* Write data from msg buffer to output buffer */
-			if (shi_params.tx_buf == SHI_OBUF_START_ADDR +
-					SHI_OBUF_FULL_SIZE) {
-				/* Write data from bottom address again */
-				shi_params.tx_buf = SHI_OBUF_START_ADDR;
-				return shi_write_half_outbuf();
-			} else /* ignore it */
-				return;
-		} else if (state == SHI_STATE_PROCESSING) {
-			/* Wait for host to handle request */
-		}
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-		else if (state == SHI_STATE_WAIT_ALIGNMENT) {
-			/*
-			 * If pointer of output buffer will reach 256 bytes
-			 * boundary soon, start to fill response data.
-			 */
-			if (shi_params.bytes_in_256b == SHI_BYPASS_BOUNDARY -
-					SHI_OBUF_FULL_SIZE) {
-				state = SHI_STATE_SENDING;
-				DEBUG_CPRINTF("SND-");
-				return shi_write_half_outbuf();
-			}
-		}
-#endif
-		else
-			/* Unexpected status */
-			log_unexpected_state("IBHF");
-	}
-
-#ifdef NPCX_SHI_V2
-	/*
-	 * The size of input buffer reaches the size of
-	 * protocol V3 header(=8) after CS asserted.
-	 */
-	if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_IBHF2)) {
-		/* Clear IBHF2 */
-		NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_IBHF2);
-		DEBUG_CPRINTF("HDR-");
-		/* Disable second IBF interrupt and start to parse header */
-		shi_sec_ibf_int_enable(0);
-		shi_parse_header();
-	}
-#endif
-
-	/*
-	 * Indicate input/output buffer pointer reaches the full buffer size.
-	 * Transaction is processing.
-	 */
-	if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_IBF)) {
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-		/* Record the sent bytes within 256B boundary */
-		shi_params.bytes_in_256b = (shi_params.bytes_in_256b +
-				SHI_OBUF_FULL_SIZE) % SHI_BYPASS_BOUNDARY;
-#endif
-		if (state == SHI_STATE_RECEIVING) {
-			/* read data from input to msg buffer */
-			shi_read_half_inbuf();
-			/* Read to bottom address again */
-			shi_params.rx_buf = SHI_IBUF_START_ADDR;
-			return shi_handle_host_package();
-		} else if (state == SHI_STATE_SENDING)
-			/* Write data from msg buffer to output buffer */
-			if (shi_params.tx_buf == SHI_OBUF_START_ADDR +
-					SHI_OBUF_HALF_SIZE)
-				return shi_write_half_outbuf();
-			else /* ignore it */
-				return;
-		else if (state == SHI_STATE_PROCESSING
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-				|| state == SHI_STATE_WAIT_ALIGNMENT
-#endif
-				)
-			/* Wait for host handles request */
-			return;
-		else
-			/* Unexpected status */
-			log_unexpected_state("IBF");
-	}
-}
-DECLARE_IRQ(NPCX_IRQ_SHI, shi_int_handler, 2);
-
-/* Handle an CS assert event on the SHI_CS_L pin */
-void shi_cs_event(enum gpio_signal signal)
-{
-#ifdef NPCX_SHI_V2
-	/*
-	 * New SHI module handles the CS low event in the SHI module interrupt
-	 * handler (checking CSNFE bit) instead of in GPIO(MIWU) interrupt
-	 * handler. But there is still a need to configure the MIWU to generate
-	 * event to wake up EC from deep sleep. Immediately return to bypass
-	 * the CS low interrupt event from MIWU module.
-	 */
-	return;
-#else
-	shi_handle_cs_assert();
-#endif
-
-}
-
-/*****************************************************************************/
-/* Hook functions for chipset and initialization */
-
-/*
- * Reset SHI bus and prepare next transaction
- * Please make sure it is executed when there're no spi transactions
- */
-static void shi_reset_prepare(void)
-{
-	uint16_t i;
-
-	/* We no longer care about SHI interrupts, so disable them. */
-	task_disable_irq(NPCX_IRQ_SHI);
-
-	/* Disable SHI unit to clear all status bits */
-	CLEAR_BIT(NPCX_SHICFG1, NPCX_SHICFG1_EN);
-
-	/* Initialize parameters of next transaction */
-	shi_params.rx_msg = in_msg;
-	shi_params.tx_msg = out_msg;
-	shi_params.rx_buf = SHI_IBUF_START_ADDR;
-	shi_params.tx_buf = SHI_OBUF_HALF_ADDR;
-	shi_params.sz_received = 0;
-	shi_params.sz_sending = 0;
-	shi_params.sz_request = 0;
-	shi_params.sz_response = 0;
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	shi_params.bytes_in_256b = 0;
-#endif
-	/* Record last IBUFSTAT for glitch case */
-	shi_params.pre_ibufstat = shi_read_buf_pointer();
-
-	/*
-	 * Fill output buffer to indicate we`re
-	 * ready to receive next transaction.
-	 */
-	for (i = 1; i < SHI_OBUF_FULL_SIZE; i++)
-		NPCX_OBUF(i) = EC_SPI_RECEIVING;
-	NPCX_OBUF(0) = EC_SPI_OLD_READY;
-
-	/* Enable SHI & WEN functionality */
-	NPCX_SHICFG1 = 0x85;
-
-	/* Ready to receive */
-	state = SHI_STATE_READY_TO_RECV;
-	last_error_state = -1;
-
-	/* Setup second IBF interrupt and enable SHI's interrupt */
-#ifdef NPCX_SHI_V2
-	shi_sec_ibf_int_enable(1);
-	task_enable_irq(NPCX_IRQ_SHI);
-#endif
-
-	/* Allow deep sleep at the end of SHI transaction */
-	enable_sleep(SLEEP_MASK_SPI);
-
-	DEBUG_CPRINTF("RDY-");
-}
-
-static void shi_enable(void)
-{
-	int gpio_flags;
-
-	shi_reset_prepare();
-
-	/* Ensure SHI_CS_L interrupt is disabled */
-	gpio_disable_interrupt(GPIO_SHI_CS_L);
-
-	/* Enable PU, if requested */
-	gpio_flags = GPIO_INPUT | GPIO_INT_F_FALLING;
-#ifdef NPCX_SHI_CS_PU
-	gpio_flags |= GPIO_PULL_UP;
-#endif
-	gpio_set_flags(GPIO_SHI_CS_L, gpio_flags);
-
-	/*
-	 * Mux SHI related pins
-	 * SHI_SDI SHI_SDO SHI_CS# SHI_SCLK are selected to device pins
-	 */
-	SET_BIT(NPCX_DEVALT(ALT_GROUP_C), NPCX_DEVALTC_SHI_SL);
-
-	task_clear_pending_irq(NPCX_IRQ_SHI);
-
-	/* Enable SHI_CS_L interrupt */
-	gpio_enable_interrupt(GPIO_SHI_CS_L);
-
-	/*
-	 * If CS is already asserted prior to enabling our GPIO interrupt then
-	 * we have missed the falling edge and we need to handle the
-	 * deassertion interrupt.
-	 */
-	task_enable_irq(NPCX_IRQ_SHI);
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, shi_enable, HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, shi_enable, HOOK_PRIO_DEFAULT);
-#endif
-
-static void shi_reenable_on_sysjump(void)
-{
-#if !(DEBUG_SHI)
-	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
-#endif
-		shi_enable();
-}
-/* Call hook after chipset sets initial power state */
-DECLARE_HOOK(HOOK_INIT,
-	     shi_reenable_on_sysjump,
-	     HOOK_PRIO_INIT_CHIPSET + 1);
-
-/* Disable SHI bus */
-static void shi_disable(void)
-{
-	state = SHI_STATE_DISABLED;
-
-	task_disable_irq(NPCX_IRQ_SHI);
-
-	/* Disable SHI_CS_L interrupt */
-	gpio_disable_interrupt(GPIO_SHI_CS_L);
-
-	/* Restore SHI_CS_L back to default state */
-	gpio_reset(GPIO_SHI_CS_L);
-
-	/*
-	 * Mux SHI related pins
-	 * SHI_SDI SHI_SDO SHI_CS# SHI_SCLK are selected to GPIO
-	 */
-	CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_C), NPCX_DEVALTC_SHI_SL);
-
-	/*
-	 * Allow deep sleep again in case CS dropped before ec was
-	 * informed in hook function and turn off SHI's interrupt in time.
-	 */
-	enable_sleep(SLEEP_MASK_SPI);
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND_COMPLETE, shi_disable, HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, shi_disable, HOOK_PRIO_DEFAULT);
-#endif
-DECLARE_HOOK(HOOK_SYSJUMP, shi_disable, HOOK_PRIO_DEFAULT);
-
-static void shi_init(void)
-{
-	/* Power on SHI module first */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_SHI_PD);
-
-#ifdef NPCX_SHI_V2
-	/* Enable SHI module Version 2 */
-	SET_BIT(NPCX_DEVALT(ALT_GROUP_F), NPCX_DEVALTF_SHI_NEW);
-#endif
-
-	/*
-	 * SHICFG1 (SHI Configuration 1) setting
-	 * [7] - IWRAP	= 1: Wrap input buffer to the first address
-	 * [6] - CPOL	= 0: Sampling on rising edge and output on falling edge
-	 * [5] - DAS	= 0: return STATUS reg data after Status command
-	 * [4] - AUTOBE	= 0: Automatically update the OBES bit in STATUS reg
-	 * [3] - AUTIBF	= 0: Automatically update the IBFS bit in STATUS reg
-	 * [2] - WEN    = 0: Enable host write to input buffer
-	 * [1] - Reserved 0
-	 * [0] - ENABLE	= 0: Disable SHI at the beginning
-	 */
-	NPCX_SHICFG1 = 0x80;
-
-	/*
-	 * SHICFG2 (SHI Configuration 2) setting
-	 * [7] - Reserved 0
-	 * [6] - REEVEN = 0: Restart events are not used
-	 * [5] - Reserved 0
-	 * [4] - REEN   = 0: Restart transactions are not used
-	 * [3] - SLWU   = 0: Seem-less wake-up is enabled by default
-	 * [2] - ONESHOT= 0: WEN is cleared at the end of a write transaction
-	 * [1] - BUSY   = 0: SHI bus is busy 0: idle.
-	 * [0] - SIMUL	= 1: Turn on simultaneous Read/Write
-	 */
-	NPCX_SHICFG2 = 0x01;
-
-	/*
-	 * EVENABLE (Event Enable) setting
-	 * [7] - IBOREN = 0: Input buffer overrun interrupt enable
-	 * [6] - STSREN = 0: status read interrupt disable
-	 * [5] - EOWEN  = 0: End-of-Data for Write Transaction Interrupt Enable
-	 * [4] - EOREN  = 1: End-of-Data for Read Transaction Interrupt Enable
-	 * [3] - IBHFEN = 1: Input Buffer Half Full Interrupt Enable
-	 * [2] - IBFEN  = 1: Input Buffer Full Interrupt Enable
-	 * [1] - OBHEEN = 0: Output Buffer Half Empty Interrupt Enable
-	 * [0] - OBEEN  = 0: Output Buffer Empty Interrupt Enable
-	 */
-	NPCX_EVENABLE = 0x1C;
-
-#ifdef NPCX_SHI_V2
-	/*
-	 * EVENABLE2 (Event Enable 2) setting
-	 * [2] - CSNFEEN = 1: SHI_CS Falling Edge Interrupt Enable
-	 * [1] - CSNREEN = 1: SHI_CS Rising Edge Interrupt Enable
-	 * [0] - IBHF2EN = 0: Input Buffer Half Full 2 Interrupt Enable
-	 */
-	NPCX_EVENABLE2 = 0x06;
-#endif
-
-	/* Clear SHI events status register */
-	NPCX_EVSTAT = 0XFF;
-}
-/* Call hook before chipset sets initial power state and calls resume hooks */
-DECLARE_HOOK(HOOK_INIT, shi_init, HOOK_PRIO_INIT_CHIPSET - 1);
-
-/**
- * Get protocol information
- */
-static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = SHI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = SHI_MAX_RESPONSE_SIZE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info,
-EC_VER_MASK(0));
diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h
deleted file mode 100644
index c14aec196e..0000000000
--- a/chip/npcx/shi_chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific SHI module for Chrome EC */
-
-#ifndef SHI_CHIP_H_
-#define SHI_CHIP_H_
-
-#ifdef CONFIG_HOSTCMD_SHI
-/**
- * Called when the NSS level changes, signalling the start of a SHI
- * transaction.
- *
- * @param signal	GPIO signal that changed
- */
-void shi_cs_event(enum gpio_signal signal);
-#ifdef NPCX_SHI_V2
-void shi_cs_gpio_int(enum gpio_signal signal);
-#endif
-#endif
-
-#endif /* SHI_CHIP_H_ */
diff --git a/chip/npcx/sib.c b/chip/npcx/sib.c
deleted file mode 100644
index b8e2e17955..0000000000
--- a/chip/npcx/sib.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific SIB module for Chrome EC */
-
-#include "console.h"
-#include "hwtimer_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/*
- * Timeout to wait for host transaction to be completed.
- *
- * For eSPI - it is 200 us.
- * For LPC - it is 5 us.
- */
-#ifdef CONFIG_HOSTCMD_ESPI
-#define HOST_TRANSACTION_TIMEOUT_US 200
-#else
-#define HOST_TRANSACTION_TIMEOUT_US 5
-#endif
-
-/* Console output macros */
-#ifdef DEBUG_SIB
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#else
-#define CPUTS(...)
-#define CPRINTS(...)
-#endif
-
-/*
- * Check host read is not in-progress and no timeout
- */
-static void sib_wait_host_read_done(void)
-{
-	timestamp_t deadline, start;
-
-	start = get_time();
-	deadline.val = start.val + HOST_TRANSACTION_TIMEOUT_US;
-	while (IS_BIT_SET(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD)) {
-		if (timestamp_expired(deadline, NULL)) {
-			CPRINTS("Unexpected time of host read transaction");
-			break;
-		}
-		/* Handle ITIM32 overflow condition */
-		__hw_clock_handle_overflow(start.le.hi);
-	}
-}
-
-/*
- * Check host write is not in-progress and no timeout
- */
-static void sib_wait_host_write_done(void)
-{
-	timestamp_t deadline, start;
-
-	start = get_time();
-	deadline.val = start.val + HOST_TRANSACTION_TIMEOUT_US;
-	while (IS_BIT_SET(NPCX_SIBCTRL, NPCX_SIBCTRL_CSWR)) {
-		if (timestamp_expired(deadline, NULL)) {
-			CPRINTS("Unexpected time of host write transaction");
-			break;
-		}
-		/* Handle ITIM32 overflow condition */
-		__hw_clock_handle_overflow(start.le.hi);
-	}
-}
-
-/* Emulate host to read Keyboard I/O */
-uint8_t sib_read_kbc_reg(uint8_t io_offset)
-{
-	uint8_t data_value;
-
-	/* Disable interrupts */
-	interrupt_disable();
-
-	/* Lock host keyboard module */
-	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD);
-	/* Verify Core read/write to host modules is not in progress */
-	sib_wait_host_read_done();
-	sib_wait_host_write_done();
-	/* Enable Core access to keyboard module */
-	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_HIKBDAE);
-
-	/* Specify the io_offset A0 = 0. the index register is accessed */
-	NPCX_IHIOA = io_offset;
-
-	/* Start a Core read from host module */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD);
-	/* Wait while Core read operation is in progress */
-	sib_wait_host_read_done();
-	/* Read the data */
-	data_value = NPCX_IHD;
-
-	/* Disable Core access to keyboard module */
-	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_HIKBDAE);
-	/* unlock host keyboard module */
-	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD);
-
-	/* Enable interrupts */
-	interrupt_enable();
-
-	return data_value;
-}
-
-/* Super-IO read/write function */
-void sib_write_reg(uint8_t io_offset, uint8_t index_value,
-		uint8_t io_data)
-{
-	/* Disable interrupts */
-	interrupt_disable();
-
-	/* Lock host CFG module */
-	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-	/* Enable Core access to CFG module */
-	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* Verify Core read/write to host modules is not in progress */
-	sib_wait_host_read_done();
-	sib_wait_host_write_done();
-
-	/* Specify the io_offset A0 = 0. the index register is accessed */
-	NPCX_IHIOA = io_offset;
-	/* Write the data. This starts the write access to the host module */
-	NPCX_IHD = index_value;
-	/* Wait while Core write operation is in progress */
-	sib_wait_host_write_done();
-
-	/* Specify the io_offset A0 = 1. the data register is accessed */
-	NPCX_IHIOA = io_offset+1;
-	/* Write the data. This starts the write access to the host module */
-	NPCX_IHD = io_data;
-	/* Wait while Core write operation is in progress */
-	sib_wait_host_write_done();
-
-	/* Disable Core access to CFG module */
-	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* unlock host CFG  module */
-	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-
-	/* Enable interrupts */
-	interrupt_enable();
-}
-
-uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value)
-{
-	uint8_t data_value;
-
-	/* Disable interrupts */
-	interrupt_disable();
-
-	/* Lock host CFG module */
-	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-	/* Enable Core access to CFG module */
-	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* Verify Core read/write to host modules is not in progress */
-	sib_wait_host_read_done();
-	sib_wait_host_write_done();
-
-	/* Specify the io_offset A0 = 0. the index register is accessed */
-	NPCX_IHIOA = io_offset;
-	/* Write the data. This starts the write access to the host module */
-	NPCX_IHD = index_value;
-	/* Wait while Core write operation is in progress */
-	sib_wait_host_write_done();
-
-	/* Specify the io_offset A0 = 1. the data register is accessed */
-	NPCX_IHIOA = io_offset+1;
-	/* Start a Core read from host module */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD);
-	/* Wait while Core read operation is in progress */
-	sib_wait_host_read_done();
-	/* Read the data */
-	data_value = NPCX_IHD;
-
-	/* Disable Core access to CFG module */
-	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* unlock host CFG  module */
-	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-
-	/* Enable interrupts */
-	interrupt_enable();
-
-	return data_value;
-}
-
diff --git a/chip/npcx/sib_chip.h b/chip/npcx/sib_chip.h
deleted file mode 100644
index 2341f219b4..0000000000
--- a/chip/npcx/sib_chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific SIB module for Chrome EC */
-
-/* Super-IO index and register definitions */
-#define INDEX_SID       0x20
-#define INDEX_CHPREV    0x24
-#define INDEX_SRID      0x27
-
-#define SIO_OFFSET      0x4E
-
-/* Super-IO register write function */
-void sib_write_reg(uint8_t io_offset, uint8_t index_value,
-		uint8_t io_data);
-/* Super-IO register read function */
-uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value);
-/* Emulate host to read Keyboard I/O */
-uint8_t sib_read_kbc_reg(uint8_t io_offset);
-
diff --git a/chip/npcx/spi.c b/chip/npcx/spi.c
deleted file mode 100644
index 55fa8f85ab..0000000000
--- a/chip/npcx/spi.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI module for Chrome EC */
-
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "clock.h"
-#include "clock_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#if !DEBUG_SPI
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#endif
-
-/* SPI IP as SPI controller */
-#define SPI_CLK         8000000
-/**
- * Clear SPI data buffer.
- *
- * @param none
- * @return none.
- */
-static void clear_databuf(void)
-{
-	volatile uint8_t unused __attribute__((unused));
-	while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
-		unused = NPCX_SPI_DATA;
-}
-
-/**
- * Preset SPI operation clock.
- *
- * @param   none
- * @return  none
- * @notes   changed when initial or HOOK_FREQ_CHANGE command
- */
-void spi_freq_changed(void)
-{
-	uint8_t prescaler_divider    = 0;
-
-	/* Set clock prescaler divider to SPI module*/
-	prescaler_divider = (uint8_t)((uint32_t)clock_get_apb2_freq()
-			/ 2 / SPI_CLK);
-	if (prescaler_divider >= 1)
-		prescaler_divider = prescaler_divider - 1;
-	if (prescaler_divider > 0x7F)
-		prescaler_divider = 0x7F;
-
-	/* Set core clock division factor in order to obtain the SPI clock */
-	NPCX_SPI_CTL1 = (NPCX_SPI_CTL1&(~(((1<<7)-1)<<NPCX_SPI_CTL1_SCDV)))
-			|(prescaler_divider<<NPCX_SPI_CTL1_SCDV);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, spi_freq_changed, HOOK_PRIO_FIRST);
-
-/**
- * Set SPI enabled.
- *
- * @spi_device SPI device to act on.
- * @param   enable enabled flag
- * @return  success
- */
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	enum gpio_signal gpio;
-
-	if (enable) {
-		/* Enabling spi module for gpio configuration */
-		gpio_config_module(MODULE_SPI, 1);
-		/* GPIO No SPI Select */
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
-
-		gpio = spi_device->gpio_cs;
-		/* Make sure CS# is in GPIO output mode. */
-		gpio_set_flags(gpio, GPIO_OUTPUT);
-		/* Make sure CS# is deselected */
-		gpio_set_level(gpio, 1);
-
-		/* Enabling spi module */
-		SET_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
-	} else {
-		/* Disabling spi module */
-		CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
-		gpio = spi_device->gpio_cs;
-		/* Make sure CS# is deselected */
-		gpio_set_level(gpio, 1);
-		gpio_set_flags(gpio, GPIO_ODR_HIGH);
-		/* Disabling spi module for gpio configuration */
-		gpio_config_module(MODULE_SPI, 0);
-		/* GPIO No SPI Select */
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
-	}
-	return EC_SUCCESS;
-}
-
-
-/**
- * Flush an SPI transaction and receive data from peripheral.
- *
- * @param   spi_device  device to talk to
- * @param   txdata  transfer data
- * @param   txlen   transfer length
- * @param   rxdata  receive data
- * @param   rxlen   receive length
- * @return  success
- * @notes   set controller transaction mode in npcx chip
- */
-int spi_transaction(const struct spi_device_t *spi_device,
-		const uint8_t *txdata, int txlen,
-		uint8_t *rxdata, int rxlen)
-{
-	int i = 0;
-	enum gpio_signal gpio = spi_device->gpio_cs;
-	static struct mutex spi_lock;
-
-	mutex_lock(&spi_lock);
-	/* Make sure CS# is a GPIO output mode. */
-	gpio_set_flags(gpio, GPIO_OUTPUT);
-	/* Make sure CS# is deselected */
-	gpio_set_level(gpio, 1);
-	/* Cleaning junk data in the buffer */
-	clear_databuf();
-	/* Assert CS# to start transaction */
-	gpio_set_level(gpio, 0);
-	CPRINTS("NPCX_SPI_DATA=%x", NPCX_SPI_DATA);
-	CPRINTS("NPCX_SPI_CTL1=%x", NPCX_SPI_CTL1);
-	CPRINTS("NPCX_SPI_STAT=%x", NPCX_SPI_STAT);
-	/* Writing the data */
-	for (i = 0; i < txlen; ++i) {
-		/* Making sure we can write */
-		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
-			;
-		/* Write the data */
-		NPCX_SPI_DATA =  txdata[i];
-		CPRINTS("txdata[i]=%x", txdata[i]);
-		/* Waiting till reading is finished */
-		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
-			;
-		/* Reading the (unused) data */
-		clear_databuf();
-	}
-	CPRINTS("write end");
-	/* Reading the data */
-	for (i = 0; i < rxlen; ++i) {
-		/* Making sure we can write */
-		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
-			;
-		/* Write the (unused) data */
-		NPCX_SPI_DATA =  0;
-		/* Wait till reading is finished */
-		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
-			;
-		/* Reading the data */
-		rxdata[i] = (uint8_t)NPCX_SPI_DATA;
-		CPRINTS("rxdata[i]=%x", rxdata[i]);
-	}
-	/* Deassert CS# (high) to end transaction */
-	gpio_set_level(gpio, 1);
-	mutex_unlock(&spi_lock);
-
-	return EC_SUCCESS;
-}
-
-/**
- * SPI initial.
- *
- * @param none
- * @return none
- */
-static void spi_init(void)
-{
-	int i;
-	/* Enable clock for SPI peripheral */
-	clock_enable_peripheral(CGC_OFFSET_SPI, CGC_SPI_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Disabling spi module */
-	for (i = 0; i < spi_devices_used; i++)
-		spi_enable(&spi_devices[i], 0);
-
-	/* Disabling spi irq */
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_EIR);
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_EIW);
-
-	/* Setting clocking mode to normal mode */
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCM);
-	/* Setting 8bit mode transfer */
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_MOD);
-	/* Set core clock division factor in order to obtain the spi clock */
-	spi_freq_changed();
-
-	/* We emit zeros in idle (default behaivor) */
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCIDL);
-
-	CPRINTS("nSPI_COMP=%x", IS_BIT_SET(NPCX_STRPST, NPCX_STRPST_SPI_COMP));
-	CPRINTS("SPI_SP_SEL=%x", IS_BIT_SET(NPCX_DEV_CTL4,
-			NPCX_DEV_CTL4_SPI_SP_SEL));
-	/* Cleaning junk data in the buffer */
-	clear_databuf();
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
-
-/*****************************************************************************/
-/* Console commands */
-#ifdef CONFIG_CMD_SPI_FLASH
-static int printrx(const char *desc, const uint8_t *txdata, int txlen,
-		int rxlen)
-{
-	uint8_t rxdata[32];
-	int rv;
-	int i;
-
-	rv = spi_transaction(SPI_FLASH_DEVICE, txdata, txlen, rxdata, rxlen);
-	if (rv)
-		return rv;
-
-	CPRINTS("%-12s:", desc);
-	for (i = 0; i < rxlen; i++)
-		CPRINTS(" 0x%02x", rxdata[i]);
-	CPUTS("\n");
-	return EC_SUCCESS;
-}
-
-static int command_spirom(int argc, char **argv)
-{
-	uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00};
-	uint8_t txjedec[] = {0x9f};
-	uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00};
-	uint8_t txsr1[] = {0x05};
-	uint8_t txsr2[] = {0x35};
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	printrx("Man/Dev ID", txmandev, sizeof(txmandev), 2);
-	printrx("JEDEC ID", txjedec, sizeof(txjedec), 3);
-	printrx("Unique ID", txunique, sizeof(txunique), 8);
-	printrx("Status reg 1", txsr1, sizeof(txsr1), 1);
-	printrx("Status reg 2", txsr2, sizeof(txsr2), 1);
-
-	spi_enable(SPI_FLASH_DEVICE, 0);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(spirom, command_spirom,
-		NULL,
-		"Test reading SPI EEPROM");
-#endif
diff --git a/chip/npcx/spiflashfw/monitor_hdr.c b/chip/npcx/spiflashfw/monitor_hdr.c
deleted file mode 100644
index 219a037d27..0000000000
--- a/chip/npcx/spiflashfw/monitor_hdr.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX SoC spi flash update tool -  monitor firmware header
- */
-
-#include "config.h"
-#include "npcx_monitor.h"
-
-const struct monitor_header_tag monitor_hdr = {
-	/* 0x00: TAG = 0xA5075001 */
-	NPCX_MONITOR_UUT_TAG,
-	/* 0x04: Size·of·the·EC image·be·programmed.
-	 * Default = code RAM size
-	 */
-	NPCX_PROGRAM_MEMORY_SIZE,
-	/*
-	 * 0x08: The start of RAM address to store the EC image, which will be
-	 * programed into the SPI flash.
-	 */
-	CONFIG_PROGRAM_MEMORY_BASE,
-	/* 0x0C:The Flash start address to be programmed*/
-#ifdef SECTION_IS_RO
-	/* Default: RO image is programed from the start of SPI flash */
-	CONFIG_EC_PROTECTED_STORAGE_OFF,
-#else
-	/* Default: RW image is programed from the half of SPI flash */
-	CONFIG_EC_WRITABLE_STORAGE_OFF,
-#endif
-	/* 0x10: Maximum allowable flash clock frequency */
-	0,
-	/* 0x11: SPI Flash read mode */
-	0,
-	/* 0x12: Reserved */
-	0,
-};
diff --git a/chip/npcx/spiflashfw/npcx_monitor.c b/chip/npcx/spiflashfw/npcx_monitor.c
deleted file mode 100644
index cd52e7a80f..0000000000
--- a/chip/npcx/spiflashfw/npcx_monitor.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX SoC spi flash update tool - monitor firmware
- */
-
-#include <stdint.h>
-#include "config.h"
-#include "npcx_monitor.h"
-#include "registers.h"
-#include "util.h"
-
-/*****************************************************************************/
-/* spi flash internal functions */
-void sspi_flash_pinmux(int enable)
-{
-	if (enable)
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-	else
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-
-	/* CS0/1 pinmux */
-	if (enable) {
-#if (FIU_CHIP_SELECT == 1)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-#elif (FIU_CHIP_SELECT == 2)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-#endif
-	} else {
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-	}
-}
-
-void sspi_flash_tristate(int enable)
-{
-	if (enable) {
-		/* Enable FIU pins to tri-state */
-		SET_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-	} else {
-		/* Disable FIU pins to tri-state */
-		CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-	}
-}
-
-void sspi_flash_execute_cmd(uint8_t code, uint8_t cts)
-{
-	/* set UMA_CODE */
-	NPCX_UMA_CODE = code;
-	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
-	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-		;
-}
-
-void sspi_flash_cs_level(int level)
-{
-	/* level is high */
-	if (level) {
-		/* Set chip select to high */
-		SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
-	} else { /* level is low */
-		/* Set chip select to low */
-		CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
-	}
-}
-
-void sspi_flash_wait_ready(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_BUSY;
-
-	/* Chip Select down. */
-	sspi_flash_cs_level(0);
-	/* Command for Read status register */
-	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
-	do {
-		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
-		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-			;
-	} while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */
-	/* Chip Select high. */
-	sspi_flash_cs_level(1);
-}
-
-int sspi_flash_write_enable(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_WEL;
-	/* Write enable command */
-	sspi_flash_execute_cmd(CMD_WRITE_EN, MASK_CMD_ONLY);
-	/* Wait for flash is not busy */
-	sspi_flash_wait_ready();
-
-	if (NPCX_UMA_DB0 & mask)
-		return 1;
-	else
-		return 0;
-}
-
-void sspi_flash_set_address(uint32_t dest_addr)
-{
-	uint8_t *addr = (uint8_t *)&dest_addr;
-	/* Write address */
-	NPCX_UMA_AB2 = addr[2];
-	NPCX_UMA_AB1 = addr[1];
-	NPCX_UMA_AB0 = addr[0];
-}
-
-void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
-{
-	unsigned int i;
-	/* Chip Select down. */
-	sspi_flash_cs_level(0);
-	/* Set erase address */
-	sspi_flash_set_address(dest_addr);
-	/* Start write */
-	sspi_flash_execute_cmd(CMD_FLASH_PROGRAM, MASK_CMD_WR_ADR);
-	for (i = 0; i < bytes; i++) {
-		sspi_flash_execute_cmd(*data, MASK_CMD_WR_ONLY);
-		data++;
-	}
-	/* Chip Select up */
-	sspi_flash_cs_level(1);
-}
-
-int sspi_flash_physical_clear_stsreg(void)
-{
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-	/* Enable write */
-	sspi_flash_write_enable();
-
-	NPCX_UMA_DB0 = 0x0;
-	NPCX_UMA_DB1 = 0x0;
-
-	/* Write status register 1/2 */
-	sspi_flash_execute_cmd(CMD_WRITE_STATUS_REG, MASK_CMD_WR_2BYTE);
-
-	/* Wait writing completed */
-	sspi_flash_wait_ready();
-
-	/* Read status register 1/2 for checking */
-	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_RD_1BYTE);
-	if (NPCX_UMA_DB0 != 0x00)
-		return 0;
-	sspi_flash_execute_cmd(CMD_READ_STATUS_REG2, MASK_CMD_RD_1BYTE);
-	if (NPCX_UMA_DB0 != 0x00)
-		return 0;
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-
-	return 1;
-}
-
-void sspi_flash_physical_write(int offset, int size, const char *data)
-{
-	int dest_addr = offset;
-	const int sz_page = CONFIG_FLASH_WRITE_IDEAL_SIZE;
-
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-
-	/* Write the data per CONFIG_FLASH_WRITE_IDEAL_SIZE bytes */
-	for (; size >= sz_page; size -= sz_page) {
-		/* Enable write */
-		sspi_flash_write_enable();
-		/* Burst UMA transaction */
-		sspi_flash_burst_write(dest_addr, sz_page, data);
-		/* Wait write completed */
-		sspi_flash_wait_ready();
-
-		data += sz_page;
-		dest_addr += sz_page;
-	}
-
-	/* Handle final partial page, if any */
-	if (size != 0) {
-		/* Enable write */
-		sspi_flash_write_enable();
-		/* Burst UMA transaction */
-		sspi_flash_burst_write(dest_addr, size, data);
-
-		/* Wait write completed */
-		sspi_flash_wait_ready();
-	}
-
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-}
-
-void sspi_flash_physical_erase(int offset, int size)
-{
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-
-	/* Alignment has been checked in upper layer */
-	for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE,
-		offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
-		/* Enable write */
-		sspi_flash_write_enable();
-		/* Set erase address */
-		sspi_flash_set_address(offset);
-		/* Start erase */
-		sspi_flash_execute_cmd(CMD_SECTOR_ERASE, MASK_CMD_ADR);
-
-		/* Wait erase completed */
-		sspi_flash_wait_ready();
-	}
-
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-}
-
-int sspi_flash_verify(int offset, int size, const char *data)
-{
-	int i, result;
-	uint8_t *ptr_flash;
-	uint8_t *ptr_mram;
-	uint8_t cmp_data;
-
-	ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset);
-	ptr_mram  = (uint8_t *)data;
-	result = 1;
-
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-
-	/* Start to verify */
-	for (i = 0; i < size; i++) {
-		cmp_data = ptr_mram ? ptr_mram[i] : 0xFF;
-		if (ptr_flash[i] != cmp_data) {
-			result = 0;
-			break;
-		}
-	}
-
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-	return result;
-}
-
-int sspi_flash_get_image_used(const char *fw_base)
-{
-	const uint8_t *image;
-	int size = MAX(CONFIG_RO_SIZE, CONFIG_RW_SIZE); /* max size is 128KB */
-
-	image = (const uint8_t *)fw_base;
-	/*
-	 * Scan backwards looking for 0xea byte, which is by definition the
-	 * last byte of the image.  See ec.lds.S for how this is inserted at
-	 * the end of the image.
-	 */
-	for (size--; size > 0 && image[size] != 0xea; size--)
-		;
-
-	return size ? size + 1 : 0;  /* 0xea byte IS part of the image */
-
-}
-
-/* Entry function of spi upload function */
-uint32_t  __attribute__ ((section(".startup_text")))
-sspi_flash_upload(int spi_offset, int spi_size)
-{
-	/*
-	 * Flash image has been uploaded to Code RAM
-	 */
-	uint32_t sz_image;
-	uint32_t uut_tag;
-	const char *image_base;
-	uint32_t *flag_upload = (uint32_t *)SPI_PROGRAMMING_FLAG;
-	struct monitor_header_tag *monitor_header =
-		(struct monitor_header_tag *)NPCX_MONITOR_HEADER_ADDR;
-
-	*flag_upload = 0;
-
-	uut_tag = monitor_header->tag;
-	/* If it is UUT tag, read required parameters from header */
-	if (uut_tag == NPCX_MONITOR_UUT_TAG) {
-		sz_image = monitor_header->size;
-		spi_offset = monitor_header->dest_addr;
-		image_base = (const char *)(monitor_header->src_addr);
-	} else {
-		sz_image = spi_size;
-		image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE;
-	}
-
-	/* Unlock & stop watchdog */
-	NPCX_WDSDM = 0x87;
-	NPCX_WDSDM = 0x61;
-	NPCX_WDSDM = 0x63;
-
-	/* UMA Unlock */
-	CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK);
-
-	/*
-	 * If UUT is used, assuming the target is the internal flash.
-	 * Don't switch the pinmux and make sure bit 7 of DEVALT0 is set.
-	 */
-	if (uut_tag == NPCX_MONITOR_UUT_TAG)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-	else
-		/* Set pinmux first */
-		sspi_flash_pinmux(1);
-
-	/* Get size of image automatically */
-	if (sz_image == 0)
-		sz_image = sspi_flash_get_image_used(image_base);
-
-	/* Clear status reg of spi flash for protection */
-	if (sspi_flash_physical_clear_stsreg()) {
-		/* Start to erase */
-		sspi_flash_physical_erase(spi_offset, sz_image);
-		/* Start to write */
-		if (image_base != NULL)
-			sspi_flash_physical_write(spi_offset, sz_image,
-						image_base);
-		/* Verify data */
-		if (sspi_flash_verify(spi_offset, sz_image, image_base))
-			*flag_upload |= 0x02;
-	}
-	if (uut_tag != NPCX_MONITOR_UUT_TAG)
-		/* Disable pinmux */
-		sspi_flash_pinmux(0);
-
-	/* Mark we have finished upload work */
-	*flag_upload |= 0x01;
-
-	/* Return the status back to ROM code is required for UUT */
-	if (uut_tag == NPCX_MONITOR_UUT_TAG)
-		return *flag_upload;
-
-	/* Infinite loop */
-	for (;;)
-		;
-}
-
diff --git a/chip/npcx/spiflashfw/npcx_monitor.h b/chip/npcx/spiflashfw/npcx_monitor.h
deleted file mode 100644
index f4f30454d2..0000000000
--- a/chip/npcx/spiflashfw/npcx_monitor.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_NPCX_MONITOR_H
-#define __CROS_EC_NPCX_MONITOR_H
-
-#include <stdint.h>
-
-#define NPCX_MONITOR_UUT_TAG      0xA5075001
-#define NPCX_MONITOR_HEADER_ADDR  0x200C3000
-
-/* Flag to record the progress of programming SPI flash */
-#define SPI_PROGRAMMING_FLAG     0x200C4000
-
-struct monitor_header_tag {
-	/* offset 0x00: TAG NPCX_MONITOR_TAG */
-	uint32_t tag;
-	/* offset 0x04: Size of the binary being programmed (in bytes) */
-	uint32_t size;
-	/* offset 0x08: The RAM address of the binary to program into the SPI */
-	uint32_t src_addr;
-	/* offset 0x0C: The Flash address to be programmed (Absolute address) */
-	uint32_t dest_addr;
-	/* offset 0x10: Maximum allowable flash clock frequency */
-	uint8_t  max_clock;
-	/* offset 0x11: SPI Flash read mode */
-	uint8_t  read_mode;
-	/* offset 0x12: Reserved */
-	uint16_t reserved;
-} __packed;
-
-#endif /* __CROS_EC_NPCX_MONITOR_H */
diff --git a/chip/npcx/spiflashfw/npcx_monitor.ld b/chip/npcx/spiflashfw/npcx_monitor.ld
deleted file mode 100644
index 03e38b0609..0000000000
--- a/chip/npcx/spiflashfw/npcx_monitor.ld
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX SoC spi flash update tool
- */
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-    CODERAM (rx) : ORIGIN = 0x200C3020, LENGTH = 0xFE0
-}
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(sspi_flash_upload)
-
-
-/* Sections Definitions */
-
-SECTIONS
-{
-    .startup_text :
-    {
-        . = ALIGN(4);
-        *(.startup_text )	/* Startup code */
-        . = ALIGN(4);
-    } >CODERAM
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to CODERAM.
-     */
-    .text :
-    {
-        . = ALIGN(4);
-        *(.text .text.*)			/* all remaining code */
-        *(.rodata .rodata.*)		/* read-only data (constants) */
-    } >CODERAM
-
-    . = ALIGN(4);
-    _etext = .;
-
-    /*
-     * This address is used by the startup code to
-     * initialise the .data section.
-     */
-    _sidata = _etext;
-
-}
diff --git a/chip/npcx/system-npcx5.c b/chip/npcx/system-npcx5.c
deleted file mode 100644
index 4dd12fbae2..0000000000
--- a/chip/npcx/system-npcx5.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdnoreturn.h>
-
-/* System module driver depends on chip series for Chrome EC */
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hwtimer_chip.h"
-#include "mpu.h"
-#include "registers.h"
-#include "rom_chip.h"
-#include "system.h"
-#include "system_chip.h"
-#include "task.h"
-#include "util.h"
-
-/* Begin address of Suspend RAM for hibernate utility */
-uintptr_t __lpram_fw_start = CONFIG_LPRAM_BASE;
-/* Offset of little FW in Suspend Ram for GDMA bypass */
-#define LFW_OFFSET 0x160
-/* Begin address of Suspend RAM for little FW (GDMA utilities). */
-uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET;
-
-/*****************************************************************************/
-/* IC specific low-level driver depends on chip series */
-
-/**
- * Configure address 0x40001600 (Low Power RAM) in the the MPU
- * (Memory Protection Unit) as a "regular" memory
- */
-void system_mpu_config(void)
-{
-	/* Enable MPU */
-	CPU_MPU_CTRL = 0x7;
-
-	/* Create a new MPU Region to allow execution from low-power ram */
-	CPU_MPU_RNR  = REGION_CHIP_RESERVED;
-	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
-	CPU_MPU_RBAR = CONFIG_LPRAM_BASE;         /* Set region base address */
-	/*
-	 * Set region size & attribute and enable region
-	 * [31:29] - Reserved.
-	 * [28]    - XN (Execute Never) = 0
-	 * [27]    - Reserved.
-	 * [26:24] - AP                 = 011 (Full access)
-	 * [23:22] - Reserved.
-	 * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory)
-	 * [15:8]  - SRD                = 0 (Subregions enabled)
-	 * [7:6]   - Reserved.
-	 * [5:1]   - SIZE               = 01001 (1K)
-	 * [0]     - ENABLE             = 1 (enabled)
-	 */
-	CPU_MPU_RASR = 0x03080013;
-}
-
-/**
- * hibernate function in low power ram for npcx5 series.
- */
-noreturn void __keep __attribute__ ((section(".lowpower_ram")))
-__enter_hibernate_in_lpram(void)
-{
-	/*
-	 * TODO (ML): Set stack pointer to upper 512B of Suspend RAM.
-	 * Our bypass needs stack instructions but FW will turn off main ram
-	 * later for better power consumption.
-	 */
-	asm (
-		"ldr r0, =0x40001800\n"
-		"mov sp, r0\n"
-	);
-
-	/* Disable Code RAM first */
-	SET_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_MRFSH_DIS);
-	SET_BIT(NPCX_DISIDL_CTL, NPCX_DISIDL_CTL_RAM_DID);
-
-	/* Set deep idle mode*/
-	NPCX_PMCSR = 0x6;
-
-	/* Enter deep idle, wake-up by GPIOs or RTC */
-	/*
-	 * TODO (ML): Although the probability is small, it still has chance
-	 * to meet the same symptom that CPU's behavior is abnormal after
-	 * wake-up from deep idle.
-	 * Workaround: Apply the same bypass of idle but don't enable interrupt.
-	 */
-	asm (
-		"push {r0-r5}\n"        /* Save needed registers */
-		"ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */
-		"wfi\n"                 /* Wait for int to enter idle */
-		"ldm r0, {r0-r5}\n"     /* Add a delay after WFI */
-		"pop {r0-r5}\n"         /* Restore regs before enabling ints */
-		"isb\n"                 /* Flush the cpu pipeline */
-	);
-
-	/* RTC wake-up */
-	if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO))
-		/*
-		 * Mark wake-up reason for hibernate
-		 * Do not call bbram_data_write directly cause of
-		 * executing in low-power ram
-		 */
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_MTC;
-	else
-		/* Otherwise, we treat it as GPIOs wake-up */
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN;
-
-	/* Start a watchdog reset */
-	NPCX_WDCNT = 0x01;
-	/* Reload and restart Timer 0 */
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
-	/* Wait for timer is loaded and restart */
-	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
-		;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-/**
- * Hibernate function for different Nuvoton chip series.
- */
-void __hibernate_npcx_series(void)
-{
-	int i;
-	void (*__hibernate_in_lpram)(void) =
-			(void(*)(void))(__lpram_fw_start | 0x01);
-
-	/* Enable power for the Low Power RAM */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6);
-
-	/* Enable Low Power RAM */
-	NPCX_LPRAM_CTRL = 1;
-
-	/* Copy the __enter_hibernate_in_lpram instructions to LPRAM */
-	for (i = 0; i < &__flash_lpfw_end - &__flash_lpfw_start; i++)
-		*((uint32_t *)__lpram_fw_start + i) =
-				*(&__flash_lpfw_start + i);
-
-	/* execute hibernate func in LPRAM */
-	__hibernate_in_lpram();
-}
-
-#ifdef CONFIG_EXTERNAL_STORAGE
-/* Sysjump utilities in low power ram for npcx5 series. */
-noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
-__start_gdma(uint32_t exeAddr)
-{
-	/* Enable GDMA now */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/* Start GDMA */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_SOFTREQ);
-
-	/* Wait for transfer to complete/fail */
-	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
-			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		;
-
-	/* Disable GDMA now */
-	CLEAR_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/*
-	 * Failure occurs during GMDA transaction. Let watchdog issue and
-	 * boot from RO region again.
-	 */
-	if (IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		while (1)
-			;
-
-	/*
-	 * Jump to the exeAddr address if needed. Setting bit 0 of address to
-	 * indicate it's a thumb branch for cortex-m series CPU.
-	 */
-	((void (*)(void))(exeAddr | 0x01))();
-
-	/* Should never get here */
-	while (1)
-		;
-}
-
-/* Bypass for GMDA issue of ROM api utilities only on npcx5 series. */
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr)
-{
-	int i;
-	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
-	/*
-	 * GDMA utility in Suspend RAM. Setting bit 0 of address to indicate
-	 * it's a thumb branch for cortex-m series CPU.
-	 */
-	void (*__start_gdma_in_lpram)(uint32_t) =
-			(void(*)(uint32_t))(__lpram_lfw_start | 0x01);
-
-	/*
-	 * Before enabling burst mode for better performance of GDMA, it's
-	 * important to make sure srcAddr, dstAddr and size of transactions
-	 * are 16 bytes aligned in case failure occurs.
-	 */
-	ASSERT((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 &&
-			(dstAddr % chunkSize) == 0);
-
-	/* Check valid address for jumpiing */
-	ASSERT(exeAddr != 0x0);
-
-	/* Enable power for the Low Power RAM */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6);
-
-	/* Enable Low Power RAM */
-	NPCX_LPRAM_CTRL = 1;
-
-	/*
-	 * Initialize GDMA for flash reading.
-	 * [31:21] - Reserved.
-	 * [20]    - GDMAERR   = 0  (Indicate GMDA transfer error)
-	 * [19]    - Reserved.
-	 * [18]    - TC        = 0  (Terminal Count. Indicate operation is end.)
-	 * [17]    - Reserved.
-	 * [16]    - SOFTREQ   = 0  (Don't trigger here)
-	 * [15]    - DM        = 0  (Set normal demand mode)
-	 * [14]    - Reserved.
-	 * [13:12] - TWS.      = 10 (One double-word for every GDMA transaction)
-	 * [11:10] - Reserved.
-	 * [9]     - BME       = 1  (4-data ie.16 bytes - Burst mode enable)
-	 * [8]     - SIEN      = 0  (Stop interrupt disable)
-	 * [7]     - SAFIX     = 0  (Fixed source address)
-	 * [6]     - Reserved.
-	 * [5]     - SADIR     = 0  (Source address incremented)
-	 * [4]     - DADIR     = 0  (Destination address incremented)
-	 * [3:2]   - GDMAMS    = 00 (Software mode)
-	 * [1]     - Reserved.
-	 * [0]     - ENABLE    = 0  (Don't enable yet)
-	 */
-	NPCX_GDMA_CTL = 0x00002200;
-
-	/* Set source base address */
-	NPCX_GDMA_SRCB = CONFIG_MAPPED_STORAGE_BASE + srcAddr;
-
-	/* Set destination base address */
-	NPCX_GDMA_DSTB = dstAddr;
-
-	/* Set number of transfers */
-	NPCX_GDMA_TCNT = (size / chunkSize);
-
-	/* Clear Transfer Complete event */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC);
-
-	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
-	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
-		*((uint32_t *)__lpram_lfw_start + i) =
-				*(&__flash_lplfw_start + i);
-
-	/* Start GDMA in Suspend RAM */
-	__start_gdma_in_lpram(exeAddr);
-}
-#endif /* CONFIG_EXTERNAL_STORAGE */
diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c
deleted file mode 100644
index 89b3e25e9b..0000000000
--- a/chip/npcx/system-npcx7.c
+++ /dev/null
@@ -1,392 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdnoreturn.h>
-
-/* System module driver depends on chip series for Chrome EC */
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "lct_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "gpio.h"
-#include "hwtimer_chip.h"
-#include "mpu.h"
-#include "system_chip.h"
-#include "rom_chip.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Macros for last 32K ram block */
-#define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1)
-/* Higher bits are reserved and need to be masked */
-#define RAM_PD_MASK  (~BIT(LAST_RAM_BLK))
-
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-#define LFW_OFFSET 0x160
-/* Begin address of Suspend RAM for little FW (GDMA utilities). */
-uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET;
-#endif
-/*****************************************************************************/
-/* IC specific low-level driver depends on chip series */
-
-/*
- * Configure address 0x40001600 (Low Power RAM) in the the MPU
- * (Memory Protection Unit) as a "regular" memory
- */
-void system_mpu_config(void)
-{
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-	/*
-	 * npcx9 Rev.1 has the problem for download_from_flash API.
-	 * Workwaroud it by by the system_download_from_flash function
-	 * in the suspend RAM like npcx5.
-	 * TODO: Remove this when A2 chip is available
-	 */
-	/* Enable MPU */
-	CPU_MPU_CTRL = 0x7;
-
-	/* Create a new MPU Region to allow execution from low-power ram */
-	CPU_MPU_RNR  = REGION_CHIP_RESERVED;
-	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
-	CPU_MPU_RBAR = CONFIG_LPRAM_BASE;         /* Set region base address */
-	/*
-	 * Set region size & attribute and enable region
-	 * [31:29] - Reserved.
-	 * [28]    - XN (Execute Never) = 0
-	 * [27]    - Reserved.
-	 * [26:24] - AP                 = 011 (Full access)
-	 * [23:22] - Reserved.
-	 * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory)
-	 * [15:8]  - SRD                = 0 (Subregions enabled)
-	 * [7:6]   - Reserved.
-	 * [5:1]   - SIZE               = 01001 (1K)
-	 * [0]     - ENABLE             = 1 (enabled)
-	 */
-	CPU_MPU_RASR = 0x03080013;
-#endif
-}
-
-#ifdef CONFIG_HIBERNATE_PSL
-#ifndef NPCX_PSL_MODE_SUPPORT
-#error "Do not enable CONFIG_HIBERNATE_PSL if npcx ec doesn't support PSL mode!"
-#endif
-
-static enum psl_pin_t system_gpio_to_psl(enum gpio_signal signal)
-{
-	enum psl_pin_t psl_no;
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (g->port == GPIO_PORT_D && g->mask == MASK_PIN2) /* GPIOD2 */
-		psl_no = PSL_IN1;
-	else if (g->port == GPIO_PORT_0 && (g->mask & 0x07)) /* GPIO00/01/02 */
-		psl_no = GPIO_MASK_TO_NUM(g->mask) + 1;
-	else
-		psl_no = PSL_NONE;
-
-	return psl_no;
-}
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-void system_set_psl_gpo(int level)
-{
-	if (level)
-		SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL);
-	else
-		CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL);
-}
-#endif
-
-void system_enter_psl_mode(void)
-{
-	/* Configure pins from GPIOs to PSL which rely on VSBY power rail. */
-	gpio_config_module(MODULE_PMU, 1);
-
-	/*
-	 * In npcx7, only physical PSL_IN pins can pull PSL_OUT to high and
-	 * reboot ec.
-	 * In npcx9, LCT timeout event can also pull PSL_OUT.
-	 * We won't decide the wake cause now but only mark we are entering
-	 * hibernation via PSL.
-	 * The actual wakeup cause will be checked by the PSL input event bits
-	 * when ec reboots.
-	 */
-	NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL;
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	 /*
-	  * If pulse mode is enabled, the VCC power is turned off by the
-	  * external component (Ex: PMIC) but PSL_OUT. So we can just return
-	  * here.
-	  */
-	if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN))
-		return;
-#endif
-
-	/*
-	 * Pull PSL_OUT (GPIO85) to low to cut off ec's VCC power rail by
-	 * setting bit 5 of PDOUT(8).
-	 */
-	SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5);
-}
-
-/* Hibernate function implemented by PSL (Power Switch Logic) mode. */
-noreturn void __keep __enter_hibernate_in_psl(void)
-{
-	system_enter_psl_mode();
-	/* Spin and wait for PSL cuts power; should never return */
-	while (1)
-		;
-}
-
-static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags)
-{
-	/* Set PSL input events' type as level or edge trigger */
-	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW))
-		CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
-	else if ((flags & GPIO_INT_F_RISING) ||
-		 (flags & GPIO_INT_F_FALLING))
-		SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
-
-	/*
-	 * Set PSL input events' polarity is low (high-to-low) active or
-	 * high (low-to-high) active
-	 */
-	if (flags & GPIO_HIB_WAKE_HIGH)
-		SET_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin);
-	else
-		CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin);
-}
-
-int system_config_psl_mode(enum gpio_signal signal)
-{
-	enum psl_pin_t psl_no;
-	const struct gpio_info *g = gpio_list + signal;
-
-	psl_no = system_gpio_to_psl(signal);
-	if (psl_no == PSL_NONE)
-		return 0;
-
-	system_psl_type_sel(psl_no, g->flags);
-	return 1;
-}
-
-#else
-/**
- * Hibernate function in last 32K ram block for npcx7 series.
- * Do not use global variable since we also turn off data ram.
- */
-noreturn void __keep __attribute__ ((section(".after_init")))
-__enter_hibernate_in_last_block(void)
-{
-	/*
-	 * The hibernate utility is located in the last block of RAM. The size
-	 * of each RAM block is 32KB. We turn off all blocks except last one
-	 * for better power consumption.
-	 */
-	NPCX_RAM_PD(0) = RAM_PD_MASK & 0xFF;
-#if defined(CHIP_FAMILY_NPCX7)
-	NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x0F;
-#elif defined(CHIP_FAMILY_NPCX9)
-	NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x7F;
-#endif
-
-	/* Set deep idle mode */
-	NPCX_PMCSR = 0x6;
-
-	/* Enter deep idle, wake-up by GPIOs or RTC */
-	asm volatile ("wfi");
-
-	/* RTC wake-up */
-	if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO))
-		/*
-		 * Mark wake-up reason for hibernate
-		 * Do not call bbram_data_write directly cause of
-		 * no stack.
-		 */
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_MTC;
-#ifdef NPCX_LCT_SUPPORT
-	else if (IS_BIT_SET(NPCX_LCTSTAT, NPCX_LCTSTAT_EVST)) {
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_LCT;
-		/* Clear LCT event */
-		NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST);
-	}
-#endif
-	else
-		/* Otherwise, we treat it as GPIOs wake-up */
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN;
-
-	/* Start a watchdog reset */
-	NPCX_WDCNT = 0x01;
-	/* Reload and restart Timer 0 */
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
-	/* Wait for timer is loaded and restart */
-	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
-		;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-#endif
-
-/**
- * Hibernate function for different Nuvoton chip series.
- */
-void __hibernate_npcx_series(void)
-{
-#ifdef CONFIG_HIBERNATE_PSL
-	__enter_hibernate_in_psl();
-#else
-	/* Make sure this is located in the last 32K code RAM block */
-	ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE
-								< (32*1024));
-
-	/* Execute hibernate func in last 32K block */
-	__enter_hibernate_in_last_block();
-#endif
-}
-
-#if defined(CONFIG_HIBERNATE_PSL)
-static void report_psl_wake_source(void)
-{
-	if (!(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE))
-		return;
-
-	CPRINTS("PSL_CTS: 0x%x", NPCX_GLUE_PSL_CTS & 0xf);
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	CPRINTS("PSL_MCTL1 event: 0x%x", NPCX_GLUE_PSL_MCTL1 & 0x18);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, report_psl_wake_source, HOOK_PRIO_DEFAULT);
-#endif
-
-/*
- * npcx9 Rev.1 has the problem for download_from_flash API.
- * Workwaroud it by executing the system_download_from_flash function
- * in the suspend RAM like npcx5.
- * TODO: Removing npcx9 when Rev.2 is available.
- */
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-#ifdef CONFIG_EXTERNAL_STORAGE
-/* Sysjump utilities in low power ram for npcx9 series. */
-noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
-__start_gdma(uint32_t exeAddr)
-{
-	/* Enable GDMA now */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/* Start GDMA */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_SOFTREQ);
-
-	/* Wait for transfer to complete/fail */
-	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
-			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		;
-
-	/* Disable GDMA now */
-	CLEAR_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/*
-	 * Failure occurs during GMDA transaction. Let watchdog issue and
-	 * boot from RO region again.
-	 */
-	if (IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		while (1)
-			;
-
-	/*
-	 * Jump to the exeAddr address if needed. Setting bit 0 of address to
-	 * indicate it's a thumb branch for cortex-m series CPU.
-	 */
-	((void (*)(void))(exeAddr | 0x01))();
-
-	/* Should never get here */
-	while (1)
-		;
-}
-
-/* Bypass for GMDA issue of ROM api utilities only on npcx5 series. */
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr)
-{
-	int i;
-	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
-	/*
-	 * GDMA utility in Suspend RAM. Setting bit 0 of address to indicate
-	 * it's a thumb branch for cortex-m series CPU.
-	 */
-	void (*__start_gdma_in_lpram)(uint32_t) =
-			(void(*)(uint32_t))(__lpram_lfw_start | 0x01);
-
-	/*
-	 * Before enabling burst mode for better performance of GDMA, it's
-	 * important to make sure srcAddr, dstAddr and size of transactions
-	 * are 16 bytes aligned in case failure occurs.
-	 */
-	ASSERT((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 &&
-			(dstAddr % chunkSize) == 0);
-
-	/* Check valid address for jumpiing */
-	ASSERT(exeAddr != 0x0);
-
-	/* Enable power for the Low Power RAM */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6);
-
-	/* Enable Low Power RAM */
-	NPCX_LPRAM_CTRL = 1;
-
-	/*
-	 * Initialize GDMA for flash reading.
-	 * [31:21] - Reserved.
-	 * [20]    - GDMAERR   = 0  (Indicate GMDA transfer error)
-	 * [19]    - Reserved.
-	 * [18]    - TC        = 0  (Terminal Count. Indicate operation is end.)
-	 * [17]    - Reserved.
-	 * [16]    - SOFTREQ   = 0  (Don't trigger here)
-	 * [15]    - DM        = 0  (Set normal demand mode)
-	 * [14]    - Reserved.
-	 * [13:12] - TWS.      = 10 (One double-word for every GDMA transaction)
-	 * [11:10] - Reserved.
-	 * [9]     - BME       = 1  (4-data ie.16 bytes - Burst mode enable)
-	 * [8]     - SIEN      = 0  (Stop interrupt disable)
-	 * [7]     - SAFIX     = 0  (Fixed source address)
-	 * [6]     - Reserved.
-	 * [5]     - SADIR     = 0  (Source address incremented)
-	 * [4]     - DADIR     = 0  (Destination address incremented)
-	 * [3:2]   - GDMAMS    = 00 (Software mode)
-	 * [1]     - Reserved.
-	 * [0]     - ENABLE    = 0  (Don't enable yet)
-	 */
-	NPCX_GDMA_CTL = 0x00002200;
-
-	/* Set source base address */
-	NPCX_GDMA_SRCB = CONFIG_MAPPED_STORAGE_BASE + srcAddr;
-
-	/* Set destination base address */
-	NPCX_GDMA_DSTB = dstAddr;
-
-	/* Set number of transfers */
-	NPCX_GDMA_TCNT = (size / chunkSize);
-
-	/* Clear Transfer Complete event */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC);
-
-	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
-	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
-		*((uint32_t *)__lpram_lfw_start + i) =
-				*(&__flash_lplfw_start + i);
-
-	/* Start GDMA in Suspend RAM */
-	__start_gdma_in_lpram(exeAddr);
-}
-#endif /* CONFIG_EXTERNAL_STORAGE */
-#endif
diff --git a/chip/npcx/system-npcx9.c b/chip/npcx/system-npcx9.c
deleted file mode 120000
index 48088614a0..0000000000
--- a/chip/npcx/system-npcx9.c
+++ /dev/null
@@ -1 +0,0 @@
-system-npcx7.c
\ No newline at end of file
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
deleted file mode 100644
index ac7056330f..0000000000
--- a/chip/npcx/system.c
+++ /dev/null
@@ -1,1437 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : NPCX hardware specific implementation */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "hwtimer_chip.h"
-#include "lct_chip.h"
-#include "registers.h"
-#include "rom_chip.h"
-#include "sib_chip.h"
-#include "system.h"
-#include "system_chip.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Delay after writing TTC for value to latch */
-#define MTC_TTC_LOAD_DELAY_US 250
-#define MTC_ALARM_MASK     (BIT(25) - 1)
-#define MTC_WUI_GROUP      MIWU_GROUP_4
-#define MTC_WUI_MASK       MASK_PIN7
-
-/* ROM address of chip revision */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-#define CHIP_REV_ADDR        0x0000FFFC
-#define CHIP_REV_STR_SIZE    12
-#else
-#define CHIP_REV_ADDR        0x00007FFC
-#define CHIP_REV_STR_SIZE    6
-#endif
-
-/*  Legacy SuperI/O Configuration D register offset */
-#define SIOCFD_REG_OFFSET    0x2D
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#if defined(NPCX_LCT_SUPPORT)
-/* A flag for waking up from hibernate mode by RTC overflow event */
-static int is_rtc_overflow_event;
-#endif
-
-/*****************************************************************************/
-/* Internal functions */
-
-void system_watchdog_reset(void)
-{
-	/* Unlock & stop watchdog registers */
-	watchdog_stop_and_unlock();
-
-	/* Reset TWCFG */
-	NPCX_TWCFG = 0;
-	/* Select T0IN clock as watchdog prescaler clock */
-	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDCT0I);
-
-	/* Clear watchdog reset status initially*/
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS);
-
-	/* Keep prescaler ratio timer0 clock to 1:1 */
-	NPCX_TWCP = 0x00;
-
-	/* Set internal counter and prescaler */
-	NPCX_TWDT0 = 0x00;
-	NPCX_WDCNT = 0x01;
-
-	/* Disable interrupt */
-	interrupt_disable();
-	/* Reload and restart Timer 0*/
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
-	/* Wait for timer is loaded and restart */
-	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
-		;
-	/* Enable interrupt */
-	interrupt_enable();
-}
-
-/* Return true if index is stored as a single byte in bbram */
-static int bbram_is_byte_access(enum bbram_data_index index)
-{
-	return index == BBRM_DATA_INDEX_PD0 ||
-	       index == BBRM_DATA_INDEX_PD1 ||
-	       index == BBRM_DATA_INDEX_PD2 ||
-	       index == BBRM_DATA_INDEX_PANIC_FLAGS;
-}
-
-/* Check and clear BBRAM status on any reset */
-void system_check_bbram_on_reset(void)
-{
-	if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR)) {
-		/*
-		 * If the reset cause is not power-on reset and VBAT has ever
-		 * dropped, print a warning message.
-		 */
-		if (IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH) ||
-			IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS))
-			CPRINTF("VBAT drop!\n");
-
-		/*
-		 * npcx5/npcx7m6g/npcx7m6f:
-		 *   Clear IBBR bit
-		 * npcx7m6fb/npcx7m6fc/npcx7m7fc/npcx7m7wb/npcx7m7wc:
-		 *   Clear IBBR/VSBY_STS/VCC1_STS bit
-		 */
-		NPCX_BKUP_STS = NPCX_BKUP_STS_ALL_MASK;
-	}
-}
-
-/* Check index is within valid BBRAM range and IBBR is not set */
-static int bbram_valid(enum bbram_data_index index, int bytes)
-{
-	/* Check index */
-	if (index < 0 || index + bytes > NPCX_BBRAM_SIZE)
-		return 0;
-
-	/* Check BBRAM is valid */
-	if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR)) {
-		NPCX_BKUP_STS = BIT(NPCX_BKUP_STS_IBBR);
-		panic_printf("IBBR set: BBRAM corrupted!\n");
-		return 0;
-	}
-	return 1;
-}
-
-/**
- * Read battery-backed ram (BBRAM) at specified index.
- *
- * @return The value of the register or 0 if invalid index.
- */
-static uint32_t bbram_data_read(enum bbram_data_index index)
-{
-	uint32_t value = 0;
-	int bytes = bbram_is_byte_access(index) ? 1 : 4;
-
-	if (!bbram_valid(index, bytes))
-		return 0;
-
-	/* Read BBRAM */
-	if (bytes == 4) {
-		value += NPCX_BBRAM(index + 3);
-		value = value << 8;
-		value += NPCX_BBRAM(index + 2);
-		value = value << 8;
-		value += NPCX_BBRAM(index + 1);
-		value = value << 8;
-	}
-	value += NPCX_BBRAM(index);
-
-	return value;
-}
-
-/**
- * Write battery-backed ram (BBRAM) at specified index.
- *
- * @return nonzero if error.
- */
-static int bbram_data_write(enum bbram_data_index index, uint32_t value)
-{
-	int bytes = bbram_is_byte_access(index) ? 1 : 4;
-
-	if (!bbram_valid(index, bytes))
-		return EC_ERROR_INVAL;
-
-	/* Write BBRAM */
-	NPCX_BBRAM(index) = value & 0xFF;
-	if (bytes == 4) {
-		NPCX_BBRAM(index + 1) = (value >> 8)  & 0xFF;
-		NPCX_BBRAM(index + 2) = (value >> 16) & 0xFF;
-		NPCX_BBRAM(index + 3) = (value >> 24) & 0xFF;
-	}
-
-	/* Wait for write-complete */
-	return EC_SUCCESS;
-}
-
-/* Map idx to a returned BBRM_DATA_INDEX_*, or return -1 on invalid idx */
-static int bbram_idx_lookup(enum system_bbram_idx idx)
-{
-	if (idx == SYSTEM_BBRAM_IDX_PD0)
-		return BBRM_DATA_INDEX_PD0;
-	if (idx == SYSTEM_BBRAM_IDX_PD1)
-		return BBRM_DATA_INDEX_PD1;
-	if (idx == SYSTEM_BBRAM_IDX_PD2)
-		return BBRM_DATA_INDEX_PD2;
-	if (idx == SYSTEM_BBRAM_IDX_TRY_SLOT)
-		return BBRM_DATA_INDEX_TRY_SLOT;
-	return -1;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int bbram_idx = bbram_idx_lookup(idx);
-
-	if (bbram_idx < 0)
-		return EC_ERROR_INVAL;
-
-	*value = bbram_data_read(bbram_idx);
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	int bbram_idx = bbram_idx_lookup(idx);
-
-	if (bbram_idx < 0)
-		return EC_ERROR_INVAL;
-
-	return bbram_data_write(bbram_idx, value);
-}
-
-/* MTC functions */
-uint32_t system_get_rtc_sec(void)
-{
-	/* Get MTC counter unit:seconds */
-	uint32_t sec = NPCX_TTC;
-	return sec;
-}
-
-void system_set_rtc(uint32_t seconds)
-{
-	/*
-	 * Set MTC counter unit:seconds, write twice to ensure values
-	 * latch to NVMem.
-	 */
-	NPCX_TTC = seconds;
-	udelay(MTC_TTC_LOAD_DELAY_US);
-	NPCX_TTC = seconds;
-	udelay(MTC_TTC_LOAD_DELAY_US);
-}
-
-#ifdef CONFIG_CHIP_PANIC_BACKUP
-/*
- * Following information from panic data is stored in BBRAM:
- *
- * index     |       data
- * ==========|=============
- *   36      |       CFSR
- *   40      |       HFSR
- *   44      |       BFAR
- *   48      |      LREG1
- *   52      |      LREG3
- *   56      |      LREG4
- *   60      |     reserved
- *
- * Above registers are chosen to be saved in case of panic because:
- * 1. CFSR, HFSR and BFAR seem to provide more information about the fault.
- * 2. LREG1, LREG3 and LREG4 store exception, reason and info in case of
- * software panic.
- */
-#define BKUP_CFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 0)
-#define BKUP_HFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 4)
-#define BKUP_BFAR		(BBRM_DATA_INDEX_PANIC_BKUP + 8)
-#define BKUP_LREG1		(BBRM_DATA_INDEX_PANIC_BKUP + 12)
-#define BKUP_LREG3		(BBRM_DATA_INDEX_PANIC_BKUP + 16)
-#define BKUP_LREG4		(BBRM_DATA_INDEX_PANIC_BKUP + 20)
-
-#define BKUP_PANIC_DATA_VALID	BIT(0)
-
-void chip_panic_data_backup(void)
-{
-	struct panic_data *d = panic_get_data();
-
-	if (!d)
-		return;
-
-	bbram_data_write(BKUP_CFSR, d->cm.cfsr);
-	bbram_data_write(BKUP_HFSR, d->cm.hfsr);
-	bbram_data_write(BKUP_BFAR, d->cm.dfsr);
-	bbram_data_write(BKUP_LREG1, d->cm.regs[1]);
-	bbram_data_write(BKUP_LREG3, d->cm.regs[3]);
-	bbram_data_write(BKUP_LREG4, d->cm.regs[4]);
-	bbram_data_write(BBRM_DATA_INDEX_PANIC_FLAGS, BKUP_PANIC_DATA_VALID);
-}
-
-static void chip_panic_data_restore(void)
-{
-	struct panic_data *d;
-
-	/* Ensure BBRAM is valid. */
-	if (!bbram_valid(BKUP_CFSR, 4))
-		return;
-
-	/* Ensure Panic data in BBRAM is valid. */
-	if (!(bbram_data_read(BBRM_DATA_INDEX_PANIC_FLAGS) &
-	      BKUP_PANIC_DATA_VALID))
-		return;
-
-	d = get_panic_data_write();
-
-	memset(d, 0, CONFIG_PANIC_DATA_SIZE);
-	d->magic = PANIC_DATA_MAGIC;
-	d->struct_size = CONFIG_PANIC_DATA_SIZE;
-	d->struct_version = 2;
-	d->arch = PANIC_ARCH_CORTEX_M;
-
-	d->cm.cfsr = bbram_data_read(BKUP_CFSR);
-	d->cm.hfsr = bbram_data_read(BKUP_HFSR);
-	d->cm.dfsr = bbram_data_read(BKUP_BFAR);
-
-	d->cm.regs[1] = bbram_data_read(BKUP_LREG1);
-	d->cm.regs[3] = bbram_data_read(BKUP_LREG3);
-	d->cm.regs[4] = bbram_data_read(BKUP_LREG4);
-
-	/* Reset panic data in BBRAM. */
-	bbram_data_write(BBRM_DATA_INDEX_PANIC_FLAGS, 0);
-}
-#endif /* CONFIG_CHIP_PANIC_BACKUP */
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	bbram_data_write(BBRM_DATA_INDEX_SAVED_RESET_FLAGS, flags);
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return bbram_data_read(BBRM_DATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-static void chip_set_hib_flag(uint32_t *flags, uint32_t hib_wake_flags)
-{
-	/* Hibernate via PSL */
-	if (hib_wake_flags & HIBERNATE_WAKE_PSL) {
-#ifdef NPCX_LCT_SUPPORT
-		if (npcx_lct_is_event_set()) {
-			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
-			/* Is RTC overflow event? */
-			if (bbram_data_read(BBRM_DATA_INDEX_LCT_TIME) ==
-				NPCX_LCT_MAX) {
-				/*
-				 * Mark it as RTC overflow event and handle it
-				 * in hook init function later for logging info.
-				 */
-				is_rtc_overflow_event = 1;
-			}
-			npcx_lct_clear_event();
-			return;
-		}
-#endif
-		*flags |= EC_RESET_FLAG_WAKE_PIN |
-				  EC_RESET_FLAG_HIBERNATE;
-	} else { /* Hibernate via non-PSL */
-#ifdef NPCX_LCT_SUPPORT
-		if (hib_wake_flags & HIBERNATE_WAKE_LCT) {
-			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
-			return;
-		}
-#endif
-		if (hib_wake_flags & HIBERNATE_WAKE_PIN) {
-			*flags |= EC_RESET_FLAG_WAKE_PIN |
-					  EC_RESET_FLAG_HIBERNATE;
-		} else if (hib_wake_flags & HIBERNATE_WAKE_MTC) {
-			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
-		}
-	}
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t hib_wake_flags = bbram_data_read(BBRM_DATA_INDEX_WAKE);
-	uint32_t chip_flags = chip_read_reset_flags();
-	uint32_t flags = chip_flags;
-
-	/* Clear saved reset flags in bbram */
-#ifdef CONFIG_POWER_BUTTON_INIT_IDLE
-	/*
-	 * We're not sure whether we're booting or not. AP_IDLE will be cleared
-	 * on S5->S3 transition.
-	 */
-	chip_flags &= EC_RESET_FLAG_AP_IDLE;
-#else
-	chip_flags = 0;
-#endif
-	/* Clear saved hibernate wake flag in bbram , too */
-	bbram_data_write(BBRM_DATA_INDEX_WAKE, 0);
-
-	chip_set_hib_flag(&flags, hib_wake_flags);
-
-	/* Use scratch bit to check power on reset or VCC1_RST reset */
-	if (!IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH)) {
-#ifdef CONFIG_BOARD_FORCE_RESET_PIN
-		/* Treat all resets as RESET_PIN */
-		flags |= EC_RESET_FLAG_RESET_PIN;
-#else
-		/* Check for VCC1 reset */
-		int reset = IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS);
-
-		/*
-		 * If configured, check the saved flags to see whether
-		 * the previous restart was a power-on, in which case
-		 * treat this restart as a power-on as well.
-		 * This is to workaround the fact that the H1 will
-		 * reset the EC at power up.
-		 */
-		if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON)) {
-			/*
-			 * Reset pin restart rather than power-on, so check
-			 * for any flag set from a previous power-on.
-			 */
-			if (reset) {
-				if (flags & EC_RESET_FLAG_INITIAL_PWR)
-					/*
-					 * The previous restart was a power-on
-					 * so treat this restart as that, and
-					 * clear the flag so later code will
-					 * not wait for the second reset.
-					 */
-					flags =
-					  (flags & ~EC_RESET_FLAG_INITIAL_PWR)
-					   | EC_RESET_FLAG_POWER_ON;
-				else
-					/*
-					 * No previous power-on flag,
-					 * so this is a subsequent restart
-					 * i.e any restarts after the
-					 * second restart caused by the H1.
-					 */
-					flags |= EC_RESET_FLAG_RESET_PIN;
-			} else {
-				flags |= EC_RESET_FLAG_POWER_ON;
-
-				/*
-				 * Power-on restart, so set a flag and save it
-				 * for the next imminent reset. Later code
-				 * will check for this flag and wait for the
-				 * second reset. Waking from PSL hibernate is
-				 * power-on for EC but not for H1, so do not
-				 * wait for the second reset.
-				 */
-				if (!(flags & EC_RESET_FLAG_HIBERNATE)) {
-					flags |= EC_RESET_FLAG_INITIAL_PWR;
-					chip_flags |= EC_RESET_FLAG_INITIAL_PWR;
-				}
-			}
-		} else
-			/*
-			 * No second reset after power-on, so
-			 * set the flags according to the restart reason.
-			 */
-			flags |= reset ? EC_RESET_FLAG_RESET_PIN
-				       : EC_RESET_FLAG_POWER_ON;
-#endif
-	}
-	chip_save_reset_flags(chip_flags);
-
-	/*
-	 * Set scratch bit to distinguish VCC1RST# is asserted again
-	 * or not. This bit will be clear automatically when VCC1RST#
-	 * is asserted or power-on reset occurs
-	 */
-	SET_BIT(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH);
-
-	/* Software debugger reset */
-	if (IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_DBGRST_STS)) {
-		flags |= EC_RESET_FLAG_SOFT;
-		/* Clear debugger reset status initially*/
-		SET_BIT(NPCX_RSTCTL, NPCX_RSTCTL_DBGRST_STS);
-	}
-
-	/* Watchdog Reset */
-	if (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS)) {
-		/*
-		 * Don't set EC_RESET_FLAG_WATCHDOG flag if watchdog is issued
-		 * by system_reset or hibernate in order to distinguish reset
-		 * cause is panic reason or not.
-		 */
-		if (!(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
-				EC_RESET_FLAG_HIBERNATE)))
-			flags |= EC_RESET_FLAG_WATCHDOG;
-
-		/* Clear watchdog reset status initially*/
-		SET_BIT(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS);
-	}
-
-	system_set_reset_flags(flags);
-}
-
-/**
- * Chip-level function to set GPIOs and wake-up inputs for hibernate.
- */
-#ifdef CONFIG_SUPPORT_CHIP_HIBERNATION
-static void system_set_gpios_and_wakeup_inputs_hibernate(void)
-{
-	int table, i;
-
-	/* Disable all MIWU inputs before entering hibernate */
-	for (table = MIWU_TABLE_0 ; table < MIWU_TABLE_2 ; table++) {
-		for (i = 0 ; i < 8 ; i++) {
-			/* Disable all wake-ups */
-			NPCX_WKEN(table, i)  = 0x00;
-			/* Clear all pending bits of wake-ups */
-			NPCX_WKPCL(table, i) = 0xFF;
-			/*
-			 * Disable all inputs of wake-ups to prevent leakage
-			 * caused by input floating.
-			 */
-			NPCX_WKINEN(table, i) = 0x00;
-		}
-	}
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	/* Disable MIWU 2 group 6 inputs which used for the additional GPIOs */
-	NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6)  = 0x00;
-	NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) = 0xFF;
-	NPCX_WKINEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00;
-#endif
-
-	/* Enable wake-up inputs of hibernate_wake_pins array */
-	for (i = 0; i < hibernate_wake_pins_used; i++) {
-		gpio_reset(hibernate_wake_pins[i]);
-		/* Re-enable interrupt for wake-up inputs */
-		gpio_enable_interrupt(hibernate_wake_pins[i]);
-#if defined(CONFIG_HIBERNATE_PSL)
-		/* Config PSL pins setting for wake-up inputs */
-		if (!system_config_psl_mode(hibernate_wake_pins[i]))
-			ccprintf("Invalid PSL setting in wake-up pin %d\n", i);
-#endif
-	}
-}
-
-#ifdef NPCX_LCT_SUPPORT
-static void system_set_lct_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	/* The min resolution of LCT is 1 seconds */
-	if ((seconds == 0) && (microseconds != 0))
-		seconds = 1;
-
-	npcx_lct_enable(0);
-	npcx_lct_sel_power_src(NPCX_LCT_PWR_SRC_VSBY);
-#ifdef CONFIG_HIBERNATE_PSL
-	/* Enable LCT event to PSL */
-	npcx_lct_config(seconds, 1, 0);
-	/* save the start time of LCT */
-	if (IS_ENABLED(CONFIG_HOSTCMD_RTC) || IS_ENABLED(CONFIG_CMD_RTC))
-		bbram_data_write(BBRM_DATA_INDEX_LCT_TIME, seconds);
-#else
-	/* Enable LCT event interrupt and MIWU */
-	npcx_lct_config(seconds, 0, 1);
-	task_disable_irq(NPCX_IRQ_LCT_WKINTF_2);
-	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP)  |= LCT_WUI_MASK;
-	NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP)   |= LCT_WUI_MASK;
-	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
-#endif
-	npcx_lct_enable(1);
-}
-#endif
-
-/**
- * hibernate function for npcx ec.
- *
- * @param seconds      Number of seconds to sleep before LCT alarm
- * @param microseconds Number of microseconds to sleep before LCT alarm
- */
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-
-	/* Disable ADC */
-	NPCX_ADCCNF = 0;
-	usleep(1000);
-
-#ifdef NPCX_LCT_SUPPORT
-	/*
-	 * This function must be called before the ITIM (system tick)
-	 * is disabled because it calls udelay inside this function
-	 */
-	npcx_lct_enable_clk(1);
-#endif
-
-	/* Set SPI pins to be in Tri-State */
-	SET_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-
-	/* Disable instant wake up mode for better power consumption */
-	CLEAR_BIT(NPCX_ENIDL_CTL, NPCX_ENIDL_CTL_LP_WK_CTL);
-
-	/* Disable interrupt */
-	interrupt_disable();
-
-	/* Unlock & stop watchdog */
-	watchdog_stop_and_unlock();
-
-	/* ITIM event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-	/* ITIM time module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_ITEN);
-	/* ITIM watchdog warn module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-
-	/* Initialize watchdog */
-	NPCX_TWCFG = 0; /* Select T0IN clock as watchdog prescaler clock */
-	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDCT0I);
-	NPCX_TWCP = 0x00; /* Keep prescaler ratio timer0 clock to 1:1 */
-	NPCX_TWDT0 = 0x00; /* Set internal counter and prescaler */
-
-	/* Disable interrupt */
-	interrupt_disable();
-
-	/*
-	 * Set gpios and wake-up input for better power consumption before
-	 * entering hibernate.
-	 */
-	system_set_gpios_and_wakeup_inputs_hibernate();
-
-	/*
-	 * Give the board a chance to do any late stage hibernation work.  This
-	 * is likely going to configure GPIOs for hibernation.  On some boards,
-	 * it's possible that this may not return at all.  On those boards,
-	 * power to the EC is likely being turn off entirely.
-	 */
-	if (board_hibernate_late)
-		board_hibernate_late();
-
-	/* Clear all pending IRQ otherwise wfi will have no affect */
-	for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++)
-		task_clear_pending_irq(i);
-
-	/* Set the timer interrupt for wake up.  */
-#ifdef NPCX_LCT_SUPPORT
-	if (seconds || microseconds) {
-		system_set_lct_alarm(seconds, microseconds);
-	} else if (IS_ENABLED(CONFIG_HIBERNATE_PSL_COMPENSATE_RTC)) {
-		system_set_lct_alarm(NPCX_LCT_MAX, 0);
-	}
-#else
-	if (seconds || microseconds)
-		system_set_rtc_alarm(seconds, microseconds);
-#endif
-
-	/* execute hibernate func depend on chip series */
-	__hibernate_npcx_series();
-}
-
-#ifdef CONFIG_HIBERNATE_PSL_COMPENSATE_RTC
-#ifndef NPCX_LCT_SUPPORT
-#error "Do not enable CONFIG_HIBERNATE_PSL_COMPENSATE_RTC if npcx ec doesn't \
-support LCT!"
-#endif
-/*
- * The function uses the LCT counter value to compensate for RTC after hibernate
- * wake-up. Because system_set_rtc() will invoke udelay(), the function should
- * execute after timer_init(). The function also should execute before
- * npcx_lct_init() which will clear all LCT register.
- */
-void system_compensate_rtc(void)
-{
-	uint32_t rtc_time, ltc_start_time;
-
-	ltc_start_time = bbram_data_read(BBRM_DATA_INDEX_LCT_TIME);
-	if (ltc_start_time == 0)
-		return;
-
-	rtc_time = system_get_rtc_sec();
-	rtc_time += ltc_start_time - npcx_lct_get_time();
-	system_set_rtc(rtc_time);
-	/* Clear BBRAM data to avoid compensating again. */
-	bbram_data_write(BBRM_DATA_INDEX_LCT_TIME, 0);
-}
-#endif
-#endif /* CONFIG_SUPPORT_CHIP_HIBERNATION */
-
-static char system_to_hex(uint8_t val)
-{
-	uint8_t x = val & 0x0F;
-
-	if (x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/*
- * Microseconds will be ignored.  The WTC register only
- * stores wakeup time in seconds.
- * Set seconds = 0 to disable the alarm
- */
-void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	uint32_t cur_secs, alarm_secs;
-
-	if (seconds == EC_RTC_ALARM_CLEAR && !microseconds) {
-		CLEAR_BIT(NPCX_WTC, NPCX_WTC_WIE);
-		SET_BIT(NPCX_WTC, NPCX_WTC_PTO);
-
-		return;
-	}
-
-	/* Get current clock */
-	cur_secs = NPCX_TTC;
-
-	/* If alarm clock is not sequential or not in range */
-	alarm_secs = cur_secs + seconds;
-	alarm_secs = alarm_secs & MTC_ALARM_MASK;
-
-	/*
-	 * We should set new alarm (first 25 bits of clock value) first before
-	 * clearing PTO in case issue rtc interrupt immediately.
-	 */
-	NPCX_WTC = alarm_secs;
-
-	/* Reset alarm first */
-	system_reset_rtc_alarm();
-
-	/* Enable interrupt mode alarm */
-	SET_BIT(NPCX_WTC, NPCX_WTC_WIE);
-
-	/* Enable MTC interrupt */
-	task_enable_irq(NPCX_IRQ_MTC);
-
-	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP)  |= MTC_WUI_MASK;
-	NPCX_WKINEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP)   |= MTC_WUI_MASK;
-}
-
-void system_reset_rtc_alarm(void)
-{
-	/*
-	 * Clear interrupt & Disable alarm interrupt
-	 * Update alarm value to zero
-	 */
-	CLEAR_BIT(NPCX_WTC, NPCX_WTC_WIE);
-	SET_BIT(NPCX_WTC, NPCX_WTC_PTO);
-
-	/* Disable MTC interrupt */
-	task_disable_irq(NPCX_IRQ_MTC);
-}
-
-/*
- * Return the seconds remaining before the RTC alarm goes off.
- * Returns 0 if alarm is not set.
- */
-uint32_t system_get_rtc_alarm(void)
-{
-	/*
-	 * Return 0:
-	 * 1. If alarm is not set to go off, OR
-	 * 2. If alarm is set and has already gone off
-	 */
-	if (!IS_BIT_SET(NPCX_WTC, NPCX_WTC_WIE) ||
-	    IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO)) {
-		return 0;
-	}
-	/* Get seconds before alarm goes off */
-	return (NPCX_WTC - NPCX_TTC) & MTC_ALARM_MASK;
-}
-
-/**
- * Enable hibernate interrupt
- */
-void system_enable_hib_interrupt(void)
-{
-	task_enable_irq(NPCX_IRQ_MTC);
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-#ifdef CONFIG_SUPPORT_CHIP_HIBERNATION
-	/* Add additional hibernate operations here */
-	__enter_hibernate(seconds, microseconds);
-#endif
-}
-
-#ifndef CONFIG_ENABLE_JTAG_SELECTION
-static void system_disable_host_sel_jtag(void)
-{
-	int data;
-
-	/* Enable Core-to-Host Modules Access */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
-	/* Clear SIOCFD.JEN0_HSL to disable JTAG0 */
-	data = sib_read_reg(SIO_OFFSET, SIOCFD_REG_OFFSET);
-	data &= ~0x80;
-	sib_write_reg(SIO_OFFSET, SIOCFD_REG_OFFSET, data);
-	/* Disable Core-to-Host Modules Access */
-	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
-}
-#endif
-
-void chip_pre_init(void)
-{
-	/* Setting for fixing JTAG issue */
-	NPCX_DBGCTRL = 0x04;
-	/* Enable automatic freeze mode */
-	CLEAR_BIT(NPCX_DBGFRZEN3, NPCX_DBGFRZEN3_GLBL_FRZ_DIS);
-
-	/*
-	 * Enable JTAG functionality by SW without pulling down strap-pin
-	 * nJEN0 or nJEN1 during ec POWERON or VCCRST reset occurs.
-	 * Please notice it will change pinmux to JTAG directly.
-	 */
-#ifdef NPCX_ENABLE_JTAG
-#if NPCX_JTAG_MODULE2
-	CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_5), NPCX_DEVALT5_NJEN1_EN);
-#else
-	CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_5), NPCX_DEVALT5_NJEN0_EN);
-#endif
-#endif
-
-#ifndef CONFIG_ENABLE_JTAG_SELECTION
-	/*
-	 * (b/129908668)
-	 * This is the workaround to disable the JTAG0 which is enabled
-	 * accidentally by a special key combination.
-	 */
-#if NPCX_FAMILY_VERSION < NPCX_FAMILY_NPCX9
-	if (!IS_BIT_SET(NPCX_DEVALT(5), NPCX_DEVALT5_NJEN0_EN)) {
-		/* Set DEVALT5.nJEN0_EN to disable JTAG0 */
-		SET_BIT(NPCX_DEVALT(5), NPCX_DEVALT5_NJEN0_EN);
-		system_disable_host_sel_jtag();
-	}
-#else
-	if (GET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD) ==
-		      NPCX_JEN_CTL1_JEN_EN_ENA) {
-		SET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD,
-			  NPCX_JEN_CTL1_JEN_EN_DIS);
-		system_disable_host_sel_jtag();
-	}
-#endif
-#endif
-}
-
-void system_pre_init(void)
-{
-	uint8_t pwdwn6;
-
-	/*
-	 * Add additional initialization here
-	 * EC should be initialized in Booter
-	 */
-
-	/* Power-down the modules we don't need */
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_1) = 0xF9; /* Skip SDP_PD FIU_PD */
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_2) = 0xFF;
-#if defined(CHIP_FAMILY_NPCX5)
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x0F; /* Skip GDMA */
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x3F; /* Skip GDMA */
-#endif
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_4) = 0xF4; /* Skip ITIM2/1_PD */
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5) = 0xF8;
-
-	pwdwn6 = 0x70 |
-#if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7
-		/*
-		 * Don't set PD of ITIM6 for NPCX9 and later chips because
-		 * they use it as the system timer.
-		 */
-		BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
-#endif
-		BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */
-#if !defined(CONFIG_HOSTCMD_ESPI)
-	pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD;
-#endif
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6;
-
-#if defined(CHIP_FAMILY_NPCX7)
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
-	defined(CHIP_VARIANT_NPCX7M7WC)
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xE7;
-#else
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07;
-#endif
-#endif
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xFF;
-#endif
-
-	/* Following modules can be powered down automatically in npcx7 */
-#if defined(CHIP_FAMILY_NPCX5)
-	/* Power down the modules of npcx5 used internally */
-	NPCX_INTERNAL_CTRL1 = 0x03;
-	NPCX_INTERNAL_CTRL2 = 0x03;
-	NPCX_INTERNAL_CTRL3 = 0x03;
-
-	/* Enable low-power regulator */
-	CLEAR_BIT(NPCX_LFCGCALCNT, NPCX_LFCGCALCNT_LPREG_CTL_EN);
-	SET_BIT(NPCX_LFCGCALCNT, NPCX_LFCGCALCNT_LPREG_CTL_EN);
-#endif
-
-	/*
-	 * Configure LPRAM in the MPU as a regular memory
-	 * and DATA RAM to prevent code execution
-	 */
-	system_mpu_config();
-
-	/*
-	 * Change FMUL_WIN_DLY from 0x8A to 0x81 for better WoV
-	 * audio quality.
-	 */
-#ifdef CHIP_FAMILY_NPCX7
-	NPCX_FMUL_WIN_DLY = 0x81;
-#endif
-
-#ifdef CONFIG_CHIP_PANIC_BACKUP
-	chip_panic_data_restore();
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	if (IS_ENABLED(CONFIG_HIBERNATE_PSL)) {
-		uint8_t opt_flag = CONFIG_HIBERNATE_PSL_OUT_FLAGS;
-
-		/* PSL Glitch Protection */
-		SET_BIT(NPCX_GLUE_PSL_MCTL2, NPCX_GLUE_PSL_MCTL2_PSL_GP_EN);
-
-		/*
-		 * TODO: Remove this when NPCX9 A2 chip is available because A2
-		 * chip will enable VCC1_RST to PSL wakeup source and lock it in
-		 * the booter.
-		 */
-		if (IS_ENABLED(CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP)) {
-			/*
-			 * Enable VCC1_RST as the wake-up source from
-			 * hibernation.
-			 */
-			SET_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL);
-			/* Disable VCC_RST Pull-Up */
-			SET_BIT(NPCX_DEVALT(ALT_GROUP_G),
-					NPCX_DEVALTG_VCC1_RST_PUD);
-			/*
-			 * Lock this bit itself and VCC1_RST_PSL in the
-			 * PSL_MCTL1 register to read-only.
-			 */
-			SET_BIT(NPCX_GLUE_PSL_MCTL2,
-					NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK);
-		}
-
-		/* Don't set PSL_OUT to open-drain if it is the level mode */
-		ASSERT((opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE) ||
-			 !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD));
-
-		if (opt_flag & NPCX_PSL_CFG_PSL_OUT_OD)
-			SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_OD_EN);
-		else
-			CLEAR_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_OD_EN);
-
-		if (opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE)
-			SET_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_PLS_EN);
-		else
-			CLEAR_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_PLS_EN);
-	}
-#endif
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/*  Get flags to be saved in BBRAM */
-	system_encode_save_flags(flags, &save_flags);
-
-	/* Store flags to battery backed RAM. */
-	chip_save_reset_flags(save_flags);
-
-	/* If WAIT_EXT is set, then allow 10 seconds for external reset */
-	if (flags & SYSTEM_RESET_WAIT_EXT) {
-		int i;
-
-		/* Wait 10 seconds for external reset */
-		for (i = 0; i < 1000; i++) {
-			watchdog_reload();
-			udelay(10000);
-		}
-	}
-
-	/* Ask the watchdog to trigger a hard reboot */
-	system_watchdog_reset();
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-/**
- * Return the chip vendor/name/revision string.
- */
-const char *system_get_chip_vendor(void)
-{
-	static char str[15] = "Unknown-";
-	char *p = str + 8;
-
-	/* Read Vendor ID in core register */
-	uint8_t fam_id = NPCX_SID_CR;
-	switch (fam_id) {
-	case 0x20:
-		return "Nuvoton";
-	default:
-		*p       = system_to_hex(fam_id >> 4);
-		*(p + 1) = system_to_hex(fam_id);
-		*(p + 2) = '\0';
-		return str;
-	}
-}
-
-const char *system_get_chip_name(void)
-{
-	static char str[15] = "Unknown-";
-	char *p = str + 8;
-
-	/* Read Chip ID in core register */
-	uint8_t chip_id = NPCX_DEVICE_ID_CR;
-
-	switch (chip_id) {
-#if defined(CHIP_FAMILY_NPCX5)
-	case NPCX585G_CHIP_ID:
-		return "NPCX585G";
-	case NPCX575G_CHIP_ID:
-		return "NPCX575G";
-	case NPCX586G_CHIP_ID:
-		return "NPCX586G";
-	case NPCX576G_CHIP_ID:
-		return "NPCX576G";
-#elif defined(CHIP_FAMILY_NPCX7)
-	case NPCX787G_CHIP_ID:
-		return "NPCX787G";
-	case NPCX797F_C_CHIP_ID:
-		return "NPCX797F";
-	case NPCX796F_A_B_CHIP_ID:
-	case NPCX796F_C_CHIP_ID:
-		return "NPCX796F";
-	case NPCX797W_B_CHIP_ID:
-	case NPCX797W_C_CHIP_ID:
-		return "NPCX797W";
-#elif defined(CHIP_FAMILY_NPCX9)
-	case NPCX996F_CHIP_ID:
-		return "NPCX996F";
-	case NPCX993F_CHIP_ID:
-		return "NPCX993F";
-#endif
-	default:
-		*p       = system_to_hex(chip_id >> 4);
-		*(p + 1) = system_to_hex(chip_id);
-		*(p + 2) = '\0';
-		return str;
-	}
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char rev[CHIP_REV_STR_SIZE];
-	char *p = rev;
-	/* Read chip generation from SRID_CR */
-	uint8_t chip_gen = NPCX_SRID_CR;
-	/* Read ROM data for chip revision directly */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	uint32_t rev_num = *((uint32_t *)CHIP_REV_ADDR);
-#else
-	uint8_t rev_num = *((uint8_t *)CHIP_REV_ADDR);
-#endif
-
-#ifdef CHIP_FAMILY_NPCX7
-	uint8_t chip_id = NPCX_DEVICE_ID_CR;
-#endif
-	int s;
-
-	switch (chip_gen) {
-#if defined(CHIP_FAMILY_NPCX5)
-	case 0x05:
-		*p++ = 'A';
-		break;
-#elif defined(CHIP_FAMILY_NPCX7)
-	case 0x06:
-		*p++ = 'A';
-		break;
-	case 0x07:
-		if (chip_id == NPCX796F_A_B_CHIP_ID ||
-			chip_id == NPCX797W_B_CHIP_ID)
-			*p++ = 'B';
-		else
-			*p++ = 'C';
-		break;
-#elif defined(CHIP_FAMILY_NPCX9)
-	case 0x09:
-		*p++ = 'A';
-		break;
-#endif
-	default:
-		*p++ = system_to_hex(chip_gen >> 4);
-		*p++ = system_to_hex(chip_gen);
-		break;
-	}
-
-	*p++ = '.';
-	/*
-	 * For npcx5/npcx7, the revision number is 1 byte.
-	 * For NPCX9 and later chips, the revision number is 4 bytes.
-	 */
-	for (s = sizeof(rev_num) - 1; s >= 0; s--) {
-		uint8_t r = rev_num >> (s * 8);
-
-		*p++ = system_to_hex(r >> 4);
-		*p++ = system_to_hex(r);
-	}
-	*p++ = '\0';
-
-	return rev;
-}
-
-/**
- * Set a scratchpad register to the specified value.
- *
- * The scratchpad register must maintain its contents across a
- * software-requested warm reset.
- *
- * @param value		Value to store.
- * @return EC_SUCCESS, or non-zero if error.
- */
-int system_set_scratchpad(uint32_t value)
-{
-	return bbram_data_write(BBRM_DATA_INDEX_SCRATCHPAD, value);
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = bbram_data_read(BBRM_DATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-int system_is_reboot_warm(void)
-{
-	uint32_t reset_flags;
-
-	/*
-	 * Check reset cause here,
-	 * gpio_pre_init is executed faster than system_pre_init
-	 */
-	check_reset_cause();
-	reset_flags = system_get_reset_flags();
-
-	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-	    (reset_flags & EC_RESET_FLAG_POWER_ON) ||
-	    (reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-	    (reset_flags & EC_RESET_FLAG_HARD) ||
-	    (reset_flags & EC_RESET_FLAG_SOFT) ||
-	    (reset_flags & EC_RESET_FLAG_HIBERNATE))
-		return 0;
-	else
-		return 1;
-}
-
-#if defined(CONFIG_HIBERNATE_PSL) && defined(NPCX_LCT_SUPPORT)
-static void system_init_check_rtc_wakeup_event(void)
-{
-	/*
-	 * If platform uses PSL (Power Switch Logic) for hibernating and RTC is
-	 * also supported, determine whether ec is woken up by RTC with overflow
-	 * event (16 weeks). If so, let it go to hibernate mode immediately.
-	 */
-	if (is_rtc_overflow_event){
-		CPRINTS("Hibernate due to RTC overflow event");
-		system_hibernate(0, 0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, system_init_check_rtc_wakeup_event,
-	     HOOK_PRIO_DEFAULT - 1);
-#endif
-
-/*****************************************************************************/
-/* Console commands */
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t sec = system_get_rtc_sec();
-
-	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
-}
-
-#ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
-{
-	if (argc == 3 && !strcasecmp(argv[1], "set")) {
-		char *e;
-		uint32_t t = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		system_set_rtc(t);
-	} else if (argc > 1) {
-		return EC_ERROR_INVAL;
-	}
-
-	print_system_rtc(CC_COMMAND);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-		"[set <seconds>]",
-		"Get/set real-time clock");
-
-#ifdef CONFIG_CMD_RTC_ALARM
-/**
- * Test the RTC alarm by setting an interrupt on RTC match.
- */
-static int command_rtc_alarm_test(int argc, char **argv)
-{
-	int s = 1, us = 0;
-	char *e;
-
-	ccprintf("Setting RTC alarm\n");
-	system_enable_hib_interrupt();
-
-	if (argc > 1) {
-		s = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-	}
-	if (argc > 2) {
-		us = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-	}
-
-	system_set_rtc_alarm(s, us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-		"[seconds [microseconds]]",
-		"Test alarm");
-#endif /* CONFIG_CMD_RTC_ALARM */
-#endif /* CONFIG_CMD_RTC */
-
-/*****************************************************************************/
-/* Host commands */
-
-#ifdef CONFIG_HOSTCMD_RTC
-static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = system_get_rtc_sec();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		system_rtc_get_value,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	system_set_rtc(p->time);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		system_rtc_set_value,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	system_set_rtc_alarm(p->time, 0);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM,
-		system_rtc_set_alarm,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = system_get_rtc_alarm();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM,
-		system_rtc_get_alarm,
-		EC_VER_MASK(0));
-
-#endif /* CONFIG_HOSTCMD_RTC */
-#ifdef CONFIG_EXTERNAL_STORAGE
-void system_jump_to_booter(void)
-{
-	enum API_RETURN_STATUS_T status __attribute__((unused));
-	static uint32_t flash_offset;
-	static uint32_t flash_used;
-	static uint32_t addr_entry;
-
-	/*
-	 * Get memory offset and size for RO/RW regions.
-	 * Both of them need 16-bytes alignment since GDMA burst mode.
-	 */
-	switch (system_get_shrspi_image_copy()) {
-	case EC_IMAGE_RW:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_STORAGE_OFF;
-		flash_used = CONFIG_RW_SIZE;
-		break;
-#ifdef CONFIG_RW_B
-	case EC_IMAGE_RW_B:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_STORAGE_OFF;
-		flash_used = CONFIG_RW_SIZE;
-		break;
-#endif
-	case EC_IMAGE_RO:
-	default: /* Jump to RO by default */
-		flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
-				CONFIG_RO_STORAGE_OFF;
-		flash_used = CONFIG_RO_SIZE;
-		break;
-	}
-
-	/* Make sure the reset vector is inside the destination image */
-	addr_entry = *(uintptr_t *)(flash_offset +
-				    CONFIG_MAPPED_STORAGE_BASE + 4);
-
-	/*
-	 * Speed up FW download time by increasing clock freq of EC. It will
-	 * restore to default in clock_init() later.
-	 */
-	clock_turbo();
-
-/*
- * npcx9 Rev.1 has the problem for download_from_flash API.
- * Workwaroud it by executing the system_download_from_flash function
- * in the suspend RAM like npcx5.
- * TODO: Removing npcx9 when Rev.2 is available.
- */
-	/* Bypass for GMDA issue of ROM api utilities */
-#if defined(CHIP_FAMILY_NPCX5) || defined(CONFIG_WORKAROUND_FLASH_DOWNLOAD_API)
-	system_download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		addr_entry         /* jump to this address after download */
-	);
-#else
-	download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		SIGN_NO_CHECK,     /* Need CRC check or not               */
-		addr_entry,        /* jump to this address after download */
-		&status            /* Status fo download */
-	);
-#endif
-}
-
-uint32_t system_get_lfw_address()
-{
-	/*
-	 * In A3 version, we don't use little FW anymore
-	 * We provide the alternative function in ROM
-	 */
-	uint32_t jump_addr = (uint32_t)system_jump_to_booter;
-	return jump_addr;
-}
-
-/*
- * Set and clear image copy flags in MDC register.
- *
- * NPCX_FWCTRL_RO_REGION: 1 - RO, 0 - RW
- * NPCX_FWCTRL_FW_SLOT: 1 - SLOT_A, 0 - SLOT_B
- */
-void system_set_image_copy(enum ec_image copy)
-{
-	switch (copy) {
-	case EC_IMAGE_RW:
-		CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
-		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT);
-		break;
-#ifdef CONFIG_RW_B
-	case EC_IMAGE_RW_B:
-		CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
-		CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT);
-		break;
-#endif
-	default:
-		CPRINTS("Invalid copy (%d) is requested as a jump destination. "
-			"Change it to %d.", copy, EC_IMAGE_RO);
-		/* Fall through to EC_IMAGE_RO */
-	case EC_IMAGE_RO:
-		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
-		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT);
-		break;
-	}
-}
-
-enum ec_image system_get_shrspi_image_copy(void)
-{
-	if (IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION)) {
-		/* RO image */
-#ifdef CHIP_HAS_RO_B
-		if (!IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT))
-			return EC_IMAGE_RO_B;
-#endif
-		return EC_IMAGE_RO;
-	} else {
-#ifdef CONFIG_RW_B
-		/* RW image */
-		if (!IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT))
-			/* Slot A */
-			return EC_IMAGE_RW_B;
-#endif
-		return EC_IMAGE_RW;
-	}
-}
-
-#endif
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h
deleted file mode 100644
index e3cc2a8865..0000000000
--- a/chip/npcx/system_chip.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific SIB module for Chrome EC */
-
-#ifndef __CROS_EC_SYSTEM_CHIP_H
-#define __CROS_EC_SYSTEM_CHIP_H
-
-/* Flags for BBRM_DATA_INDEX_WAKE */
-#define HIBERNATE_WAKE_MTC        BIT(0)  /* MTC alarm */
-#define HIBERNATE_WAKE_PIN        BIT(1)  /* Wake pin */
-#define HIBERNATE_WAKE_LCT        BIT(2)  /* LCT alarm */
-/*
- * Indicate that EC enters hibernation via PSL. When EC wakes up from
- * hibernation and this flag is set, it will check the related status bit to
- * know the actual wake up source. (From LCT or physical wakeup pins)
- */
-#define HIBERNATE_WAKE_PSL        BIT(3)
-
-/* Indices for battery-backed ram (BBRAM) data position */
-enum bbram_data_index {
-	BBRM_DATA_INDEX_SCRATCHPAD = 0,        /* General-purpose scratchpad */
-	BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */
-	BBRM_DATA_INDEX_WAKE = 8,	       /* Wake reasons for hibernate */
-	BBRM_DATA_INDEX_PD0 = 12,	       /* USB-PD saved port0 state */
-	BBRM_DATA_INDEX_PD1 = 13,	       /* USB-PD saved port1 state */
-	BBRM_DATA_INDEX_TRY_SLOT = 14,         /* Vboot EC try slot */
-	BBRM_DATA_INDEX_PD2 = 15,	       /* USB-PD saved port2 state */
-	/* Index 16-31 available for future use */
-	BBRM_DATA_INDEX_RAMLOG = 32,	       /* RAM log for Booter */
-	BBRM_DATA_INDEX_PANIC_FLAGS = 35,      /* Flag to indicate validity of
-						* panic data starting at index
-						* 36.
-						*/
-	BBRM_DATA_INDEX_PANIC_BKUP = 36,       /* Panic data (index 35-63)*/
-	BBRM_DATA_INDEX_LCT_TIME = 64,         /* The start time of LCT(4 bytes)
-						*/
-};
-
-enum psl_pin_t {
-	PSL_IN1,
-	PSL_IN2,
-	PSL_IN3,
-	PSL_IN4,
-	PSL_NONE,
-};
-
-/* Issue a watchdog reset */
-void system_watchdog_reset(void);
-
-/* Stops the watchdog timer and unlocks configuration. */
-void watchdog_stop_and_unlock(void);
-
-/*
- * Configure the specific memory addresses in the the MPU
- * (Memory Protection Unit) for Nuvoton different chip series.
- */
-void system_mpu_config(void);
-
-/* Hibernate function for different Nuvoton chip series. */
-void __hibernate_npcx_series(void);
-
-/* Check and clear BBRAM status on power-on reset */
-void system_check_bbram_on_reset(void);
-
-/* The utilities and variables depend on npcx chip family */
-#if defined(CHIP_FAMILY_NPCX5) || defined(CONFIG_WORKAROUND_FLASH_DOWNLOAD_API)
-/* Bypass for GMDA issue of ROM api utilities only on npcx5 series */
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr);
-
-/* Begin address for hibernate utility; defined in linker script */
-extern unsigned int __flash_lpfw_start;
-
-/* End address for hibernate utility; defined in linker script */
-extern unsigned int __flash_lpfw_end;
-
-/* Begin address for little FW; defined in linker script */
-extern unsigned int __flash_lplfw_start;
-
-/* End address for little FW; defined in linker script */
-extern unsigned int __flash_lplfw_end;
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-/* Configure PSL mode setting for the wake-up pins. */
-int system_config_psl_mode(enum gpio_signal signal);
-
-/* Configure PSL pins and enter PSL mode. */
-void system_enter_psl_mode(void);
-
-/* End address for hibernate utility; defined in linker script */
-extern unsigned int __after_init_end;
-
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-void system_set_psl_gpo(int level);
-#endif
-
-#endif /* __CROS_EC_SYSTEM_CHIP_H */
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c
deleted file mode 100644
index efe991ec0b..0000000000
--- a/chip/npcx/uart.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "lpc.h"
-#include "registers.h"
-#include "clock_chip.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "uartn.h"
-#include "util.h"
-
-#define CONSOLE_UART            CONFIG_CONSOLE_UART
-
-#if CONSOLE_UART
-#define CONSOLE_UART_IRQ        NPCX_IRQ_UART2
-#else
-#define CONSOLE_UART_IRQ        NPCX_IRQ_UART
-#endif
-
-static int init_done;
-
-#ifdef CONFIG_UART_PAD_SWITCH
-
-/* Current pad: 0 for default pad, 1 for alternate. */
-static volatile enum uart_pad pad;
-
-/*
- * When switched to alternate pad, read/write data according to the parameters
- * below.
- */
-static uint8_t *altpad_rx_buf;
-static volatile int altpad_rx_pos;
-static int altpad_rx_len;
-static uint8_t *altpad_tx_buf;
-static volatile int altpad_tx_pos;
-static int altpad_tx_len;
-
-/*
- * Time we last received a byte on default UART, we do not allow use of
- * alternate pad for block_alt_timeout_us after that, to make sure input
- * characters are not lost (either interactively, or though servod/FAFT).
- */
-static timestamp_t last_default_pad_rx_time;
-
-static const uint32_t block_alt_timeout_us = 500*MSEC;
-
-#else
-
-/* Default pad is always selected. */
-static const enum uart_pad pad = UART_DEFAULT_PAD;
-
-#endif /* CONFIG_UART_PAD_SWITCH */
-
-#if defined(CHIP_FAMILY_NPCX5)
-/* This routine switches the functionality from UART rx to GPIO */
-void npcx_uart2gpio(void)
-{
-	/* Switch both pads back to GPIO mode. */
-	CLEAR_BIT(NPCX_DEVALT(0x0C), NPCX_DEVALTC_UART_SL2);
-	CLEAR_BIT(NPCX_DEVALT(0x0A), NPCX_DEVALTA_UART_SL1);
-}
-#endif /* CHIP_FAMILY_NPCX5 */
-
-/*
- * This routine switches the functionality from GPIO to UART rx, depending
- * on the global variable "pad". It also deactivates the previous pad.
- *
- * Note that, when switching pad, we first configure the new pad, then switch
- * off the old one, to avoid having no pad selected at a given time, see
- * b/65526215#c26.
- */
-void npcx_gpio2uart(void)
-{
-#ifdef CONFIG_UART_PAD_SWITCH
-	if (pad == UART_ALTERNATE_PAD) {
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-		SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SIN__SL);
-		SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SOUT_SL);
-		CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SIN_SL);
-		CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SOUT_SL);
-#else
-		SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SL);
-		CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL);
-#endif
-		return;
-	}
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SIN_SL);
-	SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SOUT_SL);
-	CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SIN_SL);
-	CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SOUT_SL);
-#else
-	SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL);
-	CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SL);
-#endif
-
-#if !NPCX_UART_MODULE2 && (NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7)
-	/*
-	 * UART module 1 belongs to KSO since wake-up functionality in npcx7
-	 * and later chips.
-	 */
-	CLEAR_BIT(NPCX_DEVALT(0x09), NPCX_DEVALT9_NO_KSO09_SL);
-#endif
-}
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-#if defined(CHIP_FAMILY_NPCX5)
-	if (uart_is_enable_wakeup() && pad == UART_DEFAULT_PAD) {
-		/* disable MIWU */
-		uart_enable_wakeup(0);
-		/* Set pin-mask for UART */
-		npcx_gpio2uart();
-		/* enable uart again from MIWU mode */
-		task_enable_irq(NPCX_IRQ_UART);
-	}
-#endif
-
-	uartn_tx_start(CONSOLE_UART);
-}
-
-void uart_tx_stop(void)
-{
-#ifdef NPCX_UART_FIFO_SUPPORT
-	uartn_tx_stop(CONSOLE_UART, 0);
-#else
-	uint8_t sleep_ena;
-
-	sleep_ena = (pad == UART_DEFAULT_PAD) ? 1 : 0;
-	uartn_tx_stop(CONSOLE_UART, sleep_ena);
-#endif
-}
-
-void uart_tx_flush(void)
-{
-	uartn_tx_flush(CONSOLE_UART);
-}
-
-int uart_tx_ready(void)
-{
-	return uartn_tx_ready(CONSOLE_UART);
-}
-
-int uart_tx_in_progress(void)
-{
-	return uartn_tx_in_progress(CONSOLE_UART);
-}
-
-int uart_rx_available(void)
-{
-	int rx_available = uartn_rx_available(CONSOLE_UART);
-
-	if (rx_available && pad == UART_DEFAULT_PAD) {
-#ifdef CONFIG_LOW_POWER_IDLE
-		/*
-		 * Activity seen on UART RX pin while UART was disabled for deep
-		 * sleep. The console won't see that character because the UART
-		 * is disabled, so we need to inform the clock module of UART
-		 * activity ourselves.
-		 */
-		clock_refresh_console_in_use();
-#endif
-#ifdef CONFIG_UART_PAD_SWITCH
-		last_default_pad_rx_time = get_time();
-#endif
-	}
-	return rx_available; /* If RX FIFO is empty return '0'. */
-}
-
-void uart_write_char(char c)
-{
-	uartn_write_char(CONSOLE_UART, c);
-}
-
-int uart_read_char(void)
-{
-	return uartn_read_char(CONSOLE_UART);
-}
-
-/* Interrupt handler for Console UART */
-void uart_ec_interrupt(void)
-{
-#ifdef CONFIG_UART_PAD_SWITCH
-	if (pad == UART_ALTERNATE_PAD) {
-		if (uartn_rx_available(NPCX_UART_PORT0)) {
-			uint8_t c = uartn_read_char(NPCX_UART_PORT0);
-
-			if (altpad_rx_pos < altpad_rx_len)
-				altpad_rx_buf[altpad_rx_pos++] = c;
-		}
-		if (uartn_tx_ready(NPCX_UART_PORT0)) {
-			if (altpad_tx_pos < altpad_tx_len)
-				uartn_write_char(NPCX_UART_PORT0,
-					altpad_tx_buf[altpad_tx_pos++]);
-			else
-				uart_tx_stop();
-		}
-		return;
-	}
-#endif
-#ifdef NPCX_UART_FIFO_SUPPORT
-	if (!uartn_tx_in_progress(CONSOLE_UART)) {
-		if (uart_buffer_empty()) {
-			uartn_enable_tx_complete_int(CONSOLE_UART, 0);
-			enable_sleep(SLEEP_MASK_UART);
-		}
-	}
-#endif
-
-	/* Default pad. */
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-}
-#ifdef NPCX_UART_FIFO_SUPPORT
-DECLARE_IRQ(CONSOLE_UART_IRQ, uart_ec_interrupt, 4);
-#else
-DECLARE_IRQ(CONSOLE_UART_IRQ, uart_ec_interrupt, 1);
-#endif
-
-#ifdef CONFIG_UART_PAD_SWITCH
-/*
- * Switch back to default UART pad, without flushing RX/TX buffers: If we are
- * about to panic, we just want to switch immmediately, and we don't care if we
- * output a bit of garbage.
- */
-void uart_reset_default_pad_panic(void)
-{
-	pad = UART_DEFAULT_PAD;
-
-	/* Configure new pad. */
-	npcx_gpio2uart();
-
-	/* Wait for ~2 bytes, to help the receiver resync. */
-	udelay(200);
-}
-
-static void uart_set_pad(enum uart_pad newpad)
-{
-#ifdef NPCX_UART_FIFO_SUPPORT
-	NPCX_UFTCTL(NPCX_UART_PORT0) &= ~0xE0;
-	NPCX_UFRCTL(NPCX_UART_PORT0) &= ~0xE0;
-#else
-	NPCX_UICTRL(NPCX_UART_PORT0) = 0x00;
-#endif
-	task_disable_irq(NPCX_IRQ_UART);
-
-	/* Flush the last byte */
-	uartn_tx_flush(NPCX_UART_PORT0);
-	uart_tx_stop();
-
-	/*
-	 * Allow deep sleep when default pad is selected (sleep is inhibited
-	 * during TX). Disallow deep sleep when alternate pad is selected.
-	 */
-	if (newpad == UART_DEFAULT_PAD)
-		enable_sleep(SLEEP_MASK_UART);
-	else
-		disable_sleep(SLEEP_MASK_UART);
-
-	pad = newpad;
-
-	/* Configure new pad. */
-	npcx_gpio2uart();
-
-	/* Re-enable receive interrupt. */
-	uartn_rx_int_en(NPCX_UART_PORT0);
-
-	/*
-	 * If pad is switched while a byte is being received, the last byte may
-	 * be corrupted, let's wait for ~1 byte (9/115200 = 78 us + margin),
-	 * then flush the FIFO. See b/65526215.
-	 */
-	udelay(100);
-	uartn_clear_rx_fifo(NPCX_UART_PORT0);
-
-	task_enable_irq(NPCX_IRQ_UART);
-}
-
-/* TODO(b:67026316): Remove this and replace with software flow control. */
-void uart_default_pad_rx_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * We received an interrupt on the primary pad, give up on the
-	 * transaction and switch back.
-	 */
-	gpio_disable_interrupt(GPIO_UART_MAIN_RX);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	clock_refresh_console_in_use();
-#endif
-	last_default_pad_rx_time = get_time();
-
-	uart_set_pad(UART_DEFAULT_PAD);
-}
-
-int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len,
-			    int timeout_us)
-{
-	uint32_t start = __hw_clock_source_read();
-	int ret = 0;
-
-	if ((get_time().val - last_default_pad_rx_time.val)
-			< block_alt_timeout_us)
-		return -EC_ERROR_BUSY;
-
-	cflush();
-
-	altpad_rx_buf = rx;
-	altpad_rx_pos = 0;
-	altpad_rx_len = rx_len;
-	altpad_tx_buf = tx;
-	altpad_tx_pos = 0;
-	altpad_tx_len = tx_len;
-
-	/*
-	 * Turn on additional pull-up during transaction: that prevents the line
-	 * from going low in case the base gets disconnected during the
-	 * transaction. See b/68954760.
-	 */
-	gpio_set_flags(GPIO_EC_COMM_PU, GPIO_OUTPUT | GPIO_HIGH);
-
-	uart_set_pad(UART_ALTERNATE_PAD);
-	gpio_clear_pending_interrupt(GPIO_UART_MAIN_RX);
-	gpio_enable_interrupt(GPIO_UART_MAIN_RX);
-	uartn_tx_start(NPCX_UART_PORT0);
-
-	do {
-		usleep(100);
-
-		/* Pad switched during transaction. */
-		if (pad != UART_ALTERNATE_PAD) {
-			ret = -EC_ERROR_BUSY;
-			goto out;
-		}
-
-		if (altpad_rx_pos == altpad_rx_len &&
-		    altpad_tx_pos == altpad_tx_len)
-			break;
-	} while ((__hw_clock_source_read() - start) < timeout_us);
-
-	gpio_disable_interrupt(GPIO_UART_MAIN_RX);
-	uart_set_pad(UART_DEFAULT_PAD);
-
-	if (altpad_tx_pos == altpad_tx_len)
-		ret = altpad_rx_pos;
-	else
-		ret = -EC_ERROR_TIMEOUT;
-
-out:
-	gpio_set_flags(GPIO_EC_COMM_PU, GPIO_INPUT);
-
-	altpad_rx_len = 0;
-	altpad_rx_pos = 0;
-	altpad_rx_buf = NULL;
-	altpad_tx_len = 0;
-	altpad_tx_pos = 0;
-	altpad_tx_buf = NULL;
-
-	return ret;
-}
-#endif
-void uart_init(void)
-{
-
-	uartn_init(CONSOLE_UART);
-	init_done = 1;
-}
diff --git a/chip/npcx/uartn.c b/chip/npcx/uartn.c
deleted file mode 100644
index 2269e11e7c..0000000000
--- a/chip/npcx/uartn.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for Chrome EC */
-
-#include <clock.h>
-#include "common.h"
-#include <gpio.h>
-#include <gpio_chip.h>
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-/* Enable UART Tx FIFO empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_EN(n)      \
-		(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
-/* True if UART Tx FIFO empty interrupt is enabled */
-#define NPCX_UART_TX_EMPTY_INT_IS_EN(n)   \
-		(IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
-/* Disable UART Tx FIFO empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_DIS(n)     \
-		(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
-/* True if the Tx FIFO is not completely full */
-#define NPCX_UART_TX_IS_READY(n)          \
-		(!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0))
-
-/* Enable UART Tx "not" in transmission interrupt */
-#define NPCX_UART_TX_NXMIP_INT_EN(n)      \
-		(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
-/* Disable UART Tx "not" in transmission interrupt */
-#define NPCX_UART_TX_NXMIP_INT_DIS(n)      \
-		(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
-/*
- * True if Tx is in progress
- * (i.e. FIFO is not empty or last byte in TSFT (Transmit Shift register)
- * is not sent)
- */
-#define NPCX_UART_TX_IN_XMIT(n)           \
-		(!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP))
-
-/*
- * Enable to generate interrupt when there is at least one byte
- * in the receive FIFO
- */
-#define NPCX_UART_RX_INT_EN(n)            \
-		(SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN))
-/* True if at least one byte is in the receive FIFO */
-#define NPCX_UART_RX_IS_AVAILABLE(n)      \
-		(IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS))
-#else
-/* Enable UART Tx buffer empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_EN(n)      (NPCX_UICTRL(n) |= 0x20)
-/* True if UART Tx buffer empty interrupt is enabled */
-#define NPCX_UART_TX_EMPTY_INT_IS_EN(n)   (NPCX_UICTRL(n) & 0x20)
-/* Disable UART Tx buffer empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_DIS(n)     (NPCX_UICTRL(n) &= ~0x20)
-/* True if 1-byte Tx buffer is empty */
-#define NPCX_UART_TX_IS_READY(n)          (NPCX_UICTRL(n) & 0x01)
-/*
- * True if Tx is in progress
- * (i.e. Tx buffer is not empty or last byte in TSFT (Transmit Shift register)
- * is not sent)
- */
-#define NPCX_UART_TX_IN_XMIT(n)           (NPCX_USTAT(n) & 0x40)
- /* Enable to generate interrupt when there is data in the receive buffer */
-#define NPCX_UART_RX_INT_EN(n)            (NPCX_UICTRL(n) = 0x40)
-/* True if there is data in the 1-byte Receive buffer */
-#define NPCX_UART_RX_IS_AVAILABLE(n)      (NPCX_UICTRL(n) & 0x02)
-#endif
-
-struct uart_configs {
-	uint32_t irq;
-	uint32_t clk_en_offset;
-	uint32_t clk_en_msk;
-};
-static const struct uart_configs uart_cfg[] = {
-	{NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK},
-#ifdef NPCX_SECOND_UART
-	{NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(uart_cfg) == UART_MODULE_COUNT);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-static const struct npcx_wui uart_wui[] = {
-	WUI(1, NPCX_UART_WK_GROUP, NPCX_UART_WK_BIT),
-#ifdef NPCX_SECOND_UART
-	WUI(0, NPCX_UART2_WK_GROUP, NPCX_UART2_WK_BIT),
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(uart_wui) == UART_MODULE_COUNT);
-
-void uartn_wui_en(uint8_t uart_num)
-{
-	struct npcx_wui wui;
-
-	wui = uart_wui[uart_num];
-	/* Clear pending bit before enable uart wake-up */
-	SET_BIT(NPCX_WKPCL(wui.table, wui.group), wui.bit);
-	/* Enable UART1 wake-up and interrupt request */
-	SET_BIT(NPCX_WKEN(wui.table, wui.group), wui.bit);
-}
-#endif
-
-void uartn_rx_int_en(uint8_t uart_num)
-{
-	NPCX_UART_RX_INT_EN(uart_num);
-}
-
-void uartn_tx_start(uint8_t uart_num)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (NPCX_UART_TX_EMPTY_INT_IS_EN(uart_num))
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-	/*
-	 * For FIFO mode, enable the NXMIP interrupt. This generates an
-	 * interrupt when Tx (both FIFO and shift register) is empty
-	 */
-	NPCX_UART_TX_NXMIP_INT_EN(uart_num);
-#else
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	NPCX_UART_TX_EMPTY_INT_EN(uart_num);
-#endif
-
-	task_trigger_irq(uart_cfg[uart_num].irq);
-}
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable)
-{
-	enable ? NPCX_UART_TX_NXMIP_INT_EN(uart_num) :
-		NPCX_UART_TX_NXMIP_INT_DIS(uart_num);
-}
-#endif
-
-void uartn_tx_stop(uint8_t uart_num, uint8_t sleep_ena)
-{
-	/* Disable TX interrupt */
-	NPCX_UART_TX_EMPTY_INT_DIS(uart_num);
-	/*
-	 * Re-allow deep sleep when transmiting on the default pad (deep sleep
-	 * is always disabled when alternate pad is selected).
-	 */
-	if (sleep_ena == 1)
-		enable_sleep(SLEEP_MASK_UART);
-}
-
-void uartn_tx_flush(uint8_t uart_num)
-{
-	/* Wait for transmit FIFO empty and last byte is sent */
-	while (NPCX_UART_TX_IN_XMIT(uart_num))
-		;
-}
-
-int uartn_tx_ready(uint8_t uart_num)
-{
-	return NPCX_UART_TX_IS_READY(uart_num);
-}
-
-int uartn_tx_in_progress(uint8_t uart_num)
-{
-	return NPCX_UART_TX_IN_XMIT(uart_num);
-}
-
-int uartn_rx_available(uint8_t uart_num)
-{
-	return NPCX_UART_RX_IS_AVAILABLE(uart_num);
-}
-
-void uartn_write_char(uint8_t uart_num, char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uartn_tx_ready(uart_num))
-		;
-
-	NPCX_UTBUF(uart_num) = c;
-}
-
-int uartn_read_char(uint8_t uart_num)
-{
-	return NPCX_URBUF(uart_num);
-}
-
-void uartn_clear_rx_fifo(int channel)
-{
-	int scratch __attribute__ ((unused));
-
-	/* If '1',  that means there is RX data on the FIFO register */
-	while (NPCX_UART_RX_IS_AVAILABLE(channel))
-		scratch = NPCX_URBUF(channel);
-}
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-static void uartn_set_fifo_mode(uint8_t uart_num)
-{
-	/* Enable the UART FIFO mode */
-	SET_BIT(NPCX_UMDSL(uart_num), NPCX_UMDSL_FIFO_MD);
-	/* Disable all Tx interrupts */
-	NPCX_UFTCTL(uart_num) &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) |
-					BIT(NPCX_UFTCTL_TEMPTY_EN) |
-					BIT(NPCX_UFTCTL_NXMIPEN));
-}
-
-#endif
-
-static void uartn_config(uint8_t uart_num)
-{
-#ifdef CONFIG_LOW_POWER_IDLE
-	struct npcx_wui wui;
-#endif
-
-	/* Configure pins from GPIOs to CR_UART */
-	gpio_config_module(MODULE_UART, 1);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * Configure the UART wake-up event triggered from a falling edge
-	 * on CR_SIN pin.
-	 */
-	wui = uart_wui[uart_num];
-	SET_BIT(NPCX_WKEDG(wui.table, wui.group), wui.bit);
-#endif
-	/*
-	 * If apb2's clock is not 15MHz, we need to find the other optimized
-	 * values of UPSR and UBAUD for baud rate 115200.
-	 */
-#if (NPCX_APB_CLOCK(2) != 15000000)
-#error "Unsupported apb2 clock for UART!"
-#endif
-
-	/*
-	 * Fix baud rate to 115200. If this value is modified, please also
-	 * modify the delay in uart_set_pad and uart_reset_default_pad_panic.
-	 */
-	NPCX_UPSR(uart_num) = 0x38;
-	NPCX_UBAUD(uart_num) = 0x01;
-
-	/*
-	 * 8-N-1, FIFO enabled.  Must be done after setting
-	 * the divisor for the new divisor to take effect.
-	 */
-	NPCX_UFRS(uart_num) = 0x00;
-#ifdef NPCX_UART_FIFO_SUPPORT
-	uartn_set_fifo_mode(uart_num);
-#endif
-	NPCX_UART_RX_INT_EN(uart_num);
-}
-
-void uartn_init(uint8_t uart_num)
-{
-	uint32_t offset, mask;
-
-	offset = uart_cfg[uart_num].clk_en_offset;
-	mask = uart_cfg[uart_num].clk_en_msk;
-	clock_enable_peripheral(offset, mask, CGC_MODE_ALL);
-
-	if (uart_num == NPCX_UART_PORT0)
-		npcx_gpio2uart();
-
-	/* Configure UARTs (identically) */
-	uartn_config(uart_num);
-
-	/*
-	 * Enable interrupts for UART0 only. Host UART will have to wait
-	 * until the LPC bus is initialized.
-	 */
-	uartn_clear_rx_fifo(uart_num);
-	task_enable_irq(uart_cfg[uart_num].irq);
-}
diff --git a/chip/npcx/uartn.h b/chip/npcx/uartn.h
deleted file mode 100644
index e5326f72b8..0000000000
--- a/chip/npcx/uartn.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_UARTN_H
-#define __CROS_EC_UARTN_H
-
-#include "common.h"
-
-/*
- * Initialize the UART module.
- */
-void uartn_init(uint8_t uart_num);
-
-/*
- * Re-enable the UART transmit interrupt.
- *
- * This also forces triggering a UART interrupt, if the transmit interrupt was
- * disabled.
- */
-void uartn_tx_start(uint8_t uart_num);
-
- /* Disable the UART transmit interrupt. */
-void uartn_tx_stop(uint8_t uart_num, uint8_t sleep_ena);
-
-/* Flush the transmit FIFO. */
-void uartn_tx_flush(uint8_t uart_num);
-
-/* Return non-zero if there is room to transmit a character immediately. */
-int uartn_tx_ready(uint8_t uart_num);
-
-/* Return non-zero if a transmit is in progress. */
-int uartn_tx_in_progress(uint8_t uart_num);
-
-/* Return non-zero if the UART has a character available to read. */
-int uartn_rx_available(uint8_t uart_num);
-
-/*
- * Send a character to the UART data register.
- *
- * If the transmit FIFO is full, blocks until there is space.
- *
- * @param c    Character to send.
- */
-void uartn_write_char(uint8_t uart_num, char c);
-
-/*
- * Read one char from the UART data register.
- *
- * @return		The character read.
- */
-int uartn_read_char(uint8_t uart_num);
-
-/* Clear all data in the UART Rx FIFO */
-void uartn_clear_rx_fifo(int channel);
-
-/* Enable the UART Rx interrupt */
-void uartn_rx_int_en(uint8_t uart_num);
-/* Enable the UART Wake-up */
-void uartn_wui_en(uint8_t uart_num);
-/* Enable/disable Tx NXMIP (No Transmit In Progress) interrupt */
-void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable);
-#endif  /* __CROS_EC_UARTN_H */
diff --git a/chip/npcx/watchdog.c b/chip/npcx/watchdog.c
deleted file mode 100644
index 55b8df8c1c..0000000000
--- a/chip/npcx/watchdog.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "registers.h"
-#include "hwtimer_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "timer.h"
-#include "task.h"
-#include "util.h"
-#include "system_chip.h"
-#include "watchdog.h"
-
-/* WDCNT value for watchdog period */
-#define WDCNT_VALUE \
-	((CONFIG_WATCHDOG_PERIOD_MS * INT_32K_CLOCK) / (1024 * 1000))
-
-void watchdog_init_warning_timer(void)
-{
-	/* init watchdog timer first */
-	init_hw_timer(ITIM_WDG_NO, ITIM_SOURCE_CLOCK_32K);
-
-	/*
-	 * prescaler to TIMER_TICK
-	 * Ttick_unit = (PRE_8+1) * T32k
-	 * PRE_8 = (Ttick_unit/T32K) - 1
-	 * Unit: 1 msec
-	 */
-	NPCX_ITPRE(ITIM_WDG_NO) =
-		DIV_ROUND_NEAREST(1000 * INT_32K_CLOCK, SECOND) - 1;
-
-	/* Event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-	/* ITIM count down : event expired */
-	NPCX_ITCNT(ITIM_WDG_NO) = CONFIG_AUX_TIMER_PERIOD_MS;
-	/* Event module enable */
-	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-	/* Enable interrupt of ITIM */
-	task_enable_irq(ITIM_INT(ITIM_WDG_NO));
-}
-
-static timestamp_t last_watchdog_touch;
-void watchdog_stop_and_unlock(void)
-{
-	/*
-	 * Ensure we have waited at least 3 watchdog ticks since touching WD
-	 * timer. 3 / (32768 / 1024) HZ = 93.75ms
-	 */
-	while (time_since32(last_watchdog_touch) < (100 * MSEC))
-		continue;
-
-	NPCX_WDSDM = 0x87;
-	NPCX_WDSDM = 0x61;
-	NPCX_WDSDM = 0x63;
-}
-
-static void touch_watchdog_count(void)
-{
-	NPCX_WDSDM = 0x5C;
-	last_watchdog_touch = get_time();
-}
-
-static void watchdog_reload_warning_timer(void)
-{
-	/* Disable warning timer module  */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-	/* Wait for module disable to take effect before updating count */
-	while (IS_BIT_SET(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN))
-		;
-
-	/* Reload the warning timer count */
-	NPCX_ITCNT(ITIM_WDG_NO) = CONFIG_AUX_TIMER_PERIOD_MS;
-
-	/* enable warning timer module  */
-	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-	/* Wait for module enable */
-	while (!IS_BIT_SET(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN))
-		;
-}
-
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-#ifdef CONFIG_TASK_PROFILING
-	/*
-	 * Perform IRQ profiling accounting. This is normally done by
-	 * DECLARE_IRQ(), but we are not using that for ITIM_WDG_NO.
-	 */
-	task_start_irq_handler((void *)excep_lr);
-#endif
-
-	/* Clear timeout status for event */
-	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_TO_STS);
-
-	/* Print panic info */
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-/* ISR for watchdog warning naked will keep SP & LR */
-void IRQ_HANDLER(ITIM_INT(ITIM_WDG_NO))(void) __attribute__((naked));
-void IRQ_HANDLER(ITIM_INT(ITIM_WDG_NO))(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-			"mov r1, sp\n"
-			/* Must push registers in pairs to keep 64-bit aligned
-			 * stack for ARM EABI.  This also conveninently saves
-			 * R0=LR so we can pass it to task_resched_if_needed. */
-			"push {r0, lr}\n"
-			"bl watchdog_check\n"
-			"pop {r0, lr}\n"
-			"b task_resched_if_needed\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(ITIM_INT(ITIM_WDG_NO))
-__attribute__((section(".rodata.irqprio")))
-= {ITIM_INT(ITIM_WDG_NO), 0};
-/* put the watchdog at the highest priority */
-
-void watchdog_reload(void)
-{
-	/* Disable watchdog interrupt */
-	task_disable_irq(ITIM_INT(ITIM_WDG_NO));
-
-	watchdog_reload_warning_timer();
-
-#if 1 /* mark this for testing watchdog */
-	/* Touch watchdog & reset software counter */
-	touch_watchdog_count();
-#endif
-
-	/* Enable watchdog interrupt */
-	task_enable_irq(ITIM_INT(ITIM_WDG_NO));
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-#if SUPPORT_WDG
-	/* Touch watchdog before init if it is already running */
-	if (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_WD_RUN))
-		touch_watchdog_count();
-
-	/* Keep prescaler ratio timer0 clock to 1:1024 */
-	NPCX_TWCP = 0x0A;
-	/* Keep prescaler ratio watchdog clock to 1:1 */
-	NPCX_WDCP = 0;
-
-	/* Clear watchdog reset status initially*/
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS);
-
-	/* Reset TWCFG */
-	NPCX_TWCFG = 0;
-	/* Watchdog touch by writing 5Ch to WDSDM */
-	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDSDME);
-	/* Select T0IN clock as watchdog prescaler clock */
-	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDCT0I);
-	/* Disable early touch functionality */
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_TESDIS);
-
-	/*
-	 * Set WDCNT initial reload value and T0OUT timeout period
-	 * WDCNT = 0 will generate watchdog reset
-	 */
-	NPCX_WDCNT = WDCNT_VALUE;
-
-	/* Disable interrupt */
-	interrupt_disable();
-	/* Reload TWDT0/WDCNT */
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
-	/* Wait for timer is loaded and restart */
-	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
-		;
-	/* Enable interrupt */
-	interrupt_enable();
-
-	/* Init watchdog warning timer */
-	watchdog_init_warning_timer();
-#endif
-	return EC_SUCCESS;
-}
diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c
deleted file mode 100644
index c4f68f5369..0000000000
--- a/chip/npcx/wov.c
+++ /dev/null
@@ -1,2071 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific WOV module for Chrome EC */
-
-#include "apm_chip.h"
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "wov_chip.h"
-
-#ifndef NPCX_WOV_SUPPORT
-#error "Do not enable CONFIG_AUDIO_CODEC_* if npcx ec doesn't support WOV !"
-#endif
-
-/* Console output macros */
-#ifndef DEBUG_AUDIO_CODEC
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_AUDIO_CODEC, outstr)
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
-#endif
-
-/* WOV FIFO status. */
-#define WOV_STATUS_OFFSET NPCX_WOV_STATUS_CFIFO_OIT
-#define WOV_IS_CFIFO_INT_THRESHOLD(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_CFIFO_OIT - WOV_STATUS_OFFSET))
-#define WOV_IS_CFIFO_WAKE_THRESHOLD(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_CFIFO_OWT - WOV_STATUS_OFFSET))
-#define WOV_IS_CFIFO_OVERRUN(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_CFIFO_OVRN - WOV_STATUS_OFFSET))
-#define WOV_IS_I2S_FIFO_OVERRUN(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_I2S_FIFO_OVRN - WOV_STATUS_OFFSET))
-#define WOV_IS_I2S_FIFO_UNDERRUN(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_I2S_FIFO_UNDRN - WOV_STATUS_OFFSET))
-
-/* Core FIFO threshold. */
-#define WOV_SET_FIFO_WAKE_THRESHOLD(n) \
-	SET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_FIFO_WTHRSH, n)
-
-#define WOV_SET_FIFO_INT_THRESHOLD(n) \
-	SET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_FIFO_ITHRSH, n)
-#define WOV_GET_FIFO_INT_THRESHOLD \
-	GET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_FIFO_ITHRSH)
-
-#define WOV_PLL_IS_NOT_LOCK \
-	(!IS_BIT_SET(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_LOCKI))
-
-/* mask definitions that clear reserved fields for WOV registers.*/
-#define WOV_CLK_CTRL_REG_RESERVED_MASK 0x037F7FFF
-
-#define WOV_GET_FIFO_WAKE_THRESHOLD \
-	GET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_FIFO_WTHRSH)
-
-/* Wait time 4ms for FMUL2 enabled and for configuration tuning sequence. */
-#define WOV_FMUL2_CLK_TUNING_DELAY_TIME (4 * 1000)
-
-/* The size of RAM buffer to store the voice data */
-#define VOICE_BUF_SIZE    16000
-
-/* PLL setting options. */
-struct wov_pll_set_options_val {
-	uint8_t pll_indv;     /* Input Divider */
-	uint16_t pll_fbdv;    /* Feedback Divider */
-	uint8_t pll_otdv1;    /* Output devide 1. */
-	uint8_t pll_otdv2;    /* Output devide 2. */
-	uint32_t pll_ext_div; /* Index for the table pll_ext_div */
-};
-
-/* PLL External Divider Load Values. */
-struct wov_pll_ext_div_val {
-	uint8_t pll_ediv;    /* Required PLL external divider */
-	uint8_t pll_ediv_dc; /* Required PLL external divider DC */
-};
-
-static const struct wov_pll_ext_div_val pll_ext_div[] = {
-	{0x2F, 0x78}, /* 12 */
-	{0x57, 0x7C}, /* 13 */
-	{0x2B, 0x7C}, /* 14 */
-	{0x55, 0x7E}, /* 15 */
-	{0x2A, 0x7E}, /* 16 */
-	{0x15, 0x7F}, /* 17 */
-	{0x4A, 0x7F}, /* 18 */
-	{0x65, 0x3F}, /* 19 */
-	{0x32, 0x3F}, /* 20 */
-	{0x19, 0x5F}, /* 21 */
-	{0x4C, 0x5F}, /* 22 */
-	{0x66, 0x2F}, /* 23 */
-	{0x73, 0x2F}, /* 24 */
-	{0x39, 0x57}, /* 25 */
-	{0x5C, 0x57}, /* 26 */
-	{0x6E, 0x2B}, /* 27 */
-	{0x77, 0x2B}, /* 28 */
-	{0x3B, 0x55}, /* 29 */
-	{0x5D, 0x55}, /* 30 */
-	{0x2E, 0x2A}, /* 31 */
-	{0x17, 0x2A}, /* 32 */
-	{0x4B, 0x15}, /* 33 */
-	{0x25, 0x15}, /* 34 */
-	{0x52, 0x4A}, /* 35 */
-	{0x69, 0x4A}, /* 36 */
-	{0x34, 0x65}, /* 37 */
-	{0x1A, 0x65}, /* 38 */
-	{0x0D, 0x32}, /* 39 */
-	{0x46, 0x32}, /* 40 */
-	{0x63, 0x19}, /* 41 */
-	{0x31, 0x19}, /* 42 */
-	{0x58, 0x4C}, /* 43 */
-	{0x6C, 0x4C}, /* 44 */
-	{0x76, 0x66}, /* 45 */
-	{0x7B, 0x66}, /* 46 */
-	{0x3D, 0x73}, /* 47 */
-	{0x5E, 0x73}, /* 48 */
-	{0x6F, 0x39}, /* 49 */
-	{0x37, 0x39}, /* 50 */
-	{0x5B, 0x5C}, /* 51 */
-	{0x2D, 0x5C}, /* 52 */
-	{0x56, 0x6E}, /* 53 */
-	{0x6B, 0x6E}, /* 54 */
-	{0x35, 0x77}, /* 55 */
-	{0x5A, 0x77}, /* 56 */
-	{0x6D, 0x3B}, /* 57 */
-	{0x36, 0x3B}, /* 58 */
-	{0x1B, 0x5D}, /* 59 */
-	{0x4D, 0x5D}, /* 60 */
-	{0x26, 0x2E}, /* 61 */
-	{0x13, 0x2E}, /* 62 */
-	{0x49, 0x17}, /* 63 */
-	{0x24, 0x17}, /* 64 */
-	{0x12, 0x4B}, /* 65 */
-	{0x09, 0x4B}, /* 66 */
-	{0x44, 0x25}  /* 67 */
-};
-
-/* WOV interrupts */
-static const uint8_t wov_interupts[] = {
-	0,  /* VAD_INTEN */
-	1,  /* VAD_WKEN */
-	8,  /* CFIFO_NE_IE */
-	9,  /* CFIFO_OIT_IE */
-	10, /* CFIFO_OWT_WE */
-	11, /* CFIFO_OVRN_IE */
-	12, /* I2S_FIFO_OVRN_IE */
-	13  /* I2S_FIFO_UNDRN_IE */
-};
-
-struct wov_ppl_divider {
-	uint16_t pll_frame_len; /* PLL frame length. */
-	uint16_t pll_fbdv;      /* PLL feedback divider. */
-	uint8_t pll_indv;       /* PLL Input Divider. */
-	uint8_t pll_otdv1;      /* PLL Output Divider 1. */
-	uint8_t pll_otdv2;      /* PLL Output Divider 2. */
-	uint8_t pll_ediv;       /* PLL External Divide Factor. */
-};
-
-struct wov_cfifo_buf {
-	uint32_t *buf; /* Pointer to a buffer. */
-	int size;      /* Buffer size in words. */
-};
-
-struct wov_config wov_conf;
-
-static struct wov_cfifo_buf cfifo_buf;
-static wov_call_back_t callback_fun;
-
-#define WOV_RATE_ERROR_THRESH_MSEC 10
-#define WOV_RATE_ERROR_THRESH 5
-
-static int irq_underrun_count;
-static int irq_overrun_count;
-static uint32_t wov_i2s_underrun_tstamp;
-static uint32_t wov_i2s_overrun_tstamp;
-
-#define WOV_CALLBACK(event)                  \
-	{                                    \
-		if (callback_fun != NULL)    \
-			callback_fun(event); \
-	}
-
-#define CONFIG_WOV_FIFO_THRESH_WORDS WOV_FIFO_THRESHOLD_80_DATA_WORDS
-
-/**
- * Reads data from the core fifo.
- *
- * @param   num_elements - Number of elements (Dword) to read.
- *
- * @return  None
- */
-void wov_cfifo_read_handler_l(uint32_t num_elements)
-{
-	uint32_t index;
-
-	for (index = 0; index < num_elements; index++)
-		cfifo_buf.buf[index] = NPCX_WOV_FIFO_OUT;
-
-	cfifo_buf.buf = &cfifo_buf.buf[index];
-	cfifo_buf.size -= num_elements;
-}
-
-static enum ec_error_list wov_calc_pll_div_s(int32_t d_in,
-					int32_t total_div, int32_t vco_freq,
-					struct wov_ppl_divider *pll_div)
-{
-	int32_t	 d_1, d_2, d_e;
-
-	/*
-	 * Please see comments in wov_calc_pll_div_l function below.
-	 */
-	for (d_e = 4; d_e < 75; d_e++) {
-		for (d_2 = 1; d_2 < 7; d_2++) {
-			for (d_1 = 1; d_1 < 7; d_1++) {
-				if ((vco_freq / (d_1 * d_2)) > 900)
-					continue;
-
-				if (total_div == (d_in * d_e * d_1 * d_2)) {
-					pll_div->pll_indv  = d_in;
-					pll_div->pll_otdv1 = d_1;
-					pll_div->pll_otdv2 = d_2;
-					pll_div->pll_ediv  = d_e;
-					return EC_SUCCESS;
-				}
-			}
-		}
-	}
-	return EC_ERROR_INVAL;
-}
-
-/**
- * Gets the PLL divider value accordingly to the i2S clock frequency.
- *
- * @param   i2s_clk_freq - i2S clock frequency
- * @param   sample_rate  - Sample rate in KHz (16KHz or 48KHz)
- * @param   pll_div      - PLL dividers.
- *
- * @return  None
- */
-static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq,
-			uint32_t sample_rate, struct wov_ppl_divider *pll_div)
-{
-	int32_t d_f;
-	int32_t total_div;
-	int32_t d_in;
-	int32_t n;
-	int32_t vco_freq;
-	int32_t i2s_clk_freq_khz;
-
-	n = i2s_clk_freq / sample_rate;
-	if (i2s_clk_freq != (sample_rate * n))
-		return EC_ERROR_INVAL;
-
-	if ((n < 32) || (n >= 257))
-		return EC_ERROR_INVAL;
-
-	pll_div->pll_frame_len = n;
-
-	i2s_clk_freq_khz = i2s_clk_freq / 1000;
-
-	/*
-	 * The code below implemented the “PLL setting option” table as
-	 * describe in the NPCX7m7wb specification document.
-	 * - Total_div is VCO frequency in MHz / 12 MHz
-	 * - d_f is the Feedback Divider
-	 * - d_in is the Input Divider (PLL_INDV)
-	 * - d_e is the PLL Ext Divider
-	 * - d_2 is the Output Divide 2 (PLL_OTDV2)
-	 * - d_1 is the Output Divide 1 (PLL_OTDV1)
-	 * It is preferred that d_f will be as smaller as possible, after that
-	 * the d_in will be as smaller as possible and so on, this is the
-	 * reason that d_f (calculated from total_div) is in the external loop
-	 * and d-1 is in the internal loop (as it may contain the bigger value).
-	 * The “PLL setting option” code divided to 2 function in order to
-	 * fulfil the coding style indentation rule.
-	 */
-
-	/* total div is min_vco/12 400/12=33. */
-	for (total_div = 33; total_div < 1500; total_div++) {
-		d_f = (total_div * 12000) / i2s_clk_freq_khz;
-		if ((total_div * 12000) == (d_f * i2s_clk_freq_khz)) {
-			for (d_in = 1; d_in < 10; d_in++) {
-				if (((i2s_clk_freq / 1000) / d_in) <= 500)
-					continue;
-
-				vco_freq = total_div * 12 / d_in;
-				if ((vco_freq < 500) || (vco_freq > 1600))
-					continue;
-				if (wov_calc_pll_div_s(d_in, total_div,
-						vco_freq, pll_div) ==
-						EC_SUCCESS) {
-					pll_div->pll_fbdv  = d_f;
-					return EC_SUCCESS;
-				}
-
-			}
-		}
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-/**
- * Check if PLL is locked.
- *
- * @param   None
- *
- * @return  EC_SUCCESS if PLL is locked, EC_ERROR_UNKNOWN otherwise .
- */
-enum ec_error_list wov_wait_for_pll_lock_l(void)
-{
-	volatile uint32_t index;
-
-	for (index = 0; WOV_PLL_IS_NOT_LOCK; index++) {
-		/* PLL doesn't reach to lock state. */
-		if (index > 0xFFFF)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Configure I2S bus. (Parameters determined via common config functions.)
- *
- * @param   None.
- *
- * @return  none.
- */
-static enum ec_error_list wov_set_i2s_config_l(void)
-{
-	struct wov_ppl_divider pll_div;
-	enum ec_error_list ret_code;
-	enum wov_i2s_chan_trigger trigger_0, trigger_1;
-	int32_t start_delay_0, start_delay_1;
-
-	ret_code = wov_calc_pll_div_l(wov_conf.i2s_clock,
-				wov_conf.sample_per_sec, &pll_div);
-	if (ret_code == EC_SUCCESS) {
-		/* Configure the PLL. */
-		ret_code = wov_pll_clk_div_config(
-			pll_div.pll_otdv1, pll_div.pll_otdv2, pll_div.pll_fbdv,
-			pll_div.pll_indv);
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-
-		ret_code = wov_pll_clk_ext_div_config(
-			(enum wov_pll_ext_div_sel)(pll_div.pll_ediv > 15),
-			pll_div.pll_ediv);
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-
-		wov_i2s_global_config(
-			(enum wov_floating_mode)(wov_conf.dai_format ==
-						 WOV_DAI_FMT_PCM_TDM),
-			WOV_FLOATING_DRIVEN, WOV_CLK_NORMAL, 0, WOV_PULL_DOWN,
-			0, WOV_PULL_DOWN, WOV_NORMAL_MODE);
-
-		/* Configure DAI format. */
-		switch (wov_conf.dai_format) {
-		case WOV_DAI_FMT_I2S:
-			trigger_0 = WOV_I2S_SAMPLED_0_AFTER_1;
-			trigger_1 = WOV_I2S_SAMPLED_1_AFTER_0;
-			start_delay_0 = 1;
-			start_delay_1 = 1;
-			break;
-
-		case WOV_DAI_FMT_RIGHT_J:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_0_AFTER_1;
-			start_delay_0 = (pll_div.pll_frame_len / 2) -
-					wov_conf.bit_depth;
-			start_delay_1 = (pll_div.pll_frame_len / 2) -
-					wov_conf.bit_depth;
-			break;
-
-		case WOV_DAI_FMT_LEFT_J:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_0_AFTER_1;
-			start_delay_0 = 0;
-			start_delay_1 = 0;
-			break;
-
-		case WOV_DAI_FMT_PCM_A:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_1_AFTER_0;
-			start_delay_0 = 1;
-			start_delay_1 = wov_conf.bit_depth + 1;
-			break;
-
-		case WOV_DAI_FMT_PCM_B:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_1_AFTER_0;
-			start_delay_0 = 0;
-			start_delay_1 = wov_conf.bit_depth;
-			break;
-
-		case WOV_DAI_FMT_PCM_TDM:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_1_AFTER_0;
-			start_delay_0 = wov_conf.i2s_start_delay_0;
-			start_delay_1 = wov_conf.i2s_start_delay_1;
-			break;
-
-		default:
-			return EC_ERROR_INVALID_CONFIG;
-		}
-
-		udelay(100);
-
-		ret_code = wov_i2s_channel_config(0, wov_conf.bit_depth,
-					trigger_0, start_delay_0);
-
-		ret_code = wov_i2s_channel_config(1, wov_conf.bit_depth,
-					trigger_1, start_delay_1);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * wov_i2s_channel1_disable
- *
- * @param  disable - disabled flag, 1 means disable
- *
- * @return  None
- */
-static void wov_i2s_channel1_disable(int disable)
-{
-	if (disable)
-		SET_BIT(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(1),
-			  NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS);
-}
-
-/**
- * Sets microphone source.
- *
- *		    |	Left	|  Right	|  Mono		|  Stereo
- *------------------|-----------|---------------|---------------|--------------
- *FIFO_CNT.	    |0x0 or 0x2	| 0x0 or 0x2	| 0x1 or 0x3	|0x1 or 0x3
- *CFIFI_ISEL	    |	(left)	|(left)		|(left & Right)	|(left & right)
- *------------------|-----------|---------------|---------------|--------------
- *CR_DMIC.	    |   0x1	|     0x1	|      0x2	|     0x1
- *ADC_DMIC_SEL_LEFT |  (left)	|    (left)	|   (average)	|   (left)
- *------------------|-----------|---------------|---------------|--------------
- *CR_DMIC.	    |   0x1	|     0x1	|      0x2	|     0x1
- *ADC_DMIC_SEL_RIGHT|  (right)	|    (right)	|   (average)	|   (right)
- *------------------|-----------|---------------|---------------|--------------
- *MIX_2.	    |   0x0	|     0x1	|      0x0	|     0x0
- *AIADCL_SEL	    |  (normal)	|(cross inputs)	|    (normal)	|   (normal)
- *------------------|-----------|---------------|---------------|--------------
- *MIX_2.	    |   0x3	|     0x3	|      0x0	|     0x0
- *AIADCR_SEL	    |(no input)	|  (no input)	|    (normal)	|   (normal)
- *------------------|-----------|---------------|---------------|--------------
- *VAD_0.	    |   0x0	|     0x1	|      0x2	|    Not
- *VAD_INSEL	    |  (left)	|    (right)	|    (average)	|  applicable
- *
- * @param   None.
- * @return  return EC_SUCCESS if mic source valid othewise return error code.
- */
-static enum ec_error_list wov_set_mic_source_l(void)
-{
-	switch (wov_conf.mic_src) {
-	case WOV_SRC_LEFT:
-		if (wov_conf.bit_depth == 16)
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00);
-		else
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
-		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
-					 APM_OUT_MIX_NO_INPUT);
-		apm_set_vad_input_channel(APM_IN_LEFT);
-		wov_i2s_channel1_disable(1);
-		break;
-
-	case WOV_SRC_RIGHT:
-		if (wov_conf.bit_depth == 16)
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00);
-		else
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
-		apm_digital_mixer_config(APM_OUT_MIX_CROSS_INPUT,
-					APM_OUT_MIX_NO_INPUT);
-		apm_set_vad_input_channel(APM_IN_RIGHT);
-		wov_i2s_channel1_disable(1);
-		break;
-
-	case WOV_SRC_MONO:
-		if (wov_conf.bit_depth == 16)
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
-		else
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x02);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x02);
-		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
-					APM_OUT_MIX_NORMAL_INPUT);
-		apm_set_vad_input_channel(APM_IN_AVERAGE_LEFT_RIGHT);
-		wov_i2s_channel1_disable(0);
-		break;
-
-	case WOV_SRC_STEREO:
-		if (wov_conf.bit_depth == 16)
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
-		else
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
-		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
-					 APM_OUT_MIX_NORMAL_INPUT);
-		wov_i2s_channel1_disable(0);
-		break;
-
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-static void wov_over_under_deferred(void)
-{
-	CPRINTS("wov: Under/Over run error: under = %d, over = %d",
-		irq_underrun_count, irq_overrun_count);
-}
-DECLARE_DEFERRED(wov_over_under_deferred);
-
-static void wov_under_over_error_handler(int *count, uint32_t *last_time)
-{
-	uint32_t time_delta_msec;
-	uint32_t current_time = get_time().le.lo;
-
-	if (!(*count)) {
-		*last_time = current_time;
-		(*count)++;
-	} else {
-		time_delta_msec = (current_time - *last_time) / MSEC;
-		*last_time = current_time;
-		if (time_delta_msec < WOV_RATE_ERROR_THRESH_MSEC)
-			(*count)++;
-		else
-			*count = 0;
-
-		if (*count >= WOV_RATE_ERROR_THRESH) {
-			wov_stop_i2s_capture();
-			hook_call_deferred(&wov_over_under_deferred_data, 0);
-		}
-	}
-}
-
-/**
- * WoV interrupt handler.
- *
- * @param   None
- *
- * @return  None
- */
-void wov_interrupt_handler(void)
-{
-	uint32_t wov_status;
-	uint32_t wov_inten;
-
-	wov_inten = GET_FIELD(NPCX_WOV_WOV_INTEN, NPCX_WOV_STATUS_BITS);
-	wov_status = wov_inten &
-			GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS);
-
-	/*
-	 * Voice activity detected.
-	 */
-	if (APM_IS_VOICE_ACTIVITY_DETECTED) {
-		apm_enable_vad_interrupt(0);
-		APM_CLEAR_VAD_INTERRUPT;
-		WOV_CALLBACK(WOV_EVENT_VAD);
-	}
-
-	/* Core FIFO is overrun. Reset the Core FIFO and inform the FW */
-	if (WOV_IS_CFIFO_OVERRUN(wov_status)) {
-		WOV_CALLBACK(WOV_EVENT_ERROR_CORE_FIFO_OVERRUN);
-		wov_core_fifo_reset();
-	} else if (WOV_IS_CFIFO_INT_THRESHOLD(wov_status) &&
-				(cfifo_buf.buf != NULL)) {
-		/*
-		 * Core FIFO threshold or FIFO not empty event occurred.
-		 * - Read data from core FIFO to the buffer.
-		 * - In case data ready or no space for data, inform the FW.
-		 */
-
-		/* Copy data from CFIFO to RAM. */
-		wov_cfifo_read_handler_l((WOV_GET_CORE_FIFO_THRESHOLD * 2));
-
-		if (cfifo_buf.size < (WOV_GET_CORE_FIFO_THRESHOLD * 2)) {
-			cfifo_buf.buf = NULL;
-			cfifo_buf.size = 0;
-			WOV_CALLBACK(WOV_EVENT_DATA_READY);
-		}
-	}
-
-	/* I2S FIFO is overrun. Reset the I2S FIFO and inform the FW. */
-	if (WOV_IS_I2S_FIFO_OVERRUN(wov_status)) {
-		WOV_CALLBACK(WOV_EVENT_ERROR_I2S_FIFO_OVERRUN);
-		wov_under_over_error_handler(&irq_overrun_count,
-					     &wov_i2s_overrun_tstamp);
-		wov_i2s_fifo_reset();
-	}
-
-	/* I2S FIFO is underrun. Reset the I2S FIFO and inform the FW. */
-	if (WOV_IS_I2S_FIFO_UNDERRUN(wov_status)) {
-		WOV_CALLBACK(WOV_EVENT_ERROR_I2S_FIFO_UNDERRUN);
-		wov_under_over_error_handler(&irq_underrun_count,
-					     &wov_i2s_underrun_tstamp);
-		wov_i2s_fifo_reset();
-	}
-
-
-	/* Clear the WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, wov_status);
-}
-
-DECLARE_IRQ(NPCX_IRQ_WOV, wov_interrupt_handler, 4);
-
-/**
- * Enable FMUL2.
- *
- * @param   enable - enabled flag, true for enable
- * @return  None
- */
-static void wov_fmul2_enable(int enable)
-{
-	if (enable) {
-
-		/* If clock disabled, then enable it. */
-		if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) {
-			/* Enable clock tuning. */
-			CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-			/* Enable clock. */
-			CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
-
-			udelay(WOV_FMUL2_CLK_TUNING_DELAY_TIME);
-
-		}
-	} else
-		SET_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
-}
-
-#define WOV_FMUL2_MAX_RETRIES 0x000FFFFF
-
-/* FMUL2 clock multipliers values. */
-struct wov_fmul2_multiplier_setting_val {
-	uint8_t fm2mh;
-	uint8_t fm2ml;
-	uint8_t fm2n;
-};
-
-/**
- * Configure FMUL2 clock tunning.
- *
- * @param   None
- * @return  None
- */
-void wov_fmul2_conf_tuning(void)
-{
-	/* Check if FMUL2 is enabled, then do nothing. */
-	if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS) ==
-			0x00)
-		return;
-
-	/* Enable clock tuning. */
-	CLEAR_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-
-	udelay(WOV_FMUL2_CLK_TUNING_DELAY_TIME);
-
-	/* Disable clock tuning. */
-	SET_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-}
-
-static int wov_get_cfifo_threshold_l(void)
-{
-	int fifo_threshold;
-
-	fifo_threshold = WOV_GET_FIFO_INT_THRESHOLD;
-
-	if (fifo_threshold == 0)
-		return 1;
-	else
-		return (fifo_threshold * 2);
-}
-
-/**
- * Gets clock source FMUL2 or PLL.
- *
- * @param   None.
- *
- *  NOTE:
- *
- * @return  The clock source FMUL2 (WOV_FMUL2_CLK_SRC) and
- *                    PLL (WOV_PLL_CLK_SRC)
- */
-static enum wov_clk_src_sel wov_get_clk_selection(void)
-{
-	if (IS_BIT_SET(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_CLK_SEL))
-		return WOV_PLL_CLK_SRC;
-	else
-		return WOV_FMUL2_CLK_SRC;
-}
-
-/***************************************************************************
- *
- * Exported function.
- *
- **************************************************************************/
-
-/**
- * Set FMUL2 clock divider.
- *
- * @param   None
- * @return  None
- */
-void wov_fmul2_set_clk_divider(enum fmul2_clk_divider clk_div)
-{
-	SET_FIELD(NPCX_FMUL2_FM2P, NPCX_FMUL2_FM2P_WFPRED, clk_div);
-}
-
-/**
- * Configure DMIC clock.
- *
- * @param   enable          - DMIC enabled , 1 means enable
- * @param   clk_div         - DMIC clock division factor (disable, divide by 2
- *			      divide by 4)
- * @return  None
- */
-void wov_dmic_clk_config(int enable, enum wov_dmic_clk_div_sel clk_div)
-{
-	/* If DMIC enabled then configured its clock.*/
-	if (enable) {
-		if (clk_div != WOV_DMIC_DIV_DISABLE) {
-			SET_BIT(NPCX_WOV_CLOCK_CNTL,
-				NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN);
-			if (clk_div == WOV_DMIC_DIV_BY_2)
-				CLEAR_BIT(NPCX_WOV_CLOCK_CNTL,
-					  NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL);
-			else
-				SET_BIT(NPCX_WOV_CLOCK_CNTL,
-					NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL);
-		} else
-			CLEAR_BIT(NPCX_WOV_CLOCK_CNTL,
-				  NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN);
-
-		SET_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_DMIC_EN);
-	} else
-		CLEAR_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_DMIC_EN);
-}
-
-/**
- * Sets WoV mode
- *
- * @param   wov_mode - WoV mode
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_set_mode(enum wov_modes wov_mode)
-{
-	enum ec_error_list ret_code;
-	enum wov_clk_src_sel prev_clock;
-
-	/* If mode is OFF, then power down and exit. */
-	if (wov_mode == WOV_MODE_OFF) {
-		wov_stop_i2s_capture();
-		wov_stop_ram_capture();
-		wov_set_clk_selection(WOV_FMUL2_CLK_SRC);
-		wov_dmic_clk_config(0, WOV_DMIC_DIV_DISABLE);
-		wov_mute(1);
-		apm_set_mode(WOV_MODE_OFF);
-		wov_fmul2_enable(0);
-		wov_conf.mode = WOV_MODE_OFF;
-		return EC_SUCCESS;
-	}
-
-	switch (wov_mode) {
-	case WOV_MODE_VAD:
-		if (apm_get_vad_dmic_rate() == APM_DMIC_RATE_0_75)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_4);
-		else if (apm_get_vad_dmic_rate() == APM_DMIC_RATE_1_2)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_2);
-		else
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_DISABLE);
-		wov_stop_i2s_capture();
-		wov_stop_ram_capture();
-		wov_set_clk_selection(WOV_FMUL2_CLK_SRC);
-		apm_set_mode(wov_mode);
-		ret_code = wov_set_mic_source_l();
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-		break;
-	case WOV_MODE_RAM:
-		if ((wov_conf.bit_depth != 16) && (wov_conf.bit_depth != 24))
-			return EC_ERROR_INVAL;
-
-		if (apm_get_adc_ram_dmic_rate() == APM_DMIC_RATE_0_75)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_4);
-		else if (apm_get_adc_ram_dmic_rate() == APM_DMIC_RATE_1_2)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_2);
-		else
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_DISABLE);
-		wov_stop_i2s_capture();
-		wov_set_clk_selection(WOV_FMUL2_CLK_SRC);
-		apm_set_mode(wov_mode);
-		ret_code = wov_set_mic_source_l();
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-		wov_start_ram_capture();
-		break;
-	case WOV_MODE_RAM_AND_I2S:
-		if ((wov_conf.bit_depth != 16) && (wov_conf.bit_depth != 24))
-			return EC_ERROR_INVAL;
-	case WOV_MODE_I2S:
-		if (apm_get_adc_i2s_dmic_rate() == APM_DMIC_RATE_0_75)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_4);
-		else if (apm_get_adc_i2s_dmic_rate() == APM_DMIC_RATE_1_2)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_2);
-		else
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_DISABLE);
-		prev_clock = wov_get_clk_selection();
-		if (prev_clock != WOV_PLL_CLK_SRC) {
-			wov_set_i2s_config_l();
-			wov_set_clk_selection(WOV_PLL_CLK_SRC);
-		}
-		apm_set_mode(wov_mode);
-		ret_code = wov_set_mic_source_l();
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-		wov_start_i2s_capture();
-		if (wov_mode == WOV_MODE_RAM_AND_I2S)
-			wov_start_ram_capture();
-		else
-			wov_stop_ram_capture();
-		break;
-	default:
-		wov_dmic_clk_config(0, WOV_DMIC_DIV_DISABLE);
-		wov_fmul2_enable(0);
-		wov_mute(1);
-		return EC_ERROR_INVAL;
-	}
-
-	wov_mute(0);
-
-	wov_conf.mode = wov_mode;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Gets WoV mode
- *
- * @param   None
- * @return  WoV mode
- */
-enum wov_modes wov_get_mode(void)
-{
-	return wov_conf.mode;
-}
-
-/**
- * Initiates WoV.
- *
- * @param	callback	 - Pointer to callback function.
- *
- * @return	None
- */
-void wov_init(void)
-{
-	apm_init();
-
-	wov_apm_active(1);
-	wov_mute(1);
-
-	wov_conf.mode = WOV_MODE_OFF;
-	wov_conf.sample_per_sec = 16000;
-	wov_conf.bit_depth = 16;
-	wov_conf.mic_src = WOV_SRC_LEFT;
-	wov_conf.left_chan_gain = 0;
-	wov_conf.right_chan_gain = 0;
-	wov_conf.i2s_start_delay_0 = 0;
-	wov_conf.i2s_start_delay_1 = 0;
-	wov_conf.i2s_clock = 0;
-	wov_conf.dai_format = WOV_DAI_FMT_I2S;
-	wov_conf.sensitivity_db = 5;
-
-	/* Set DMIC clock signal output to use fast transitions. */
-	SET_BIT(NPCX_DEVALT(0xE), NPCX_DEVALTE_DMCLK_FAST);
-
-	callback_fun = wov_handle_event;
-
-	wov_cfifo_config(WOV_CFIFO_IN_LEFT_CHAN_2_CONS_16_BITS,
-			 WOV_FIFO_THRESHOLD_80_DATA_WORDS);
-
-	apm_set_vad_dmic_rate(APM_DMIC_RATE_0_75);
-	apm_set_adc_ram_dmic_config(APM_DMIC_RATE_0_75);
-	apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_3_0);
-}
-
-/**
- * Select clock source FMUL2 or PLL.
- *
- * @param   clk_src - select between FMUL2 (WOV_FMUL2_CLK_SRC) and
- *                    PLL (WOV_PLL_CLK_SRC)
- *
- *  NOTE: THIS FUNCTION RESETS THE APM and RETURN ITS REGISSTERS TO THEIR
- *        DEFAULT VALUES !!!!!!!
- *
- * @return  None
- */
-void wov_set_clk_selection(enum wov_clk_src_sel clk_src)
-{
-	int is_apm_disable;
-
-	/*
-	 * Be sure that both clocks are active, as both of them need to
-	 * be active when modify the CLK_SEL bit.
-	 */
-	if (IS_BIT_SET(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN))
-		wov_pll_enable(1);
-
-	if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS))
-		wov_fmul2_enable(1);
-
-	is_apm_disable = IS_BIT_SET(NPCX_APM_CR_APM, NPCX_APM_CR_APM_PD);
-
-	apm_enable(0);
-
-	if (clk_src == WOV_FMUL2_CLK_SRC)
-		CLEAR_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_CLK_SEL);
-	else if (wov_wait_for_pll_lock_l() == EC_SUCCESS)
-		SET_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_CLK_SEL);
-
-	udelay(100);
-
-	if (!is_apm_disable)
-		apm_enable(1);
-
-	/* Disable the unneeded clock. */
-	if (clk_src == WOV_PLL_CLK_SRC)
-		wov_fmul2_enable(0);
-	else
-		wov_pll_enable(0);
-
-}
-
-/**
- * Configure PLL clock.
- *
- * @param   ext_div_sel         - PLL external divider selector.
- * @param   div_factor          - When ext_div_sel is WOV_PLL_EXT_DIV_BIN_CNT
- *                                then it is the 4 LSBits of this field,
- *                                otherwise this field is an index to
- *                                PLL External Divider Load Values table.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_pll_clk_ext_div_config(
-	enum wov_pll_ext_div_sel ext_div_sel,
-	uint32_t div_factor)
-{
-	/* Sets the clock division factor for the PLL external divider.
-	 * The divide factor should be in the range of 2 to 67.
-	 * When ext_div_sel is WOV_PLL_EXT_DIV_BIN_CNT, then the 4 least
-	 * significant bits of div_factor  are used to set the divide
-	 * ratio.
-	 * In this case the divide ration legal values are from 2 to 15
-	 * For WOV_PLL_EXT_DIV_LFSR, this parameter is used as index for
-	 * pll_ext_div table.
-	 */
-	if (ext_div_sel == WOV_PLL_EXT_DIV_BIN_CNT)
-		CLEAR_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL);
-	else
-		SET_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL);
-
-	if (ext_div_sel == WOV_PLL_EXT_DIV_BIN_CNT) {
-		if ((div_factor > 15) || (div_factor < 2))
-			return EC_ERROR_INVAL;
-
-		SET_FIELD(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV,
-			  (div_factor));
-	} else {
-		if ((div_factor > 67) || (div_factor < 12))
-			return EC_ERROR_INVAL;
-
-		SET_FIELD(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV,
-			  pll_ext_div[div_factor - 12].pll_ediv);
-
-		SET_FIELD(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC,
-			  pll_ext_div[div_factor - 12].pll_ediv_dc);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * PLL power down.
- *
- * @param   enable - 1 enable the PLL or 0 PLL disable
- * @return  None
- */
-void wov_pll_enable(int enable)
-{
-	if (enable)
-		CLEAR_BIT(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN);
-	else
-		SET_BIT(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN);
-
-	udelay(100);
-}
-
-/**
- * Configures PLL clock dividers..
- *
- * @param   out_div_1    - PLL output divider #1, valid values 1-7
- * @param   out_div_2    - PLL output divider #2, valid values 1-7
- * @param   feedback_div - PLL feadback divider (Default is 375 decimal)
- * @param   in_div       - PLL input divider
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1,
-					uint32_t out_div_2,
-					uint32_t feedback_div,
-					uint32_t in_div)
-{
-	/* Parameter check. */
-	if ((out_div_1 < 1) || (out_div_1 > 7) ||
-		(out_div_2 < 1) || (out_div_2 > 7))
-		return EC_ERROR_INVAL;
-
-	/*
-	 * PLL configuration sequence:
-	 * 1. Set PLL_PWDEN bit to 1.
-	 * 2. Set PLL divider values.
-	 * 3. Wait 1usec.
-	 * 4. Clear PLL_PWDEN bit to 0 while not changing other PLL parameters.
-	 */
-	SET_BIT(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN);
-
-	SET_FIELD(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_OTDV1, out_div_1);
-	SET_FIELD(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_OTDV2, out_div_2);
-
-	SET_FIELD(NPCX_WOV_PLL_CNTL2, NPCX_WOV_PLL_CNTL2_PLL_FBDV,
-		  feedback_div);
-
-	SET_FIELD(NPCX_WOV_PLL_CNTL2, NPCX_WOV_PLL_CNTL2_PLL_INDV, in_div);
-
-	udelay(100);
-
-	CLEAR_BIT(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN);
-
-	udelay(100);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Enables/Disables WoV interrupt.
- *
- * @param   int_index - Interrupt ID.
- * @param   enable    - enabled flag, 1 means enable
- *
- * @return  None.
- */
-void wov_interrupt_enable(enum wov_interrupt_index int_index, int enable)
-{
-	if (enable)
-		SET_BIT(NPCX_WOV_WOV_INTEN, wov_interupts[int_index]);
-	else
-		CLEAR_BIT(NPCX_WOV_WOV_INTEN, wov_interupts[int_index]);
-}
-
-/**
- * Sets core FIFO threshold.
- *
- * @param   in_sel    - Core FIFO input select
- * @param   threshold - Core FIFO threshold
- *
- * @return  None
- */
-void wov_cfifo_config(enum wov_core_fifo_in_sel in_sel,
-		      enum wov_fifo_threshold threshold)
-{
-	/* Set core FIFO input selection. */
-	SET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CFIFO_ISEL, in_sel);
-
-	/* Set wake & interrupt core FIFO threshold. */
-	WOV_SET_FIFO_WAKE_THRESHOLD(threshold);
-	WOV_SET_FIFO_INT_THRESHOLD(threshold);
-}
-
-/**
- * Start the actual capturing of the Voice data to the RAM.
- * Note that the pointer to the RAM buffer must be precisely
- * set by calling wov_set_buffer();
- *
- * @param   None
- *
- * @return  None
- */
-void wov_start_ram_capture(void)
-{
-	/* Clear the CFIFO status bits in WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, 0x27);
-
-	CLEAR_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CORE_FFRST);
-
-	wov_interrupt_enable(WOV_CFIFO_OVERRUN_INT_INDX, 1);
-	wov_interrupt_enable(WOV_CFIFO_THRESHOLD_INT_INDX, 1);
-	wov_interrupt_enable(WOV_CFIFO_THRESHOLD_WAKE_INDX, 1);
-}
-
-/**
- * Stop the capturing of the Voice data to the RAM.
- *
- * @param   none
- *
- * @return  None
- */
-void wov_stop_ram_capture(void)
-{
-	SET_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CORE_FFRST);
-
-	wov_interrupt_enable(WOV_CFIFO_OVERRUN_INT_INDX, 0);
-	wov_interrupt_enable(WOV_CFIFO_THRESHOLD_INT_INDX, 0);
-	wov_interrupt_enable(WOV_CFIFO_THRESHOLD_WAKE_INDX, 0);
-
-	udelay(100);
-}
-
-/**
- * Rests the Core FIFO.
- *
- * @param   None
- *
- * @return  None
- */
-void wov_core_fifo_reset(void)
-{
-	SET_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CORE_FFRST);
-
-	udelay(1000);
-
-	/* Clear the CFIFO status bits in WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, 0x27);
-
-	CLEAR_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CORE_FFRST);
-}
-
-/**
- * Rests the I2S FIFO.
- *
- * @param   None
- *
- * @return  None
- */
-void wov_i2s_fifo_reset(void)
-{
-	int disable;
-
-	disable = IS_BIT_SET(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-
-	SET_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-
-	udelay(1000);
-
-	/* Clear the I2S status bits in WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, 0x18);
-
-	if (!disable)
-		CLEAR_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-}
-
-/**
- * Start the capturing of the Voice data via I2S.
- *
- * @param   None
- *
- * @return  None
- */
-void wov_start_i2s_capture(void)
-{
-	/* Clear counters used to track for underrun/overrun errors */
-	irq_underrun_count = 0;
-	irq_overrun_count = 0;
-
-	/* Clear the I2S status bits in WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, 0x18);
-
-	CLEAR_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-
-	wov_interrupt_enable(WOV_I2SFIFO_OVERRUN_INT_INDX, 1);
-	wov_interrupt_enable(WOV_I2SFIFO_UNDERRUN_INT_INDX, 1);
-}
-
-/**
- * Stop the capturing of the Voice data via I2S.
- *
- * @param   none
- *
- * @return  None
- */
-void wov_stop_i2s_capture(void)
-{
-	SET_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-
-	wov_interrupt_enable(WOV_I2SFIFO_OVERRUN_INT_INDX, 0);
-	wov_interrupt_enable(WOV_I2SFIFO_UNDERRUN_INT_INDX, 0);
-
-	udelay(100);
-}
-
-/**
- * Sets data buffer for reading from core FIFO
- *
- * @param  buff          - Pointer to the read buffer, buffer must be 32 bits
- *                         aligned.
- * @param  size_in_words - Size must be a multiple of CONFIG_WOV_THRESHOLD_WORDS
- *                         (defaulte = 80 words)
- *
- * @return  None
- *
- *  Note - When the data buffer will be full the FW will be notifyed
- *         about it, and the FW will need to recall to this function.
- */
-int wov_set_buffer(uint32_t *buf, int size_in_words)
-{
-	int cfifo_threshold;
-
-	cfifo_threshold = wov_get_cfifo_threshold_l();
-	if (size_in_words !=
-		((size_in_words / cfifo_threshold) * cfifo_threshold))
-		return EC_ERROR_INVAL;
-
-	cfifo_buf.buf = buf;
-	cfifo_buf.size = size_in_words;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Resets the APM.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void wov_apm_active(int enable)
-{
-	/* For APM it is negativ logic. */
-	if (enable)
-		CLEAR_BIT(NPCX_WOV_APM_CTRL, NPCX_WOV_APM_CTRL_APM_RST);
-	else
-		SET_BIT(NPCX_WOV_APM_CTRL, NPCX_WOV_APM_CTRL_APM_RST);
-}
-
-/**
- * I2S golobal configuration
- *
- * @param   i2s_hiz_data  - Defines when the I2S data output is floating.
- * @param   i2s_hiz       - Defines if the I2S data output is always floating.
- * @param   clk_invert    - Defines the I2S bit clock edge sensitivity
- * @param   out_pull_en   - Enable a pull-up or a pull-down resistor on
- *                          I2S output
- * @param   out_pull_mode - Select a pull-up or a pull-down resistor on
- *                          I2S output
- * @param   in_pull_en    - Enable a pull-up or a pull-down resistor on
- *                          I2S input
- * @param   in_pull_mode  - Select a pull-up or a pull-down resistor on
- *                          I2S intput
- * @param   test_mode     - Selects I2S test mode
- *
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_i2s_global_config(
-	enum wov_floating_mode i2s_hiz_data,
-	enum wov_floating_mode i2s_hiz,
-	enum wov_clk_inverted_mode clk_invert,
-	int out_pull_en,
-	enum wov_pull_upd_down_sel out_pull_mode,
-	int in_pull_en,
-	enum wov_pull_upd_down_sel in_pull_mode,
-	enum wov_test_mode test_mode)
-{
-	/* Check the parameters correctness. */
-	if ((i2s_hiz_data == WOV_FLOATING) &&
-		((GET_FIELD(NPCX_WOV_I2S_CNTL(0),
-				NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0) ||
-		(GET_FIELD(NPCX_WOV_I2S_CNTL(1),
-				NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0)))
-		return EC_ERROR_INVAL;
-
-	/* Set the parameters. */
-	if (i2s_hiz_data == WOV_FLOATING_DRIVEN)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_HIZD);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_HIZD);
-
-	if (i2s_hiz == WOV_FLOATING_DRIVEN)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_HIZ);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_HIZ);
-
-	if (clk_invert == WOV_CLK_NORMAL)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0),
-			  NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV);
-
-	if (out_pull_en)
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_OPE);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_OPE);
-
-	if (out_pull_mode == WOV_PULL_DOWN)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_OPS);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_OPS);
-
-	if (in_pull_en)
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_IPE);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_IPE);
-
-	if (in_pull_mode == WOV_PULL_DOWN)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_IPS);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_IPS);
-
-	if (test_mode == WOV_NORMAL_MODE)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_TST);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_TST);
-
-	/* I2S should be reset in order I2S interface to function correctly. */
-	wov_i2s_fifo_reset();
-
-	return EC_SUCCESS;
-}
-
-/**
- * I2S channel configuration
- *
- * @param  channel_num     - I2S channel number, 0 or 1.
- * @param  bit_count       - I2S channel bit count.
- * @param  trigger         - Define the I2S chanel trigger 1->0 or 0->1
- * @param  start_delay     - Defines the delay from the trigger defined for
- *                           the channel till the first bit (MSB) of the data.
- *
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
-					uint32_t bit_count,
-					enum wov_i2s_chan_trigger trigger,
-					int32_t start_delay)
-{
-	/* Check the parameters correctnes. */
-	if ((channel_num != 0) && (channel_num != 1))
-		return EC_ERROR_INVAL;
-
-	if ((start_delay < 0) || (start_delay > 496))
-		return EC_ERROR_INVAL;
-
-	if ((bit_count != 16) && (bit_count != 18) && (bit_count != 20) &&
-	    (bit_count != 24))
-		return EC_ERROR_INVAL;
-
-	/* Set the parameters. */
-	SET_FIELD(NPCX_WOV_I2S_CNTL(channel_num), NPCX_WOV_I2S_CNTL_I2S_BCNT,
-			(bit_count - 1));
-
-	if (trigger == WOV_I2S_SAMPLED_1_AFTER_0)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(channel_num),
-			  NPCX_WOV_I2S_CNTL_I2S_TRIG);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(channel_num),
-			NPCX_WOV_I2S_CNTL_I2S_TRIG);
-
-	SET_FIELD(NPCX_WOV_I2S_CNTL(channel_num), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-		  start_delay);
-
-	/* I2S should be reset in order I2S interface to function correctly. */
-	wov_i2s_fifo_reset();
-
-	return EC_SUCCESS;
-}
-
-/**
- * Sets sampling rate.
- *
- * @param   samples_per_second - Valid sample rate.
- * @return  In case sample rate is valid return EC_SUCCESS othewise return
- *          error code.
- */
-int wov_set_sample_rate(uint32_t samples_per_second)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return EC_ERROR_INVALID_CONFIG;
-
-	switch (samples_per_second) {
-	case 8000:
-	case 12000:
-	case 16000:
-	case 24000:
-	case 32000:
-	case 48000:
-		wov_conf.sample_per_sec = samples_per_second;
-		return EC_SUCCESS;
-	default:
-		return EC_ERROR_INVAL;
-	}
-}
-
-/**
- * Gets sampling rate.
- *
- * @param   None
- * @return  the current sampling rate.
- */
-uint32_t wov_get_sample_rate(void)
-{
-	return wov_conf.sample_per_sec;
-}
-
-/**
- * Sets sampling depth.
- *
- * @param   bits_num - Valid sample depth in bits.
- * @return  In case sample depth is valid return EC_SUCCESS othewise return
- *          error code.
- */
-int wov_set_sample_depth(int bits_num)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return EC_ERROR_INVALID_CONFIG;
-
-	if ((bits_num != 16) && (bits_num != 18) &&
-		(bits_num != 20) && (bits_num != 24))
-		return EC_ERROR_INVAL;
-
-	wov_conf.bit_depth = bits_num;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Gets sampling depth.
- *
- * @param   None.
- * @return  sample depth in bits.
- */
-int wov_get_sample_depth(void)
-{
-	return wov_conf.bit_depth;
-}
-
-/**
- * Sets microphone source.
- *
- * @param   mic_src - Valid microphone source
- * @return  return EC_SUCCESS if mic source valid othewise return error code.
- */
-int wov_set_mic_source(enum wov_mic_source mic_src)
-{
-	wov_conf.mic_src = mic_src;
-
-	return wov_set_mic_source_l();
-}
-
-/**
- * Gets microphone source.
- *
- * @param   None.
- * @return  sample depth in bits.
- */
-enum wov_mic_source wov_get_mic_source(void)
-{
-	return wov_conf.mic_src;
-}
-
-/**
- * Mutes the WoV.
- *
- * @param   enable  - enabled flag, 1 means enable
- * @return  None
- */
-void wov_mute(int enable)
-{
-	if (enable)
-		SET_BIT(NPCX_APM_CR_ADC, NPCX_APM_CR_ADC_ADC_SOFT_MUTE);
-	else
-		CLEAR_BIT(NPCX_APM_CR_ADC, NPCX_APM_CR_ADC_ADC_SOFT_MUTE);
-}
-
-/**
- * Sets gain
- *
- * @param   left_chan_gain  - Left channel gain.
- * @param   right_chan_gain - Right channel gain
- * @return  None
- */
-void wov_set_gain(int left_chan_gain, int right_chan_gain)
-{
-	wov_conf.left_chan_gain = left_chan_gain;
-	wov_conf.right_chan_gain = right_chan_gain;
-
-	(void) apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT,
-				left_chan_gain, right_chan_gain);
-}
-
-/**
- * Gets gain values
- *
- * @param   left_chan_gain  - address of left channel gain response.
- * @param   right_chan_gain - address of right channel gain response.
- * @return  None
- */
-void wov_get_gain(int *left_chan_gain, int *right_chan_gain)
-{
-	*left_chan_gain = wov_conf.left_chan_gain;
-	*right_chan_gain = wov_conf.right_chan_gain;
-}
-
-/**
- * Enables/Disables ADC.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void wov_enable_agc(int enable)
-{
-	apm_auto_gain_cntrl_enable(enable);
-}
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param stereo                - Stereo enabled flag, 1 means enable.
- * @param target                - Target output level of the ADC.
- * @param noise_gate_threshold  - Noise Gate system select. 1 means enable.
- * @param hold_time             - Hold time before starting AGC adjustment to
- *                                the TARGET value.
- * @param attack_time           - Attack time - gain ramp down.
- * @param decay_time            - Decay time - gain ramp up.
- * @param max_applied_gain      - Maximum Gain Value to apply to the ADC path.
- * @param min_applied_gain      - Minimum Gain Value to apply to the ADC path.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_set_agc_config(int stereo, float target,
-				int noise_gate_threshold, uint8_t hold_time,
-				uint16_t attack_time, uint16_t decay_time,
-				float max_applied_gain, float min_applied_gain)
-{
-	int target_code;
-	int ngth_code;
-	int attack_time_code;
-	int decay_time_code;
-	int max_applied_gain_code;
-	int min_applied_gain_code;
-	enum ec_error_list ret_code;
-	struct apm_auto_gain_config gain_cfg;
-
-	for (target_code = 0; target_code < 16; target_code++) {
-		if (((float)target_code * (-1.5)) == target)
-			break;
-	}
-	if (target_code == 16)
-		return EC_ERROR_INVAL;
-
-	if (noise_gate_threshold == 0)
-		ngth_code = 0;
-	else {
-		for (ngth_code = 0; ngth_code <= 0x07; ngth_code++) {
-			if ((-68 + ngth_code * 6) == noise_gate_threshold)
-				break;
-		}
-		if (ngth_code * 6 > 42)
-			return EC_ERROR_INVAL;
-	}
-
-	if (hold_time > 15)
-		return EC_ERROR_INVAL;
-
-	for (attack_time_code = 0; attack_time_code <= 0x0F;
-			attack_time_code++) {
-		if (((attack_time_code + 1) * 32) == attack_time)
-			break;
-	}
-	if (attack_time_code > 0x0F)
-		return EC_ERROR_INVAL;
-
-	for (decay_time_code = 0; decay_time_code <= 0x0F; decay_time_code++) {
-		if (((decay_time_code + 1) * 32) == decay_time)
-			break;
-	}
-	if (decay_time_code > 0x0F)
-		return EC_ERROR_INVAL;
-
-	for (max_applied_gain_code = 0; max_applied_gain_code < 16;
-			max_applied_gain_code++) {
-		if ((max_applied_gain_code * 1.5) == max_applied_gain)
-			break;
-	}
-	if (max_applied_gain_code == 16) {
-		for (max_applied_gain_code = 18; max_applied_gain_code < 32;
-				max_applied_gain_code++) {
-			if (((max_applied_gain_code * 1.5) - 4) ==
-					max_applied_gain)
-				break;
-		}
-	}
-	if (max_applied_gain_code >= 32)
-		return EC_ERROR_INVAL;
-
-	for (min_applied_gain_code = 0; min_applied_gain_code < 16;
-			min_applied_gain_code++) {
-		if ((min_applied_gain_code * 1.5) == min_applied_gain)
-			break;
-	}
-	if (min_applied_gain_code == 16) {
-		for (min_applied_gain_code = 18; min_applied_gain_code < 32;
-				min_applied_gain_code++) {
-			if (((min_applied_gain_code * 1.5) - 4) ==
-					min_applied_gain)
-				break;
-		}
-	}
-	if (min_applied_gain_code > 32)
-		return EC_ERROR_INVAL;
-
-	gain_cfg.stereo_enable = stereo,
-	gain_cfg.agc_target = (enum apm_adc_target_out_level) target_code;
-	gain_cfg.nois_gate_en = (noise_gate_threshold != 0);
-	gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold) ngth_code;
-	gain_cfg.hold_time = (enum apm_agc_adj_hold_time) hold_time;
-	gain_cfg.attack_time = (enum apm_gain_ramp_time) attack_time_code;
-	gain_cfg.decay_time = (enum apm_gain_ramp_time) decay_time_code;
-	gain_cfg.gain_max = (enum apm_gain_values) max_applied_gain_code;
-	gain_cfg.gain_min = (enum apm_gain_values) min_applied_gain_code;
-
-	ret_code = apm_adc_auto_gain_config(&gain_cfg);
-
-	return ret_code;
-}
-
-/**
- * Sets VAD sensitivity.
- *
- * @param   sensitivity_db - VAD sensitivity in db.
- * @return  None
- */
-int wov_set_vad_sensitivity(int sensitivity_db)
-{
-
-	if ((sensitivity_db < 0) || (sensitivity_db > 31))
-		return EC_ERROR_INVAL;
-
-	wov_conf.sensitivity_db = sensitivity_db;
-
-	apm_set_vad_sensitivity(sensitivity_db);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Gets VAD sensitivity.
- *
- * @param   None.
- * @return  VAD sensitivity in db
- */
-int wov_get_vad_sensitivity(void)
-{
-	return wov_conf.sensitivity_db;
-}
-
-/**
- * Configure I2S bus format. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   format    - one of the following: I2S mode, Right Justified mode,
- *                      Left Justified mode, PCM A Audio, PCM B Audio and
- *                      Time Division Multiplexing
- * @return  EC error code.
- */
-void wov_set_i2s_fmt(enum wov_dai_format format)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return;
-
-	wov_conf.dai_format = format;
-}
-
-/**
- * Configure I2S bus clock. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   i2s_clock - I2S clock frequency in Hz (needed in order to
- *                      configure the internal PLL for 12MHz)
- * @return  EC error code.
- */
-void wov_set_i2s_bclk(uint32_t i2s_clock)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return;
-
-	wov_conf.i2s_clock = i2s_clock;
-}
-
-/**
- * Configure I2S bus. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   ch0_delay - 0 to 496.  Defines the delay from the SYNC till the
- *                      first bit (MSB) of channel 0 (left channel)
- * @param   ch1_delay - -1 to 496.  Defines the delay from the SYNC till the
- *                      first bit (MSB) of channel 1 (right channel).
- *                      If channel 1 is not used set this field to -1.
- *
- * @param   flags     -  WOV_TDM_ADJACENT_TO_CH0 = BIT(0).  There is a
- *                       channel adjacent to channel 0, so float SDAT when
- *                       driving the last bit (LSB) of the channel during the
- *                       second half of the clock cycle to avoid bus contention.
- *
- *                       WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel
- *                       adjacent to channel 1.
- *
- * @return  EC error code.
- */
-enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay,
-				uint32_t flags)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return EC_ERROR_INVALID_CONFIG;
-
-	if ((ch0_delay < 0) || (ch0_delay > 496) ||
-		(ch1_delay < -1) || (ch1_delay > 496))
-		return EC_ERROR_INVAL;
-
-	wov_conf.i2s_start_delay_0 = ch0_delay;
-	wov_conf.i2s_start_delay_1 = ch1_delay;
-
-	SET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-			ch0_delay);
-
-	if (ch1_delay == -1)
-		wov_i2s_channel1_disable(1);
-	else {
-		wov_i2s_channel1_disable(0);
-		SET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-			ch1_delay);
-	}
-
-	if (flags & 0x0001)
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_LBHIZ);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_LBHIZ);
-
-	if (flags & 0x0002)
-		SET_BIT(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_LBHIZ);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_LBHIZ);
-
-	/* I2S should be reset in order I2S interface to function correctly. */
-	wov_i2s_fifo_reset();
-
-	return EC_SUCCESS;
-}
-
-static void wov_system_init(void)
-{
-	/* Set WoV module to be operational. */
-	clock_enable_peripheral(CGC_OFFSET_WOV, CGC_WOV_MASK,
-				CGC_MODE_RUN | CGC_MODE_SLEEP);
-	/* Configure pins from GPIOs to WOV */
-	gpio_config_module(MODULE_WOV, 1);
-	wov_init();
-
-	task_enable_irq(NPCX_IRQ_WOV);
-
-	CPRINTS("WoV init done");
-}
-DECLARE_HOOK(HOOK_INIT, wov_system_init, HOOK_PRIO_DEFAULT);
-
-void wov_handle_event(enum wov_events event)
-{
-	if (event == WOV_EVENT_DATA_READY) {
-		CPRINTS("ram data ready and stop ram capture");
-		/* just capture one times on RAM*/
-		wov_stop_ram_capture();
-	}
-	if (event == WOV_EVENT_VAD)
-		CPRINTS("got vad");
-	if (event == WOV_EVENT_ERROR_CORE_FIFO_OVERRUN)
-		CPRINTS("error: cfifo overrun");
-}
-
-#ifdef DEBUG_AUDIO_CODEC
-static uint32_t voice_buffer[VOICE_BUF_SIZE] = {0};
-
-/* voice data 16Khz 2ch 16bit 1s */
-static int command_wov(int argc, char **argv)
-{
-	static int bit_clk;
-	static enum wov_dai_format i2s_fmt;
-
-	if (argc == 2) {
-		if (strcasecmp(argv[1], "init") == 0) {
-			wov_system_init();
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgget") == 0) {
-			CPRINTS("mode:%d", wov_get_mode());
-			CPRINTS("sample rate:%d", wov_get_sample_rate());
-			CPRINTS("sample bits:%d", wov_get_sample_depth());
-			CPRINTS("mic source:%d", wov_get_mic_source());
-			CPRINTS("vad sensitivity :%d",
-				wov_get_vad_sensitivity());
-			return EC_SUCCESS;
-		}
-		/* Start to capature voice data and store in RAM buffer */
-		if (strcasecmp(argv[1], "capram") == 0) {
-			if (wov_set_buffer((uint32_t *)voice_buffer,
-				sizeof(voice_buffer) / sizeof(uint32_t))
-					== EC_SUCCESS) {
-				CPRINTS("Start RAM Catpure...");
-				wov_start_ram_capture();
-				return EC_SUCCESS;
-			}
-			CPRINTS("Init fail: voice buffer size");
-			return EC_ERROR_INVAL;
-		}
-	} else if (argc == 3) {
-		if (strcasecmp(argv[1], "cfgsrc") == 0) {
-			if (strcasecmp(argv[2], "mono") == 0)
-				wov_set_mic_source(WOV_SRC_MONO);
-			else if (strcasecmp(argv[2], "stereo") == 0)
-				wov_set_mic_source(WOV_SRC_STEREO);
-			else if (strcasecmp(argv[2], "left") == 0)
-				wov_set_mic_source(WOV_SRC_LEFT);
-			else if (strcasecmp(argv[2], "right") == 0)
-				wov_set_mic_source(WOV_SRC_RIGHT);
-			else
-				return EC_ERROR_INVAL;
-
-			wov_i2s_fifo_reset();
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgbit") == 0) {
-			int bits;
-
-			bits = atoi(argv[2]);
-			if ((bits == 16) || (bits == 18) || (bits == 20) ||
-			    (bits == 24)) {
-				return wov_set_sample_depth(bits);
-			}
-		}
-		if (strcasecmp(argv[1], "cfgsfs") == 0) {
-			int fs;
-
-			fs = atoi(argv[2]);
-			return wov_set_sample_rate(fs);
-		}
-		if (strcasecmp(argv[1], "cfgbck") == 0) {
-			int fs;
-
-			fs = wov_get_sample_rate();
-			if (strcasecmp(argv[2], "32fs") == 0)
-				bit_clk = fs * 32;
-			else if (strcasecmp(argv[2], "48fs") == 0)
-				bit_clk = fs * 48;
-			else if (strcasecmp(argv[2], "64fs") == 0)
-				bit_clk = fs * 64;
-			else if (strcasecmp(argv[2], "128fs") == 0)
-				bit_clk = fs * 128;
-			else if (strcasecmp(argv[2], "256fs") == 0)
-				bit_clk = fs * 256;
-			else
-				return EC_ERROR_INVAL;
-
-			wov_set_i2s_fmt(i2s_fmt);
-			wov_set_i2s_bclk(bit_clk);
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgfmt") == 0) {
-			if (strcasecmp(argv[2], "i2s") == 0)
-				i2s_fmt = WOV_DAI_FMT_I2S;
-			else if (strcasecmp(argv[2], "right") == 0)
-				i2s_fmt = WOV_DAI_FMT_RIGHT_J;
-			else if (strcasecmp(argv[2], "left") == 0)
-				i2s_fmt = WOV_DAI_FMT_LEFT_J;
-			else if (strcasecmp(argv[2], "pcma") == 0)
-				i2s_fmt = WOV_DAI_FMT_PCM_A;
-			else if (strcasecmp(argv[2], "pcmb") == 0)
-				i2s_fmt = WOV_DAI_FMT_PCM_B;
-			else if (strcasecmp(argv[2], "tdm") == 0)
-				i2s_fmt = WOV_DAI_FMT_PCM_TDM;
-			else
-				return EC_ERROR_INVAL;
-
-			wov_set_i2s_fmt(i2s_fmt);
-			wov_set_i2s_bclk(bit_clk);
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgdckV") == 0) {
-			if (strcasecmp(argv[2], "1.0") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_1_0);
-			else if (strcasecmp(argv[2], "1.2") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_1_2);
-			else if (strcasecmp(argv[2], "2.4") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_2_4);
-			else if (strcasecmp(argv[2], "3.0") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_3_0);
-			else if (strcasecmp(argv[2], "0.75") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_0_75);
-			else
-				return EC_ERROR_INVAL;
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgdckR") == 0) {
-			if (strcasecmp(argv[2], "1.0") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_1_0);
-			else if (strcasecmp(argv[2], "1.2") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_1_2);
-			else if (strcasecmp(argv[2], "2.4") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_2_4);
-			else if (strcasecmp(argv[2], "3.0") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_3_0);
-			else if (strcasecmp(argv[2], "0.75") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_0_75);
-			else
-				return EC_ERROR_INVAL;
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgdckI") == 0) {
-			if (strcasecmp(argv[2], "1.0") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_1_0);
-			else if (strcasecmp(argv[2], "1.2") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_1_2);
-			else if (strcasecmp(argv[2], "2.4") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_2_4);
-			else if (strcasecmp(argv[2], "3.0") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_3_0);
-			else if (strcasecmp(argv[2], "0.75") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_0_75);
-			else
-				return EC_ERROR_INVAL;
-			return EC_SUCCESS;
-		}
-
-		if (strcasecmp(argv[1], "cfgmod") == 0) {
-			if (strcasecmp(argv[2], "off") == 0) {
-				wov_set_mode(WOV_MODE_OFF);
-				wov_stop_ram_capture();
-			} else if (strcasecmp(argv[2], "vad") == 0) {
-				wov_set_mode(WOV_MODE_VAD);
-			} else if (strcasecmp(argv[2], "ram") == 0) {
-				if (wov_set_buffer((uint32_t *)voice_buffer,
-					sizeof(voice_buffer) / sizeof(uint32_t))
-						== EC_SUCCESS)
-					wov_set_mode(WOV_MODE_RAM);
-				else
-					return EC_ERROR_INVAL;
-			} else if (strcasecmp(argv[2], "i2s") == 0) {
-				wov_set_mode(WOV_MODE_I2S);
-			} else if (strcasecmp(argv[2], "rami2s") == 0) {
-				if (wov_set_buffer((uint32_t *)voice_buffer,
-					sizeof(voice_buffer) / sizeof(uint32_t))
-						== EC_SUCCESS)
-					wov_set_mode(WOV_MODE_RAM_AND_I2S);
-				else
-					return EC_ERROR_INVAL;
-			} else {
-				return EC_ERROR_INVAL;
-			}
-			wov_i2s_fifo_reset();
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "mute") == 0) {
-			if (strcasecmp(argv[2], "enable") == 0) {
-				wov_mute(1);
-				return EC_SUCCESS;
-			}
-			if (strcasecmp(argv[2], "disable") == 0) {
-				wov_mute(0);
-				return EC_SUCCESS;
-			}
-		}
-		if (strcasecmp(argv[1], "fmul2") == 0) {
-			if (strcasecmp(argv[2], "enable") == 0) {
-				CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-				return EC_SUCCESS;
-			}
-			if (strcasecmp(argv[2], "disable") == 0) {
-				SET_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-				return EC_SUCCESS;
-			}
-		}
-		if (strcasecmp(argv[1], "vadsens") == 0)
-			return wov_set_vad_sensitivity(atoi(argv[2]));
-
-		if (strcasecmp(argv[1], "gain") == 0) {
-			wov_set_gain(atoi(argv[2]), atoi(argv[2]));
-			return EC_SUCCESS;
-		}
-	} else if (argc == 5) {
-		if (strcasecmp(argv[1], "cfgtdm") == 0) {
-			int delay0, delay1;
-			uint32_t flags;
-
-			delay0 = atoi(argv[2]);
-			delay1 = atoi(argv[3]);
-			flags = atoi(argv[4]);
-			if ((delay0 > 496) || (delay1 > 496) || (flags > 3) ||
-			    (delay0 < 0) || (delay1 < 0)) {
-				return EC_ERROR_INVAL;
-			}
-			wov_set_i2s_tdm_config(delay0, delay1, flags);
-			return EC_SUCCESS;
-		}
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-DECLARE_CONSOLE_COMMAND(wov, command_wov,
-		"init\n"
-		"mute <enable|disable>\n"
-		"capram\n"
-		"cfgsrc <mono|stereo|left|right>\n"
-		"cfgbit <16|18|20|24>\n"
-		"cfgsfs <8000|12000|16000|24000|32000|48000>\n"
-		"cfgbck <32fs|48fs|64fs|128fs|256fs>\n"
-		"cfgfmt <i2s|right|left|pcma|pcmb|tdm>\n"
-		"cfgmod <off|vad|ram|i2s|rami2s>\n"
-		"cfgtdm [0~496 0~496 0~3]>\n"
-		"cfgdckV <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgdckR <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgdckI <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgget\n"
-		"fmul2 <enable|disable>\n"
-		"vadsens <0~31>\n"
-		"gain <0~31>",
-		"wov configuration");
-#endif
diff --git a/chip/npcx/wov_chip.h b/chip/npcx/wov_chip.h
deleted file mode 100644
index dce534c501..0000000000
--- a/chip/npcx/wov_chip.h
+++ /dev/null
@@ -1,658 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_WOV_CHIP_H
-#define __CROS_EC_WOV_CHIP_H
-
-#include "common.h"
-
-/* FMUL2 clock Frequency. */
-enum fmul2_clk_freq {
-	FMUL2_48_MHZ = 0, /* Default */
-	FMUL2_24_MHZ
-};
-
-enum fmul2_clk_divider {
-	FMUL2_CLK_NO_DIVIDER = 0x00,
-	FMUL2_CLK_DIVIDER_BY_2 = 0x01,
-	FMUL2_CLK_DIVIDER_BY_4 = 0x03, /* Default */
-	FMUL2_CLK_DIVIDER_BY_8 = 0x07
-};
-
-/* Microphone source. */
-enum wov_mic_source {
-	/* Only data from left mic. */
-	WOV_SRC_LEFT = 0,
-	/* Only data from right mic. */
-	WOV_SRC_RIGHT,
-	/* Both channels have the same data (average of left & right */
-	WOV_SRC_MONO,
-	/* Each channel has its own data. */
-	WOV_SRC_STEREO
-};
-
-/* Clock source for APM. */
-enum wov_clk_src_sel {
-	WOV_FMUL2_CLK_SRC = 0,
-	WOV_PLL_CLK_SRC = 1
-};
-
-/* FMUL clock division factore. */
-enum wov_fmul_div {
-	WOV_NODIV = 0,
-	WOV_DIV_BY_2,
-	WOV_DIV_BY_4, /* Default value */
-	WOV_DIV_BY_8
-};
-
-/* Lock state. */
-enum wov_lock_state {
-	WOV_UNLOCK = 0,
-	WOV_LOCK = 1
-};
-
-/* Reference clock source select. */
-enum wov_ref_clk_src_sel {
-	WOV_FREE_RUN_OSCILLATOR = 0,
-	WOV_CRYSTAL_OSCILLATOR = 1
-};
-
-/* PLL external divider select. */
-enum wov_ext_div_sel {
-	WOV_EXT_DIV_BINARY_CNT = 0,
-	WOV_EXT_DIV_LFSR_DIV = 1
-};
-
-/* FMUL output frequency. */
-enum wov_fmul_out_freq {
-	WOV_FMUL_OUT_FREQ_48_MHZ = 0,
-	WOV_FMUL_OUT_FREQ_49_MHZ = 1
-};
-
-/* Digital microphone clock divider select. */
-enum wov_dmic_clk_div_sel {
-	WOV_DMIC_DIV_DISABLE = 1,
-	WOV_DMIC_DIV_BY_2 = 2,
-	WOV_DMIC_DIV_BY_4 = 4
-};
-
-/* FIFO threshold. */
-enum wov_fifo_threshold {
-	WOV_FIFO_THRESHOLD_1_DATA_WORD = 0,
-	WOV_FIFO_THRESHOLD_2_DATA_WORDS = 1,
-	WOV_FIFO_THRESHOLD_4_DATA_WORDS = 2,
-	WOV_FIFO_THRESHOLD_8_DATA_WORDS = 4,
-	WOV_FIFO_THRESHOLD_16_DATA_WORDS = 8,
-	WOV_FIFO_THRESHOLD_32_DATA_WORDS = 16,
-	WOV_FIFO_THRESHOLD_40_DATA_WORDS = 20,
-	WOV_FIFO_THRESHOLD_64_DATA_WORDS = 32,
-	WOV_FIFO_THRESHOLD_80_DATA_WORDS = 40,
-	WOV_FIFO_THRESHOLD_96_DATA_WORDS = 48
-};
-
-/* FIFO DMA request select. */
-enum wov_fifo_dma_req_sel {
-	WOV_FIFO_DMA_DFLT_DMA_REQ_CONN = 0,
-	WOV_FIFO_DMA_DMA_REQ_CON_FIFO
-};
-
-/* FIFO operational state. */
-enum wov_fifo_oper_state {
-	WOV_FIFO_OPERATIONAL = 0,
-	WOV_FIFO_RESET, /* Default */
-};
-
-/* WoV interrupt index. */
-enum wov_interrupt_index {
-	WOV_VAD_INT_INDX,
-	WOV_VAD_WAKE_INDX,
-	WOV_CFIFO_NOT_EMPTY_INDX,
-	WOV_CFIFO_THRESHOLD_INT_INDX,
-	WOV_CFIFO_THRESHOLD_WAKE_INDX,
-	WOV_CFIFO_OVERRUN_INT_INDX,
-	WOV_I2SFIFO_OVERRUN_INT_INDX,
-	WOV_I2SFIFO_UNDERRUN_INT_INDX
-};
-
-/* FIFO DMA request selection. */
-enum wov_dma_req_sel {
-	WOV_DFLT_ESPI_DMA_REQ = 0,
-	WOV_FROM_FIFO_DMA_REQUEST
-};
-
-/* Core FIFO input select. */
-enum wov_core_fifo_in_sel {
-	WOV_CFIFO_IN_LEFT_CHAN_2_CONS_16_BITS = 0, /* Default */
-	WOV_CFIFO_IN_LEFT_RIGHT_CHAN_16_BITS,
-	WOV_CFIFO_IN_LEFT_CHAN_24_BITS,
-	WOV_CFIFO_IN_LEFT_RIGHT_CHAN_24_BITS
-};
-
-/* PLL external divider selector. */
-enum wov_pll_ext_div_sel {
-	WOV_PLL_EXT_DIV_BIN_CNT = 0,
-	WOV_PLL_EXT_DIV_LFSR
-};
-
-/* Code for events for call back function. */
-enum wov_events {
-	WOV_NO_EVENT = 0,
-	/*
-	 * Data is ready.
-	 * need to call to wov_set_buffer to update the buffer * pointer
-	 */
-	WOV_EVENT_DATA_READY = 1,
-	WOV_EVENT_VAD,		  /* Voice activity detected */
-
-	WOV_EVENT_ERROR_FIRST = 128,
-	WOV_EVENT_ERROR_CORE_FIFO_OVERRUN = 128,
-	WOV_EVENT_ERROR_I2S_FIFO_UNDERRUN = 129,
-	WOV_EVENT_ERROR_I2S_FIFO_OVERRUN = 130,
-	WOV_EVENT_ERROR_LAST = 255,
-
-};
-
-/* WoV FIFO errors. */
-enum wov_fifo_errors {
-	WOV_FIFO_NO_ERROR = 0,
-	WOV_CORE_FIFO_OVERRUN = 1, /* 2 : I2S FIFO is underrun. */
-	WOV_I2S_FIFO_OVERRUN = 2,  /* 3 : I2S FIFO is overrun.  */
-	WOV_I2S_FIFO_UNDERRUN = 3  /* 4 : I2S FIFO is underrun. */
-
-};
-
-/* Selects I2S test mode. */
-enum wov_test_mode { WOV_NORMAL_MODE = 0, WOV_TEST_MODE };
-
-/* PULL_UP/PULL_DOWN selection. */
-enum wov_pull_upd_down_sel { WOV_PULL_DOWN = 0, WOV_PULL_UP };
-
-/* I2S output data floating mode. */
-enum wov_floating_mode { WOV_FLOATING_DRIVEN = 0, WOV_FLOATING };
-
-/* Clock inverted mode. */
-enum wov_clk_inverted_mode { WOV_CLK_NORMAL = 0, WOV_CLK_INVERTED };
-
-enum wov_i2s_chan_trigger {
-	WOV_I2S_SAMPLED_1_AFTER_0 = 0,
-	WOV_I2S_SAMPLED_0_AFTER_1 = 1
-};
-
-/* APM modes. */
-enum wov_modes {
-	WOV_MODE_OFF = 1,
-	WOV_MODE_VAD,
-	WOV_MODE_RAM,
-	WOV_MODE_I2S,
-	WOV_MODE_RAM_AND_I2S
-};
-
-/* DAI format. */
-enum wov_dai_format {
-	WOV_DAI_FMT_I2S,     /* I2S mode			*/
-	WOV_DAI_FMT_RIGHT_J, /* Right Justified mode		*/
-	WOV_DAI_FMT_LEFT_J,  /* Left Justified mode		*/
-	WOV_DAI_FMT_PCM_A,   /* PCM A Audio			*/
-	WOV_DAI_FMT_PCM_B,   /* PCM B Audio			*/
-	WOV_DAI_FMT_PCM_TDM  /* Time Division Multiplexing	*/
-};
-
-struct wov_config {
-	enum wov_modes mode;
-	uint32_t sample_per_sec;
-	int bit_depth;
-	enum wov_mic_source mic_src;
-	int left_chan_gain;
-	int right_chan_gain;
-	uint16_t i2s_start_delay_0;
-	uint16_t i2s_start_delay_1;
-	uint32_t i2s_clock;
-	enum wov_dai_format dai_format;
-	int sensitivity_db;
-};
-
-extern struct wov_config wov_conf;
-
-/**
- * Set FMUL2 clock divider.
- *
- * @param   None
- * @return  None
- */
-void wov_fmul2_set_clk_divider(enum fmul2_clk_divider clk_div);
-
-/**
- * WoV Call back function decleration.
- *
- * @param   event - the event that cause the call to the callback
- *		    function.
- *
- * @return  None
- */
-typedef void (*wov_call_back_t)(enum wov_events);
-
-/*
- * WoV macros.
- */
-
-/* MACROs that set fields of the Clock Control Register structure. */
-#define WOV_APM_CLK_SRC_FMUL2(reg_val) reg_val.clk_sel = 0
-#define WOV_APM_CLK_SRC_PLL(reg_val) reg_val.clk_sel = 1
-#define WOV_APM_GET_CLK_SRC(reg_val) (reg_val.clk_sel)
-
-/* Core FIFO threshold. */
-#define WOV_GET_CORE_FIFO_THRESHOLD WOV_GET_FIFO_INT_THRESHOLD
-
-/******************************************************************************
- *
- * WoV APIs
- *
- ******************************************************************************/
-
-/**
- * Initiates WoV.
- *
- * @param	callback	 - Pointer to callback function.
- *
- * @return	None
- */
-void wov_init(void);
-
-/**
- * Sets WoV stage
- *
- * @param	wov_mode - WoV stage (Table 38)
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_set_mode(enum wov_modes wov_mode);
-
-/**
- * Gets WoV mode
- *
- * @param	None
- * @return	WoV mode
- */
-enum wov_modes wov_get_mode(void);
-
-/**
- * Configure WoV.
- *
- * @param	samples_per_second - Valid sample rate.
- * @return	In case sample rate is valid return EC_SUCCESS othewise return
- * error code.
- */
-int wov_set_sample_rate(uint32_t samples_per_second);
-
-/**
- * Gets sampling rate.
- *
- * @param	None
- * @return	the current sampling rate.
- */
-uint32_t wov_get_sample_rate(void);
-
-/**
- * Sets sampling depth.
- *
- * @param	bits_num - Valid sample depth in bits.
- * @return	In case sample depth is valid return EC_SUCCESS othewise return
- * error code.
- */
-int wov_set_sample_depth(int bits_num);
-
-/**
- * Gets sampling depth.
- *
- * @param	None.
- * @return	sample depth in bits.
- */
-int wov_get_sample_depth(void);
-
-/**
- * Sets microphone source.
- *
- * @param	mic_src - Valid microphone source
- * @return	return EC_SUCCESS if mic source valid othewise
- * return error code.
- */
-int wov_set_mic_source(enum wov_mic_source mic_src);
-
-/**
- * Gets microphone source.
- *
- * @param	None.
- * @return	sample depth in bits.
- */
-enum wov_mic_source wov_get_mic_source(void);
-
-/**
- * Mutes the WoV.
- *
- * @param	enable	- enabled flag, true means enable
- * @return	None
- */
-void wov_mute(int enable);
-
-/**
- * Gets gain values
- *
- * @param   left_chan_gain  - address of left channel gain response.
- * @param   right_chan_gain - address of right channel gain response.
- * @return  None
- */
-void wov_get_gain(int *left_chan_gain, int *right_chan_gain);
-
-/**
- * Sets gain
- *
- * @param		left_chan_gain	- Left channel gain.
- * @param		right_chan_gain - Right channel gain
- * @return	None
- */
-void wov_set_gain(int left_chan_gain, int right_chan_gain);
-
-/**
- * Enables/Disables ADC.
- *
- * @param	enable - enabled flag, true means enable
- * @return	None
- */
-void wov_enable_agc(int enable);
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param stereo                - Stereo enabled flag, 1 means enable.
- * @param target                - Target output level of the ADC.
- * @param noise_gate_threshold  - Noise Gate system select. 1 means enable.
- * @param hold_time             - Hold time before starting AGC adjustment to
- *                                the TARGET value.
- * @param attack_time           - Attack time - gain ramp down.
- * @param decay_time            - Decay time - gain ramp up.
- * @param max_applied_gain      - Maximum Gain Value to apply to the ADC path.
- * @param min_applied_gain      - Minimum Gain Value to apply to the ADC path.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_set_agc_config(int stereo, float target,
-		int noise_gate_threshold, uint8_t hold_time,
-		uint16_t attack_time, uint16_t decay_time,
-		float max_applied_gain, float min_applied_gain);
-
-/**
- * Sets VAD sensitivity.
- *
- * @param	sensitivity_db - VAD sensitivity in db.
- * @return	None
- */
-int wov_set_vad_sensitivity(int sensitivity_db);
-
-/**
- * Gets VAD sensitivity.
- *
- * @param	None.
- * @return	VAD sensitivity in db
- */
-int wov_get_vad_sensitivity(void);
-
-/**
- * Configure I2S bus format. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   format    - one of the following: I2S mode, Right Justified mode,
- *                      Left Justified mode, PCM A Audio, PCM B Audio and
- *                      Time Division Multiplexing
- * @return  EC error code.
- */
-void wov_set_i2s_fmt(enum wov_dai_format format);
-
-/**
- * Configure I2S bus clock. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   i2s_clock - I2S clock frequency in Hz (needed in order to
- *                      configure the internal PLL for 12MHz)
- * @return  EC error code.
- */
-void wov_set_i2s_bclk(uint32_t i2s_clock);
-
-/**
- * Configure I2S bus. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   ch0_delay - 0 to 496.  Defines the delay from the SYNC till the
- *                      first bit (MSB) of channel 0 (left channel)
- * @param   ch1_delay - -1 to 496.  Defines the delay from the SYNC till the
- *                      first bit (MSB) of channel 1 (right channel).
- *                      If channel 1 is not used set this field to -1.
- *
- * @param   flags     -  WOV_TDM_ADJACENT_TO_CH0 = BIT(0).  There is a
- *                       channel adjacent to channel 0, so float SDAT when
- *                       driving the last bit (LSB) of the channel during the
- *                       second half of the clock cycle to avoid bus contention.
- *
- *                       WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel
- *                       adjacent to channel 1.
- *
- * @return  EC error code.
- */
-enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay,
-				uint32_t flags);
-
-/**
- * Configure FMUL2 clock tunning.
- *
- * @param   None
- * @return  None
- */
-void wov_fmul2_conf_tuning(void);
-
-/**
- * Configure DMIC clock.
- *
- * @param   enable          - DMIC enabled , true means enable
- * @param   clk_div         - DMIC clock division factor (disable, divide by 2
- *			      divide by 4)
- * @return  None
- */
-void wov_dmic_clk_config(int enable, enum wov_dmic_clk_div_sel clk_div);
-
-/**
- * FMUL2 clock control configuration.
- *
- * @param clk_src - select between FMUL2 (WOV_FMUL2_CLK_SRC) and
- *		    PLL (WOV_PLL_CLK_SRC)
- * @return	None
- */
-extern void wov_set_clk_selection(enum wov_clk_src_sel clk_src);
-
-/**
- * Configure PLL clock.
- *
- * @param   ext_div_sel         - PLL external divider selector.
- * @param   div_factor          - When ext_div_sel is WOV_PLL_EXT_DIV_BIN_CNT
- *                                then it is the 4 LSBits of this field,
- *                                otherwise this field is an index to
- *                                PLL External Divider Load Values table.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_pll_clk_ext_div_config(
-	enum wov_pll_ext_div_sel ext_div_sel, uint32_t div_factor);
-
-/**
- * PLL power down.
- *
- * @param enable - true power down the PLL or false PLL operating
- * @return	None
- */
-void wov_pll_enable(int enable);
-
-/**
- * Configures PLL clock dividers..
- *
- * @param   out_div_1    - PLL output divider #1, valid values 1-7
- * @param   out_div_2    - PLL output divider #2, valid values 1-7
- * @param   feedback_div - PLL feadback divider (Default is 375 decimal)
- * @param   in_div       - PLL input divider
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1,
-			uint32_t out_div_2,
-			uint32_t feedback_div,
-			uint32_t in_div);
-
-/**
- * Enables/Disables WoV interrupt.
- *
- * @param   int_index - Interrupt ID.
- * @param   enable    - enabled flag, 1 means enable
- *
- * @return  None.
- */
-void wov_interrupt_enable(enum wov_interrupt_index int_index, int enable);
-
-/**
- * Sets core FIFO threshold.
- *
- * @param   in_sel    - Core FIFO input select
- * @param   threshold - Core FIFO threshold
- *
- * @return  None
- */
-void wov_cfifo_config(enum wov_core_fifo_in_sel in_sel,
-			enum wov_fifo_threshold threshold);
-
-/**
- * Start the actual capturing of the Voice data to the RAM.
- * Note that the pointer to the RAM buffer must be precisely
- * set by calling wov_set_buffer();
- *
- * @param	None
- *
- * @return	None
- */
-void wov_start_ram_capture(void);
-
-/**
- * Stop the capturing of the Voice data to the RAM.
- *
- * @param	none
- *
- * @return  None
- */
-void wov_stop_ram_capture(void);
-
-/**
- * Rests the Core FIFO.
- *
- * @param	None
- *
- * @return	None
- */
-void wov_core_fifo_reset(void);
-
-/**
- * Rests the I2S FIFO.
- *
- * @param	None
- *
- * @return	None
- */
-void wov_i2s_fifo_reset(void);
-
-/**
- * Start the capturing of the Voice data via I2S.
- *
- * @param	None
- *
- * @return	None
- */
-void wov_start_i2s_capture(void);
-
-/**
- * Stop the capturing of the Voice data via I2S.
- *
- * @param	none
- *
- * @return  None
- */
-void wov_stop_i2s_capture(void);
-
-/**
- * Reads data from the core fifo.
- *
- * @param	num_elements - Number of elements (Dword) to read.
- *
- * @return	None
- */
-void wov_cfifo_read_handler(uint32_t num_elements);
-
-/**
- * Sets data buffer for reading from core FIFO
- *
- * @param  buff          - Pointer to the read buffer, buffer must be 32 bits
- *                         aligned.
- * @param  size_in_words - Size must be a multiple of CONFIG_WOV_THRESHOLD_WORDS
- *                         (defaulte = 80 words)
- *
- * @return  None
- *
- *  Note - When the data buffer will be full the FW will be notifyed
- *         about it, and the FW will need to recall to this function.
- */
-int wov_set_buffer(uint32_t *buff, int size_in_words);
-
-/**
- * Resets the APM.
- *
- * @param enable - enabled flag, true or false
- * @return	None
- */
-void wov_apm_active(int enable);
-
-void wov_handle_event(enum wov_events event);
-
-/**
- * I2S golobal configuration
- *
- * @param   i2s_hiz_data  - Defines when the I2S data output is floating.
- * @param   i2s_hiz       - Defines if the I2S data output is always floating.
- * @param   clk_invert    - Defines the I2S bit clock edge sensitivity
- * @param   out_pull_en   - Enable a pull-up or a pull-down resistor on
- *                          I2S output
- * @param   out_pull_mode - Select a pull-up or a pull-down resistor on
- *                          I2S output
- * @param   in_pull_en    - Enable a pull-up or a pull-down resistor on
- *                          I2S input
- * @param   in_pull_mode  - Select a pull-up or a pull-down resistor on
- *                          I2S intput
- * @param   test_mode     - Selects I2S test mode
- *
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_i2s_global_config(
-	enum wov_floating_mode i2s_hiz_data,
-	enum wov_floating_mode i2s_hiz,
-	enum wov_clk_inverted_mode clk_invert,
-	int out_pull_en, enum wov_pull_upd_down_sel out_pull_mode,
-	int in_pull_en,
-	enum wov_pull_upd_down_sel in_pull_mode,
-	enum wov_test_mode test_mode);
-
-/**
- * I2S channel configuration
- *
- * @param  channel_num     - I2S channel number, 0 or 1.
- * @param  bit_count       - I2S channel bit count.
- * @param  trigger         - Define the I2S chanel trigger 1->0 or 0->1
- * @param  start_delay     - Defines the delay from the trigger defined for
- *                           the channel till the first bit (MSB) of the data.
- *
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
-			uint32_t bit_count, enum wov_i2s_chan_trigger trigger,
-			int32_t start_delay);
-
-#endif /* __CROS_EC_WOV_CHIP_H */
diff --git a/chip/nrf51/bluetooth_le.c b/chip/nrf51/bluetooth_le.c
deleted file mode 100644
index 89eb117efd..0000000000
--- a/chip/nrf51/bluetooth_le.c
+++ /dev/null
@@ -1,537 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le.h"
-#include "include/bluetooth_le.h"
-#include "console.h"
-#include "ppi.h"
-#include "radio.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_BLUETOOTH_LE, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ## args)
-
-static void ble2nrf_packet(struct ble_pdu *ble_p,
-		struct nrf51_ble_packet_t *radio_p)
-{
-	if (ble_p->header_type_adv) {
-		radio_p->s0 = ble_p->header.adv.type & 0xf;
-		radio_p->s0 |= (ble_p->header.adv.txaddr ?
-			1 << BLE_ADV_HEADER_TXADD_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.adv.rxaddr ?
-			1 << BLE_ADV_HEADER_RXADD_SHIFT : 0);
-		radio_p->length = ble_p->header.adv.length & 0x3f; /* 6 bits */
-	} else {
-		radio_p->s0 = ble_p->header.data.llid & 0x3;
-		radio_p->s0 |= (ble_p->header.data.nesn ?
-			1 << BLE_DATA_HEADER_NESN_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.data.sn ?
-			1 << BLE_DATA_HEADER_SN_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.data.md ?
-			1 << BLE_DATA_HEADER_MD_SHIFT : 0);
-		radio_p->length = ble_p->header.data.length & 0x1f; /* 5 bits */
-	}
-
-	if (radio_p->length > 0)
-		memcpy(radio_p->payload, ble_p->payload, radio_p->length);
-}
-
-static void nrf2ble_packet(struct ble_pdu *ble_p,
-		struct nrf51_ble_packet_t *radio_p, int type_adv)
-{
-	if (type_adv) {
-		ble_p->header_type_adv = 1;
-		ble_p->header.adv.type = radio_p->s0 & 0xf;
-		ble_p->header.adv.txaddr = (radio_p->s0 &
-			BIT(BLE_ADV_HEADER_TXADD_SHIFT)) != 0;
-		ble_p->header.adv.rxaddr = (radio_p->s0 &
-			BIT(BLE_ADV_HEADER_RXADD_SHIFT)) != 0;
-		/* Length check? 6-37 Bytes */
-		ble_p->header.adv.length = radio_p->length;
-	} else {
-		ble_p->header_type_adv = 0;
-		ble_p->header.data.llid = radio_p->s0 & 0x3;
-		ble_p->header.data.nesn = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_NESN_SHIFT)) != 0;
-		ble_p->header.data.sn = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_SN_SHIFT)) != 0;
-		ble_p->header.data.md = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_MD_SHIFT)) != 0;
-		/* Length check? 0-31 Bytes */
-		ble_p->header.data.length = radio_p->length;
-	}
-
-	if (radio_p->length > 0)
-		memcpy(ble_p->payload, radio_p->payload, radio_p->length);
-}
-
-struct ble_pdu adv_packet;
-struct nrf51_ble_packet_t on_air_packet;
-
-struct ble_pdu rcv_packet;
-
-int ble_radio_init(uint32_t access_address, uint32_t crc_init_val)
-{
-	int rv = radio_init(BLE_1MBIT);
-
-	if (rv)
-		return rv;
-	NRF51_RADIO_CRCCNF = 3 | NRF51_RADIO_CRCCNF_SKIP_ADDR; /* 3-byte CRC */
-	/* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */
-	/* 0x1_0000_0000_0000_0110_0101_1011 */
-	NRF51_RADIO_CRCPOLY = 0x100065B;
-
-	NRF51_RADIO_CRCINIT = crc_init_val;
-
-	NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM;
-
-	NRF51_RADIO_BASE0 = access_address << 8;
-	NRF51_RADIO_PREFIX0 = access_address >> 24;
-
-	if (access_address != BLE_ADV_ACCESS_ADDRESS)
-		CPRINTF("Initializing radio for data packet.\n");
-
-	NRF51_RADIO_TXADDRESS = 0;
-	NRF51_RADIO_RXADDRESSES = 1;
-	NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_ADV_DATA;
-	NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_ADV_DATA;
-
-	return rv;
-
-}
-
-static struct nrf51_ble_packet_t tx_packet;
-
-static uint32_t tx_end, rsp_end;
-
-void ble_tx(struct ble_pdu *pdu)
-{
-	uint32_t timeout_time;
-
-	ble2nrf_packet(pdu, &tx_packet);
-
-	NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet;
-	NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0;
-	NRF51_RADIO_RXEN = 0;
-	NRF51_RADIO_TXEN = 1;
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_READY) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("ERROR DURING RADIO TX SETUP. TRY AGAIN.\n");
-			return;
-		}
-	}
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_END) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("RADIO DID NOT SHUT DOWN AFTER TX. "
-				"RECOMMEND REBOOT.\n");
-			return;
-		}
-	}
-	NRF51_RADIO_DISABLE = 1;
-}
-
-static struct nrf51_ble_packet_t rx_packet;
-int ble_rx(struct ble_pdu *pdu, int timeout, int adv)
-{
-	uint32_t done;
-	uint32_t timeout_time;
-	int ppi_channel_requested;
-
-	/* Prevent illegal wait times */
-	if (timeout <= 0) {
-		NRF51_RADIO_DISABLE = 1;
-		return EC_ERROR_TIMEOUT;
-	}
-
-	NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet;
-	NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0;
-	/*
-	 * These shortcuts cause packet transmission 150 microseconds after
-	 * packet receive, as is the BTLE standard. See NRF51 manual:
-	 * section 17.1.12
-	 */
-	NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START |
-			NRF51_RADIO_SHORTS_DISABLED_TXEN |
-			NRF51_RADIO_SHORTS_END_DISABLE;
-
-	/*
-	 * This creates a shortcut that marks the time
-	 * that the payload was received by the radio
-	 * in NRF51_TIMER_CC(0,1)
-	 */
-	ppi_channel_requested = NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1;
-	if (ppi_request_channel(&ppi_channel_requested) == EC_SUCCESS) {
-		NRF51_PPI_CHEN |= BIT(ppi_channel_requested);
-		NRF51_PPI_CHENSET |= BIT(ppi_channel_requested);
-	}
-
-
-	NRF51_RADIO_RXEN = 1;
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_READY) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("RADIO NOT SET UP IN TIME. TIMING OUT.\n");
-			return EC_ERROR_TIMEOUT;
-		}
-	}
-
-	timeout_time = get_time().val + timeout;
-	do {
-		if (get_time().val >= timeout_time) {
-			NRF51_RADIO_DISABLE = 1;
-			return EC_ERROR_TIMEOUT;
-		}
-		done = NRF51_RADIO_END;
-	} while (!done);
-
-	rsp_end = get_time().le.lo;
-
-	if (NRF51_RADIO_CRCSTATUS == 0) {
-		CPRINTF("INVALID CRC\n");
-		return EC_ERROR_CRC;
-	}
-
-	nrf2ble_packet(pdu, &rx_packet, adv);
-
-	/*
-	 * Throw error if radio not yet disabled. Something has
-	 * gone wrong. May be in an unexpected state.
-	 */
-	if (NRF51_RADIO_DISABLED != 1)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/* Allow list handling */
-int ble_radio_clear_allow_list(void)
-{
-	NRF51_RADIO_DACNF = 0;
-	return EC_SUCCESS;
-}
-
-int ble_radio_read_allow_list_size(uint8_t *ret_size)
-{
-	int i, size = 0;
-	uint32_t dacnf = NRF51_RADIO_DACNF;
-
-	/* Count the bits that are set */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++)
-		if (dacnf & NRF51_RADIO_DACNF_ENA(i))
-			size++;
-
-	*ret_size = size;
-
-	return EC_SUCCESS;
-}
-
-int ble_radio_add_device_to_allow_list(const uint8_t *addr_ptr, uint8_t rand)
-{
-	uint32_t dacnf = NRF51_RADIO_DACNF;
-	int i;
-	uint32_t aligned;
-
-	/* Check for duplicates using ble_radio_remove_device? */
-
-	/* Find a free entry */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX &&
-		(dacnf & NRF51_RADIO_DACNF_ENA(i)); i++)
-		;
-
-	if (i == NRF51_RADIO_DACNF_MAX)
-		return EC_ERROR_OVERFLOW;
-
-	memcpy(&aligned, addr_ptr, 4);
-	NRF51_RADIO_DAB(i) = aligned;
-	memcpy(&aligned, addr_ptr + 4, 2);
-	NRF51_RADIO_DAP(i) = aligned;
-
-	NRF51_RADIO_DACNF = dacnf | NRF51_RADIO_DACNF_ENA(i) |
-		(rand ? NRF51_RADIO_DACNF_TXADD(i) : 0);
-
-	return EC_SUCCESS;
-}
-
-int ble_radio_remove_device_from_allow_list(const uint8_t *addr_ptr,
-					    uint8_t rand)
-{
-	int i, dacnf = NRF51_RADIO_DACNF;
-
-	/* Find a matching entry */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++) {
-		uint32_t dab = NRF51_RADIO_DAB(i), dap = NRF51_RADIO_DAP(i);
-
-		if ((dacnf & NRF51_RADIO_DACNF_ENA(i)) && /* Enabled */
-		    /* Rand flag matches */
-		    (rand == ((dacnf & NRF51_RADIO_DACNF_TXADD(i)) != 0)) &&
-		    /* Address matches */
-		    (!memcmp(addr_ptr, &dab, 4)) &&
-		    (!memcmp(addr_ptr + 4, &dap, 2)))
-			break;
-	}
-
-	if (i == NRF51_RADIO_DACNF_MAX) /* Not found is successfully removed */
-		return EC_SUCCESS;
-
-	NRF51_RADIO_DACNF = dacnf & ~((NRF51_RADIO_DACNF_ENA(i)) |
-		(rand ? NRF51_RADIO_DACNF_TXADD(i) : 0));
-
-	return EC_SUCCESS;
-}
-
-
-int ble_adv_packet(struct ble_pdu *adv_packet, int chan)
-{
-	int done;
-	int rv;
-
-	/* Change channel */
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan));
-	NRF51_RADIO_DATAWHITEIV = chan;
-
-	ble_tx(adv_packet);
-
-	do {
-		done = NRF51_RADIO_END;
-	} while (!done);
-
-	tx_end = get_time().le.lo;
-
-	if (adv_packet->header.adv.type ==
-	    BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND)
-		return EC_SUCCESS;
-
-	rv = ble_rx(&rcv_packet, 16000, 1);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Check for valid responses */
-	switch (rcv_packet.header.adv.type) {
-	case BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ:
-		/* Scan requests are only allowed for ADV_IND and SCAN_IND */
-		if (adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		    adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND)
-			return rv;
-		/* The advertising address needs to match */
-		if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-		    &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-	break;
-	case BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ:
-		/* Connections are only allowed for two types of advertising */
-		if (adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		    adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
-			return rv;
-		/* The advertising address needs to match */
-		if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-		    &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-		/* The InitAddr needs to match for Directed advertising */
-		if (adv_packet->header.adv.type ==
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND &&
-		    memcmp(&adv_packet->payload[BLUETOOTH_ADDR_OCTETS],
-			   &rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-	break;
-	default: /* Unhandled response packet */
-		return rv;
-	break;
-	}
-
-	dump_ble_packet(&rcv_packet);
-	CPRINTF("tx_end %u Response %u\n", tx_end, rsp_end);
-
-	return rv;
-}
-
-int ble_adv_event(struct ble_pdu *adv_packet)
-{
-	int chan;
-	int rv;
-
-	for (chan = 37; chan < 40; chan++) {
-		rv = ble_adv_packet(adv_packet, chan);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	return rv;
-}
-
-static void fill_header(struct ble_pdu *adv, int type, int txaddr, int rxaddr)
-{
-	adv->header_type_adv = 1;
-	adv->header.adv.type = type;
-	adv->header.adv.txaddr = txaddr ?
-		BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR;
-	adv->header.adv.rxaddr = rxaddr ?
-		BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR;
-	adv->header.adv.length = 0;
-}
-
-static int fill_payload(uint8_t *payload, uint64_t addr, int name_length)
-{
-	uint8_t *curr;
-
-	curr = pack_adv_addr(payload, addr);
-	curr = pack_adv(curr, name_length, GAP_COMPLETE_NAME,
-		"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrs");
-	curr = pack_adv_int(curr, 2, GAP_APPEARANCE,
-			    GAP_APPEARANCE_HID_KEYBOARD);
-	curr = pack_adv_int(curr, 1, GAP_FLAGS,
-		GAP_FLAGS_LE_LIM_DISC | GAP_FLAGS_LE_NO_BR_EDR);
-	curr = pack_adv_int(curr, 2, GAP_COMP_16_BIT_UUID,
-			    GATT_SERVICE_HID_UUID);
-
-	return curr - payload;
-}
-
-static void fill_packet(struct ble_pdu *adv, uint64_t addr, int type,
-			int name_length)
-{
-	fill_header(adv, type, BLE_ADV_HEADER_RANDOM_ADDR,
-		    BLE_ADV_HEADER_PUBLIC_ADDR);
-
-	adv->header.adv.length = fill_payload(adv->payload, addr, name_length);
-}
-
-static int command_ble_adv(int argc, char **argv)
-{
-	int type, length, reps, interval;
-	uint64_t addr;
-	char *e;
-	int i;
-	int rv;
-
-	if (argc < 3 || argc > 5)
-		return EC_ERROR_PARAM_COUNT;
-
-	type = strtoi(argv[1], &e, 0);
-	if (*e || type < 0 || (type > 2 && type != 6))
-		return EC_ERROR_PARAM1;
-
-	length = strtoi(argv[2], &e, 0);
-	if (*e || length > 32)
-		return EC_ERROR_PARAM2;
-
-	if (argc >= 4) {
-		reps = strtoi(argv[3], &e, 0);
-		if (*e || reps < 0)
-			return EC_ERROR_PARAM3;
-	} else {
-		reps = 1;
-	}
-
-	if (argc >= 5) {
-		interval = strtoi(argv[4], &e, 0);
-		if (*e || interval < 0)
-			return EC_ERROR_PARAM4;
-	} else {
-		interval = 100000;
-	}
-
-	if (type == BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND && length != 12) {
-		length = 12;
-		CPRINTS("type DIRECT needs to have a length of 12");
-	}
-
-	rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-
-
-		CPRINTS("ADV @%pP", &adv_packet);
-
-	((uint32_t *)&addr)[0] = 0xA3A2A1A0 | type;
-	((uint32_t *)&addr)[1] = BLE_RANDOM_ADDR_MSBS_STATIC << 8 | 0x5A4;
-
-		fill_packet(&adv_packet, addr, type, length);
-
-	for (i = 0; i < reps; i++) {
-		ble_adv_event(&adv_packet);
-		usleep(interval);
-	}
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(ble_adv, command_ble_adv,
-			"type len [reps] [interval = 100000 (100ms)]",
-			"Send a BLE packet of type type of length len");
-
-static int command_ble_adv_scan(int argc, char **argv)
-{
-	int chan, packets, i;
-	int addr_lsbyte;
-	char *e;
-	int rv;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	chan = strtoi(argv[1], &e, 0);
-	if (*e || chan < 37 || chan > 39)
-		return EC_ERROR_PARAM1;
-
-	chan = strtoi(argv[1], &e, 0);
-	if (*e || chan < 37 || chan > 39)
-		return EC_ERROR_PARAM1;
-
-	if (argc >= 3) {
-		packets = strtoi(argv[2], &e, 0);
-		if (*e || packets < 0)
-			return EC_ERROR_PARAM2;
-	} else {
-		packets = 1;
-	}
-
-	if (argc >= 4) {
-		addr_lsbyte = strtoi(argv[3], &e, 0);
-		if (*e || addr_lsbyte > 255)
-			return EC_ERROR_PARAM3;
-	} else {
-		addr_lsbyte = -1;
-	}
-
-	rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-
-	/* Change channel */
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan));
-	NRF51_RADIO_DATAWHITEIV = chan;
-
-	CPRINTS("ADV Listen");
-	if (addr_lsbyte != -1)
-		CPRINTS("filtered (%x)", addr_lsbyte);
-
-	for (i = 0; i < packets; i++) {
-		rv = ble_rx(&rcv_packet, 1000000, 1);
-
-		if (rv == EC_ERROR_TIMEOUT)
-			continue;
-
-		if (addr_lsbyte == -1 || rcv_packet.payload[0] == addr_lsbyte)
-			dump_ble_packet(&rcv_packet);
-	}
-
-	rv = radio_disable();
-
-	CPRINTS("on_air payload rcvd %pP", &rx_packet);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(ble_scan, command_ble_adv_scan,
-			"chan [num] [addr0]",
-			"Scan for [num] BLE packets on channel chan");
-
diff --git a/chip/nrf51/bluetooth_le.h b/chip/nrf51/bluetooth_le.h
deleted file mode 100644
index dbb3bccd6e..0000000000
--- a/chip/nrf51/bluetooth_le.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __NRF51_BLUETOOTH_LE_H
-#define __NRF51_BLUETOOTH_LE_H
-
-#include "common.h"
-#include "include/bluetooth_le.h"
-
-#define NRF51_BLE_LENGTH_BITS 8
-#define NRF51_BLE_S0_BYTES    1
-#define NRF51_BLE_S1_BITS     0 /* no s1 field */
-
-#define BLE_ACCESS_ADDRESS_BYTES 4
-#define EXTRA_RECEIVE_BYTES      0
-#define BLE_ADV_WHITEN           1
-
-#define RADIO_SETUP_TIMEOUT 1000
-
-/* Data and Advertisements have the same PCNF values */
-#define NRF51_RADIO_PCNF0_ADV_DATA \
-			NRF51_RADIO_PCNF0_VAL(NRF51_BLE_LENGTH_BITS, \
-			NRF51_BLE_S0_BYTES, \
-			NRF51_BLE_S1_BITS)
-
-#define NRF51_RADIO_PCNF1_ADV_DATA \
-			NRF51_RADIO_PCNF1_VAL(BLE_MAX_ADV_PAYLOAD_OCTETS, \
-		    EXTRA_RECEIVE_BYTES, \
-		    BLE_ACCESS_ADDRESS_BYTES - 1, \
-		    BLE_ADV_WHITEN)
-
-struct nrf51_ble_packet_t {
-	uint8_t s0; /* First byte */
-	uint8_t length; /* Length field */
-	uint8_t payload[BLE_MAX_DATA_PAYLOAD_OCTETS];
-} __packed;
-
-struct nrf51_ble_config_t {
-	uint8_t channel;
-	uint8_t address;
-	uint32_t crc_init;
-};
-
-/* Initialize the nRF51 radio for BLE */
-int ble_radio_init(uint32_t access_address, uint32_t crc_init_val);
-
-/* Transmit pdu on the radio */
-void ble_tx(struct ble_pdu *pdu);
-
-/* Receive a packet into pdu if one comes before the timeout */
-int ble_rx(struct ble_pdu *pdu, int timeout, int adv);
-
-/* Allow list handling */
-
-/* Clear the allow list */
-int ble_radio_clear_allow_list(void);
-
-/* Read the size of the allow list and assign it to ret_size */
-int ble_radio_read_allow_list_size(uint8_t *ret_size);
-
-/* Add the device with the address specified by addr_ptr and type */
-int ble_radio_add_device_to_allow_list(const uint8_t *addr_ptr, uint8_t type);
-
-/* Remove the device with the address specified by addr_ptr and type */
-int ble_radio_remove_device_from_allow_list(const uint8_t *addr_ptr,
-					    uint8_t type);
-
-#endif  /* __NRF51_BLUETOOTH_LE_H */
diff --git a/chip/nrf51/build.mk b/chip/nrf51/build.mk
deleted file mode 100644
index 7a7a33d402..0000000000
--- a/chip/nrf51/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# nRF51822 chip specific files build
-#
-
-CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
-
-chip-y+=gpio.o system.o uart.o
-chip-y+=watchdog.o ppi.o
-
-chip-$(CONFIG_BLUETOOTH_LE)+=radio.o bluetooth_le.o
-chip-$(CONFIG_BLUETOOTH_LE_RADIO_TEST)+=radio_test.o
-chip-$(CONFIG_COMMON_TIMER)+=hwtimer.o clock.o
-chip-$(CONFIG_I2C)+=i2c.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
diff --git a/chip/nrf51/clock.c b/chip/nrf51/clock.c
deleted file mode 100644
index fe56140175..0000000000
--- a/chip/nrf51/clock.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-void clock_init(void)
-{
-}
-
-int clock_get_freq(void)
-{
-	/* constant 16 MHz clock */
-	return 16000000;
-}
diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h
deleted file mode 100644
index f63fff0fe3..0000000000
--- a/chip/nrf51/config_chip.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/cortex-m0/config_core.h"
-
-/* System stack size */
-#define CONFIG_STACK_SIZE 1024
-
-/* Idle task stack size */
-#define IDLE_TASK_STACK_SIZE 256
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-/* Larger task stack size, for hook task */
-#define LARGER_TASK_STACK_SIZE 640
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 2
-
-/*
- * --- chip variant settings ---
- */
-
-/* RAM mapping */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
-
-/* Flash mapping */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Not that much RAM, set to smaller */
-#undef  CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 1024
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
-
diff --git a/chip/nrf51/gpio.c b/chip/nrf51/gpio.c
deleted file mode 100644
index 53694b5a74..0000000000
--- a/chip/nrf51/gpio.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * For each interrupt (INT0-INT3, PORT), record which GPIO entry uses it.
- */
-
-static const struct gpio_info *gpio_ints[NRF51_GPIOTE_IN_COUNT];
-static const struct gpio_info *gpio_int_port;
-
-volatile uint32_t * const nrf51_alt_funcs[] = {
-	/* UART */
-	&NRF51_UART_PSELRTS,
-	&NRF51_UART_PSELTXD,
-	&NRF51_UART_PSELCTS,
-	&NRF51_UART_PSELRXD,
-	/* SPI1 (SPI Master) */
-	&NRF51_SPI0_PSELSCK,
-	&NRF51_SPI0_PSELMOSI,
-	&NRF51_SPI0_PSELMISO,
-	/* TWI0 (I2C) */
-	&NRF51_TWI0_PSELSCL,
-	&NRF51_TWI0_PSELSDA,
-	/* SPI1 (SPI Master) */
-	&NRF51_SPI1_PSELSCK,
-	&NRF51_SPI1_PSELMOSI,
-	&NRF51_SPI1_PSELMISO,
-	/* TWI1 (I2C) */
-	&NRF51_TWI1_PSELSCL,
-	&NRF51_TWI1_PSELSDA,
-	/* SPIS1 (SPI SLAVE) */
-	&NRF51_SPIS1_PSELSCK,
-	&NRF51_SPIS1_PSELMISO,
-	&NRF51_SPIS1_PSELMOSI,
-	&NRF51_SPIS1_PSELCSN,
-	/* QDEC (ROTARY DECODER) */
-	&NRF51_QDEC_PSELLED,
-	&NRF51_QDEC_PSELA,
-	&NRF51_QDEC_PSELB,
-	/* LPCOMP (Low Power Comparator) */
-	&NRF51_LPCOMP_PSEL,
-};
-
-const unsigned int nrf51_alt_func_count = ARRAY_SIZE(nrf51_alt_funcs);
-
-/* Make sure the function table and defines stay in sync */
-BUILD_ASSERT(ARRAY_SIZE(nrf51_alt_funcs) == NRF51_MAX_ALT_FUNCS &&
-	NRF51_MAX_ALT_FUNCS <= GPIO_ALT_FUNC_MAX);
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	uint32_t val = 0;
-	uint32_t bit = GPIO_MASK_TO_NUM(mask);
-
-	if (flags & GPIO_OUTPUT)
-		val |= NRF51_PIN_CNF_DIR_OUTPUT;
-	else if (flags & GPIO_INPUT)
-		val |= NRF51_PIN_CNF_DIR_INPUT;
-
-	if (flags & GPIO_PULL_DOWN)
-		val |= NRF51_PIN_CNF_PULLDOWN;
-	else if (flags & GPIO_PULL_UP)
-		val |= NRF51_PIN_CNF_PULLUP;
-
-	/* TODO: Drive strength? H0D1? */
-	if (flags & GPIO_OPEN_DRAIN)
-		val |= NRF51_PIN_CNF_DRIVE_S0D1;
-
-	if (flags & GPIO_OUTPUT) {
-		if (flags & GPIO_HIGH)
-			NRF51_GPIO0_OUTSET = mask;
-		else if (flags & GPIO_LOW)
-			NRF51_GPIO0_OUTCLR = mask;
-	}
-
-	/* Interrupt levels */
-	if (flags & GPIO_INT_SHARED) {
-		/*
-		 * There are no shared edge-triggered interrupts;
-		 * they're either high or low.
-		 */
-		ASSERT((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) == 0);
-		ASSERT((flags & GPIO_INT_LEVEL) != GPIO_INT_LEVEL);
-		if (flags & GPIO_INT_F_LOW)
-			val |= NRF51_PIN_CNF_SENSE_LOW;
-		else if (flags & GPIO_INT_F_HIGH)
-			val |= NRF51_PIN_CNF_SENSE_HIGH;
-	}
-
-	NRF51_PIN_CNF(bit) = val;
-}
-
-
-static void gpio_init(void)
-{
-	task_enable_irq(NRF51_PERID_GPIOTE);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return !!(NRF51_GPIO0_IN & gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	if (value)
-		NRF51_GPIO0_OUTSET = gpio_list[signal].mask;
-	else
-		NRF51_GPIO0_OUTCLR = gpio_list[signal].mask;
-}
-
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int is_warm = 0;
-	int i;
-
-	if (NRF51_POWER_RESETREAS &
-			(NRF51_POWER_RESETREAS_OFF | /* GPIO Wake */
-			 NRF51_POWER_RESETREAS_LPCOMP)) {
-		/* This is a warm reboot */
-		is_warm = 1;
-	}
-
-	/* Initialize Interrupt configuration */
-	for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++)
-		gpio_ints[i] = NULL;
-	gpio_int_port = NULL;
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels again.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-/*
- * NRF51 doesn't have an alternate function table.
- * Use the pin select registers in place of the function number.
- */
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	uint32_t bit = GPIO_MASK_TO_NUM(mask);
-
-	ASSERT((~mask & BIT(bit)) == 0); /* Only one bit set. */
-	ASSERT(port == GPIO_0);
-	ASSERT((func >= GPIO_ALT_FUNC_DEFAULT && func < nrf51_alt_func_count) ||
-		func == GPIO_ALT_FUNC_NONE);
-
-	/* Remove the previous setting(s) */
-	if (func == GPIO_ALT_FUNC_NONE) {
-		int i;
-		for (i = 0; i < nrf51_alt_func_count; i++) {
-			if (*(nrf51_alt_funcs[i]) == bit)
-				*(nrf51_alt_funcs[i]) = 0xffffffff;
-		}
-	} else {
-		*(nrf51_alt_funcs[func]) = bit;
-	}
-}
-
-
-/*
- *  Enable the interrupt associated with the "signal"
- *  The architecture has one general (PORT)
- *  and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
- *
- */
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int pin;
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* If it's not shared, use INT0-INT3, otherwise use PORT. */
-	if (!(g->flags & GPIO_INT_SHARED)) {
-		int int_num, free_slot = -1;
-		uint32_t event_config = 0;
-
-		for (int_num = 0; int_num < NRF51_GPIOTE_IN_COUNT; int_num++) {
-			if (gpio_ints[int_num] == g)
-				return EC_SUCCESS; /* This is already set up. */
-
-			if (gpio_ints[int_num] == NULL && free_slot == -1)
-				free_slot = int_num;
-		}
-
-		ASSERT(free_slot != -1);
-
-		gpio_ints[free_slot] = g;
-		pin = GPIO_MASK_TO_NUM(g->mask);
-		event_config = (pin << NRF51_GPIOTE_PSEL_POS) |
-			NRF51_GPIOTE_MODE_EVENT;
-
-		ASSERT(g->flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING));
-
-		/* RISING | FALLING = TOGGLE */
-		if (g->flags & GPIO_INT_F_RISING)
-			event_config |= NRF51_GPIOTE_POLARITY_LOTOHI;
-		if (g->flags & GPIO_INT_F_FALLING)
-			event_config |= NRF51_GPIOTE_POLARITY_HITOLO;
-
-		NRF51_GPIOTE_CONFIG(free_slot) = event_config;
-
-		/* Enable the IN[] interrupt. */
-		NRF51_GPIOTE_INTENSET = 1 << free_slot;
-
-	} else {
-		/* The first handler for the shared interrupt wins. */
-		if (gpio_int_port == NULL) {
-			gpio_int_port = g;
-
-			/* Enable the PORT interrupt. */
-			NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- *  Disable the interrupt associated with the "signal"
- *  The architecture has one general (PORT)
- *  and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
- */
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	int i;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* If it's not shared, use INT0-INT3, otherwise use PORT. */
-	if (!(g->flags & GPIO_INT_SHARED)) {
-		for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
-			/* Remove matching handler. */
-			if (gpio_ints[i] == g) {
-				/* Disable the interrupt */
-				NRF51_GPIOTE_INTENCLR =
-					1 << NRF51_GPIOTE_IN_BIT(i);
-				/* Zero the handler */
-				gpio_ints[i] = NULL;
-			}
-		}
-	} else {
-		/* Disable the interrupt */
-		NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT;
-		/* Zero the shared handler */
-		gpio_int_port = NULL;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Clear interrupt and run handler.
- */
-void gpio_interrupt(void)
-{
-	const struct gpio_info *g;
-	int i;
-	int signal;
-
-	for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
-		if (NRF51_GPIOTE_IN(i)) {
-			NRF51_GPIOTE_IN(i) = 0;
-			g = gpio_ints[i];
-			signal = g - gpio_list;
-			if (g && signal < GPIO_IH_COUNT)
-				gpio_irq_handlers[signal](signal);
-		}
-	}
-
-	if (NRF51_GPIOTE_PORT) {
-		NRF51_GPIOTE_PORT = 0;
-		g = gpio_int_port;
-		signal = g - gpio_list;
-		if (g && signal < GPIO_IH_COUNT)
-			gpio_irq_handlers[signal](signal);
-	}
-}
-DECLARE_IRQ(NRF51_PERID_GPIOTE, gpio_interrupt, 1);
diff --git a/chip/nrf51/hwtimer.c b/chip/nrf51/hwtimer.c
deleted file mode 100644
index 980a889657..0000000000
--- a/chip/nrf51/hwtimer.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Hardware timers driver.
- *
- * nRF51x has one fully functional hardware counter, but 4 stand-alone
- * capture/compare (CC) registers.
- */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/*
- * capture/compare (CC) registers:
- *   CC_INTERRUPT -- used to interrupt next clock event.
- *   CC_CURRENT -- used to capture the current value.
- *   CC_OVERFLOW -- used to detect overflow on virtual timer (not hardware).
- */
-
-#define CC_INTERRUPT  0
-#define CC_CURRENT    1
-#define CC_OVERFLOW   2
-
-/* The nRF51 has 3 timers, use HWTIMER to specify which one is used here. */
-#define HWTIMER       0
-
-static uint32_t last_deadline;  /* cache of event set */
-
-/*
- * The nRF51x timer cannot be set to a specified value (reset to zero only).
- * Thus, we have to use a variable "shift" to maintain the offset between the
- * hardware value and virtual clock value.
- *
- * Once __hw_clock_source_set(ts) is called, the shift will be like:
- *
- *   virtual time  ------------------------------------------------
- *                  <----------> ^
- *                      shift    | ts
- *               0 |             |
- *   hardware      v
- *   counter time  ------------------------------------------------
- *
- *
- * Below diagram shows what it is when overflow happens.
- *
- *                       | now                                | prev_read
- *                       v                                    v
- *   virtual time  ------------------------------------------------
- *                 ---->                                    <------
- *                 shift                                      shift
- *                                                         |
- *   hardware                                              v
- *   counter time  ------------------------------------------------
- *
- */
-static uint32_t shift;
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	last_deadline = deadline;
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = deadline - shift;
-
-	/* enable interrupt */
-	NRF51_TIMER_INTENSET(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* disable interrupt */
-	NRF51_TIMER_INTENCLR(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	/* to capture the current value */
-	NRF51_TIMER_CAPTURE(HWTIMER, CC_CURRENT) = 1;
-	return NRF51_TIMER_CC(HWTIMER, CC_CURRENT) + shift;
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	shift = ts;
-
-	/* reset counter to zero */
-	NRF51_TIMER_STOP(HWTIMER) = 1;
-	NRF51_TIMER_CLEAR(HWTIMER) = 1;
-
-	/* So that no interrupt until next __hw_clock_event_set() */
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = ts - 1;
-
-	/* Update the overflow point */
-	NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0 - shift;
-
-	/* Start the timer again */
-	NRF51_TIMER_START(HWTIMER) = 1;
-}
-
-
-/* Interrupt handler for timer */
-void timer_irq(void)
-{
-	int overflow = 0;
-
-	/* clear status */
-	NRF51_TIMER_COMPARE(HWTIMER, CC_INTERRUPT) = 0;
-
-	if (NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW)) {
-		NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW) = 0;
-		overflow = 1;
-	}
-
-	process_timers(overflow);
-}
-
-/* DECLARE_IRQ doesn't like the NRF51_PERID_TIMER(n) macro */
-BUILD_ASSERT(NRF51_PERID_TIMER(HWTIMER) == NRF51_PERID_TIMER0);
-DECLARE_IRQ(NRF51_PERID_TIMER0, timer_irq, 1);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-
-	/* Start the high freq crystal oscillator */
-	NRF51_CLOCK_HFCLKSTART = 1;
-	/* TODO: check if the crystal oscillator is running (HFCLKSTAT) */
-
-	/* 32-bit timer mode */
-	NRF51_TIMER_MODE(HWTIMER) = NRF51_TIMER_MODE_TIMER;
-	NRF51_TIMER_BITMODE(HWTIMER) = NRF51_TIMER_BITMODE_32;
-
-	/*
-	 * The external crystal oscillator is 16MHz (HFCLK).
-	 * Set the prescaler to 16 so that the timer counter is increasing
-	 * every micro-second (us).
-	 */
-	NRF51_TIMER_PRESCALER(HWTIMER) = 4;  /* actual value is 2**4 = 16 */
-
-	/* Not to trigger interrupt until __hw_clock_event_set() is called. */
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = 0xffffffff;
-
-	/* Set to 0 so that the next overflow can trigger timer_irq(). */
-	NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0;
-	NRF51_TIMER_INTENSET(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_OVERFLOW);
-
-	/* Clear the timer counter */
-	NRF51_TIMER_CLEAR(HWTIMER) = 1;
-
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
-	/* Enable interrupt */
-	task_enable_irq(NRF51_PERID_TIMER(HWTIMER));
-
-	/* Start the timer */
-	NRF51_TIMER_START(HWTIMER) = 1;
-
-	return NRF51_PERID_TIMER(HWTIMER);
-}
-
diff --git a/chip/nrf51/i2c.c b/chip/nrf51/i2c.c
deleted file mode 100644
index ff23152c89..0000000000
--- a/chip/nrf51/i2c.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ppi.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_TIMEOUT 20000
-
-/* Keep track of the PPI channel used for each port */
-static int i2c_ppi_chan[] = {-1, -1};
-
-static void i2c_init_port(unsigned int port);
-
-/* board-specific setup for post-I2C module init */
-void __board_i2c_post_init(int port)
-{
-}
-
-void board_i2c_post_init(int port)
-		__attribute__((weak, alias("__board_i2c_post_init")));
-
-static void i2c_init_port(unsigned int port)
-{
-	NRF51_TWI_RXDRDY(port) = 0;
-	NRF51_TWI_TXDSENT(port) = 0;
-
-	NRF51_TWI_PSELSCL(port) = NRF51_TWI_SCL_PIN(port);
-	NRF51_TWI_PSELSDA(port) = NRF51_TWI_SDA_PIN(port);
-	NRF51_TWI_FREQUENCY(port) = NRF51_TWI_FREQ(port);
-
-	NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port];
-
-	NRF51_PPI_EEP(i2c_ppi_chan[port]) = (uint32_t)&NRF51_TWI_BB(port);
-	NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-		(uint32_t)&NRF51_TWI_SUSPEND(port);
-
-	/* Master enable */
-	NRF51_TWI_ENABLE(port) = NRF51_TWI_ENABLE_VAL;
-
-	if (!(i2c_raw_get_scl(port) && (i2c_raw_get_sda(port))))
-		CPRINTF("port %d could be wedged\n", port);
-}
-
-void i2c_init(void)
-{
-	int i, rv;
-
-	gpio_config_module(MODULE_I2C, 1);
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		if (i2c_ppi_chan[i] == -1) {
-			rv = ppi_request_channel(&i2c_ppi_chan[i]);
-			ASSERT(rv == EC_SUCCESS);
-
-			i2c_init_port(i);
-		}
-	}
-}
-
-static void dump_i2c_reg(int port)
-{
-#ifdef CONFIG_I2C_DEBUG
-	CPRINTF("port      : %01d\n", port);
-	CPRINTF("Regs :\n");
-	CPRINTF(" 1: INTEN     : %08x\n", NRF51_TWI_INTEN(port));
-	CPRINTF(" 2: ERRORSRC  : %08x\n", NRF51_TWI_ERRORSRC(port));
-	CPRINTF(" 3: ENABLE    : %08x\n", NRF51_TWI_ENABLE(port));
-	CPRINTF(" 4: PSELSCL   : %08x\n", NRF51_TWI_PSELSCL(port));
-	CPRINTF(" 5: PSELSDA   : %08x\n", NRF51_TWI_PSELSDA(port));
-	CPRINTF(" 6: RXD       : %08x\n", NRF51_TWI_RXD(port));
-	CPRINTF(" 7: TXD       : %08x\n", NRF51_TWI_TXD(port));
-	CPRINTF(" 8: FREQUENCY : %08x\n", NRF51_TWI_FREQUENCY(port));
-	CPRINTF(" 9: ADDRESS   : %08x\n", NRF51_TWI_ADDRESS(port));
-	CPRINTF("Events :\n");
-	CPRINTF(" STOPPED   : %08x\n", NRF51_TWI_STOPPED(port));
-	CPRINTF(" RXDRDY    : %08x\n", NRF51_TWI_RXDRDY(port));
-	CPRINTF(" TXDSENT   : %08x\n", NRF51_TWI_TXDSENT(port));
-	CPRINTF(" ERROR     : %08x\n", NRF51_TWI_ERROR(port));
-	CPRINTF(" BB        : %08x\n", NRF51_TWI_BB(port));
-#endif /* CONFIG_I2C_DEBUG */
-}
-
-static void i2c_recover(int port)
-{
-	/*
-	 * Recovery of the TWI peripheral:
-	 * To recover a TWI peripheral that has been locked up you must use
-	 * the following code.
-	 * After the recover function it is important to reconfigure all
-	 * relevant TWI registers explicitly to ensure that it operates
-	 * correctly.
-	 *    TWI0:
-	 *      NRF_TWI0->ENABLE =
-	 *         TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
-	 *      *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 0;
-	 *      nrf_delay_us(5);
-	 *      *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 1;
-	 *      NRF_TWI0->ENABLE =
-	 *         TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
-	 */
-	NRF51_TWI_ENABLE(port) = NRF51_TWI_DISABLE_VAL;
-	NRF51_TWI_POWER(port) = 0;
-	udelay(5);
-	NRF51_TWI_POWER(port) = 1;
-
-	i2c_init_port(port);
-}
-
-static void handle_i2c_error(int port, int rv)
-{
-	if (rv == EC_SUCCESS)
-		return;
-
-#ifdef CONFIG_I2C_DEBUG
-	if (rv != EC_ERROR_TIMEOUT)
-		CPRINTF("handle_i2c_error %d\n", rv);
-	else
-		CPRINTF("handle_i2c_error: Timeout\n");
-
-	dump_i2c_reg(port);
-#endif
-
-	/* This may be a little too heavy handed. */
-	i2c_recover(port);
-}
-
-static int i2c_master_write(const int port, const uint16_t slave_addr_flags,
-			    const uint8_t *data, int size, int stop)
-{
-	int bytes_sent;
-	int timeout = I2C_TIMEOUT;
-
-	NRF51_TWI_ADDRESS(port) = I2C_STRIP_FLAGS(slave_addr_flags);
-
-	/* Clear the sent bit */
-	NRF51_TWI_TXDSENT(port) = 0;
-
-	for (bytes_sent = 0; bytes_sent < size; bytes_sent++) {
-		/*Send a byte */
-		NRF51_TWI_TXD(port) = data[bytes_sent];
-
-		/* Only send a start for the first byte */
-		if (bytes_sent == 0)
-			NRF51_TWI_STARTTX(port) = 1;
-
-		/* Wait for ACK/NACK */
-		timeout = I2C_TIMEOUT;
-		while (timeout > 0 && NRF51_TWI_TXDSENT(port) == 0 &&
-				NRF51_TWI_ERROR(port) == 0)
-			timeout--;
-
-		if (timeout == 0)
-			return EC_ERROR_TIMEOUT;
-
-		if (NRF51_TWI_ERROR(port))
-			return EC_ERROR_UNKNOWN;
-
-		/* Clear the sent bit */
-		NRF51_TWI_TXDSENT(port) = 0;
-	}
-
-	if (stop) {
-		NRF51_TWI_STOPPED(port) = 0;
-		NRF51_TWI_STOP(port) = 1;
-		timeout = 10;
-		while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0)
-			timeout--;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int i2c_master_read(const int port, const uint16_t slave_addr_flags,
-			   uint8_t *data, int size)
-{
-	int curr_byte;
-	int timeout = I2C_TIMEOUT;
-
-	NRF51_TWI_ADDRESS(port) = I2C_STRIP_FLAGS(slave_addr_flags);
-
-	if (size == 1) /* Last byte: stop after this one. */
-		NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-			(uint32_t)&NRF51_TWI_STOP(port);
-	else
-		NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-			(uint32_t)&NRF51_TWI_SUSPEND(port);
-	NRF51_PPI_CHENSET = 1 << i2c_ppi_chan[port];
-
-	NRF51_TWI_RXDRDY(port) = 0;
-	NRF51_TWI_STARTRX(port) = 1;
-
-	for (curr_byte = 0; curr_byte < size; curr_byte++) {
-
-		/* Wait for data */
-		while (timeout > 0 && NRF51_TWI_RXDRDY(port) == 0 &&
-				NRF51_TWI_ERROR(port) == 0)
-			timeout--;
-
-		if (timeout == 0)
-			return EC_ERROR_TIMEOUT;
-
-		if (NRF51_TWI_ERROR(port))
-			return EC_ERROR_UNKNOWN;
-
-		data[curr_byte] = NRF51_TWI_RXD(port);
-		NRF51_TWI_RXDRDY(port) = 0;
-
-		/* Second to the last byte: stop next time. */
-		if (curr_byte == size-2)
-			NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-				(uint32_t)&NRF51_TWI_STOP(port);
-
-		/*
-		 * According to nRF51822-PAN v2.4 (Product Anomaly Notice),
-		 * the I2C locks up when RESUME is triggered too soon.
-		 * "the firmware should ensure that the time between receiving
-		 * the RXDRDY event and trigging the RESUME task is at least
-		 * two times the TWI clock period (i.e. 20 μs at 100 kbps).
-		 * Provided the TWI slave doesn’t do clock stretching during
-		 * the ACK bit, this will be enough to avoid the RESUME task
-		 * hit the end of the ACK bit. If this fails, a recovery of
-		 * the peripheral will be necessary, see i2c_recover.
-		 */
-		udelay(20);
-		NRF51_TWI_RESUME(port) = 1;
-	}
-
-	timeout = I2C_TIMEOUT;
-	while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0)
-		timeout--;
-
-	NRF51_TWI_STOP(port) = 0;
-
-	NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port];
-
-	return EC_SUCCESS;
-}
-
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int rv = EC_SUCCESS;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	if (out_bytes)
-		rv = i2c_master_write(port, slave_addr_flags,
-				      out, out_bytes,
-				      in_bytes ? 0 : 1);
-	if (rv == EC_SUCCESS && in_bytes)
-		rv = i2c_master_read(port, slave_addr_flags,
-				     in, in_bytes);
-
-	handle_i2c_error(port, rv);
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
diff --git a/chip/nrf51/keyboard_raw.c b/chip/nrf51/keyboard_raw.c
deleted file mode 100644
index 779c68454c..0000000000
--- a/chip/nrf51/keyboard_raw.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for nRF51
- *
- * To make this code portable, we rely heavily on looping over the keyboard
- * input and output entries in the board's gpio_list[]. Each set of inputs or
- * outputs must be listed in consecutive, increasing order so that scan loops
- * can iterate beginning at KB_IN00 or KB_OUT00 for however many GPIOs are
- * utilized (KEYBOARD_ROWS or KEYBOARD_COLS_MAX).
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/* Mask of output pins for driving. */
-static unsigned int col_mask;
-
-void keyboard_raw_init(void)
-{
-	int i;
-
-	/* Initialize col_mask */
-	col_mask = 0;
-	for (i = 0; i < keyboard_cols; i++)
-		col_mask |= gpio_list[GPIO_KB_OUT00 + i].mask;
-
-	/* Ensure interrupts are disabled */
-	keyboard_raw_enable_interrupt(0);
-}
-
-void keyboard_raw_task_start(void)
-{
-	/*
-	 * Enable the interrupt for keyboard matrix inputs.
-	 * One is enough, since they are shared.
-	 */
-	gpio_enable_interrupt(GPIO_KB_IN00);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	/* tri-state all first */
-	NRF51_GPIO0_OUTSET = col_mask;
-
-	/* drive low for specified pin(s) */
-	if (out == KEYBOARD_COLUMN_ALL)
-		NRF51_GPIO0_OUTCLR = col_mask;
-	else if (out != KEYBOARD_COLUMN_NONE)
-		NRF51_GPIO0_OUTCLR = gpio_list[GPIO_KB_OUT00 + out].mask;
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	int i;
-	int state = 0;
-
-	for (i = 0; i < KEYBOARD_ROWS; i++) {
-		if (NRF51_GPIO0_IN & gpio_list[GPIO_KB_IN00 + i].mask)
-			state |= 1 << i;
-	}
-
-	/* Invert it so 0=not pressed, 1=pressed */
-	return state ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/*
-		 * Clear the PORT event before enabling the interrupt.
-		 */
-		NRF51_GPIOTE_PORT = 0;
-		NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT;
-	} else {
-		NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT;
-	}
-}
-
-void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_KEYSCAN);
-}
diff --git a/chip/nrf51/ppi.c b/chip/nrf51/ppi.c
deleted file mode 100644
index 016cbf3008..0000000000
--- a/chip/nrf51/ppi.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ppi.h"
-#include "registers.h"
-#include "util.h"
-
-#define NRF51_PPI_FIRST_PP_CH NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN
-#define NRF51_PPI_LAST_PP_CH  NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START
-
-static uint32_t channels_in_use;
-static uint32_t channel_groups_in_use;
-
-int ppi_request_pre_programmed_channel(int ppi_chan)
-{
-	ASSERT(ppi_chan >= NRF51_PPI_FIRST_PP_CH &&
-		ppi_chan <= NRF51_PPI_LAST_PP_CH);
-
-	if (channels_in_use & BIT(ppi_chan))
-		return EC_ERROR_BUSY;
-
-	channels_in_use |= BIT(ppi_chan);
-
-	return EC_SUCCESS;
-}
-
-int ppi_request_channel(int *ppi_chan)
-{
-	int chan;
-
-	for (chan = 0; chan < NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS; chan++)
-		if ((channels_in_use & BIT(chan)) == 0)
-			break;
-
-	if (chan == NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS)
-		return EC_ERROR_BUSY;
-
-	channels_in_use |= BIT(chan);
-	*ppi_chan = chan;
-	return EC_SUCCESS;
-}
-
-void ppi_release_channel(int ppi_chan)
-{
-	channels_in_use &= ~BIT(ppi_chan);
-}
-
-void ppi_release_group(int ppi_group)
-{
-	channel_groups_in_use &= ~BIT(ppi_group);
-}
-
-int ppi_request_group(int *ppi_group)
-{
-	int group;
-
-	for (group = 0; group < NRF51_PPI_NUM_GROUPS; group++)
-		if ((channel_groups_in_use & BIT(group)) == 0)
-			break;
-
-	if (group == NRF51_PPI_NUM_GROUPS)
-		return EC_ERROR_BUSY;
-
-	channel_groups_in_use |= BIT(group);
-	*ppi_group = group;
-	return EC_SUCCESS;
-}
diff --git a/chip/nrf51/ppi.h b/chip/nrf51/ppi.h
deleted file mode 100644
index bbb74a2cf0..0000000000
--- a/chip/nrf51/ppi.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * PPI channels are a way to connect NRF51 EVENTs to TASKs without software
- * involvement. They are like SHORTs, except between peripherals.
- *
- * PPI groups are user-defined sets of channels that can be enabled and disabled
- * together.
- */
-
-/*
- * Reserve a pre-programmed PPI channel.
- *
- * Return EC_SUCCESS if ppi_chan is a pre-programmed channel that was not in
- * use, otherwise returns EC_ERROR_BUSY.
- */
-int ppi_request_pre_programmed_channel(int ppi_chan);
-
-/*
- * Reserve an available PPI channel.
- *
- * Return EC_SUCCESS and set the value of ppi_chan to an available PPI
- * channel.  If no channel is available, return EC_ERROR_BUSY.
- */
-int ppi_request_channel(int *ppi_chan);
-
-/* Release a PPI channel which was reserved with ppi_request_*_channel.  */
-void ppi_release_channel(int ppi_chan);
-
-/*
- * Reserve a PPI group.
- *
- * Return EC_SUCCESS and set the value of ppi_group to an available PPI
- * group.  If no group is available, return EC_ERROR_BUSY.
- */
-int ppi_request_group(int *ppi_group);
-
-/* Release a PPI channel which was reserved with ppi_request_*_channel.  */
-void ppi_release_group(int ppi_group);
diff --git a/chip/nrf51/radio.c b/chip/nrf51/radio.c
deleted file mode 100644
index af9d029a0d..0000000000
--- a/chip/nrf51/radio.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "radio.h"
-
-int radio_disable(void)
-{
-	int timeout = 10000;
-
-	NRF51_RADIO_DISABLED = 0;
-	NRF51_RADIO_DISABLE = 1;
-
-	while (!NRF51_RADIO_DISABLED && timeout > 0)
-		timeout--;
-
-	if (timeout == 0)
-		return EC_ERROR_TIMEOUT;
-
-	return EC_SUCCESS;
-}
-
-int radio_init(enum nrf51_radio_mode_t mode)
-{
-	int err_code = radio_disable();
-
-	if (mode == BLE_1MBIT) {
-		NRF51_RADIO_MODE = NRF51_RADIO_MODE_BLE_1MBIT;
-
-		NRF51_RADIO_TIFS = 150;	/* Bluetooth 4.1 Vol 6 pg 58 4.1 */
-
-		/*
-		 * BLE never sends or receives two packets in a row.
-		 * Enabling the radio means we want to transmit or receive.
-		 * After transmission, disable as quickly as possible.
-		 */
-		NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START |
-				NRF51_RADIO_SHORTS_END_DISABLE;
-
-		/* Use factory parameters if available */
-		if (!(NRF51_FICR_OVERRIDEEN & NRF51_FICR_OVERRIDEEN_BLE_BIT_N)
-		    ) {
-			int i;
-
-			for (i = 0; i < 4; i++) {
-				NRF51_RADIO_OVERRIDE(i) =
-					NRF51_FICR_BLE_1MBIT(i);
-			}
-			NRF51_RADIO_OVERRIDE(4) = NRF51_FICR_BLE_1MBIT(4) |
-				NRF51_RADIO_OVERRIDE_EN;
-		}
-	} else {
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	return err_code;
-}
-
diff --git a/chip/nrf51/radio.h b/chip/nrf51/radio.h
deleted file mode 100644
index 5b7e764fb9..0000000000
--- a/chip/nrf51/radio.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Radio interface for Chrome EC */
-
-#ifndef __NRF51_RADIO_H
-#define __NRF51_RADIO_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "registers.h"
-
-#ifndef NRF51_RADIO_MAX_PAYLOAD
-	#define NRF51_RADIO_MAX_PAYLOAD 253
-#endif
-
-#define RADIO_DONE (NRF51_RADIO_END == 1)
-
-enum nrf51_radio_mode_t {
-	BLE_1MBIT = NRF51_RADIO_MODE_BLE_1MBIT,
-};
-
-struct nrf51_radio_packet_t {
-	uint8_t s0; /* First byte */
-	uint8_t length; /* Length field */
-	uint8_t s1; /* Bits after length */
-	uint8_t payload[NRF51_RADIO_MAX_PAYLOAD];
-} __packed;
-
-int radio_init(enum nrf51_radio_mode_t mode);
-
-int radio_disable(void);
-
-#endif  /* __NRF51_RADIO_H */
diff --git a/chip/nrf51/radio_test.c b/chip/nrf51/radio_test.c
deleted file mode 100644
index 6c20874f4e..0000000000
--- a/chip/nrf51/radio_test.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le.h" /* chan2freq */
-#include "btle_hci_int.h"
-#include "console.h"
-#include "radio.h"
-#include "radio_test.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define BLE_TEST_TYPE_PRBS9   0
-#define BLE_TEST_TYPE_F0      1
-#define BLE_TEST_TYPE_AA      2
-#define BLE_TEST_TYPE_PRBS15  3
-#define BLE_TEST_TYPE_FF      4
-#define BLE_TEST_TYPE_00      5
-#define BLE_TEST_TYPE_0F      6
-#define BLE_TEST_TYPE_55      7
-
-#define BLE_TEST_TYPES_IMPLEMENTED 0xf6 /* No PRBS yet */
-
-static struct nrf51_ble_packet_t rx_packet;
-static struct nrf51_ble_packet_t tx_packet;
-static uint32_t rx_end;
-
-static int test_in_progress;
-
-void ble_test_stop(void)
-{
-	test_in_progress = 0;
-}
-
-static uint32_t prbs_lfsr;
-static uint32_t prbs_poly;
-
-/*
- * This is a Galois LFSR, the polynomial is the counterpart of the Fibonacci
- * LFSR in the doc.  It requires fewer XORs to implement in software.
- * This also means that the initial value is different.
- */
-static uint8_t prbs_next_byte(void)
-{
-	int i;
-	int lsb;
-	uint8_t rv = 0;
-
-	for (i = 0; i < 8; i++) {
-		lsb = prbs_lfsr & 1;
-		rv |= lsb << i;
-		prbs_lfsr = prbs_lfsr >> 1;
-		if (lsb)
-			prbs_lfsr ^= prbs_poly;
-	}
-	return rv;
-}
-
-void ble_test_fill_tx_packet(int type, int len)
-{
-	int i;
-
-	tx_packet.s0 = type & 0xf;
-	tx_packet.length = len;
-
-	switch (type) {
-	case BLE_TEST_TYPE_PRBS9:
-		prbs_lfsr = 0xf;
-		prbs_poly = 0x108;
-		for (i = 0; i < len; i++)
-			tx_packet.payload[i] = prbs_next_byte();
-		break;
-	case BLE_TEST_TYPE_PRBS15:
-		prbs_lfsr = 0xf;
-		prbs_poly = 0x6000;
-		for (i = 0; i < len; i++)
-			tx_packet.payload[i] = prbs_next_byte();
-		break;
-	case BLE_TEST_TYPE_F0:
-		memset(tx_packet.payload, 0xF0, len);
-		break;
-	case BLE_TEST_TYPE_AA:
-		memset(tx_packet.payload, 0xAA, len);
-		break;
-	case BLE_TEST_TYPE_FF:
-		memset(tx_packet.payload, 0xFF, len);
-		break;
-	case BLE_TEST_TYPE_00:
-		memset(tx_packet.payload, 0x00, len);
-		break;
-	case BLE_TEST_TYPE_0F:
-		memset(tx_packet.payload, 0x0F, len);
-		break;
-	case BLE_TEST_TYPE_55:
-		memset(tx_packet.payload, 0x55, len);
-		break;
-	default:
-		break;
-	}
-}
-
-static int ble_test_init(int chan)
-{
-	int rv = radio_init(BLE_1MBIT);
-
-	if (rv)
-		return HCI_ERR_Hardware_Failure;
-
-	if (chan > BLE_MAX_TEST_CHANNEL || chan < BLE_MIN_TEST_CHANNEL)
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	NRF51_RADIO_CRCCNF = 3 | BIT(8); /* 3-byte, skip address */
-	/* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */
-	/* 0x1_0000_0000_0000_0110_0101_1011 */
-	NRF51_RADIO_CRCPOLY = 0x100065B;
-	NRF51_RADIO_CRCINIT = 0x555555;
-
-	NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM;
-
-	/* The testing address is the inverse of the advertising address. */
-	NRF51_RADIO_BASE0 = (~BLE_ADV_ACCESS_ADDRESS) << 8;
-
-	NRF51_RADIO_PREFIX0 = (~BLE_ADV_ACCESS_ADDRESS) >> 24;
-
-	NRF51_RADIO_TXADDRESS = 0;
-	NRF51_RADIO_RXADDRESSES = 1;
-
-	NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_TEST;
-
-	NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_TEST;
-
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(2*chan + 2402);
-
-	test_in_progress = 1;
-	return rv;
-}
-
-int ble_test_rx_init(int chan)
-{
-	NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet;
-	return ble_test_init(chan);
-}
-
-int ble_test_tx_init(int chan, int len, int type)
-{
-	if ((BIT(type) & BLE_TEST_TYPES_IMPLEMENTED) == 0 ||
-			(len < 0 || len > BLE_MAX_TEST_PAYLOAD_OCTETS))
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	ble_test_fill_tx_packet(type, len);
-	NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet;
-
-	return ble_test_init(chan);
-}
-
-void ble_test_tx(void)
-{
-	NRF51_RADIO_END = 0;
-	NRF51_RADIO_TXEN = 1;
-}
-
-int ble_test_rx(void)
-{
-	int retries = 100;
-
-	NRF51_RADIO_END = 0;
-	NRF51_RADIO_RXEN = 1;
-
-	do {
-		retries--;
-		if (retries <= 0) {
-			radio_disable();
-			return EC_ERROR_TIMEOUT;
-		}
-		usleep(100);
-	} while (!NRF51_RADIO_END);
-
-	rx_end = get_time().le.lo;
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/nrf51/radio_test.h b/chip/nrf51/radio_test.h
deleted file mode 100644
index 591b78a78c..0000000000
--- a/chip/nrf51/radio_test.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Radio test interface for NRF51
- *
- * These functions implement parts of the Direct Test Mode functionality in
- * the Bluetooth Spec.
- */
-
-#ifndef __NRF51_RADIO_TEST_H
-#define __NRF51_RADIO_TEST_H
-
-#define BLE_MAX_TEST_PAYLOAD_OCTETS       37
-#define BLE_MAX_TEST_CHANNEL              39
-#define BLE_MIN_TEST_CHANNEL              0
-
-#define NRF51_RADIO_PCNF0_TEST NRF51_RADIO_PCNF0_ADV_DATA
-
-#define BLE_TEST_WHITEN           0
-
-#define NRF51_RADIO_PCNF1_TEST \
-	NRF51_RADIO_PCNF1_VAL(BLE_MAX_TEST_PAYLOAD_OCTETS, \
-			      EXTRA_RECEIVE_BYTES, \
-			      BLE_ACCESS_ADDRESS_BYTES - 1, \
-			      BLE_TEST_WHITEN)
-
-/*
- * Prepare the radio for transmitting packets.  The value of chan must be
- * between 0 and 39 inclusive.  The maximum length is 37.
- */
-
-int ble_test_tx_init(int chan, int type, int len);
-int ble_test_rx_init(int chan);
-void ble_test_tx(void);
-int ble_test_rx(void);
-void ble_test_stop(void);
-
-#endif /* __NRF51_RADIO_TEST_H */
diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h
deleted file mode 100644
index daf014df72..0000000000
--- a/chip/nrf51/registers.h
+++ /dev/null
@@ -1,720 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for STM32 processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-/*
- *  Peripheral IDs
- *
- *  nRF51 has very good design that the peripheral IDs is actually the IRQ#.
- *  Thus, the following numbers are used in DECLARE_IRQ(), task_enable_irq()
- *  and task_disable_irq().
- */
-#define NRF51_PERID_POWER   0
-#define NRF51_PERID_CLOCK   0
-#define NRF51_PERID_RADIO   1
-#define NRF51_PERID_USART   2
-#define NRF51_PERID_SPI0    3
-#define NRF51_PERID_TWI0    3
-#define NRF51_PERID_SPI1    4
-#define NRF51_PERID_TWI1    4
-#define NRF51_PERID_SPIS    4
-#define NRF51_PERID_GPIOTE  6
-#define NRF51_PERID_ADC     7
-#define NRF51_PERID_TIMER0  8
-#define NRF51_PERID_TIMER1  9
-#define NRF51_PERID_TIMER2  10
-#define NRF51_PERID_RTC     11
-#define NRF51_PERID_TEMP    12
-#define NRF51_PERID_RNG     13
-#define NRF51_PERID_ECB     14
-#define NRF51_PERID_CCM     15
-#define NRF51_PERID_AAR     16
-#define NRF51_PERID_WDT     17
-#define NRF51_PERID_QDEC    18
-#define NRF51_PERID_LPCOMP  19
-#define NRF51_PERID_NVMC    30
-#define NRF51_PERID_PPI     31
-
-/*
- * The nRF51 allows any pin to be mapped to any function.  This
- * doesn't fit well with the notion of the alternate function table.
- * Implement an alternate function table.  See ./gpio.c.
- */
-
-	/* UART */
-#define NRF51_UART_ALT_FUNC_RTS        0
-#define NRF51_UART_ALT_FUNC_TXD        1
-#define NRF51_UART_ALT_FUNC_CTS        2
-#define NRF51_UART_ALT_FUNC_RXD        3
-	/* SPI1 (SPI Master) */
-#define NRF51_SPI0_ALT_FUNC_SCK        4
-#define NRF51_SPI0_ALT_FUNC_MOSI       5
-#define NRF51_SPI0_ALT_FUNC_MISO       6
-	/* TWI0 (I2C) */
-#define NRF51_TWI0_ALT_FUNC_SCL        7
-#define NRF51_TWI0_ALT_FUNC_SDA        8
-	/* SPI1 (SPI Master) */
-#define NRF51_SPI1_ALT_FUNC_SCK        9
-#define NRF51_SPI1_ALT_FUNC_MOSI       10
-#define NRF51_SPI1_ALT_FUNC_MISO       11
-	/* TWI1 (I2C) */
-#define NRF51_TWI1_ALT_FUNC_SCL        12
-#define NRF51_TWI1_ALT_FUNC_SDA        13
-	/* SPIS1 (SPI SLAVE) */
-#define NRF51_SPIS1_ALT_FUNC_SCK       14
-#define NRF51_SPIS1_ALT_FUNC_MISO      15
-#define NRF51_SPIS1_ALT_FUNC_MOSI      16
-#define NRF51_SPIS1_ALT_FUNC_CSN       17
-	/* QDEC (ROTARY DECODER) */
-#define NRF51_QDEC_ALT_FUNC_LED        18
-#define NRF51_QDEC_ALT_FUNC_A          19
-#define NRF51_QDEC_ALT_FUNC_B          20
-	/* LPCOMP (Low Power Comparator) */
-#define NRF51_LPCOMP_ALT_FUNC          21
-#define NRF51_MAX_ALT_FUNCS            22
-
-/*
- * Configuration Registers
- */
-
-/*
- * FICR
- */
-#define NRF51_FICR_BASE                0x10000000
-#define NRF51_FICR_CODEPAGESIZE        REG32(NRF51_FICR_BASE + 0x010)
-#define NRF51_FICR_CLENR0              REG32(NRF51_FICR_BASE + 0x014)
-#define NRF51_FICR_PPFC                REG32(NRF51_FICR_BASE + 0x028)
-#define NRF51_FICR_NUMRAMBLOCK         REG32(NRF51_FICR_BASE + 0x02C)
-#define NRF51_FICR_SIZERAMBLOCK(n)     REG32(NRF51_FICR_BASE + 0x034 + ((n)*4))
-#define NRF51_FICR_CONFIGID            REG32(NRF51_FICR_BASE + 0x05C)
-#define NRF51_FICR_DEVICEID(n)         REG32(NRF51_FICR_BASE + 0x060 + ((n)*4))
-#define NRF51_FICR_ER(n)               REG32(NRF51_FICR_BASE + 0x080 + ((n)*4))
-#define NRF51_FICR_IR(n)               REG32(NRF51_FICR_BASE + 0x090 + ((n)*4))
-#define NRF51_FICR_DEVICEADDRTYPE      REG32(NRF51_FICR_BASE + 0x0A0)
-#define NRF51_FICR_DEVICEADDR(n)       REG32(NRF51_FICR_BASE + 0x0A4 + ((n)*4))
-#define NRF51_FICR_OVERRIDEEN          REG32(NRF51_FICR_BASE + 0x0AC)
-#define NRF51_FICR_BLE_1MBIT(n)        REG32(NRF51_FICR_BASE + 0x0EC + ((n)*4))
-
-/* DEVICEADDRTYPE */
-#define NRF51_FICR_DEVICEADDRTYPE_RANDOM      1
-
-/* OVERRIDEEN */
-#define NRF51_FICR_OVERRIDEEN_NRF_BIT_N       1
-#define NRF51_FICR_OVERRIDEEN_BLE_BIT_N       8
-
-/*
- * UICR
- */
-#define NRF51_UICR_BASE                0x10001000
-#define NRF51_UICR_CLENR0              REG32(NRF51_UICR_BASE + 0x000)
-#define NRF51_UICR_RBPCONF             REG32(NRF51_UICR_BASE + 0x004)
-#define NRF51_UICR_XTALFREQ            REG32(NRF51_UICR_BASE + 0x008)
-#define NRF51_UICR_FWID                REG32(NRF51_UICR_BASE + 0x010)
-#define NRF51_UICR_FWID_CUSTOMER(n)    REG32(NRF51_UICR_BASE + 0x080 + ((n)*4))
-
-#define NRF51_UICR_XTALFREQ_16MHZ      0xFF
-#define NRF51_UICR_XTALFREQ_32MHZ      0x00
-
-/*
- * Devices
- */
-
-/*
- *  Power
- */
-#define NRF51_POWER_BASE    0x40000000
-/* Tasks */
-#define NRF51_POWER_CONSTLAT  REG32(NRF51_POWER_BASE + 0x078)
-#define NRF51_POWER_LOWPWR    REG32(NRF51_POWER_BASE + 0x07C)
-/* Events */
-#define NRF51_POWER_POFWARN   REG32(NRF51_POWER_BASE + 0x108)
-/* Registers */
-#define NRF51_POWER_INTENSET  REG32(NRF51_POWER_BASE + 0x304)
-#define NRF51_POWER_INTENCLR  REG32(NRF51_POWER_BASE + 0x308)
-#define NRF51_POWER_RESETREAS REG32(NRF51_POWER_BASE + 0x400)
-#define NRF51_POWER_SYSTEMOFF REG32(NRF51_POWER_BASE + 0x500)
-#define NRF51_POWER_POFCON    REG32(NRF51_POWER_BASE + 0x510)
-#define NRF51_POWER_GPREGRET  REG32(NRF51_POWER_BASE + 0x51C)
-#define NRF51_POWER_RAMON     REG32(NRF51_POWER_BASE + 0x524)
-#define NRF51_POWER_RESET     REG32(NRF51_POWER_BASE + 0x544)
-#define NRF51_POWER_DCDCEN    REG32(NRF51_POWER_BASE + 0x578)
-
-#define NRF51_POWER_RESETREAS_RESETPIN          0x00001
-#define NRF51_POWER_RESETREAS_DOG               0x00002
-#define NRF51_POWER_RESETREAS_SREQ              0x00004
-#define NRF51_POWER_RESETREAS_LOCKUP            0x00008
-#define NRF51_POWER_RESETREAS_OFF               0x10000
-#define NRF51_POWER_RESETREAS_LPCOMP            0x20000
-#define NRF51_POWER_RESETREAS_DIF               0x40000
-
-
-/*
- *  Clock
- */
-#define NRF51_CLOCK_BASE    0x40000000
-/* Tasks */
-#define NRF51_CLOCK_HFCLKSTART REG32(NRF51_CLOCK_BASE + 0x000)
-#define NRF51_CLOCK_HFCLKSTOP  REG32(NRF51_CLOCK_BASE + 0x004)
-#define NRF51_CLOCK_LFCLKSTART REG32(NRF51_CLOCK_BASE + 0x008)
-#define NRF51_CLOCK_LFCLKSTOP  REG32(NRF51_CLOCK_BASE + 0x00C)
-#define NRF51_CLOCK_CAL     REG32(NRF51_CLOCK_BASE + 0x010)
-#define NRF51_CLOCK_CTSTART REG32(NRF51_CLOCK_BASE + 0x014)
-#define NRF51_CLOCK_CTSTOP  REG32(NRF51_CLOCK_BASE + 0x018)
-/* Events */
-#define NRF51_CLOCK_HFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x100)
-#define NRF51_CLOCK_LFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x104)
-#define NRF51_CLOCK_DONE    REG32(NRF51_CLOCK_BASE + 0x10C)
-#define NRF51_CLOCK_CCTO    REG32(NRF51_CLOCK_BASE + 0x110)
-/* Registers */
-#define NRF51_CLOCK_INTENSET  REG32(NRF51_CLOCK_BASE + 0x304)
-#define NRF51_CLOCK_INTENCLR  REG32(NRF51_CLOCK_BASE + 0x308)
-#define NRF51_CLOCK_HFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x40C)
-#define NRF51_CLOCK_LFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x418)
-#define NRF51_CLOCK_LFCLKSRC  REG32(NRF51_CLOCK_BASE + 0x518)
-#define NRF51_CLOCK_CTIV      REG32(NRF51_CLOCK_BASE + 0x538)
-#define NRF51_CLOCK_XTALFREQ  REG32(NRF51_CLOCK_BASE + 0x550)
-
-/*
- *  Radio
- */
-#define NRF51_RADIO_BASE    0x40001000
-/* Tasks */
-#define NRF51_RADIO_TXEN      REG32(NRF51_RADIO_BASE + 0x000)
-#define NRF51_RADIO_RXEN      REG32(NRF51_RADIO_BASE + 0x004)
-#define NRF51_RADIO_START     REG32(NRF51_RADIO_BASE + 0x008)
-#define NRF51_RADIO_STOP      REG32(NRF51_RADIO_BASE + 0x00C)
-#define NRF51_RADIO_DISABLE   REG32(NRF51_RADIO_BASE + 0x010)
-#define NRF51_RADIO_RSSISTART REG32(NRF51_RADIO_BASE + 0x014)
-#define NRF51_RADIO_RSSISTOP  REG32(NRF51_RADIO_BASE + 0x018)
-#define NRF51_RADIO_BCSTART   REG32(NRF51_RADIO_BASE + 0x01C)
-#define NRF51_RADIO_BCSTOP    REG32(NRF51_RADIO_BASE + 0x020)
-/* Events */
-#define NRF51_RADIO_READY     REG32(NRF51_RADIO_BASE + 0x100)
-#define NRF51_RADIO_ADDRESS   REG32(NRF51_RADIO_BASE + 0x104)
-#define NRF51_RADIO_PAYLOAD   REG32(NRF51_RADIO_BASE + 0x108)
-#define NRF51_RADIO_END       REG32(NRF51_RADIO_BASE + 0x10C)
-#define NRF51_RADIO_DISABLED  REG32(NRF51_RADIO_BASE + 0x110)
-#define NRF51_RADIO_DEVMATCH  REG32(NRF51_RADIO_BASE + 0x114)
-#define NRF51_RADIO_DEVMISS   REG32(NRF51_RADIO_BASE + 0x118)
-#define NRF51_RADIO_RSSIEND   REG32(NRF51_RADIO_BASE + 0x11C)
-#define NRF51_RADIO_BCMATCH   REG32(NRF51_RADIO_BASE + 0x128)
-/* Registers */
-#define NRF51_RADIO_SHORTS      REG32(NRF51_RADIO_BASE + 0x200)
-#define NRF51_RADIO_INTENSET    REG32(NRF51_RADIO_BASE + 0x304)
-#define NRF51_RADIO_INTENCLR    REG32(NRF51_RADIO_BASE + 0x308)
-#define NRF51_RADIO_CRCSTATUS   REG32(NRF51_RADIO_BASE + 0x400)
-#define NRF51_RADIO_RXMATCH     REG32(NRF51_RADIO_BASE + 0x408)
-#define NRF51_RADIO_RXCRC       REG32(NRF51_RADIO_BASE + 0x40C)
-#define NRF51_RADIO_DAI         REG32(NRF51_RADIO_BASE + 0x410)
-#define NRF51_RADIO_PACKETPTR   REG32(NRF51_RADIO_BASE + 0x504)
-#define NRF51_RADIO_FREQUENCY   REG32(NRF51_RADIO_BASE + 0x508)
-#define NRF51_RADIO_TXPOWER     REG32(NRF51_RADIO_BASE + 0x50C)
-#define NRF51_RADIO_MODE        REG32(NRF51_RADIO_BASE + 0x510)
-#define NRF51_RADIO_PCNF0       REG32(NRF51_RADIO_BASE + 0x514)
-#define NRF51_RADIO_PCNF1       REG32(NRF51_RADIO_BASE + 0x518)
-#define NRF51_RADIO_BASE0       REG32(NRF51_RADIO_BASE + 0x51C)
-#define NRF51_RADIO_BASE1       REG32(NRF51_RADIO_BASE + 0x520)
-#define NRF51_RADIO_PREFIX0     REG32(NRF51_RADIO_BASE + 0x524)
-#define NRF51_RADIO_PREFIX1     REG32(NRF51_RADIO_BASE + 0x528)
-#define NRF51_RADIO_TXADDRESS   REG32(NRF51_RADIO_BASE + 0x52C)
-#define NRF51_RADIO_RXADDRESSES REG32(NRF51_RADIO_BASE + 0x530)
-#define NRF51_RADIO_CRCCNF      REG32(NRF51_RADIO_BASE + 0x534)
-#define NRF51_RADIO_CRCPOLY     REG32(NRF51_RADIO_BASE + 0x538)
-#define NRF51_RADIO_CRCINIT     REG32(NRF51_RADIO_BASE + 0x53C)
-#define NRF51_RADIO_TEST        REG32(NRF51_RADIO_BASE + 0x540)
-#define NRF51_RADIO_TIFS        REG32(NRF51_RADIO_BASE + 0x544)
-#define NRF51_RADIO_RSSISAMPLE  REG32(NRF51_RADIO_BASE + 0x548)
-/* NRF51_RADIO_STATE (0x550) is Broken (PAN 2.4) */
-#define NRF51_RADIO_DATAWHITEIV REG32(NRF51_RADIO_BASE + 0x554)
-#define NRF51_RADIO_BCC         REG32(NRF51_RADIO_BASE + 0x560)
-#define NRF51_RADIO_DAB(n)      REG32(NRF51_RADIO_BASE + 0x600 + ((n) * 4))
-#define NRF51_RADIO_DAP(n)      REG32(NRF51_RADIO_BASE + 0x620 + ((n) * 4))
-#define NRF51_RADIO_DACNF       REG32(NRF51_RADIO_BASE + 0x640)
-#define NRF51_RADIO_OVERRIDE(n) REG32(NRF51_RADIO_BASE + 0x724 + ((n) * 4))
-#define NRF51_RADIO_POWER       REG32(NRF51_RADIO_BASE + 0xFFC)
-
-/* Shorts */
-#define NRF51_RADIO_SHORTS_READY_START                0x001
-#define NRF51_RADIO_SHORTS_END_DISABLE                0x002
-#define NRF51_RADIO_SHORTS_DISABLED_TXEN              0x004
-#define NRF51_RADIO_SHORTS_DISABLED_RXEN              0x008
-#define NRF51_RADIO_SHORTS_ADDRESS_RSSISTART          0x010
-/* NRF51_RADIO_SHORTS_END_START (0x20) is Broken (PAN 2.4) */
-#define NRF51_RADIO_SHORTS_ADDRESS_BCSTART            0x040
-#define NRF51_RADIO_SHORTS_DISABLED_RSSISTOP          0x100
-
-/* For RADIO.INTEN bits */
-#define NRF51_RADIO_READY_BIT                         0
-#define NRF51_RADIO_ADDRESS_BIT                       1
-#define NRF51_RADIO_PAYLOAD_BIT                       2
-#define NRF51_RADIO_END_BIT                           3
-#define NRF51_RADIO_DISABLED_BIT                      4
-#define NRF51_RADIO_DEVMATCH_BIT                      5
-#define NRF51_RADIO_DEVMISS_BIT                       6
-#define NRF51_RADIO_RSSIEND_BIT                       7
-#define NRF51_RADIO_BCMATCH_BIT                       10
-
-/* CRC Status */
-#define NRF51_RADIO_CRCSTATUS_OK                      0x1
-
-/* Frequency (in MHz) */
-#define NRF51_RADIO_FREQUENCY_VAL(x)                  ((x) - 2400)
-
-/* TX Power */
-#define NRF51_RADIO_TXPOWER_POS_4_DBM                 0x04
-#define NRF51_RADIO_TXPOWER_0_DBM                     0x00
-#define NRF51_RADIO_TXPOWER_NEG_8_DBM                 0xFC
-#define NRF51_RADIO_TXPOWER_NEG_12_DBM                0xF8
-#define NRF51_RADIO_TXPOWER_NEG_16_DBM                0xF4
-#define NRF51_RADIO_TXPOWER_NEG_20_DBM                0xEC
-#define NRF51_RADIO_TXPOWER_NEG_30_DBM                0xD8
-
-/* TX Mode */
-#define NRF51_RADIO_MODE_BLE_1MBIT                    0x03
-
-/*
- * PCNF0 and PCNF1 Packet Configuration
- *
- * The radio unpacks the packet for you according to these settings.
- *
- * The on-air format is:
- *
- * |_Preamble_|___Base___|_Prefix_|___S0____|_Length_,_S1_|__Payload__|___|
- * 0           <ba_bytes> <1 byte><s0_bytes>   <1 byte>    <max_bytes> <extra>
- *
- * The in-memory format is
- *
- * uint8_t s0[s0_bytes];
- * uint8_t length;
- * uint8_t s1;
- * uint8_t payload[max_bytes];
- *
- * lf_bits is how many bits to store in length
- * s1_bits is how many bits to store in s1
- *
- * If any one of these lengths are set to zero, the field is omitted in memory.
- */
-
-#define NRF51_RADIO_PCNF0_LFLEN_SHIFT                 0
-#define NRF51_RADIO_PCNF0_S0LEN_SHIFT                 8
-#define NRF51_RADIO_PCNF0_S1LEN_SHIFT                 16
-
-#define NRF51_RADIO_PCNF0_VAL(lf_bits, s0_bytes, s1_bits) \
-	((lf_bits) << NRF51_RADIO_PCNF0_LFLEN_SHIFT | \
-	 (s0_bytes) << NRF51_RADIO_PCNF0_S0LEN_SHIFT | \
-	 (s1_bits) << NRF51_RADIO_PCNF0_S1LEN_SHIFT)
-
-#define NRF51_RADIO_PCNF1_MAXLEN_SHIFT                0
-#define NRF51_RADIO_PCNF1_STATLEN_SHIFT               8
-#define NRF51_RADIO_PCNF1_BALEN_SHIFT                 16
-#define NRF51_RADIO_PCNF1_ENDIAN_BIG                  0x1000000
-#define NRF51_RADIO_PCNF1_WHITEEN                     0x2000000
-
-#define NRF51_RADIO_PCNF1_VAL(max_bytes, extra_bytes, ba_bytes, whiten) \
-	((max_bytes) << NRF51_RADIO_PCNF1_MAXLEN_SHIFT | \
-	 (extra_bytes) << NRF51_RADIO_PCNF1_STATLEN_SHIFT | \
-	 (ba_bytes) << NRF51_RADIO_PCNF1_BALEN_SHIFT | \
-	 ((whiten) ? NRF51_RADIO_PCNF1_WHITEEN : 0))
-
-/* PREFIX0 */
-#define NRF51_RADIO_PREFIX0_AP0_SHIFT                 0
-#define NRF51_RADIO_PREFIX0_AP1_SHIFT                 8
-#define NRF51_RADIO_PREFIX0_AP2_SHIFT                 16
-#define NRF51_RADIO_PREFIX0_AP3_SHIFT                 24
-
-/* PREFIX1 */
-#define NRF51_RADIO_PREFIX1_AP4_SHIFT                 0
-#define NRF51_RADIO_PREFIX1_AP5_SHIFT                 8
-#define NRF51_RADIO_PREFIX1_AP6_SHIFT                 16
-#define NRF51_RADIO_PREFIX1_AP7_SHIFT                 24
-
-/* CRCCNF */
-#define NRF51_RADIO_CRCCNF_SKIP_ADDR                  0x100
-
-/* TEST */
-#define NRF51_RADIO_TEST_CONST_CARRIER_EN             0x01
-#define NRF51_RADIO_TEST_PLL_LOCK_EN                  0x02
-
-/* STATE */
-#define NRF51_RADIO_STATE_DISABLED                    0
-#define NRF51_RADIO_STATE_RXRU                        1
-#define NRF51_RADIO_STATE_RXIDLE                      2
-#define NRF51_RADIO_STATE_RX                          3
-#define NRF51_RADIO_STATE_RXDISABLE                   4
-#define NRF51_RADIO_STATE_TXRU                        9
-#define NRF51_RADIO_STATE_TXIDLE                      10
-#define NRF51_RADIO_STATE_TX                          11
-#define NRF51_RADIO_STATE_TXDISABLE                   12
-
-/* DACNF */
-#define NRF51_RADIO_DACNF_ENA(n)                      (1 << (n))
-#define NRF51_RADIO_DACNF_MAX                         8
-#define NRF51_RADIO_DACNF_TXADD(n)                    (1 << ((n)+8))
-#define NRF51_RADIO_TXADD_MAX                         8
-
-/* OVERRIDE4 */
-#define NRF51_RADIO_OVERRIDE_EN                       BIT(31)
-
-
-/*
- *  UART
- */
-#define NRF51_UART_BASE     0x40002000
-/* Tasks */
-#define NRF51_UART_STARTRX  REG32(NRF51_UART_BASE + 0x000)
-#define NRF51_UART_STOPRX   REG32(NRF51_UART_BASE + 0x004)
-#define NRF51_UART_STARTTX  REG32(NRF51_UART_BASE + 0x008)
-#define NRF51_UART_STOPTX   REG32(NRF51_UART_BASE + 0x00C)
-/* Events */
-#define NRF51_UART_RXDRDY   REG32(NRF51_UART_BASE + 0x108)
-#define NRF51_UART_TXDRDY   REG32(NRF51_UART_BASE + 0x11C)
-#define NRF51_UART_ERROR    REG32(NRF51_UART_BASE + 0x124)
-#define NRF51_UART_RXTO     REG32(NRF51_UART_BASE + 0x144)
-/* Registers */
-#define NRF51_UART_INTENSET REG32(NRF51_UART_BASE + 0x304)
-#define NRF51_UART_INTENCLR REG32(NRF51_UART_BASE + 0x308)
-#define NRF51_UART_ERRORSRC REG32(NRF51_UART_BASE + 0x480)
-#define NRF51_UART_ENABLE   REG32(NRF51_UART_BASE + 0x500)
-#define NRF51_UART_PSELRTS  REG32(NRF51_UART_BASE + 0x508)
-#define NRF51_UART_PSELTXD  REG32(NRF51_UART_BASE + 0x50C)
-#define NRF51_UART_PSELCTS  REG32(NRF51_UART_BASE + 0x510)
-#define NRF51_UART_PSELRXD  REG32(NRF51_UART_BASE + 0x514)
-#define NRF51_UART_RXD      REG32(NRF51_UART_BASE + 0x518)
-#define NRF51_UART_TXD      REG32(NRF51_UART_BASE + 0x51C)
-#define NRF51_UART_BAUDRATE REG32(NRF51_UART_BASE + 0x524)
-#define NRF51_UART_CONFIG   REG32(NRF51_UART_BASE + 0x56C)
-/* For UART.INTEN bits */
-#define NRF55_UART_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_UART_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  TWI (I2C) Instances
- */
-#define NRF51_TWI_BASE(port)     (0x40003000 + ((port == 0) ? 0 : 0x1000))
-/* Tasks */
-#define NRF51_TWI_STARTRX(port)   REG32(NRF51_TWI_BASE(port) + 0x000)
-#define NRF51_TWI_STARTTX(port)   REG32(NRF51_TWI_BASE(port) + 0x008)
-#define NRF51_TWI_STOP(port)      REG32(NRF51_TWI_BASE(port) + 0x014)
-#define NRF51_TWI_SUSPEND(port)   REG32(NRF51_TWI_BASE(port) + 0x01C)
-#define NRF51_TWI_RESUME(port)    REG32(NRF51_TWI_BASE(port) + 0x020)
-/* Events */
-#define NRF51_TWI_STOPPED(port)   REG32(NRF51_TWI_BASE(port) + 0x104)
-#define NRF51_TWI_RXDRDY(port)    REG32(NRF51_TWI_BASE(port) + 0x108)
-#define NRF51_TWI_TXDSENT(port)   REG32(NRF51_TWI_BASE(port) + 0x11C)
-#define NRF51_TWI_ERROR(port)     REG32(NRF51_TWI_BASE(port) + 0x124)
-#define NRF51_TWI_BB(port)        REG32(NRF51_TWI_BASE(port) + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI_INTEN(port)     REG32(NRF51_TWI_BASE(port) + 0x300)
-#define NRF51_TWI_INTENSET(port)  REG32(NRF51_TWI_BASE(port) + 0x304)
-#define NRF51_TWI_INTENCLR(port)  REG32(NRF51_TWI_BASE(port) + 0x308)
-#define NRF51_TWI_ERRORSRC(port)  REG32(NRF51_TWI_BASE(port) + 0x4C4)
-#define NRF51_TWI_ENABLE(port)    REG32(NRF51_TWI_BASE(port) + 0x500)
-#define NRF51_TWI_PSELSCL(port)   REG32(NRF51_TWI_BASE(port) + 0x508)
-#define NRF51_TWI_PSELSDA(port)   REG32(NRF51_TWI_BASE(port) + 0x50C)
-#define NRF51_TWI_RXD(port)       REG32(NRF51_TWI_BASE(port) + 0x518)
-#define NRF51_TWI_TXD(port)       REG32(NRF51_TWI_BASE(port) + 0x51C)
-#define NRF51_TWI_FREQUENCY(port) REG32(NRF51_TWI_BASE(port) + 0x524)
-#define NRF51_TWI_ADDRESS(port)   REG32(NRF51_TWI_BASE(port) + 0x588)
-#define NRF51_TWI_POWER(port)     REG32(NRF51_TWI_BASE(port) + 0xFFC)
-
-#define NRF51_TWI_100KBPS         0x01980000
-#define NRF51_TWI_250KBPS         0x40000000
-#define NRF51_TWI_400KBPS         0x06680000
-
-#define NRF51_TWI_ENABLE_VAL      0x5
-#define NRF51_TWI_DISABLE_VAL     0x0
-
-#define NRF51_TWI_ERRORSRC_ANACK  BIT(1) /* Address NACK */
-#define NRF51_TWI_ERRORSRC_DNACK  BIT(2) /* Data NACK */
-
-/*
- *  TWI (I2C) Instance 0
- */
-#define NRF51_TWI0_BASE     0x40003000
-/* Tasks */
-#define NRF51_TWI0_STARTRX   REG32(NRF51_TWI0_BASE + 0x000)
-#define NRF51_TWI0_STARTTX   REG32(NRF51_TWI0_BASE + 0x008)
-#define NRF51_TWI0_STOP      REG32(NRF51_TWI0_BASE + 0x014)
-#define NRF51_TWI0_SUSPEND   REG32(NRF51_TWI0_BASE + 0x01C)
-#define NRF51_TWI0_RESUME    REG32(NRF51_TWI0_BASE + 0x020)
-/* Events */
-#define NRF51_TWI0_STOPPED   REG32(NRF51_TWI0_BASE + 0x104)
-#define NRF51_TWI0_RXDRDY    REG32(NRF51_TWI0_BASE + 0x108)
-#define NRF51_TWI0_TXDSENT   REG32(NRF51_TWI0_BASE + 0x11C)
-#define NRF51_TWI0_ERROR     REG32(NRF51_TWI0_BASE + 0x124)
-#define NRF51_TWI0_BB        REG32(NRF51_TWI0_BASE + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI0_INTENSET  REG32(NRF51_TWI0_BASE + 0x304)
-#define NRF51_TWI0_INTENCLR  REG32(NRF51_TWI0_BASE + 0x308)
-#define NRF51_TWI0_ERRORSRC  REG32(NRF51_TWI0_BASE + 0x4C4)
-#define NRF51_TWI0_ENABLE    REG32(NRF51_TWI0_BASE + 0x500)
-#define NRF51_TWI0_PSELSCL   REG32(NRF51_TWI0_BASE + 0x508)
-#define NRF51_TWI0_PSELSDA   REG32(NRF51_TWI0_BASE + 0x50C)
-#define NRF51_TWI0_RXD       REG32(NRF51_TWI0_BASE + 0x518)
-#define NRF51_TWI0_TXD       REG32(NRF51_TWI0_BASE + 0x51C)
-#define NRF51_TWI0_FREQUENCY REG32(NRF51_TWI0_BASE + 0x524)
-#define NRF51_TWI0_ADDRESS   REG32(NRF51_TWI0_BASE + 0x588)
-
-/* For TWI0.INTEN bits */
-#define NRF55_TWI0_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_TWI0_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  TWI (I2C) Instance 1
- */
-#define NRF51_TWI1_BASE     0x40004000
-/* Tasks */
-#define NRF51_TWI1_STARTRX   REG32(NRF51_TWI1_BASE + 0x000)
-#define NRF51_TWI1_STARTTX   REG32(NRF51_TWI1_BASE + 0x008)
-#define NRF51_TWI1_STOP      REG32(NRF51_TWI1_BASE + 0x014)
-#define NRF51_TWI1_SUSPEND   REG32(NRF51_TWI1_BASE + 0x01C)
-#define NRF51_TWI1_RESUME    REG32(NRF51_TWI1_BASE + 0x020)
-/* Events */
-#define NRF51_TWI1_STOPPED   REG32(NRF51_TWI1_BASE + 0x104)
-#define NRF51_TWI1_RXDRDY    REG32(NRF51_TWI1_BASE + 0x108)
-#define NRF51_TWI1_TXDSENT   REG32(NRF51_TWI1_BASE + 0x11C)
-#define NRF51_TWI1_ERROR     REG32(NRF51_TWI1_BASE + 0x124)
-#define NRF51_TWI1_BB        REG32(NRF51_TWI1_BASE + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI1_INTENSET  REG32(NRF51_TWI1_BASE + 0x304)
-#define NRF51_TWI1_INTENCLR  REG32(NRF51_TWI1_BASE + 0x308)
-#define NRF51_TWI1_ERRORSRC  REG32(NRF51_TWI1_BASE + 0x4C4)
-#define NRF51_TWI1_ENABLE    REG32(NRF51_TWI1_BASE + 0x500)
-#define NRF51_TWI1_PSELSCL   REG32(NRF51_TWI1_BASE + 0x508)
-#define NRF51_TWI1_PSELSDA   REG32(NRF51_TWI1_BASE + 0x50C)
-#define NRF51_TWI1_RXD       REG32(NRF51_TWI1_BASE + 0x518)
-#define NRF51_TWI1_TXD       REG32(NRF51_TWI1_BASE + 0x51C)
-#define NRF51_TWI1_FREQUENCY REG32(NRF51_TWI1_BASE + 0x524)
-#define NRF51_TWI1_ADDRESS   REG32(NRF51_TWI1_BASE + 0x588)
-
-/* For TWI1.INTEN bits */
-#define NRF55_TWI1_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_TWI1_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  GPIOTE - GPIO Tasks and Events
- */
-#define NRF51_GPIOTE_BASE   0x40006000
-/* Tasks */
-#define NRF51_GPIOTE_OUT(n)    REG32(NRF51_GPIOTE_BASE + ((n) * 4))
-/* Events */
-#define NRF51_GPIOTE_IN(n)     REG32(NRF51_GPIOTE_BASE + 0x100 + ((n) * 4))
-#define NRF51_GPIOTE_PORT      REG32(NRF51_GPIOTE_BASE + 0x17C)
-/* Registers */
-#define NRF51_GPIOTE_INTENSET  REG32(NRF51_GPIOTE_BASE + 0x304)
-#define NRF51_GPIOTE_INTENCLR  REG32(NRF51_GPIOTE_BASE + 0x308)
-#define NRF51_GPIOTE_CONFIG(n) REG32(NRF51_GPIOTE_BASE + 0x510 + ((n) * 4))
-#define NRF51_GPIOTE_POWER     REG32(NRF51_GPIOTE_BASE + 0xFFC)
-
-/* Number of IN events */
-#define NRF51_GPIOTE_IN_COUNT  4
-
-/* Bits */
-/* For GPIOTE.INTEN */
-#define NRF51_GPIOTE_IN_BIT(n) (n)
-#define NRF51_GPIOTE_PORT_BIT  31
-/* For GPIOTE.CONFIG */
-#define NRF51_GPIOTE_MODE_DISABLED     (0<<0)
-#define NRF51_GPIOTE_MODE_EVENT        BIT(0)
-#define NRF51_GPIOTE_MODE_TASK         (3<<0)
-#define NRF51_GPIOTE_PSEL_POS          (8)
-#define NRF51_GPIOTE_POLARITY_LOTOHI   BIT(16)
-#define NRF51_GPIOTE_POLARITY_HITOLO   (2<<16)
-#define NRF51_GPIOTE_POLARITY_TOGGLE   (3<<16)
-#define NRF51_GPIOTE_OUTINIT_LOW       (0<<20)
-#define NRF51_GPIOTE_OUTINIT_HIGH      BIT(20)
-
-/*
- *  Timer / Counter
- */
-#define NRF51_TIMER0_BASE   0x40008000
-#define NRF51_TIMER_BASE(n)   (NRF51_TIMER0_BASE + (n) * 0x1000)
-#define NRF51_PERID_TIMER(n)  (NRF51_PERID_TIMER0 + (n))
-/* Tasks */
-#define NRF51_TIMER_START(n)  REG32(NRF51_TIMER_BASE(n) + 0x000)
-#define NRF51_TIMER_STOP(n)   REG32(NRF51_TIMER_BASE(n) + 0x004)
-#define NRF51_TIMER_COUNT(n)  REG32(NRF51_TIMER_BASE(n) + 0x008)
-#define NRF51_TIMER_CLEAR(n)  REG32(NRF51_TIMER_BASE(n) + 0x00C)
-#define NRF51_TIMER_CAPTURE(n, c)  REG32(NRF51_TIMER_BASE(n) + 0x040 + 4 * (c))
-/* Events */
-#define NRF51_TIMER_COMPARE(n, c)  REG32(NRF51_TIMER_BASE(n) + 0x140 + 4 * (c))
-/* Registers */
-#define NRF51_TIMER_SHORTCUT(n)  REG32(NRF51_TIMER_BASE(n) + 0x200)
-#define NRF51_TIMER_INTENSET(n)  REG32(NRF51_TIMER_BASE(n) + 0x304)
-#define NRF51_TIMER_INTENCLR(n)  REG32(NRF51_TIMER_BASE(n) + 0x308)
-#define NRF51_TIMER_MODE(n)      REG32(NRF51_TIMER_BASE(n) + 0x504)
-#define NRF51_TIMER_BITMODE(n)   REG32(NRF51_TIMER_BASE(n) + 0x508)
-#define NRF51_TIMER_PRESCALER(n) REG32(NRF51_TIMER_BASE(n) + 0x510)
-#define NRF51_TIMER_CC(n, c)     REG32(NRF51_TIMER_BASE(n) + 0x540 + 4 * (c))
-/* For Timer.INTEN bits */
-#define NRF51_TIMER_COMPARE_BIT(n)  (((0x140 - 0x100) / 4) + (n))
-/* For Timer Shortcuts */
-#define NRF51_TIMER_COMPARE_CLEAR(n)  (1 << (n))
-#define NRF51_TIMER_COMPARE_STOP(n)   (1 << (8 + (n)))
-/* Timer Mode (NRF51_TIMER_MODE) */
-#define NRF51_TIMER_MODE_TIMER   0  /* reset default */
-#define NRF51_TIMER_MODE_COUNTER 1
-/* Prescaler */
-#define NRF51_TIMER_PRESCALER_MASK (0xf)  /* range: 0-9, reset default: 4 */
-/* Bit length (NRF51_TIMER_BITMODE) */
-#define NRF51_TIMER_BITMODE_16  0  /* reset default */
-#define NRF51_TIMER_BITMODE_8   1
-#define NRF51_TIMER_BITMODE_24  2
-#define NRF51_TIMER_BITMODE_32  3
-
-
-/*
- *  Random Number Generator (RNG)
- */
-#define NRF51_RNG_BASE               0x4000D000
-/* Tasks */
-#define NRF51_RNG_START              REG32(NRF51_RNG_BASE + 0x000)
-#define NRF51_RNG_STOP               REG32(NRF51_RNG_BASE + 0x004)
-/* Events */
-#define NRF51_RNG_VALRDY             REG32(NRF51_RNG_BASE + 0x100)
-/* Registers */
-#define NRF51_RNG_SHORTS             REG32(NRF51_RNG_BASE + 0x200)
-#define NRF51_RNG_INTENSET           REG32(NRF51_RNG_BASE + 0x304)
-#define NRF51_RNG_INTENCLR           REG32(NRF51_RNG_BASE + 0x308)
-#define NRF51_RNG_CONFIG             REG32(NRF51_RNG_BASE + 0x504)
-#define NRF51_RNG_VALUE              REG32(NRF51_RNG_BASE + 0x508)
-/* For RNG Shortcuts */
-#define NRF51_RNG_SHORTS_VALRDY_STOP BIT(0)
-/* For RNG Config */
-#define NRF51_RNG_DERCEN             BIT(0)
-
-
-/*
- *  Watchdog Timer (WDT)
- */
-#define NRF51_WDT_BASE        0x40010000
-/* Tasks */
-#define NRF51_WDT_START       REG32(NRF51_WDT_BASE + 0x000)
-/* Events */
-#define NRF51_WDT_TIMEOUT     REG32(NRF51_WDT_BASE + 0x100)
-/* Registers */
-#define NRF51_WDT_INTENSET    REG32(NRF51_WDT_BASE + 0x304)
-#define NRF51_WDT_INTENCLR    REG32(NRF51_WDT_BASE + 0x308)
-#define NRF51_WDT_RUNSTATUS   REG32(NRF51_WDT_BASE + 0x400)
-#define NRF51_WDT_REQSTATUS   REG32(NRF51_WDT_BASE + 0x404)
-#define NRF51_WDT_CRV         REG32(NRF51_WDT_BASE + 0x504)
-#define NRF51_WDT_RREN        REG32(NRF51_WDT_BASE + 0x508)
-#define NRF51_WDT_CONFIG      REG32(NRF51_WDT_BASE + 0x50C)
-#define NRF51_WDT_RR(n)       REG32(NRF51_WDT_BASE + 0x600 + ((n) * 4))
-#define NRF51_WDT_POWER       REG32(NRF51_WDT_BASE + 0xFFC)
-/* Bitfields */
-#define NRF51_WDT_RUNSTATUS_RUNNING        1
-#define NRF51_WDT_REQSTATUS_BIT(n)        (1<<(n))
-#define NRF51_WDT_RREN_BIT(n)             (1<<(n))
-#define NRF51_WDT_CONFIG_SLEEP_PAUSE       0
-#define NRF51_WDT_CONFIG_SLEEP_RUN         1
-#define NRF51_WDT_CONFIG_HALT_PAUSE       (0<<4)
-#define NRF51_WDT_CONFIG_HALT_RUN         BIT(4)
-
-#define NRF51_WDT_RELOAD_VAL             0x6E524635
-
-
-/*
- *  GPIO
- */
-#define NRF51_GPIO_BASE     0x50000000
-#define NRF51_GPIO0_BASE    (NRF51_GPIO_BASE + 0x500)
-#define NRF51_GPIO0_OUT     REG32(NRF51_GPIO0_BASE + 0x004)
-#define NRF51_GPIO0_OUTSET  REG32(NRF51_GPIO0_BASE + 0x008)
-#define NRF51_GPIO0_OUTCLR  REG32(NRF51_GPIO0_BASE + 0x00C)
-#define NRF51_GPIO0_IN      REG32(NRF51_GPIO0_BASE + 0x010)
-#define NRF51_GPIO0_DIR     REG32(NRF51_GPIO0_BASE + 0x014)  /* 1 for output */
-#define NRF51_GPIO0_DIRSET  REG32(NRF51_GPIO0_BASE + 0x018)
-#define NRF51_GPIO0_DIRCLR  REG32(NRF51_GPIO0_BASE + 0x01C)
-#define NRF51_PIN_BASE      (NRF51_GPIO_BASE + 0x700)
-#define NRF51_PIN_CNF(n)    REG32(NRF51_PIN_BASE + ((n) * 4))
-#define GPIO_0              NRF51_GPIO0_BASE
-
-#define NRF51_PIN_CNF_DIR_INPUT        (0)
-#define NRF51_PIN_CNF_DIR_OUTPUT       (1)
-#define NRF51_PIN_CNF_INPUT_CONNECT    (0<<1)
-#define NRF51_PIN_CNF_INPUT_DISCONNECT BIT(1)
-#define NRF51_PIN_CNF_PULL_DISABLED    (0<<2)
-#define NRF51_PIN_CNF_PULLDOWN         BIT(2)
-#define NRF51_PIN_CNF_PULLUP           (3<<2)
-/*
- * Logic levels 0 and 1, strengths S=Standard, H=High D=Disconnect
- * for example, S0D1 = Standard drive 0, disconnect on 1
- */
-#define NRF51_PIN_CNF_DRIVE_S0S1       (0<<8)
-#define NRF51_PIN_CNF_DRIVE_H0S1       BIT(8)
-#define NRF51_PIN_CNF_DRIVE_S0H1       (2<<8)
-#define NRF51_PIN_CNF_DRIVE_H0H1       (3<<8)
-#define NRF51_PIN_CNF_DRIVE_D0S1       (4<<8)
-#define NRF51_PIN_CNF_DRIVE_D0H1       (5<<8)
-#define NRF51_PIN_CNF_DRIVE_S0D1       (6<<8)
-#define NRF51_PIN_CNF_DRIVE_H0D1       (7<<8)
-
-#define NRF51_PIN_CNF_SENSE_DISABLED   (0<<16)
-#define NRF51_PIN_CNF_SENSE_HIGH       (2<<16)
-#define NRF51_PIN_CNF_SENSE_LOW        (3<<16)
-
-#define UNIMPLEMENTED_GPIO_BANK     GPIO_0  /* for UNIMPLEMENTED() macro */
-
-#define NRF51_PPI_BASE                 0x4001F000
-#define NRF51_PPI_CHEN                 REG32(NRF51_PPI_BASE + 0x500)
-#define NRF51_PPI_CHENSET              REG32(NRF51_PPI_BASE + 0x504)
-#define NRF51_PPI_CHENCLR              REG32(NRF51_PPI_BASE + 0x508)
-#define NRF51_PPI_EEP(channel)         REG32(NRF51_PPI_BASE + 0x510 + channel*8)
-#define NRF51_PPI_TEP(channel)         REG32(NRF51_PPI_BASE + 0x514 + channel*8)
-#define NRF51_PPI_CHG(group)           REG32(NRF51_PPI_BASE + 0x800 + group*4)
-
-#define NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS        16
-#define NRF51_PPI_NUM_GROUPS                       4
-
-#define NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN        20
-#define NRF51_PPI_CH_TIMER0_CC0__RADIO_RXEN        21
-#define NRF51_PPI_CH_TIMER0_CC1__RADIO_DISABLE     22
-#define NRF51_PPI_CH_RADIO_BCMATCH__AAR_START      23
-#define NRF51_PPI_CH_RADIO_READY__CCM_KSGEN        24
-#define NRF51_PPI_CH_RADIO_ADDR__CCM_CRYPT         25
-#define NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1         26
-#define NRF51_PPI_CH_RADIO_END_TIMER0CC2           27
-#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_TXEN     28
-#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_RXEN     29
-#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_CLEAR   30
-#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START   31
-
-#define NRF51_PPI_CH_FIRST NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN
-#define NRF51_PPI_CH_LAST  NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START
-
-
-/* These will be defined in their respective functions if/when they are used. */
-#define NRF51_SPI0_BASE       0x40003000
-#define NRF51_SPI0_PSELSCK    REG32(NRF51_SPI0_BASE + 0x508)
-#define NRF51_SPI0_PSELMOSI   REG32(NRF51_SPI0_BASE + 0x50C)
-#define NRF51_SPI0_PSELMISO   REG32(NRF51_SPI0_BASE + 0x510)
-#define NRF51_SPI1_BASE       0x40004000
-#define NRF51_SPI1_PSELSCK    REG32(NRF51_SPI1_BASE + 0x508)
-#define NRF51_SPI1_PSELMOSI   REG32(NRF51_SPI1_BASE + 0x50C)
-#define NRF51_SPI1_PSELMISO   REG32(NRF51_SPI1_BASE + 0x510)
-#define NRF51_SPIS1_BASE      0x40004000
-#define NRF51_SPIS1_PSELSCK   REG32(NRF51_SPIS1_BASE + 0x508)
-#define NRF51_SPIS1_PSELMISO  REG32(NRF51_SPIS1_BASE + 0x50C)
-#define NRF51_SPIS1_PSELMOSI  REG32(NRF51_SPIS1_BASE + 0x510)
-#define NRF51_SPIS1_PSELCSN   REG32(NRF51_SPIS1_BASE + 0x514)
-#define NRF51_QDEC_BASE       0x40012000
-#define NRF51_QDEC_PSELLED    REG32(NRF51_QDEC_BASE + 0x51C)
-#define NRF51_QDEC_PSELA      REG32(NRF51_QDEC_BASE + 0x520)
-#define NRF51_QDEC_PSELB      REG32(NRF51_QDEC_BASE + 0x524)
-#define NRF51_LPCOMP_BASE     0x40013000
-#define NRF51_LPCOMP_PSEL     REG32(NRF51_LPCOMP_BASE + 0x504)
-
-#endif /* __CROS_EC_REGISTERS_H */
-
diff --git a/chip/nrf51/system.c b/chip/nrf51/system.c
deleted file mode 100644
index dc7bff2059..0000000000
--- a/chip/nrf51/system.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : hardware specific implementation */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "cpu.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-const char *system_get_chip_vendor(void)
-{
-	return "nrf";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "nrf51822";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* chip specific standby mode */
-	CPRINTS("TODO: implement %s()", __func__);
-}
-
-
-static void check_reset_cause(void)
-{
-	uint32_t flags = 0;
-	uint32_t raw_cause = NRF51_POWER_RESETREAS;
-
-	if (raw_cause & NRF51_POWER_RESETREAS_RESETPIN)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-	if (raw_cause & NRF51_POWER_RESETREAS_DOG)
-		flags |= EC_RESET_FLAG_WATCHDOG;
-
-	/* Note that the programmer uses a soft reset in debug mode. */
-	if (raw_cause & NRF51_POWER_RESETREAS_SREQ)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (raw_cause & (NRF51_POWER_RESETREAS_OFF |
-			NRF51_POWER_RESETREAS_LPCOMP))
-		flags |= EC_RESET_FLAG_WAKE_PIN;
-
-	if (raw_cause & (NRF51_POWER_RESETREAS_LOCKUP |
-			NRF51_POWER_RESETREAS_DIF))
-		flags |= EC_RESET_FLAG_OTHER;
-
-	system_set_reset_flags(flags);
-
-	/* clear it by writing 1's */
-	NRF51_POWER_RESETREAS = raw_cause;
-}
-
-static void system_watchdog_reset(void)
-{
-	if (NRF51_WDT_TIMEOUT != 0) {
-		/* Hard reset the WDT */
-		NRF51_WDT_POWER = 0;
-		NRF51_WDT_POWER = 1;
-	}
-
-	/* NRF51_WDT_CONFIG_HALT_RUN breaks this */
-	NRF51_WDT_CONFIG = NRF51_WDT_CONFIG_SLEEP_RUN;
-
-	NRF51_WDT_RREN = NRF51_WDT_RREN_BIT(0);
-	NRF51_WDT_CRV = 3; /* @32KHz */
-	NRF51_WDT_START = 1;
-}
-
-void system_reset(int flags)
-{
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	if (flags & SYSTEM_RESET_HARD)
-		/* Ask the watchdog to trigger a hard reboot */
-		system_watchdog_reset();
-	else {
-		/* Use SYSRESETREQ to trigger a soft reboot */
-		CPU_NVIC_APINT = 0x05fa0004;
-	}
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void system_pre_init(void)
-{
-	check_reset_cause();
-}
diff --git a/chip/nrf51/uart.c b/chip/nrf51/uart.c
deleted file mode 100644
index 1f546a2b79..0000000000
--- a/chip/nrf51/uart.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USART driver for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-
-static int ever_sent;    /* if we ever sent byte to TXD? */
-static int init_done;    /* Initialization done? */
-static int should_stop;  /* Last TX control action */
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	disable_sleep(SLEEP_MASK_UART);
-	should_stop = 0;
-	NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT);
-	task_trigger_irq(NRF51_PERID_USART);
-}
-
-void uart_tx_stop(void)
-{
-	NRF51_UART_INTENCLR = BIT(NRF55_UART_TXDRDY_BIT);
-	should_stop = 1;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * nRF51 design is NOT tx-empty style. Instead, it is if a byte is
-	 * ever transmitted from TxD. This means NRF51_UART_TXDRDY is always
-	 * 0 after reset. So, we use 'ever_sent' to send the first byte.
-	 */
-	return NRF51_UART_TXDRDY || (!ever_sent);
-}
-
-int uart_rx_available(void)
-{
-	return NRF51_UART_RXDRDY;
-}
-
-void uart_tx_flush(void)
-{
-	while (!uart_tx_ready())
-		;
-}
-
-void uart_write_char(char c)
-{
-	ever_sent = 1;
-	NRF51_UART_TXDRDY = 0;
-	NRF51_UART_TXD = c;
-	NRF51_UART_STARTTX = 1;
-}
-
-int uart_read_char(void)
-{
-	NRF51_UART_RXDRDY = 0;
-	return NRF51_UART_RXD;
-}
-
-/* Interrupt handler for console USART */
-void uart_interrupt(void)
-{
-#ifndef CONFIG_UART_RX_DMA
-	/*
-	 * Read input FIFO until empty.  DMA-based receive does this from a
-	 * hook in the UART buffering module.
-	 */
-	uart_process_input();
-#endif
-
-	/* Fill output FIFO */
-	uart_process_output();
-
-#ifndef CONFIG_UART_TX_DMA
-	if (!should_stop)
-		NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT);
-#endif  /* CONFIG_UART_TX_DMA */
-
-}
-DECLARE_IRQ(NRF51_PERID_USART, uart_interrupt, 2);
-
-
-void uart_init(void)
-{
-	NRF51_UART_PSELTXD = NRF51_UART_TX_PIN;   /* GPIO Port for Tx */
-	NRF51_UART_PSELRXD = NRF51_UART_RX_PIN;   /* GPIO Port for Rx */
-	NRF51_UART_CONFIG = 0;    /* disable HW flow control, no parity bit */
-	NRF51_UART_BAUDRATE = 0x01d7e000;  /* 115200 */
-	NRF51_UART_ENABLE = 0x4;  /* Enable UART */
-
-	task_enable_irq(NRF51_PERID_USART);
-
-	NRF51_UART_INTENSET = BIT(NRF55_UART_RXDRDY_BIT);
-	NRF51_UART_STARTRX = 1;
-
-	init_done = 1;
-}
diff --git a/chip/nrf51/watchdog.c b/chip/nrf51/watchdog.c
deleted file mode 100644
index da947df48e..0000000000
--- a/chip/nrf51/watchdog.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "console.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-
-int watchdog_init(void)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c
deleted file mode 100644
index b0654132cd..0000000000
--- a/chip/stm32/adc-stm32f0.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-struct mutex adc_lock;
-
-struct adc_profile_t {
-	/* Register values. */
-	uint32_t cfgr1_reg;
-	uint32_t cfgr2_reg;
-	uint32_t smpr_reg;	/* Default Sampling Rate */
-	uint32_t ier_reg;
-	/* DMA config. */
-	const struct dma_option *dma_option;
-	/* Size of DMA buffer, in units of ADC_CH_COUNT. */
-	int dma_buffer_size;
-};
-
-#ifdef CONFIG_ADC_PROFILE_SINGLE
-static const struct dma_option dma_single = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
-	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT,
-};
-
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_13_5_CY
-#endif
-
-static const struct adc_profile_t profile = {
-	/* Sample all channels once using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD,
-	.cfgr2_reg = 0,
-	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
-	.ier_reg = 0,
-	.dma_option = &dma_single,
-	.dma_buffer_size = 1,
-};
-#endif
-
-#ifdef CONFIG_ADC_PROFILE_FAST_CONTINUOUS
-
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_1_5_CY
-#endif
-
-static const struct dma_option dma_continuous = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
-	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT |
-	STM32_DMA_CCR_CIRC,
-};
-
-static const struct adc_profile_t profile = {
-	/* Sample all channels continuously using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD |
-		     STM32_ADC_CFGR1_CONT |
-		     STM32_ADC_CFGR1_DMACFG,
-	.cfgr2_reg = 0,
-	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
-	/* Fire interrupt at end of sequence. */
-	.ier_reg = STM32_ADC_IER_EOSEQIE,
-	.dma_option = &dma_continuous,
-	/* Double-buffer our samples. */
-	.dma_buffer_size = 2,
-};
-#endif
-
-static void adc_init(const struct adc_t *adc)
-{
-	/*
-	 * If clock is already enabled, and ADC module is enabled
-	 * then this is a warm reboot and ADC is already initialized.
-	 */
-	if (STM32_RCC_APB2ENR & BIT(9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN))
-		return;
-
-	/* Enable ADC clock */
-	clock_enable_module(MODULE_ADC, 1);
-	/* check HSI14 in RCC ? ON by default */
-
-	/* ADC calibration (done with ADEN = 0) */
-	STM32_ADC_CR = STM32_ADC_CR_ADCAL; /* set ADCAL = 1, ADC off */
-	/* wait for the end of calibration */
-	while (STM32_ADC_CR & STM32_ADC_CR_ADCAL)
-		;
-
-	/* Single conversion, right aligned, 12-bit */
-	STM32_ADC_CFGR1 = profile.cfgr1_reg;
-	/* clock is ADCCLK (ADEN must be off when writing this reg) */
-	STM32_ADC_CFGR2 = profile.cfgr2_reg;
-
-	/*
-	 * ADC enable (note: takes 4 ADC clocks between end of calibration
-	 * and setting ADEN).
-	 */
-	STM32_ADC_CR = STM32_ADC_CR_ADEN;
-	while (!(STM32_ADC_ISR & STM32_ADC_ISR_ADRDY))
-		STM32_ADC_CR = STM32_ADC_CR_ADEN;
-}
-
-static void adc_configure(int ain_id, enum stm32_adc_smpr sample_rate)
-{
-	/* Sampling time */
-	if (sample_rate == STM32_ADC_SMPR_DEFAULT ||
-			sample_rate >= STM32_ADC_SMPR_COUNT)
-		STM32_ADC_SMPR = profile.smpr_reg;
-	else
-		STM32_ADC_SMPR = STM32_ADC_SMPR_SMP(sample_rate);
-
-	/* Select channel to convert */
-	STM32_ADC_CHSELR = BIT(ain_id);
-
-	/* Disable DMA */
-	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_DMAEN;
-}
-
-#ifdef CONFIG_ADC_WATCHDOG
-
-static int watchdog_ain_id;
-static int watchdog_delay_ms;
-
-static void adc_continuous_read(int ain_id)
-{
-	adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT);
-
-	/* CONT=1 -> continuous mode on */
-	STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_CONT;
-
-	/* Start continuous conversion */
-	STM32_ADC_CR |= BIT(2); /* ADSTART */
-}
-
-static void adc_continuous_stop(void)
-{
-	/* Stop on-going conversion */
-	STM32_ADC_CR |= BIT(4); /* ADSTP */
-
-	/* Wait for conversion to stop */
-	while (STM32_ADC_CR & BIT(4))
-		;
-
-	/* CONT=0 -> continuous mode off */
-	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_CONT;
-}
-
-static void adc_interval_read(int ain_id, int interval_ms)
-{
-	adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT);
-
-	/* EXTEN=01 -> hardware trigger detection on rising edge */
-	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK)
-		| STM32_ADC_CFGR1_EXTEN_RISE;
-
-	/* EXTSEL=TRG3 -> Trigger on TIM3_TRGO */
-	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_TRG_MASK) |
-		STM32_ADC_CFGR1_TRG3;
-
-	__hw_timer_enable_clock(TIM_ADC, 1);
-
-	/* Upcounter, counter disabled, update event only on underflow */
-	STM32_TIM_CR1(TIM_ADC) = 0x0004;
-
-	/* TRGO on update event */
-	STM32_TIM_CR2(TIM_ADC) = 0x0020;
-	STM32_TIM_SMCR(TIM_ADC) = 0x0000;
-
-	/* Auto-reload value */
-	STM32_TIM_ARR(TIM_ADC) = interval_ms & 0xffff;
-
-	/* Set prescaler to tick per millisecond */
-	STM32_TIM_PSC(TIM_ADC) = (clock_get_freq() / MSEC) - 1;
-
-	/* Start counting */
-	STM32_TIM_CR1(TIM_ADC) |= 1;
-
-	/* Start ADC conversion */
-	STM32_ADC_CR |= BIT(2); /* ADSTART */
-}
-
-static void adc_interval_stop(void)
-{
-	/* EXTEN=00 -> hardware trigger detection disabled */
-	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_EXTEN_MASK;
-
-	/* Set ADSTP to clear ADSTART */
-	STM32_ADC_CR |= BIT(4); /* ADSTP */
-
-	/* Wait for conversion to stop */
-	while (STM32_ADC_CR & BIT(4))
-		;
-
-	/* Stop the timer */
-	STM32_TIM_CR1(TIM_ADC) &= ~0x1;
-}
-
-static int adc_watchdog_enabled(void)
-{
-	return STM32_ADC_CFGR1 & STM32_ADC_CFGR1_AWDEN;
-}
-
-static int adc_enable_watchdog_no_lock(void)
-{
-	/* Select channel */
-	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_AWDCH_MASK) |
-			  (watchdog_ain_id << 26);
-	adc_configure(watchdog_ain_id, STM32_ADC_SMPR_DEFAULT);
-
-	/* Clear AWD interrupt flag */
-	STM32_ADC_ISR = 0x80;
-	/* Set Watchdog enable bit on a single channel */
-	STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_AWDEN | STM32_ADC_CFGR1_AWDSGL;
-	/* Enable interrupt */
-	STM32_ADC_IER |= STM32_ADC_IER_AWDIE;
-
-	if (watchdog_delay_ms)
-		adc_interval_read(watchdog_ain_id, watchdog_delay_ms);
-	else
-		adc_continuous_read(watchdog_ain_id);
-
-	return EC_SUCCESS;
-}
-
-int adc_enable_watchdog(int ain_id, int high, int low)
-{
-	int ret;
-
-	mutex_lock(&adc_lock);
-
-	watchdog_ain_id = ain_id;
-
-	/* Set thresholds */
-	STM32_ADC_TR = ((high & 0xfff) << 16) | (low & 0xfff);
-
-	ret = adc_enable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-	return ret;
-}
-
-static int adc_disable_watchdog_no_lock(void)
-{
-	if (watchdog_delay_ms)
-		adc_interval_stop();
-	else
-		adc_continuous_stop();
-
-	/* Clear Watchdog enable bit */
-	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_AWDEN;
-
-	return EC_SUCCESS;
-}
-
-int adc_disable_watchdog(void)
-{
-	int ret;
-
-	mutex_lock(&adc_lock);
-	ret = adc_disable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-
-	return ret;
-}
-
-int adc_set_watchdog_delay(int delay_ms)
-{
-	int resume_watchdog = 0;
-
-	mutex_lock(&adc_lock);
-	if (adc_watchdog_enabled()) {
-		resume_watchdog = 1;
-		adc_disable_watchdog_no_lock();
-	}
-
-	watchdog_delay_ms = delay_ms;
-
-	if (resume_watchdog)
-		adc_enable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-
-	return EC_SUCCESS;
-}
-
-#else /* CONFIG_ADC_WATCHDOG */
-
-static int adc_watchdog_enabled(void) { return 0; }
-static int adc_enable_watchdog_no_lock(void) { return 0; }
-static int adc_disable_watchdog_no_lock(void) { return 0; }
-
-#endif /* CONFIG_ADC_WATCHDOG */
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-	int restore_watchdog = 0;
-
-	mutex_lock(&adc_lock);
-
-	adc_init(adc);
-
-	if (adc_watchdog_enabled()) {
-		restore_watchdog = 1;
-		adc_disable_watchdog_no_lock();
-	}
-
-	adc_configure(adc->channel, adc->sample_rate);
-
-	/* Clear flags */
-	STM32_ADC_ISR = 0xe;
-
-	/* Start conversion */
-	STM32_ADC_CR |= BIT(2); /* ADSTART */
-
-	/* Wait for end of conversion */
-	while (!(STM32_ADC_ISR & BIT(2)))
-		;
-	/* read converted value */
-	value = STM32_ADC_DR;
-
-	if (restore_watchdog)
-		adc_enable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-
-	return value * adc->factor_mul / adc->factor_div + adc->shift;
-}
-
-void adc_disable(void)
-{
-	STM32_ADC_CR |= STM32_ADC_CR_ADDIS;
-	/*
-	 * Note that the ADC is not in OFF state immediately.
-	 * Once the ADC is effectively put into OFF state,
-	 * STM32_ADC_CR_ADDIS bit will be cleared by hardware.
-	 */
-}
diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c
deleted file mode 100644
index 543a44ab1a..0000000000
--- a/chip/stm32/adc-stm32f3.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
-
-#define SMPR1_EXPAND(v) ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | \
-			 ((v) << 12) | ((v) << 15) | ((v) << 18) | \
-			 ((v) << 21))
-#define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27))
-
-/* Default ADC sample time = 13.5 cycles */
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME 2
-#endif
-
-struct mutex adc_lock;
-
-static int watchdog_ain_id;
-
-static inline void adc_set_channel(int sample_id, int channel)
-{
-	uint32_t mask, val;
-	volatile uint32_t *sqr_reg;
-
-	if (sample_id < 6) {
-		mask = 0x1f << (sample_id * 5);
-		val = channel << (sample_id * 5);
-		sqr_reg = &STM32_ADC_SQR3;
-	} else if (sample_id < 12) {
-		mask = 0x1f << ((sample_id - 6) * 5);
-		val = channel << ((sample_id - 6) * 5);
-		sqr_reg = &STM32_ADC_SQR2;
-	} else {
-		mask = 0x1f << ((sample_id - 12) * 5);
-		val = channel << ((sample_id - 12) * 5);
-		sqr_reg = &STM32_ADC_SQR1;
-	}
-
-	*sqr_reg = (*sqr_reg & ~mask) | val;
-}
-
-static void adc_configure(int ain_id)
-{
-	/* Set ADC channel */
-	adc_set_channel(0, ain_id);
-
-	/* Disable DMA */
-	STM32_ADC_CR2 &= ~BIT(8);
-
-	/* Disable scan mode */
-	STM32_ADC_CR1 &= ~BIT(8);
-}
-
-static void __attribute__((unused)) adc_configure_all(void)
-{
-	int i;
-
-	/* Set ADC channels */
-	STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20;
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		adc_set_channel(i, adc_channels[i].channel);
-
-	/* Enable DMA */
-	STM32_ADC_CR2 |= BIT(8);
-
-	/* Enable scan mode */
-	STM32_ADC_CR1 |= BIT(8);
-}
-
-static inline int adc_powered(void)
-{
-	return STM32_ADC_CR2 & BIT(0);
-}
-
-static inline int adc_conversion_ended(void)
-{
-	return STM32_ADC_SR & BIT(1);
-}
-
-static int adc_watchdog_enabled(void)
-{
-	return STM32_ADC_CR1 & BIT(23);
-}
-
-static int adc_enable_watchdog_no_lock(void)
-{
-	/* Fail if watchdog already enabled */
-	if (adc_watchdog_enabled())
-		return EC_ERROR_UNKNOWN;
-
-	/* Set channel */
-	STM32_ADC_SQR3 = watchdog_ain_id;
-	STM32_ADC_SQR1 = 0;
-	STM32_ADC_CR1 = (STM32_ADC_CR1 & ~0x1f) | watchdog_ain_id;
-
-	/* Clear interrupt bit */
-	STM32_ADC_SR &= ~0x1;
-
-	/* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */
-	STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23);
-
-	/* Disable DMA */
-	STM32_ADC_CR2 &= ~BIT(8);
-
-	/* CONT=1 */
-	STM32_ADC_CR2 |= BIT(1);
-
-	/* Start conversion */
-	STM32_ADC_CR2 |= BIT(0);
-
-	return EC_SUCCESS;
-}
-
-int adc_enable_watchdog(int ain_id, int high, int low)
-{
-	int ret;
-
-	if (!adc_powered())
-		return EC_ERROR_UNKNOWN;
-
-	mutex_lock(&adc_lock);
-
-	watchdog_ain_id = ain_id;
-
-	/* Set thresholds */
-	STM32_ADC_HTR = high & 0xfff;
-	STM32_ADC_LTR = low & 0xfff;
-
-	ret = adc_enable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-	return ret;
-}
-
-static int adc_disable_watchdog_no_lock(void)
-{
-	/* Fail if watchdog not running */
-	if (!adc_watchdog_enabled())
-		return EC_ERROR_UNKNOWN;
-
-	/* AWDEN=0, AWDIE=0 */
-	STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6);
-
-	/* CONT=0 */
-	STM32_ADC_CR2 &= ~BIT(1);
-
-	return EC_SUCCESS;
-}
-
-int adc_disable_watchdog(void)
-{
-	int ret;
-
-	if (!adc_powered())
-		return EC_ERROR_UNKNOWN;
-
-	mutex_lock(&adc_lock);
-	ret = adc_disable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-	return ret;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-	int restore_watchdog = 0;
-	timestamp_t deadline;
-
-	if (!adc_powered())
-		return EC_ERROR_UNKNOWN;
-
-	mutex_lock(&adc_lock);
-
-	if (adc_watchdog_enabled()) {
-		restore_watchdog = 1;
-		adc_disable_watchdog_no_lock();
-	}
-
-	adc_configure(adc->channel);
-
-	/* Clear EOC bit */
-	STM32_ADC_SR &= ~BIT(1);
-
-	/* Start conversion (Note: For now only confirmed on F4) */
-#if defined(CHIP_FAMILY_STM32F4)
-	STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART;
-#else
-	STM32_ADC_CR2 |= STM32_ADC_CR2_ADON;
-#endif
-
-	/* Wait for EOC bit set */
-	deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT;
-	value = ADC_READ_ERROR;
-	do {
-		if (adc_conversion_ended()) {
-			value = STM32_ADC_DR & ADC_READ_MAX;
-			break;
-		}
-	} while (!timestamp_expired(deadline, NULL));
-
-	if (restore_watchdog)
-		adc_enable_watchdog_no_lock();
-
-	mutex_unlock(&adc_lock);
-	return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
-	       value * adc->factor_mul / adc->factor_div + adc->shift;
-}
-
-static void adc_init(void)
-{
-	/*
-	 * Enable ADC clock.
-	 * APB2 clock is 16MHz. ADC clock prescaler is /2.
-	 * So the ADC clock is 8MHz.
-	 */
-	clock_enable_module(MODULE_ADC, 1);
-
-	/*
-	 * ADC clock is divided with respect to AHB, so no delay needed
-	 * here. If ADC clock is the same as AHB, a read on ADC
-	 * register is needed here.
-	 */
-
-	if (!adc_powered()) {
-		/* Power on ADC module */
-		STM32_ADC_CR2 |= STM32_ADC_CR2_ADON;
-
-		/* Reset calibration */
-		STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL;
-		while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL)
-			;
-
-		/* A/D Calibrate */
-		STM32_ADC_CR2 |= STM32_ADC_CR2_CAL;
-		while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL)
-			;
-	}
-
-	/* Set right alignment */
-	STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN;
-
-	/* Set sample time of all channels */
-	STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME);
-	STM32_ADC_SMPR2 = SMPR2_EXPAND(CONFIG_ADC_SAMPLE_TIME);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c
deleted file mode 120000
index 5e375b9dbf..0000000000
--- a/chip/stm32/adc-stm32f4.c
+++ /dev/null
@@ -1 +0,0 @@
-adc-stm32f3.c
\ No newline at end of file
diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c
deleted file mode 100644
index c1f1cfae4a..0000000000
--- a/chip/stm32/adc-stm32l.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "clock.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
-
-struct mutex adc_lock;
-
-static int restore_clock;
-
-static inline void adc_set_channel(int sample_id, int channel)
-{
-	uint32_t mask, val;
-	volatile uint32_t *sqr_reg;
-	int reg_id;
-
-	reg_id = 5 - sample_id / 6;
-
-	mask = 0x1f << ((sample_id % 6) * 5);
-	val = channel << ((sample_id % 6) * 5);
-	sqr_reg = &STM32_ADC_SQR(reg_id);
-
-	*sqr_reg = (*sqr_reg & ~mask) | val;
-}
-
-static void adc_configure(int ain_id)
-{
-	/* Set ADC channel */
-	adc_set_channel(0, ain_id);
-
-	/* Disable DMA */
-	STM32_ADC_CR2 &= ~BIT(8);
-
-	/* Disable scan mode */
-	STM32_ADC_CR1 &= ~BIT(8);
-}
-
-static void adc_configure_all(void)
-{
-	int i;
-
-	/* Set ADC channels */
-	STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20;
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		adc_set_channel(i, adc_channels[i].channel);
-
-	/* Enable DMA */
-	STM32_ADC_CR2 |= BIT(8);
-
-	/* Enable scan mode */
-	STM32_ADC_CR1 |= BIT(8);
-}
-
-static inline int adc_powered(void)
-{
-	return STM32_ADC_SR & BIT(6); /* ADONS */
-}
-
-static void adc_enable_clock(void)
-{
-	STM32_RCC_APB2ENR |= BIT(9);
-	/* ADCCLK = HSI / 2 = 8MHz*/
-	STM32_ADC_CCR |= BIT(16);
-}
-
-static void adc_init(void)
-{
-	/*
-	 * For STM32L, ADC clock source is HSI/2 = 8 MHz. HSI must be enabled
-	 * for ADC.
-	 *
-	 * Note that we are not powering on ADC on EC initialization because
-	 * STM32L ADC module requires HSI clock. Instead, ADC module is powered
-	 * on/off in adc_prepare()/adc_release().
-	 */
-
-	/* Enable ADC clock. */
-	adc_enable_clock();
-
-	if (!adc_powered())
-		/* Power on ADC module */
-		STM32_ADC_CR2 |= BIT(0);  /* ADON */
-
-	/* Set right alignment */
-	STM32_ADC_CR2 &= ~BIT(11);
-
-	/*
-	 * Set sample time of all channels to 16 cycles.
-	 * Conversion takes (12+16)/8M = 3.34 us.
-	 */
-	STM32_ADC_SMPR1 = 0x24924892;
-	STM32_ADC_SMPR2 = 0x24924892;
-	STM32_ADC_SMPR3 = 0x24924892;
-}
-
-static void adc_prepare(void)
-{
-	if (!adc_powered()) {
-		clock_enable_module(MODULE_ADC, 1);
-		adc_init();
-		restore_clock = 1;
-	}
-}
-
-static void adc_release(void)
-{
-	if (restore_clock) {
-		clock_enable_module(MODULE_ADC, 0);
-		restore_clock = 0;
-	}
-
-	/*
-	 * Power down the ADC.  The ADC consumes a non-trivial amount of power,
-	 * so it's wasteful to leave it on.
-	 */
-	if (adc_powered())
-		STM32_ADC_CR2 = 0;
-}
-
-static inline int adc_conversion_ended(void)
-{
-	return STM32_ADC_SR & BIT(1);
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-	timestamp_t deadline;
-
-	mutex_lock(&adc_lock);
-
-	adc_prepare();
-
-	adc_configure(adc->channel);
-
-	/* Clear EOC bit */
-	STM32_ADC_SR &= ~BIT(1);
-
-	/* Start conversion */
-	STM32_ADC_CR2 |= BIT(30); /* SWSTART */
-
-	/* Wait for EOC bit set */
-	deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT;
-	value = ADC_READ_ERROR;
-	do {
-		if (adc_conversion_ended()) {
-			value = STM32_ADC_DR & ADC_READ_MAX;
-			break;
-		}
-	} while (!timestamp_expired(deadline, NULL));
-
-	adc_release();
-
-	mutex_unlock(&adc_lock);
-	return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
-	       value * adc->factor_mul / adc->factor_div + adc->shift;
-}
diff --git a/chip/stm32/adc-stm32l4.c b/chip/stm32/adc-stm32l4.c
deleted file mode 100644
index 8609d44f5d..0000000000
--- a/chip/stm32/adc-stm32l4.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-struct mutex adc_lock;
-
-struct adc_profile_t {
-	/* Register values. */
-	uint32_t cfgr1_reg;
-	uint32_t cfgr2_reg;
-	uint32_t smpr_reg;	/* Default Sampling Rate */
-	uint32_t ier_reg;
-	/* DMA config. */
-	const struct dma_option *dma_option;
-	/* Size of DMA buffer, in units of ADC_CH_COUNT. */
-	int dma_buffer_size;
-};
-
-#ifdef CONFIG_ADC_PROFILE_SINGLE
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_12_5_CY
-#endif
-#endif
-
-#if defined(CHIP_FAMILY_STM32L4)
-#define ADC_CALIBRATION_TIMEOUT_US	100000U
-#define ADC_ENABLE_TIMEOUT_US		200000U
-#define ADC_CONVERSION_TIMEOUT_US	200000U
-
-#define NUMBER_OF_ADC_CHANNEL   2
-uint8_t adc1_initialized;
-#endif
-
-#ifdef CONFIG_ADC_PROFILE_FAST_CONTINUOUS
-
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_1_5_CY
-#endif
-
-static const struct dma_option dma_continuous = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
-	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT |
-	STM32_DMA_CCR_CIRC,
-};
-
-static const struct adc_profile_t profile = {
-	/* Sample all channels continuously using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD |
-		     STM32_ADC_CFGR1_CONT |
-		     STM32_ADC_CFGR1_DMACFG,
-	.cfgr2_reg = 0,
-	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
-	/* Fire interrupt at end of sequence. */
-	.ier_reg = STM32_ADC_IER_EOSEQIE,
-	.dma_option = &dma_continuous,
-	/* Double-buffer our samples. */
-	.dma_buffer_size = 2,
-};
-#endif
-
-static void adc_init(const struct adc_t *adc)
-{
-	/*
-	 * If clock is already enabled, and ADC module is enabled
-	 * then this is a warm reboot and ADC is already initialized.
-	 */
-
-	if (STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_ADCEN &&
-	    (STM32_ADC1_CR & STM32_ADC1_CR_ADEN))
-		return;
-
-	/* Enable ADC clock */
-	clock_enable_module(MODULE_ADC, 1);
-
-	/* set ADC clock to 20MHz */
-	STM32_ADC1_CCR &= ~0x003C0000;
-	STM32_ADC1_CCR |=  0x00080000;
-
-	STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOA;
-	STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOB;
-
-	/* Set ADC data resolution */
-	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_CONT;
-	/* Set ADC conversion data alignment */
-	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_ALIGN;
-	/* Set ADC delayed conversion mode */
-	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_AUTDLY;
-}
-
-static void adc_configure(int ain_id, int ain_rank,
-		enum stm32_adc_smpr sample_rate)
-{
-	/* Select Sampling time and channel to convert */
-	if (ain_id <= 10)	{
-		STM32_ADC1_SMPR1 &= ~(7 << ((ain_id - 1) * 3));
-		STM32_ADC1_SMPR1 |= (sample_rate << ((ain_id - 1) * 3));
-	} else	{
-		STM32_ADC1_SMPR2 &= ~(7 << ((ain_id - 11) * 3));
-		STM32_ADC1_SMPR2 |= (sample_rate << ((ain_id - 11) * 3));
-	}
-
-	/* Setup Rank */
-	STM32_ADC1_JSQR &= ~(0x03);
-	STM32_ADC1_JSQR |= NUMBER_OF_ADC_CHANNEL - 1;
-
-	STM32_ADC1_JSQR &= ~(0x1F << (((ain_rank - 1) * 6) + 8));
-	STM32_ADC1_JSQR |= (ain_id << (((ain_rank - 1) * 6) + 8));
-
-	/* Disable DMA */
-	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_DMAEN;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-
-	int value = 0;
-	uint32_t wait_loop_index;
-
-	mutex_lock(&adc_lock);
-
-	if (adc1_initialized == 0) {
-		adc_init(adc);
-
-		/* Configure Injected Channel N */
-		for (uint8_t i = 0; i < NUMBER_OF_ADC_CHANNEL; i++) {
-			const struct adc_t *adc = adc_channels + i;
-
-			adc_configure(adc->channel, adc->rank,
-				      adc->sample_rate);
-		}
-
-		if ((STM32_ADC1_CR & STM32_ADC1_CR_ADEN) !=
-		    STM32_ADC1_CR_ADEN) {
-			/* Disable ADC deep power down (enabled by default after
-			 * reset state)
-			 */
-			STM32_ADC1_CR &= ~STM32_ADC1_CR_DEEPPWD;
-			/* Enable ADC internal voltage regulator */
-			STM32_ADC1_CR |= STM32_ADC1_CR_ADVREGEN;
-		}
-
-		/*
-		 * Delay for ADC internal voltage regulator stabilization.
-		 * Compute number of CPU cycles to wait for, from delay in us.
-		 *
-		 * Note: Variable divided by 2 to compensate partially
-		 * CPU processing cycles (depends on compilation optimization).
-		 *
-		 * Note: If system core clock frequency is below 200kHz, wait
-		 * time is only a few CPU processing cycles.
-		 */
-		wait_loop_index = ((20 * (80000000 / (100000 * 2))) / 10);
-		while (wait_loop_index-- != 0)
-			;
-
-		/* Run ADC self calibration */
-		STM32_ADC1_CR |= STM32_ADC1_CR_ADCAL;
-
-		/* wait for the end of calibration */
-		wait_loop_index = ((ADC_CALIBRATION_TIMEOUT_US *
-				(CPU_CLOCK / (100000 * 2))) / 10);
-		while (STM32_ADC1_CR & STM32_ADC1_CR_ADCAL) {
-			if (wait_loop_index-- == 0)
-				break;
-		}
-
-		/* Enable ADC */
-		STM32_ADC1_ISR |= STM32_ADC1_ISR_ADRDY;
-		STM32_ADC1_CR |= STM32_ADC1_CR_ADEN;
-		wait_loop_index = ((ADC_ENABLE_TIMEOUT_US *
-				(CPU_CLOCK / (100000 * 2))) / 10);
-		while (!(STM32_ADC1_ISR & STM32_ADC1_ISR_ADRDY)) {
-			wait_loop_index--;
-			if (wait_loop_index == 0)
-				break;
-		}
-
-		adc1_initialized = 1;
-	}
-
-	/* Start injected conversion */
-	STM32_ADC1_CR |= BIT(3); /* JADSTART */
-
-	/* Wait for end of injected conversion */
-	wait_loop_index = ((ADC_CONVERSION_TIMEOUT_US *
-			(CPU_CLOCK / (100000 * 2))) / 10);
-	while (!(STM32_ADC1_ISR & BIT(6))) {
-		if (wait_loop_index-- == 0)
-			break;
-	}
-
-	/* Clear JEOS bit */
-	STM32_ADC1_ISR |= BIT(6);
-
-	/* read converted value */
-	if (adc->rank == 1)
-		value = STM32_ADC1_JDR1;
-	if (adc->rank == 2)
-		value = STM32_ADC1_JDR2;
-
-	mutex_unlock(&adc_lock);
-
-	return value * adc->factor_mul / adc->factor_div + adc->shift;
-}
-
-void adc_disable(void)
-{
-	/* Disable ADC */
-	/* Do not Set ADDIS when ADC is disabled */
-	adc1_initialized = 0;
-
-	if (STM32_ADC1_CR & STM32_ADC1_CR_ADEN)
-		STM32_ADC1_CR |= STM32_ADC1_CR_ADDIS;
-
-	/*
-	 * Note that the ADC is not in OFF state immediately.
-	 * Once the ADC is effectively put into OFF state,
-	 * STM32_ADC_CR_ADDIS bit will be cleared by hardware.
-	 */
-}
diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h
deleted file mode 100644
index 7e3c688c14..0000000000
--- a/chip/stm32/adc_chip.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-#ifdef CHIP_FAMILY_STM32L4
-enum stm32_adc_smpr {
-	STM32_ADC_SMPR_DEFAULT = 0,
-	STM32_ADC_SMPR_2_5_CY,
-	STM32_ADC_SMPR_6_5_CY,
-	STM32_ADC_SMPR_12_5_CY,
-	STM32_ADC_SMPR_24_5_CY,
-	STM32_ADC_SMPR_47_5_CY,
-	STM32_ADC_SMPR_92_5_CY,
-	STM32_ADC_SMPR_247_5_CY,
-	STM32_ADC_SMPR_640_5_CY,
-	STM32_ADC_SMPR_COUNT,
-};
-#else
-enum stm32_adc_smpr {
-	STM32_ADC_SMPR_DEFAULT = 0,
-	STM32_ADC_SMPR_1_5_CY,
-	STM32_ADC_SMPR_7_5_CY,
-	STM32_ADC_SMPR_13_5_CY,
-	STM32_ADC_SMPR_28_5_CY,
-	STM32_ADC_SMPR_41_5_CY,
-	STM32_ADC_SMPR_55_5_CY,
-	STM32_ADC_SMPR_71_5_CY,
-	STM32_ADC_SMPR_239_5_CY,
-	STM32_ADC_SMPR_COUNT,
-};
-#endif
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-#ifdef CHIP_FAMILY_STM32L4
-	int rank;
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-	enum stm32_adc_smpr sample_rate;  /* Sampling Rate of the channel */
-#endif
-};
-
-/* Disable ADC module when we don't need it anymore. */
-void adc_disable(void);
-
-/* Minimum and maximum values returned by adc_read_channel(). */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 4095
-
-/* Just plain id mapping for code readability */
-#define STM32_AIN(x) (x)
-
-/* Add for ADCs with RANK */
-#define STM32_RANK(x) (x)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/stm32/bkpdata.c b/chip/stm32/bkpdata.c
deleted file mode 100644
index 8c85366857..0000000000
--- a/chip/stm32/bkpdata.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <assert.h>
-
-#include "bkpdata.h"
-#include "registers.h"
-#include "system.h" /* enum system_bbram_idx */
-#include "task.h"
-
-uint16_t bkpdata_read(enum bkpdata_index index)
-{
-	if (index < 0 || index >= STM32_BKP_ENTRIES)
-		return 0;
-
-	if (index & 1)
-		return STM32_BKP_DATA(index >> 1) >> 16;
-	else
-		return STM32_BKP_DATA(index >> 1) & 0xFFFF;
-}
-
-int bkpdata_write(enum bkpdata_index index, uint16_t value)
-{
-	static struct mutex bkpdata_write_mutex;
-	int use_mutex = !in_interrupt_context();
-
-	if (index < 0 || index >= STM32_BKP_ENTRIES)
-		return EC_ERROR_INVAL;
-
-	/*
-	 * Two entries share a single 32-bit register, lock mutex to prevent
-	 * read/mask/write races.
-	 */
-	if (use_mutex)
-		mutex_lock(&bkpdata_write_mutex);
-	if (index & 1) {
-		uint32_t val = STM32_BKP_DATA(index >> 1);
-		val = (val & 0x0000FFFF) | (value << 16);
-		STM32_BKP_DATA(index >> 1) = val;
-	} else {
-		uint32_t val = STM32_BKP_DATA(index >> 1);
-		val = (val & 0xFFFF0000) | value;
-		STM32_BKP_DATA(index >> 1) = val;
-	}
-	if (use_mutex)
-		mutex_unlock(&bkpdata_write_mutex);
-
-	return EC_SUCCESS;
-}
-
-int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb)
-{
-	*msb = 0;
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	if (idx == SYSTEM_BBRAM_IDX_PD0)
-		return BKPDATA_INDEX_PD0;
-	if (idx == SYSTEM_BBRAM_IDX_PD1)
-		return BKPDATA_INDEX_PD1;
-	if (idx == SYSTEM_BBRAM_IDX_PD2)
-		return BKPDATA_INDEX_PD2;
-#endif
-	return -1;
-}
-
-uint32_t bkpdata_read_reset_flags()
-{
-	uint32_t flags = bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS);
-
-	flags |= bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS_2) << 16;
-
-	return flags;
-}
-
-__overridable
-void bkpdata_write_reset_flags(uint32_t save_flags)
-{
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff);
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, save_flags >> 16);
-}
diff --git a/chip/stm32/bkpdata.h b/chip/stm32/bkpdata.h
deleted file mode 100644
index 14bd3517cc..0000000000
--- a/chip/stm32/bkpdata.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Backup data functionality */
-
-#ifndef __CROS_EC_BKPDATA_H
-#define __CROS_EC_BKPDATA_H
-
-#include "common.h"
-#include "registers.h"
-#include "system.h" /* enum system_bbram_idx */
-
-/* We use 16-bit BKP / BBRAM entries. */
-#define STM32_BKP_ENTRIES (STM32_BKP_BYTES / 2)
-
-enum bkpdata_index {
-	BKPDATA_INDEX_SCRATCHPAD,	     /* General-purpose scratchpad */
-	BKPDATA_INDEX_SAVED_RESET_FLAGS,     /* Saved reset flags */
-	BKPDATA_INDEX_SAVED_RESET_FLAGS_2,   /* Saved reset flags (cont) */
-#ifdef CONFIG_SOFTWARE_PANIC
-	BKPDATA_INDEX_SAVED_PANIC_REASON,    /* Saved panic reason */
-	BKPDATA_INDEX_SAVED_PANIC_INFO,      /* Saved panic data */
-	BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, /* Saved panic exception code */
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	BKPDATA_INDEX_PD0,		     /* USB-PD saved port0 state */
-	BKPDATA_INDEX_PD1,		     /* USB-PD saved port1 state */
-	BKPDATA_INDEX_PD2,		     /* USB-PD saved port2 state */
-#endif
-#ifdef CONFIG_SOFTWARE_PANIC
-	/**
-	 * Saving the panic flags in case that AP thinks the panic is new
-	 * after a hard reset.
-	 */
-	BKPDATA_INDEX_SAVED_PANIC_FLAGS,     /* Saved panic flags */
-#endif
-	BKPDATA_COUNT
-};
-BUILD_ASSERT(STM32_BKP_ENTRIES >= BKPDATA_COUNT);
-
-/**
- * Read backup register at specified index.
- *
- * @return The value of the register or 0 if invalid index.
- */
-uint16_t bkpdata_read(enum bkpdata_index index);
-
-/**
- * Write hibernate register at specified index.
- *
- * @return nonzero if error.
- */
-int bkpdata_write(enum bkpdata_index index, uint16_t value);
-
-int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb);
-uint32_t bkpdata_read_reset_flags(void);
-void bkpdata_write_reset_flags(uint32_t save_flags);
-
-#endif /* __CROS_EC_BKPDATA_H */
diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
deleted file mode 100644
index 6817a3647d..0000000000
--- a/chip/stm32/build.mk
+++ /dev/null
@@ -1,106 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# STM32 chip specific files build
-#
-
-ifeq ($(CHIP_FAMILY),stm32f0)
-# STM32F0xx sub-family has a Cortex-M0 ARM core
-CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
-else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4 \
-stm32g4))
-# STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7))
-# STM32FH7xx family has a Cortex-M7 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set (identical to M7)
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32l5))
-# STM32FL5xx family has a Cortex-M33 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M33 instruction set
-CFLAGS_CPU+=-march=armv8-m.main+dsp -mcpu=cortex-m33
-else
-# other STM32 SoCs have a Cortex-M3 ARM core
-CORE:=cortex-m
-# Force Cortex-M3 subset of instructions
-CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
-endif
-
-# Select between 16-bit and 32-bit timer for clock source
-TIMER_TYPE=$(if $(CONFIG_STM_HWTIMER32),32,)
-DMA_TYPE=$(if $(CHIP_FAMILY_STM32F4)$(CHIP_FAMILY_STM32H7),-stm32f4,)
-SPI_TYPE=$(if $(CHIP_FAMILY_STM32H7),-stm32h7,)
-
-chip-$(CONFIG_DMA)+=dma$(DMA_TYPE).o
-chip-$(CONFIG_COMMON_RUNTIME)+=bkpdata.o system.o
-chip-y+=clock-$(CHIP_FAMILY).o
-ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f0 stm32f3 stm32f4))
-chip-y+=clock-f.o
-endif
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_SPI_CONTROLLER)+=spi_master$(SPI_TYPE).o
-chip-$(CONFIG_COMMON_GPIO)+=gpio.o gpio-$(CHIP_FAMILY).o
-chip-$(CONFIG_COMMON_TIMER)+=hwtimer$(TIMER_TYPE).o
-chip-$(CONFIG_I2C)+=i2c-$(CHIP_FAMILY).o
-chip-$(CONFIG_ITE_FLASH_SUPPORT)+=i2c_ite_flash_support.o
-chip-$(CONFIG_STREAM_USART)+=usart.o usart-$(CHIP_FAMILY).o
-chip-$(CONFIG_STREAM_USART)+=usart_rx_interrupt-$(CHIP_FAMILY).o
-chip-$(CONFIG_STREAM_USART)+=usart_tx_interrupt.o
-chip-$(CONFIG_STREAM_USART)+=usart_rx_dma.o usart_tx_dma.o
-chip-$(CONFIG_USART_HOST_COMMAND)+=usart_host_command.o
-chip-$(CONFIG_CMD_USART_INFO)+=usart_info_command.o
-chip-$(HAS_TASK_CONSOLE)+=host_command_common.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-chip-$(HAS_TASK_CONSOLE)+=uart.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-chip-$(HAS_TASK_POWERLED)+=power_led.o
-ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32g4 stm32l4 stm32l5))
-# STM32G4, STM32L4 and STM32L5 use the same flash IP block
-chip-y+=flash-stm32g4-l4.o
-else
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash-$(CHIP_FAMILY).o
-endif
-ifdef CONFIG_FLASH_PHYSICAL
-chip-$(CHIP_FAMILY_STM32F0)+=flash-f.o
-chip-$(CHIP_FAMILY_STM32F3)+=flash-f.o
-chip-$(CHIP_FAMILY_STM32F4)+=flash-f.o
-endif
-chip-$(CONFIG_ADC)+=adc-$(CHIP_FAMILY).o
-chip-$(CONFIG_STM32_CHARGER_DETECT)+=charger_detect.o
-chip-$(CONFIG_DEBUG_PRINTF)+=debug_printf.o
-chip-$(CONFIG_OTP)+=otp-$(CHIP_FAMILY).o
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_RNG)+=trng.o
-
-ifeq ($(CHIP_FAMILY),stm32f4)
-chip-$(CONFIG_USB)+=usb_dwc.o usb_endpoints.o
-chip-$(CONFIG_USB_CONSOLE)+=usb_dwc_console.o
-chip-$(CONFIG_USB_POWER)+=usb_power.o
-chip-$(CONFIG_STREAM_USB)+=usb_dwc_stream.o
-else
-chip-$(CONFIG_STREAM_USB)+=usb-stream.o
-chip-$(CONFIG_USB)+=usb.o usb-$(CHIP_FAMILY).o usb_endpoints.o
-chip-$(CONFIG_USB_CONSOLE)+=usb_console.o
-chip-$(CONFIG_USB_GPIO)+=usb_gpio.o
-chip-$(CONFIG_USB_HID)+=usb_hid.o
-chip-$(CONFIG_USB_HID_KEYBOARD)+=usb_hid_keyboard.o
-chip-$(CONFIG_USB_HID_TOUCHPAD)+=usb_hid_touchpad.o
-chip-$(CONFIG_USB_ISOCHRONOUS)+=usb_isochronous.o
-chip-$(CONFIG_USB_PD_TCPC)+=usb_pd_phy.o
-chip-$(CONFIG_USB_SPI)+=usb_spi.o
-endif
-chip-$(CONFIG_USB_PD_TCPM_STM32GX)+=ucpd-stm32gx.o
diff --git a/chip/stm32/charger_detect.c b/chip/stm32/charger_detect.c
deleted file mode 100644
index b32b9f3ac0..0000000000
--- a/chip/stm32/charger_detect.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Detect what adapter is connected */
-
-#include "charge_manager.h"
-#include "hooks.h"
-#include "registers.h"
-#include "timer.h"
-
-static void enable_usb(void)
-{
-	/* Enable USB device clock. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
-}
-DECLARE_HOOK(HOOK_INIT, enable_usb, HOOK_PRIO_DEFAULT);
-
-static void disable_usb(void)
-{
-	/* Disable USB device clock. */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
-}
-DECLARE_HOOK(HOOK_SYSJUMP, disable_usb, HOOK_PRIO_DEFAULT);
-
-static uint16_t detect_type(uint16_t det_type)
-{
-	STM32_USB_BCDR &= 0;
-	usleep(1);
-	STM32_USB_BCDR |= (STM32_USB_BCDR_BCDEN | det_type);
-	usleep(1);
-	STM32_USB_BCDR &= ~(STM32_USB_BCDR_BCDEN | det_type);
-	return STM32_USB_BCDR;
-}
-
-
-int charger_detect_get_device_type(void)
-{
-	uint16_t pdet_result;
-
-	if (!(detect_type(STM32_USB_BCDR_DCDEN) & STM32_USB_BCDR_DCDET))
-		return CHARGE_SUPPLIER_PD;
-
-	pdet_result = detect_type(STM32_USB_BCDR_PDEN);
-	/* TODO: add support for detecting proprietary chargers. */
-	if (pdet_result & STM32_USB_BCDR_PDET) {
-		if (detect_type(STM32_USB_BCDR_SDEN) & STM32_USB_BCDR_SDET)
-			return CHARGE_SUPPLIER_BC12_DCP;
-		else
-			return CHARGE_SUPPLIER_BC12_CDP;
-	} else if (pdet_result & STM32_USB_BCDR_PS2DET)
-		return CHARGE_SUPPLIER_PROPRIETARY;
-	else
-		return CHARGE_SUPPLIER_BC12_SDP;
-}
diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c
deleted file mode 100644
index 1a77d8ad60..0000000000
--- a/chip/stm32/clock-f.c
+++ /dev/null
@@ -1,507 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "rtc.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/* Convert decimal to BCD */
-static uint8_t u8_to_bcd(uint8_t val)
-{
-	/* Fast division by 10 (when lacking HW div) */
-	uint32_t quot = ((uint32_t)val * 0xCCCD) >> 19;
-	uint32_t rem = val - quot * 10;
-
-	return rem | (quot << 4);
-}
-
-/* Convert between RTC regs in BCD and seconds */
-static uint32_t rtc_tr_to_sec(uint32_t rtc_tr)
-{
-	uint32_t sec;
-
-	/* convert the hours field */
-	sec = (((rtc_tr & 0x300000) >> 20) * 10 +
-	       ((rtc_tr & 0xf0000) >> 16)) * 3600;
-	/* convert the minutes field */
-	sec += (((rtc_tr & 0x7000) >> 12) * 10 + ((rtc_tr & 0xf00) >> 8)) * 60;
-	/* convert the seconds field */
-	sec += ((rtc_tr & 0x70) >> 4) * 10 + (rtc_tr & 0xf);
-	return sec;
-}
-
-static uint32_t sec_to_rtc_tr(uint32_t sec)
-{
-	uint32_t rtc_tr;
-	uint8_t hour;
-	uint8_t min;
-
-	sec %= SECS_PER_DAY;
-	/* convert the hours field */
-	hour = sec / 3600;
-	rtc_tr = u8_to_bcd(hour) << 16;
-	/* convert the minutes field */
-	sec -= hour * 3600;
-	min = sec / 60;
-	rtc_tr |= u8_to_bcd(min) << 8;
-	/* convert the seconds field */
-	sec -= min * 60;
-	rtc_tr |= u8_to_bcd(sec);
-
-	return rtc_tr;
-}
-
-/* Register setup before RTC alarm is allowed for update */
-static void pre_work_set_rtc_alarm(void)
-{
-	rtc_unlock_regs();
-
-	/* Make sure alarm is disabled */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF))
-		;
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
-}
-
-/* Register setup after RTC alarm is updated */
-static void post_work_set_rtc_alarm(void)
-{
-	STM32_EXTI_PR = EXTI_RTC_ALR_EVENT;
-
-	/* Enable alarm and alarm interrupt */
-	STM32_EXTI_IMR |= EXTI_RTC_ALR_EVENT;
-	STM32_RTC_CR |= STM32_RTC_CR_ALRAE;
-
-	rtc_lock_regs();
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static struct wake_time host_wake_time;
-
-int is_host_wake_alarm_expired(timestamp_t ts)
-{
-	return host_wake_time.ts.val &&
-	       timestamp_expired(host_wake_time.ts, &ts);
-}
-
-void restore_host_wake_alarm(void)
-{
-	if (!host_wake_time.ts.val)
-		return;
-
-	pre_work_set_rtc_alarm();
-
-	/* Set alarm time */
-	STM32_RTC_ALRMAR = host_wake_time.rtc_alrmar;
-
-	post_work_set_rtc_alarm();
-}
-
-static uint32_t rtc_dr_to_sec(uint32_t rtc_dr)
-{
-	struct calendar_date time;
-	uint32_t sec;
-
-	time.year = (((rtc_dr & 0xf00000) >> 20) * 10 +
-		    ((rtc_dr & 0xf0000) >> 16));
-	time.month = (((rtc_dr & 0x1000) >> 12) * 10 +
-		     ((rtc_dr & 0xf00) >> 8));
-	time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf);
-
-	sec = date_to_sec(time);
-
-	return sec;
-}
-
-static uint32_t sec_to_rtc_dr(uint32_t sec)
-{
-	struct calendar_date time;
-	uint32_t rtc_dr;
-
-	time = sec_to_date(sec);
-
-	rtc_dr = u8_to_bcd(time.year) << 16;
-	rtc_dr |= u8_to_bcd(time.month) << 8;
-	rtc_dr |= u8_to_bcd(time.day);
-
-	return rtc_dr;
-}
-#endif
-
-uint32_t rtc_to_sec(const struct rtc_time_reg *rtc)
-{
-	uint32_t sec = 0;
-#ifdef CONFIG_HOSTCMD_RTC
-	sec = rtc_dr_to_sec(rtc->rtc_dr);
-#endif
-	return sec + (rtcss_to_us(rtc->rtc_ssr) / SECOND) +
-	       rtc_tr_to_sec(rtc->rtc_tr);
-}
-
-void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc)
-{
-	rtc->rtc_dr = 0;
-#ifdef CONFIG_HOSTCMD_RTC
-	rtc->rtc_dr = sec_to_rtc_dr(sec);
-#endif
-	rtc->rtc_tr = sec_to_rtc_tr(sec);
-	rtc->rtc_ssr = 0;
-}
-
-/* Return sub-10-sec time diff between two rtc readings
- *
- * Note: this function assumes rtc0 was sampled before rtc1.
- * Additionally, this function only looks at the difference mod 10
- * seconds.
- */
-uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
-		      const struct rtc_time_reg *rtc1)
-{
-	uint32_t rtc0_val, rtc1_val, diff;
-
-	rtc0_val = (rtc0->rtc_tr & 0xF) * SECOND + rtcss_to_us(rtc0->rtc_ssr);
-	rtc1_val = (rtc1->rtc_tr & 0xF) * SECOND + rtcss_to_us(rtc1->rtc_ssr);
-	diff = rtc1_val;
-	if (rtc1_val < rtc0_val) {
-		/* rtc_ssr has wrapped, since we assume rtc0 < rtc1, add
-		 * 10 seconds to get the correct value
-		 */
-		diff += 10 * SECOND;
-	}
-	diff -= rtc0_val;
-	return diff;
-}
-
-void rtc_read(struct rtc_time_reg *rtc)
-{
-	/*
-	 * Read current time synchronously. Each register must be read
-	 * twice with identical values because glitches may occur for reads
-	 * close to the RTCCLK edge.
-	 */
-	do {
-		rtc->rtc_dr = STM32_RTC_DR;
-
-		do {
-			rtc->rtc_tr = STM32_RTC_TR;
-
-			do {
-				rtc->rtc_ssr = STM32_RTC_SSR;
-			} while (rtc->rtc_ssr != STM32_RTC_SSR);
-
-		} while (rtc->rtc_tr != STM32_RTC_TR);
-
-	} while (rtc->rtc_dr != STM32_RTC_DR);
-}
-
-void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
-		   struct rtc_time_reg *rtc, uint8_t save_alarm)
-{
-	uint32_t alarm_sec = 0;
-	uint32_t alarm_us = 0;
-
-	if (delay_s == EC_RTC_ALARM_CLEAR && !delay_us) {
-		reset_rtc_alarm(rtc);
-		return;
-	}
-
-	/* Alarm timeout must be within 1 day (86400 seconds) */
-	ASSERT((delay_s + delay_us / SECOND) < SECS_PER_DAY);
-
-	pre_work_set_rtc_alarm();
-	rtc_read(rtc);
-
-	/* Calculate alarm time */
-	alarm_sec = rtc_tr_to_sec(rtc->rtc_tr) + delay_s;
-
-	if (delay_us) {
-		alarm_us = rtcss_to_us(rtc->rtc_ssr) + delay_us;
-		alarm_sec = alarm_sec + alarm_us / SECOND;
-		alarm_us = alarm_us % SECOND;
-	}
-
-	/*
-	 * If seconds is greater than 1 day, subtract by 1 day to deal with
-	 * 24-hour rollover.
-	 */
-	if (alarm_sec >= SECS_PER_DAY)
-		alarm_sec -= SECS_PER_DAY;
-
-	/*
-	 * Set alarm time in seconds and check for match on
-	 * hours, minutes, and seconds.
-	 */
-	STM32_RTC_ALRMAR = sec_to_rtc_tr(alarm_sec) | 0xc0000000;
-
-	/*
-	 * Set alarm time in subseconds and check for match on subseconds.
-	 * If the caller doesn't specify subsecond delay (e.g. host command),
-	 * just align the alarm time to second.
-	 */
-	STM32_RTC_ALRMASSR = delay_us ?
-			     (us_to_rtcss(alarm_us) | 0x0f000000) : 0;
-
-#ifdef CONFIG_HOSTCMD_RTC
-	/*
-	 * If alarm is set by the host, preserve the wake time timestamp
-	 * and alarm registers.
-	 */
-	if (save_alarm) {
-		host_wake_time.ts.val = delay_s * SECOND + get_time().val;
-		host_wake_time.rtc_alrmar = STM32_RTC_ALRMAR;
-	}
-#endif
-	post_work_set_rtc_alarm();
-}
-
-uint32_t get_rtc_alarm(void)
-{
-	struct rtc_time_reg now;
-	uint32_t now_sec;
-	uint32_t alarm_sec;
-
-	if (!(STM32_RTC_CR & STM32_RTC_CR_ALRAE))
-		return 0;
-
-	rtc_read(&now);
-
-	now_sec = rtc_tr_to_sec(now.rtc_tr);
-	alarm_sec = rtc_tr_to_sec(STM32_RTC_ALRMAR & 0x3fffff);
-
-	return ((alarm_sec < now_sec) ? SECS_PER_DAY : 0) +
-	       (alarm_sec - now_sec);
-}
-
-void reset_rtc_alarm(struct rtc_time_reg *rtc)
-{
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
-
-	/* Disable RTC alarm interrupt */
-	STM32_EXTI_IMR &= ~EXTI_RTC_ALR_EVENT;
-	STM32_EXTI_PR = EXTI_RTC_ALR_EVENT;
-
-	/* Clear the pending RTC alarm IRQ in NVIC */
-	task_clear_pending_irq(STM32_IRQ_RTC_ALARM);
-
-	/* Read current time */
-	rtc_read(rtc);
-
-	rtc_lock_regs();
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-test_mockable
-void __rtc_alarm_irq(void)
-{
-	struct rtc_time_reg rtc;
-	reset_rtc_alarm(&rtc);
-
-#ifdef CONFIG_HOSTCMD_RTC
-	/* Wake up the host if there is a saved rtc wake alarm. */
-	if (host_wake_time.ts.val) {
-		host_wake_time.ts.val = 0;
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-	}
-#endif
-}
-DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
-
-__attribute__((weak))
-int clock_get_timer_freq(void)
-{
-	return clock_get_freq();
-}
-
-void clock_init(void)
-{
-	/*
-	 * The initial state :
-	 *  SYSCLK from HSI (=8MHz), no divider on AHB, APB1, APB2
-	 *  PLL unlocked, RTC enabled on LSE
-	 */
-
-	/*
-	 * put 1 Wait-State for flash access to ensure proper reads at 48Mhz
-	 * and enable prefetch buffer.
-	 */
-	STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN;
-
-#ifdef CHIP_FAMILY_STM32F4
-	/* Enable data and instruction cache. */
-	STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN;
-#endif
-
-	config_hispeed_clock();
-
-	rtc_init();
-}
-
-#ifdef CHIP_FAMILY_STM32F4
-void reset_flash_cache(void)
-{
-	/* Disable data and instruction cache. */
-	STM32_FLASH_ACR &= ~(STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN);
-
-	/* Reset data and instruction cache */
-	STM32_FLASH_ACR |= STM32_FLASH_ACR_DCRST | STM32_FLASH_ACR_ICRST;
-}
-DECLARE_HOOK(HOOK_SYSJUMP, reset_flash_cache, HOOK_PRIO_DEFAULT);
-#endif
-
-/*****************************************************************************/
-/* Console commands */
-
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t sec;
-	struct rtc_time_reg rtc;
-
-	rtc_read(&rtc);
-	sec = rtc_to_sec(&rtc);
-
-	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
-}
-
-#ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
-{
-	char *e;
-	uint32_t t;
-
-	if (argc == 3 && !strcasecmp(argv[1], "set")) {
-		t = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-		rtc_set(t);
-	} else if (argc > 1)
-		return EC_ERROR_INVAL;
-
-	print_system_rtc(CC_COMMAND);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-		"[set <seconds>]",
-		"Get/set real-time clock");
-
-#ifdef CONFIG_CMD_RTC_ALARM
-static int command_rtc_alarm_test(int argc, char **argv)
-{
-	int s = 1, us = 0;
-	struct rtc_time_reg rtc;
-	char *e;
-
-	ccprintf("Setting RTC alarm\n");
-
-	if (argc > 1) {
-		s = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-	}
-	if (argc > 2) {
-		us = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-	}
-
-	set_rtc_alarm(s, us, &rtc, 0);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-			"[seconds [microseconds]]",
-			"Test alarm");
-#endif /* CONFIG_CMD_RTC_ALARM */
-#endif /* CONFIG_CMD_RTC */
-
-/*****************************************************************************/
-/* Host commands */
-
-#ifdef CONFIG_HOSTCMD_RTC
-static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-	struct rtc_time_reg rtc;
-
-	rtc_read(&rtc);
-	r->time = rtc_to_sec(&rtc);
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		system_rtc_get_value,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	rtc_set(p->time);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		system_rtc_set_value,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
-{
-	struct rtc_time_reg rtc;
-	const struct ec_params_rtc *p = args->params;
-
-	/* Alarm timeout must be within 1 day (86400 seconds) */
-	if (p->time >= SECS_PER_DAY)
-		return EC_RES_INVALID_PARAM;
-
-	set_rtc_alarm(p->time, 0, &rtc, 1);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM,
-		system_rtc_set_alarm,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = get_rtc_alarm();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM,
-		system_rtc_get_alarm,
-		EC_VER_MASK(0));
-
-#endif /* CONFIG_HOSTCMD_RTC */
diff --git a/chip/stm32/clock-f.h b/chip/stm32/clock-f.h
deleted file mode 100644
index 4662b043cb..0000000000
--- a/chip/stm32/clock-f.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#ifndef __CROS_EC_CLOCK_F_H
-#define __CROS_EC_CLOCK_F_H
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Lock and unlock RTC write access */
-static inline void rtc_lock_regs(void)
-{
-	STM32_RTC_WPR = 0xff;
-}
-static inline void rtc_unlock_regs(void)
-{
-	STM32_RTC_WPR = 0xca;
-	STM32_RTC_WPR = 0x53;
-}
-
-struct rtc_time_reg {
-	uint32_t rtc_ssr; /* subseconds */
-	uint32_t rtc_tr; /* hours, minutes, seconds */
-	uint32_t rtc_dr; /* years, months, dates, week days */
-};
-
-/* Save the RTC alarm wake time */
-struct wake_time {
-	timestamp_t ts;
-	uint32_t rtc_alrmar; /* the value of register STM32_RTC_ALRMAR */
-};
-
-/* Convert between RTC regs in BCD and seconds */
-uint32_t rtc_to_sec(const struct rtc_time_reg *rtc);
-
-/* Convert between seconds and RTC regs */
-void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc);
-
-/* Calculate microseconds from rtc sub-second register. */
-int32_t rtcss_to_us(uint32_t rtcss);
-
-/* Calculate rtc sub-second register value from microseconds. */
-uint32_t us_to_rtcss(int32_t us);
-
-/* Return sub-10-sec time diff between two rtc readings */
-uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
-		      const struct rtc_time_reg *rtc1);
-
-/* Read RTC values */
-void rtc_read(struct rtc_time_reg *rtc);
-
-/* Set RTC value */
-void rtc_set(uint32_t sec);
-
-/* Set RTC wakeup, save alarm wakeup time when save_alarm != 0 */
-void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
-		   struct rtc_time_reg *rtc, uint8_t save_alarm);
-
-/* Clear RTC wakeup */
-void reset_rtc_alarm(struct rtc_time_reg *rtc);
-
-/*
- * Return the remaining seconds before the RTC alarm goes off.
- * Sub-seconds are ignored. Returns 0 if alarm is not set.
- */
-uint32_t get_rtc_alarm(void);
-
-/* RTC init */
-void rtc_init(void);
-
-/* Init clock blocks and functionality */
-void clock_init(void);
-
-/* Init high speed clock config */
-void config_hispeed_clock(void);
-
-/* Get timer clock frequency (for STM32 only) */
-int clock_get_timer_freq(void);
-
-/*
- * Return 1 if host_wake_time is nonzero and the saved host_wake_time
- * is expired at a given time, ts.
- */
-int is_host_wake_alarm_expired(timestamp_t ts);
-
-/* Set RTC wakeup based on the value saved in host_wake_time */
-void restore_host_wake_alarm(void);
-
-#endif  /* __CROS_EC_CLOCK_F_H */
diff --git a/chip/stm32/clock-l4.h b/chip/stm32/clock-l4.h
deleted file mode 100644
index d237b84580..0000000000
--- a/chip/stm32/clock-l4.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#ifndef __CROS_EC_CLOCK_L4_H
-#define __CROS_EC_CLOCK_L4_H
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define STM32L4_RTC_REQ 1000000
-#define STM32L4_LSI_CLOCK 32000
-
-/* Lock and unlock RTC write access */
-static inline void rtc_lock_regs(void)
-{
-	STM32_RTC_WPR = 0xff;
-}
-static inline void rtc_unlock_regs(void)
-{
-	STM32_RTC_WPR = 0xca;
-	STM32_RTC_WPR = 0x53;
-}
-
-struct rtc_time_reg {
-	uint32_t rtc_ssr; /* subseconds */
-	uint32_t rtc_tr; /* hours, minutes, seconds */
-	uint32_t rtc_dr; /* years, months, dates, week days */
-};
-
-/* Save the RTC alarm wake time */
-struct wake_time {
-	timestamp_t ts;
-	uint32_t rtc_alrmar; /* the value of register STM32_RTC_ALRMAR */
-};
-
-/* Convert between RTC regs in BCD and seconds */
-uint32_t rtc_to_sec(const struct rtc_time_reg *rtc);
-
-/* Convert between seconds and RTC regs */
-void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc);
-
-/* Calculate microseconds from rtc sub-second register. */
-uint32_t rtcss_to_us(uint32_t rtcss);
-
-/* Calculate rtc sub-second register value from microseconds. */
-uint32_t us_to_rtcss(uint32_t us);
-
-/* Return sub-10-sec time diff between two rtc readings */
-uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
-		      const struct rtc_time_reg *rtc1);
-
-/* Read RTC values */
-void rtc_read(struct rtc_time_reg *rtc);
-
-/* Set RTC value */
-void rtc_set(uint32_t sec);
-
-/* Set RTC wakeup, save alarm wakeup time when save_alarm != 0 */
-void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
-		   struct rtc_time_reg *rtc, uint8_t save_alarm);
-
-/* Clear RTC wakeup */
-void reset_rtc_alarm(struct rtc_time_reg *rtc);
-
-/*
- * Return the remaining seconds before the RTC alarm goes off.
- * Sub-seconds are ignored. Returns 0 if alarm is not set.
- */
-uint32_t get_rtc_alarm(void);
-
-/* RTC init */
-void rtc_init(void);
-
-/* Init clock blocks and functionality */
-void clock_init(void);
-
-/* Init high speed clock config */
-void config_hispeed_clock(void);
-
-/* Get timer clock frequency (for STM32 only) */
-int clock_get_timer_freq(void);
-
-/*
- * Return 1 if host_wake_time is nonzero and the saved host_wake_time
- * is expired at a given time, ts.
- */
-bool is_host_wake_alarm_expired(timestamp_t ts);
-
-/* Set RTC wakeup based on the value saved in host_wake_time */
-void restore_host_wake_alarm(void);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void low_power_init(void);
-#endif
-
-#endif  /* __CROS_EC_CLOCK_L4_H */
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c
deleted file mode 100644
index 0f63bdd394..0000000000
--- a/chip/stm32/clock-stm32f0.c
+++ /dev/null
@@ -1,503 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/* use 48Mhz USB-synchronized High-speed oscillator */
-#define HSI48_CLOCK 48000000
-
-/* use PLL at 38.4MHz as system clock. */
-#define PLL_CLOCK 38400000
-
-/* Low power idle statistics */
-#ifdef CONFIG_LOW_POWER_IDLE
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/*
- * minimum delay to enter stop mode
- *
- * STOP_MODE_LATENCY: max time to wake up from STOP mode with regulator in low
- * power mode is 5 us + PLL locking time is 200us.
- *
- * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
- * in the past, it will never wake up and cause a watchdog.
- * For STM32F3, we are using HSE, which requires additional time to start up.
- * Therefore, the latency for STM32F3 is set longer.
- *
- * RESTORE_HOST_ALARM_LATENCY: max latency between the deferred routine is
- * called and the host alarm is actually restored. In practice, the max latency
- * is measured as ~600us. 1000us should be conservative enough to guarantee
- * we won't miss the host alarm.
- */
-#ifdef CHIP_VARIANT_STM32F373
-#define STOP_MODE_LATENCY 500  /* us */
-#elif defined(CHIP_VARIANT_STM32F05X)
-#define STOP_MODE_LATENCY 300  /* us */
-#elif (CPU_CLOCK == PLL_CLOCK)
-#define STOP_MODE_LATENCY 300   /* us */
-#else
-#define STOP_MODE_LATENCY 50    /* us */
-#endif
-#define SET_RTC_MATCH_DELAY 200 /* us */
-
-#ifdef CONFIG_HOSTCMD_RTC
-#define RESTORE_HOST_ALARM_LATENCY 1000 /* us */
-#endif
-
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-/*
- * RTC clock frequency (By default connected to LSI clock)
- *
- * The LSI on any given chip can be between 30 kHz to 60 kHz.
- * Without calibration, LSI frequency may be off by as much as 50%.
- *
- * Set synchronous clock freq to (RTC clock source / 2) to maximize
- * subsecond resolution. Set asynchronous clock to 1 Hz.
- */
-
-#define RTC_PREDIV_A 1
-#ifdef CONFIG_STM32_CLOCK_LSE
-#define RTC_FREQ (32768 / (RTC_PREDIV_A + 1)) /* Hz */
-/* GCD(RTC_FREQ, 1000000) */
-#define RTC_GCD 64
-#else /* LSI clock, 40kHz-ish */
-#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */
-/* GCD(RTC_FREQ, 1000000) */
-#define RTC_GCD 20000
-#endif
-#define RTC_PREDIV_S (RTC_FREQ - 1)
-
-/*
- * There are (1000000 / RTC_FREQ) us per RTC tick, take GCD of both terms
- * for conversion calculations to fit in 32 bits.
- */
-#define US_GCD (1000000 / RTC_GCD)
-#define RTC_FREQ_GCD (RTC_FREQ / RTC_GCD)
-
-int32_t rtcss_to_us(uint32_t rtcss)
-{
-	return ((RTC_PREDIV_S - (rtcss & 0x7fff)) * US_GCD) / RTC_FREQ_GCD;
-}
-
-uint32_t us_to_rtcss(int32_t us)
-{
-	return RTC_PREDIV_S - us * RTC_FREQ_GCD / US_GCD;
-}
-
-void config_hispeed_clock(void)
-{
-#ifdef CHIP_FAMILY_STM32F3
-	/* Ensure that HSE is ON */
-	wait_for_ready(&STM32_RCC_CR, BIT(16), BIT(17));
-
-	/*
-	 * HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK
-	 * HCLK = SYSCLK, PCLK = HCLK / 2 = 24MHz
-	 * ADCCLK = PCLK / 6 = 4MHz
-	 * USB uses SYSCLK = 48MHz
-	 */
-	STM32_RCC_CFGR = 0x0041a400;
-
-	/* Enable the PLL */
-	STM32_RCC_CR |= 0x01000000;
-
-	/* Wait until the PLL is ready */
-	while (!(STM32_RCC_CR & 0x02000000))
-		;
-
-	/* Switch SYSCLK to PLL */
-	STM32_RCC_CFGR |= 0x2;
-
-	/* Wait until the PLL is the clock source */
-	while ((STM32_RCC_CFGR & 0xc) != 0x8)
-		;
-/* F03X and F05X and F070 don't have HSI48 */
-#elif defined(CHIP_VARIANT_STM32F03X) || \
-defined(CHIP_VARIANT_STM32F05X) || \
-defined(CHIP_VARIANT_STM32F070)
-	/* If PLL is the clock source, PLL has already been set up. */
-	if ((STM32_RCC_CFGR & 0xc) == 0x8)
-		return;
-
-	/* Ensure that HSI is ON */
-	wait_for_ready(&STM32_RCC_CR, BIT(0), BIT(1));
-
-	/*
-	 * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz
-	 * therefore PCLK = FCLK = SYSCLK = 48MHz
-	 */
-	/* Switch the PLL source to HSI/2 */
-	STM32_RCC_CFGR &= ~(0x00018000);
-
-	/*
-	 * Specify HSI/2 clock as input clock to PLL and set PLL (*12).
-	 */
-	STM32_RCC_CFGR |= 0x00280000;
-
-	/* Enable the PLL. */
-	STM32_RCC_CR |= 0x01000000;
-
-	/* Wait until PLL is ready. */
-	while (!(STM32_RCC_CR & 0x02000000))
-		;
-
-	/* Switch SYSCLK to PLL. */
-	STM32_RCC_CFGR |= 0x2;
-
-	/* wait until the PLL is the clock source */
-	while ((STM32_RCC_CFGR & 0xc) != 0x8)
-		;
-#else
-	/* Ensure that HSI48 is ON */
-	wait_for_ready(&STM32_RCC_CR2, BIT(16), BIT(17));
-
-#if (CPU_CLOCK == HSI48_CLOCK)
-	/*
-	 * HSI48 = 48MHz, no prescaler, no MCO, no PLL
-	 * therefore PCLK = FCLK = SYSCLK = 48MHz
-	 * USB uses HSI48 = 48MHz
-	 */
-
-#ifdef CONFIG_USB
-	/*
-	 * Configure and enable Clock Recovery System
-	 *
-	 * Since we are running from the internal RC HSI48 clock, the CSR
-	 * is needed to guarantee an accurate 48MHz clock for USB.
-	 *
-	 * The default values configure the CRS to use the periodic USB SOF
-	 * as the SYNC signal for calibrating the HSI48.
-	 *
-	 */
-
-	/* Enable Clock Recovery System */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_CRS;
-
-	/* Enable automatic trimming */
-	STM32_CRS_CR |= STM32_CRS_CR_AUTOTRIMEN;
-
-	/* Enable oscillator clock for the frequency error counter */
-	STM32_CRS_CR |= STM32_CRS_CR_CEN;
-#endif
-
-	/* switch SYSCLK to HSI48 */
-	STM32_RCC_CFGR = 0x00000003;
-
-	/* wait until the HSI48 is the clock source */
-	while ((STM32_RCC_CFGR & 0xc) != 0xc)
-		;
-
-#elif (CPU_CLOCK == PLL_CLOCK)
-	/*
-	 * HSI48 = 48MHz, no prescalar, no MCO, with PLL *4/5 => 38.4MHz SYSCLK
-	 * therefore PCLK = FCLK = SYSCLK = 38.4MHz
-	 * USB uses HSI48 = 48MHz
-	 */
-
-	/* If PLL is the clock source, PLL has already been set up. */
-	if ((STM32_RCC_CFGR & 0xc) == 0x8)
-		return;
-
-	/*
-	 * Specify HSI48 clock as input clock to PLL and set PLL multiplier
-	 * and divider.
-	 */
-	STM32_RCC_CFGR = 0x00098000;
-	STM32_RCC_CFGR2 = 0x4;
-
-	/* Enable the PLL. */
-	STM32_RCC_CR |= 0x01000000;
-
-	/* Wait until PLL is ready. */
-	while (!(STM32_RCC_CR & 0x02000000))
-		;
-
-	/* Switch SYSCLK to PLL. */
-	STM32_RCC_CFGR |= 0x2;
-
-	/* wait until the PLL is the clock source */
-	while ((STM32_RCC_CFGR & 0xc) != 0x8)
-		;
-
-#else
-#error "CPU_CLOCK must be either 48MHz or 38.4MHz"
-#endif
-#endif
-}
-
-#ifdef CONFIG_HIBERNATE
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	struct rtc_time_reg rtc;
-
-	if (seconds || microseconds)
-		set_rtc_alarm(seconds, microseconds, &rtc, 0);
-
-	/* interrupts off now */
-	asm volatile("cpsid i");
-
-#ifdef CONFIG_HIBERNATE_WAKEUP_PINS
-	/* enable the wake up pins */
-	STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS;
-#endif
-	STM32_PWR_CR |= 0xe;
-	CPU_SCB_SYSCTRL |= 0x4;
-	/* go to Standby mode */
-	asm("wfi");
-
-	/* we should never reach that point */
-	while (1)
-		;
-}
-#endif
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void restore_host_wake_alarm_deferred(void)
-{
-	restore_host_wake_alarm();
-}
-DECLARE_DEFERRED(restore_host_wake_alarm_deferred);
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-
-void clock_refresh_console_in_use(void)
-{
-}
-
-void __idle(void)
-{
-	timestamp_t t0;
-	uint32_t rtc_diff;
-	int next_delay, margin_us;
-	struct rtc_time_reg rtc0, rtc1;
-
-	while (1) {
-		asm volatile("cpsid i");
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-#ifdef CONFIG_LOW_POWER_IDLE_LIMITED
-		if (idle_is_disabled())
-			goto en_int;
-#endif
-
-		if (DEEP_SLEEP_ALLOWED &&
-#ifdef CONFIG_HOSTCMD_RTC
-		    /*
-		     * Don't go to deep sleep mode if we might miss the
-		     * wake alarm that the host requested. Note that the
-		     * host alarm always aligns to second. Considering the
-		     * worst case, we have to ensure alarm won't go off
-		     * within RESTORE_HOST_ALARM_LATENCY + 1 second after
-		     * EC exits deep sleep mode.
-		     */
-		    !is_host_wake_alarm_expired(
-			(timestamp_t)(next_delay + t0.val + SECOND +
-				      RESTORE_HOST_ALARM_LATENCY)) &&
-#endif
-		    (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) {
-			/* Deep-sleep in STOP mode */
-			idle_dsleep_cnt++;
-
-			uart_enable_wakeup(1);
-
-			/* Set deep sleep bit */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY,
-				      &rtc0, 0);
-			asm("wfi");
-
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			uart_enable_wakeup(0);
-
-			/*
-			 * By default only HSI 8MHz is enabled here. Re-enable
-			 * high-speed clock if in use.
-			 */
-			config_hispeed_clock();
-
-			/* Fast forward timer according to RTC counter */
-			reset_rtc_alarm(&rtc1);
-			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
-			t0.val = t0.val + rtc_diff;
-			force_time(t0);
-
-#ifdef CONFIG_HOSTCMD_RTC
-			hook_call_deferred(
-				&restore_host_wake_alarm_deferred_data, 0);
-#endif
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += rtc_diff;
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - rtc_diff;
-			if (margin_us < 0)
-				/* Use CPUTS to save stack space */
-				CPUTS("Idle overslept!\n");
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
-		}
-#ifdef CONFIG_LOW_POWER_IDLE_LIMITED
-en_int:
-#endif
-		asm volatile("cpsie i");
-	}
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-int clock_get_freq(void)
-{
-	return CPU_CLOCK;
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA1_REGS->isr;
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	if (module == MODULE_ADC) {
-		if (enable)
-			STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADCEN;
-		else
-			STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN;
-		return;
-	} else if (module == MODULE_USB) {
-		if (enable)
-			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
-		else
-			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
-	}
-}
-
-int clock_is_module_enabled(enum module_id module)
-{
-	if (module == MODULE_ADC)
-		return !!(STM32_RCC_APB2ENR & STM32_RCC_APB2ENR_ADCEN);
-	else if (module == MODULE_USB)
-		return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB);
-	return 0;
-}
-
-void rtc_init(void)
-{
-	rtc_unlock_regs();
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-	while (STM32_RTC_ISR & STM32_RTC_ISR_INITF)
-		;
-
-	/* Enable RTC alarm interrupt */
-	STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD;
-	STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT;
-	task_enable_irq(STM32_IRQ_RTC_ALARM);
-
-	rtc_lock_regs();
-}
-
-#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC)
-void rtc_set(uint32_t sec)
-{
-	struct rtc_time_reg rtc;
-
-	sec_to_rtc(sec, &rtc);
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	STM32_RTC_TR = rtc.rtc_tr;
-	STM32_RTC_DR = rtc.rtc_dr;
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-
-	rtc_lock_regs();
-}
-#endif
-
-#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_COMMON_RUNTIME)
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* CONFIG_CMD_IDLE_STATS */
-#endif
diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c
deleted file mode 120000
index be91154e52..0000000000
--- a/chip/stm32/clock-stm32f3.c
+++ /dev/null
@@ -1 +0,0 @@
-clock-stm32f0.c
\ No newline at end of file
diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c
deleted file mode 100644
index a50f5f51dd..0000000000
--- a/chip/stm32/clock-stm32f4.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-enum clock_osc {
-	OSC_HSI = 0,	/* High-speed internal oscillator */
-	OSC_HSE,	/* High-speed external oscillator */
-	OSC_PLL,	/* PLL */
-};
-
-/*
- * NOTE: Sweetberry requires MCO2 <- HSE @ 24MHz
- * MCO outputs are selected here but are not changeable later.
- * A CONFIG may be needed if other boards have different MCO
- * requirements.
- */
-#define RCC_CFGR_MCO_CONFIG ((2 << 30) | /* MCO2 <- HSE  */ \
-			     (0 << 27) | /* MCO2 div / 4 */ \
-			     (6 << 24) | /* MCO1 div / 4 */ \
-			     (3 << 21))  /* MCO1 <- PLL  */
-
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-/* RTC clock must 1 Mhz when derived from HSE */
-#define RTC_DIV DIV_ROUND_NEAREST(CONFIG_STM32_CLOCK_HSE_HZ, STM32F4_RTC_REQ)
-#else /* !CONFIG_STM32_CLOCK_HSE_HZ */
-/* RTC clock not derived from HSE, turn it off */
-#define RTC_DIV 0
-#endif /* CONFIG_STM32_CLOCK_HSE_HZ */
-
-
-/* Bus clocks dividers depending on the configuration */
-/*
- * max speed configuration with the PLL ON
- * as defined in the registers file.
- * For STM32F446: max 45 MHz
- * For STM32F412: max AHB 100 MHz / APB2 100 Mhz / APB1 50 Mhz
- */
-#define RCC_CFGR_DIVIDERS_WITH_PLL (RCC_CFGR_MCO_CONFIG  | \
-				    CFGR_RTCPRE(RTC_DIV) | \
-				    CFGR_PPRE2(STM32F4_APB2_PRE) | \
-				    CFGR_PPRE1(STM32F4_APB1_PRE) | \
-				    CFGR_HPRE(STM32F4_AHB_PRE))
-/*
- * lower power configuration without the PLL
- * the frequency will be low (8-24Mhz), we don't want dividers to the
- * peripheral clocks, put /1 everywhere.
- */
-#define RCC_CFGR_DIVIDERS_NO_PLL (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | \
-				  CFGR_PPRE2(0) | CFGR_PPRE1(0) | CFGR_HPRE(0))
-
-/* PLL output frequency */
-#define STM32F4_PLL_CLOCK (STM32F4_VCO_CLOCK / STM32F4_PLLP_DIV)
-
-/* current clock settings (PLL is initialized at startup) */
-static int current_osc = OSC_PLL;
-static int current_io_freq = STM32F4_IO_CLOCK;
-static int current_timer_freq = STM32F4_TIMER_CLOCK;
-
-/* the EC code expects to get the USART/I2C clock frequency here (APB clock) */
-int clock_get_freq(void)
-{
-	return current_io_freq;
-}
-
-int clock_get_timer_freq(void)
-{
-	return current_timer_freq;
-}
-
-static void clock_enable_osc(enum clock_osc osc, bool enabled)
-{
-	uint32_t ready;
-	uint32_t on;
-
-	switch (osc) {
-	case OSC_HSI:
-		ready = STM32_RCC_CR_HSIRDY;
-		on = STM32_RCC_CR_HSION;
-		break;
-	case OSC_HSE:
-		ready = STM32_RCC_CR_HSERDY;
-		on = STM32_RCC_CR_HSEON;
-		break;
-	case OSC_PLL:
-		ready = STM32_RCC_CR_PLLRDY;
-		on = STM32_RCC_CR_PLLON;
-		break;
-	default:
-		ASSERT(0);
-		return;
-	}
-
-	/* Turn off the oscillator, but don't wait for shutdown */
-	if (!enabled) {
-		STM32_RCC_CR &= ~on;
-		return;
-	}
-
-	/* Turn on the oscillator if not already on */
-	wait_for_ready(&STM32_RCC_CR, on, ready);
-}
-
-static void clock_switch_osc(enum clock_osc osc)
-{
-	uint32_t sw;
-	uint32_t sws;
-
-	switch (osc) {
-	case OSC_HSI:
-		sw = STM32_RCC_CFGR_SW_HSI | RCC_CFGR_DIVIDERS_NO_PLL;
-		sws = STM32_RCC_CFGR_SWS_HSI;
-		break;
-	case OSC_HSE:
-		sw = STM32_RCC_CFGR_SW_HSE | RCC_CFGR_DIVIDERS_NO_PLL;
-		sws = STM32_RCC_CFGR_SWS_HSE;
-		break;
-	case OSC_PLL:
-		sw = STM32_RCC_CFGR_SW_PLL | RCC_CFGR_DIVIDERS_WITH_PLL;
-		sws = STM32_RCC_CFGR_SWS_PLL;
-		break;
-	default:
-		return;
-	}
-
-	STM32_RCC_CFGR = sw;
-	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws)
-		;
-}
-
-void clock_set_osc(enum clock_osc osc)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (osc == current_osc)
-		return;
-
-	hook_notify(HOOK_PRE_FREQ_CHANGE);
-
-	switch (osc) {
-	default:
-	case OSC_HSI:
-		/* new clock settings: no dividers */
-		current_io_freq = STM32F4_HSI_CLOCK;
-		current_timer_freq = STM32F4_HSI_CLOCK;
-		/* Switch to HSI */
-		clock_switch_osc(OSC_HSI);
-		/* optimized flash latency settings for <30Mhz clock (0-WS) */
-		STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK)
-				| STM32_FLASH_ACR_LATENCY_SLOW;
-		/* read-back the latency as advised by the Reference Manual */
-		unused = STM32_FLASH_ACR;
-		/* Turn off the PLL1 to save power */
-		clock_enable_osc(OSC_PLL, false);
-		break;
-
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	case OSC_HSE:
-		/* new clock settings: no dividers */
-		current_io_freq = CONFIG_STM32_CLOCK_HSE_HZ;
-		current_timer_freq = CONFIG_STM32_CLOCK_HSE_HZ;
-		/* Switch to HSE */
-		clock_switch_osc(OSC_HSE);
-		/* optimized flash latency settings for <30Mhz clock (0-WS) */
-		STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK)
-				| STM32_FLASH_ACR_LATENCY_SLOW;
-		/* read-back the latency as advised by the Reference Manual */
-		unused = STM32_FLASH_ACR;
-		/* Turn off the PLL1 to save power */
-		clock_enable_osc(OSC_PLL, false);
-		break;
-#endif /* CONFIG_STM32_CLOCK_HSE_HZ */
-
-	case OSC_PLL:
-		/* new clock settings */
-		current_io_freq = STM32F4_IO_CLOCK;
-		current_timer_freq = STM32F4_TIMER_CLOCK;
-		/* turn on PLL and wait until it's ready */
-		clock_enable_osc(OSC_PLL, true);
-		/*
-		 * Increase flash latency before transition the clock
-		 * Use the minimum Wait States value optimized for the platform.
-		 */
-		STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK)
-				| STM32_FLASH_ACR_LATENCY;
-		/* read-back the latency as advised by the Reference Manual */
-		unused = STM32_FLASH_ACR;
-		/* Switch to PLL */
-		clock_switch_osc(OSC_PLL);
-
-		break;
-	}
-
-	current_osc = osc;
-	hook_notify(HOOK_FREQ_CHANGE);
-}
-
-static void clock_pll_configure(void)
-{
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	int srcclock = CONFIG_STM32_CLOCK_HSE_HZ;
-#else
-	int srcclock = STM32F4_HSI_CLOCK;
-#endif
-	int plldiv, pllinputclock;
-	int pllmult, vcoclock;
-	int systemclock;
-	int usbdiv;
-	int i2sdiv;
-
-	/* PLL input must be between 1-2MHz, near 2 */
-	/* Valid values 2-63 */
-	plldiv = (srcclock + STM32F4_PLL_REQ - 1) / STM32F4_PLL_REQ;
-	pllinputclock = srcclock / plldiv;
-
-	/* PLL output clock: Must be 100-432MHz */
-	pllmult = (STM32F4_VCO_CLOCK + (pllinputclock / 2)) / pllinputclock;
-	vcoclock = pllinputclock * pllmult;
-
-	/* CPU/System clock */
-	systemclock = vcoclock / STM32F4_PLLP_DIV;
-	/* USB clock = 48MHz exactly */
-	usbdiv = (vcoclock + (STM32F4_USB_REQ / 2)) / STM32F4_USB_REQ;
-	assert(vcoclock / usbdiv == STM32F4_USB_REQ);
-
-	/* SYSTEM/I2S: same system clock */
-	i2sdiv = (vcoclock + (systemclock / 2)) / systemclock;
-
-	/* Set up PLL */
-	STM32_RCC_PLLCFGR =
-		PLLCFGR_PLLM(plldiv) |
-		PLLCFGR_PLLN(pllmult) |
-		PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) |
-#if defined(CONFIG_STM32_CLOCK_HSE_HZ)
-		PLLCFGR_PLLSRC_HSE |
-#else
-		PLLCFGR_PLLSRC_HSI |
-#endif
-		PLLCFGR_PLLQ(usbdiv) |
-		PLLCFGR_PLLR(i2sdiv);
-}
-
-void low_power_init(void);
-
-void config_hispeed_clock(void)
-{
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	/* Ensure that HSE is ON */
-	clock_enable_osc(OSC_HSE, true);
-#endif
-
-	/* Put the PLL settings, they are never changing */
-	clock_pll_configure();
-	clock_enable_osc(OSC_PLL, true);
-
-	/* Switch SYSCLK to PLL, setup bus prescalers. */
-	clock_switch_osc(OSC_PLL);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	low_power_init();
-#endif
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA_GET_ISR(0);
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	if (module == MODULE_USB) {
-		if (enable) {
-			STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_OTGFSEN;
-			STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_OTGHSEN |
-				STM32_RCC_AHB1ENR_OTGHSULPIEN;
-		} else {
-			STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_OTGFSEN;
-			STM32_RCC_AHB1ENR &= ~STM32_RCC_AHB1ENR_OTGHSEN &
-				     ~STM32_RCC_AHB1ENR_OTGHSULPIEN;
-		}
-		return;
-	} else if (module == MODULE_I2C) {
-		if (enable) {
-			/* Enable clocks to I2C modules if necessary */
-			STM32_RCC_APB1ENR |=
-				STM32_RCC_I2C1EN | STM32_RCC_I2C2EN
-				| STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN;
-			STM32_RCC_DCKCFGR2 =
-				(STM32_RCC_DCKCFGR2 & ~DCKCFGR2_FMPI2C1SEL_MASK)
-				| DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB);
-		} else {
-			STM32_RCC_APB1ENR &=
-				~(STM32_RCC_I2C1EN | STM32_RCC_I2C2EN |
-				  STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN);
-		}
-		return;
-	} else if (module == MODULE_ADC) {
-		if (enable)
-			STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADC1EN;
-		else
-			STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADC1EN;
-		return;
-	}
-}
-
-/* Real Time Clock (RTC) */
-
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-#define RTC_PREDIV_A 39
-#define RTC_FREQ ((STM32F4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */
-#else /* from LSI clock */
-#define RTC_PREDIV_A 1
-#define RTC_FREQ (STM32F4_LSI_CLOCK / (RTC_PREDIV_A + 1)) /* Hz */
-#endif
-#define RTC_PREDIV_S (RTC_FREQ - 1)
-/*
- * Scaling factor to ensure that the intermediate values computed from/to the
- * RTC frequency are fitting in a 32-bit integer.
- */
-#define SCALING 1000
-
-int32_t rtcss_to_us(uint32_t rtcss)
-{
-	return ((RTC_PREDIV_S - rtcss) * (SECOND/SCALING) / (RTC_FREQ/SCALING));
-}
-
-uint32_t us_to_rtcss(int32_t us)
-{
-	return (RTC_PREDIV_S - (us * (RTC_FREQ/SCALING) / (SECOND/SCALING)));
-}
-
-void rtc_init(void)
-{
-	/* Setup RTC Clock input */
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	/* RTC clocked from the HSE */
-	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE);
-#else
-	/* RTC clocked from the LSI, ensure first it is ON */
-	wait_for_ready(&(STM32_RCC_CSR),
-		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
-
-	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI);
-#endif
-
-	rtc_unlock_regs();
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars: Needs two separate writes. */
-	STM32_RTC_PRER =
-		(STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | RTC_PREDIV_S;
-	STM32_RTC_PRER =
-		(STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK)
-		| (RTC_PREDIV_A << 16);
-
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-	while (STM32_RTC_ISR & STM32_RTC_ISR_INITF)
-		;
-
-	/* Enable RTC alarm interrupt */
-	STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD;
-	STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT;
-	task_enable_irq(STM32_IRQ_RTC_ALARM);
-
-	rtc_lock_regs();
-}
-
-#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC)
-void rtc_set(uint32_t sec)
-{
-	struct rtc_time_reg rtc;
-
-	sec_to_rtc(sec, &rtc);
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	STM32_RTC_TR = rtc.rtc_tr;
-	STM32_RTC_DR = rtc.rtc_dr;
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-
-	rtc_lock_regs();
-}
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Low power idle statistics */
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/* STOP_MODE_LATENCY: delay to wake up from STOP mode with main regulator off */
-#define STOP_MODE_LATENCY 50 /* us */
-/* PLL_LOCK_LATENCY: delay to switch from HSI to PLL */
-#define PLL_LOCK_LATENCY 150 /* us */
-/*
- * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
- * in the past, it will never wake up and cause a watchdog.
- */
-#define SET_RTC_MATCH_DELAY 120 /* us */
-
-
-void low_power_init(void)
-{
-	/* Turn off the main regulator during stop mode */
-	STM32_PWR_CR |= STM32_PWR_CR_LPSDSR /* aka LPDS */;
-}
-
-void clock_refresh_console_in_use(void)
-{
-}
-
-void __idle(void)
-{
-	timestamp_t t0;
-	uint32_t rtc_diff;
-	int next_delay, margin_us;
-	struct rtc_time_reg rtc0, rtc1;
-
-	while (1) {
-		asm volatile("cpsid i");
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		if (DEEP_SLEEP_ALLOWED &&
-		    (next_delay > (STOP_MODE_LATENCY + PLL_LOCK_LATENCY +
-				   SET_RTC_MATCH_DELAY))) {
-			/* Deep-sleep in STOP mode */
-			idle_dsleep_cnt++;
-
-			/*
-			 * TODO(b/174337385) no support for wake-up on USART
-			 * uart_enable_wakeup(1);
-			 */
-
-			/* Set deep sleep bit */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY
-						    - PLL_LOCK_LATENCY,
-				      &rtc0, 0);
-
-			/* Switch to HSI */
-			clock_switch_osc(OSC_HSI);
-			/* Turn off the PLL1 to save power */
-			clock_enable_osc(OSC_PLL, false);
-
-			/* ensure outstanding memory transactions complete */
-			asm volatile("dsb");
-
-			asm("wfi");
-
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			/* turn on PLL and wait until it's ready */
-			clock_enable_osc(OSC_PLL, true);
-			/* Switch to PLL */
-			clock_switch_osc(OSC_PLL);
-
-			/*uart_enable_wakeup(0);*/
-
-			/* Fast forward timer according to RTC counter */
-			reset_rtc_alarm(&rtc1);
-			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
-			t0.val = t0.val + rtc_diff;
-			force_time(t0);
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += rtc_diff;
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - rtc_diff;
-			if (margin_us < 0)
-				/* Use CPUTS to save stack space */
-				CPUTS("Idle overslept!\n");
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
-		}
-		asm volatile("cpsie i");
-	}
-}
-
-/* Print low power idle statistics. */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c
deleted file mode 100644
index 42a00a0f6a..0000000000
--- a/chip/stm32/clock-stm32g4.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks configuration routines */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#define MHZ(x) ((x) * 1000000)
-#define WAIT_STATE_FREQ_STEP_HZ	MHZ(20)
-/* PLL configuration constants */
-#define STM32G4_SYSCLK_MAX_HZ		MHZ(170)
-#define STM32G4_HSI_CLK_HZ		MHZ(16)
-#define STM32G4_PLL_IN_FREQ_HZ		MHZ(4)
-#define STM32G4_PLL_R 2
-#define STM32G4_AHB_PRE 1
-#define STM32G4_APB1_PRE 1
-#define STM32G4_APB2_PRE 1
-
-enum rcc_clksrc {
-	sysclk_rsvd,
-	sysclk_hsi,
-	sysclk_hse,
-	sysclk_pll,
-};
-
-static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
-			      uint32_t pll_clk_in_hz)
-{
-	/*
-	 * The pll output frequency (Fhclkc) is determined by:
-	 *     Fvco = Fosc_in * (PLL_N / PLL_M)
-	 *     Fsysclk = Fvco / PLL_R
-	 *     Fhclk = Fsysclk / AHBpre = (Fosc * N) /(M * R * AHBpre)
-	 *
-	 * PLL_N: 8 <= N <= 127
-	 * PLL_M: 1 <= M <= 16
-	 * PLL_R: 2, 4, 6, or 8
-	 *
-	 * PLL_input freq (4 - 16 MHz)
-	 * Fvco: 2.66 MHz <= Fvco_in <= 8 MHz
-	 *       64 MHz <= Fvco_out <= 344 MHz
-	 * Fhclk <= 170 MHz
-	 *
-	 * PLL config parameters are selected given the following assumptions:
-	 *     - PLL input freq = 4 MHz
-	 *     - PLL_R divider = 2
-	 * With these assumptions the value N can be calculated by:
-	 *     N = (Fhclk * M * R * AHBpre) / Fosc
-	 *     where M = Fosc / F_pllin
-	 *     Replacing M gives:
-	 *     N = (Fhclk * R * AHBpre) / Fpll_in
-	 */
-	uint32_t pll_n;
-	uint32_t pll_m;
-	uint32_t hclk_freq;
-
-	/* Pll input divider = input freq / desired_input_freq */
-	pll_m = pll_clk_in_hz / STM32G4_PLL_IN_FREQ_HZ;
-	pll_n = (hclk_hz * STM32G4_PLL_R * STM32G4_AHB_PRE) /
-		STM32G4_PLL_IN_FREQ_HZ;
-
-	/* validity checks */
-	ASSERT(pll_m && (pll_m <= 16));
-	ASSERT((pll_n >= 8) && (pll_n <= 127));
-
-	hclk_freq = pll_clk_in_hz * pll_n / (pll_m *
-					      STM32G4_PLL_R * STM32G4_AHB_PRE);
-	/* Ensure that there aren't any integer rounding errors */
-	ASSERT(hclk_freq == hclk_hz);
-
-	/* Program PLL config register */
-	STM32_RCC_PLLCFGR = PLLCFGR_PLLP(0) |
-		PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) |
-		PLLCFGR_PLLR_EN |
-		PLLCFGR_PLLQ(0) |
-		PLLCFGR_PLLQ_EN |
-		PLLCFGR_PLLN(pll_n) |
-		PLLCFGR_PLLM(pll_m - 1) |
-		pll_src;
-
-	/* Wait until PLL is locked */
-	wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_PLLON,
-		       STM32_RCC_CR_PLLRDY);
-
-	/*
-	 * Program prescalers and set system clock source as PLL
-	 * Assuming AHB, APB1, and APB2 prescalers are 1, and no clock output
-	 * desired so MCO fields are left at reset value.
-	 */
-	STM32_RCC_CFGR = STM32_RCC_CFGR_SW_PLL;
-
-	/* Wait until the PLL is the system clock source */
-	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-	       STM32_RCC_CFGR_SWS_PLL)
-		;
-}
-
-static void stm32g4_config_low_speed_clock(void)
-{
-	/* Ensure that LSI is ON */
-	wait_for_ready(&(STM32_RCC_CSR),
-		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
-
-	/* Setup RTC Clock input */
-	STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
-	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI);
-}
-
-static void stm32g4_config_high_speed_clock(uint32_t hclk_hz,
-					    enum rcc_clksrc sysclk_src,
-					    uint32_t pll_clksrc)
-{
-	/* TODO(b/161502871): PLL is currently only supported clock source */
-	ASSERT(sysclk_src == sysclk_pll);
-
-	/* Ensure that HSI is ON */
-	wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_HSION,
-		       STM32_RCC_CR_HSIRDY);
-
-	if (sysclk_src == sysclk_pll) {
-		/*
-		 * If PLL_R is the desired clock source, then need to calculate
-		 * PLL multilier/diviber parameters. Once the PLL output is
-		 * stable, then the PLL must be selected as the clock
-		 * source. Note, that if the current clock source selection is
-		 * the PLL and sysclk frequency == hclk_hz, there is nothing
-		 * that needs to be done here.
-		 */
-		/* If PLL is the clock source, PLL has already been set up. */
-		if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) ==
-		    STM32_RCC_CFGR_SWS_PLL)
-			return;
-		stm32g4_config_pll(hclk_hz, pll_clksrc, STM32G4_HSI_CLK_HZ);
-	}
-}
-
-void stm32g4_set_flash_ws(uint32_t freq_hz)
-{
-	int ws;
-
-	ASSERT(freq_hz <= STM32G4_SYSCLK_MAX_HZ);
-	/*
-	 * Need to calculate and then set number of wait states (in CPU cycles)
-	 * required for access to internal flash. The required values can be
-	 * found in Table 9 of RM0440 - STM32G4 technical reference manual. A
-	 * table lookup is not required though as WS = HCLK (MHz) / 20
-	 */
-	ws = freq_hz /  WAIT_STATE_FREQ_STEP_HZ;
-	/* Enable data and instruction cache */
-	STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN |
-		STM32_FLASH_ACR_PRFTEN | ws;
-}
-
-void clock_init(void)
-{
-	/*
-	 * The STM32G4 has 3 potential sysclk sources:
-	 *   1. HSE -> external cyrstal oscillator circuit
-	 *   2. HSI -> Internal RC oscillator (16 MHz output)
-	 *   3. PLL -> input from either HSI or HSI
-	 *
-	 * SYSCLK is routed to AHB via the AHB prescaler. The AHB clock is fed
-	 * directly to AHB bus, core, memory, DMA, and cortex FCLK. The AHB bus
-	 * clock is then fed to both APB1 and APB2 buses via the APB1 and APB2
-	 * prescalers.
-	 *
-	 * CrosEC doesn't support having multiple clocks of different
-	 * frequencies and therefore f(AHB) = f(APB1) = f(APB2) must be
-	 * enforced. The max frequency of all these clocks is 170 MHz. Max input
-	 * frequency to the PLL is 48 MHz. The M divider can be used to lower
-	 * the PLL input frequency if necessary. The PLL has 3 different output
-	 * clocks, PLL_P, PLL_Q, and PLL_R. PLL_R is the clock which can be used
-	 * as SYSCLK.
-	 *
-	 * The STM32G4 has an additional 48 MHz internal oscillator that is fed
-	 * directly to the USB and RNG blocks.
-	 *
-	 * The STM32G4 also has a low speed clock which feeds the RTC and IWDG
-	 * blocks and as a low power clock source that can be kept running
-	 * during stop and standby modes. The low speed clock is generated from:
-	 *   1. LSE -> external crystal oscillator (max = 1 MHz)
-	 *   2. LSI -> internal fixed 32 kHz
-	 *
-	 * The initial state following system reset:
-	 *  SYSCLK from HSI, AHB, APB1, and APB2 presecaler = 1
-	 *  PLL unlocked, RTC enabled on LSE
-	 */
-
-	/* Configure flash wait state and enable I/D cache */
-	stm32g4_set_flash_ws(CPU_CLOCK);
-	/* Set up high speed clock and enable PLL */
-	stm32g4_config_high_speed_clock(CPU_CLOCK, sysclk_pll,
-					PLLCFGR_PLLSRC_HSI);
-	/* Set up low speed clock */
-	stm32g4_config_low_speed_clock();
-}
-
-int clock_get_timer_freq(void)
-{
-	/*
-	 * STM32G4 timer clocks (TCLK) are either at the same frequency as
-	 * PCLK_N when the APB prescaler is 1, and TLCK = 2 * PCLK if
-	 * APBn_pre > 1. It's expected that PCLK1 == PCLK2, so only have to
-	 * check either of the apb prescalar settings.
-	 */
-	return (STM32G4_APB1_PRE > 1 ? CPU_CLOCK * 2 : CPU_CLOCK);
-}
-
-int clock_get_freq(void)
-{
-	return CPU_CLOCK;
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA1_REGS->isr;
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	if (module == MODULE_USB) {
-		if (enable) {
-			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
-			STM32_RCC_CRRCR |= RCC_CRRCR_HSI48O;
-		} else {
-			STM32_RCC_CRRCR &= ~RCC_CRRCR_HSI48O;
-			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
-		}
-	} else if (module == MODULE_I2C) {
-		if (enable) {
-			/* Enable clocks to I2C modules if necessary */
-			STM32_RCC_APB1ENR1 |=
-				STM32_RCC_APB1ENR1_I2C1EN |
-				STM32_RCC_APB1ENR1_I2C2EN |
-				STM32_RCC_APB1ENR1_I2C3EN;
-			STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_I2C4EN;
-		} else {
-			STM32_RCC_APB1ENR1 &=
-				~(STM32_RCC_APB1ENR1_I2C1EN |
-				  STM32_RCC_APB1ENR1_I2C2EN |
-				  STM32_RCC_APB1ENR1_I2C3EN);
-			STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_I2C4EN;
-		}
-	} else if (module == MODULE_ADC) {
-		/* TODO does clock select need to be set here too? */
-		if (enable)
-			STM32_RCC_AHB2ENR |= (STM32_RCC_AHB2ENR_ADC12EN |
-					      STM32_RCC_APB2ENR_ADC345EN);
-		else
-			STM32_RCC_AHB2ENR &= ~(STM32_RCC_AHB2ENR_ADC12EN |
-					      STM32_RCC_APB2ENR_ADC345EN);
-	} else {
-		CPRINTS("stm32g4: enable clock module %d not supported",
-			module);
-	}
-}
-
-int clock_is_module_enabled(enum module_id module)
-{
-	if (module == MODULE_USB)
-		return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB);
-	else if (module == MODULE_I2C)
-		return !!(STM32_RCC_APB1ENR1 & STM32_RCC_APB1ENR1_I2C1EN);
-	else if (module == MODULE_ADC)
-		return !!(STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_ADC12EN);
-	return 0;
-}
-
diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c
deleted file mode 100644
index ba233dbd76..0000000000
--- a/chip/stm32/clock-stm32h7.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Clocks and power management settings
- *
- * Error Handling and Unimplemented Features:
- * Since we are dealing with code critical to the runtime of the CPU,
- * our strategy for unimplemented functionality is to ASSERT, but fallback
- * to doing nothing if ASSERT is not enabled. This is not a perfect solution,
- * but at least yields predictable behavior.
- */
-
-
-#include <stdbool.h>
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-/* Check chip family and variant for compatibility */
-#ifndef CHIP_FAMILY_STM32H7
-#error  Source clock-stm32h7.c does not support this chip family.
-#endif
-#ifndef CHIP_VARIANT_STM32H7X3
-#error Unsupported chip variant.
-#endif
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-
-enum clock_osc {
-	OSC_HSI = 0,	/* High-speed internal oscillator */
-	OSC_CSI,	/* Multi-speed internal oscillator: NOT IMPLEMENTED */
-	OSC_HSE,	/* High-speed external oscillator: NOT IMPLEMENTED */
-	OSC_PLL,	/* PLL */
-};
-
-enum voltage_scale {
-	VOLTAGE_SCALE0 = 0,
-	VOLTAGE_SCALE1,
-	VOLTAGE_SCALE2,
-	VOLTAGE_SCALE3,
-	VOLTAGE_SCALE_COUNT,
-};
-
-enum freq {
-	FREQ_1KHZ   = 1000,
-	FREQ_32KHZ  = 32  * FREQ_1KHZ,
-	FREQ_1MHZ   = 1000000,
-	FREQ_2MHZ   = 2   * FREQ_1MHZ,
-	FREQ_16MHZ  = 16  * FREQ_1MHZ,
-	FREQ_64MHZ  = 64  * FREQ_1MHZ,
-	FREQ_140MHZ = 140 * FREQ_1MHZ,
-	FREQ_200MHZ = 200 * FREQ_1MHZ,
-	FREQ_280MHZ = 280 * FREQ_1MHZ,
-	FREQ_400MHZ = 400 * FREQ_1MHZ,
-	FREQ_480MHZ = 480 * FREQ_1MHZ,
-};
-
-/* High-speed oscillator default is 64 MHz */
-#define STM32_HSI_CLOCK FREQ_64MHZ
-/* Low-speed oscillator is 32-Khz */
-#define STM32_LSI_CLOCK FREQ_32KHZ
-
-/*
- * LPTIM is a 16-bit counter clocked by LSI
- * with /4 prescaler (2^2): period 125 us, full range ~8s
- */
-#define LPTIM_PRESCALER_LOG2 2
-/*
- * LPTIM_PRESCALER and LPTIM_PERIOD_US have to be signed, because they
- * determine the signedness of the comparison with |next_delay| in
- * __idle(), where |next_delay| is negative if no next event.
- */
-#define LPTIM_PRESCALER ((int)BIT(LPTIM_PRESCALER_LOG2))
-#define LPTIM_PERIOD_US (SECOND / (STM32_LSI_CLOCK / LPTIM_PRESCALER))
-
-/* This is not the core frequency */
-static enum freq current_bus_freq = STM32_HSI_CLOCK;
-static int current_osc = OSC_HSI;
-
-int clock_get_freq(void)
-{
-	return current_bus_freq;
-}
-
-int clock_get_timer_freq(void)
-{
-	return clock_get_freq();
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_GPIO_IDR(GPIO_A);
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-/* Flash latency values are dependent on peripheral speed and voltage scale */
-static void clock_flash_latency(enum freq axi_freq, enum voltage_scale vos)
-{
-	uint32_t target_acr;
-
-	if (axi_freq == FREQ_64MHZ && vos == VOLTAGE_SCALE3) {
-		target_acr = STM32_FLASH_ACR_WRHIGHFREQ_85MHZ |
-			     (0 << STM32_FLASH_ACR_LATENCY_SHIFT);
-	} else if (axi_freq == FREQ_200MHZ && vos == VOLTAGE_SCALE1) {
-		target_acr = STM32_FLASH_ACR_WRHIGHFREQ_285MHZ |
-			     (2 << STM32_FLASH_ACR_LATENCY_SHIFT);
-	} else {
-		ASSERT(0);
-		return;
-	}
-
-	STM32_FLASH_ACR(0) = target_acr;
-	while (STM32_FLASH_ACR(0) != target_acr)
-		;
-}
-
-/**
- * @brief Configure PLL1 to output the specified frequency.
- *
- * The input frequency to PLL1 is assumed to be the HSI, which
- * is 64MHz.
- *
- * @param output_freq The target output frequency.
- */
-static void clock_pll1_configure(enum freq output_freq) {
-	uint32_t divm = 4; // Input prescaler (16MHz max for PLL -- 64/4 ==> 16)
-	uint32_t divn;     // Pll multiplier
-	uint32_t divp;     // Output 1 prescaler
-
-	switch (output_freq)
-	{
-	case FREQ_400MHZ:
-		/*
-		 * PLL1 configuration:
-		 * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP
-		 *          = 64MHz/4 * 50 / 2
-		 *          = 16MHz * 50 / 2
-		 *          = 400 Mhz
-		 */
-		divn = 50;
-		divp = 2;
-		break;
-	case FREQ_200MHZ:
-		/*
-		 * PLL1 configuration:
-		 * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP
-		 *          = 64 / 4 * 25 / 2
-		 *          = 16MHz * 25 / 2
-		 *          = 200 Mhz
-		 */
-		divn = 25;
-		divp = 2;
-		break;
-	case FREQ_280MHZ:
-		divn = 35;
-		divp = 2;
-		break;
-	case FREQ_480MHZ:
-		divn = 60;
-		divp = 2;
-		break;
-	default:
-		ASSERT(0);
-		return;
-	}
-
-	/*
-	 * Using VCO wide-range setting, STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE,
-	 * requires input frequency to be between 2MHz and 16MHz.
-	 */
-	ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK/divm));
-	ASSERT((STM32_HSI_CLOCK/divm) <= FREQ_16MHZ);
-
-	/*
-	 * Ensure that we actually reach the target frequency.
-	 */
-	ASSERT((STM32_HSI_CLOCK / divm * divn / divp) == output_freq);
-
-	/* Configure PLL1 using 64 Mhz HSI as input */
-	STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI
-			    | STM32_RCC_PLLCKSEL_DIVM1(divm);
-	/* in integer mode, wide range VCO with 16Mhz input, use divP */
-	STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE
-			  | STM32_RCC_PLLCFG_PLL1RGE_8M_16M
-			  | STM32_RCC_PLLCFG_DIVP1EN;
-	STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp)
-			   | STM32_RCC_PLLDIV_DIVN(divn);
-}
-
-/**
- * Configure peripheral domain prescalers to allow a given sysclk frequency.
- *
- * @param sysclk The input system clock, after the system clock prescaler.
- * @return The bus clock speed selected and configured
- */
-static enum freq clock_peripheral_configure(enum freq sysclk) {
-	switch (sysclk)
-	{
-	case FREQ_64MHZ:
-		/* Restore /1 HPRE (AHB prescaler) */
-		/* Disable downstream prescalers */
-		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1PPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1CPRE_DIV1;
-		/* TODO(b/149512910): Adjust more peripheral prescalers */
-		return FREQ_64MHZ;
-	case FREQ_400MHZ:
-		/* Put /2 on HPRE (AHB prescaler) to keep at the 200MHz max */
-		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2
-				 | STM32_RCC_D1CFGR_D1PPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1CPRE_DIV1;
-		/* TODO(b/149512910): Adjust more peripheral prescalers */
-		return FREQ_200MHZ;
-	default:
-		ASSERT(0);
-		return 0;
-	}
-}
-
-static void clock_enable_osc(enum clock_osc osc, bool enabled)
-{
-	uint32_t ready;
-	uint32_t on;
-
-	switch (osc) {
-	case OSC_HSI:
-		ready = STM32_RCC_CR_HSIRDY;
-		on = STM32_RCC_CR_HSION;
-		break;
-	case OSC_PLL:
-		ready = STM32_RCC_CR_PLL1RDY;
-		on = STM32_RCC_CR_PLL1ON;
-		break;
-	default:
-		ASSERT(0);
-		return;
-	}
-
-	/* Turn off the oscillator, but don't wait for shutdown */
-	if (!enabled) {
-		STM32_RCC_CR &= ~on;
-		return;
-	}
-
-	/* Turn on the oscillator if not already on */
-	wait_for_ready(&STM32_RCC_CR, on, ready);
-}
-
-static void clock_switch_osc(enum clock_osc osc)
-{
-	uint32_t sw;
-	uint32_t sws;
-
-	switch (osc) {
-	case OSC_HSI:
-		sw = STM32_RCC_CFGR_SW_HSI;
-		sws = STM32_RCC_CFGR_SWS_HSI;
-		break;
-	case OSC_PLL:
-		sw = STM32_RCC_CFGR_SW_PLL1;
-		sws = STM32_RCC_CFGR_SWS_PLL1;
-		break;
-	default:
-		return;
-	}
-
-	STM32_RCC_CFGR = sw;
-	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws)
-		;
-}
-
-static void switch_voltage_scale(enum voltage_scale vos)
-{
-	volatile uint32_t *const vos_reg   = &STM32_PWR_D3CR;
-	const uint32_t           vos_ready = STM32_PWR_D3CR_VOSRDY;
-	const uint32_t           vos_mask  = STM32_PWR_D3CR_VOSMASK;
-	const uint32_t           vos_values[] = {
-						/* See note below about VOS0. */
-						STM32_PWR_D3CR_VOS1,
-						STM32_PWR_D3CR_VOS1,
-						STM32_PWR_D3CR_VOS2,
-						STM32_PWR_D3CR_VOS3,
-						};
-	BUILD_ASSERT(ARRAY_SIZE(vos_values) == VOLTAGE_SCALE_COUNT);
-
-	/*
-	 * Real VOS0 on the H743 requires entering VOS1 and setting an extra
-	 * SYS boost register. We currently do not implement this functionality.
-	 */
-	if (vos == VOLTAGE_SCALE0) {
-		ASSERT(0);
-		return;
-	}
-
-	*vos_reg &= ~vos_mask;
-	*vos_reg |= vos_values[vos];
-	while (!(*vos_reg & vos_ready))
-		;
-}
-
-static void clock_set_osc(enum clock_osc osc)
-{
-	enum freq target_sysclk_freq = FREQ_64MHZ;
-	enum voltage_scale target_voltage_scale = VOLTAGE_SCALE3;
-
-	if (osc == current_osc)
-		return;
-
-	switch (osc) {
-	case OSC_HSI:
-	case OSC_PLL:
-		break;
-	default:
-		ASSERT(0);
-		return;
-	}
-
-	hook_notify(HOOK_PRE_FREQ_CHANGE);
-
-	switch (osc) {
-	default:
-	case OSC_HSI:
-		/* Switch to HSI */
-		clock_switch_osc(osc);
-		current_bus_freq = clock_peripheral_configure(target_sysclk_freq);
-		/* Use more optimized flash latency settings for 64-MHz ACLK */
-		clock_flash_latency(current_bus_freq, target_voltage_scale);
-		/* Turn off the PLL1 to save power */
-		clock_enable_osc(OSC_PLL, false);
-		switch_voltage_scale(target_voltage_scale);
-		break;
-
-	case OSC_PLL:
-		/*
-		 * PLL1 configuration:
-		 * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP
-		 *          = 64 / 4 * 50 / 2
-		 *          = 400 Mhz
-		 * System clock = 400 Mhz
-		 *  HPRE = /2  => AHB/Timer clock = 200 Mhz
-		 */
-		target_sysclk_freq = FREQ_400MHZ;
-		target_voltage_scale = VOLTAGE_SCALE1;
-
-		switch_voltage_scale(target_voltage_scale);
-		clock_pll1_configure(target_sysclk_freq);
-		/* turn on PLL1 and wait until it's ready */
-		clock_enable_osc(OSC_PLL, true);
-		current_bus_freq = clock_peripheral_configure(target_sysclk_freq);
-		/* Increase flash latency before transition the clock */
-		clock_flash_latency(current_bus_freq, target_voltage_scale);
-
-		/* Switch to PLL */
-		clock_switch_osc(OSC_PLL);
-		break;
-	}
-
-	current_osc = osc;
-	hook_notify(HOOK_FREQ_CHANGE);
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	/* Assume we have a single task using MODULE_FAST_CPU */
-	if (module == MODULE_FAST_CPU) {
-		/* the PLL would be off in low power mode, disable it */
-		if (enable)
-			disable_sleep(SLEEP_MASK_PLL);
-		else
-			enable_sleep(SLEEP_MASK_PLL);
-		clock_set_osc(enable ? OSC_PLL : OSC_HSI);
-	}
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Low power idle statistics */
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/* STOP_MODE_LATENCY: delay to wake up from STOP mode with flash off in SVOS5 */
-#define STOP_MODE_LATENCY 50 /* us */
-
-static void low_power_init(void)
-{
-	/* Clock LPTIM1 on the 32-kHz LSI for STOP mode time keeping */
-	STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R &
-		~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK)
-		| STM32_RCC_D2CCIP2_LPTIM1SEL_LSI;
-
-	/* configure LPTIM1 as our 1-Khz low power timer in STOP mode */
-	STM32_RCC_APB1LENR |= STM32_RCC_PB1_LPTIM1;
-	STM32_LPTIM_CR(1) = 0; /* ensure it's disabled before configuring */
-	STM32_LPTIM_CFGR(1) = LPTIM_PRESCALER_LOG2 << 9; /* Prescaler /4 */
-	STM32_LPTIM_IER(1) = STM32_LPTIM_INT_CMPM; /* Compare int for wake-up */
-	/* Start the 16-bit free-running counter */
-	STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE;
-	STM32_LPTIM_ARR(1) = 0xFFFF;
-	STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE | STM32_LPTIM_CR_CNTSTRT;
-	task_enable_irq(STM32_IRQ_LPTIM1);
-
-	/* Wake-up interrupts from EXTI for USART and LPTIM */
-	STM32_EXTI_CPUIMR1 |= BIT(26); /* [26] wkup26: USART1 wake-up */
-	STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */
-
-	/* optimize power vs latency in STOP mode */
-	STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK)
-		     | STM32_PWR_CR_SVOS5
-		     | STM32_PWR_CR_FLPS;
-}
-
-void clock_refresh_console_in_use(void)
-{
-}
-
-void lptim_interrupt(void)
-{
-	STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM;
-}
-DECLARE_IRQ(STM32_IRQ_LPTIM1, lptim_interrupt, 2);
-
-static uint16_t lptim_read(void)
-{
-	uint16_t cnt;
-
-	do {
-		cnt = STM32_LPTIM_CNT(1);
-	} while (cnt != STM32_LPTIM_CNT(1));
-
-	return cnt;
-}
-
-static void set_lptim_event(int delay_us, uint16_t *lptim_cnt)
-{
-	uint16_t cnt = lptim_read();
-
-	STM32_LPTIM_CMP(1) = cnt + MIN(delay_us / LPTIM_PERIOD_US - 1, 0xffff);
-	/* clean-up previous event */
-	STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM;
-	*lptim_cnt = cnt;
-}
-
-void __idle(void)
-{
-	timestamp_t t0;
-	int next_delay;
-	int margin_us, t_diff;
-	uint16_t lptim0;
-
-	while (1) {
-		asm volatile("cpsid i");
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		if (DEEP_SLEEP_ALLOWED &&
-		    next_delay > LPTIM_PERIOD_US + STOP_MODE_LATENCY) {
-			/* deep-sleep in STOP mode */
-			idle_dsleep_cnt++;
-
-			uart_enable_wakeup(1);
-
-			/* set deep sleep bit */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			set_lptim_event(next_delay - STOP_MODE_LATENCY,
-					&lptim0);
-
-			/* ensure outstanding memory transactions complete */
-			asm volatile("dsb");
-
-			asm("wfi");
-
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			/* fast forward timer according to low power counter */
-			if (STM32_PWR_CPUCR & STM32_PWR_CPUCR_STOPF) {
-				uint16_t lptim_dt = lptim_read() - lptim0;
-
-				t_diff = (int)lptim_dt * LPTIM_PERIOD_US;
-				t0.val = t0.val + t_diff;
-				force_time(t0);
-				/* clear STOPF flag */
-				STM32_PWR_CPUCR |= STM32_PWR_CPUCR_CSSF;
-			} else { /* STOP entry was aborted, no fixup */
-				t_diff = 0;
-			}
-
-			uart_enable_wakeup(0);
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += t_diff;
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - t_diff;
-			if (margin_us < 0)
-				/* Use CPUTS to save stack space */
-				CPUTS("Overslept!\n");
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* normal idle : only CPU clock stopped */
-			asm("wfi");
-		}
-		asm volatile("cpsie i");
-	}
-}
-
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* CONFIG_CMD_IDLE_STATS */
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-void clock_init(void)
-{
-	/*
-	 * STM32H743 Errata 2.2.15:
-	 * 'Reading from AXI SRAM might lead to data read corruption'
-	 *
-	 * limit concurrent read access on AXI master to 1.
-	 */
-	STM32_AXI_TARG_FN_MOD(7) |= READ_ISS_OVERRIDE;
-
-	/*
-	 * Lock (SCUEN=0) power configuration with the LDO enabled.
-	 *
-	 * The STM32H7 Reference Manual says:
-	 * The lower byte of this register is written once after POR and shall
-	 * be written before changing VOS level or ck_sys clock frequency.
-	 *
-	 * The interesting side-effect of this that while the LDO is enabled by
-	 * default at startup, if we enter STOP mode without locking it the MCU
-	 * seems to freeze forever.
-	 */
-	STM32_PWR_CR3 = STM32_PWR_CR3_LDOEN;
-	/*
-	 * Ensure the SPI is always clocked at the same frequency
-	 * by putting it on the fixed 64-Mhz HSI clock.
-	 * per_ck is clocked directly by the HSI (as per the default settings).
-	 */
-	STM32_RCC_D2CCIP1R = (STM32_RCC_D2CCIP1R &
-		~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK |
-		  STM32_RCC_D2CCIP1R_SPI45SEL_MASK))
-		| STM32_RCC_D2CCIP1R_SPI123SEL_PERCK
-		| STM32_RCC_D2CCIP1R_SPI45SEL_HSI;
-
-	/* Use more optimized flash latency settings for ACLK = HSI = 64 Mhz */
-	clock_flash_latency(FREQ_64MHZ, VOLTAGE_SCALE3);
-
-	/* Ensure that LSI is ON to clock LPTIM1 and IWDG */
-	STM32_RCC_CSR |= STM32_RCC_CSR_LSION;
-	while (!(STM32_RCC_CSR & STM32_RCC_CSR_LSIRDY))
-		;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	low_power_init();
-#endif
-}
-
-static int command_clock(int argc, char **argv)
-{
-	if (argc >= 2) {
-		if (!strcasecmp(argv[1], "hsi"))
-			clock_set_osc(OSC_HSI);
-		else if (!strcasecmp(argv[1], "pll"))
-			clock_set_osc(OSC_PLL);
-		else
-			return EC_ERROR_PARAM1;
-	}
-	ccprintf("Clock frequency is now %d Hz\n", clock_get_freq());
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | pll", "Set clock frequency");
diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c
deleted file mode 100644
index bb0da42d14..0000000000
--- a/chip/stm32/clock-stm32l.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "registers.h"
-#include "util.h"
-
-#ifdef CONFIG_STM32L_FAKE_HIBERNATE
-#include "extpower.h"
-#include "keyboard_config.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-
-static int fake_hibernate;
-#endif
-
-/* High-speed oscillator is 16 MHz */
-#define HSI_CLOCK 16000000
-/*
- * MSI is 2 MHz (default) 1 MHz, depending on ICSCR setting.  We use 1 MHz
- * because it's the lowest clock rate we can still run 115200 baud serial
- * for the debug console.
- */
-#define MSI_2MHZ_CLOCK BIT(21)
-#define MSI_1MHZ_CLOCK BIT(20)
-
-enum clock_osc {
-	OSC_INIT = 0,	/* Uninitialized */
-	OSC_HSI,	/* High-speed oscillator */
-	OSC_MSI,	/* Med-speed oscillator @ 1 MHz */
-};
-
-static int freq;
-static int current_osc;
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-int clock_get_timer_freq(void)
-{
-	return clock_get_freq();
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA1_REGS->isr;
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-/**
- * Set which oscillator is used for the clock
- *
- * @param osc		Oscillator to use
- */
-static void clock_set_osc(enum clock_osc osc)
-{
-	uint32_t tmp_acr;
-
-	if (osc == current_osc)
-		return;
-
-	if (current_osc != OSC_INIT)
-		hook_notify(HOOK_PRE_FREQ_CHANGE);
-
-	switch (osc) {
-	case OSC_HSI:
-		/* Ensure that HSI is ON */
-		wait_for_ready(&STM32_RCC_CR,
-			       STM32_RCC_CR_HSION, STM32_RCC_CR_HSIRDY);
-
-		/* Disable LPSDSR */
-		STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR;
-
-		/*
-		 * Set the recommended flash settings for 16MHz clock.
-		 *
-		 * The 3 bits must be programmed strictly sequentially.
-		 * Also, follow the RM to check 64-bit access and latency bit
-		 * after writing those bits to the FLASH_ACR register.
-		 */
-		tmp_acr = STM32_FLASH_ACR;
-		/* Enable 64-bit access */
-		tmp_acr |= STM32_FLASH_ACR_ACC64;
-		STM32_FLASH_ACR = tmp_acr;
-		/* Check ACC64 bit == 1 */
-		while (!(STM32_FLASH_ACR & STM32_FLASH_ACR_ACC64))
-			;
-
-		/* Enable Prefetch Buffer */
-		tmp_acr |= STM32_FLASH_ACR_PRFTEN;
-		STM32_FLASH_ACR = tmp_acr;
-
-		/* Flash 1 wait state */
-		tmp_acr |= STM32_FLASH_ACR_LATENCY;
-		STM32_FLASH_ACR = tmp_acr;
-		/* Check LATENCY bit == 1 */
-		while (!(STM32_FLASH_ACR & STM32_FLASH_ACR_LATENCY))
-			;
-
-		/* Switch to HSI */
-		STM32_RCC_CFGR = STM32_RCC_CFGR_SW_HSI;
-		/* RM says to check SWS bits to make sure HSI is the sysclock */
-		while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-			STM32_RCC_CFGR_SWS_HSI)
-			;
-
-		/* Disable MSI */
-		STM32_RCC_CR &= ~STM32_RCC_CR_MSION;
-
-		freq = HSI_CLOCK;
-		break;
-
-	case OSC_MSI:
-		/* Switch to MSI @ 1MHz */
-		STM32_RCC_ICSCR =
-			(STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
-			STM32_RCC_ICSCR_MSIRANGE_1MHZ;
-		/* Ensure that MSI is ON */
-		wait_for_ready(&STM32_RCC_CR,
-			       STM32_RCC_CR_MSION, STM32_RCC_CR_MSIRDY);
-
-		/* Switch to MSI */
-		STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI;
-		/* RM says to check SWS bits to make sure MSI is the sysclock */
-		while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-			STM32_RCC_CFGR_SWS_MSI)
-			;
-
-		/*
-		 * Set the recommended flash settings for <= 2MHz clock.
-		 *
-		 * The 3 bits must be programmed strictly sequentially.
-		 * Also, follow the RM to check 64-bit access and latency bit
-		 * after writing those bits to the FLASH_ACR register.
-		 */
-		tmp_acr = STM32_FLASH_ACR;
-		/* Flash 0 wait state */
-		tmp_acr &= ~STM32_FLASH_ACR_LATENCY;
-		STM32_FLASH_ACR = tmp_acr;
-		/* Check LATENCY bit == 0 */
-		while (STM32_FLASH_ACR & STM32_FLASH_ACR_LATENCY)
-			;
-
-		/* Disable prefetch Buffer */
-		tmp_acr &= ~STM32_FLASH_ACR_PRFTEN;
-		STM32_FLASH_ACR = tmp_acr;
-
-		/* Disable 64-bit access */
-		tmp_acr &= ~STM32_FLASH_ACR_ACC64;
-		STM32_FLASH_ACR = tmp_acr;
-		/* Check ACC64 bit == 0 */
-		while (STM32_FLASH_ACR & STM32_FLASH_ACR_ACC64)
-			;
-
-		/* Disable HSI */
-		STM32_RCC_CR &= ~STM32_RCC_CR_HSION;
-
-		/* Enable LPSDSR */
-		STM32_PWR_CR |= STM32_PWR_CR_LPSDSR;
-
-		freq = MSI_1MHZ_CLOCK;
-		break;
-
-	default:
-		break;
-	}
-
-	/* Notify modules of frequency change unless we're initializing */
-	if (current_osc != OSC_INIT) {
-		current_osc = osc;
-		hook_notify(HOOK_FREQ_CHANGE);
-	} else {
-		current_osc = osc;
-	}
-}
-
-static uint64_t clock_mask;
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	uint64_t new_mask;
-
-	if (enable)
-		new_mask = clock_mask | BIT_ULL(module);
-	else
-		new_mask = clock_mask & ~BIT_ULL(module);
-
-	/* Only change clock if needed */
-	if ((!!new_mask) != (!!clock_mask)) {
-
-		/* Flush UART before switching clock speed */
-		cflush();
-
-		clock_set_osc(new_mask ? OSC_HSI : OSC_MSI);
-	}
-
-	if (module == MODULE_USB) {
-		if (enable)
-			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
-		else
-			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
-	}
-
-	clock_mask = new_mask;
-}
-
-int clock_is_module_enabled(enum module_id module)
-{
-	return !!(clock_mask & BIT_ULL(module));
-}
-
-#ifdef CONFIG_STM32L_FAKE_HIBERNATE
-/*
- *  This is for NOT having enough hibernate (more precisely, the stand-by mode)
- *  wake-up source pin. STM32L100 supports 3 wake-up source pins:
- *
- *     WKUP1 (PA0)  -- used for ACOK_PMU
- *     WKUP2 (PC13) -- used for LID_OPEN
- *     WKUP3 (PE6)  -- cannot be used due to IC package.
- *
- *  However, we need the power button as a wake-up source as well and there is
- *  no available pin for us (we don't want to move the ACOK_PMU pin).
- *
- *  Fortunately, the STM32L is low-power enough so that we don't need the
- *  super-low-power mode. So, we fake this hibernate mode and accept the
- *  following wake-up source.
- *
- *     RTC alarm  (faked as well).
- *     Power button
- *     Lid open
- *     AC detected
- *
- *  The original issue is here: crosbug.com/p/25435.
- */
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-	fake_hibernate = 1;
-
-#ifdef CONFIG_POWER_COMMON
-	/*
-	 * A quick hack to stop annoying messages from charger task.
-	 *
-	 * When the battery is under 3%, the power task would call
-	 * power_off() to shutdown AP. However, the power_off() would
-	 * notify the HOOK_CHIPSET_SHUTDOWN, where the last hook is
-	 * charge_shutdown() and it hibernates the power task (infinite
-	 * loop -- not real CPU hibernate mode). Unfortunately, the
-	 * charger task is still running. It keeps generating annoying
-	 * log message.
-	 *
-	 * Thus, the hack is to set the power state machine (before we
-	 * enter infinite loop) so that the charger task thinks the AP
-	 * is off and stops generating messages.
-	 */
-	power_set_state(POWER_G3);
-#endif
-
-	/*
-	 * Change keyboard outputs to high-Z to reduce power draw.
-	 * We don't need corresponding code to change them back,
-	 * because fake hibernate is always exited with a reboot.
-	 *
-	 * A little hacky to do this here.
-	 */
-	for (i = GPIO_KB_OUT00; i < GPIO_KB_OUT00 + KEYBOARD_COLS_MAX; i++)
-		gpio_set_flags(i, GPIO_INPUT);
-
-	ccprints("fake hibernate. waits for power button/lid/RTC/AC");
-	cflush();
-
-	if (seconds || microseconds) {
-		if (seconds)
-			sleep(seconds);
-		if (microseconds)
-			usleep(microseconds);
-	} else {
-		while (1)
-			task_wait_event(-1);
-	}
-
-	ccprints("fake RTC alarm fires. resets EC");
-	cflush();
-	system_reset(SYSTEM_RESET_HARD);
-}
-
-static void fake_hibernate_power_button_hook(void)
-{
-	if (fake_hibernate && lid_is_open() && !power_button_is_pressed()) {
-		ccprints("%s() resets EC", __func__);
-		cflush();
-		system_reset(SYSTEM_RESET_HARD);
-	}
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, fake_hibernate_power_button_hook,
-	HOOK_PRIO_DEFAULT);
-
-static void fake_hibernate_lid_hook(void)
-{
-	if (fake_hibernate && lid_is_open()) {
-		ccprints("%s() resets EC", __func__);
-		cflush();
-		system_reset(SYSTEM_RESET_HARD);
-	}
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, fake_hibernate_lid_hook, HOOK_PRIO_DEFAULT);
-
-static void fake_hibernate_ac_hook(void)
-{
-	if (fake_hibernate && extpower_is_present()) {
-		ccprints("%s() resets EC", __func__);
-		cflush();
-		system_reset(SYSTEM_RESET_HARD);
-	}
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, fake_hibernate_ac_hook, HOOK_PRIO_DEFAULT);
-#endif
-
-void clock_init(void)
-{
-	/*
-	 * The initial state :
-	 *  SYSCLK from MSI (=2MHz), no divider on AHB, APB1, APB2
-	 *  PLL unlocked, RTC enabled on LSE
-	 */
-
-	/* Switch to high-speed oscillator */
-	clock_set_osc(1);
-}
-
-static void clock_chipset_startup(void)
-{
-	/* Return to full speed */
-	clock_enable_module(MODULE_CHIPSET, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, clock_chipset_startup, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, clock_chipset_startup, HOOK_PRIO_DEFAULT);
-
-static void clock_chipset_shutdown(void)
-{
-	/* Drop to lower clock speed if no other module requires full speed */
-	clock_enable_module(MODULE_CHIPSET, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-static int command_clock(int argc, char **argv)
-{
-	if (argc >= 2) {
-		if (!strcasecmp(argv[1], "hsi"))
-			clock_set_osc(OSC_HSI);
-		else if (!strcasecmp(argv[1], "msi"))
-			clock_set_osc(OSC_MSI);
-		else
-			return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("Clock frequency is now %d Hz\n", freq);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | msi",
-			"Set clock frequency");
diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c
deleted file mode 100644
index 2094751aab..0000000000
--- a/chip/stm32/clock-stm32l4.c
+++ /dev/null
@@ -1,1110 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings for STM32L4xx as well as STM32L5xx. */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-l4.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "rtc.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/* High-speed oscillator is 16 MHz */
-#define STM32_HSI_CLOCK 16000000
-/* Multi-speed oscillator is 4 MHz by default */
-#define STM32_MSI_CLOCK 4000000
-
-/* Real Time Clock (RTC) */
-
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-#define RTC_PREDIV_A 39
-#define RTC_FREQ ((STM32L4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */
-#else /* from LSI clock */
-#define RTC_PREDIV_A 1
-#define RTC_FREQ (STM32L4_LSI_CLOCK / (RTC_PREDIV_A + 1)) /* Hz */
-#endif
-#define RTC_PREDIV_S (RTC_FREQ - 1)
-/*
- * Scaling factor to ensure that the intermediate values computed from/to the
- * RTC frequency are fitting in a 32-bit integer.
- */
-#define SCALING 1000
-
-enum clock_osc {
-	OSC_INIT = 0,	/* Uninitialized */
-	OSC_HSI,	/* High-speed internal oscillator */
-	OSC_MSI,	/* Multi-speed internal oscillator */
-#ifdef STM32_HSE_CLOCK	/* Allows us to catch absence of HSE at comiple time */
-	OSC_HSE,	/* High-speed external oscillator */
-#endif
-	OSC_PLL,	/* PLL */
-};
-
-static int freq = STM32_MSI_CLOCK;
-static int current_osc;
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-int clock_get_timer_freq(void)
-{
-	return clock_get_freq();
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA1_REGS->isr;
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-static void clock_enable_osc(enum clock_osc osc)
-{
-	uint32_t ready;
-	uint32_t on;
-
-	switch (osc) {
-	case OSC_HSI:
-		ready = STM32_RCC_CR_HSIRDY;
-		on = STM32_RCC_CR_HSION;
-		break;
-	case OSC_MSI:
-		ready = STM32_RCC_CR_MSIRDY;
-		on = STM32_RCC_CR_MSION;
-		break;
-#ifdef STM32_HSE_CLOCK
-	case OSC_HSE:
-#ifdef STM32_HSE_BYP
-		STM32_RCC_CR |= STM32_RCC_CR_HSEBYP;
-#endif
-		ready = STM32_RCC_CR_HSERDY;
-		on = STM32_RCC_CR_HSEON;
-		break;
-#endif
-	case OSC_PLL:
-		ready = STM32_RCC_CR_PLLRDY;
-		on = STM32_RCC_CR_PLLON;
-		break;
-	default:
-		return;
-	}
-
-	/* Enable HSI and wait for HSI to be ready */
-	wait_for_ready(&STM32_RCC_CR, on, ready);
-}
-
-/* Switch system clock oscillator */
-static void clock_switch_osc(enum clock_osc osc)
-{
-	uint32_t sw;
-	uint32_t sws;
-	uint32_t val;
-
-	switch (osc) {
-	case OSC_HSI:
-		sw = STM32_RCC_CFGR_SW_HSI;
-		sws = STM32_RCC_CFGR_SWS_HSI;
-		break;
-	case OSC_MSI:
-		sw = STM32_RCC_CFGR_SW_MSI;
-		sws = STM32_RCC_CFGR_SWS_MSI;
-		break;
-#ifdef STM32_HSE_CLOCK
-	case OSC_HSE:
-		sw = STM32_RCC_CFGR_SW_HSE;
-		sws = STM32_RCC_CFGR_SWS_HSE;
-		break;
-#endif
-	case OSC_PLL:
-		sw = STM32_RCC_CFGR_SW_PLL;
-		sws = STM32_RCC_CFGR_SWS_PLL;
-		break;
-	default:
-		return;
-	}
-	val = STM32_RCC_CFGR;
-	val &= ~STM32_RCC_CFGR_SW;
-	val |= sw;
-	STM32_RCC_CFGR = val;
-	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) != sws)
-		;
-}
-
-/*
- * Configure PLL for HSE
- *
- * 1. Disable the PLL by setting PLLON to 0 in RCC_CR.
- * 2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
- * 3. Change the desired parameter.
- * 4. Enable the PLL again by setting PLLON to 1.
- * 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN
- *    in RCC_PLLCFGR.
- */
-static int stm32_configure_pll(enum clock_osc osc,
-			       uint8_t m, uint8_t n, uint8_t r)
-{
-	uint32_t val;
-	bool pll_unchanged;
-	int f;
-
-	val = STM32_RCC_PLLCFGR;
-	pll_unchanged = true;
-
-	if (osc == OSC_HSI)
-		if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) !=
-		    STM32_RCC_PLLCFGR_PLLSRC_HSI)
-			pll_unchanged = false;
-
-	if (osc == OSC_MSI)
-		if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) !=
-		    STM32_RCC_PLLCFGR_PLLSRC_MSI)
-			pll_unchanged = false;
-
-#ifdef STM32_HSE_CLOCK
-	if (osc == OSC_HSE)
-		if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) !=
-		    STM32_RCC_PLLCFGR_PLLSRC_HSE)
-			pll_unchanged = false;
-#endif
-
-	if ((val & STM32_RCC_PLLCFGR_PLLM_MSK) !=
-	    ((m - 1) << STM32_RCC_PLLCFGR_PLLM_POS))
-		pll_unchanged = false;
-
-	if ((val & STM32_RCC_PLLCFGR_PLLN_MSK) !=
-	    (n << STM32_RCC_PLLCFGR_PLLN_POS))
-		pll_unchanged = false;
-
-	if ((val & STM32_RCC_PLLCFGR_PLLR_MSK) !=
-	    (((r >> 1) - 1) << STM32_RCC_PLLCFGR_PLLR_POS))
-		pll_unchanged = false;
-
-	if (pll_unchanged == true) {
-		if (osc == OSC_HSI)
-			f = STM32_HSI_CLOCK;
-		else
-			f = STM32_MSI_CLOCK;
-
-		if (!(STM32_RCC_CR & STM32_RCC_CR_PLLRDY)) {
-			STM32_RCC_CR |= STM32_RCC_CR_PLLON;
-			STM32_RCC_PLLCFGR |= STM32_RCC_PLLCFGR_PLLREN;
-
-			while ((STM32_RCC_CR & STM32_RCC_CR_PLLRDY) == 0)
-				;
-		}
-		/* (f * n) shouldn't overflow based on their max values */
-		return (f * n / m / r);
-	}
-	/* 1 */
-	STM32_RCC_CR &= ~STM32_RCC_CR_PLLON;
-
-	/* 2 */
-	while (STM32_RCC_CR & STM32_RCC_CR_PLLRDY)
-		;
-
-	/* 3 */
-	val = STM32_RCC_PLLCFGR;
-
-	val &= ~STM32_RCC_PLLCFGR_PLLSRC_MSK;
-	switch (osc) {
-	case OSC_HSI:
-		val |= STM32_RCC_PLLCFGR_PLLSRC_HSI;
-		f = STM32_HSI_CLOCK;
-		break;
-	case OSC_MSI:
-		val |= STM32_RCC_PLLCFGR_PLLSRC_MSI;
-		f = STM32_MSI_CLOCK;
-		break;
-#ifdef STM32_HSE_CLOCK
-	case OSC_HSE:
-		val |= STM32_RCC_PLLCFGR_PLLSRC_HSE;
-		f = STM32_HSE_CLOCK;
-		break;
-#endif
-	default:
-		return -1;
-	}
-
-	ASSERT(m > 0 && m < 9);
-	val &= ~STM32_RCC_PLLCFGR_PLLM_MSK;
-	val |= (m - 1) << STM32_RCC_PLLCFGR_PLLM_POS;
-
-	/* Max and min values are from TRM */
-	ASSERT(n > 7 && n < 87);
-	val &= ~STM32_RCC_PLLCFGR_PLLN_MSK;
-	val |= n << STM32_RCC_PLLCFGR_PLLN_POS;
-
-	val &= ~STM32_RCC_PLLCFGR_PLLR_MSK;
-	switch (r) {
-	case 2:
-		val |= 0 << STM32_RCC_PLLCFGR_PLLR_POS;
-		break;
-	case 4:
-		val |= 1 << STM32_RCC_PLLCFGR_PLLR_POS;
-		break;
-	case 6:
-		val |= 2 << STM32_RCC_PLLCFGR_PLLR_POS;
-		break;
-	case 8:
-		val |= 3 << STM32_RCC_PLLCFGR_PLLR_POS;
-		break;
-	default:
-		return -1;
-	}
-
-	STM32_RCC_PLLCFGR = val;
-
-	/* 4 */
-	clock_enable_osc(OSC_PLL);
-
-	/* 5 */
-	val = STM32_RCC_PLLCFGR;
-	val |= 1 << STM32_RCC_PLLCFGR_PLLREN_POS;
-	STM32_RCC_PLLCFGR = val;
-
-	/* (f * n) shouldn't overflow based on their max values */
-	return (f * n / m / r);
-}
-
-/**
- * Set system clock oscillator
- *
- * @param osc		Oscillator to use
- * @param pll_osc	Source oscillator for PLL. Ignored if osc is not PLL.
- */
-static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
-{
-	uint32_t val;
-
-	if (osc == current_osc)
-		return;
-
-	if (current_osc != OSC_INIT)
-		hook_notify(HOOK_PRE_FREQ_CHANGE);
-
-	switch (osc) {
-	case OSC_HSI:
-		/* Ensure that HSI is ON */
-		clock_enable_osc(osc);
-
-		/* Set HSI as system clock after exiting stop mode */
-		STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK;
-
-		/* Switch to HSI */
-		clock_switch_osc(osc);
-
-		/* Disable MSI */
-		STM32_RCC_CR &= ~STM32_RCC_CR_MSION;
-
-		freq = STM32_HSI_CLOCK;
-		break;
-
-	case OSC_MSI:
-		/* Switch to MSI @ 1MHz */
-		STM32_RCC_CR =
-			(STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
-			STM32_RCC_ICSCR_MSIRANGE_1MHZ;
-		/* Ensure that MSI is ON */
-		clock_enable_osc(osc);
-
-		/*
-		 * Set MSI as system clock after exiting stop mode
-		 */
-		STM32_RCC_CFGR &= ~STM32_RCC_CFGR_STOPWUCK;
-
-		/* Switch to MSI */
-		clock_switch_osc(osc);
-
-		/* Disable HSI */
-		STM32_RCC_CR &= ~STM32_RCC_CR_HSION;
-
-		freq = STM32_MSI_CLOCK;
-		break;
-
-#ifdef STM32_HSE_CLOCK
-	case OSC_HSE:
-		/* Ensure that HSE is stable */
-		clock_enable_osc(osc);
-
-		/* Switch to HSE */
-		clock_switch_osc(osc);
-
-		/* Disable other clock sources */
-		STM32_RCC_CR &= ~(STM32_RCC_CR_MSION | STM32_RCC_CR_HSION |
-				STM32_RCC_CR_PLLON);
-
-		freq = STM32_HSE_CLOCK;
-
-		break;
-#endif
-	case OSC_PLL:
-		/* Ensure that source clock is stable */
-		if (pll_osc == OSC_INIT) {
-			if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) !=
-			    STM32_RCC_CFGR_SWS_PLL) {
-				STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK;
-				clock_enable_osc(OSC_HSI);
-				freq = stm32_configure_pll(OSC_HSI, STM32_PLLM,
-							   STM32_PLLN,
-							   STM32_PLLR);
-			} else {
-				/* already set PLL, skip */
-				freq = STM32_HSI_CLOCK * STM32_PLLN /
-				       STM32_PLLM / STM32_PLLR;
-				break;
-			}
-		} else {
-			clock_enable_osc(pll_osc);
-			/* Configure PLLCFGR */
-			freq = stm32_configure_pll(pll_osc, STM32_PLLM,
-						   STM32_PLLN, STM32_PLLR);
-		}
-		ASSERT(freq > 0);
-
-		/* Change to Range 1 if Freq > 26MHz */
-		if (freq > 26000000U) {
-			/* Set VCO range 1 */
-			val = STM32_RCC_CR;
-			val &= ~PWR_CR1_VOS_MSK;
-			val |= PWR_CR1_VOS_0;
-			STM32_RCC_CR = val;
-
-			/*
-			 * Set Flash latency according to frequency
-			 */
-			val = STM32_FLASH_ACR;
-			val &= ~STM32_FLASH_ACR_LATENCY_MASK;
-			if (freq <= 16000000U)	{
-				val = val;
-			} else if (freq <= 32000000U)	{
-				val |= 1;
-			} else if (freq <= 48000000U)	{
-				val |= 2;
-			} else if (freq <= 64000000U)	{
-				val |= 3;
-			} else if (freq <= 80000000U)	{
-				val |= 4;
-			} else	{
-				val |= 4;
-				CPUTS("Incorrect Frequency setting in VOS1!\n");
-			}
-			STM32_FLASH_ACR = val;
-		} else	{
-			val = STM32_FLASH_ACR;
-			val &= ~STM32_FLASH_ACR_LATENCY_MASK;
-
-			if (freq <= 6000000U) {
-				val = val;
-			} else if (freq <= 12000000U) {
-				val |= 1;
-			} else if (freq <= 18000000U) {
-				val |= 2;
-			} else if (freq <= 26000000U) {
-				val |= 3;
-			} else	{
-				val |= 4;
-				CPUTS("Incorrect Frequency setting in VOS2!\n");
-			}
-			STM32_FLASH_ACR = val;
-		}
-
-		while (val != STM32_FLASH_ACR)
-			;
-
-		/* Switch to PLL */
-		clock_switch_osc(osc);
-
-		/* TODO: Disable other sources */
-		break;
-	default:
-		break;
-	}
-
-	/* Notify modules of frequency change unless we're initializing */
-	if (current_osc != OSC_INIT) {
-		current_osc = osc;
-		hook_notify(HOOK_FREQ_CHANGE);
-	} else {
-		current_osc = osc;
-	}
-}
-
-static uint64_t clock_mask;
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	uint64_t new_mask;
-
-	if (enable)
-		new_mask = clock_mask | BIT_ULL(module);
-	else
-		new_mask = clock_mask & ~BIT_ULL(module);
-
-	/* Only change clock if needed */
-	if (new_mask != clock_mask) {
-		if (module == MODULE_ADC) {
-			STM32_RCC_APB2ENR |= STM32_RCC_PB2_SYSCFGEN;
-			STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_PWREN;
-
-			/* ADC select bit 28/29 */
-			STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK;
-			STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_ADCSEL_0 |
-					    STM32_RCC_CCIPR_ADCSEL_1);
-			/* ADC clock enable */
-			if (enable)
-				STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1;
-			else
-				STM32_RCC_AHB2ENR &= ~STM32_RCC_HB2_ADC1;
-		} else if (module == MODULE_SPI_FLASH) {
-			if (enable)
-				STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2;
-			else
-				STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2;
-		} else if (module == MODULE_SPI ||
-			   module == MODULE_SPI_CONTROLLER) {
-			if (enable)
-				STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN;
-			else if ((new_mask & (BIT(MODULE_SPI) |
-					      BIT(MODULE_SPI_CONTROLLER))) == 0)
-				STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN;
-		} else if (module == MODULE_USB) {
-#if defined(STM32_RCC_APB1ENR2_USBFSEN)
-			if (enable)
-				STM32_RCC_APB1ENR2 |=
-					STM32_RCC_APB1ENR2_USBFSEN;
-			else
-				STM32_RCC_APB1ENR2 &=
-					~STM32_RCC_APB1ENR2_USBFSEN;
-#endif
-		}
-	}
-
-	clock_mask = new_mask;
-}
-
-int clock_is_module_enabled(enum module_id module)
-{
-	return !!(clock_mask & BIT_ULL(module));
-}
-
-void rtc_init(void)
-{
-	/* Enable RTC Alarm in EXTI */
-	STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT;
-	task_enable_irq(STM32_IRQ_RTC_ALARM);
-
-	/* RTC was initilized, avoid initialization again */
-	if (STM32_RTC_ISR & STM32_RTC_ISR_INITS)
-		return;
-
-	rtc_unlock_regs();
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-	while (STM32_RTC_ISR & STM32_RTC_ISR_INITF)
-		;
-
-	/* Enable RTC alarm interrupt */
-	STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD;
-
-	rtc_lock_regs();
-}
-
-#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC)
-void rtc_set(uint32_t sec)
-{
-	struct rtc_time_reg rtc;
-
-	sec_to_rtc(sec, &rtc);
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	STM32_RTC_TR = rtc.rtc_tr;
-	STM32_RTC_DR = rtc.rtc_dr;
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-
-	rtc_lock_regs();
-}
-#endif
-
-
-void clock_init(void)
-{
-#ifdef STM32_HSE_CLOCK
-	clock_set_osc(OSC_PLL, OSC_HSE);
-#else
-#ifdef STM32_USE_PLL
-	clock_set_osc(OSC_PLL, OSC_INIT);
-#else
-	clock_set_osc(OSC_HSI, OSC_INIT);
-#endif
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	low_power_init();
-	rtc_init();
-#endif
-}
-
-static void clock_chipset_startup(void)
-{
-	/* Return to full speed */
-	clock_enable_module(MODULE_CHIPSET, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, clock_chipset_startup, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, clock_chipset_startup, HOOK_PRIO_DEFAULT);
-
-static void clock_chipset_shutdown(void)
-{
-	/* Drop to lower clock speed if no other module requires full speed */
-	clock_enable_module(MODULE_CHIPSET, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-static int command_clock(int argc, char **argv)
-{
-	if (argc >= 2) {
-		if (!strcasecmp(argv[1], "hsi"))
-			clock_set_osc(OSC_HSI, OSC_INIT);
-		else if (!strcasecmp(argv[1], "msi"))
-			clock_set_osc(OSC_MSI, OSC_INIT);
-#ifdef STM32_HSE_CLOCK
-		else if (!strcasecmp(argv[1], "hse"))
-			clock_set_osc(OSC_HSE, OSC_INIT);
-		else if (!strcasecmp(argv[1], "pll"))
-			clock_set_osc(OSC_PLL, OSC_HSE);
-#else
-		else if (!strcasecmp(argv[1], "pll"))
-			clock_set_osc(OSC_PLL, OSC_HSI);
-#endif
-		else
-			return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("Clock frequency is now %d Hz\n", freq);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | msi"
-#ifdef STM32_HSE_CLOCK
-			" | hse | pll"
-#endif
-			,
-			"Set clock frequency");
-
-uint32_t rtcss_to_us(uint32_t rtcss)
-{
-	return ((RTC_PREDIV_S - (rtcss & 0x7FFF)) * (SECOND / SCALING) /
-		(RTC_FREQ / SCALING));
-}
-
-uint32_t us_to_rtcss(uint32_t us)
-{
-	return (RTC_PREDIV_S -
-		(us * (RTC_FREQ / SCALING) / (SECOND / SCALING)));
-}
-
-
-/* Convert decimal to BCD */
-static uint8_t u8_to_bcd(uint8_t val)
-{
-	/* Fast division by 10 (when lacking HW div) */
-	uint32_t quot = ((uint32_t)val * 0xCCCD) >> 19;
-	uint32_t rem = val - quot * 10;
-
-	return rem | (quot << 4);
-}
-
-/* Convert between RTC regs in BCD and seconds */
-static uint32_t rtc_tr_to_sec(uint32_t rtc_tr)
-{
-	uint32_t sec;
-
-	/* convert the hours field */
-	sec = (((rtc_tr & RTC_TR_HT) >> RTC_TR_HT_POS) * 10 +
-	       ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) * 3600;
-	/* convert the minutes field */
-	sec += (((rtc_tr & RTC_TR_MNT) >> RTC_TR_MNT_POS) * 10 +
-		((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) * 60;
-	/* convert the seconds field */
-	sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) *  10 +
-	       (rtc_tr & RTC_TR_SU);
-	return sec;
-}
-
-static uint32_t sec_to_rtc_tr(uint32_t sec)
-{
-	uint32_t rtc_tr;
-	uint8_t hour;
-	uint8_t min;
-
-	sec %= SECS_PER_DAY;
-	/* convert the hours field */
-	hour = sec / 3600;
-	rtc_tr = u8_to_bcd(hour) << 16;
-	/* convert the minutes field */
-	sec -= hour * 3600;
-	min = sec / 60;
-	rtc_tr |= u8_to_bcd(min) << 8;
-	/* convert the seconds field */
-	sec -= min * 60;
-	rtc_tr |= u8_to_bcd(sec);
-
-	return rtc_tr;
-}
-
-/* Register setup before RTC alarm is allowed for update */
-static void pre_work_set_rtc_alarm(void)
-{
-	rtc_unlock_regs();
-
-	/* Make sure alarm is disabled */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF))
-		;
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
-	STM32_EXTI_PR = BIT(18);
-}
-
-/* Register setup after RTC alarm is updated */
-static void post_work_set_rtc_alarm(void)
-{
-	/* Enable alarm and alarm interrupt */
-	STM32_EXTI_IMR |= BIT(18);
-	STM32_EXTI_RTSR |= BIT(18);
-	STM32_RTC_CR |= (STM32_RTC_CR_ALRAE);
-
-	rtc_lock_regs();
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static struct wake_time host_wake_time;
-
-bool is_host_wake_alarm_expired(timestamp_t ts)
-{
-	return host_wake_time.ts.val &&
-	       timestamp_expired(host_wake_time.ts, &ts);
-}
-
-void restore_host_wake_alarm(void)
-{
-	if (!host_wake_time.ts.val)
-		return;
-
-	pre_work_set_rtc_alarm();
-
-	/* Set alarm time */
-	STM32_RTC_ALRMAR = host_wake_time.rtc_alrmar;
-
-	post_work_set_rtc_alarm();
-}
-
-static uint32_t rtc_dr_to_sec(uint32_t rtc_dr)
-{
-	struct calendar_date time;
-	uint32_t sec;
-
-	time.year = (((rtc_dr & 0xf00000) >> 20) * 10 +
-		    ((rtc_dr & 0xf0000) >> 16));
-	time.month = (((rtc_dr & 0x1000) >> 12) * 10 +
-		     ((rtc_dr & 0xf00) >> 8));
-	time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf);
-
-	sec = date_to_sec(time);
-
-	return sec;
-}
-
-static uint32_t sec_to_rtc_dr(uint32_t sec)
-{
-	struct calendar_date time;
-	uint32_t rtc_dr;
-
-	time = sec_to_date(sec);
-
-	rtc_dr = u8_to_bcd(time.year) << 16;
-	rtc_dr |= u8_to_bcd(time.month) << 8;
-	rtc_dr |= u8_to_bcd(time.day);
-
-	return rtc_dr;
-}
-#endif
-
-uint32_t rtc_to_sec(const struct rtc_time_reg *rtc)
-{
-	uint32_t sec = 0;
-
-#ifdef CONFIG_HOSTCMD_RTC
-	sec = rtc_dr_to_sec(rtc->rtc_dr);
-#endif
-	return sec + (rtcss_to_us(rtc->rtc_ssr) / SECOND) +
-	       rtc_tr_to_sec(rtc->rtc_tr);
-}
-
-void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc)
-{
-	rtc->rtc_dr = 0;
-#ifdef CONFIG_HOSTCMD_RTC
-	rtc->rtc_dr = sec_to_rtc_dr(sec);
-#endif
-	rtc->rtc_tr = sec_to_rtc_tr(sec);
-	rtc->rtc_ssr = 0;
-}
-
-/* Return sub-10-sec time diff between two rtc readings
- *
- * Note: this function assumes rtc0 was sampled before rtc1.
- * Additionally, this function only looks at the difference mod 10
- * seconds.
- */
-uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
-		      const struct rtc_time_reg *rtc1)
-{
-	uint32_t rtc0_val, rtc1_val, diff;
-
-	rtc0_val = (rtc0->rtc_tr & RTC_TR_SU) * SECOND +
-		   rtcss_to_us(rtc0->rtc_ssr);
-	rtc1_val = (rtc1->rtc_tr & RTC_TR_SU) * SECOND +
-		   rtcss_to_us(rtc1->rtc_ssr);
-	diff = rtc1_val;
-	if (rtc1_val < rtc0_val) {
-		/* rtc_ssr has wrapped, since we assume rtc0 < rtc1, add
-		 * 10 seconds to get the correct value
-		 */
-		diff += 10 * SECOND;
-	}
-	diff -= rtc0_val;
-	return diff;
-}
-
-void rtc_read(struct rtc_time_reg *rtc)
-{
-	/*
-	 * Read current time synchronously. Each register must be read
-	 * twice with identical values because glitches may occur for reads
-	 * close to the RTCCLK edge.
-	 */
-	do {
-		rtc->rtc_dr = STM32_RTC_DR;
-
-		do {
-			rtc->rtc_tr = STM32_RTC_TR;
-
-			do {
-				rtc->rtc_ssr = STM32_RTC_SSR;
-			} while (rtc->rtc_ssr != STM32_RTC_SSR);
-
-		} while (rtc->rtc_tr != STM32_RTC_TR);
-
-	} while (rtc->rtc_dr != STM32_RTC_DR);
-}
-
-void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
-		   struct rtc_time_reg *rtc, uint8_t save_alarm)
-{
-	uint32_t alarm_sec = 0;
-	uint32_t alarm_us = 0;
-
-	if (delay_s == EC_RTC_ALARM_CLEAR && !delay_us) {
-		reset_rtc_alarm(rtc);
-		return;
-	}
-
-	/* Alarm timeout must be within 1 day (86400 seconds) */
-	ASSERT((delay_s + delay_us / SECOND) < SECS_PER_DAY);
-
-	pre_work_set_rtc_alarm();
-	rtc_read(rtc);
-
-	/* Calculate alarm time */
-	alarm_sec = rtc_tr_to_sec(rtc->rtc_tr) + delay_s;
-
-	if (delay_us) {
-		alarm_us = rtcss_to_us(rtc->rtc_ssr) + delay_us;
-		alarm_sec = alarm_sec + alarm_us / SECOND;
-		alarm_us = alarm_us % SECOND;
-	}
-
-	/*
-	 * If seconds is greater than 1 day, subtract by 1 day to deal with
-	 * 24-hour rollover.
-	 */
-	if (alarm_sec >= SECS_PER_DAY)
-		alarm_sec -= SECS_PER_DAY;
-
-	/*
-	 * Set alarm time in seconds and check for match on
-	 * hours, minutes, and seconds.
-	 */
-	STM32_RTC_ALRMAR = sec_to_rtc_tr(alarm_sec) | 0xc0000000;
-
-	/*
-	 * Set alarm time in subseconds and check for match on subseconds.
-	 * If the caller doesn't specify subsecond delay (e.g. host command),
-	 * just align the alarm time to second.
-	 */
-	STM32_RTC_ALRMASSR = delay_us ?
-			     (us_to_rtcss(alarm_us) | 0x0f000000) : 0;
-
-#ifdef CONFIG_HOSTCMD_RTC
-	/*
-	 * If alarm is set by the host, preserve the wake time timestamp
-	 * and alarm registers.
-	 */
-	if (save_alarm) {
-		host_wake_time.ts.val = delay_s * SECOND + get_time().val;
-		host_wake_time.rtc_alrmar = STM32_RTC_ALRMAR;
-	}
-#endif
-	post_work_set_rtc_alarm();
-}
-
-uint32_t get_rtc_alarm(void)
-{
-	struct rtc_time_reg now;
-	uint32_t now_sec;
-	uint32_t alarm_sec;
-
-	if (!(STM32_RTC_CR & STM32_RTC_CR_ALRAE))
-		return 0;
-
-	rtc_read(&now);
-
-	now_sec = rtc_tr_to_sec(now.rtc_tr);
-	alarm_sec = rtc_tr_to_sec(STM32_RTC_ALRMAR & 0x3fffff);
-
-	return ((alarm_sec < now_sec) ? SECS_PER_DAY : 0) +
-	       (alarm_sec - now_sec);
-}
-
-void reset_rtc_alarm(struct rtc_time_reg *rtc)
-{
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
-
-	/* Disable RTC alarm interrupt */
-	STM32_EXTI_IMR &= ~BIT(18);
-	STM32_EXTI_PR = BIT(18);
-
-	/* Clear the pending RTC alarm IRQ in NVIC */
-	task_clear_pending_irq(STM32_IRQ_RTC_ALARM);
-
-	/* Read current time */
-	rtc_read(rtc);
-
-	rtc_lock_regs();
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-test_mockable
-void __rtc_alarm_irq(void)
-{
-	struct rtc_time_reg rtc;
-
-	reset_rtc_alarm(&rtc);
-
-#ifdef CONFIG_HOSTCMD_RTC
-	/* Wake up the host if there is a saved rtc wake alarm. */
-	if (host_wake_time.ts.val) {
-		host_wake_time.ts.val = 0;
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-	}
-#endif
-}
-DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
-
-
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t sec;
-	struct rtc_time_reg rtc;
-
-	rtc_read(&rtc);
-	sec = rtc_to_sec(&rtc);
-
-	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
-}
-
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Low power idle statistics */
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/* STOP_MODE_LATENCY: delay to wake up from STOP mode with main regulator off */
-#define STOP_MODE_LATENCY 50 /* us */
-/* PLL_LOCK_LATENCY: delay to switch from HSI to PLL */
-#define PLL_LOCK_LATENCY 150 /* us */
-/*
- * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
- * in the past, it will never wake up and cause a watchdog.
- */
-#define SET_RTC_MATCH_DELAY 120 /* us */
-
-
-void low_power_init(void)
-{
-	/* Enter stop1 mode */
-	uint32_t val;
-
-	val = STM32_PWR_CR1;
-	val &= ~PWR_CR1_LPMS_MSK;
-	val |= PWR_CR1_LPMS_STOP1;
-	STM32_PWR_CR1 = val;
-}
-
-void clock_refresh_console_in_use(void)
-{
-}
-
-void __idle(void)
-{
-	timestamp_t t0;
-	uint32_t rtc_diff;
-	int next_delay, margin_us;
-	struct rtc_time_reg rtc0, rtc1;
-
-	while (1) {
-		asm volatile("cpsid i");
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		if (DEEP_SLEEP_ALLOWED &&
-		    (next_delay > (STOP_MODE_LATENCY + PLL_LOCK_LATENCY +
-				   SET_RTC_MATCH_DELAY))) {
-			/* Deep-sleep in STOP mode */
-			idle_dsleep_cnt++;
-
-			uart_enable_wakeup(1);
-
-			/* Set deep sleep bit */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY
-						    - PLL_LOCK_LATENCY,
-				      &rtc0, 0);
-
-
-			/* ensure outstanding memory transactions complete */
-			asm volatile("dsb");
-
-			asm("wfi");
-
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			/* turn on PLL and wait until it's ready */
-			STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN;
-			clock_wait_bus_cycles(BUS_APB, 2);
-
-			stm32_configure_pll(OSC_HSI, STM32_PLLM,
-						   STM32_PLLN, STM32_PLLR);
-
-			/* Switch to PLL */
-			clock_switch_osc(OSC_PLL);
-
-			uart_enable_wakeup(0);
-
-			/* Fast forward timer according to RTC counter */
-			reset_rtc_alarm(&rtc1);
-			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
-			t0.val = t0.val + rtc_diff;
-			force_time(t0);
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += rtc_diff;
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - rtc_diff;
-			if (margin_us < 0)
-				/* Use CPUTS to save stack space */
-				CPUTS("Idle overslept!\n");
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
-		}
-		asm volatile("cpsie i");
-	}
-}
-
-/*****************************************************************************/
-/* Console commands */
-/* Print low power idle statistics. */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llus\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llus\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/stm32/clock-stm32l5.c b/chip/stm32/clock-stm32l5.c
deleted file mode 100644
index 63f5b874bc..0000000000
--- a/chip/stm32/clock-stm32l5.c
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock-stm32l4.c"
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h
deleted file mode 100644
index 3c51086c26..0000000000
--- a/chip/stm32/config-stm32f03x.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifdef CHIP_VARIANT_STM32F03X8
-#define CONFIG_FLASH_SIZE_BYTES 0x00010000
-#define CONFIG_RAM_SIZE   0x00002000
-#else
-#define CONFIG_FLASH_SIZE_BYTES 0x00008000
-#define CONFIG_RAM_SIZE   0x00001000
-#endif
-
-/* Memory mapping */
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Reduced history because of limited RAM */
-#undef CONFIG_CONSOLE_HISTORY
-#define CONFIG_CONSOLE_HISTORY 3
diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h
deleted file mode 100644
index 00bf45fde5..0000000000
--- a/chip/stm32/config-stm32f05x.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES (64 * 1024)
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00002000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Reduced history because of limited RAM */
-#undef CONFIG_CONSOLE_HISTORY
-#define CONFIG_CONSOLE_HISTORY 3
diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h
deleted file mode 100644
index 918a117a22..0000000000
--- a/chip/stm32/config-stm32f07x.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES (128 * 1024)
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Reduced history because of limited RAM */
-#undef CONFIG_CONSOLE_HISTORY
-#define CONFIG_CONSOLE_HISTORY 3
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
-#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 2
diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h
deleted file mode 100644
index 9dc27a1fb2..0000000000
--- a/chip/stm32/config-stm32f09x.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-/*
- * Flash physical size: 256KB
- * Write protect sectors: 31 4KB sectors, one 132KB sector
- */
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00008000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/*
- * STM32F09x flash layout:
- * - RO image starts at the beginning of flash: sector 0 ~ 29
- * - PSTATE immediately follows the RO image: sector 30
- * - RW image starts at 0x1f00: sector 31
- * - Protected region consists of the RO image + PSTATE: sector 0 ~ 30
- * - Unprotected region consists of second half of RW image
- *
- *                            PSTATE(4KB)
- *                              |
- *          (124KB)             v            (132KB)
- * |<-----Protected Region------>|<------Unprotected Region----->|
- * |<--------RO image--------->| |<----------RW image----------->|
- * 0        (120KB)            ^ ^
- *                             | |
- *                             | 31(132KB sector)
- *                             |
- *                             30
- *
- */
-
-#define _SECTOR_4KB             (4 * 1024)
-#define _SECTOR_132KB           (132 * 1024)
-
-/* The EC uses one sector to emulate persistent state */
-#define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE   _SECTOR_4KB
-#define CONFIG_FW_PSTATE_OFF    (30 * _SECTOR_4KB)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (30 * _SECTOR_4KB)
-#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \
-				 CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE          _SECTOR_132KB
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (CONFIG_FLASH_SIZE_BYTES - \
-					  CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF   CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE  CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* We map each write protect sector to a bank */
-#define PHYSICAL_BANKS          32
-#define WP_BANK_COUNT           31
-#define PSTATE_BANK             30
-#define PSTATE_BANK_COUNT       1
-
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h
deleted file mode 100644
index 3df5bfce67..0000000000
--- a/chip/stm32/config-stm32f373.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x2000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00008000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 81
-
-/* STM32F3 uses the older 4 byte aligned access mechanism */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
-#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h
deleted file mode 100644
index 73c9a3694f..0000000000
--- a/chip/stm32/config-stm32f4.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#ifdef CHIP_VARIANT_STM32F412
-#	define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024)
-#else
-#	define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#endif
-
-/* 3 regions type: 16K, 64K and 128K */
-#define SIZE_16KB (16 * 1024)
-#define SIZE_64KB (64 * 1024)
-#define SIZE_128KB (128 * 1024)
-#define CONFIG_FLASH_REGION_TYPE_COUNT 3
-#define CONFIG_FLASH_MULTIPLE_REGION \
-	(5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB)
-
-/* Erasing 128K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/* minimum write size for 3.3V. 1 for 1.8V */
-#define STM32_FLASH_WRITE_SIZE_1800 1
-#define STM32_FLASH_WS_DIV_1800 16000000
-#define STM32_FLASH_WRITE_SIZE_3300 4
-#define STM32_FLASH_WS_DIV_3300 30000000
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
-
-#ifdef CHIP_VARIANT_STM32F412
-#	define CONFIG_RAM_BASE  0x20000000
-#	define CONFIG_RAM_SIZE  0x00040000 /* 256 KB */
-#else
-#	define CONFIG_RAM_BASE  0x20000000
-#	define CONFIG_RAM_SIZE  0x00020000 /* 128 KB */
-#endif
-
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(256 * 1024)
-#define CONFIG_RW_MEM_OFF	(256 * 1024)
-#define CONFIG_RW_SIZE		(256 * 1024)
-
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#define CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Use OTP regions */
-#define CONFIG_OTP
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	97
-
-#undef CONFIG_CMD_CHARGEN
diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h
deleted file mode 100644
index d027ad62fb..0000000000
--- a/chip/stm32/config-stm32f76x.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES       (2048 * 1024)
-
-/* 3 regions type: 32K, 128K and 256K */
-#define SIZE_32KB (32 * 1024)
-#define SIZE_128KB (128 * 1024)
-#define SIZE_256KB (256 * 1024)
-#define CONFIG_FLASH_REGION_TYPE_COUNT 3
-#define CONFIG_FLASH_MULTIPLE_REGION \
-	(5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB)
-
-/* Erasing 256K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/* minimum write size for 3.3V. 1 for 1.8V */
-#define STM32_FLASH_WRITE_SIZE_1800 1
-#define STM32_FLASH_WS_DIV_1800 16000000
-#define STM32_FLASH_WRITE_SIZE_3300 4
-#define STM32_FLASH_WS_DIV_3300 30000000
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
-
-/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/
-/* SRAM1:    368kB 0x20020000 - 0x2007BFFF */
-/* SRAM2:     16kB 0x2007C000 - 0x2007FFFF */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00080000
-
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(1024 * 1024)
-#define CONFIG_RW_MEM_OFF	(1024 * 1024)
-#define CONFIG_RW_SIZE		(1024 * 1024)
-
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#define CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	109
diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h
deleted file mode 100644
index 4f1ed96871..0000000000
--- a/chip/stm32/config-stm32g41xb.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Memory mapping for STM32G431xb. The STM32G431xb is a category 2 device within
- * the STM32G4 chip family. Category 2 devices have either 32, 64, or 128 kB of
- * internal flash. The 'xB' indicates 128 kB of internal flash.
- *
- * STM32G431x is a single bank only device consisting of 64 pages of 2 kB
- * each. It supports both a mass erase or page erase feature. Note that
- * CONFIG_FLASH_BANK_SIZE is consistent with page size as defined in RM0440 TRM
- * for the STM32G4 chip family. The minimum erase size is 1 page.
- *
- * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support
- * PSTATE in single bank memories with a write size > 4 bytes.
- */
-
-#define CONFIG_FLASH_SIZE_BYTES       (128 * 1024)
-#define CONFIG_FLASH_WRITE_SIZE 0x0004
-#define CONFIG_FLASH_BANK_SIZE (2 * 1024)
-#define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE
-
-
-/* Erasing 128K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/* No page mode on STM32G4, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
-
-/*
- * STM32G431x6/x8/xB devices feature 32 Kbytes of embedded SRAM. This SRAM
- * is split into three blocks:
- * • 16 Kbytes mapped at address 0x2000 0000 (SRAM1).
- * •  6 Kbytes mapped at address 0x2000 4000 (SRAM2).
- * • 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased
- *   at 0x2000 5800 address to be accessed by all bus controllers.
- */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00008000
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	3
-
-/* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */
-#define DMAC_COUNT 12
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#define CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	101
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
-#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 2
diff --git a/chip/stm32/config-stm32g473xc.h b/chip/stm32/config-stm32g473xc.h
deleted file mode 100644
index 1cb5133121..0000000000
--- a/chip/stm32/config-stm32g473xc.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Memory mapping for STM32G473xc. The STM32G473xc is a category 1 device within
- * the STM32G4 chip family. Category 1 devices have either 128, 256, or 512 kB
- * of internal flash. 'xc' indicates 256 kB of internal flash.
- *
- * STM32G473xc can be configured via option bytes as either a single bank or
- * dual bank device. Dual bank is the default selection.
- * CONFIG_FLASH_BANK_SIZE is consistent with page size as defined in RM0440 TRM
- * for the STM32G4 chip family. In dual bank mode, the flash is organized in 2
- * kB pages, with 64 pages per bank for this variant.
- *
- * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support
- * PSTATE in single bank memories with a write size > 4 bytes.
- *
- * TODO(b/181874494): Verify that dual bank mode should be used, or add support
- * for enabling single bank mode on STM32G473xc.
- */
-#define CONFIG_FLASH_SIZE_BYTES (256 * 1024)
-#define CONFIG_FLASH_WRITE_SIZE 0x0004
-#define CONFIG_FLASH_BANK_SIZE (2 * 1024)
-#define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE
-
-/* Dual-bank (DBANK) mode is enabled by default for this chip */
-#define STM32_FLASH_DBANK_MODE
-
-/* Erasing 128K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/* No page mode on STM32G4, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
-
-/*
- * STM32G473xc is a category 3 SRAM device featuring 128 Kbytes of embedded
- * SRAM. This SRAM is split into three blocks:
- * • 80 Kbytes mapped at address 0x2000 0000 (SRAM1).
- * • 16 Kbytes mapped at address 0x2001 4000 (SRAM2).
- * • 32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased
- *   at 0x2001 8000 address to be accessed by all bus controllers.
- */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00020000
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */
-#define DMAC_COUNT 12
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#define CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	101
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
-#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 2
diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h
deleted file mode 100644
index da94b09069..0000000000
--- a/chip/stm32/config-stm32h7x3.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES       (2048 * 1024)
-#define CONFIG_FLASH_ERASE_SIZE (128 * 1024)  /* erase bank size */
-/* always use 256-bit writes due to ECC */
-#define CONFIG_FLASH_WRITE_SIZE          32   /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE    32
-
-/*
- * What the code is calling 'bank' is really the size of the block used for
- * write-protected, here it's 128KB sector (same as erase size).
- */
-#define CONFIG_FLASH_BANK_SIZE  (128 * 1024)
-
-/* Erasing 128K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/*       ITCM-RAM:  64kB 0x00000000 - 0x0000FFFF (CPU and MDMA) */
-/*       DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF (CPU and MDMA) */
-/* (D1) AXI-SRAM : 512kB 0x24000000 - 0x2407FFFF (no BDMA) */
-/* (D2) AHB-SRAM1: 128kB 0x30000000 - 0x3001FFFF */
-/* (D2) AHB-SRAM2: 128kB 0x30020000 - 0x3003FFFF */
-/* (D2) AHB-SRAM3:  32kB 0x30040000 - 0x30047FFF */
-/* (D3) AHB-SRAM4:  64kB 0x38000000 - 0x3800FFFF */
-/* (D3) backup RAM:  4kB 0x38800000 - 0x38800FFF */
-#define CONFIG_RAM_BASE		0x24000000
-#define CONFIG_RAM_SIZE		0x00080000
-
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(128 * 1024)
-#define CONFIG_RW_MEM_OFF	(CONFIG_FLASH_SIZE_BYTES / 2)
-#define CONFIG_RW_SIZE		(512 * 1024)
-
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/*
- * Cannot use PSTATE:
- * 128kB blocks are too large and ECC prevents re-writing PSTATE word.
- */
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	150
-
-/* the Cortex-M7 core has 'standard' ARMv7-M caches */
-#define CONFIG_ARMV7M_CACHE
-/* Use the MPU to configure cacheability */
-#define CONFIG_MPU
-/* Store in uncached buffers for DMA transfers in ahb4 region */
-#define CONFIG_CHIP_UNCACHED_REGION ahb4
-/* Override MPU attribute settings to match the chip requirements */
-/* Code is Normal memory type / non-shareable / write-through */
-#define MPU_ATTR_FLASH_MEMORY  0x02
-/* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */
-#define MPU_ATTR_INTERNAL_SRAM 0x0B
diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h
deleted file mode 100644
index 2c4efcc6df..0000000000
--- a/chip/stm32/config-stm32l100.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES 0x00020000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
-
-/*
- * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at
- * a time), but that's really slow, and older host interfaces which can't ask
- * about the ideal size would then end up writing in that mode instead of the
- * faster page mode.  So lie about the write size for now.  Once all software
- * (flashrom, u-boot, ectool) which cares has been updated to know about ver.1
- * of EC_CMD_GET_FLASH_INFO, we can remove this workaround.
- */
-#define CONFIG_FLASH_WRITE_SIZE 0x0080
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00002800
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 45
-
-/* Flash erases to 0, not 1 */
-#define CONFIG_FLASH_ERASED_VALUE32 0
-
-/* Use DMA for UART receive */
-#define CONFIG_UART_RX_DMA
-
-/* Fake hibernate mode */
-#define CONFIG_STM32L_FAKE_HIBERNATE
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
-#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h
deleted file mode 100644
index 0b32f95572..0000000000
--- a/chip/stm32/config-stm32l15x.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES 0x00020000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
-
-/*
- * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at
- * a time), but that's really slow, and older host interfaces which can't ask
- * about the ideal size would then end up writing in that mode instead of the
- * faster page mode.  So lie about the write size for now.  Once all software
- * (flashrom, u-boot, ectool) which cares has been updated to know about ver.1
- * of EC_CMD_GET_FLASH_INFO, we can remove this workaround.
- */
-#define CONFIG_FLASH_WRITE_SIZE 0x0080
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 45
-
-/* Lots of RAM, so use bigger UART buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-
-/* Use DMA for UART receive */
-#define CONFIG_UART_RX_DMA
-
-/* Flash erases to 0, not 1 */
-#define CONFIG_FLASH_ERASED_VALUE32 0
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
-#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config-stm32l431.h b/chip/stm32/config-stm32l431.h
deleted file mode 100644
index 7021bc2ce8..0000000000
--- a/chip/stm32/config-stm32l431.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000   /* 256 kB */
-#define CONFIG_FLASH_BANK_SIZE \
-	0x800 /* 2 kB. NOTE: BANK in chrome-ec means page */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
-
-/*
- * SRAM1 (48kB) at 0x20000000
- * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
- * so they are contiguous.
- */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 82
-
-/*
- * STM32L431 flash layout:
- * - RO image starts at the beginning of flash: sector 0 ~ 61
- * - PSTATE immediately follows the RO image: sector 62
- * - RW image starts at 0x1f800: sector 63
- * - Protected region consists of the RO image + PSTATE: sector 0 ~ 62
- * - Unprotected region consists of second half of RW image
- *
- *                            PSTATE(2KB)
- *                              |
- *          (126KB)             v            (130KB)
- * |<-----Protected Region------>|<------Unprotected Region----->|
- * |<--------RO image--------->| |<----------RW image----------->|
- * 0        (124KB)            ^ ^
- *                             | |
- *                             | 63(2KB sector)
- *                             |
- *                             62
- *
- */
-
-
-
-/* The EC uses one sector to emulate persistent state */
-#define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (62 * CONFIG_FLASH_BANK_SIZE)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (62 * CONFIG_FLASH_BANK_SIZE)
-#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \
-				 CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE          (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - \
-                                 CONFIG_RW_STORAGE_OFF)
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (CONFIG_FLASH_SIZE_BYTES - \
-					  CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF   CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE  CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* We map each write protect sector to a bank */
-#define PHYSICAL_BANKS          128
-#define WP_BANK_COUNT           63
-#define PSTATE_BANK             62
-#define PSTATE_BANK_COUNT       1
diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h
deleted file mode 100644
index 54ba9bac8d..0000000000
--- a/chip/stm32/config-stm32l442.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000   /* 256 kB */
-#define CONFIG_FLASH_BANK_SIZE  0x800   /* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
-
-/*
- * SRAM1 (48kB) at 0x20000000
- * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
- * so they are contiguous.
- */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 82
diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h
deleted file mode 100644
index 2e0084fd94..0000000000
--- a/chip/stm32/config-stm32l476.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES 0x00100000	/* 1 MB */
-#define CONFIG_FLASH_BANK_SIZE  0x800	/* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800	/* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8	/* 64 bits (without 8 bits ECC) */
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100	/* 256 (32 double words) */
-
-#define CONFIG_RAM_BASE         0x20000000
-/* Only using SRAM1. SRAM2 (32 KB) is ignored. */
-#define CONFIG_RAM_SIZE         0x00018000	/* 96 kB */
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 82
diff --git a/chip/stm32/config-stm32l552xe.h b/chip/stm32/config-stm32l552xe.h
deleted file mode 100644
index 6953df3950..0000000000
--- a/chip/stm32/config-stm32l552xe.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES  0x00080000   /* 512 kB */
-#define CONFIG_FLASH_BANK_SIZE  0x800   /* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
-
-/*
- * SRAM1 (48kB) at 0x20000000
- * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
- * so they are contiguous.
- */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 109
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x4000D800
-#define CONFIG_USB_RAM_SIZE        1024
-#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 4
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/* Number of DMA channels supported (8 channels each for DMA1 and DMA2) */
-#define DMAC_COUNT 16
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
deleted file mode 100644
index 4d630909e1..0000000000
--- a/chip/stm32/config_chip.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#ifdef CHIP_FAMILY_STM32F0
-/* CPU core BFD configuration */
-#include "core/cortex-m0/config_core.h"
-/* IRQ priorities */
-#define STM32_IRQ_EXT0_1_PRIORITY	1
-#define STM32_IRQ_EXT2_3_PRIORITY	1
-#define STM32_IRQ_EXTI4_15_PRIORITY	1
-#else
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-#define STM32_IRQ_EXTI0_PRIORITY	1
-#define STM32_IRQ_EXTI1_PRIORITY	1
-#define STM32_IRQ_EXTI2_PRIORITY	1
-#define STM32_IRQ_EXTI3_PRIORITY	1
-#define STM32_IRQ_EXTI4_PRIORITY	1
-#define STM32_IRQ_EXTI9_5_PRIORITY	1
-#define STM32_IRQ_EXTI15_10_PRIORITY	1
-#endif
-
-/* Default to UART 1 for EC console */
-#define CONFIG_UART_CONSOLE 1
-
-/* Use variant specific configuration for flash / UART / IRQ */
-/* STM32F03X8 it itself a variant of STM32F03X with non-default flash sizes */
-#ifdef CHIP_VARIANT_STM32F03X8
-#define CHIP_VARIANT_STM32F03X
-#endif
-
-/* Number of I2C ports, can be overridden in variant */
-#define I2C_PORT_COUNT 2
-
-#if defined(CHIP_VARIANT_STM32L476)
-#include "config-stm32l476.h"
-#elif defined(CHIP_VARIANT_STM32L15X)
-#include "config-stm32l15x.h"
-#elif defined(CHIP_VARIANT_STM32L100)
-#include "config-stm32l100.h"
-#elif defined(CHIP_VARIANT_STM32L442)
-#include "config-stm32l442.h"
-#elif defined(CHIP_VARIANT_STM32L552XE)
-#include "config-stm32l552xe.h"
-#elif defined(CHIP_VARIANT_STM32F76X)
-#include "config-stm32f76x.h"
-#elif defined(CHIP_FAMILY_STM32F4)
-/* STM32F4 family */
-#include "config-stm32f4.h"
-#elif defined(CHIP_VARIANT_STM32F373)
-#include "config-stm32f373.h"
-#elif defined(CHIP_VARIANT_STM32F09X)
-/* STM32F09xx */
-#include "config-stm32f09x.h"
-#elif defined(CHIP_VARIANT_STM32F07X) || defined(CHIP_VARIANT_STM32F070)
-/* STM32F07xx */
-#include "config-stm32f07x.h"
-#elif defined(CHIP_VARIANT_STM32F05X)
-/* STM32F05xx */
-#include "config-stm32f05x.h"
-#elif defined(CHIP_VARIANT_STM32F03X)
-/* STM32F03x */
-#include "config-stm32f03x.h"
-#elif defined(CHIP_VARIANT_STM32H7X3)
-#include "config-stm32h7x3.h"
-#elif defined(CHIP_VARIANT_STM32G431XB)
-#include "config-stm32g41xb.h"
-#elif defined(CHIP_VARIANT_STM32G473XC)
-#include "config-stm32g473xc.h"
-#elif defined(CHIP_VARIANT_STM32L431X)
-#include "config-stm32l431.h"
-#else
-#error "Unsupported chip variant"
-#endif
-
-#define CONFIG_PROGRAM_MEMORY_BASE 0x08000000
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-#if !defined(CHIP_FAMILY_STM32F4) && \
-	!defined(CHIP_FAMILY_STM32F7) && \
-	!defined(CHIP_FAMILY_STM32H7) && \
-	!defined(CHIP_VARIANT_STM32F09X) && \
-	!defined(CHIP_VARIANT_STM32L431X)
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-#endif
-
-/* Additional special purpose regions (USB RAM and other special SRAMs) */
-#define CONFIG_CHIP_MEMORY_REGIONS
-
-/* System stack size */
-#if defined(CHIP_VARIANT_STM32F05X)
-#define CONFIG_STACK_SIZE 768
-#else
-#define CONFIG_STACK_SIZE 1024
-#endif
-
-/* Idle task stack size */
-#define IDLE_TASK_STACK_SIZE 256
-
-/* Smaller task stack size */
-#define SMALLER_TASK_STACK_SIZE 384
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-/* Larger task stack size, for hook task */
-#define LARGER_TASK_STACK_SIZE 640
-
-/* Even bigger */
-#define VENTI_TASK_STACK_SIZE 768
-#define ULTRA_TASK_STACK_SIZE 1056
-#define TRENTA_TASK_STACK_SIZE 1184
-
-/*
- * Console stack size. For test builds, the console is used to interact with
- * the test, and insufficient stack size causes console stack overflow after
- * running the on-device tests.
- */
-#define CONSOLE_TASK_STACK_SIZE 4096
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/*
- * Use a timer to print a watchdog warning event before the actual watchdog
- * timer fires.  This is needed on STM32, where the independent watchdog has no
- * early warning feature and the windowed watchdog has a very short period.
- */
-#define CONFIG_WATCHDOG_HELP
-
-/* Use DMA */
-#define CONFIG_DMA
-
-/* STM32 features RTC (optional feature) */
-#define CONFIG_RTC
-
-/* Number of peripheral request signals per DMA channel */
-#define STM32_DMA_PERIPHERALS_PER_CHANNEL	4
-
-/*
- * Use DMA for UART transmit for all platforms.  DMA for UART receive is
- * enabled on a per-chip basis because it doesn't seem to work reliably on
- * STM32F (see crosbug.com/p/24141).
- */
-#define CONFIG_UART_TX_DMA
-
-#ifndef CHIP_FAMILY_STM32H7
-/* Flash protection applies to the next boot, not the current one */
-#define CONFIG_FLASH_PROTECT_NEXT_BOOT
-#endif /* !CHIP_FAMILY_STM32H7 */
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_NAME_BY_PIN(port, index) #port#index
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-/* Prescaler values for PLL. Currently used only by STM32L476 and STM32L431. */
-#define STM32_PLLM	1
-#define STM32_PLLN	1
-#define STM32_PLLR	1
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h
deleted file mode 100644
index 2a50d5760e..0000000000
--- a/chip/stm32/crc_hw.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CRC_HW_H
-#define __CROS_EC_CRC_HW_H
-/* CRC-32 hardware implementation with USB constants */
-
-#include "clock.h"
-#include "registers.h"
-
-static inline void crc32_init(void)
-{
-	/* switch on CRC controller */
-	STM32_RCC_AHBENR |= BIT(6); /* switch on CRC controller */
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-	/* reset CRC state */
-	STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT
-		     | STM32_CRC_CR_REV_IN_WORD;
-	while (STM32_CRC_CR & 1)
-		;
-}
-
-static inline void crc32_hash32(uint32_t val)
-{
-	STM32_CRC_DR = val;
-}
-
-static inline void crc32_hash16(uint16_t val)
-{
-	STM32_CRC_DR16 = val;
-}
-
-static inline uint32_t crc32_result(void)
-{
-	return STM32_CRC_DR ^ 0xFFFFFFFF;
-}
-
-#endif /* __CROS_EC_CRC_HW_H */
diff --git a/chip/stm32/debug_printf.c b/chip/stm32/debug_printf.c
deleted file mode 100644
index c4e151692c..0000000000
--- a/chip/stm32/debug_printf.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Synchronous UART debug printf */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "printf.h"
-#include "registers.h"
-#include "util.h"
-
-static int debug_txchar(void *context, int c)
-{
-	if (c == '\n') {
-		while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE))
-			;
-		STM32_USART_TDR(UARTN_BASE) = '\r';
-	}
-
-	/* Wait for space to transmit */
-	while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE))
-		;
-	STM32_USART_TDR(UARTN_BASE) = c;
-
-	return 0;
-}
-
-
-
-void debug_printf(const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(debug_txchar, NULL, format, args);
-	va_end(args);
-}
-
-#ifdef CONFIG_COMMON_RUNTIME
-void cflush(void)
-{
-	/* Wait for transmit complete */
-	while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC))
-		;
-}
-
-int cputs(enum console_channel channel, const char *outstr)
-{
-	debug_printf(outstr);
-
-	return 0;
-}
-
-void panic_puts(const char *outstr)
-{
-	debug_printf(outstr);
-	cflush();
-}
-
-int cprintf(enum console_channel channel, const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(debug_txchar, NULL, format, args);
-	va_end(args);
-
-	return 0;
-}
-
-void panic_printf(const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(debug_txchar, NULL, format, args);
-	va_end(args);
-
-	cflush();
-}
-
-int cprints(enum console_channel channel, const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(debug_txchar, NULL, format, args);
-	va_end(args);
-
-	debug_printf("\n");
-
-	return 0;
-}
-
-void uart_init(void)
-{
-	/* Enable USART1 clock */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1;
-	/* set baudrate */
-	STM32_USART_BRR(UARTN_BASE) =
-		DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE);
-	/* UART enabled, 8 Data bits, oversampling x16, no parity */
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
-	/* 1 stop bit, no fancy stuff */
-	STM32_USART_CR2(UARTN_BASE) = 0x0000;
-	/* DMA disabled, special modes disabled, error interrupt disabled */
-	STM32_USART_CR3(UARTN_BASE) = 0x0000;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_UART, 1);
-}
-#endif
diff --git a/chip/stm32/debug_printf.h b/chip/stm32/debug_printf.h
deleted file mode 100644
index 6091cfc7fc..0000000000
--- a/chip/stm32/debug_printf.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Synchronous UART debug printf */
-
-#ifndef __CROS_EC_DEBUG_H
-#define __CROS_EC_DEBUG_H
-
-#ifdef CONFIG_DEBUG_PRINTF
-__attribute__((__format__(__printf__, 1, 2)))
-void debug_printf(const char *format, ...);
-#else
-#define debug_printf(...)
-#endif
-
-#endif /* __CROS_EC_DEBUG_H */
diff --git a/chip/stm32/dma-stm32f4.c b/chip/stm32/dma-stm32f4.c
deleted file mode 100644
index 860874de8c..0000000000
--- a/chip/stm32/dma-stm32f4.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
-
-stm32_dma_regs_t *STM32_DMA_REGS[] = { STM32_DMA1_REGS, STM32_DMA2_REGS };
-
-/* Callback data to use when IRQ fires */
-static struct {
-	void (*cb)(void *);	/* Callback function to call */
-	void *cb_data;		/* Callback data for callback function */
-} dma_irq[STM32_DMAS_TOTAL_COUNT];
-
-/**
- * Return the IRQ for the DMA stream
- *
- * @param stream	stream number
- * @return IRQ for the stream
- */
-static int dma_get_irq(enum dma_channel stream)
-{
-	if (stream < STM32_DMA1_STREAM6)
-		return STM32_IRQ_DMA1_STREAM0 + stream;
-	if (stream == STM32_DMA1_STREAM7)
-		return STM32_IRQ_DMA1_STREAM7;
-	if (stream < STM32_DMA2_STREAM5)
-		return STM32_IRQ_DMA2_STREAM0 + stream - STM32_DMA2_STREAM0;
-	else
-		return STM32_IRQ_DMA2_STREAM5 + stream - STM32_DMA2_STREAM5;
-}
-
-stm32_dma_regs_t *dma_get_ctrl(enum dma_channel stream)
-{
-	return STM32_DMA_REGS[stream / STM32_DMAS_COUNT];
-}
-
-stm32_dma_stream_t *dma_get_channel(enum dma_channel stream)
-{
-	stm32_dma_regs_t *dma = dma_get_ctrl(stream);
-
-	return &dma->stream[stream % STM32_DMAS_COUNT];
-}
-
-#ifdef CHIP_FAMILY_STM32H7
-void dma_select_channel(enum dma_channel channel, uint8_t req)
-{
-	STM2_DMAMUX_CxCR(DMAMUX1, channel) = req;
-}
-#endif
-
-void dma_disable(enum dma_channel ch)
-{
-	stm32_dma_stream_t *stream = dma_get_channel(ch);
-
-	if (stream->scr & STM32_DMA_CCR_EN) {
-		stream->scr &= ~STM32_DMA_CCR_EN;
-		while (stream->scr & STM32_DMA_CCR_EN)
-			;
-	}
-}
-
-void dma_disable_all(void)
-{
-	int ch;
-
-	for (ch = 0; ch < STM32_DMAS_TOTAL_COUNT; ch++)
-		dma_disable(ch);
-}
-
-/**
- * Prepare a stream for use and start it
- *
- * @param stream	stream to read
- * @param count		Number of bytes to transfer
- * @param periph	Pointer to peripheral data register
- * @param memory	Pointer to memory address for receive/transmit
- * @param flags		DMA flags for the control register.
- */
-static void prepare_stream(enum dma_channel stream, unsigned count,
-		void *periph, void *memory, unsigned flags)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-	uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
-
-	dma_disable(stream);
-	dma_clear_isr(stream);
-
-	/* Following the order in DocID026448 Rev 1 (RM0383) p181 */
-	dma_stream->spar = (uint32_t)periph;
-	dma_stream->sm0ar = (uint32_t)memory;
-	dma_stream->sndtr = count;
-	dma_stream->scr = ccr;
-	ccr |= flags & STM32_DMA_CCR_CHANNEL_MASK;
-	dma_stream->scr = ccr;
-	dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS;
-	ccr |= flags;
-	dma_stream->scr = ccr;
-}
-
-void dma_go(stm32_dma_stream_t *stream)
-{
-	/* Flush data in write buffer so that DMA can get the latest data */
-	asm volatile("dsb;");
-
-	/* Fire it up */
-	stream->scr |= STM32_DMA_CCR_EN;
-}
-
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
-		    const void *memory)
-{
-	/*
-	 * Cast away const for memory pointer; this is ok because we know
-	 * we're preparing the stream for transmit.
-	 */
-	prepare_stream(option->channel, count, option->periph, (void *)memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P |
-			option->flags);
-}
-
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
-{
-	stm32_dma_stream_t *stream = dma_get_channel(option->channel);
-
-	prepare_stream(option->channel, count, option->periph, memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M |
-			option->flags);
-	dma_go(stream);
-}
-
-int dma_bytes_done(stm32_dma_stream_t *stream, int orig_count)
-{
-	/*
-	 * Note that we're intentionally not checking that DMA is enabled here
-	 * because there is a race when the hardware stops the transfer:
-	 *
-	 * From Section 9.3.14 DMA transfer completion in RM0402 Rev 5
-	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf:
-	 * If the stream is configured in non-circular mode, after the end of
-	 * the transfer (that is when the number of data to be transferred
-	 * reaches zero), the DMA is stopped (EN bit in DMA_SxCR register is
-	 * cleared by Hardware) and no DMA request is served unless the software
-	 * reprograms the stream and re-enables it (by setting the EN bit in the
-	 * DMA_SxCR register).
-	 *
-	 * See http://b/132444384 for full details.
-	 */
-	return orig_count - stream->sndtr;
-}
-
-bool dma_is_enabled(stm32_dma_stream_t *stream)
-{
-	return (stream->scr & STM32_DMA_CCR_EN);
-}
-
-#ifdef CONFIG_DMA_HELP
-void dma_dump(enum dma_channel stream)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-
-	CPRINTF("scr=%x, sndtr=%x, spar=%x, sm0ar=%x, sfcr=%x\n",
-		dma_stream->scr, dma_stream->sndtr, dma_stream->spar,
-		dma_stream->sm0ar, dma_stream->sfcr);
-	CPRINTF("stream %d, isr=%x, ifcr=%x\n",
-		stream,
-		STM32_DMA_GET_ISR(stream),
-		STM32_DMA_GET_IFCR(stream));
-}
-
-void dma_check(enum dma_channel stream, char *buf)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-	int count;
-	int i;
-
-	count = dma_stream->sndtr;
-	CPRINTF("c=%d\n", count);
-	udelay(100 * MSEC);
-	CPRINTF("c=%d\n", dma_stream->sndtr);
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", buf[i]);
-	udelay(100 * MSEC);
-	CPRINTF("c=%d\n", dma_stream->sndtr);
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", buf[i]);
-}
-
-/* Run a check of memory-to-memory DMA */
-void dma_test(enum dma_channel stream)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-	uint32_t ctrl;
-	char periph[32], memory[32];
-	unsigned count = sizeof(periph);
-	int i;
-
-	memset(memory, '\0', sizeof(memory));
-	for (i = 0; i < count; i++)
-		periph[i] = 10 + i;
-
-	dma_clear_isr(stream);
-	/* Following the order in Doc ID 15965 Rev 5 p194 */
-	dma_stream->spar = (uint32_t)periph;
-	dma_stream->sm0ar = (uint32_t)memory;
-	dma_stream->sndtr = count;
-	dma_stream->sfcr  &= ~STM32_DMA_SFCR_DMDIS;
-	ctrl = STM32_DMA_CCR_PL_MEDIUM;
-	dma_stream->scr = ctrl;
-
-	ctrl |= STM32_DMA_CCR_MINC;
-	ctrl |= STM32_DMA_CCR_DIR_M2M;
-	ctrl |= STM32_DMA_CCR_PINC;
-
-	dma_stream->scr = ctrl;
-	dma_dump(stream);
-	dma_stream->scr = ctrl | STM32_DMA_CCR_EN;
-
-	for (i = 0; i < count; i++)
-		CPRINTF("%d/%d ", periph[i], memory[i]);
-	CPRINTF("\ncount=%d\n", dma_stream->sndtr);
-	dma_dump(stream);
-}
-#endif /* CONFIG_DMA_HELP */
-
-void dma_init(void)
-{
-	STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA1 | STM32_RCC_HB1_DMA2;
-}
-
-int dma_wait(enum dma_channel stream)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
-	while ((STM32_DMA_GET_ISR(stream) & STM32_DMA_TCIF) == 0) {
-		if (deadline.val <= get_time().val)
-			return EC_ERROR_TIMEOUT;
-
-		udelay(DMA_POLLING_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-static inline void _dma_wake_callback(void *cb_data)
-{
-	task_id_t id = (task_id_t)(int)cb_data;
-
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_DMA_TC);
-}
-
-void dma_enable_tc_interrupt(enum dma_channel stream)
-{
-	dma_enable_tc_interrupt_callback(stream, _dma_wake_callback,
-					 (void *)(int)task_get_current());
-}
-
-void dma_enable_tc_interrupt_callback(enum dma_channel stream,
-				      void (*callback)(void *),
-				      void *callback_data)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-
-	dma_irq[stream].cb = callback;
-	dma_irq[stream].cb_data = callback_data;
-
-	dma_stream->scr |= STM32_DMA_CCR_TCIE;
-	task_enable_irq(dma_get_irq(stream));
-}
-
-void dma_disable_tc_interrupt(enum dma_channel stream)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-
-	dma_stream->scr &= ~STM32_DMA_CCR_TCIE;
-	task_disable_irq(dma_get_irq(stream));
-
-	dma_irq[stream].cb = NULL;
-	dma_irq[stream].cb_data = NULL;
-}
-
-void dma_clear_isr(enum dma_channel stream)
-{
-	STM32_DMA_SET_IFCR(stream, STM32_DMA_ALL);
-}
-
-#ifdef CONFIG_DMA_DEFAULT_HANDLERS
-#define STM32_DMA_IDX(dma, x)   CONCAT4(STM32_DMA, dma, _STREAM, x)
-#define STM32_DMA_FCT(dma, x)   CONCAT4(dma_, dma, _event_interrupt_stream_, x)
-#define DECLARE_DMA_IRQ(dma, x) \
-	void STM32_DMA_FCT(dma, x)(void) \
-	{ \
-		dma_clear_isr(STM32_DMA_IDX(dma, x)); \
-		if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \
-			(*dma_irq[STM32_DMA_IDX(dma, x)].cb) \
-				(dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \
-	} \
-	DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \
-		    STM32_DMA_FCT(dma, x), 1);
-
-DECLARE_DMA_IRQ(1, 0);
-DECLARE_DMA_IRQ(1, 1);
-DECLARE_DMA_IRQ(1, 2);
-DECLARE_DMA_IRQ(1, 3);
-DECLARE_DMA_IRQ(1, 4);
-DECLARE_DMA_IRQ(1, 5);
-DECLARE_DMA_IRQ(1, 6);
-DECLARE_DMA_IRQ(1, 7);
-DECLARE_DMA_IRQ(2, 0);
-DECLARE_DMA_IRQ(2, 1);
-DECLARE_DMA_IRQ(2, 2);
-DECLARE_DMA_IRQ(2, 3);
-DECLARE_DMA_IRQ(2, 4);
-DECLARE_DMA_IRQ(2, 5);
-DECLARE_DMA_IRQ(2, 6);
-DECLARE_DMA_IRQ(2, 7);
-
-#endif /* CONFIG_DMA_DEFAULT_HANDLERS */
-
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c
deleted file mode 100644
index 55317ba003..0000000000
--- a/chip/stm32/dma.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
-
-/* Callback data to use when IRQ fires */
-static struct {
-	void (*cb)(void *);	/* Callback function to call */
-	void *cb_data;		/* Callback data for callback function */
-} dma_irq[STM32_DMAC_COUNT];
-
-
-/**
- * Return the IRQ for the DMA channel
- *
- * @param channel	Channel number
- * @return IRQ for the channel
- */
-static int dma_get_irq(enum dma_channel channel)
-{
-#ifdef CHIP_FAMILY_STM32F0
-	if (channel == STM32_DMAC_CH1)
-		return STM32_IRQ_DMA_CHANNEL_1;
-
-	return channel > STM32_DMAC_CH3 ?
-		STM32_IRQ_DMA_CHANNEL_4_7 :
-		STM32_IRQ_DMA_CHANNEL_2_3;
-#elif defined(CHIP_FAMILY_STM32L4)
-	if (channel < STM32_DMAC_PER_CTLR)
-		return STM32_IRQ_DMA_CHANNEL_1 + channel;
-	else {
-		if (channel <= STM32_DMAC_CH13)
-			return STM32_IRQ_DMA2_CHANNEL1 +
-			       (channel - STM32_DMAC_PER_CTLR);
-		else
-			return STM32_IRQ_DMA2_CHANNEL6 +
-			       (channel - STM32_DMAC_PER_CTLR - 5);
-	}
-#else
-	if (channel < STM32_DMAC_PER_CTLR)
-		return STM32_IRQ_DMA_CHANNEL_1 + channel;
-	else
-		return STM32_IRQ_DMA2_CHANNEL1 +
-			(channel - STM32_DMAC_PER_CTLR);
-#endif
-}
-
-/*
- * Note, you must decrement the channel value by 1 from what is specified
- * in the datasheets, as they index from 1 and this indexes from 0!
- */
-stm32_dma_chan_t *dma_get_channel(enum dma_channel channel)
-{
-	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
-
-	return &dma->chan[channel % STM32_DMAC_PER_CTLR];
-}
-
-#ifdef STM32_DMAMUX_CxCR
-void dma_select_channel(enum dma_channel channel, uint8_t req)
-{
-	/*
-	 * STM32G4 includes a DMAMUX block which is used to handle dma requests
-	 * by peripherals. The correct 'req' number for a given peripheral is
-	 * given in ST doc RM0440.
-	 */
-	STM32_DMAMUX_CxCR(channel) = req;
-}
-#elif defined(STM32_DMA_CSELR)
-void dma_select_channel(enum dma_channel channel, unsigned char stream)
-{
-	/* Local channel # starting from 0 on each DMA controller */
-	const unsigned char ch = channel % STM32_DMAC_PER_CTLR;
-	const unsigned char shift = STM32_DMA_PERIPHERALS_PER_CHANNEL;
-	const unsigned char mask = BIT(shift) - 1;
-	uint32_t val;
-
-	ASSERT(ch < STM32_DMAC_PER_CTLR);
-	ASSERT(stream <= mask);
-	val = STM32_DMA_CSELR(channel) & ~(mask << ch * shift);
-	STM32_DMA_CSELR(channel) = val | (stream << ch * shift);
-}
-#endif /* STM32_DMAMUX_CxCR/STM32_DMA_CSELR */
-
-void dma_disable(enum dma_channel channel)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-
-	if (chan->ccr & STM32_DMA_CCR_EN)
-		chan->ccr &= ~STM32_DMA_CCR_EN;
-}
-
-void dma_disable_all(void)
-{
-	int ch;
-
-	for (ch = 0; ch < STM32_DMAC_COUNT; ch++) {
-		stm32_dma_chan_t *chan = dma_get_channel(ch);
-
-		chan->ccr &= ~STM32_DMA_CCR_EN;
-	}
-}
-
-/**
- * Prepare a channel for use and start it
- *
- * @param chan		Channel to read
- * @param count		Number of bytes to transfer
- * @param periph	Pointer to peripheral data register
- * @param memory	Pointer to memory address for receive/transmit
- * @param flags		DMA flags for the control register, normally:
- *				STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR for tx
- *				0 for rx
- */
-static void prepare_channel(enum dma_channel channel, unsigned int count,
-		void *periph, void *memory, unsigned int flags)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-	uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
-
-	dma_disable(channel);
-	dma_clear_isr(channel);
-
-	/* Following the order in Doc ID 15965 Rev 5 p194 */
-	chan->cpar = (uint32_t)periph;
-	chan->cmar = (uint32_t)memory;
-	chan->cndtr = count;
-	chan->ccr = ccr;
-	ccr |= flags;
-	chan->ccr = ccr;
-}
-
-void dma_go(stm32_dma_chan_t *chan)
-{
-	/* Flush data in write buffer so that DMA can get the latest data */
-	asm volatile("dsb;");
-
-	/* Fire it up */
-	chan->ccr |= STM32_DMA_CCR_EN;
-}
-
-void dma_prepare_tx(const struct dma_option *option, unsigned int count,
-		    const void *memory)
-{
-	/*
-	 * Cast away const for memory pointer; this is ok because we know
-	 * we're preparing the channel for transmit.
-	 */
-	prepare_channel(option->channel, count, option->periph, (void *)memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR |
-			option->flags);
-}
-
-void dma_start_rx(const struct dma_option *option, unsigned int count,
-		  void *memory)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(option->channel);
-
-	prepare_channel(option->channel, count, option->periph, memory,
-			STM32_DMA_CCR_MINC | option->flags);
-	dma_go(chan);
-}
-
-int dma_bytes_done(stm32_dma_chan_t *chan, int orig_count)
-{
-	return orig_count - chan->cndtr;
-}
-
-bool dma_is_enabled(stm32_dma_chan_t *chan)
-{
-	return (chan->ccr & STM32_DMA_CCR_EN);
-}
-
-#ifdef CONFIG_DMA_HELP
-void dma_dump(enum dma_channel channel)
-{
-	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-
-	CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr,
-		chan->cndtr, chan->cpar, chan->cmar);
-	CPRINTF("chan %d, isr=%x, ifcr=%x\n",
-		channel,
-		(dma->isr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf,
-		(dma->ifcr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf);
-}
-
-void dma_check(enum dma_channel channel, char *buf)
-{
-	stm32_dma_chan_t *chan;
-	int count;
-	int i;
-
-	chan = dma_get_channel(channel);
-	count = chan->cndtr;
-	CPRINTF("c=%d\n", count);
-	udelay(100 * MSEC);
-	CPRINTF("c=%d\n", chan->cndtr);
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", buf[i]);
-	udelay(100 * MSEC);
-	CPRINTF("c=%d\n", chan->cndtr);
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", buf[i]);
-}
-
-/* Run a check of memory-to-memory DMA */
-void dma_test(enum dma_channel channel)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-	uint32_t ctrl;
-	char periph[16], memory[16];
-	unsigned int count = sizeof(periph);
-	int i;
-
-	memset(memory, '\0', sizeof(memory));
-	for (i = 0; i < count; i++)
-		periph[i] = 10 + i;
-
-	/* Following the order in Doc ID 15965 Rev 5 p194 */
-	chan->cpar = (uint32_t)periph;
-	chan->cmar = (uint32_t)memory;
-	chan->cndtr = count;
-	ctrl = STM32_DMA_CCR_PL_MEDIUM;
-	chan->ccr = ctrl;
-
-	ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */;
-	ctrl |= STM32_DMA_CCR_MEM2MEM;
-	ctrl |= STM32_DMA_CCR_PINC;
-/*	ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */
-/*	ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */
-	chan->ccr = ctrl;
-	chan->ccr = ctrl | STM32_DMA_CCR_EN;
-
-	for (i = 0; i < count; i++)
-		CPRINTF("%d/%d ", periph[i], memory[i]);
-	CPRINTF("\ncount=%d\n", chan->cndtr);
-}
-#endif /* CONFIG_DMA_HELP */
-
-void dma_init(void)
-{
-#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN;
-#elif defined(CHIP_FAMILY_STM32G4)
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN |
-		STM32_RCC_AHB1ENR_DMAMUXEN;
-#else
-	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
-#endif
-#ifdef CHIP_FAMILY_STM32F3
-	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA2;
-#endif
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-int dma_wait(enum dma_channel channel)
-{
-	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
-	const uint32_t mask = STM32_DMA_ISR_TCIF(channel);
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
-	while ((dma->isr & mask) != mask) {
-		if (deadline.val <= get_time().val)
-			return EC_ERROR_TIMEOUT;
-
-		udelay(DMA_POLLING_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-static inline void _dma_wake_callback(void *cb_data)
-{
-	task_id_t id = (task_id_t)(int)cb_data;
-
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_DMA_TC);
-}
-
-void dma_enable_tc_interrupt(enum dma_channel channel)
-{
-	dma_enable_tc_interrupt_callback(channel, _dma_wake_callback,
-					 (void *)(int)task_get_current());
-}
-
-void dma_enable_tc_interrupt_callback(enum dma_channel channel,
-				      void (*callback)(void *),
-				      void *callback_data)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-
-	dma_irq[channel].cb = callback;
-	dma_irq[channel].cb_data = callback_data;
-
-	chan->ccr |= STM32_DMA_CCR_TCIE;
-	task_enable_irq(dma_get_irq(channel));
-}
-
-void dma_disable_tc_interrupt(enum dma_channel channel)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-
-	chan->ccr &= ~STM32_DMA_CCR_TCIE;
-	task_disable_irq(dma_get_irq(channel));
-
-	dma_irq[channel].cb = NULL;
-	dma_irq[channel].cb_data = NULL;
-}
-
-void dma_clear_isr(enum dma_channel channel)
-{
-	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
-
-	dma->ifcr |= STM32_DMA_ISR_ALL(channel);
-}
-
-#ifdef CONFIG_DMA_DEFAULT_HANDLERS
-#ifdef CHIP_FAMILY_STM32F0
-void dma_event_interrupt_channel_1(void)
-{
-	if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) {
-		dma_clear_isr(STM32_DMAC_CH1);
-		if (dma_irq[STM32_DMAC_CH1].cb != NULL)
-			(*dma_irq[STM32_DMAC_CH1].cb)
-				(dma_irq[STM32_DMAC_CH1].cb_data);
-	}
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 1);
-
-void dma_event_interrupt_channel_2_3(void)
-{
-	int i;
-
-	for (i = STM32_DMAC_CH2; i <= STM32_DMAC_CH3; i++) {
-		if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) {
-			dma_clear_isr(i);
-			if (dma_irq[i].cb != NULL)
-				(*dma_irq[i].cb)(dma_irq[i].cb_data);
-		}
-	}
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 1);
-
-void dma_event_interrupt_channel_4_7(void)
-{
-	int i;
-	const unsigned int max_chan = MIN(STM32_DMAC_CH7, STM32_DMAC_COUNT);
-
-	for (i = STM32_DMAC_CH4; i <= max_chan; i++) {
-		if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) {
-			dma_clear_isr(i);
-			if (dma_irq[i].cb != NULL)
-				(*dma_irq[i].cb)(dma_irq[i].cb_data);
-		}
-	}
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1);
-
-#else /* !CHIP_FAMILY_STM32F0 */
-
-#define DECLARE_DMA_IRQ(x) \
-	void CONCAT2(dma_event_interrupt_channel_, x)(void) \
-	{ \
-		dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \
-		if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \
-			(*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb) \
-				(dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \
-	} \
-	DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \
-		    CONCAT2(dma_event_interrupt_channel_, x), 1)
-
-DECLARE_DMA_IRQ(1);
-DECLARE_DMA_IRQ(2);
-DECLARE_DMA_IRQ(3);
-DECLARE_DMA_IRQ(4);
-DECLARE_DMA_IRQ(5);
-DECLARE_DMA_IRQ(6);
-DECLARE_DMA_IRQ(7);
-#ifdef CHIP_FAMILY_STM32F3
-DECLARE_DMA_IRQ(9);
-DECLARE_DMA_IRQ(10);
-#endif
-#ifdef CHIP_FAMILY_STM32L4
-DECLARE_DMA_IRQ(9);
-DECLARE_DMA_IRQ(10);
-DECLARE_DMA_IRQ(11);
-DECLARE_DMA_IRQ(12);
-DECLARE_DMA_IRQ(13);
-DECLARE_DMA_IRQ(14);
-DECLARE_DMA_IRQ(15);
-#endif
-
-#endif /* CHIP_FAMILY_STM32F0 */
-#endif /* CONFIG_DMA_DEFAULT_HANDLERS */
diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c
deleted file mode 100644
index 9e35a2c689..0000000000
--- a/chip/stm32/flash-f.c
+++ /dev/null
@@ -1,833 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common flash memory module for STM32F and STM32F0 */
-
-#include <stdbool.h>
-#include "battery.h"
-#include "console.h"
-#include "clock.h"
-#include "flash.h"
-#include "flash-f.h"
-#include "hooks.h"
-#include "registers.h"
-#include "panic.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/*
- * Approximate number of CPU cycles per iteration of the loop when polling
- * the flash status
- */
-#define CYCLE_PER_FLASH_LOOP 10
-
-/*
- * While flash write / erase is in progress, the stm32 CPU core is mostly
- * non-functional, due to the inability to fetch instructions from flash.
- * This may greatly increase interrupt latency.
- */
-
-/* Flash page programming timeout.  This is 2x the datasheet max. */
-#define FLASH_WRITE_TIMEOUT_US 16000
-/* 20ms < tERASE < 40ms on F0/F3, for 1K / 2K sector size. */
-#define FLASH_ERASE_TIMEOUT_US 40000
-
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-#if !defined(CHIP_FAMILY_STM32F4)
-#error "CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE should work with all STM32F "
-"series chips, but has not been tested"
-#endif /* !CHIP_FAMILY_STM32F4 */
-#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
-
-/* Forward declarations */
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-static enum flash_rdp_level flash_physical_get_rdp_level(void);
-static int flash_physical_set_rdp_level(enum flash_rdp_level level);
-#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
-
-static inline int calculate_flash_timeout(void)
-{
-	return (FLASH_WRITE_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
-}
-
-static int wait_busy(void)
-{
-	int timeout = calculate_flash_timeout();
-	while ((STM32_FLASH_SR & FLASH_SR_BUSY) && timeout-- > 0)
-		udelay(CYCLE_PER_FLASH_LOOP);
-	return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-}
-
-
-void unlock_flash_control_register(void)
-{
-	STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
-	STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
-}
-
-void unlock_flash_option_bytes(void)
-{
-	STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
-	STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
-}
-
-void disable_flash_option_bytes(void)
-{
-	ignore_bus_fault(1);
-	/*
-	 * Writing anything other than the pre-defined keys to the option key
-	 * register results in a bus fault and the register being locked until
-	 * reboot (even with a further correct key write).
-	 */
-	STM32_FLASH_OPTKEYR = 0xffffffff;
-	ignore_bus_fault(0);
-}
-
-void disable_flash_control_register(void)
-{
-	ignore_bus_fault(1);
-	/*
-	 * Writing anything other than the pre-defined keys to the key
-	 * register results in a bus fault and the register being locked until
-	 * reboot (even with a further correct key write).
-	 */
-	STM32_FLASH_KEYR = 0xffffffff;
-	ignore_bus_fault(0);
-}
-
-void lock_flash_control_register(void)
-{
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-	/* FLASH_CR_OPTWRE was set by writing the keys in unlock(). */
-	STM32_FLASH_CR &= ~FLASH_CR_OPTWRE;
-#endif
-	STM32_FLASH_CR |= FLASH_CR_LOCK;
-}
-
-void lock_flash_option_bytes(void)
-{
-#if !(defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3))
-	STM32_FLASH_OPTCR |= FLASH_OPTLOCK;
-#endif
-}
-
-bool flash_option_bytes_locked(void)
-{
-	return !!STM32_FLASH_OPT_LOCKED;
-}
-
-bool flash_control_register_locked(void)
-{
-	return !!(STM32_FLASH_CR & FLASH_CR_LOCK);
-}
-
-/*
- * We at least unlock the control register lock.
- * We may also unlock other locks.
- */
-enum extra_lock_type  {
-	NO_EXTRA_LOCK = 0,
-	OPT_LOCK = 1,
-};
-
-static int unlock(int locks)
-{
-	/*
-	 * We may have already locked the flash module and get a bus fault
-	 * in the attempt to unlock. Need to disable bus fault handler now.
-	 */
-	ignore_bus_fault(1);
-
-	/* Always unlock CR if needed */
-	if (flash_control_register_locked())
-		unlock_flash_control_register();
-
-	/* unlock option memory if required */
-	if ((locks & OPT_LOCK) && flash_option_bytes_locked())
-		unlock_flash_option_bytes();
-
-	/* Re-enable bus fault handler */
-	ignore_bus_fault(0);
-
-	if ((locks & OPT_LOCK) && flash_option_bytes_locked())
-		return EC_ERROR_UNKNOWN;
-	if (STM32_FLASH_CR & FLASH_CR_LOCK)
-		return EC_ERROR_UNKNOWN;
-	return EC_SUCCESS;
-}
-
-static void lock(void)
-{
-	lock_flash_control_register();
-}
-
-#ifdef CHIP_FAMILY_STM32F4
-static int write_optb(uint32_t mask, uint32_t value)
-{
-	int rv;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-
-	/* The target byte is the value we want to write. */
-	if ((STM32_FLASH_OPTCR & mask) == value)
-		return EC_SUCCESS;
-
-	rv = unlock(OPT_LOCK);
-	if (rv)
-		return rv;
-
-	STM32_FLASH_OPTCR = (STM32_FLASH_OPTCR & ~mask) | value;
-	STM32_FLASH_OPTCR |= FLASH_OPTSTRT;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-	lock();
-
-	return EC_SUCCESS;
-}
-#else
-static int write_optb(int byte, uint8_t value);
-/*
- * Option byte organization
- *
- *                 [31:24]    [23:16]    [15:8]   [7:0]
- *
- *   0x1FFF_F800    nUSER      USER       nRDP     RDP
- *
- *   0x1FFF_F804    nData1     Data1     nData0    Data0
- *
- *   0x1FFF_F808    nWRP1      WRP1      nWRP0     WRP0
- *
- *   0x1FFF_F80C    nWRP3      WRP2      nWRP2     WRP2
- *
- * Note that the variable with n prefix means the complement.
- */
-static uint8_t read_optb(int byte)
-{
-	return *(uint8_t *)(STM32_OPTB_BASE + byte);
-}
-
-static int erase_optb(void)
-{
-	int rv;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-
-	rv = unlock(OPT_LOCK);
-	if (rv)
-		return rv;
-
-	/* Must be set in 2 separate lines. */
-	STM32_FLASH_CR |= FLASH_CR_OPTER;
-	STM32_FLASH_CR |= FLASH_CR_STRT;
-
-	rv = wait_busy();
-
-	STM32_FLASH_CR &= ~FLASH_CR_OPTER;
-
-	if (rv)
-		return rv;
-	lock();
-
-	return EC_SUCCESS;
-}
-
-static int write_optb(int byte, uint8_t value);
-/*
- * Since the option byte erase is WHOLE erase, this function is to keep
- * rest of bytes, but make this byte 0xff.
- * Note that this could make a recursive call to write_optb().
- */
-static int preserve_optb(int byte)
-{
-	int i, rv;
-	uint8_t optb[8];
-
-	/* The byte has been reset, no need to run preserve. */
-	if (*(uint16_t *)(STM32_OPTB_BASE + byte) == 0xffff)
-		return EC_SUCCESS;
-
-	for (i = 0; i < ARRAY_SIZE(optb); ++i)
-		optb[i] = read_optb(i * 2);
-
-	optb[byte / 2] = 0xff;
-
-	rv = erase_optb();
-	if (rv)
-		return rv;
-	for (i = 0; i < ARRAY_SIZE(optb); ++i) {
-		rv = write_optb(i * 2, optb[i]);
-		if (rv)
-			return rv;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int write_optb(int byte, uint8_t value)
-{
-	volatile int16_t *hword = (uint16_t *)(STM32_OPTB_BASE + byte);
-	int rv;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-
-	/* The target byte is the value we want to write. */
-	if (*(uint8_t *)hword == value)
-		return EC_SUCCESS;
-
-	/* Try to erase that byte back to 0xff. */
-	rv = preserve_optb(byte);
-	if (rv)
-		return rv;
-
-	/* The value is 0xff after erase. No need to write 0xff again. */
-	if (value == 0xff)
-		return EC_SUCCESS;
-
-	rv = unlock(OPT_LOCK);
-	if (rv)
-		return rv;
-
-	/* set OPTPG bit */
-	STM32_FLASH_CR |= FLASH_CR_OPTPG;
-
-	*hword = ((~value) << STM32_OPTB_COMPL_SHIFT) | value;
-
-	/* reset OPTPG bit */
-	STM32_FLASH_CR &= ~FLASH_CR_OPTPG;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-	lock();
-
-	return EC_SUCCESS;
-}
-#endif
-
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-/**
- * @return true if RDP (read protection) Level 1 or 2 enabled, false otherwise
- */
-bool is_flash_rdp_enabled(void)
-{
-	enum flash_rdp_level level = flash_physical_get_rdp_level();
-
-	if (level == FLASH_RDP_LEVEL_INVALID) {
-		CPRINTS("ERROR: unable to read RDP level");
-		return false;
-	}
-
-	return level != FLASH_RDP_LEVEL_0;
-}
-#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-#if CONFIG_FLASH_WRITE_SIZE == 1
-	uint8_t *address = (uint8_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	uint8_t quantum = 0;
-#elif CONFIG_FLASH_WRITE_SIZE == 2
-	uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	uint16_t quantum = 0;
-#elif CONFIG_FLASH_WRITE_SIZE == 4
-	uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	uint32_t quantum = 0;
-#else
-#error "CONFIG_FLASH_WRITE_SIZE not supported."
-#endif
-	int res = EC_SUCCESS;
-	int timeout = calculate_flash_timeout();
-
-	if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS) {
-		res = EC_ERROR_UNKNOWN;
-		goto exit_wr;
-	}
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = FLASH_SR_ALL_ERR | FLASH_SR_EOP;
-
-	/* set PG bit */
-	STM32_FLASH_CR |= FLASH_CR_PG;
-
-	for (; size > 0; size -= CONFIG_FLASH_WRITE_SIZE) {
-		int i;
-
-		for (i = CONFIG_FLASH_WRITE_SIZE - 1, quantum = 0; i >= 0; i--)
-			quantum = (quantum << 8) + data[i];
-		data += CONFIG_FLASH_WRITE_SIZE;
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset when doing
-		 * long writing with interrupt disabled.
-		 */
-		watchdog_reload();
-
-		/* wait to be ready  */
-		for (i = 0;
-		     (STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		     (i < timeout);
-		     i++)
-			;
-
-		/* write the data */
-		*address++ = quantum;
-
-		/* Wait for writes to complete */
-		for (i = 0;
-		     (STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		     (i < timeout);
-		     i++)
-			;
-
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		/* Check for error conditions - erase failed, voltage error,
-		 * protection error */
-		if (STM32_FLASH_SR & FLASH_SR_ALL_ERR) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_wr;
-		}
-	}
-
-exit_wr:
-	/* Disable PG bit */
-	STM32_FLASH_CR &= ~FLASH_CR_PG;
-
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int res = EC_SUCCESS;
-	int sector_size;
-	int timeout_us;
-#ifdef CHIP_FAMILY_STM32F4
-	int sector = crec_flash_bank_index(offset);
-	/* we take advantage of sector_size == erase_size */
-	if ((sector < 0) || (crec_flash_bank_index(offset + size) < 0))
-		return EC_ERROR_INVAL;  /* Invalid range */
-#endif
-
-	if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = FLASH_SR_ALL_ERR | FLASH_SR_EOP;
-
-	/* set SER/PER bit */
-	STM32_FLASH_CR |= FLASH_CR_PER;
-
-	while (size > 0) {
-		timestamp_t deadline;
-#ifdef CHIP_FAMILY_STM32F4
-		sector_size = crec_flash_bank_size(sector);
-		/* Timeout: from spec, proportional to the size
-		 * inversely proportional to the write size.
-		 */
-		timeout_us = sector_size * 4 / CONFIG_FLASH_WRITE_SIZE;
-#else
-		sector_size = CONFIG_FLASH_ERASE_SIZE;
-		timeout_us = FLASH_ERASE_TIMEOUT_US;
-#endif
-		/* Do nothing if already erased */
-		if (crec_flash_is_erased(offset, sector_size))
-			goto next_sector;
-#ifdef CHIP_FAMILY_STM32F4
-		/* select page to erase */
-		STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_SNB_MASK) |
-			(sector << STM32_FLASH_CR_SNB_OFFSET);
-#else
-		/* select page to erase */
-		STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset;
-#endif
-		/* set STRT bit : start erase */
-		STM32_FLASH_CR |= FLASH_CR_STRT;
-
-		deadline.val = get_time().val + timeout_us;
-		/* Wait for erase to complete */
-		watchdog_reload();
-		while ((STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		       (get_time().val < deadline.val)) {
-			usleep(timeout_us/100);
-		}
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_er;
-		}
-
-		/*
-		 * Check for error conditions - erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR & FLASH_SR_ALL_ERR) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_er;
-		}
-next_sector:
-		size -= sector_size;
-		offset += sector_size;
-#ifdef CHIP_FAMILY_STM32F4
-		sector++;
-#endif
-	}
-
-exit_er:
-	/* reset SER/PER bit */
-	STM32_FLASH_CR &= ~FLASH_CR_PER;
-
-	lock();
-
-	return res;
-}
-
-#ifdef CHIP_FAMILY_STM32F4
-static int flash_physical_get_protect_at_boot(int block)
-{
-	/* 0: Write protection active on sector i. */
-	return !(STM32_OPTB_WP & STM32_OPTB_nWRP(block));
-}
-
-static int flash_physical_protect_at_boot_update_rdp_pstate(uint32_t new_flags)
-{
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-	int rv = EC_SUCCESS;
-
-	bool rdp_enable = (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT) != 0;
-
-	/*
-	 * This is intentionally a one-way latch. Once we have enabled RDP
-	 * Level 1, we will only allow going back to Level 0 using the
-	 * bootloader (e.g., "stm32mon -U") since transitioning from Level 1 to
-	 * Level 0 triggers a mass erase.
-	 */
-	if (rdp_enable)
-		rv = flash_physical_set_rdp_level(FLASH_RDP_LEVEL_1);
-
-	return rv;
-#else
-	return EC_SUCCESS;
-#endif
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int block;
-	int original_val, val;
-
-	original_val = val = STM32_OPTB_WP & STM32_OPTB_nWRP_ALL;
-
-	for (block = WP_BANK_OFFSET;
-	     block < WP_BANK_OFFSET + PHYSICAL_BANKS;
-	     block++) {
-		int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
-
-		if (block >= WP_BANK_OFFSET &&
-		    block < WP_BANK_OFFSET + WP_BANK_COUNT)
-			protect |= new_flags & EC_FLASH_PROTECT_RO_AT_BOOT;
-#ifdef CONFIG_FLASH_PROTECT_RW
-		else
-			protect |= new_flags & EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-
-		if (protect)
-			val &= ~BIT(block);
-		else
-			val |= 1 << block;
-	}
-	if (original_val != val) {
-		int rv = write_optb(STM32_FLASH_nWRP_ALL,
-				    val << STM32_FLASH_nWRP_OFFSET);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	return flash_physical_protect_at_boot_update_rdp_pstate(new_flags);
-}
-
-static void unprotect_all_blocks(void)
-{
-	write_optb(STM32_FLASH_nWRP_ALL, STM32_FLASH_nWRP_ALL);
-}
-
-#else   /* CHIP_FAMILY_STM32F4 */
-static int flash_physical_get_protect_at_boot(int block)
-{
-	uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block/8));
-	return (!(val & (1 << (block % 8)))) ? 1 : 0;
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int block;
-	int i;
-	int original_val[4], val[4];
-
-	for (i = 0; i < 4; ++i)
-		original_val[i] = val[i] = read_optb(i * 2 + 8);
-
-	for (block = WP_BANK_OFFSET;
-	     block < WP_BANK_OFFSET + PHYSICAL_BANKS;
-	     block++) {
-		int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
-		int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4;
-
-		if (block >= WP_BANK_OFFSET &&
-		    block < WP_BANK_OFFSET + WP_BANK_COUNT)
-			protect |= new_flags & EC_FLASH_PROTECT_RO_AT_BOOT;
-#ifdef CONFIG_ROLLBACK
-		else if (block >= ROLLBACK_BANK_OFFSET &&
-			 block < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT)
-			protect |= new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif
-#ifdef CONFIG_FLASH_PROTECT_RW
-		else
-			protect |= new_flags & EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-
-		if (protect)
-			val[byte_off] = val[byte_off] & (~(1 << (block % 8)));
-		else
-			val[byte_off] = val[byte_off] | (1 << (block % 8));
-	}
-
-	for (i = 0; i < 4; ++i)
-		if (original_val[i] != val[i])
-			write_optb(i * 2 + 8, val[i]);
-
-#ifdef CONFIG_FLASH_READOUT_PROTECTION
-	/*
-	 * Set a permanent protection by increasing RDP to level 1,
-	 * trying to unprotected the flash will trigger a full erase.
-	 */
-	write_optb(0, 0x11);
-#endif
-
-	return EC_SUCCESS;
-}
-
-static void unprotect_all_blocks(void)
-{
-	int i;
-
-	for (i = 4; i < 8; ++i)
-		write_optb(i * 2, 0xff);
-}
-#endif
-
-/**
- * Check if write protect register state is inconsistent with RO_AT_BOOT and
- * ALL_AT_BOOT state.
- *
- * @return zero if consistent, non-zero if inconsistent.
- */
-static int registers_need_reset(void)
-{
-	uint32_t flags = crec_flash_get_protect();
-	int i;
-	int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0;
-	int ro_wp_region_start = WP_BANK_OFFSET;
-	int ro_wp_region_end = WP_BANK_OFFSET + WP_BANK_COUNT;
-
-	for (i = ro_wp_region_start; i < ro_wp_region_end; i++)
-		if (flash_physical_get_protect_at_boot(i) != ro_at_boot)
-			return 1;
-	return 0;
-}
-
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-/**
- * Set Flash RDP (read protection) level.
- *
- * @note Does not take effect until reset.
- *
- * @param level new RDP (read protection) level to set
- * @return EC_SUCCESS on success, other on failure
- */
-int flash_physical_set_rdp_level(enum flash_rdp_level level)
-{
-	uint32_t reg_level;
-
-	switch (level) {
-	case FLASH_RDP_LEVEL_0:
-		/*
-		 * Asserting by default since we don't want to inadvertently
-		 * go from Level 1 to Level 0, which triggers a mass erase.
-		 * Remove assert if you want to use it.
-		 */
-		ASSERT(false);
-		reg_level = FLASH_OPTCR_RDP_LEVEL_0;
-		break;
-	case FLASH_RDP_LEVEL_1:
-		reg_level = FLASH_OPTCR_RDP_LEVEL_1;
-		break;
-	case FLASH_RDP_LEVEL_2:
-		/*
-		 * Asserting by default since it's permanent (there is no
-		 * way to reverse). Remove assert if you want to use it.
-		 */
-		ASSERT(false);
-		reg_level = FLASH_OPTCR_RDP_LEVEL_2;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	return write_optb(FLASH_OPTCR_RDP_MASK, reg_level);
-}
-
-/**
- * @return On success, current flash read protection level.
- *         On failure, FLASH_RDP_LEVEL_INVALID
- */
-enum flash_rdp_level flash_physical_get_rdp_level(void)
-{
-	uint32_t level = (STM32_FLASH_OPTCR & FLASH_OPTCR_RDP_MASK);
-
-	switch (level) {
-	case FLASH_OPTCR_RDP_LEVEL_0:
-		return FLASH_RDP_LEVEL_0;
-	case FLASH_OPTCR_RDP_LEVEL_1:
-		return FLASH_RDP_LEVEL_1;
-	case FLASH_OPTCR_RDP_LEVEL_2:
-		return FLASH_RDP_LEVEL_2;
-	default:
-		return FLASH_RDP_LEVEL_INVALID;
-	}
-}
-#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
-
-/*****************************************************************************/
-/* High-level APIs */
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	int need_reset = 0;
-
-
-#ifdef CHIP_FAMILY_STM32F4
-	unlock(NO_EXTRA_LOCK);
-	/* Set the proper write size */
-	STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_PSIZE_MASK) |
-		 (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) <<
-		 STM32_FLASH_CR_PSIZE_OFFSET;
-	lock();
-#endif
-	if (crec_flash_physical_restore_state())
-		return EC_SUCCESS;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		if (prot_flags & EC_FLASH_PROTECT_RO_NOW) {
-			/* Enable physical protection for RO (0 means RO). */
-			crec_flash_physical_protect_now(0);
-		}
-
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			/*
-			 * Pstate wants RO protected at boot, but the write
-			 * protect register wasn't set to protect it.  Force an
-			 * update to the write protect register and reboot so
-			 * it takes effect.
-			 */
-			crec_flash_physical_protect_at_boot(
-				EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-
-		if (registers_need_reset()) {
-			/*
-			 * Write protect register was in an inconsistent state.
-			 * Set it back to a good state and reboot.
-			 *
-			 * TODO(crosbug.com/p/23798): this seems really similar
-			 * to the check above.  One of them should be able to
-			 * go away.
-			 */
-			crec_flash_protect_at_boot(
-				prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-	} else {
-		if (prot_flags & EC_FLASH_PROTECT_RO_NOW) {
-			/*
-			 * Write protect pin unasserted but some section is
-			 * protected. Drop it and reboot.
-			 */
-			unprotect_all_blocks();
-			need_reset = 1;
-		}
-	}
-
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_ALL_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) {
-		/*
-		 * ALL_AT_BOOT and ALL_NOW should be both set or both unset
-		 * at boot. If they are not, it must be that the chip requires
-		 * OBL_LAUNCH to be set to reload option bytes. Let's reset
-		 * the system with OBL_LAUNCH set.
-		 * This assumes OBL_LAUNCH is used for hard reset in
-		 * chip/stm32/system.c.
-		 */
-		need_reset = 1;
-	}
-
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_RW_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) {
-		/* RW_AT_BOOT and RW_NOW do not match. */
-		need_reset = 1;
-	}
-#endif
-
-#ifdef CONFIG_ROLLBACK
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) {
-		/* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */
-		need_reset = 1;
-	}
-#endif
-
-	if (need_reset)
-		system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	return EC_SUCCESS;
-}
diff --git a/chip/stm32/flash-f.h b/chip/stm32/flash-f.h
deleted file mode 100644
index cbbe6ec86f..0000000000
--- a/chip/stm32/flash-f.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_STM32_FLASH_F_H
-#define __CROS_EC_STM32_FLASH_F_H
-
-#include <stdbool.h>
-
-enum flash_rdp_level {
-	FLASH_RDP_LEVEL_INVALID = -1,	/**< Error occurred. */
-	FLASH_RDP_LEVEL_0,		/**< No read protection. */
-	FLASH_RDP_LEVEL_1,		/**< Reading flash is disabled while in
-					 *   bootloader mode or JTAG attached.
-					 *   Changing to Level 0 from this level
-					 *   triggers mass erase.
-					 */
-	FLASH_RDP_LEVEL_2,		/**< Same as Level 1, but is permanent
-					 *   and can never be disabled.
-					 */
-};
-
-bool is_flash_rdp_enabled(void);
-
-#endif /* __CROS_EC_STM32_FLASH_F_H */
diff --git a/chip/stm32/flash-regs.h b/chip/stm32/flash-regs.h
deleted file mode 100644
index b0a46667a1..0000000000
--- a/chip/stm32/flash-regs.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_STM32_FLASH_REGS_H
-#define __CROS_EC_STM32_FLASH_REGS_H
-
-#include <stdbool.h>
-
-/**
- * Unlock the flash control register using the unlock sequence.
- *
- * If the flash control register has been disabled since the last reset when
- * this function is called, a bus fault will be generated.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- * See "4.9.2  FLASH key register for bank 1" in RM0433.
- */
-void unlock_flash_control_register(void);
-
-/**
- * Unlock the flash option bytes register using the unlock sequence.
- *
- * If the flash option bytes register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
- *
- * See "3.6.2 Programming user option bytes" in RM0402.
- * See "4.9.3 FLASH option key register" in RM0433.
- */
-void unlock_flash_option_bytes(void);
-
-/**
- * Lock the flash control register.
- *
- * If the flash control register has been disabled since the last reset when
- * this function is called, a bus fault will be generated.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- * See "4.9.4 Flash control register for bank 1" in RM0433.
- */
-void lock_flash_control_register(void);
-
-/**
- * Lock the flash option bytes register.
- *
- * If the flash option bytes register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
- *
- * See "3.6.2 Programming user option bytes" in RM0402.
- * See "4.9.7 FLASH option control register" in RM0433.
- */
-void lock_flash_option_bytes(void);
-
-/**
- * Disable the flash option bytes register.
- *
- * This function expects that bus faults have not already been ignored when
- * called.
- *
- * Once this function is called any attempt at accessing the flash option
- * bytes register will generate a bus fault until the next reset.
- *
- * See "3.6.2 Programming user option bytes" in RM0402.
- * See "4.9.7 FLASH option control register" in RM0433.
- */
-void disable_flash_option_bytes(void);
-
-/**
- * Disable the flash control register.
- *
- * This function expects that bus faults have not already been ignored when
- * called.
- *
- * Once this function is called any attempt at accessing the flash control
- * register will generate a bus fault until the next reset.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- * See "4.9.4 Flash control register for bank 1" in RM0433.
- */
-void disable_flash_control_register(void);
-
-/**
- * Check if the flash option bytes are locked.
- *
- * If the flash option bytes register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
-
- * See "3.6.2 Programming user option bytes" in RM0402.
- * See "4.9.7 FLASH option control register" in RM0433.
- *
- * @return true if option bytes are locked, false otherwise
- */
-bool flash_option_bytes_locked(void);
-
-/**
- * Check if the flash control register is locked.
- *
- * If the flash control register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- * See "4.9.4 Flash control register for bank 1" in RM0433.
- *
- * @return true if register is locked, false otherwise
- */
-bool flash_control_register_locked(void);
-
-#endif /* __CROS_EC_STM32_FLASH_REGS_H */
diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c
deleted file mode 100644
index f790a657c8..0000000000
--- a/chip/stm32/flash-stm32f0.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC */
-
-#include "common.h"
-#include "flash.h"
-#include "registers.h"
-#include "util.h"
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_get_protect(int block)
-{
-	return !(STM32_FLASH_WRPR & BIT(block));
-}
-
-/*
- * Note: This does not need to update _NOW flags, as get_protect_flags
- * in common code already does so.
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-	uint32_t wrp01 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP01);
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-	uint32_t wrp23 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP23);
-#endif
-
-	/*
-	 * We only need to return detailed flags if we want to protect RW or
-	 * ROLLBACK independently (EC_FLASH_PROTECT_RO_AT_BOOT should be set
-	 * by pstate logic).
-	 */
-#if defined(CONFIG_FLASH_PROTECT_RW) || defined(CONFIG_ROLLBACK)
-	/* Flags that must be set for each region. */
-	const int mask_flags[] = {
-		[FLASH_REGION_RW] = EC_FLASH_PROTECT_RW_AT_BOOT,
-		[FLASH_REGION_RO] = EC_FLASH_PROTECT_RO_AT_BOOT,
-#ifdef CONFIG_ROLLBACK
-		[FLASH_REGION_ROLLBACK] = EC_FLASH_PROTECT_ROLLBACK_AT_BOOT,
-#endif
-	};
-
-	/*
-	 * Sets up required mask for wrp01/23 registers: for protection to be
-	 * set, values set in the mask must be zeros, values in the mask << 8
-	 * must be ones.
-	 *
-	 * Note that these masks are actually static, and could be precomputed
-	 * at build time to save flash space.
-	 */
-	uint32_t wrp_mask[FLASH_REGION_COUNT][2];
-	int i;
-	int shift = 0;
-	int reg = 0;
-
-	memset(wrp_mask, 0, sizeof(wrp_mask));
-
-	/* Scan flash protection */
-	for (i = 0; i < PHYSICAL_BANKS; i++) {
-		/* Default: RW. */
-		int region = FLASH_REGION_RW;
-
-		if (i >= WP_BANK_OFFSET &&
-		    i < WP_BANK_OFFSET + WP_BANK_COUNT)
-			region = FLASH_REGION_RO;
-#ifdef CONFIG_ROLLBACK
-		if (i >= ROLLBACK_BANK_OFFSET &&
-		    i < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT)
-			region = FLASH_REGION_ROLLBACK;
-#endif
-
-		switch (i) {
-		case 8:
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-		case 24:
-#endif
-			shift += 8;
-			break;
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-		case 16:
-			reg = 1;
-			shift = 0;
-			break;
-#endif
-		}
-
-		wrp_mask[region][reg] |= 1 << shift;
-		shift++;
-	}
-
-	for (i = 0; i < FLASH_REGION_COUNT; i++) {
-		if (!(wrp01 & wrp_mask[i][0]) &&
-			(wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8))
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-			if (!(wrp23 & wrp_mask[i][1]) &&
-			     (wrp23 & wrp_mask[i][1] << 8) ==
-							 (wrp_mask[i][1] << 8))
-#endif
-				flags |= mask_flags[i];
-	}
-#endif /* CONFIG_FLASH_PROTECT_RW || CONFIG_ROLLBACK */
-
-	if (wrp01 == 0xff00ff00)
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-		if (wrp23 == 0xff00ff00)
-#endif
-			flags |= EC_FLASH_PROTECT_ALL_AT_BOOT;
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	return EC_ERROR_INVAL;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	/* Nothing to restore */
-	return 0;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-#ifdef CONFIG_FLASH_PROTECT_RW
-	       EC_FLASH_PROTECT_RW_AT_BOOT |
-	       EC_FLASH_PROTECT_RW_NOW |
-#endif
-#ifdef CONFIG_ROLLBACK
-	       EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-	       EC_FLASH_PROTECT_ROLLBACK_NOW |
-#endif
-	       EC_FLASH_PROTECT_ALL_AT_BOOT |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * ALL/RW at-boot state can be set if WP GPIO is asserted and can always
-	 * be cleared.
-	 */
-	if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_AT_BOOT;
-
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-
-#ifdef CONFIG_ROLLBACK
-	if (cur_flags & (EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif
-
-	return ret;
-}
diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c
deleted file mode 100644
index 138e690fcc..0000000000
--- a/chip/stm32/flash-stm32f3.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for stm32f3 and stm32f4 */
-
-#include <stdbool.h>
-#include "common.h"
-#include "flash.h"
-#include "flash-f.h"
-#include "flash-regs.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "panic.h"
-
-/*****************************************************************************/
-/* Physical layer APIs */
-#ifdef CHIP_VARIANT_STM32F76X
-/*
- * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB
- */
-struct ec_flash_bank const flash_bank_array[] = {
-	{
-		.count = 4,
-		.size_exp = __fls(SIZE_32KB),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(SIZE_32KB),
-		.protect_size_exp = __fls(SIZE_32KB),
-	},
-	{
-		.count = 1,
-		.size_exp = __fls(SIZE_128KB),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(SIZE_128KB),
-		.protect_size_exp = __fls(SIZE_128KB),
-	},
-	{
-		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB,
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.size_exp = __fls(SIZE_256KB),
-		.erase_size_exp = __fls(SIZE_256KB),
-		.protect_size_exp = __fls(SIZE_256KB),
-	},
-};
-#elif defined(CHIP_FAMILY_STM32F4)
-/*
- * STM32F412xE has 512 KB flash
- *   8 "erase" sectors (512 KB) : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB
- *
- * STM32F412xG has 1 MB flash
- *   12 "erase" sectors (1024 KB) :
- *           16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB/128KB/128KB/128KB/128KB
- *
- * https://www.st.com/resource/en/datasheet/stm32f412cg.pdf
- */
-struct ec_flash_bank const flash_bank_array[] = {
-	{
-		.count = 4,
-		.size_exp = __fls(SIZE_16KB),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(SIZE_16KB),
-		.protect_size_exp = __fls(SIZE_16KB),
-	},
-	{
-		.count = 1,
-		.size_exp = __fls(SIZE_64KB),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(SIZE_64KB),
-		.protect_size_exp = __fls(SIZE_64KB),
-	},
-	{
-		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB,
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.size_exp = __fls(SIZE_128KB),
-		.erase_size_exp = __fls(SIZE_128KB),
-		.protect_size_exp = __fls(SIZE_128KB),
-	},
-};
-#endif
-
-/* Flag indicating whether we have locked down entire flash */
-static int entire_flash_locked;
-
-#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
-#define FLASH_HOOK_VERSION 1
-
-/* The previous write protect state before sys jump */
-struct flash_wp_state {
-	int entire_flash_locked;
-};
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_get_protect(int block)
-{
-	return (entire_flash_locked ||
-#if defined(CHIP_FAMILY_STM32F3)
-		!(STM32_FLASH_WRPR & BIT(block))
-#elif defined(CHIP_FAMILY_STM32F4)
-		!(STM32_OPTB_WP & STM32_OPTB_nWRP(block))
-#endif
-	       );
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	/* Read all-protected state from our shadow copy */
-	if (entire_flash_locked)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-	if (is_flash_rdp_enabled())
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-#endif
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		disable_flash_control_register();
-		entire_flash_locked = 1;
-
-		return EC_SUCCESS;
-	}
-
-	disable_flash_option_bytes();
-
-	return EC_SUCCESS;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	int version, size;
-	const struct flash_wp_state *prev;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
-		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
-		if (prev && version == FLASH_HOOK_VERSION &&
-		    size == sizeof(*prev))
-			entire_flash_locked = prev->entire_flash_locked;
-		return 1;
-	}
-
-	return 0;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void flash_preserve_state(void)
-{
-	struct flash_wp_state state;
-
-	state.entire_flash_locked = entire_flash_locked;
-
-	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c
deleted file mode 120000
index 6ff8130e17..0000000000
--- a/chip/stm32/flash-stm32f4.c
+++ /dev/null
@@ -1 +0,0 @@
-flash-stm32f3.c
\ No newline at end of file
diff --git a/chip/stm32/flash-stm32g4-l4.c b/chip/stm32/flash-stm32g4-l4.c
deleted file mode 100644
index f792da6e3c..0000000000
--- a/chip/stm32/flash-stm32g4-l4.c
+++ /dev/null
@@ -1,792 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Flash memory module for STM32L4 family */
-
-#include "common.h"
-#include "clock.h"
-#include "flash.h"
-#include "hooks.h"
-#include "registers.h"
-#include "panic.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * Approximate number of CPU cycles per iteration of the loop when polling
- * the flash status
- */
-#define CYCLE_PER_FLASH_LOOP 10
-
-/* Flash page programming timeout.  This is 2x the datasheet max. */
-#define FLASH_TIMEOUT_US 48000
-
-/*
- * Cros-Ec common flash APIs use the term 'bank' equivalent to how 'page' is
- * used in the STM32 TRMs. Redifining macros here in terms of pages in order to
- * match STM32 documentation for write protect computations in this file.
- *
- * These macros are from the common flash API and mean the following:
- * WP_BANK_OFFSET         -> index of first RO page
- * CONFIG_WP_STORAGE_SIZE -> size of RO region in bytes
- */
-#define FLASH_PAGE_SIZE CONFIG_FLASH_BANK_SIZE
-#define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE_BYTES / FLASH_PAGE_SIZE)
-#define FLASH_RO_FIRST_PAGE_IDX WP_BANK_OFFSET
-#define FLASH_RO_LAST_PAGE_IDX ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) \
-				 + FLASH_RO_FIRST_PAGE_IDX - 1)
-#define FLASH_RW_FIRST_PAGE_IDX (FLASH_RO_LAST_PAGE_IDX + 1)
-#define FLASH_RW_LAST_PAGE_IDX (FLASH_PAGE_MAX_COUNT - 1)
-
-
-#define FLASH_PAGE_ROLLBACK_COUNT ROLLBACK_BANK_COUNT
-#define FLASH_PAGE_ROLLBACK_FIRST_IDX ROLLBACK_BANK_OFFSET
-#define FLASH_PAGE_ROLLBACK_LAST_IDX (FLASH_PAGE_ROLLBACK_FIRST_IDX +\
-					FLASH_PAGE_ROLLBACK_COUNT -1)
-
-#ifdef STM32_FLASH_DBANK_MODE
-#define FLASH_WRP_MASK              (FLASH_PAGE_MAX_COUNT - 1)
-#else
-#ifdef CHIP_FAMILY_STM32L4
-#define FLASH_WRP_MASK              0xFF
-#else
-#define FLASH_WRP_MASK              ((FLASH_PAGE_MAX_COUNT) / 2 - 1)
-#endif
-#endif /* CONFIG_FLASH_DBANK_MODE */
-#define FLASH_WRP_START(val)        ((val) & FLASH_WRP_MASK)
-#define FLASH_WRP_END(val)          (((val) >> 16) & FLASH_WRP_MASK)
-#define FLASH_WRP_RANGE(start, end) (((start) & FLASH_WRP_MASK) | \
-				       (((end) & FLASH_WRP_MASK) << 16))
-#define FLASH_WRP_RANGE_DISABLED    FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00)
-#define FLASH_WRP1X_MASK FLASH_WRP_RANGE(FLASH_WRP_MASK, FLASH_WRP_MASK)
-
-enum wrp_region {
-	WRP_RO,
-	WRP_RW,
-};
-
-struct wrp_info {
-	int enable;
-	int start;
-	int end;
-};
-
-static inline int calculate_flash_timeout(void)
-{
-	return (FLASH_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
-}
-
-static int wait_while_busy(void)
-{
-	int timeout = calculate_flash_timeout();
-
-	while (STM32_FLASH_SR & FLASH_SR_BUSY && timeout-- > 0)
-		;
-	return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-}
-
-static int unlock(int locks)
-{
-	/*
-	 * We may have already locked the flash module and get a bus fault
-	 * in the attempt to unlock. Need to disable bus fault handler now.
-	 */
-	ignore_bus_fault(1);
-
-	/* unlock CR if needed */
-	if (STM32_FLASH_CR & FLASH_CR_LOCK) {
-		STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
-		STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
-	}
-	/* unlock option memory if required */
-	if ((locks & FLASH_CR_OPTLOCK) &&
-	    (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) {
-		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
-		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
-	}
-
-	/* Re-enable bus fault handler */
-	ignore_bus_fault(0);
-
-	return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN
-							  : EC_SUCCESS;
-}
-
-static void lock(void)
-{
-	STM32_FLASH_CR |= FLASH_CR_LOCK;
-}
-
-static void ob_lock(void)
-{
-	STM32_FLASH_CR |= FLASH_CR_OPTLOCK;
-}
-
-/*
- * Option byte organization
- *
- *                [63:56][55:48][47:40][39:32]   [31:24][23:16][15: 8][ 7: 0]
- * +--------------+-------------------+------+   +-------------------+------+
- * | 0x1FFF7800   |         nUSER     | nRDP |   |       USER        |  RDP |
- * +--------------+------------+------+------+   +------------+------+------+
- * | 0x1FFF7808   |            | nPCROP1_STRT|   |            | PCROP1_STRT |
- * +--------------+------------+-------------+   +------------+-------------+
- * | 0x1FFF7810   |            | nPCROP1_END |   |            | PCROP1_END  |
- * +--------------+------------+-------------+   +------------+-------------+
- * | 0x1FFF7818   |     |nWRP1A|      |nWRP1A|   |     | WRP1A|      | WRP1A|
- * |              |     |_END  |      |_STRT |   |     | _END |      | _STRT|
- * +--------------+------------+-------------+   +------------+-------------+
- * | 0x1FFF7820   |     |nWRP1B|      |nWRP1B|   |     | WRP1B|      | WRP1B|
- * |              |     |_END  |      |_STRT |   |     | _END |      | _STRT|
- * +--------------+------------+-------------+   +------------+-------------+
- * | 0x1FFF7828   |     |nBOOT |      |nSEC_ |   |     | BOOT |      | SEC_ |
- * |              |     |LOCK  |      |SIZE1 |   |     | _LOCK|      | SIZE1|
- * +--------------+------------+-------------+   +------------+-------------+
- *
- * Note that the variable with n prefix means the complement.
- */
-static int unlock_optb(void)
-{
-	int rv;
-
-	rv = wait_while_busy();
-	if (rv)
-		return rv;
-
-	rv = unlock(FLASH_CR_OPTLOCK);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS;
-}
-
-static int commit_optb(void)
-{
-	int rv;
-
-	/*
-	 * Wait for last operation.
-	 */
-	rv = wait_while_busy();
-	if (rv)
-		return rv;
-
-	STM32_FLASH_CR |= FLASH_CR_OPTSTRT;
-
-	rv = wait_while_busy();
-	if (rv)
-		return rv;
-
-	ob_lock();
-	lock();
-
-	return EC_SUCCESS;
-}
-
-/*
- * There are a minimum of 2 WRP regions that can be set. The STM32G4
- * family has both category 2, and category 3 devices. Category 2
- * devices have only 2 WRP regions, but category 3 devices have 4 WRP
- * regions that can be configured. Category 3 devices also support dual
- * flash banks, and this mode is the default setting. When DB mode is enabled,
- * then each WRP register can only protect up to 64 2kB pages. This means that
- * one WRP register is needed per bank.
- *
- *   1. WRP1A -> used always for RO
- *   2. WRP1B -> used always for RW
- *   3. WRP2A -> may be used for RW if dual-bank (DB) mode is enabled
- *   4. WRP2B -> currently never used
- *
- * WRP areas are specified in terms of page indices with a start index
- * and an end index. start == end means a single page is protected.
- *
- *   WRPnx_start = WRPnx_end  --> WRPnx_start page is protected
- *   WRPnx_start > WRPnx_end  --> No WRP area is specified
- *   WRPnx_start < WRPnx_end  --> Pages WRPnx_start to WRPnx_end
- */
-static void optb_get_wrp(enum wrp_region region, struct wrp_info *wrp)
-{
-#ifdef STM32_FLASH_DBANK_MODE
-	int start;
-	int end;
-#endif
-	/* Assume WRP regions are not configured */
-	wrp->start = FLASH_WRP_MASK;
-	wrp->end = 0;
-	wrp->enable = 0;
-
-	if (region == WRP_RO) {
-		/*
-		 * RO write protect is fully described by WRP1AR. Get the
-		 * start/end indices. If end >= start, then RO write protect is
-		 * enabled.
-		 */
-		wrp->start = FLASH_WRP_START(STM32_OPTB_WRP1AR);
-		wrp->end = FLASH_WRP_END(STM32_OPTB_WRP1AR);
-		wrp->enable = wrp->end >= wrp->start;
-	} else if (region == WRP_RW) {
-		/*
-		 * RW write always uses WRP1BR. If dual-bank mode is being used,
-		 * then WRP2AR must also be check to determine the full range of
-		 * flash page indices being protected.
-		 */
-		wrp->start = FLASH_WRP_START(STM32_OPTB_WRP1BR);
-		wrp->end = FLASH_WRP_END(STM32_OPTB_WRP1BR);
-		wrp->enable = wrp->end >= wrp->start;
-#ifdef STM32_FLASH_DBANK_MODE
-		start = FLASH_WRP_START(STM32_FLASH_WRP2AR);
-		end = FLASH_WRP_END(STM32_FLASH_WRP2AR);
-		/*
-		 * If WRP2AR protection is enabled, then need to adjust either
-		 * the start, end, or both indices.
-		 */
-		if (end >= start) {
-			if (wrp->enable) {
-				/* WRP1BR is active, only need to adjust end */
-				wrp->end += end;
-			} else {
-				/*
-				 * WRP1BR is not active, so RW protection, if
-				 * enabled, is fully controlled by WRP2AR.
-				 */
-				wrp->start = start;
-				wrp->end = end;
-				wrp->enable = 1;
-			}
-		}
-#endif
-	}
-}
-
-static void optb_set_wrp(enum wrp_region region, struct wrp_info *wrp)
-{
-	int start = wrp->start;
-	int end = wrp->end;
-
-	if (!wrp->enable) {
-		/*
-		 * If enable is not set, then ignore the passed in start/end
-		 * values and set start/end to the default not protected range
-		 * which satisfies start > end
-		 */
-		start = FLASH_WRP_MASK;
-		end = 0;
-	}
-
-	if (region == WRP_RO) {
-		/* For RO can always use start/end directly */
-		STM32_FLASH_WRP1AR = FLASH_WRP_RANGE(start, end);
-	} else if (region == WRP_RW) {
-#ifdef STM32_FLASH_DBANK_MODE
-		/*
-		 * In the dual-bank flash case (STM32G4 Category 3 devices with
-		 * DB bit set), RW write protect can use both WRP1BR and WRP2AR
-		 * registers in order to span the full flash memory range.
-		 */
-		if (wrp->enable) {
-			int rw_end;
-
-			/*
-			 * If the 1st RW flash page is in the 1st half of
-			 * memory, then at least one block will be protected by
-			 * WRP1BR. If the end flash page is in the 2nd half of
-			 * memory, then cap the end for WRP1BR to its max
-			 * value. Otherwise, can use end passed in directly.
-			 */
-			if (start <= FLASH_WRP_MASK) {
-				rw_end = end > FLASH_WRP_MASK ?
-					FLASH_WRP_MASK : end;
-				STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start,
-								     rw_end);
-			}
-			/*
-			 * If the last RW flash page is in the 2nd half of
-			 * memory, then at least one block will be protected by
-			 * WRP2AR. If the start flash page is in the 2nd half of
-			 * memory, can use start directly. Otherwise, start
-			 * needs to be set to 0 here.
-			 */
-			if (end > FLASH_WRP_MASK) {
-				rw_end = end & FLASH_WRP_MASK;
-				STM32_FLASH_WRP2AR = FLASH_WRP_RANGE(0, rw_end);
-			}
-		} else {
-			/*
-			 * RW write protect is being disabled. Set both WRP1BR
-			 * and WRP2AR to default start > end not protected
-			 * state.
-			 */
-			STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, end);
-			STM32_FLASH_WRP2AR = FLASH_WRP_RANGE(start, end);
-		}
-#else
-		/* Single bank case, WRP1BR can cover the full memory range */
-		STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, end);
-#endif
-	}
-}
-
-static void unprotect_all_blocks(void)
-{
-	struct wrp_info wrp;
-
-	/* Set info values to unprotected */
-	wrp.start = FLASH_WRP_MASK;
-	wrp.end = 0;
-	wrp.enable = 0;
-
-	unlock_optb();
-	/* Disable RO WRP */
-	optb_set_wrp(WRP_RO, &wrp);
-	/* Disable RW WRP */
-	optb_set_wrp(WRP_RW, &wrp);
-	commit_optb();
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	struct wrp_info wrp_ro;
-	struct wrp_info wrp_rw;
-
-	wrp_ro.start = FLASH_WRP_MASK;
-	wrp_ro.end = 0;
-	wrp_ro.enable = 0;
-
-	wrp_rw.start = FLASH_WRP_MASK;
-	wrp_rw.end = 0;
-	wrp_rw.enable = 0;
-
-	/*
-	 * Default operation for this function is to disable both RO and RW
-	 * write protection in the option bytes. Based on new_flags either RO or
-	 * RW or both regions write protect may be set.
-	 */
-	if (new_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_RO_AT_BOOT)) {
-		wrp_ro.start = FLASH_RO_FIRST_PAGE_IDX;
-		wrp_ro.end = FLASH_RO_LAST_PAGE_IDX;
-		wrp_ro.enable = 1;
-	}
-
-	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) {
-		wrp_rw.start = FLASH_RW_FIRST_PAGE_IDX;
-		wrp_rw.end = FLASH_RW_LAST_PAGE_IDX;
-		wrp_rw.enable = 1;
-	} else {
-		/*
-		 * Start index will be 1st index following RO region index. The
-		 * end index is initialized as 'no protect' value. Only if end
-		 * gets changed based on either rollback or RW protection will
-		 * the 2nd memory protection area get written in option bytes.
-		 */
-		int start = FLASH_RW_FIRST_PAGE_IDX;
-		int end = 0;
-#ifdef CONFIG_ROLLBACK
-		if (new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) {
-			start = FLASH_PAGE_ROLLBACK_FIRST_IDX;
-			end = FLASH_PAGE_ROLLBACK_LAST_IDX;
-		} else {
-			start = FLASH_PAGE_ROLLBACK_LAST_IDX;
-		}
-#endif /* !CONFIG_ROLLBACK */
-#ifdef CONFIG_FLASH_PROTECT_RW
-		if (new_flags & EC_FLASH_PROTECT_RW_AT_BOOT)
-			end = FLASH_RW_LAST_PAGE_IDX;
-#endif /* CONFIG_FLASH_PROTECT_RW */
-
-		if (end) {
-			wrp_rw.start = start;
-			wrp_rw.end = end;
-			wrp_rw.enable = 1;
-		}
-	}
-
-	unlock_optb();
-#ifdef CONFIG_FLASH_READOUT_PROTECTION
-	/*
-	 * Set a permanent protection by increasing RDP to level 1,
-	 * trying to unprotected the flash will trigger a full erase.
-	 */
-	STM32_FLASH_OPTR = (STM32_FLASH_OPTR & ~0xff) | 0x11;
-#endif
-	optb_set_wrp(WRP_RO, &wrp_ro);
-	optb_set_wrp(WRP_RW, &wrp_rw);
-	commit_optb();
-
-	return EC_SUCCESS;
-}
-
-/**
- * Check if write protect register state is inconsistent with RO_AT_BOOT and
- * ALL_AT_BOOT state.
- *
- * @return zero if consistent, non-zero if inconsistent.
- */
-static int registers_need_reset(void)
-{
-	uint32_t flags = crec_flash_get_protect();
-	int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0;
-	/* The RO region is write-protected by the WRP1AR range. */
-	uint32_t wrp1ar = STM32_OPTB_WRP1AR;
-	uint32_t ro_range = ro_at_boot ?
-		FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX,
-				  FLASH_RO_LAST_PAGE_IDX)
-		: FLASH_WRP_RANGE_DISABLED;
-
-	return ro_range != (wrp1ar & FLASH_WRP1X_MASK);
-}
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	uint32_t *address = (void *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	int res = EC_SUCCESS;
-	int timeout = calculate_flash_timeout();
-	int i;
-	int unaligned = (uint32_t)data & (STM32_FLASH_MIN_WRITE_SIZE - 1);
-	uint32_t *data32 = (void *)data;
-
-	/* Check Flash offset */
-	if (offset % STM32_FLASH_MIN_WRITE_SIZE)
-		return EC_ERROR_MEMORY_ALLOCATION;
-
-	if (unlock(FLASH_CR_LOCK) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = FLASH_SR_ERR_MASK;
-
-	/* set PG bit */
-	STM32_FLASH_CR |= FLASH_CR_PG;
-
-	for (; size > 0; size -= STM32_FLASH_MIN_WRITE_SIZE) {
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset when doing
-		 * long writing.
-		 */
-		watchdog_reload();
-
-		/* wait to be ready  */
-		for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout);
-		     i++)
-			;
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		/* write the 2 words */
-		if (unaligned) {
-			*address++ = (uint32_t)data[0] | (data[1] << 8)
-				   | (data[2] << 16) | (data[3] << 24);
-			*address++ = (uint32_t)data[4] | (data[5] << 8)
-				   | (data[6] << 16) | (data[7] << 24);
-			data += STM32_FLASH_MIN_WRITE_SIZE;
-		} else {
-			*address++ = *data32++;
-			*address++ = *data32++;
-		}
-
-		/* Wait for writes to complete */
-		for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout);
-		     i++)
-			;
-
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		/*
-		 * Check for error conditions - erase failed, voltage error,
-		 * protection error.
-		 */
-		if (STM32_FLASH_SR & FLASH_SR_ERR_MASK) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_wr;
-		}
-	}
-
-exit_wr:
-	/* Disable PG bit */
-	STM32_FLASH_CR &= ~FLASH_CR_PG;
-
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int res = EC_SUCCESS;
-	int pg;
-	int last;
-
-	if (unlock(FLASH_CR_LOCK) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = FLASH_SR_ERR_MASK;
-
-	last = (offset + size) / CONFIG_FLASH_ERASE_SIZE;
-	for (pg = offset / CONFIG_FLASH_ERASE_SIZE; pg < last; pg++) {
-		timestamp_t deadline;
-
-		/* select page to erase and PER bit */
-		STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK)
-				| FLASH_CR_PER | FLASH_CR_PNB(pg);
-
-		/* set STRT bit : start erase */
-		STM32_FLASH_CR |= FLASH_CR_STRT;
-
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset during a
-		 * long erase operation.
-		 */
-		watchdog_reload();
-
-		deadline.val = get_time().val + FLASH_TIMEOUT_US;
-		/* Wait for erase to complete */
-		while ((STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		       (get_time().val < deadline.val)) {
-			usleep(300);
-		}
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_er;
-		}
-
-		/*
-		 * Check for error conditions - erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR & FLASH_SR_ERR_MASK) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_er;
-		}
-	}
-
-exit_er:
-	/* reset PER bit */
-	STM32_FLASH_CR &= ~(FLASH_CR_PER | FLASH_CR_PNB_MASK);
-
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_get_protect(int block)
-{
-	struct wrp_info wrp_ro;
-	struct wrp_info wrp_rw;
-
-	optb_get_wrp(WRP_RO, &wrp_ro);
-	optb_get_wrp(WRP_RW, &wrp_rw);
-
-	return ((block >= wrp_ro.start) && (block <= wrp_ro.end)) ||
-		((block >= wrp_rw.start) && (block <= wrp_rw.end));
-}
-
-/*
- * Note: This does not need to update _NOW flags, as get_protect_flags
- * in common code already does so.
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-	struct wrp_info wrp_ro;
-	struct wrp_info wrp_rw;
-
-	optb_get_wrp(WRP_RO, &wrp_ro);
-	optb_get_wrp(WRP_RW, &wrp_rw);
-
-	/* Check if RO is fully protected */
-	if (wrp_ro.start == FLASH_RO_FIRST_PAGE_IDX &&
-	    wrp_ro.end == FLASH_RO_LAST_PAGE_IDX)
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	if (wrp_rw.enable) {
-
-#ifdef CONFIG_ROLLBACK
-		if (wrp_rw.start <= FLASH_PAGE_ROLLBACK_FIRST_IDX &&
-		    wrp_rw.end >= FLASH_PAGE_ROLLBACK_LAST_IDX)
-			flags |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif /* CONFIG_ROLLBACK */
-#ifdef CONFIG_FLASH_PROTECT_RW
-		if (wrp_rw.end == PHYSICAL_BANKS)
-			flags |= EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif /* CONFIG_FLASH_PROTECT_RW */
-		if (wrp_rw.end == PHYSICAL_BANKS &&
-		    wrp_rw.start == WP_BANK_OFFSET + WP_BANK_COUNT &&
-		    flags & EC_FLASH_PROTECT_RO_AT_BOOT)
-			flags |= EC_FLASH_PROTECT_ALL_AT_BOOT;
-	}
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	return EC_ERROR_INVAL;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-#ifdef CONFIG_FLASH_PROTECT_RW
-	       EC_FLASH_PROTECT_RW_AT_BOOT |
-	       EC_FLASH_PROTECT_RW_NOW |
-#endif
-#ifdef CONFIG_ROLLBACK
-	       EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-	       EC_FLASH_PROTECT_ROLLBACK_NOW |
-#endif
-	       EC_FLASH_PROTECT_ALL_AT_BOOT |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * ALL/RW at-boot state can be set if WP GPIO is asserted and can always
-	 * be cleared.
-	 */
-	if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_AT_BOOT;
-
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-
-#ifdef CONFIG_ROLLBACK
-	if (cur_flags & (EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif
-
-	return ret;
-}
-
-int crec_flash_physical_force_reload(void)
-{
-	int rv = unlock(FLASH_CR_OPTLOCK);
-
-	if (rv)
-		return rv;
-
-	/* Force a reboot; this should never return. */
-	STM32_FLASH_CR = FLASH_CR_OBL_LAUNCH;
-	while (1)
-		;
-
-	return EC_ERROR_UNKNOWN;
-}
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	int need_reset = 0;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			/*
-			 * Pstate wants RO protected at boot, but the write
-			 * protect register wasn't set to protect it.  Force an
-			 * update to the write protect register and reboot so
-			 * it takes effect.
-			 */
-			crec_flash_physical_protect_at_boot(
-				EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-
-		if (registers_need_reset()) {
-			/*
-			 * Write protect register was in an inconsistent state.
-			 * Set it back to a good state and reboot.
-			 *
-			 * TODO(crosbug.com/p/23798): this seems really similar
-			 * to the check above.  One of them should be able to
-			 * go away.
-			 */
-			crec_flash_protect_at_boot(
-				prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-	} else {
-		if (prot_flags & EC_FLASH_PROTECT_RO_NOW) {
-			/*
-			 * Write protect pin unasserted but some section is
-			 * protected. Drop it and reboot.
-			 */
-			unprotect_all_blocks();
-			need_reset = 1;
-		}
-	}
-
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_ALL_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) {
-		/*
-		 * ALL_AT_BOOT and ALL_NOW should be both set or both unset
-		 * at boot. If they are not, it must be that the chip requires
-		 * OBL_LAUNCH to be set to reload option bytes. Let's reset
-		 * the system with OBL_LAUNCH set.
-		 * This assumes OBL_LAUNCH is used for hard reset in
-		 * chip/stm32/system.c.
-		 */
-		need_reset = 1;
-	}
-
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_RW_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) {
-		/* RW_AT_BOOT and RW_NOW do not match. */
-		need_reset = 1;
-	}
-#endif
-
-#ifdef CONFIG_ROLLBACK
-	if ((crec_flash_physical_get_valid_flags() &
-	     EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) {
-		/* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */
-		need_reset = 1;
-	}
-#endif
-
-	if (need_reset)
-		system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	return EC_SUCCESS;
-}
diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c
deleted file mode 100644
index 087ddbf062..0000000000
--- a/chip/stm32/flash-stm32h7.c
+++ /dev/null
@@ -1,643 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Flash memory module for STM32H7 family */
-
-#include "common.h"
-#include "clock.h"
-#include "cpu.h"
-#include "flash.h"
-#include "flash-regs.h"
-#include "hooks.h"
-#include "registers.h"
-#include "panic.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * Approximate number of CPU cycles per iteration of the loop when polling
- * the flash status
- */
-#define CYCLE_PER_FLASH_LOOP 2
-
-/* Flash 256-bit word programming timeout. */
-#define FLASH_TIMEOUT_US 600
-
-/*
- * Flash 128-KB block erase timeout.
- * Datasheet says maximum is about 4 seconds in x8.
- * Real delay seems to be: < 1 second in x64, < 2 seconds in x8.
- */
-#define FLASH_ERASE_TIMEOUT_US (4200 * MSEC)
-
-/*
- * Option bytes programming timeout.
- * No specification, real delay seems to be around 300ms.
- */
-#define FLASH_OPT_PRG_TIMEOUT_US (1000 * MSEC)
-
-/*
- * All variants have 2 banks (as in parallel hardware / controllers)
- * not what is called 'bank' in the common code (ie Write-Protect sectors)
- * both have the same number of 128KB blocks.
- */
-#define HWBANK_SIZE  (CONFIG_FLASH_SIZE_BYTES / 2)
-#define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE)
-#define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1)
-
-/*
- * We can tune the power consumption vs erase/write speed
- * by default, go fast (and consume current)
- */
-#define DEFAULT_PSIZE FLASH_CR_PSIZE_DWORD
-
-/* Can no longer write/erase flash until next reboot */
-static int access_disabled;
-/* Can no longer modify write-protection in option bytes until next reboot */
-static int option_disabled;
-/* Is physical flash stuck protected? (avoid reboot loop) */
-static int stuck_locked;
-
-#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
-#define FLASH_HOOK_VERSION 1
-
-/* The previous write protect state before sys jump */
-struct flash_wp_state {
-	int access_disabled;
-	int option_disabled;
-	int stuck_locked;
-};
-
-static inline int calculate_flash_timeout(void)
-{
-	return (FLASH_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
-}
-
-static int unlock(int bank)
-{
-	/* unlock CR only if needed */
-	if (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) {
-		/*
-		 * We may have already locked the flash module and get a bus
-		 * fault in the attempt to unlock. Need to disable bus fault
-		 * handler now.
-		 */
-		ignore_bus_fault(1);
-
-		STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY1;
-		STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY2;
-		ignore_bus_fault(0);
-	}
-
-	return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN
-						      : EC_SUCCESS;
-}
-
-static void lock(int bank)
-{
-	STM32_FLASH_CR(bank) |= FLASH_CR_LOCK;
-}
-
-static int unlock_optb(void)
-{
-	if (option_disabled)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (unlock(0))
-		return EC_ERROR_UNKNOWN;
-
-	if (flash_option_bytes_locked()) {
-		/*
-		 * We may have already locked the flash module and get a bus
-		 * fault in the attempt to unlock. Need to disable bus fault
-		 * handler now.
-		 */
-		ignore_bus_fault(1);
-
-		unlock_flash_option_bytes();
-		ignore_bus_fault(0);
-	}
-
-	return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN
-					   : EC_SUCCESS;
-}
-
-static int commit_optb(void)
-{
-	/* might use this before timer_init, cannot use get_time/usleep */
-	int timeout = (FLASH_OPT_PRG_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
-
-	STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTSTART;
-
-	while (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_BUSY && timeout-- > 0)
-		;
-
-	lock_flash_option_bytes();
-	lock(0);
-
-	return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-}
-
-static void protect_blocks(uint32_t blocks)
-{
-	if (unlock_optb())
-		return;
-	STM32_FLASH_WPSN_PRG(0) &= ~(blocks & BLOCKS_HWBANK_MASK);
-	STM32_FLASH_WPSN_PRG(1) &= ~((blocks >> BLOCKS_PER_HWBANK)
-				& BLOCKS_HWBANK_MASK);
-	commit_optb();
-}
-
-
-/*
- * Helper function definitions for consistency with F4 to enable flash
- * physical unitesting
- */
-void unlock_flash_control_register(void)
-{
-	unlock(0);
-	unlock(1);
-}
-
-void unlock_flash_option_bytes(void)
-{
-	/*
-	 * Always use bank 0 flash controller as there is only one option bytes
-	 * set for both banks. See http://b/181130245
-	 *
-	 * Consecutively program values. Ref: RM0433:4.9.2
-	 */
-	STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY1;
-	STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY2;
-}
-
-void disable_flash_option_bytes(void)
-{
-	ignore_bus_fault(1);
-	/*
-	 * Always use bank 0 flash controller as there is only one option bytes
-	 * set for both banks. See http://b/181130245
-	 *
-	 * Writing anything other than the pre-defined keys to the option key
-	 * register results in a bus fault and the register being locked until
-	 * reboot (even with a further correct key write).
-	 */
-	STM32_FLASH_OPTKEYR(0) = 0xffffffff;
-	ignore_bus_fault(0);
-}
-
-void disable_flash_control_register(void)
-{
-	ignore_bus_fault(1);
-	/*
-	 * Writing anything other than the pre-defined keys to a key
-	 * register results in a bus fault and the register being locked until
-	 * reboot (even with a further correct key write).
-	 */
-	STM32_FLASH_KEYR(0) = 0xffffffff;
-	STM32_FLASH_KEYR(1) = 0xffffffff;
-	ignore_bus_fault(0);
-}
-
-void lock_flash_control_register(void)
-{
-	lock(0);
-	lock(1);
-}
-
-void lock_flash_option_bytes(void)
-{
-	/*
-	 * Always use bank 0 flash controller as there is only one option bytes
-	 * set for both banks. See http://b/181130245
-	 */
-	STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTLOCK;
-}
-
-bool flash_option_bytes_locked(void)
-{
-	/*
-	 * Always use bank 0 flash controller as there is only one option bytes
-	 * set for both banks. See http://b/181130245
-	 */
-	return  !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK);
-}
-
-bool flash_control_register_locked(void)
-{
-	return !!(STM32_FLASH_CR(0) & FLASH_CR_LOCK) &&
-	       !!(STM32_FLASH_CR(1) & FLASH_CR_LOCK);
-}
-
-/*
- * If RDP as PSTATE option is defined, use that as 'Write Protect enabled' flag:
- * it makes no sense to be able to unlock RO, as that'd allow flashing
- * arbitrary RO that could read back all flash.
- *
- * crbug.com/888109: Do not copy this code over to other STM32 chips without
- * understanding the full implications.
- *
- * If RDP is not defined, use the option bytes RSS1 bit.
- * TODO(crbug.com/888104): Validate that using RSS1 for this purpose is safe.
- */
-#ifndef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-#error "crbug.com/888104: Using RSS1 for write protect PSTATE may not be safe."
-#endif
-static int is_wp_enabled(void)
-{
-#ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-	return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK)
-		!= FLASH_OPTSR_RDP_LEVEL_0;
-#else
-	return !!(STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RSS1);
-#endif
-}
-
-static int set_wp(int enabled)
-{
-	int rv;
-
-	rv = unlock_optb();
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-	if (enabled) {
-		/* Enable RDP level 1. */
-		STM32_FLASH_OPTSR_PRG(0) =
-			(STM32_FLASH_OPTSR_PRG(0) & ~FLASH_OPTSR_RDP_MASK) |
-			FLASH_OPTSR_RDP_LEVEL_1;
-	}
-#else
-	if (enabled)
-		STM32_FLASH_OPTSR_PRG(0) |= FLASH_OPTSR_RSS1;
-	else
-		STM32_FLASH_OPTSR_PRG(0) &= ~FLASH_OPTSR_RSS1;
-#endif
-
-	return commit_optb();
-}
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int res = EC_SUCCESS;
-	int bank = offset / HWBANK_SIZE;
-	uint32_t *address = (void *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	int timeout = calculate_flash_timeout();
-	int i;
-	int unaligned = (uint32_t)data & (CONFIG_FLASH_WRITE_SIZE - 1);
-	uint32_t *data32 = (void *)data;
-
-	if (access_disabled)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* work on a single hardware bank at a time */
-	if ((offset + size - 1) / HWBANK_SIZE != bank)
-		return EC_ERROR_INVAL;
-
-	if (unlock(bank) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK;
-
-	/* select write parallelism */
-	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK)
-			| DEFAULT_PSIZE;
-
-	/* set PG bit */
-	STM32_FLASH_CR(bank) |= FLASH_CR_PG;
-
-	for (; size > 0; size -= CONFIG_FLASH_WRITE_SIZE) {
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset when doing
-		 * long writing.
-		 */
-		watchdog_reload();
-
-		/* write a 256-bit flash word */
-		if (unaligned) {
-			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++,
-								     data += 4)
-				*address++ = (uint32_t)data[0] | (data[1] << 8)
-					   | (data[2] << 16) | (data[3] << 24);
-		} else {
-			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++)
-				*address++ = *data32++;
-		}
-
-		/* Wait for writes to complete */
-		for (i = 0; (STM32_FLASH_SR(bank) &
-		     (FLASH_SR_WBNE | FLASH_SR_QW)) && (i < timeout); i++)
-			;
-
-		if (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		if (STM32_FLASH_SR(bank) & FLASH_CCR_ERR_MASK) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_wr;
-		}
-	}
-
-exit_wr:
-	/* Disable PG bit */
-	STM32_FLASH_CR(bank) &= ~FLASH_CR_PG;
-
-	lock(bank);
-
-#ifdef CONFIG_ARMV7M_CACHE
-	/* Invalidate D-cache, to make sure we do not read back stale data. */
-	cpu_clean_invalidate_dcache();
-#endif
-
-	return res;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int res = EC_SUCCESS;
-	int bank = offset / HWBANK_SIZE;
-	int last = (offset + size) / CONFIG_FLASH_ERASE_SIZE;
-	int sect;
-
-	if (access_disabled)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* work on a single hardware bank at a time */
-	if ((offset + size - 1) / HWBANK_SIZE != bank)
-		return EC_ERROR_INVAL;
-
-	if (unlock(bank) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK;
-
-	/* select erase parallelism */
-	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK)
-			| DEFAULT_PSIZE;
-
-	for (sect = offset / CONFIG_FLASH_ERASE_SIZE; sect < last; sect++) {
-		timestamp_t deadline;
-
-		/* select page to erase and PER bit */
-		STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank)
-					& ~FLASH_CR_SNB_MASK)
-				| FLASH_CR_SER | FLASH_CR_SNB(sect);
-
-		/* set STRT bit : start erase */
-		STM32_FLASH_CR(bank) |= FLASH_CR_STRT;
-
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset during a
-		 * long erase operation.
-		 */
-		watchdog_reload();
-
-		deadline.val = get_time().val + FLASH_ERASE_TIMEOUT_US;
-		/* Wait for erase to complete */
-		while ((STM32_FLASH_SR(bank) & FLASH_SR_BUSY) &&
-		       (get_time().val < deadline.val)) {
-			/*
-			 * Interrupts may not be enabled, so we are using
-			 * udelay() instead of usleep() which can trigger
-			 * Forced Hard Fault (see b/180761547).
-			 */
-			udelay(5000);
-		}
-		if (STM32_FLASH_SR(bank) & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_er;
-		}
-
-		/*
-		 * Check for error conditions - erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR(bank) & FLASH_CCR_ERR_MASK) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_er;
-		}
-	}
-
-exit_er:
-	/* reset SER bit */
-	STM32_FLASH_CR(bank) &= ~(FLASH_CR_SER | FLASH_CR_SNB_MASK);
-
-	lock(bank);
-
-#ifdef CONFIG_ARMV7M_CACHE
-	/* Invalidate D-cache, to make sure we do not read back stale data. */
-	cpu_clean_invalidate_dcache();
-#endif
-
-	return res;
-}
-
-int crec_flash_physical_get_protect(int block)
-{
-	int bank = block / BLOCKS_PER_HWBANK;
-	int index = block % BLOCKS_PER_HWBANK;
-
-	return !(STM32_FLASH_WPSN_CUR(bank) & BIT(index));
-}
-
-/*
- * Note: This does not need to update _NOW flags, as flash_get_protect
- * in common code already does so.
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	if (access_disabled)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	if (is_wp_enabled())
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/* Check if blocks were stuck locked at pre-init */
-	if (stuck_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_STUCK;
-
-	return flags;
-}
-
-#define WP_RANGE(start, count) (((1 << (count)) - 1) << (start))
-#define RO_WP_RANGE WP_RANGE(WP_BANK_OFFSET, WP_BANK_COUNT)
-
-int crec_flash_physical_protect_now(int all)
-{
-	protect_blocks(RO_WP_RANGE);
-
-	/*
-	 * Lock the option bytes or the full access by writing a wrong
-	 * key to FLASH_*KEYR. This triggers a bus fault, so we need to
-	 * disable bus fault handler while doing this.
-	 *
-	 * This incorrect key fault causes the flash to become
-	 * permanently locked until reset, a correct keyring write
-	 * will not unlock it.
-	 */
-
-	if (all) {
-		/* cannot do any write/erase access until next reboot */
-		disable_flash_control_register();
-		access_disabled = 1;
-	}
-	/* cannot modify the WP bits in the option bytes until reboot */
-	disable_flash_option_bytes();
-	option_disabled = 1;
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int new_wp_enable = !!(new_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
-
-	if (is_wp_enabled() != new_wp_enable)
-		return set_wp(new_wp_enable);
-
-	return EC_SUCCESS;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	int version, size;
-	const struct flash_wp_state *prev;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. We simply need to represent these
-         * irreversible flags to other components.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
-		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
-		if (prev && version == FLASH_HOOK_VERSION &&
-		    size == sizeof(*prev)) {
-			access_disabled = prev->access_disabled;
-			option_disabled = prev->option_disabled;
-			stuck_locked = prev->stuck_locked;
-		}
-		return 1;
-	}
-
-	return 0;
-}
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	if (crec_flash_physical_restore_state())
-		return EC_SUCCESS;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv;
-
-			rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						    EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = crec_flash_get_protect();
-		}
-	} else {
-		/* Don't want RO flash protected */
-		unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	/* If there are no unwanted flags, done */
-	if (!(prot_flags & unwanted_prot_flags))
-		return EC_SUCCESS;
-
-	/*
-	 * If the last reboot was a power-on reset, it should have cleared
-	 * write-protect.  If it didn't, then the flash write protect registers
-	 * have been permanently committed and we can't fix that.
-	 */
-	if (reset_flags & EC_RESET_FLAG_POWER_ON) {
-		stuck_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* Otherwise, do a hard boot to clear the flash protection registers */
-	system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	/* That doesn't return, so if we're still here that's an error */
-	return EC_ERROR_UNKNOWN;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void flash_preserve_state(void)
-{
-	const struct flash_wp_state state = {
-		.access_disabled = access_disabled,
-		.option_disabled = option_disabled,
-		.stuck_locked = stuck_locked,
-	};
-
-	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c
deleted file mode 100644
index f34200219a..0000000000
--- a/chip/stm32/flash-stm32l.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "flash.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * Approximate number of CPU cycles per iteration of the loop when polling
- * the flash status.
- */
-#define CYCLE_PER_FLASH_LOOP 10
-
-/* Flash page programming timeout.  This is 2x the datasheet max. */
-#define FLASH_TIMEOUT_MS 16
-
-static int flash_timeout_loop;
-
-/**
- * Lock all the locks.
- */
-static void lock(void)
-{
-	ignore_bus_fault(1);
-
-	STM32_FLASH_PECR = STM32_FLASH_PECR_PE_LOCK |
-		STM32_FLASH_PECR_PRG_LOCK | STM32_FLASH_PECR_OPT_LOCK;
-
-	ignore_bus_fault(0);
-}
-
-/**
- * Unlock the specified locks.
- */
-static int unlock(int locks)
-{
-	/*
-	 * We may have already locked the flash module and get a bus fault
-	 * in the attempt to unlock. Need to disable bus fault handler now.
-	 */
-	ignore_bus_fault(1);
-
-	/* Unlock PECR if needed */
-	if (STM32_FLASH_PECR & STM32_FLASH_PECR_PE_LOCK) {
-		STM32_FLASH_PEKEYR = STM32_FLASH_PEKEYR_KEY1;
-		STM32_FLASH_PEKEYR = STM32_FLASH_PEKEYR_KEY2;
-	}
-
-	/* Fail if it didn't unlock */
-	if (STM32_FLASH_PECR & STM32_FLASH_PECR_PE_LOCK) {
-		ignore_bus_fault(0);
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* Unlock program memory if required */
-	if ((locks & STM32_FLASH_PECR_PRG_LOCK) &&
-	    (STM32_FLASH_PECR & STM32_FLASH_PECR_PRG_LOCK)) {
-		STM32_FLASH_PRGKEYR = STM32_FLASH_PRGKEYR_KEY1;
-		STM32_FLASH_PRGKEYR = STM32_FLASH_PRGKEYR_KEY2;
-	}
-
-	/* Unlock option memory if required */
-	if ((locks & STM32_FLASH_PECR_OPT_LOCK) &&
-	    (STM32_FLASH_PECR & STM32_FLASH_PECR_OPT_LOCK)) {
-		STM32_FLASH_OPTKEYR = STM32_FLASH_OPTKEYR_KEY1;
-		STM32_FLASH_OPTKEYR = STM32_FLASH_OPTKEYR_KEY2;
-	}
-
-	ignore_bus_fault(0);
-
-	/* Successful if we unlocked everything we wanted */
-	if (!(STM32_FLASH_PECR & (locks | STM32_FLASH_PECR_PE_LOCK)))
-		return EC_SUCCESS;
-
-	/* Otherwise relock everything and return error */
-	lock();
-	return EC_ERROR_ACCESS_DENIED;
-}
-
-/**
- * Read an option byte word.
- *
- * Option bytes are stored in pairs in 32-bit registers; the upper 16 bits is
- * the 1's compliment of the lower 16 bits.
- */
-static uint16_t read_optb(int offset)
-{
-	return REG16(STM32_OPTB_BASE + offset);
-}
-
-/**
- * Write an option byte word.
- *
- * Requires OPT_LOCK unlocked.
- */
-static void write_optb(int offset, uint16_t value)
-{
-	REG32(STM32_OPTB_BASE + offset) =
-		(uint32_t)value | ((uint32_t)(~value) << 16);
-}
-
-/**
- * Read the at-boot protection option bits.
- */
-static uint32_t read_optb_wrp(void)
-{
-	return read_optb(STM32_OPTB_WRP1L) |
-		((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16);
-}
-
-/**
- * Write the at-boot protection option bits.
- */
-static void write_optb_wrp(uint32_t value)
-{
-	write_optb(STM32_OPTB_WRP1L, (uint16_t)value);
-	write_optb(STM32_OPTB_WRP1H, value >> 16);
-}
-
-/**
- * Write data to flash.
- *
- * This function lives in internal RAM, as we cannot read flash during writing.
- * You must not call other functions from this one or declare it static.
- */
-void  __attribute__((section(".iram.text")))
-	iram_flash_write(uint32_t *addr, uint32_t *data)
-{
-	int i;
-
-	/* Wait for ready  */
-	for (i = 0; (STM32_FLASH_SR & 1) && (i < flash_timeout_loop); i++)
-		;
-
-	/* Set PROG and FPRG bits */
-	STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_FPRG;
-
-	/* Send words for the half page */
-	for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t); i++)
-		*addr++ = *data++;
-
-	/* Wait for writes to complete */
-	for (i = 0; ((STM32_FLASH_SR & 9) != 8) && (i < flash_timeout_loop);
-	     i++)
-		;
-
-	/* Disable PROG and FPRG bits */
-	STM32_FLASH_PECR &= ~(STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_FPRG);
-}
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	uint32_t *data32 = (uint32_t *)data;
-	uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	int res = EC_SUCCESS;
-	int word_mode = 0;
-	int i;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	/* Unlock program area */
-	res = unlock(STM32_FLASH_PECR_PRG_LOCK);
-	if (res)
-		goto exit_wr;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = 0xf00;
-
-	/*
-	 * If offset and size aren't on word boundaries, do word writes.  This
-	 * is slower, but since we claim to the outside world that writes must
-	 * be half-page size, the only code which hits this path is writing
-	 * pstate (which is just writing one word).
-	 */
-	if ((offset | size) & (CONFIG_FLASH_WRITE_SIZE - 1))
-		word_mode = 1;
-
-	/* Update flash timeout based on current clock speed */
-	flash_timeout_loop = FLASH_TIMEOUT_MS * (clock_get_freq() / MSEC) /
-		CYCLE_PER_FLASH_LOOP;
-
-	while (size > 0) {
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset when doing
-		 * long writing with interrupt disabled.
-		 */
-		watchdog_reload();
-
-		if (word_mode) {
-			/* Word write */
-			*address++ = *data32++;
-
-			/* Wait for writes to complete */
-			for (i = 0; ((STM32_FLASH_SR & 9) != 8) &&
-				     (i < flash_timeout_loop); i++)
-				;
-
-			size -= sizeof(uint32_t);
-		} else {
-			/* Half page write */
-			interrupt_disable();
-			iram_flash_write(address, data32);
-			interrupt_enable();
-			address += CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t);
-			data32 += CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t);
-			size -= CONFIG_FLASH_WRITE_SIZE;
-		}
-
-		if (STM32_FLASH_SR & 1) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		/*
-		 * Check for error conditions: erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR & 0xf00) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_wr;
-		}
-	}
-
-exit_wr:
-	/* Relock program lock */
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	uint32_t *address;
-	int res = EC_SUCCESS;
-
-	res = unlock(STM32_FLASH_PECR_PRG_LOCK);
-	if (res)
-		return res;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = 0xf00;
-
-	/* Set PROG and ERASE bits */
-	STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE;
-
-	for (address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	     size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-	     address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) {
-		timestamp_t deadline;
-
-		/* Do nothing if already erased */
-		if (crec_flash_is_erased((uint32_t)address -
-				    CONFIG_PROGRAM_MEMORY_BASE,
-				    CONFIG_FLASH_ERASE_SIZE))
-			continue;
-
-		/* Start erase */
-		*address = 0x00000000;
-
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset during
-		 * multi-page erase operations.
-		 */
-		watchdog_reload();
-
-		deadline.val = get_time().val + FLASH_TIMEOUT_MS * MSEC;
-		/* Wait for erase to complete */
-		while ((STM32_FLASH_SR & 1) &&
-		       (get_time().val < deadline.val)) {
-			usleep(300);
-		}
-		if (STM32_FLASH_SR & 1) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_er;
-		}
-
-		/*
-		 * Check for error conditions: erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR & 0xF00) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_er;
-		}
-	}
-
-exit_er:
-	/* Disable program and erase, and relock PECR */
-	STM32_FLASH_PECR &= ~(STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE);
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_get_protect(int block)
-{
-	/*
-	 * If the entire flash interface is locked, then all blocks are
-	 * protected until reboot.
-	 */
-	if (crec_flash_physical_get_protect_flags() & EC_FLASH_PROTECT_ALL_NOW)
-		return 1;
-
-	/* Check the active write protect status */
-	return STM32_FLASH_WRPR & BIT(block);
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	uint32_t prot;
-	uint32_t mask = (BIT(WP_BANK_COUNT) - 1) << WP_BANK_OFFSET;
-	int rv;
-
-	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	/* Read the current protection status */
-	prot = read_optb_wrp();
-
-	/* Set/clear bits */
-	if (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT)
-		prot |= mask;
-	else
-		prot &= ~mask;
-
-	if (prot == read_optb_wrp())
-		return EC_SUCCESS;  /* No bits changed */
-
-	/* Unlock option bytes */
-	rv = unlock(STM32_FLASH_PECR_OPT_LOCK);
-	if (rv)
-		return rv;
-
-	/* Update them */
-	write_optb_wrp(prot);
-
-	/* Relock */
-	lock();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_force_reload(void)
-{
-	int rv = unlock(STM32_FLASH_PECR_OPT_LOCK);
-
-	if (rv)
-		return rv;
-
-	/* Force a reboot; this should never return. */
-	STM32_FLASH_PECR = STM32_FLASH_PECR_OBL_LAUNCH;
-	while (1)
-		;
-
-	return EC_ERROR_UNKNOWN;
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	/*
-	 * Try to unlock PECR; if that fails, then all flash is protected for
-	 * the current boot.
-	 */
-	if (unlock(STM32_FLASH_PECR_PE_LOCK))
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-	lock();
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		/* Re-lock the registers if they're unlocked */
-		lock();
-
-		/* Prevent unlocking until reboot */
-		ignore_bus_fault(1);
-		STM32_FLASH_PEKEYR = 0;
-		ignore_bus_fault(0);
-
-		return EC_SUCCESS;
-	} else {
-		/* No way to protect just the RO flash until next boot */
-		return EC_ERROR_INVAL;
-	}
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	int need_reset = 0;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			/*
-			 * Pstate wants RO protected at boot, but the write
-			 * protect register wasn't set to protect it.  Force an
-			 * update to the write protect register and reboot so
-			 * it takes effect.
-			 */
-			crec_flash_protect_at_boot(EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-
-		if (prot_flags & EC_FLASH_PROTECT_ERROR_INCONSISTENT) {
-			/*
-			 * Write protect register was in an inconsistent state.
-			 * Set it back to a good state and reboot.
-			 */
-			crec_flash_protect_at_boot(prot_flags &
-					EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-	} else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW |
-				 EC_FLASH_PROTECT_ERROR_INCONSISTENT)) {
-		/*
-		 * Write protect pin unasserted but some section is
-		 * protected. Drop it and reboot.
-		 */
-		unlock(STM32_FLASH_PECR_OPT_LOCK);
-		write_optb_wrp(0);
-		lock();
-		need_reset = 1;
-	}
-
-	if (need_reset)
-		system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	return EC_SUCCESS;
-}
diff --git a/chip/stm32/gpio-f0-l.c b/chip/stm32/gpio-f0-l.c
deleted file mode 100644
index 55628cb6d4..0000000000
--- a/chip/stm32/gpio-f0-l.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * GPIO module for Chrome EC
- *
- * These functions are shared by the STM32F0 and STM32L variants.
- */
-
-#include "common.h"
-#include "gpio_chip.h"
-#include "registers.h"
-#include "util.h"
-
-static uint32_t expand_to_2bit_mask(uint32_t mask)
-{
-	uint32_t mask_out = 0;
-	while (mask) {
-		int bit = get_next_bit(&mask);
-		mask_out |= 3 << (bit * 2);
-	}
-	return mask_out;
-}
-
-int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
-{
-	uint32_t flags = 0;
-	uint32_t val = 0;
-	const uint32_t mask2 = expand_to_2bit_mask(mask);
-
-	/* Only one bit must be set. */
-	if ((mask != (mask & -mask)) || (mask == 0))
-		return 0;
-
-	/* Check output type. */
-	val = STM32_GPIO_PUPDR(port) & mask2;
-	if (val == (0x55555555 & mask2))
-		flags |= GPIO_PULL_UP;
-	if (val == (0xaaaaaaaa & mask2))
-		flags |= GPIO_PULL_DOWN;
-
-	if (STM32_GPIO_OTYPER(port) & mask)
-		flags |= GPIO_OPEN_DRAIN;
-
-	/* Check mode. */
-	val = STM32_GPIO_MODER(port) & mask2;
-	if (val == (0x55555555 & mask2))
-		flags |= GPIO_OUTPUT;
-	if (val == (0xFFFFFFFF & mask2))
-		flags |= GPIO_ANALOG;
-	if (val == (0x0 & mask2))
-		flags |= GPIO_INPUT;
-	if (val == (0xaaaaaaaa & mask2))
-		flags |= GPIO_ALTERNATE;
-
-	if (flags & GPIO_OUTPUT) {
-		if (STM32_GPIO_ODR(port) & mask)
-			flags |= GPIO_HIGH;
-		else
-			flags |= GPIO_LOW;
-	}
-
-
-	if (STM32_EXTI_RTSR & mask)
-		flags |= GPIO_INT_F_RISING;
-	if (STM32_EXTI_RTSR & mask)
-		flags |= GPIO_INT_F_RISING;
-
-	return flags;
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/* Bitmask for registers with 2 bits per GPIO pin */
-	const uint32_t mask2 = expand_to_2bit_mask(mask);
-	uint32_t val;
-
-	/* Set up pullup / pulldown */
-	val = STM32_GPIO_PUPDR(port) & ~mask2;
-	if (flags & GPIO_PULL_UP)
-		val |= 0x55555555 & mask2;	/* Pull Up = 01 */
-	else if (flags & GPIO_PULL_DOWN)
-		val |= 0xaaaaaaaa & mask2;	/* Pull Down = 10 */
-	STM32_GPIO_PUPDR(port) = val;
-
-	/*
-	 * Select open drain first, so that we don't glitch the signal when
-	 * changing the line to an output.
-	 */
-	if (flags & GPIO_OPEN_DRAIN)
-		STM32_GPIO_OTYPER(port) |= mask;
-	else
-		STM32_GPIO_OTYPER(port) &= ~mask;
-
-	val = STM32_GPIO_MODER(port) & ~mask2;
-	if (flags & GPIO_OUTPUT) {
-		/*
-		 * Set pin level first to avoid glitching.  This is harmless on
-		 * STM32L because the set/reset register isn't connected to the
-		 * output drivers until the pin is made an output.
-		 */
-		if (flags & GPIO_HIGH)
-			STM32_GPIO_BSRR(port) = mask;
-		else if (flags & GPIO_LOW)
-			STM32_GPIO_BSRR(port) = mask << 16;
-
-		/* General purpose, MODE = 01 */
-		val |= 0x55555555 & mask2;
-		STM32_GPIO_MODER(port) = val;
-
-	} else if (flags & GPIO_ANALOG) {
-		/* Analog, MODE=11 */
-		val |= 0xFFFFFFFF & mask2;
-		STM32_GPIO_MODER(port) = val;
-	} else if (flags & GPIO_INPUT) {
-		/* Input, MODE=00 */
-		STM32_GPIO_MODER(port) = val;
-	} else if (flags & GPIO_ALTERNATE) {
-		/* Alternate, MODE=10 */
-		val |= 0xaaaaaaaa & mask2;
-		STM32_GPIO_MODER(port) = val;
-	}
-
-	/* Set up interrupts if necessary */
-	ASSERT(!(flags & (GPIO_INT_F_LOW | GPIO_INT_F_HIGH)));
-	if (flags & GPIO_INT_F_RISING)
-		STM32_EXTI_RTSR |= mask;
-	if (flags & GPIO_INT_F_FALLING)
-		STM32_EXTI_FTSR |= mask;
-	/* Interrupt is enabled by gpio_enable_interrupt() */
-}
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	/* Ensure that the func parameter isn't overflowed */
-	BUILD_ASSERT((int) MODULE_COUNT <= (int) GPIO_ALT_FUNC_MAX);
-
-	int bit;
-	uint32_t half;
-	uint32_t afr;
-	uint32_t moder = STM32_GPIO_MODER(port);
-
-	if (func == GPIO_ALT_FUNC_NONE) {
-		/* Return to normal GPIO function, defaulting to input. */
-		while (mask) {
-			bit = get_next_bit(&mask);
-			moder &= ~(0x3 << (bit * 2));
-		}
-		STM32_GPIO_MODER(port) = moder;
-		return;
-	}
-
-	/* Low half of the GPIO bank */
-	half = mask & 0xff;
-	afr = STM32_GPIO_AFRL(port);
-	while (half) {
-		bit = get_next_bit(&half);
-		afr &= ~(0xf << (bit * 4));
-		afr |= func << (bit * 4);
-		moder &= ~(0x3 << (bit * 2 + 0));
-		moder |= 0x2 << (bit * 2 + 0);
-	}
-	STM32_GPIO_AFRL(port) = afr;
-
-	/* High half of the GPIO bank */
-	half = (mask >> 8) & 0xff;
-	afr = STM32_GPIO_AFRH(port);
-	while (half) {
-		bit = get_next_bit(&half);
-		afr &= ~(0xf << (bit * 4));
-		afr |= func << (bit * 4);
-		moder &= ~(0x3 << (bit * 2 + 16));
-		moder |= 0x2 << (bit * 2 + 16);
-	}
-	STM32_GPIO_AFRH(port) = afr;
-	STM32_GPIO_MODER(port) = moder;
-}
diff --git a/chip/stm32/gpio-stm32f0.c b/chip/stm32/gpio-stm32f0.c
deleted file mode 100644
index d7e7aa4391..0000000000
--- a/chip/stm32/gpio-stm32f0.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHBENR |= 0x7e0000;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0_1);
-	task_enable_irq(STM32_IRQ_EXTI2_3);
-	task_enable_irq(STM32_IRQ_EXTI4_15);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32f3.c b/chip/stm32/gpio-stm32f3.c
deleted file mode 100644
index bfc2631de8..0000000000
--- a/chip/stm32/gpio-stm32f3.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHBENR |= 0x7e0000;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32f4.c b/chip/stm32/gpio-stm32f4.c
deleted file mode 100644
index 4a4e095a71..0000000000
--- a/chip/stm32/gpio-stm32f4.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-int gpio_required_clocks(void)
-{
-	const int gpio_ports_used = (0
-#		define GPIO(name, pin, flags) pin
-#		define GPIO_INT(name, pin, flags, signal) pin
-#		define ALTERNATE(pinmask, function, module, flagz) pinmask
-#		define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT ## port
-#		define PIN_MASK(port, mask) PIN(port, 0)
-#		include "gpio.wrap"
-	);
-
-	/*
-	 * If no ports are in use, then system_is_reboot_warm
-	 * may not be valid.
-	 */
-	ASSERT(gpio_ports_used);
-
-	return gpio_ports_used;
-}
-
-void gpio_enable_clocks(void)
-{
-	/* Enable only ports that are referenced in the gpio.inc */
-	STM32_RCC_AHB1ENR |= gpio_required_clocks();
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32g4.c b/chip/stm32/gpio-stm32g4.c
deleted file mode 100644
index 55b2c11e7b..0000000000
--- a/chip/stm32/gpio-stm32g4.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-int gpio_required_clocks(void)
-{
-	const int gpio_ports_used = (0
-#		define GPIO(name, pin, flags) pin
-#		define GPIO_INT(name, pin, flags, signal) pin
-#		define ALTERNATE(pinmask, function, module, flagz) pinmask
-#		define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT ## port
-#		define PIN_MASK(port, mask) PIN(port, 0)
-#		include "gpio.wrap"
-	);
-
-	/*
-	 * If no ports are in use, then system_is_reboot_warm
-	 * may not be valid.
-	 */
-	ASSERT(gpio_ports_used);
-
-	return gpio_ports_used;
-}
-
-void gpio_enable_clocks(void)
-{
-	/* Enable only ports that are referenced in the gpio.inc */
-	STM32_RCC_AHB2ENR |= gpio_required_clocks();
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32h7.c b/chip/stm32/gpio-stm32h7.c
deleted file mode 100644
index a2fb97225d..0000000000
--- a/chip/stm32/gpio-stm32h7.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/* Enable all GPIOs clocks */
-	STM32_RCC_AHB4ENR |= STM32_RCC_AHB4ENR_GPIOMASK;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32l.c b/chip/stm32/gpio-stm32l.c
deleted file mode 100644
index 52c424eea0..0000000000
--- a/chip/stm32/gpio-stm32l.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHBENR |= 0x3f;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32l4.c b/chip/stm32/gpio-stm32l4.c
deleted file mode 100644
index b5c4940454..0000000000
--- a/chip/stm32/gpio-stm32l4.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_GPIOMASK;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32l5.c b/chip/stm32/gpio-stm32l5.c
deleted file mode 100644
index 43a7db05da..0000000000
--- a/chip/stm32/gpio-stm32l5.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_GPIOMASK;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI5);
-	task_enable_irq(STM32_IRQ_EXTI6);
-	task_enable_irq(STM32_IRQ_EXTI7);
-	task_enable_irq(STM32_IRQ_EXTI8);
-	task_enable_irq(STM32_IRQ_EXTI9);
-	task_enable_irq(STM32_IRQ_EXTI10);
-	task_enable_irq(STM32_IRQ_EXTI11);
-	task_enable_irq(STM32_IRQ_EXTI12);
-	task_enable_irq(STM32_IRQ_EXTI13);
-	task_enable_irq(STM32_IRQ_EXTI14);
-	task_enable_irq(STM32_IRQ_EXTI15);
-
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI6, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI7, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI8, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI10, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI11, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI12, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI13, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI14, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c
deleted file mode 100644
index ccfd3399e2..0000000000
--- a/chip/stm32/gpio.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-/* For each EXTI bit, record which GPIO entry is using it */
-static uint8_t exti_events[16];
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	const struct unused_pin_info *u = unused_pin_list;
-	int is_warm = system_is_reboot_warm();
-	int i;
-
-	/* Required to configure external IRQ lines (SYSCFG_EXTICRn) */
-#ifdef CHIP_FAMILY_STM32H7
-	STM32_RCC_APB4ENR |= STM32_RCC_SYSCFGEN;
-#else
-	STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN;
-#endif
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/* Disable all GPIO EXTINTs (EXTINT0..15) left enabled after sysjump. */
-	STM32_EXTI_IMR &= ~0xFFFF;
-
-	if (!is_warm)
-		gpio_enable_clocks();
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-
-	/* Configure optional unused pins for low power optimization. */
-	for (i = 0; i < unused_pin_count; i++, u++) {
-		/*
-		 * Configure unused pins as ANALOG INPUT to save power.
-		 * For more info, please see
-		 * "USING STM32F4 MCU POWER MODES WITH BEST DYNAMIC EFFICIENCY"
-		 * ("AN4365") section 1.2.6 and section 7.3.12 of the STM32F412
-		 * reference manual.
-		 */
-		if (IS_ENABLED(CHIP_FAMILY_STM32F4))
-			gpio_set_flags_by_mask(u->port, u->mask, GPIO_ANALOG);
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return !!(STM32_GPIO_IDR(gpio_list[signal].port) &
-		  gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	STM32_GPIO_BSRR(gpio_list[signal].port) =
-			gpio_list[signal].mask << (value ? 0 : 16);
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	const struct gpio_info *g_old = gpio_list;
-
-	uint32_t bit, group, shift, bank;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	bit = GPIO_MASK_TO_NUM(g->mask);
-
-	g_old += exti_events[bit];
-
-	if ((exti_events[bit]) && (exti_events[bit] != signal)) {
-		CPRINTS("Overriding %s with %s on EXTI%d",
-			g_old->name, g->name, bit);
-	}
-	exti_events[bit] = signal;
-
-	group = bit / 4;
-	shift = (bit % 4) * 4;
-	bank = (g->port - STM32_GPIOA_BASE) / 0x400;
-
-	STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) &
-				      ~(0xF << shift)) | (bank << shift);
-	STM32_EXTI_IMR |= g->mask;
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	uint32_t bit;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	STM32_EXTI_IMR &= ~g->mask;
-
-	bit = GPIO_MASK_TO_NUM(g->mask);
-
-	exti_events[bit] = 0;
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Write 1 to clear interrupt */
-	STM32_EXTI_PR = g->mask;
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Interrupt handler */
-
-void __keep gpio_interrupt(void)
-{
-	int bit;
-	/* process only GPIO EXTINTs (EXTINT0..15) not other EXTINTs */
-	uint32_t pending = STM32_EXTI_PR & 0xFFFF;
-	uint8_t signal;
-
-	/* Write 1 to clear interrupt */
-	STM32_EXTI_PR = pending;
-
-	while (pending) {
-		bit = get_next_bit(&pending);
-		signal = exti_events[bit];
-		if (signal < GPIO_IH_COUNT)
-			gpio_irq_handlers[signal](signal);
-	}
-}
-#ifdef CHIP_FAMILY_STM32F0
-DECLARE_IRQ(STM32_IRQ_EXTI0_1, gpio_interrupt, STM32_IRQ_EXT0_1_PRIORITY);
-DECLARE_IRQ(STM32_IRQ_EXTI2_3, gpio_interrupt, STM32_IRQ_EXT2_3_PRIORITY);
-DECLARE_IRQ(STM32_IRQ_EXTI4_15, gpio_interrupt, STM32_IRQ_EXTI4_15_PRIORITY);
-#endif
diff --git a/chip/stm32/gpio_chip.h b/chip/stm32/gpio_chip.h
deleted file mode 100644
index a5b642fb05..0000000000
--- a/chip/stm32/gpio_chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CHIP_STM32_GPIO_CHIP_H
-#define __CROS_EC_CHIP_STM32_GPIO_CHIP_H
-
-#include "include/gpio.h"
-
-/**
- * Enable GPIO peripheral clocks.
- */
-void gpio_enable_clocks(void);
-
-/**
- * Return gpio port clocks that are necessary to support
- * the pins in gpio.inc.
- */
-int gpio_required_clocks(void);
-
-#endif  /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */
diff --git a/chip/stm32/host_command_common.c b/chip/stm32/host_command_common.c
deleted file mode 100644
index b39a298c64..0000000000
--- a/chip/stm32/host_command_common.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "fpsensor_detect.h"
-#include "host_command.h"
-#include "spi.h"
-#include "usart_host_command.h"
-
-#ifndef CONFIG_I2C_PERIPHERAL
-
-/* Store current transport type */
-static enum fp_transport_type curr_transport_type = FP_TRANSPORT_TYPE_UNKNOWN;
-
-/*
- * Get protocol information
- */
-static enum ec_status host_command_protocol_info(struct host_cmd_handler_args
-						 *args)
-{
-	enum ec_status ret_status = EC_RES_INVALID_COMMAND;
-
-	/*
-	 * Read transport type from TRANSPORT_SEL bootstrap pin the first
-	 * time this function is called.
-	 */
-	if (IS_ENABLED(CONFIG_FINGERPRINT_MCU) &&
-	    (curr_transport_type == FP_TRANSPORT_TYPE_UNKNOWN))
-		curr_transport_type = get_fp_transport_type();
-
-	if (IS_ENABLED(CONFIG_USART_HOST_COMMAND) &&
-	    curr_transport_type == FP_TRANSPORT_TYPE_UART)
-		ret_status = usart_get_protocol_info(args);
-	else if (IS_ENABLED(CONFIG_SPI) &&
-		 curr_transport_type == FP_TRANSPORT_TYPE_SPI)
-		ret_status = spi_get_protocol_info(args);
-
-	return ret_status;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     host_command_protocol_info,
-		     EC_VER_MASK(0));
-
-#endif /* CONFIG_I2C_PERIPHERAL */
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c
deleted file mode 100644
index 953110017f..0000000000
--- a/chip/stm32/hwtimer.c
+++ /dev/null
@@ -1,454 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-/*
- * Trigger select mapping for slave timer from master timer.  This is
- * unfortunately not very straightforward; there's no tidy way to do this
- * algorithmically.  To avoid burning memory for a lookup table, use macros to
- * compute the offset.  This also has the benefit that compilation will fail if
- * an unsupported master/slave pairing is used.
- */
-#ifdef CHIP_FAMILY_STM32F0
-/*
- * Slave        Master
- *     1    15  2  3 17
- *     2     1 15  3 14
- *     3     1  2 15 14
- *    15     2  3 16 17
- *     --------------------
- *     ts =  0  1  2  3
- */
-#define STM32_TIM_TS_SLAVE_1_MASTER_15  0
-#define STM32_TIM_TS_SLAVE_1_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_1_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_1_MASTER_17  3
-#define STM32_TIM_TS_SLAVE_2_MASTER_1   0
-#define STM32_TIM_TS_SLAVE_2_MASTER_15  1
-#define STM32_TIM_TS_SLAVE_2_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_2_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_3_MASTER_1   0
-#define STM32_TIM_TS_SLAVE_3_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_3_MASTER_15  2
-#define STM32_TIM_TS_SLAVE_3_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_15_MASTER_2  0
-#define STM32_TIM_TS_SLAVE_15_MASTER_3  1
-#define STM32_TIM_TS_SLAVE_15_MASTER_16 2
-#define STM32_TIM_TS_SLAVE_15_MASTER_17 3
-#elif defined(CHIP_FAMILY_STM32F3)
-/*
- * Slave        Master
- *     2    19 15  3 14
- *     3    19  2  5 14
- *     4    19  2  3 15
- *     5     2  3  4 15
- *    12     4  5 13 14
- *    19     2  3 15 16
- *    ---------------------
- *     ts =  0  1  2  3
- */
-#define STM32_TIM_TS_SLAVE_2_MASTER_19  0
-#define STM32_TIM_TS_SLAVE_2_MASTER_15  1
-#define STM32_TIM_TS_SLAVE_2_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_2_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_3_MASTER_19  0
-#define STM32_TIM_TS_SLAVE_3_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_3_MASTER_5   2
-#define STM32_TIM_TS_SLAVE_3_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_4_MASTER_19  0
-#define STM32_TIM_TS_SLAVE_4_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_4_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_4_MASTER_15  3
-#define STM32_TIM_TS_SLAVE_5_MASTER_2   0
-#define STM32_TIM_TS_SLAVE_5_MASTER_3   1
-#define STM32_TIM_TS_SLAVE_5_MASTER_4   2
-#define STM32_TIM_TS_SLAVE_5_MASTER_15  3
-#define STM32_TIM_TS_SLAVE_12_MASTER_4  0
-#define STM32_TIM_TS_SLAVE_12_MASTER_5  1
-#define STM32_TIM_TS_SLAVE_12_MASTER_13 2
-#define STM32_TIM_TS_SLAVE_12_MASTER_14 3
-#define STM32_TIM_TS_SLAVE_19_MASTER_2  0
-#define STM32_TIM_TS_SLAVE_19_MASTER_3  1
-#define STM32_TIM_TS_SLAVE_19_MASTER_15 2
-#define STM32_TIM_TS_SLAVE_19_MASTER_16 3
-#else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */
-/*
- * Slave        Master
- *     1    15  2  3  4  (STM32F100 only)
- *     2     9 10  3  4
- *     3     9  2 11  4
- *     4    10  2  3  9
- *     9     2  3 10 11  (STM32L15x only)
- *     --------------------
- *     ts =  0  1  2  3
- */
-#define STM32_TIM_TS_SLAVE_1_MASTER_15 0
-#define STM32_TIM_TS_SLAVE_1_MASTER_2  1
-#define STM32_TIM_TS_SLAVE_1_MASTER_3  2
-#define STM32_TIM_TS_SLAVE_1_MASTER_4  3
-#define STM32_TIM_TS_SLAVE_2_MASTER_9  0
-#define STM32_TIM_TS_SLAVE_2_MASTER_10 1
-#define STM32_TIM_TS_SLAVE_2_MASTER_3  2
-#define STM32_TIM_TS_SLAVE_2_MASTER_4  3
-#define STM32_TIM_TS_SLAVE_3_MASTER_9  0
-#define STM32_TIM_TS_SLAVE_3_MASTER_2  1
-#define STM32_TIM_TS_SLAVE_3_MASTER_11 2
-#define STM32_TIM_TS_SLAVE_3_MASTER_4  3
-#define STM32_TIM_TS_SLAVE_4_MASTER_10 0
-#define STM32_TIM_TS_SLAVE_4_MASTER_2  1
-#define STM32_TIM_TS_SLAVE_4_MASTER_3  2
-#define STM32_TIM_TS_SLAVE_4_MASTER_9  3
-#define STM32_TIM_TS_SLAVE_9_MASTER_2  0
-#define STM32_TIM_TS_SLAVE_9_MASTER_3  1
-#define STM32_TIM_TS_SLAVE_9_MASTER_10 2
-#define STM32_TIM_TS_SLAVE_9_MASTER_11 3
-#endif /* !CHIP_FAMILY_STM32F0 */
-#define TSMAP(slave, master) \
-	CONCAT4(STM32_TIM_TS_SLAVE_, slave, _MASTER_, master)
-
-/*
- * Timers are defined per board.  This gives us flexibility to work around
- * timers which are dedicated to board-specific PWM sources.
- */
-#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n)
-#define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB)
-#define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB)
-#define IRQ_WD  IRQ_TIM(TIM_WATCHDOG)
-
-/* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */
-#if defined TIM_WATCHDOG && (TIM_WATCHDOG == 1)
-#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_BRK_UP_TRG
-#else /* !(TIM_WATCHDOG == 1) */
-#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_CC
-#endif /* !(TIM_WATCHDOG == 1) */
-
-#define TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE)
-#define TIM_WD_BASE TIM_BASE(TIM_WATCHDOG)
-
-static uint32_t last_deadline;
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	last_deadline = deadline;
-
-	if ((deadline >> 16) > STM32_TIM_CNT(TIM_CLOCK_MSB)) {
-		/* first set a match on the MSB */
-		STM32_TIM_CCR1(TIM_CLOCK_MSB) = deadline >> 16;
-		/* disable LSB match */
-		STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2;
-		/* Clear the match flags */
-		STM32_TIM_SR(TIM_CLOCK_MSB) = ~2;
-		STM32_TIM_SR(TIM_CLOCK_LSB) = ~2;
-		/* Set the match interrupt */
-		STM32_TIM_DIER(TIM_CLOCK_MSB) |= 2;
-	}
-	/*
-	 * In the unlikely case where the MSB has increased and matched
-	 * the deadline MSB before we set the match interrupt, as the STM
-	 * hardware timer won't trigger an interrupt, we fall back to the
-	 * following LSB event code to set another interrupt.
-	 */
-	if ((deadline >> 16) == STM32_TIM_CNT(TIM_CLOCK_MSB)) {
-		/* we can set a match on the LSB only */
-		STM32_TIM_CCR1(TIM_CLOCK_LSB) = deadline & 0xffff;
-		/* disable MSB match */
-		STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2;
-		/* Clear the match flags */
-		STM32_TIM_SR(TIM_CLOCK_MSB) = ~2;
-		STM32_TIM_SR(TIM_CLOCK_LSB) = ~2;
-		/* Set the match interrupt */
-		STM32_TIM_DIER(TIM_CLOCK_LSB) |= 2;
-	}
-	/*
-	 * If the LSB deadline is already in the past and won't trigger an
-	 * interrupt, the common code in process_timers will deal with the
-	 * expired timer and automatically set the next deadline, we don't need
-	 * to do anything here.
-	 */
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* Disable the match interrupts */
-	STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2;
-	STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2;
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	uint32_t hi;
-	uint32_t lo;
-
-	/* Ensure the two half-words are coherent */
-	do {
-		hi = STM32_TIM_CNT(TIM_CLOCK_MSB);
-		lo = STM32_TIM_CNT(TIM_CLOCK_LSB);
-	} while (hi != STM32_TIM_CNT(TIM_CLOCK_MSB));
-
-	return (hi << 16) | lo;
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	STM32_TIM_CNT(TIM_CLOCK_MSB) = ts >> 16;
-	STM32_TIM_CNT(TIM_CLOCK_LSB) = ts & 0xffff;
-}
-
-void __hw_clock_source_irq(void)
-{
-	uint32_t stat_tim_msb = STM32_TIM_SR(TIM_CLOCK_MSB);
-
-	/* Clear status */
-	STM32_TIM_SR(TIM_CLOCK_LSB) = 0;
-	STM32_TIM_SR(TIM_CLOCK_MSB) = 0;
-
-	/*
-	 * Find expired timers and set the new timer deadline
-	 * signal overflow if the 16-bit MSB counter has overflowed.
-	 */
-	process_timers(stat_tim_msb & 0x01);
-}
-DECLARE_IRQ(IRQ_MSB, __hw_clock_source_irq, 1);
-DECLARE_IRQ(IRQ_LSB, __hw_clock_source_irq, 1);
-
-void __hw_timer_enable_clock(int n, int enable)
-{
-	volatile uint32_t *reg;
-	uint32_t mask = 0;
-
-	/*
-	 * Mapping of timers to reg/mask is split into a few different ranges,
-	 * some specific to individual chips.
-	 */
-#if defined(CHIP_FAMILY_STM32F0)
-	if (n == 1) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM1;
-	}
-#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4)
-	if (n >= 9 && n <= 11) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM9 << (n - 9);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0)
-	if (n >= 15 && n <= 17) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM15 << (n - 15);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-	if (n == 14) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM14;
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F3)
-	if (n == 12 || n == 13) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM12 << (n - 12);
-	}
-	if (n == 18) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM18;
-	}
-	if (n == 19) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM19;
-	}
-#endif
-
-	if (n >= 2 && n <= 7) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM2 << (n - 2);
-	}
-
-	if (!mask)
-		return;
-
-	if (enable)
-		*reg |= mask;
-	else
-		*reg &= ~mask;
-}
-
-static void update_prescaler(void)
-{
-	/*
-	 * Pre-scaler value :
-	 * TIM_CLOCK_LSB is counting microseconds;
-	 * TIM_CLOCK_MSB is counting every TIM_CLOCK_LSB overflow.
-	 *
-	 * This will take effect at the next update event (when the current
-	 * prescaler counter ticks down, or if forced via EGR).
-	 */
-	STM32_TIM_PSC(TIM_CLOCK_MSB) = 0;
-	STM32_TIM_PSC(TIM_CLOCK_LSB) = (clock_get_timer_freq() / SECOND) - 1;
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * we use 2 chained 16-bit counters to emulate a 32-bit one :
-	 * TIM_CLOCK_MSB is the MSB (Slave)
-	 * TIM_CLOCK_LSB is the LSB (Master)
-	 */
-
-	/* Enable TIM_CLOCK_MSB and TIM_CLOCK_LSB clocks */
-	__hw_timer_enable_clock(TIM_CLOCK_MSB, 1);
-	__hw_timer_enable_clock(TIM_CLOCK_LSB, 1);
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Upcounter, counter disabled, update event only
-	 * on overflow.
-	 */
-	STM32_TIM_CR1(TIM_CLOCK_MSB) = 0x0004;
-	STM32_TIM_CR1(TIM_CLOCK_LSB) = 0x0004;
-	/*
-	 * TIM_CLOCK_LSB (master mode) generates a periodic trigger signal on
-	 * each UEV
-	 */
-	STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000;
-	STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020;
-
-	STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 |
-		(TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4);
-	STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000;
-
-	/* Auto-reload value : 16-bit free-running counters */
-	STM32_TIM_ARR(TIM_CLOCK_MSB) = 0xffff;
-	STM32_TIM_ARR(TIM_CLOCK_LSB) = 0xffff;
-
-	/* Update prescaler */
-	update_prescaler();
-
-	/* Reload the pre-scaler */
-	STM32_TIM_EGR(TIM_CLOCK_MSB) = 0x0001;
-	STM32_TIM_EGR(TIM_CLOCK_LSB) = 0x0001;
-
-	/* Set up the overflow interrupt on TIM_CLOCK_MSB */
-	STM32_TIM_DIER(TIM_CLOCK_MSB) = 0x0001;
-	STM32_TIM_DIER(TIM_CLOCK_LSB) = 0x0000;
-
-	/* Start counting */
-	STM32_TIM_CR1(TIM_CLOCK_MSB) |= 1;
-	STM32_TIM_CR1(TIM_CLOCK_LSB) |= 1;
-
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_MSB);
-	task_enable_irq(IRQ_LSB);
-
-	return IRQ_LSB;
-}
-
-#ifdef CONFIG_WATCHDOG_HELP
-
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
-
-	/* clear status */
-	timer->sr = 0;
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked));
-void IRQ_HANDLER(IRQ_WD)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0,pc}\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD)
-	__attribute__((section(".rodata.irqprio")))
-		= {IRQ_WD, 0}; /* put the watchdog at the highest
-					    priority */
-
-void hwtimer_setup_watchdog(void)
-{
-	struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
-
-	/* Enable clock */
-	__hw_timer_enable_clock(TIM_WATCHDOG, 1);
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Down counter, counter disabled, update
-	 * event only on overflow.
-	 */
-	timer->cr1 = 0x0014 | BIT(7);
-
-	/* TIM (slave mode) uses TIM_CLOCK_LSB as internal trigger */
-	timer->smcr = 0x0007 | (TSMAP(TIM_WATCHDOG, TIM_CLOCK_LSB) << 4);
-
-	/*
-	 * The auto-reload value is based on the period between rollovers for
-	 * TIM_CLOCK_LSB. Since TIM_CLOCK_LSB runs at 1MHz, it will overflow
-	 * in 65.536ms. We divide our required watchdog period by this amount
-	 * to obtain the number of times TIM_CLOCK_LSB can overflow before we
-	 * generate an interrupt.
-	 */
-	timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / BIT(16);
-
-	/* count on every TIM_CLOCK_LSB overflow */
-	timer->psc = 0;
-
-	/* Reload the pre-scaler from arr when it goes below zero */
-	timer->egr = 0x0000;
-
-	/* setup the overflow interrupt */
-	timer->dier = 0x0001;
-
-	/* Start counting */
-	timer->cr1 |= 1;
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_WD);
-}
-
-void hwtimer_reset_watchdog(void)
-{
-	struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
-
-	timer->cnt = timer->arr;
-}
-
-#endif  /* defined(CONFIG_WATCHDOG_HELP) */
diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c
deleted file mode 100644
index 963fa44e51..0000000000
--- a/chip/stm32/hwtimer32.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware 32-bit timer driver */
-
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n)
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	/* set the match on the deadline */
-	STM32_TIM32_CCR1(TIM_CLOCK32) = deadline;
-	/* Clear the match flags */
-	STM32_TIM_SR(TIM_CLOCK32) = ~2;
-	/* Set the match interrupt */
-	STM32_TIM_DIER(TIM_CLOCK32) |= 2;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return STM32_TIM32_CCR1(TIM_CLOCK32);
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* Disable the match interrupts */
-	STM32_TIM_DIER(TIM_CLOCK32) &= ~2;
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return STM32_TIM32_CNT(TIM_CLOCK32);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	STM32_TIM32_CNT(TIM_CLOCK32) = ts;
-}
-
-void __hw_clock_source_irq(void)
-{
-	uint32_t stat_tim = STM32_TIM_SR(TIM_CLOCK32);
-
-	/* Clear status */
-	STM32_TIM_SR(TIM_CLOCK32) = 0;
-
-	/*
-	 * Find expired timers and set the new timer deadline
-	 * signal overflow if the update interrupt flag is set.
-	 */
-	process_timers(stat_tim & 0x01);
-}
-DECLARE_IRQ(IRQ_TIM(TIM_CLOCK32), __hw_clock_source_irq, 1);
-
-void __hw_timer_enable_clock(int n, int enable)
-{
-	volatile uint32_t *reg;
-	uint32_t mask = 0;
-
-	/*
-	 * Mapping of timers to reg/mask is split into a few different ranges,
-	 * some specific to individual chips.
-	 */
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7)
-	if (n == 1) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM1;
-	}
-#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4)
-	if (n >= 9 && n <= 11) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM9 << (n - 9);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7)
-	if (n >= 15 && n <= 17) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM15 << (n - 15);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-defined(CHIP_FAMILY_STM32H7)
-	if (n == 14) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM14;
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32H7)
-	if (n == 12 || n == 13) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM12 << (n - 12);
-	}
-#endif
-#if defined(CHIP_FAMILY_STM32F3)
-	if (n == 18) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM18;
-	}
-	if (n == 19) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM19;
-	}
-#endif
-#if defined(CHIP_FAMILY_STM32G4)
-	reg = &STM32_RCC_APB2ENR;
-	if (n == 1)
-		mask = STM32_RCC_APB2ENR_TIM1;
-	else if (n == 8)
-		mask = STM32_RCC_APB2ENR_TIM8;
-	else if (n == 20)
-		mask = STM32_RCC_APB2ENR_TIM20;
-	else if (n >= 15 && n <= 17)
-		mask = STM32_RCC_APB2ENR_TIM15 << (n - 15);
-#endif
-#if defined(CHIP_FAMILY_STM32L4)
-	if (n >= 2 && n <= 7) {
-		reg = &STM32_RCC_APB1ENR1;
-		mask = STM32_RCC_PB1_TIM2 << (n - 2);
-	} else if (n == 1 || n == 15 || n == 16) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = (n == 1)	 ? STM32_RCC_APB2ENR_TIM1EN :
-		       (n == 15) ? STM32_RCC_APB2ENR_TIM15EN :
-					 STM32_RCC_APB2ENR_TIM16EN;
-	}
-#else
-	if (n >= 2 && n <= 7) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM2 << (n - 2);
-	}
-#endif
-
-	if (!mask)
-		return;
-
-	if (enable)
-		*reg |= mask;
-	else
-		*reg &= ~mask;
-}
-
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32H7)
-/* for families using a variable clock feeding the timer */
-static void update_prescaler(void)
-{
-	uint32_t t;
-	/*
-	 * Pre-scaler value :
-	 * the timer is incrementing every microsecond
-	 */
-	STM32_TIM_PSC(TIM_CLOCK32) = (clock_get_timer_freq() / SECOND) - 1;
-	/*
-	 * Forcing reloading the pre-scaler,
-	 * but try to maintain a sensible time-keeping while triggering
-	 * the update event.
-	 */
-	interrupt_disable();
-	/* Ignore the next update */
-	STM32_TIM_DIER(TIM_CLOCK32) &= ~0x0001;
-	/*
-	 * prepare to reload the counter with the current value
-	 * to avoid rolling backward the microsecond counter.
-	 */
-	t = STM32_TIM32_CNT(TIM_CLOCK32) + 1;
-	/* issue an update event, reloads the pre-scaler and the counter */
-	STM32_TIM_EGR(TIM_CLOCK32) = 0x0001;
-	/* clear the 'spurious' update unless we were going to roll-over */
-	if (t)
-		STM32_TIM_SR(TIM_CLOCK32) = ~1;
-	/* restore a sensible time value */
-	STM32_TIM32_CNT(TIM_CLOCK32) = t;
-	/* restore roll-over events */
-	STM32_TIM_DIER(TIM_CLOCK32) |= 0x0001;
-	interrupt_enable();
-
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Watchdog timer runs at 1KHz */
-	STM32_TIM_PSC(TIM_WATCHDOG) =
-		(clock_get_timer_freq()  / SECOND * MSEC)- 1;
-#endif  /* CONFIG_WATCHDOG_HELP */
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-#endif /* CHIP_FAMILY_STM32L  || CHIP_FAMILY_STM32L4 || */
-	/*  CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/* Enable TIM peripheral block clocks */
-	__hw_timer_enable_clock(TIM_CLOCK32, 1);
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Upcounter, counter disabled, update event only
-	 * on overflow.
-	 */
-	STM32_TIM_CR1(TIM_CLOCK32) = 0x0004;
-	/* No special configuration */
-	STM32_TIM_CR2(TIM_CLOCK32) = 0x0000;
-	STM32_TIM_SMCR(TIM_CLOCK32) = 0x0000;
-
-	/* Auto-reload value : 32-bit free-running counter */
-	STM32_TIM32_ARR(TIM_CLOCK32) = 0xffffffff;
-
-	/* Update prescaler to increment every microsecond */
-	STM32_TIM_PSC(TIM_CLOCK32) = (clock_get_timer_freq() / SECOND) - 1;
-
-	/* Reload the pre-scaler */
-	STM32_TIM_EGR(TIM_CLOCK32) = 0x0001;
-
-	/* Set up the overflow interrupt */
-	STM32_TIM_DIER(TIM_CLOCK32) = 0x0001;
-
-	/* Start counting */
-	STM32_TIM_CR1(TIM_CLOCK32) |= 1;
-
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_TIM(TIM_CLOCK32));
-
-	return IRQ_TIM(TIM_CLOCK32);
-}
-
-#ifdef CONFIG_WATCHDOG_HELP
-
-#define IRQ_WD IRQ_TIM(TIM_WATCHDOG)
-
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	/* clear status */
-	STM32_TIM_SR(TIM_WATCHDOG) = 0;
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked));
-void IRQ_HANDLER(IRQ_WD)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0,pc}\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD)
-	__attribute__((section(".rodata.irqprio")))
-		= {IRQ_WD, 0}; /* put the watchdog at the highest
-					    priority */
-
-void hwtimer_setup_watchdog(void)
-{
-	int freq;
-
-	/* Enable clock */
-	__hw_timer_enable_clock(TIM_WATCHDOG, 1);
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Up counter, counter disabled, update
-	 * event only on overflow.
-	 */
-	STM32_TIM_CR1(TIM_WATCHDOG) = 0x0004;
-	/* No special configuration */
-	STM32_TIM_CR2(TIM_WATCHDOG) = 0x0000;
-	STM32_TIM_SMCR(TIM_WATCHDOG) = 0x0000;
-
-	/*
-	 * all timers has 16-bit prescale.
-	 * For clock freq > 64MHz, 16bit prescale cannot meet 1KHz.
-	 * set prescale as 10KHz and 10 times arr value instead.
-	 * For clock freq < 64MHz, timer runs at 1KHz.
-	 */
-	freq = clock_get_timer_freq();
-
-	if (freq <= 64000000 || !IS_ENABLED(CHIP_FAMILY_STM32L4)) {
-		/* AUto-reload value */
-		STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS;
-
-		/* Update prescaler: watchdog timer runs at 1KHz */
-		STM32_TIM_PSC(TIM_WATCHDOG) =
-			(freq / SECOND * MSEC) - 1;
-	}
-#ifdef CHIP_FAMILY_STM32L4
-	else {
-		/* 10 times ARR value with 10KHz timer */
-		STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS * 10;
-
-		/* Update prescaler: watchdog timer runs at 10KHz */
-		STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND / 10 * MSEC) - 1;
-	}
-#endif
-	/* Reload the pre-scaler */
-	STM32_TIM_EGR(TIM_WATCHDOG) = 0x0001;
-
-	/* setup the overflow interrupt */
-	STM32_TIM_DIER(TIM_WATCHDOG) = 0x0001;
-	STM32_TIM_SR(TIM_WATCHDOG) = 0;
-
-	/* Start counting */
-	STM32_TIM_CR1(TIM_WATCHDOG) |= 1;
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_WD);
-}
-
-void hwtimer_reset_watchdog(void)
-{
-	STM32_TIM_CNT(TIM_WATCHDOG) = 0x0000;
-}
-
-#endif  /* CONFIG_WATCHDOG_HELP */
diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c
deleted file mode 100644
index cdf5421efc..0000000000
--- a/chip/stm32/i2c-stm32f0.c
+++ /dev/null
@@ -1,653 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "i2c_private.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd_tcpc.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_CONTROLLER	(10 * MSEC)
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-#if (I2C_PORT_EC == STM32_I2C1_PORT)
-#define IRQ_PERIPHERAL STM32_IRQ_I2C1
-#else
-#define IRQ_PERIPHERAL STM32_IRQ_I2C2
-#endif
-#endif
-
-
-/* I2C port state data */
-struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_CONTROLLER;
-}
-
-/* timingr register values for supported input clks / i2c clk rates */
-static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
-	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
-};
-
-/**
- * Wait for ISR register to contain the specified mask.
- *
- * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_isr(int port, int mask)
-{
-	uint32_t start = __hw_clock_source_read();
-	uint32_t delta = 0;
-
-	do {
-		int isr = STM32_I2C_ISR(port);
-
-		/* Check for errors */
-		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			STM32_I2C_ISR_NACK))
-			return EC_ERROR_UNKNOWN;
-
-		/* Check for desired mask */
-		if ((isr & mask) == mask)
-			return EC_SUCCESS;
-
-		delta = __hw_clock_source_read() - start;
-
-		/**
-		 * Depending on the bus speed, busy loop for a while before
-		 * sleeping and letting other things run.
-		 */
-		if (delta >= busyloop_us[pdata[port].freq])
-			usleep(100);
-	} while (delta < pdata[port].timeout_us);
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/* Supported i2c input clocks */
-enum stm32_i2c_clk_src {
-	I2C_CLK_SRC_48MHZ = 0,
-	I2C_CLK_SRC_8MHZ = 1,
-	I2C_CLK_SRC_COUNT,
-};
-
-/* timingr register values for supported input clks / i2c clk rates */
-static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
-	[I2C_CLK_SRC_48MHZ] = {
-		[I2C_FREQ_1000KHZ] = 0x50100103,
-		[I2C_FREQ_400KHZ] = 0x50330609,
-		[I2C_FREQ_100KHZ] = 0xB0421214,
-	},
-	[I2C_CLK_SRC_8MHZ] = {
-		[I2C_FREQ_1000KHZ] = 0x00100306,
-		[I2C_FREQ_400KHZ] = 0x00310309,
-		[I2C_FREQ_100KHZ] = 0x10420f13,
-	},
-};
-
-int chip_i2c_set_freq(int port, enum i2c_freq freq)
-{
-	enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ;
-
-#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
-	defined(CONFIG_LOW_POWER_IDLE) && \
-	(I2C_PORT_EC == STM32_I2C1_PORT)
-	if (port == STM32_I2C1_PORT) {
-		/*
-		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
-		 * from STOP mode since HSI is only clock running immediately
-		 * upon exit from STOP mode.
-		 */
-		src = I2C_CLK_SRC_8MHZ;
-	}
-#endif
-
-	/* Disable port */
-	STM32_I2C_CR1(port) = 0;
-	STM32_I2C_CR2(port) = 0;
-	/* Set clock frequency */
-	STM32_I2C_TIMINGR(port) = timingr_regs[src][freq];
-	/* Enable port */
-	STM32_I2C_CR1(port) = STM32_I2C_CR1_PE;
-
-	pdata[port].freq = freq;
-
-	return EC_SUCCESS;
-}
-
-enum i2c_freq chip_i2c_get_freq(int port)
-{
-	return pdata[port].freq;
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static int i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	int ret = EC_SUCCESS;
-	enum i2c_freq freq;
-
-	/* Enable clocks to I2C modules if necessary */
-	if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
-		STM32_RCC_APB1ENR |= 1 << (21 + port);
-
-	if (port == STM32_I2C1_PORT) {
-#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
-	defined(CONFIG_LOW_POWER_IDLE) && \
-	(I2C_PORT_EC == STM32_I2C1_PORT)
-		/*
-		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
-		 * from STOP mode since HSI is only clock running immediately
-		 * upon exit from STOP mode.
-		 */
-		STM32_RCC_CFGR3 &= ~0x10;
-#else
-		/* Use SYSCLK for i2c clock. */
-		STM32_RCC_CFGR3 |= 0x10;
-#endif
-	}
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Set clock frequency */
-	switch (p->kbps) {
-	case 1000:
-		freq = I2C_FREQ_1000KHZ;
-		break;
-	case 400:
-		freq = I2C_FREQ_400KHZ;
-		break;
-	case 100:
-		freq = I2C_FREQ_100KHZ;
-		break;
-	default: /* unknown speed, defaults to 100kBps */
-		CPRINTS("I2C bad speed %d kBps", p->kbps);
-		freq = I2C_FREQ_100KHZ;
-		ret = EC_ERROR_INVAL;
-	}
-
-	/* Set up initial bus frequencies */
-	chip_i2c_set_freq(p->port, freq);
-
-	/* Set up default timeout */
-	i2c_set_timeout(port, 0);
-
-	return ret;
-}
-
-/*****************************************************************************/
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-/* Host command peripheral */
-/*
- * Buffer for received host command packets (including prefix byte on request,
- * and result/size on response).  After any protocol-specific headers, the
- * buffers must be 32-bit aligned.
- */
-static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
-				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t * const host_buffer = host_buffer_padded + 2;
-static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
-static int host_i2c_resp_port;
-static int tx_pending;
-static int tx_index, tx_end;
-static struct host_packet i2c_packet;
-
-static void i2c_send_response_packet(struct host_packet *pkt)
-{
-	int size = pkt->response_size;
-	uint8_t *out = host_buffer;
-
-	/* Ignore host command in-progress */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result and size to first two bytes. */
-	*out++ = pkt->driver_result;
-	*out++ = size;
-
-	/* host_buffer data range */
-	tx_index = 0;
-	tx_end = size + 2;
-
-	/*
-	 * Set the transmitter to be in 'not full' state to keep sending
-	 * '0xec' in the event loop. Because of this, the controller i2c
-	 * doesn't need to snoop the response stream to abort transaction.
-	 */
-	STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE;
-}
-
-/* Process the command in the i2c host buffer */
-static void i2c_process_command(void)
-{
-	char *buff = host_buffer;
-
-	/*
-	 * TODO(crosbug.com/p/29241): Combine this functionality with the
-	 * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one
-	 * host command i2c process function which handles all protocol
-	 * versions.
-	 */
-	i2c_packet.send_response = i2c_send_response_packet;
-
-	i2c_packet.request = (const void *)(&buff[1]);
-	i2c_packet.request_temp = params_copy;
-	i2c_packet.request_max = sizeof(params_copy);
-	/* Don't know the request size so pass in the entire buffer */
-	i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE;
-
-	/*
-	 * Stuff response at buff[2] to leave the first two bytes of
-	 * buffer available for the result and size to send over i2c.  Note
-	 * that this 2-byte offset and the 2-byte offset from host_buffer
-	 * add up to make the response buffer 32-bit aligned.
-	 */
-	i2c_packet.response = (void *)(&buff[2]);
-	i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE;
-	i2c_packet.response_size = 0;
-
-	if (*buff >= EC_COMMAND_PROTOCOL_3) {
-		i2c_packet.driver_result = EC_RES_SUCCESS;
-	} else {
-		/* Only host command protocol 3 is supported. */
-		i2c_packet.driver_result = EC_RES_INVALID_HEADER;
-	}
-	host_packet_receive(&i2c_packet);
-}
-
-#ifdef TCPCI_I2C_PERIPHERAL
-static void i2c_send_tcpc_response(int len)
-{
-	/* host_buffer data range, beyond this length, will return 0xec */
-	tx_index = 0;
-	tx_end = len;
-
-	/* enable transmit interrupt and use irq to send data back */
-	STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE;
-}
-
-static void i2c_process_tcpc_command(int read, int addr, int len)
-{
-	tcpc_i2c_process(read, TCPC_ADDR_TO_PORT(addr), len, &host_buffer[0],
-			 i2c_send_tcpc_response);
-}
-#endif
-
-static void i2c_event_handler(int port)
-{
-	int i2c_isr;
-	static int rx_pending, buf_idx;
-#ifdef TCPCI_I2C_PERIPHERAL
-	int addr;
-#endif
-
-	i2c_isr = STM32_I2C_ISR(port);
-
-	/*
-	 * Check for error conditions. Note, arbitration loss and bus error
-	 * are the only two errors we can get as a peripheral allowing clock
-	 * stretching and in non-SMBus mode.
-	 */
-	if (i2c_isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) {
-		rx_pending = 0;
-		tx_pending = 0;
-
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-		/* Clear error status bits */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF |
-				STM32_I2C_ICR_ARLOCF;
-	}
-
-	/* Transfer matched our peripheral address */
-	if (i2c_isr & STM32_I2C_ISR_ADDR) {
-		if (i2c_isr & STM32_I2C_ISR_DIR) {
-			/* Transmitter peripheral */
-			/* Clear transmit buffer */
-			STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE;
-
-			/* Enable txis interrupt to start response */
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE;
-		} else {
-			/* Receiver peripheral */
-			buf_idx = 0;
-			rx_pending = 1;
-		}
-
-		/* Clear ADDR bit by writing to ADDRCF bit */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF;
-		/* Inhibit sleep mode when addressed until STOPF flag is set */
-		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Receiver full event */
-	if (i2c_isr & STM32_I2C_ISR_RXNE)
-		host_buffer[buf_idx++] = STM32_I2C_RXDR(port);
-
-	/* Stop condition on bus */
-	if (i2c_isr & STM32_I2C_ISR_STOP) {
-#ifdef TCPCI_I2C_PERIPHERAL
-		/*
-		 * if tcpc is being addressed, and we received a stop
-		 * while rx is pending, then this is a write only to
-		 * the tcpc.
-		 */
-		addr = STM32_I2C_ISR_ADDCODE(STM32_I2C_ISR(port));
-		if (rx_pending && ADDR_IS_TCPC(addr))
-			i2c_process_tcpc_command(0, addr, buf_idx);
-#endif
-		rx_pending = 0;
-		tx_pending = 0;
-
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-		/* Clear STOPF bit by writing to STOPCF bit */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF;
-
-		/* No longer inhibit deep sleep after stop condition */
-		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Controller requested STOP or RESTART */
-	if (i2c_isr & STM32_I2C_ISR_NACK) {
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-		/* Clear NACK */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF;
-		/* Resend last byte on RESTART */
-		if (port == I2C_PORT_EC && tx_index)
-			tx_index--;
-	}
-
-	/* Transmitter empty event */
-	if (i2c_isr & STM32_I2C_ISR_TXIS) {
-		if (port == I2C_PORT_EC) { /* host is waiting for PD response */
-			if (tx_pending) {
-				if (tx_index < tx_end) {
-					STM32_I2C_TXDR(port) =
-						host_buffer[tx_index++];
-				} else {
-					STM32_I2C_TXDR(port) = 0xec;
-					/*
-					 * Set tx_index = 0 to prevent NACK
-					 * handler resending last buffer byte.
-					 */
-					tx_index = 0;
-					tx_end = 0;
-					/* No pending data */
-					tx_pending = 0;
-				}
-			} else if (rx_pending) {
-				host_i2c_resp_port = port;
-				/*
-				 * Disable TXIS interrupt, transmission will
-				 * be prepared by host command task.
-				 */
-				STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-#ifdef TCPCI_I2C_PERIPHERAL
-				addr = STM32_I2C_ISR_ADDCODE(
-					STM32_I2C_ISR(port));
-				if (ADDR_IS_TCPC(addr))
-					i2c_process_tcpc_command(1, addr,
-								 buf_idx);
-				else
-#endif
-					i2c_process_command();
-
-				/* Reset host buffer after end of transfer */
-				rx_pending = 0;
-				tx_pending = 1;
-			} else {
-				STM32_I2C_TXDR(port) = 0xec;
-			}
-		}
-	}
-}
-void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
-DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2);
-#endif
-
-/*****************************************************************************/
-/* Interface */
-
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
-	int rv = EC_SUCCESS;
-	int i;
-	int xfer_start = flags & I2C_XFER_START;
-	int xfer_stop = flags & I2C_XFER_STOP;
-
-#if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT)
-	if (port == CONFIG_I2C_SCL_GATE_PORT &&
-	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
-		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1);
-#endif
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	/* Clear status */
-	if (xfer_start) {
-		uint32_t cr2 = STM32_I2C_CR2(port);
-
-		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
-		STM32_I2C_CR2(port) = 0;
-		if (cr2 & STM32_I2C_CR2_RELOAD) {
-			/*
-			 * If I2C_XFER_START flag is on and we've set RELOAD=1
-			 * in previous chip_i2c_xfer() call. Then we are
-			 * probably in the middle of an i2c transaction.
-			 *
-			 * In this case, we need to clear the RELOAD bit and
-			 * wait for Transfer Complete (TC) flag, to make sure
-			 * the chip is not expecting another NBYTES data, And
-			 * send repeated-start correctly.
-			 */
-			rv = wait_isr(port, STM32_I2C_ISR_TC);
-			if (rv)
-				goto xfer_exit;
-		}
-	}
-
-	if (out_bytes || !in_bytes) {
-		/*
-		 * Configure the write transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we are starting, then set START bit.
-		 */
-		STM32_I2C_CR2(port) =  ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < out_bytes; i++) {
-			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
-			if (rv)
-				goto xfer_exit;
-			/* Write next data byte */
-			STM32_I2C_TXDR(port) = out[i];
-		}
-	}
-	if (in_bytes) {
-		if (out_bytes) { /* wait for completion of the write */
-			rv = wait_isr(port, STM32_I2C_ISR_TC);
-			if (rv)
-				goto xfer_exit;
-		}
-		/*
-		 * Configure the read transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we were just transmitting, we need to
-		 * set START bit to send (re)start and begin read transaction.
-		 */
-		STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < in_bytes; i++) {
-			/* Wait for receive buffer not empty */
-			rv = wait_isr(port, STM32_I2C_ISR_RXNE);
-			if (rv)
-				goto xfer_exit;
-
-			in[i] = STM32_I2C_RXDR(port);
-		}
-	}
-
-	/*
-	 * If we are stopping, then we already set AUTOEND and we should
-	 * wait for the stop bit to be transmitted. Otherwise, we set
-	 * the RELOAD bit and we should wait for transfer complete
-	 * reload (TCR).
-	 */
-	rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR);
-	if (rv)
-		goto xfer_exit;
-
-xfer_exit:
-	/* clear status */
-	if (xfer_stop)
-		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
-
-	/* On error, queue a stop condition */
-	if (rv) {
-		/* queue a STOP condition */
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP;
-		/* wait for it to take effect */
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY))
-				break;
-			udelay(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows peripherals on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		udelay(10);
-		/* re-initialize the controller */
-		STM32_I2C_CR2(port) = 0;
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE;
-		udelay(10);
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-	}
-
-#ifdef CONFIG_I2C_SCL_GATE_ADDR
-	if (port == CONFIG_I2C_SCL_GATE_PORT &&
-	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
-		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0);
-#endif
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
-			| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
-			| STM32_I2C_CR1_NACKIE;
-#if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
-	/*
-	 * If using low power idle and EC port is I2C1, then set I2C1 to wake
-	 * from STOP mode on address match. Note, this only works on I2C1 and
-	 * only if the clock to I2C1 is HSI 8MHz.
-	 */
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN;
-#endif
-	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
-		| (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
-#ifdef TCPCI_I2C_PERIPHERAL
-	/*
-	 * Configure TCPC address with OA2[1] masked so that we respond
-	 * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2.
-	 */
-	STM32_I2C_OAR2(I2C_PORT_EC) = 0x8100
-		| (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1);
-#endif
-	task_enable_irq(IRQ_PERIPHERAL);
-#endif
-}
-
diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c
deleted file mode 120000
index ce8523ea90..0000000000
--- a/chip/stm32/i2c-stm32f3.c
+++ /dev/null
@@ -1 +0,0 @@
-i2c-stm32f0.c
\ No newline at end of file
diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c
deleted file mode 100644
index c1f19704b5..0000000000
--- a/chip/stm32/i2c-stm32f4.c
+++ /dev/null
@@ -1,1010 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
-
-/* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_CONTROLLER   (10 * MSEC)
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-#if (I2C_PORT_EC == STM32_I2C1_PORT)
-#define IRQ_PERIPHERAL_EV STM32_IRQ_I2C1_EV
-#define IRQ_PERIPHERAL_ER STM32_IRQ_I2C1_ER
-#else
-#define IRQ_PERIPHERAL_EV STM32_IRQ_I2C2_EV
-#define IRQ_PERIPHERAL_ER STM32_IRQ_I2C2_ER
-#endif
-#endif
-
-/* Define I2C blocks available in stm32f4:
- * We have standard ST I2C blocks and a "fast mode plus" I2C block,
- * which do not share the same registers or functionality. So we'll need
- * two sets of functions to handle this for stm32f4. In stm32f446, we
- * only have one FMP block so we'll hardcode its port number.
- */
-#define STM32F4_FMPI2C_PORT	3
-
-static const __unused struct dma_option dma_tx_option[I2C_PORT_COUNT] = {
-	{STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH)},
-	{STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH)},
-	{STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH)},
-	{STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH)},
-};
-
-static const struct dma_option dma_rx_option[I2C_PORT_COUNT] = {
-	{STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH)},
-	{STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH)},
-	{STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH)},
-	{STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH)},
-};
-
-/* Callback for ISR to wake task on DMA complete. */
-static inline void _i2c_dma_wake_callback(void *cb_data, int port)
-{
-	task_id_t id = (task_id_t)(int)cb_data;
-
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_I2C_COMPLETION(port));
-}
-
-/* Each callback is hardcoded to an I2C channel. */
-static void _i2c_dma_wake_callback_0(void *cb_data)
-{
-	_i2c_dma_wake_callback(cb_data, 0);
-}
-
-static void _i2c_dma_wake_callback_1(void *cb_data)
-{
-	_i2c_dma_wake_callback(cb_data, 1);
-}
-
-static void _i2c_dma_wake_callback_2(void *cb_data)
-{
-	_i2c_dma_wake_callback(cb_data, 2);
-}
-
-static void _i2c_dma_wake_callback_3(void *cb_data)
-{
-	_i2c_dma_wake_callback(cb_data, 3);
-}
-
-/* void (*callback)(void *) */
-static void (*i2c_callbacks[I2C_PORT_COUNT])(void *) = {
-	_i2c_dma_wake_callback_0,
-	_i2c_dma_wake_callback_1,
-	_i2c_dma_wake_callback_2,
-	_i2c_dma_wake_callback_3,
-};
-
-/* Enable the I2C interrupt callback for this port. */
-void i2c_dma_enable_tc_interrupt(enum dma_channel stream, int port)
-{
-	dma_enable_tc_interrupt_callback(stream, i2c_callbacks[port],
-					 (void *)(int)task_get_current());
-}
-
-/**
- * Wait for SR1 register to contain the specified mask of 0 or 1.
- *
- * @param port		I2C port
- * @param mask		mask of bits of interest
- * @param val		desired value of bits of interest
- * @param poll		uS poll frequency
- *
- * @return		EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-#define SET 0xffffffff
-#define UNSET 0
-static int wait_sr1_poll(int port, int mask, int val, int poll)
-{
-	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_CONTROLLER;
-
-	while (get_time().val < timeout) {
-		int sr1 = STM32_I2C_SR1(port);
-
-		/* Check for errors */
-		if (sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR |
-			   STM32_I2C_SR1_AF)) {
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* Check for desired mask */
-		if ((sr1 & mask) == (val & mask))
-			return EC_SUCCESS;
-
-		/* I2C is slow, so let other things run while we wait */
-		usleep(poll);
-	}
-
-	CPRINTS("I2C timeout: p:%d m:%x", port, mask);
-	return EC_ERROR_TIMEOUT;
-}
-
-/* Wait for SR1 register to contain the specified mask of ones */
-static int wait_sr1(int port, int mask)
-{
-	return wait_sr1_poll(port, mask, SET, 100);
-}
-
-
-/**
- * Send a start condition and peripheral address on the specified port.
- *
- * @param port		I2C port
- * @param addr_8bit	I2C address, with LSB set for receive-mode
- *
- * @return Non-zero if error.
- */
-static int send_start(const int port, const uint16_t addr_8bit)
-{
-	int rv;
-
-	/* Send start bit */
-	STM32_I2C_CR1(port) |= STM32_I2C_CR1_START;
-	rv = wait_sr1_poll(port, STM32_I2C_SR1_SB, SET, 1);
-	if (rv)
-		return I2C_ERROR_FAILED_START;
-
-	/* Write peripheral address */
-	STM32_I2C_DR(port) = addr_8bit;
-	rv = wait_sr1_poll(port, STM32_I2C_SR1_ADDR, SET, 1);
-	if (rv)
-		return rv;
-
-	/* Read SR2 to clear ADDR bit */
-	rv = STM32_I2C_SR2(port);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Find the i2c port structure associated with the port.
- *
- * @return i2c_port_t * associated with this port number.
- */
-static const struct i2c_port_t *find_port(int port)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++) {
-		if (p->port == port)
-			return p;
-	}
-	CPRINTS("I2C port %d invalid! Crashing now.", port);
-	return NULL;
-}
-
-/**
- * Wait for ISR register to contain the specified mask.
- *
- * @param port		I2C port
- * @param mask		mask of bits of interest
- * @param val		desired value of bits of interest
- * @param poll		uS poll frequency
- *
- * @return		EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_fmpi2c_isr_poll(int port, int mask, int val, int poll)
-{
-	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_CONTROLLER;
-
-	while (get_time().val < timeout) {
-		int isr = STM32_FMPI2C_ISR(port);
-
-		/* Check for errors */
-		if (isr & (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR |
-			   FMPI2C_ISR_NACKF)) {
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* Check for desired mask */
-		if ((isr & mask) == (val & mask))
-			return EC_SUCCESS;
-
-		/* I2C is slow, so let other things run while we wait */
-		usleep(poll);
-	}
-
-	CPRINTS("FMPI2C timeout p:%d, m:0x%08x", port, mask);
-	return EC_ERROR_TIMEOUT;
-}
-
-/* Wait for ISR register to contain the specified mask of ones */
-static int wait_fmpi2c_isr(int port, int mask)
-{
-	return wait_fmpi2c_isr_poll(port, mask, SET, 100);
-}
-
-/**
- * Send a start condition and peripheral address on the specified port.
- *
- * @param port		I2C port
- * @param addr_8bit	I2C address
- * @param size		bytes to transfer
- * @param is_read	read, or write?
- *
- * @return Non-zero if error.
- */
-static int send_fmpi2c_start(const int port, const uint16_t addr_8bit,
-			     int size, int is_read)
-{
-	uint32_t reg;
-
-	/* Send start bit */
-	reg = STM32_FMPI2C_CR2(port);
-	reg &= ~(FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK |
-		FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND |
-		FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP);
-	reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND |
-		addr_8bit | FMPI2C_CR2_SIZE(size) |
-		(is_read ? FMPI2C_CR2_RD_WRN : 0);
-	STM32_FMPI2C_CR2(port) = reg;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set i2c clock rate..
- *
- * @param p		I2C port struct
- */
-static void i2c_set_freq_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	int freq = clock_get_freq();
-
-	if (p->port == STM32F4_FMPI2C_PORT) {
-		int prescalar;
-		int actual;
-		uint32_t reg;
-
-		/* FMP I2C clock set. */
-		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE;
-		prescalar = (freq / (p->kbps * 1000 *
-			     (0x12 + 1 + 0xe + 1 + 1))) - 1;
-		actual = freq / ((prescalar + 1) * (0x12 + 1 + 0xe + 1 + 1));
-
-		reg = FMPI2C_TIMINGR_SCLL(0x12) |
-			FMPI2C_TIMINGR_SCLH(0xe) |
-			FMPI2C_TIMINGR_PRESC(prescalar);
-		STM32_FMPI2C_TIMINGR(port) = reg;
-
-		CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x",
-			port, p->kbps, prescalar, actual, reg);
-
-		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE;
-		udelay(10);
-	} else {
-		/* Force peripheral reset and disable port */
-		STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST;
-		STM32_I2C_CR1(port) = 0;
-
-		/* Set clock frequency */
-		if (p->kbps > 100) {
-			STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps);
-		} else {
-			STM32_I2C_CCR(port) = STM32_I2C_CCR_FM
-				| STM32_I2C_CCR_DUTY
-				| (freq / (16 + 9 * MSEC * p->kbps));
-		}
-		STM32_I2C_CR2(port) = freq / SECOND;
-		STM32_I2C_TRISE(port) = freq / SECOND + 1;
-
-		/* Enable port */
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-	}
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static void i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-
-	/* Configure GPIOs, clocks */
-	gpio_config_module(MODULE_I2C, 1);
-	clock_enable_module(MODULE_I2C, 1);
-
-	if (p->port == STM32F4_FMPI2C_PORT) {
-		/* FMP I2C block */
-		/* Set timing (?) */
-		STM32_FMPI2C_TIMINGR(port) = TIMINGR_THE_RIGHT_VALUE;
-		udelay(10);
-		/* Device enable */
-		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE;
-		/* Need to wait 3 APB cycles */
-		udelay(10);
-		/* Device only. */
-		STM32_FMPI2C_OAR1(port) = 0;
-		STM32_FMPI2C_CR2(port) |= FMPI2C_CR2_AUTOEND;
-	} else {
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_SWRST;
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_SWRST;
-		udelay(10);
-	}
-
-	/* Set up initial bus frequencies */
-	i2c_set_freq_port(p);
-}
-
-/*****************************************************************************/
-/* Interface */
-
-/**
- * Clear status regs on the specified I2C port.
- *
- * @param port		the I2c port
- */
-static void fmpi2c_clear_regs(int port)
-{
-	/* Clear status */
-	STM32_FMPI2C_ICR(port) = 0xffffffff;
-
-	/* Clear start, stop, NACK, etc. bits to get us in a known state */
-	STM32_FMPI2C_CR2(port) &= ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP |
-				FMPI2C_CR2_RD_WRN | FMPI2C_CR2_NACK |
-				FMPI2C_CR2_AUTOEND |
-				FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK);
-}
-
-/**
- * Perform an i2c transaction
- *
- * @param port		i2c port to use
- * @param addr_8bit	the i2c address
- * @param out		source buffer for data
- * @param out_bytes	bytes of data to write
- * @param in		destination buffer for data
- * @param in_bytes	bytes of data to read
- * @param flags		user cached I2C state
- *
- * @return		EC_SUCCESS on success.
- */
-static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
-			    const uint8_t *out, int out_bytes,
-			    uint8_t *in, int in_bytes, int flags)
-{
-	int started = (flags & I2C_XFER_START) ? 0 : 1;
-	int rv = EC_SUCCESS;
-	int i;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-	ASSERT(!started);
-
-	if (STM32_FMPI2C_ISR(port) & FMPI2C_ISR_BUSY) {
-		CPRINTS("fmpi2c port %d busy", port);
-		return EC_ERROR_BUSY;
-	}
-
-	fmpi2c_clear_regs(port);
-
-	/* No out bytes and no in bytes means just check for active */
-	if (out_bytes || !in_bytes) {
-		rv = send_fmpi2c_start(
-			port, addr_8bit, out_bytes, FMPI2C_WRITE);
-		if (rv)
-			goto xfer_exit;
-
-		/* Write data, if any */
-		for (i = 0; i < out_bytes; i++) {
-			rv = wait_fmpi2c_isr(port, FMPI2C_ISR_TXIS);
-			if (rv)
-				goto xfer_exit;
-
-			/* Write next data byte */
-			STM32_FMPI2C_TXDR(port) = out[i];
-		}
-
-		/* Wait for transaction STOP. */
-		wait_fmpi2c_isr(port, FMPI2C_ISR_STOPF);
-	}
-
-	if (in_bytes) {
-		int rv_start;
-		const struct dma_option *dma = dma_rx_option + port;
-
-		dma_start_rx(dma, in_bytes, in);
-		i2c_dma_enable_tc_interrupt(dma->channel, port);
-
-		rv_start = send_fmpi2c_start(
-				port, addr_8bit, in_bytes, FMPI2C_READ);
-		if (rv_start)
-			goto xfer_exit;
-
-		rv = wait_fmpi2c_isr(port, FMPI2C_ISR_RXNE);
-		if (rv)
-			goto xfer_exit;
-		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_RXDMAEN;
-
-		rv = task_wait_event_mask(
-				TASK_EVENT_I2C_COMPLETION(port),
-				DMA_TRANSFER_TIMEOUT_US);
-		if (rv & TASK_EVENT_I2C_COMPLETION(port))
-			rv = EC_SUCCESS;
-		else
-			rv = EC_ERROR_TIMEOUT;
-
-		dma_disable(dma->channel);
-		dma_disable_tc_interrupt(dma->channel);
-
-		/* Validate i2c is STOPped */
-		if (!rv)
-			rv = wait_fmpi2c_isr(port, FMPI2C_ISR_STOPF);
-
-		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_RXDMAEN;
-	}
-
- xfer_exit:
-	/* On error, queue a stop condition */
-	if (rv) {
-		flags |= I2C_XFER_STOP;
-		STM32_FMPI2C_CR2(port) |= FMPI2C_CR2_STOP;
-
-		/*
-		 * If failed at sending start, try resetting the port
-		 * to unwedge the bus.
-		 */
-		if (rv == I2C_ERROR_FAILED_START) {
-			const struct i2c_port_t *p;
-
-			CPRINTS("chip_fmpi2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
-
-			p = find_port(port);
-			i2c_unwedge(port);
-			i2c_init_port(p);
-		}
-	}
-
-	/* If a stop condition is queued, wait for it to take effect */
-	if (flags & I2C_XFER_STOP) {
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_FMPI2C_ISR(port) & FMPI2C_ISR_BUSY))
-				break;
-			usleep(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows peripherals on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE;
-		usleep(10);
-		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE;
-	}
-
-	return rv;
-}
-
-
-/**
- * Clear status regs on the specified I2C port.
- *
- * @param port		the I2c port
- */
-static void i2c_clear_regs(int port)
-{
-	/*
-	 * Clear status
-	 *
-	 * TODO(crosbug.com/p/29314): should check for any leftover error
-	 * status, and reset the port if present.
-	 */
-	STM32_I2C_SR1(port) = 0;
-
-	/* Clear start, stop, POS, ACK bits to get us in a known state */
-	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START |
-				 STM32_I2C_CR1_STOP |
-				 STM32_I2C_CR1_POS |
-				 STM32_I2C_CR1_ACK);
-}
-
-/*****************************************************************************
- * Exported functions declared in i2c.h
- */
-
-/* Perform an i2c transaction. */
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
-	int started = (flags & I2C_XFER_START) ? 0 : 1;
-	int rv = EC_SUCCESS;
-	int i;
-	const struct i2c_port_t *p = find_port(port);
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-	ASSERT(!started);
-
-	if (p->port == STM32F4_FMPI2C_PORT) {
-		return chip_fmpi2c_xfer(port, addr_8bit,
-					out, out_bytes,
-					in, in_bytes, flags);
-	}
-
-	i2c_clear_regs(port);
-
-	/* No out bytes and no in bytes means just check for active */
-	if (out_bytes || !in_bytes) {
-		rv = send_start(port, addr_8bit);
-		if (rv)
-			goto xfer_exit;
-
-		/* Write data, if any */
-		for (i = 0; i < out_bytes; i++) {
-			/* Write next data byte */
-			STM32_I2C_DR(port) = out[i];
-
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-		}
-
-		/* If no input bytes, queue stop condition */
-		if (!in_bytes && (flags & I2C_XFER_STOP))
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-	}
-
-	if (in_bytes) {
-		int rv_start;
-
-		const struct dma_option *dma = dma_rx_option + port;
-
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_POS;
-		dma_start_rx(dma, in_bytes, in);
-		i2c_dma_enable_tc_interrupt(dma->channel, port);
-
-		/* Setup ACK/POS before sending start as per user manual */
-		if (in_bytes == 2)
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_POS;
-		else if (in_bytes != 1)
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_ACK;
-
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_STOP;
-
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_LAST;
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_DMAEN;
-
-		rv_start = send_start(port, addr_8bit | 0x01);
-
-		if ((in_bytes == 1) && (flags & I2C_XFER_STOP))
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-		if (!rv_start) {
-			rv = task_wait_event_mask(
-				TASK_EVENT_I2C_COMPLETION(port),
-				DMA_TRANSFER_TIMEOUT_US);
-			if (rv & TASK_EVENT_I2C_COMPLETION(port))
-				rv = EC_SUCCESS;
-			else
-				rv = EC_ERROR_TIMEOUT;
-		}
-
-		dma_disable(dma->channel);
-		dma_disable_tc_interrupt(dma->channel);
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN;
-		/* Disable ack */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK;
-
-		if (rv_start)
-			rv = rv_start;
-
-		/* Send stop. */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK;
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_LAST;
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN;
-	}
-
- xfer_exit:
-	/* On error, queue a stop condition */
-	if (rv) {
-		flags |= I2C_XFER_STOP;
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-		/*
-		 * If failed at sending start, try resetting the port
-		 * to unwedge the bus.
-		 */
-		if (rv == I2C_ERROR_FAILED_START) {
-			const struct i2c_port_t *p;
-
-			CPRINTS("chip_i2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
-
-			p = find_port(port);
-			i2c_unwedge(port);
-			i2c_init_port(p);
-		}
-	}
-
-	/* If a stop condition is queued, wait for it to take effect */
-	if (flags & I2C_XFER_STOP) {
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_SR2(port) & STM32_I2C_SR2_BUSY))
-				break;
-			usleep(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows peripherals on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		usleep(10);
-	}
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-#ifdef CONFIG_I2C_CONTROLLER
-/* Handle CPU clock changing frequency */
-static void i2c_freq_change(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_set_freq_port(p);
-}
-
-/* Handle an upcoming frequency change. */
-static void i2c_pre_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/* Lock I2C ports so freq change can't interrupt an I2C transaction */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 1);
-}
-DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT);
-
-/* Handle a frequency change */
-static void i2c_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	i2c_freq_change();
-
-	/* Unlock I2C ports we locked in pre-freq change hook */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 0);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
-#endif
-
-/*****************************************************************************/
-/* Peripheral */
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-/* Host command peripheral */
-/*
- * Buffer for received host command packets (including prefix byte on request,
- * and result/size on response).  After any protocol-specific headers, the
- * buffers must be 32-bit aligned.
- */
-static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
-				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t * const host_buffer = host_buffer_padded + 2;
-static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
-static int host_i2c_resp_port;
-static int tx_pending;
-static int tx_index, tx_end;
-static struct host_packet i2c_packet;
-
-static void i2c_send_response_packet(struct host_packet *pkt)
-{
-	int size = pkt->response_size;
-	uint8_t *out = host_buffer;
-
-	/* Ignore host command in-progress */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result and size to first two bytes. */
-	*out++ = pkt->driver_result;
-	*out++ = size;
-
-	/* host_buffer data range */
-	tx_index = 0;
-	tx_end = size + 2;
-
-	/*
-	 * Set the transmitter to be in 'not full' state to keep sending
-	 * '0xec' in the event loop. Because of this, the controller i2c
-	 * doesn't need to snoop the response stream to abort transaction.
-	 */
-	STM32_I2C_CR2(host_i2c_resp_port) |= STM32_I2C_CR2_ITBUFEN;
-}
-
-/* Process the command in the i2c host buffer */
-static void i2c_process_command(void)
-{
-	char *buff = host_buffer;
-
-	/*
-	 * TODO(crosbug.com/p/29241): Combine this functionality with the
-	 * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one
-	 * host command i2c process function which handles all protocol
-	 * versions.
-	 */
-	i2c_packet.send_response = i2c_send_response_packet;
-
-	i2c_packet.request = (const void *)(&buff[1]);
-	i2c_packet.request_temp = params_copy;
-	i2c_packet.request_max = sizeof(params_copy);
-	/* Don't know the request size so pass in the entire buffer */
-	i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE;
-
-	/*
-	 * Stuff response at buff[2] to leave the first two bytes of
-	 * buffer available for the result and size to send over i2c.  Note
-	 * that this 2-byte offset and the 2-byte offset from host_buffer
-	 * add up to make the response buffer 32-bit aligned.
-	 */
-	i2c_packet.response = (void *)(&buff[2]);
-	i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE;
-	i2c_packet.response_size = 0;
-
-	if (*buff >= EC_COMMAND_PROTOCOL_3) {
-		i2c_packet.driver_result = EC_RES_SUCCESS;
-	} else {
-		/* Only host command protocol 3 is supported. */
-		i2c_packet.driver_result = EC_RES_INVALID_HEADER;
-	}
-	host_packet_receive(&i2c_packet);
-}
-
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-static void i2c_send_board_response(int len)
-{
-	/* host_buffer data range, beyond this length, will return 0xec */
-	tx_index = 0;
-	tx_end = len;
-
-	/* enable transmit interrupt and use irq to send data back */
-	STM32_I2C_CR2(host_i2c_resp_port) |= STM32_I2C_CR2_ITBUFEN;
-}
-
-static void i2c_process_board_command(int read, int addr, int len)
-{
-	board_i2c_process(read, addr, len, &host_buffer[0],
-			  i2c_send_board_response);
-}
-#endif
-
-static void i2c_event_handler(int port)
-{
-	volatile uint32_t i2c_cr1;
-	volatile uint32_t i2c_sr2;
-	volatile uint32_t i2c_sr1;
-	static int rx_pending, buf_idx;
-	static uint16_t addr_8bit;
-
-	volatile uint32_t unused __attribute__((unused));
-
-	i2c_cr1 = STM32_I2C_CR1(port);
-	i2c_sr2 = STM32_I2C_SR2(port);
-	i2c_sr1 = STM32_I2C_SR1(port);
-
-	/*
-	 * Check for error conditions. Note, arbitration loss and bus error
-	 * are the only two errors we can get as a peripheral allowing clock
-	 * stretching and in non-SMBus mode.
-	 */
-	if (i2c_sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR)) {
-		rx_pending = 0;
-		tx_pending = 0;
-		/* Disable buffer interrupt */
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
-		/* Clear error status bits */
-		STM32_I2C_SR1(port) &= ~(STM32_I2C_SR1_ARLO |
-					 STM32_I2C_SR1_BERR);
-	}
-
-	/* Transfer matched our peripheral address */
-	if (i2c_sr1 & STM32_I2C_SR1_ADDR) {
-		addr_8bit = ((i2c_sr2 & STM32_I2C_SR2_DUALF) ?
-			STM32_I2C_OAR2(port) : STM32_I2C_OAR1(port)) & 0xfe;
-		if (i2c_sr2 & STM32_I2C_SR2_TRA) {
-			/* Transmitter peripheral */
-			i2c_sr1 |= STM32_I2C_SR1_TXE;
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-			if (!rx_pending && !tx_pending) {
-				tx_pending = 1;
-				i2c_process_board_command(1, addr_8bit, 0);
-			}
-#endif
-		} else {
-			/* Receiver peripheral */
-			buf_idx = 0;
-			rx_pending = 1;
-		}
-
-		/* Enable buffer interrupt to start receive/response */
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_ITBUFEN;
-		/* Clear ADDR bit */
-		unused = STM32_I2C_SR1(port);
-		unused = STM32_I2C_SR2(port);
-		/* Inhibit stop mode when addressed until STOPF flag is set */
-		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* I2C in peripheral transmitter */
-	if (i2c_sr2 & STM32_I2C_SR2_TRA) {
-		if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_TXE)) {
-			if (tx_pending) {
-				if (tx_index < tx_end) {
-					STM32_I2C_DR(port) =
-						host_buffer[tx_index++];
-				} else {
-					STM32_I2C_DR(port) = 0xec;
-					tx_index = 0;
-					tx_end = 0;
-					tx_pending = 0;
-				}
-			} else if (rx_pending) {
-				host_i2c_resp_port = port;
-				/* Disable buffer interrupt */
-				STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-				if ((addr_8bit >> 1) ==
-				    I2C_STRIP_FLAGS(
-					    CONFIG_BOARD_I2C_ADDR_FLAGS))
-					i2c_process_board_command(1, addr_8bit,
-								  buf_idx);
-				else
-#endif
-					i2c_process_command();
-				/* Reset host buffer */
-				rx_pending = 0;
-				tx_pending = 1;
-			} else {
-				STM32_I2C_DR(port) = 0xec;
-			}
-		}
-	} else { /* I2C in peripheral receiver */
-		if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_RXNE))
-			host_buffer[buf_idx++] = STM32_I2C_DR(port);
-	}
-
-	/* STOPF or AF */
-	if (i2c_sr1 & (STM32_I2C_SR1_STOPF | STM32_I2C_SR1_AF)) {
-		/* Disable buffer interrupt */
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
-
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-		if (rx_pending &&
-		    (addr_8b >> 1) ==
-		    I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS))
-			i2c_process_board_command(0, addr_8bit, buf_idx);
-#endif
-		rx_pending = 0;
-		tx_pending = 0;
-
-		/* Clear AF */
-		STM32_I2C_SR1(port) &= ~STM32_I2C_SR1_AF;
-		/* Clear STOPF: read SR1 and write CR1 */
-		unused = STM32_I2C_SR1(port);
-		STM32_I2C_CR1(port) = i2c_cr1 | STM32_I2C_CR1_PE;
-
-		/* No longer inhibit deep sleep after stop condition */
-		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Enable again */
-	if (!(i2c_cr1 & STM32_I2C_CR1_PE))
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-}
-void i2c_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
-DECLARE_IRQ(IRQ_PERIPHERAL_EV, i2c_event_interrupt, 2);
-DECLARE_IRQ(IRQ_PERIPHERAL_ER, i2c_event_interrupt, 2);
-#endif
-
-
-/* Init all available i2c ports */
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	/* Enable ACK */
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_ACK;
-	/* Enable interrupts */
-	STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN
-			| STM32_I2C_CR2_ITERREN;
-	/* Setup host command peripheral */
-	STM32_I2C_OAR1(I2C_PORT_EC) = STM32_I2C_OAR1_B14
-		| (I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-	STM32_I2C_OAR2(I2C_PORT_EC) = STM32_I2C_OAR2_ENDUAL
-		| (I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1);
-#endif
-	task_enable_irq(IRQ_PERIPHERAL_EV);
-	task_enable_irq(IRQ_PERIPHERAL_ER);
-#endif
-}
diff --git a/chip/stm32/i2c-stm32g4.c b/chip/stm32/i2c-stm32g4.c
deleted file mode 100644
index eb1c7f1560..0000000000
--- a/chip/stm32/i2c-stm32g4.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
-
-/* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER   (10 * MSEC)
-
-enum i2c_freq_khz {
-	freq_100 = 100,
-	freq_400 = 400,
-	freq_1000 = 1000,
-};
-
-struct i2c_timing {
-	uint8_t scll;
-	uint8_t sclh;
-	uint8_t sdadel;
-	uint8_t scldel;
-	uint8_t presc;
-};
-
-/* timing register values for supported input clks / i2c clk rates */
-static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
-	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
-};
-
-/*
- * The following timing config values are given in Table 371 of TM0440 which
- * assumes an I2CCLK freq of 16 MHZ. I2CCLK is connected to HSI, with is @
- * 16MHz. The TRM recommends using the STM32CubeMX tool to get more accurate
- * values. Note that the actual clock period is (scll + 1) + (schl + 1) +
- * internal detection delays for SCL being low/high.
- */
-const struct i2c_timing i2c_timingr[I2C_FREQ_COUNT] = {
-	[I2C_FREQ_1000KHZ] = {
-		.scll = 4,
-		.sclh = 2,
-		.sdadel = 0,
-		.scldel = 2,
-		.presc = 0,
-	},
-		[I2C_FREQ_400KHZ] = {
-		.scll = 9,
-		.sclh = 4,
-		.sdadel = 2,
-		.scldel = 3,
-		.presc = 1,
-	},
-		[I2C_FREQ_100KHZ] = {
-		.scll = 19,
-		.sclh = 15,
-		.sdadel = 2,
-		.scldel = 4,
-		.presc = 3,
-	},
-};
-
-/*
- * For G4, I2C1 and I2C2 are contiguous in address space, but I2C3 and I2C4 are
- * at different offsets. In order to make the driver code easier, the base
- * address for each port's register block is defined here and can be used in i2c
- * register read/write accesses.
- */
-static const uint32_t i2c_regs_base[] = {
-	STM32_I2C1_BASE,
-	STM32_I2C2_BASE,
-	STM32_I2C3_BASE,
-	STM32_I2C4_BASE,
-};
-
-/* I2C port state data */
-struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER;
-}
-
-/**
- * Set i2c clock rate..
- *
- * @param p		I2C port struct
- */
-static void i2c_set_timingr_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	uint32_t base;
-	int index;
-	uint32_t timingr;
-
-	ASSERT(port < I2C_PORT_COUNT);
-	base = i2c_regs_base[port];
-
-	/*
-	 * To configure an I2C port frequency requires 5 values. scll, sclh,
-	 * sdadel, scldel, and presc. With these settings, the actual SCL period
-	 * (Tscl) is given by:
-	 *     Tscl = Tsync1 + Tsync2 + [(scll+1) + (sclh+1)] * presc * Ti2clck
-	 *
-	 * Using HSI for i2cclk, so this is fixed @ 16MHz. The recommended
-	 * values for the 5 parameters are from the TRM for i2clck @ 16 MHZ.
-	 * Note that Tsyncx is a function of SCL rise/fall times and filtering
-	 * selected for the given I2C port. sdadel and scldel affect when data
-	 * is written or read relative to SCL edges.
-	 */
-
-	if (p->kbps == freq_100) {
-		index = I2C_FREQ_100KHZ;
-	} else if (p->kbps == freq_400) {
-		index = I2C_FREQ_400KHZ;
-	} else if (p->kbps == freq_400) {
-		index = I2C_FREQ_1000KHZ;
-	} else {
-		index = I2C_FREQ_100KHZ;
-		CPRINTS("stm32 i2c[p%d]: Invalid freq, setting 100Khz instead!",
-			port);
-	}
-	/* Assemble write value for timingr register */
-	timingr = (i2c_timingr[index].scll << STM32_I2C_TIMINGR_SCLL_OFF) |
-		(i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) |
-		(i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) |
-		(i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) |
-		(i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF);
-
-	/* Write timingr value */
-	STM32_I2C_TIMINGR(base) = timingr;
-
-	/* Save freq lookup index for polling loop delay */
-	pdata[port].freq = index;
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static void i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	uint32_t base;
-
-	ASSERT(port < I2C_PORT_COUNT);
-	base = i2c_regs_base[port];
-
-	/*
-	 * The I2C module clock can be derived from sysclk, hsi16, or pclk1.
-	 * CrosEC will typically have sysclk = pclk = cpuclk. hsi16 is fixed at
-	 * 16 Mhz and given that it's a known freq, the timing register values
-	 * can be obtained via table lookup. The I2C clock source is selected
-	 * via the I2CnSEL field for a given I2C port.
-	 *
-	 * I2CnSEL is a 2 bit field in same register for ports 0-2 (1-3 in
-	 * STM32 notation), but is in a different register for port 3.
-	 */
-	if (port < 3) {
-		int clksel;
-		int mask;
-		int shift;
-
-		shift = STM32_RCC_CCIPR_I2C1SEL_SHIFT + 2 * port;
-		mask = STM32_RCC_CCIPR_I2CNSEL_MASK << shift;
-		clksel = STM32_RCC_CCIPR;
-		clksel &= ~mask;
-		STM32_RCC_CCIPR = clksel | (STM32_RCC_CCIPR_I2CNSEL_HSI
-					    << shift);
-	} else if (port == 3) {
-		/* i2c4sel is bits 1:0, no shift required */
-		STM32_RCC_CCIPR2 &= ~STM32_RCC_CCIPR2_I2C4SEL_MASK;
-		STM32_RCC_CCIPR2 |= STM32_RCC_CCIPR_I2CNSEL_HSI;
-	}
-
-	/*
-	 * Software reset for an I2C port is performed by clearing the PE bit in
-	 * that port's CR1 register. When this happens, SCL and SDA are
-	 * released, internal stame machines are reset, control/status bits are
-	 * also reset. The I2C block reset requires 3 APB cycles before setting
-	 * PE back to 1. This wait is ensured by the call fo i2c_set_freq_port.
-	 */
-	STM32_I2C_CR1(base) &= ~STM32_I2C_CR1_PE;
-	/* Set up initial bus frequencies */
-	i2c_set_timingr_port(p);
-	/* Enable the I2C port */
-	STM32_I2C_CR1(base) |= STM32_I2C_CR1_PE;
-
-	/* Set up default timeout */
-	i2c_set_timeout(port, 0);
-}
-
-/*****************************************************************************/
-/* Interface */
-/**
- * Wait for ISR register to contain the specified mask.
- *
- * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_isr(int port, int mask)
-{
-	uint32_t start = __hw_clock_source_read();
-	uint32_t delta;
-	uint32_t base;
-
-	ASSERT(port < I2C_PORT_COUNT);
-	base = i2c_regs_base[port];
-
-	do {
-		int isr = STM32_I2C_ISR(base);
-
-		/* Check for errors */
-		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			   STM32_I2C_ISR_NACK))
-			return EC_ERROR_UNKNOWN;
-
-		/* Check for desired mask */
-		if ((isr & mask) == mask)
-			return EC_SUCCESS;
-
-		delta = __hw_clock_source_read() - start;
-
-		/**
-		 * Depending on the bus speed, busy loop for a while before
-		 * sleeping and letting other things run.
-		 */
-		if (delta >= busyloop_us[pdata[port].freq])
-			usleep(100);
-	} while (delta < pdata[port].timeout_us);
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/*****************************************************************************
- * Exported functions declared in i2c.h
- */
-/* Perform an i2c transaction. */
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1;
-	int rv = EC_SUCCESS;
-	int i;
-	int xfer_start = flags & I2C_XFER_START;
-	int xfer_stop = flags & I2C_XFER_STOP;
-	uint32_t base;
-
-	ASSERT(port < I2C_PORT_COUNT);
-	base = i2c_regs_base[port];
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	/* Clear status */
-	if (xfer_start) {
-		STM32_I2C_ICR(base) = STM32_I2C_ICR_ALL;
-		STM32_I2C_CR2(base) = 0;
-	}
-
-	if (out_bytes || !in_bytes) {
-		/*
-		 * Configure the write transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we are starting, then set START bit.
-		 */
-		STM32_I2C_CR2(base) = ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < out_bytes; i++) {
-			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
-			if (rv)
-				goto xfer_exit;
-			/* Write next data byte */
-			STM32_I2C_TXDR(base) = out[i];
-		}
-	}
-	if (in_bytes) {
-		if (out_bytes) { /* wait for completion of the write */
-			rv = wait_isr(port, STM32_I2C_ISR_TC);
-			if (rv)
-				goto xfer_exit;
-		}
-		/*
-		 * Configure the read transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we were just transmitting, we need to
-		 * set START bit to send (re)start and begin read transaction.
-		 */
-		STM32_I2C_CR2(base) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < in_bytes; i++) {
-			/* Wait for receive buffer not empty */
-			rv = wait_isr(port, STM32_I2C_ISR_RXNE);
-			if (rv)
-				goto xfer_exit;
-			in[i] = STM32_I2C_RXDR(base);
-		}
-	}
-
-	/*
-	 * If we are stopping, then we already set AUTOEND and we should
-	 * wait for the stop bit to be transmitted. Otherwise, we set
-	 * the RELOAD bit and we should wait for transfer complete
-	 * reload (TCR).
-	 */
-	rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR);
-	if (rv)
-		goto xfer_exit;
-
-xfer_exit:
-	/* clear status */
-	if (xfer_stop)
-		STM32_I2C_ICR(base) = STM32_I2C_ICR_ALL;
-
-	/* On error, queue a stop condition */
-	if (rv) {
-		/* queue a STOP condition */
-		STM32_I2C_CR2(base) |= STM32_I2C_CR2_STOP;
-		/* wait for it to take effect */
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_ISR(base) & STM32_I2C_ISR_BUSY))
-				break;
-			udelay(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows slaves on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		udelay(10);
-		/* re-initialize the controller */
-		STM32_I2C_CR2(base) = 0;
-		STM32_I2C_CR1(base) &= ~STM32_I2C_CR1_PE;
-		udelay(10);
-		STM32_I2C_CR1(base) |= STM32_I2C_CR1_PE;
-	}
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-#ifdef CONFIG_I2C_CONTROLLER
-/* Handle an upcoming frequency change. */
-static void i2c_pre_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/* Lock I2C ports so freq change can't interrupt an I2C transaction */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 1);
-}
-DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT);
-
-/* Handle a frequency change */
-static void i2c_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/*
-	 * Handle CPU clock changing frequency and unlock I2C ports we locked
-	 * in pre-freq change hook
-	 */
-	for (i = 0; i < i2c_ports_used; i++, p++) {
-		i2c_set_timingr_port(p);
-		i2c_lock(p->port, 0);
-	}
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
-#endif
-
-/*****************************************************************************/
-
-/* Init all available i2c ports */
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/* Configure GPIO alt-func for all I2C ports */
-	gpio_config_module(MODULE_I2C, 1);
-	/* Enable the I2C clock for all I2C ports */
-	clock_enable_module(MODULE_I2C, 1);
-	/* Per port configuration */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-}
diff --git a/chip/stm32/i2c-stm32l.c b/chip/stm32/i2c-stm32l.c
deleted file mode 100644
index 2edcb1c0b6..0000000000
--- a/chip/stm32/i2c-stm32l.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
-
-/*
- * Transmit timeout in microseconds
- *
- * In theory we shouldn't have a timeout here (at least when we're in slave
- * mode).  The slave is supposed to wait forever for the master to read bytes.
- * ...but we're going to keep the timeout to make sure we're robust.  It may in
- * fact be needed if the host resets itself mid-read.
- *
- * NOTE: One case where this timeout is useful is when the battery
- * flips out.  The battery may flip out and hold lines low for up to
- * 25ms.  If we just wait it will eventually let them go.
- */
-#define I2C_TX_TIMEOUT_MASTER	(30 * MSEC)
-
-/*
- * Delay 5us in bitbang mode.  That gives us roughly 5us low and 5us high or
- * a frequency of 100kHz.
- */
-#define I2C_BITBANG_HALF_CYCLE_US    5
-
-#ifdef CONFIG_I2C_DEBUG
-static void dump_i2c_reg(int port, const char *what)
-{
-	CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s",
-		STM32_I2C_CR1(port),
-		STM32_I2C_CR2(port),
-		STM32_I2C_SR1(port),
-		STM32_I2C_SR2(port),
-		what);
-}
-#else
-static inline void dump_i2c_reg(int port, const char *what)
-{
-}
-#endif
-
-/**
- * Wait for SR1 register to contain the specified mask.
- *
- * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_sr1(int port, int mask)
-{
-	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER;
-
-	while (get_time().val < timeout) {
-		int sr1 = STM32_I2C_SR1(port);
-
-		/* Check for errors */
-		if (sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR |
-			   STM32_I2C_SR1_AF)) {
-			dump_i2c_reg(port, "wait_sr1 failed");
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* Check for desired mask */
-		if ((sr1 & mask) == mask)
-			return EC_SUCCESS;
-
-		/* I2C is slow, so let other things run while we wait */
-		usleep(100);
-	}
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/**
- * Send a start condition and slave address on the specified port.
- *
- * @param port		I2C port
- * @param slave_addr	Slave address, with LSB set for receive-mode
- *
- * @return Non-zero if error.
- */
-static int send_start(int port, uint16_t slave_addr_8bit)
-{
-	int rv;
-
-	/* Send start bit */
-	STM32_I2C_CR1(port) |= STM32_I2C_CR1_START;
-	dump_i2c_reg(port, "sent start");
-	rv = wait_sr1(port, STM32_I2C_SR1_SB);
-	if (rv)
-		return I2C_ERROR_FAILED_START;
-
-	/* Write slave address */
-	STM32_I2C_DR(port) = slave_addr_8bit & 0xff;
-	rv = wait_sr1(port, STM32_I2C_SR1_ADDR);
-	if (rv)
-		return rv;
-
-	/* Read SR2 to clear ADDR bit */
-	rv = STM32_I2C_SR2(port);
-
-	dump_i2c_reg(port, "wrote addr");
-
-	return EC_SUCCESS;
-}
-
-static void i2c_set_freq_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	int freq = clock_get_freq();
-
-	/* Force peripheral reset and disable port */
-	STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST;
-	STM32_I2C_CR1(port) = 0;
-
-	/* Set clock frequency */
-	STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps);
-	STM32_I2C_CR2(port) = freq / SECOND;
-	STM32_I2C_TRISE(port) = freq / SECOND + 1;
-
-	/* Enable port */
-	STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static void i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-
-	/* Enable clocks to I2C modules if necessary */
-	if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
-		STM32_RCC_APB1ENR |= 1 << (21 + port);
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Set up initial bus frequencies */
-	i2c_set_freq_port(p);
-}
-
-/*****************************************************************************/
-/* Interface */
-
-int chip_i2c_xfer(const int port,
-		  const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1;
-	int started = (flags & I2C_XFER_START) ? 0 : 1;
-	int rv = EC_SUCCESS;
-	int i;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	dump_i2c_reg(port, "xfer start");
-
-	/*
-	 * Clear status
-	 *
-	 * TODO(crosbug.com/p/29314): should check for any leftover error
-	 * status, and reset the port if present.
-	 */
-	STM32_I2C_SR1(port) = 0;
-
-	/* Clear start, stop, POS, ACK bits to get us in a known state */
-	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START |
-				 STM32_I2C_CR1_STOP |
-				 STM32_I2C_CR1_POS |
-				 STM32_I2C_CR1_ACK);
-
-	/* No out bytes and no in bytes means just check for active */
-	if (out_bytes || !in_bytes) {
-		if (!started) {
-			rv = send_start(port, addr_8bit);
-			if (rv)
-				goto xfer_exit;
-		}
-
-		/* Write data, if any */
-		for (i = 0; i < out_bytes; i++) {
-			/* Write next data byte */
-			STM32_I2C_DR(port) = out[i];
-			dump_i2c_reg(port, "wrote data");
-
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-		}
-
-		/* Need repeated start condition before reading */
-		started = 0;
-
-		/* If no input bytes, queue stop condition */
-		if (!in_bytes && (flags & I2C_XFER_STOP))
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-	}
-
-	if (in_bytes) {
-		/* Setup ACK/POS before sending start as per user manual */
-		if (in_bytes == 2)
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_POS;
-		else if (in_bytes != 1)
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_ACK;
-
-		if (!started) {
-			rv = send_start(port, addr_8bit | 0x01);
-			if (rv)
-				goto xfer_exit;
-		}
-
-		if (in_bytes == 1) {
-			/* Set stop immediately after ADDR cleared */
-			if (flags & I2C_XFER_STOP)
-				STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-			rv = wait_sr1(port, STM32_I2C_SR1_RXNE);
-			if (rv)
-				goto xfer_exit;
-
-			in[0] = STM32_I2C_DR(port);
-		} else if (in_bytes == 2) {
-			/* Wait till the shift register is full */
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-
-			if (flags & I2C_XFER_STOP)
-				STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-			in[0] = STM32_I2C_DR(port);
-			in[1] = STM32_I2C_DR(port);
-		} else {
-			/* Read all but last three */
-			for (i = 0; i < in_bytes - 3; i++) {
-				/* Wait for receive buffer not empty */
-				rv = wait_sr1(port, STM32_I2C_SR1_RXNE);
-				if (rv)
-					goto xfer_exit;
-
-				dump_i2c_reg(port, "read data");
-				in[i] = STM32_I2C_DR(port);
-				dump_i2c_reg(port, "post read data");
-			}
-
-			/* Wait for BTF (data N-2 in DR, N-1 in shift) */
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-
-			/* No more acking */
-			STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK;
-			in[i++] = STM32_I2C_DR(port);
-
-			/* Wait for BTF (data N-1 in DR, N in shift) */
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-
-			/* If this is the last byte, queue stop condition */
-			if (flags & I2C_XFER_STOP)
-				STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-			/* Read the last two bytes */
-			in[i++] = STM32_I2C_DR(port);
-			in[i++] = STM32_I2C_DR(port);
-		}
-	}
-
- xfer_exit:
-	/* On error, queue a stop condition */
-	if (rv) {
-		flags |= I2C_XFER_STOP;
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-		dump_i2c_reg(port, "stop after error");
-
-		/*
-		 * If failed at sending start, try resetting the port
-		 * to unwedge the bus.
-		 */
-		if (rv == I2C_ERROR_FAILED_START) {
-			const struct i2c_port_t *p = i2c_ports;
-			CPRINTS("chip_i2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
-
-			i2c_unwedge(port);
-
-			for (i = 0; i < i2c_ports_used; i++, p++) {
-				if (p->port == port) {
-					i2c_init_port(p);
-					break;
-				}
-			}
-		}
-	}
-
-	/* If a stop condition is queued, wait for it to take effect */
-	if (flags & I2C_XFER_STOP) {
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_SR2(port) & STM32_I2C_SR2_BUSY))
-				break;
-			udelay(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows slaves on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		udelay(10);
-	}
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-/* Handle CPU clock changing frequency */
-static void i2c_freq_change(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_set_freq_port(p);
-}
-
-static void i2c_pre_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/* Lock I2C ports so freq change can't interrupt an I2C transaction */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 1);
-}
-DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT);
-static void i2c_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	i2c_freq_change();
-
-	/* Unlock I2C ports we locked in pre-freq change hook */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 0);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
-
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_i2cdump(int argc, char **argv)
-{
-	dump_i2c_reg(I2C_PORT_MASTER, "dump");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump,
-			NULL,
-			"Dump I2C regs");
diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c
deleted file mode 100644
index 5997ed5b70..0000000000
--- a/chip/stm32/i2c-stm32l4.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "printf.h"
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "registers.h"
-
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER	(10 * MSEC)
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-#define I2C_SLAVE_ERROR_CODE	0xec
-#if (I2C_PORT_EC == STM32_I2C1_PORT)
-#define IRQ_SLAVE STM32_IRQ_I2C1
-#else
-#define IRQ_SLAVE STM32_IRQ_I2C2
-#endif
-#endif
-
-/* I2C port state data */
-struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER;
-}
-
-/* timing register values for supported input clks / i2c clk rates */
-static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
-	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
-};
-
-/**
- * Wait for ISR register to contain the specified mask.
- *
- * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_isr(int port, int mask)
-{
-	uint32_t start = __hw_clock_source_read();
-	uint32_t delta = 0;
-
-	do {
-		int isr = STM32_I2C_ISR(port);
-
-		/* Check for errors */
-		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			STM32_I2C_ISR_NACK))
-			return EC_ERROR_UNKNOWN;
-
-		/* Check for desired mask */
-		if ((isr & mask) == mask)
-			return EC_SUCCESS;
-
-		delta = __hw_clock_source_read() - start;
-
-		/**
-		 * Depending on the bus speed, busy loop for a while before
-		 * sleeping and letting other things run.
-		 */
-		if (delta >= busyloop_us[pdata[port].freq])
-			usleep(100);
-	} while (delta < pdata[port].timeout_us);
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/* Supported i2c input clocks */
-enum stm32_i2c_clk_src {
-	I2C_CLK_SRC_48MHZ = 0,
-	I2C_CLK_SRC_16MHZ = 1,
-	I2C_CLK_SRC_COUNT,
-};
-
-/* timing register values for supported input clks / i2c clk rates
- *
- * These values are calculated using ST's STM32cubeMX tool
- */
-static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
-	[I2C_CLK_SRC_48MHZ] = {
-		[I2C_FREQ_1000KHZ] = 0x20000209,
-		[I2C_FREQ_400KHZ] = 0x2010091A,
-		[I2C_FREQ_100KHZ] = 0x20303E5D,
-	},
-	[I2C_CLK_SRC_16MHZ] = {
-		[I2C_FREQ_1000KHZ] = 0x00000107,
-		[I2C_FREQ_400KHZ] = 0x00100B15,
-		[I2C_FREQ_100KHZ] = 0x00303D5B,
-	},
-};
-
-static void i2c_set_freq_port(const struct i2c_port_t *p,
-			      enum stm32_i2c_clk_src src,
-			      enum i2c_freq freq)
-{
-	int port = p->port;
-
-	/* Disable port */
-	STM32_I2C_CR1(port) = 0;
-	STM32_I2C_CR2(port) = 0;
-	/* Set clock frequency */
-	STM32_I2C_TIMINGR(port) = timingr_regs[src][freq];
-	/* Enable port */
-	STM32_I2C_CR1(port) = STM32_I2C_CR1_PE;
-
-	pdata[port].freq = freq;
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static void i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	uint32_t val;
-	enum i2c_freq freq;
-	enum stm32_i2c_clk_src src = I2C_CLK_SRC_16MHZ;
-
-	/* Enable I2C clock */
-	if (!(STM32_RCC_APB1ENR1 & (1 << (21 + port))))
-		STM32_RCC_APB1ENR1 |= 1 << (21 + port);
-
-	/*	Select HSI 16MHz as I2C clock source	*/
-	val = STM32_RCC_CCIPR;
-	val &= ~(STM32_RCC_CCIPR_I2C1SEL_MASK << (port * 2));
-	val |= STM32_RCC_CCIPR_I2C_HSI16
-	       << (STM32_RCC_CCIPR_I2C1SEL_SHIFT + port * 2);
-	STM32_RCC_CCIPR = val;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Set clock frequency */
-	switch (p->kbps) {
-	case 1000:
-		STM32_SYSCFG_CFGR1 |= STM32_SYSCFG_I2CFMP(port);
-		freq = I2C_FREQ_1000KHZ;
-		break;
-	case 400:
-		freq = I2C_FREQ_400KHZ;
-		break;
-	case 100:
-		freq = I2C_FREQ_100KHZ;
-		break;
-	default: /* unknown speed, defaults to 100kBps */
-		CPRINTS("I2C bad speed %d kBps", p->kbps);
-		freq = I2C_FREQ_100KHZ;
-	}
-
-	/* Set up initial bus frequencies */
-	i2c_set_freq_port(p, src, freq);
-
-	/* Set up default timeout */
-	i2c_set_timeout(port, 0);
-}
-
-/*****************************************************************************/
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-
-static void i2c_event_handler(int port)
-{
-	/* Variables tracking the handler state.
-	 * TODO: Should have as many sets of these variables as the number
-	 * of slave ports.
-	 */
-	static int rx_pending, rx_idx;
-	static int tx_pending, tx_idx, tx_end;
-	static uint8_t slave_buffer[I2C_MAX_HOST_PACKET_SIZE + 2];
-	int isr = STM32_I2C_ISR(port);
-
-	/*
-	 * Check for error conditions. Note, arbitration loss and bus error
-	 * are the only two errors we can get as a slave allowing clock
-	 * stretching and in non-SMBus mode.
-	 */
-	if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) {
-		rx_pending = 0;
-		tx_pending = 0;
-
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-		/* Clear error status bits */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF
-				| STM32_I2C_ICR_ARLOCF;
-	}
-
-	/* Transfer matched our slave address */
-	if (isr & STM32_I2C_ISR_ADDR) {
-		if (isr & STM32_I2C_ISR_DIR) {
-			/* Transmitter slave */
-			/* Clear transmit buffer */
-			STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE;
-
-			if (rx_pending)
-				/* RESTART */
-				i2c_data_received(port, slave_buffer, rx_idx);
-			tx_end = i2c_set_response(port, slave_buffer, rx_idx);
-			tx_idx = 0;
-			rx_pending = 0;
-			tx_pending = 1;
-
-			/* Enable txis interrupt to start response */
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE;
-		} else {
-			/* Receiver slave */
-			rx_idx = 0;
-			rx_pending = 1;
-			tx_pending = 0;
-		}
-
-		/* Clear ADDR bit by writing to ADDRCF bit */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF;
-		/* Inhibit stop mode when addressed until STOPF flag is set */
-		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/*
-	 * Receive buffer not empty
-	 *
-	 * When a master finishes sending data, it'll set STOP bit. It causes
-	 * the slave to receive RXNE and STOP interrupt at the same time. So,
-	 * we need to process RXNE first, then handle STOP.
-	 */
-	if (isr & STM32_I2C_ISR_RXNE)
-		slave_buffer[rx_idx++] = STM32_I2C_RXDR(port);
-
-	/* Stop condition on bus */
-	if (isr & STM32_I2C_ISR_STOP) {
-		if (rx_pending)
-			i2c_data_received(port, slave_buffer, rx_idx);
-		tx_idx = 0;
-		tx_end = 0;
-		rx_pending = 0;
-		tx_pending = 0;
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-		/* Clear STOPF bit by writing to STOPCF bit */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF;
-
-		/* No longer inhibit deep sleep after stop condition */
-		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	if (isr & STM32_I2C_ISR_NACK) {
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-		/* Clear NACK */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF;
-	}
-
-	/* Transmitter empty event */
-	if (isr & STM32_I2C_ISR_TXIS) {
-		if (port == I2C_PORT_EC) {
-			if (tx_pending) {
-				if (tx_idx < tx_end) {
-					STM32_I2C_TXDR(port) =
-						slave_buffer[tx_idx++];
-				} else {
-					STM32_I2C_TXDR(port)
-						= I2C_SLAVE_ERROR_CODE;
-					tx_idx = 0;
-					tx_end = 0;
-					tx_pending = 0;
-				}
-			} else {
-				STM32_I2C_TXDR(port) = I2C_SLAVE_ERROR_CODE;
-			}
-		}
-	}
-}
-
-void i2c_event_interrupt(void)
-{
-	i2c_event_handler(I2C_PORT_EC);
-}
-DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2);
-#endif
-
-/*****************************************************************************/
-/* Interface */
-
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1;
-	int rv = EC_SUCCESS;
-	int i;
-	int xfer_start = flags & I2C_XFER_START;
-	int xfer_stop = flags & I2C_XFER_STOP;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	/* Clear status */
-	if (xfer_start) {
-		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
-		STM32_I2C_CR2(port) = 0;
-	}
-
-	if (out_bytes || !in_bytes) {
-		/*
-		 * Configure the write transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we are starting, then set START bit.
-		 */
-		STM32_I2C_CR2(port) =  ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < out_bytes; i++) {
-			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
-			if (rv)
-				goto xfer_exit;
-			/* Write next data byte */
-			STM32_I2C_TXDR(port) = out[i];
-		}
-	}
-	if (in_bytes) {
-		if (out_bytes) { /* wait for completion of the write */
-			rv = wait_isr(port, STM32_I2C_ISR_TC);
-			if (rv)
-				goto xfer_exit;
-		}
-		/*
-		 * Configure the read transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we were just transmitting, we need to
-		 * set START bit to send (re)start and begin read transaction.
-		 */
-		STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < in_bytes; i++) {
-			/* Wait for receive buffer not empty */
-			rv = wait_isr(port, STM32_I2C_ISR_RXNE);
-			if (rv)
-				goto xfer_exit;
-
-			in[i] = STM32_I2C_RXDR(port);
-		}
-	}
-
-	/*
-	 * If we are stopping, then we already set AUTOEND and we should
-	 * wait for the stop bit to be transmitted. Otherwise, we set
-	 * the RELOAD bit and we should wait for transfer complete
-	 * reload (TCR).
-	 */
-	rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR);
-	if (rv)
-		goto xfer_exit;
-
-xfer_exit:
-	/* clear status */
-	if (xfer_stop)
-		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
-
-	/* On error, queue a stop condition */
-	if (rv) {
-		/* queue a STOP condition */
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP;
-		/* wait for it to take effect */
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY))
-				break;
-			udelay(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows slaves on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		udelay(10);
-		/* re-initialize the controller */
-		STM32_I2C_CR2(port) = 0;
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE;
-		udelay(10);
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-	}
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g))
-		/* If no SCL pin is defined, return 1 to appear idle. */
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g))
-		/* If no SDA pin is defined, return 1 to appear idle. */
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
-			| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
-			| STM32_I2C_CR1_NACKIE;
-	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
-		| (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
-	task_enable_irq(IRQ_SLAVE);
-#endif
-}
diff --git a/chip/stm32/i2c-stm32l5.c b/chip/stm32/i2c-stm32l5.c
deleted file mode 100644
index 86cc1c6df2..0000000000
--- a/chip/stm32/i2c-stm32l5.c
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c-stm32l4.c"
diff --git a/chip/stm32/i2c_ite_flash_support.c b/chip/stm32/i2c_ite_flash_support.c
deleted file mode 100644
index 916a8c364c..0000000000
--- a/chip/stm32/i2c_ite_flash_support.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* STM implementation for flashing ITE-based ECs over i2c */
-
-#include "i2c_ite_flash_support.h"
-#include "i2c.h"
-#include "registers.h"
-#include "time.h"
-
-/*
- * As of 2018-11-27 the default for both is 60 bytes.  These larger values allow
- * for reflashing of ITE EC chips over I2C
- * (https://issuetracker.google.com/79684405) in reasonably speedy fashion.  If
- * the EC firmware defaults are ever raised significantly, consider removing
- * these overrides.
- *
- * As of 2018-11-27 the actual maximum write size supported by the I2C-over-USB
- * protocol is (1<<12)-1, and the maximum read size supported is
- * (1<<15)-1.  However compile time assertions require that these values be
- * powers of 2 after overheads are included.  Thus, the write limit set here
- * /should/ be (1<<12)-4 and the read limit should be (1<<15)-6, however those
- * ideal limits are not actually possible because stm32 lacks sufficient
- * spare memory for them.  With symmetrical limits, the maximum that currently
- * fits is (1<<11)-4 write limit and (1<<11)-6 read limit, leaving 1404 bytes of
- * RAM available.
- *
- * However even with a sufficiently large write value here, the maximum that
- * actually works as of 2018-12-03 is 255 bytes.  Additionally, ITE EC firmware
- * image verification requires exactly 256 byte reads.  Thus the only useful
- * powers-of-2-minus-overhead limits to set here are (1<<9)-4 writes and
- * (1<<9)-6 reads, leaving 6012 bytes of RAM available, down from 7356 bytes of
- * RAM available with the default 60 byte limits.
- */
-#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1<<9) - 4)
-#error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 4)
-#endif
-#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1<<9) - 6)
-#error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 6)
-#endif
-
-/*
- * iteflash requires 256 byte reads for verifying ITE EC firmware.  Without this
- * the limit is CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE which is 255 for STM32F0 due
- * to an 8 bit field, per src/platform/ec/include/config.h comment.
- */
-#ifndef CONFIG_I2C_XFER_LARGE_TRANSFER
-#error Must define CONFIG_I2C_XFER_LARGE_TRANSFER
-#endif
-
-#define KHz 1000
-#define MHz (1000 * KHz)
-
-/*
- * These constants are values that one might want to try changing if
- * enable_ite_dfu stops working, or does not work on a new ITE EC chip revision.
- */
-
-#define ITE_DFU_I2C_CMD_ADDR_FLAGS 0x5A
-#define ITE_DFU_I2C_DATA_ADDR_FLAGS 0x35
-
-#define SMCLK_WAVEFORM_PERIOD_HZ (100 * KHz)
-#define SMDAT_WAVEFORM_PERIOD_HZ (200 * KHz)
-
-#define START_DELAY_MS 5
-#define SPECIAL_WAVEFORM_MS 50
-#define PLL_STABLE_MS 10
-
-/*
- * Digital line levels to hold before (PRE_) or after (POST_) sending the
- * special waveforms.  0 for low, 1 for high.
- */
-#define SMCLK_PRE_LEVEL 0
-#define SMDAT_PRE_LEVEL 0
-#define SMCLK_POST_LEVEL 0
-#define SMDAT_POST_LEVEL 0
-
-/* The caller should hold the i2c_lock() for ite_dfu_config.i2c_port. */
-static int ite_i2c_read_register(uint8_t register_offset, uint8_t *output)
-{
-	/*
-	 * Ideally the write and read would be done in one I2C transaction, as
-	 * is normally done when reading from the same I2C address that the
-	 * write was sent to.  The ITE EC is abnormal in that regard, with its
-	 * different 7-bit addresses for writes vs reads.
-	 *
-	 * i2c_xfer() does not support that.  Its I2C_XFER_START and
-	 * I2C_XFER_STOP flag bits do not cleanly support that scenario, they
-	 * are for continuing transfers without either of STOP or START
-	 * in-between.
-	 *
-	 * For what it's worth, the iteflash.c FTDI-based implementation of this
-	 * does the same thing, issuing a STOP between the write and read.  This
-	 * works, even if perhaps it should not.
-	 */
-	int ret;
-	/* Tell the ITE EC which register we want to read. */
-	ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port,
-				ITE_DFU_I2C_CMD_ADDR_FLAGS,
-				&register_offset, sizeof(register_offset),
-				NULL, 0, I2C_XFER_SINGLE);
-	if (ret != EC_SUCCESS)
-		return ret;
-	/* Read in the 1 byte register value. */
-	ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port,
-				ITE_DFU_I2C_DATA_ADDR_FLAGS,
-				NULL, 0,
-				output, sizeof(*output), I2C_XFER_SINGLE);
-	return ret;
-}
-
-/* Helper function to read ITE chip ID, for verifying ITE DFU mode. */
-static int cprint_ite_chip_id(void)
-{
-	/*
-	 * Per i2c_read8() implementation, use an array even for single byte
-	 * reads to ensure alignment for DMA on STM32.
-	 */
-	uint8_t chipid1[1];
-	uint8_t chipid2[1];
-	uint8_t chipver[1];
-
-	int ret;
-	int chip_version;
-	int flash_kb;
-
-	i2c_lock(ite_dfu_config.i2c_port, 1);
-
-	/* Read the CHIPID1 register. */
-	ret = ite_i2c_read_register(0x00, chipid1);
-	if (ret != EC_SUCCESS)
-		goto unlock;
-
-	/* Read the CHIPID2 register. */
-	ret = ite_i2c_read_register(0x01, chipid2);
-	if (ret != EC_SUCCESS)
-		goto unlock;
-
-	/* Read the CHIPVER register. */
-	ret = ite_i2c_read_register(0x02, chipver);
-
-unlock:
-	i2c_lock(ite_dfu_config.i2c_port, 0);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * Compute chip version and embedded flash size from the CHIPVER value.
-	 *
-	 * Chip version is mapping from bit 3-0
-	 * Flash size is mapping from bit 7-4
-	 *
-	 * Chip Version (bits 3-0)
-	 * 0: AX
-	 * 1: BX
-	 * 2: CX
-	 * 3: DX
-	 *
-	 * CX or prior flash size (bits 7-4)
-	 * 0:128KB
-	 * 4:192KB
-	 * 8:256KB
-	 *
-	 * DX flash size (bits 7-4)
-	 * 0:128KB
-	 * 2:192KB
-	 * 4:256KB
-	 * 6:384KB
-	 * 8:512KB
-	 */
-	chip_version = chipver[0] & 0x07;
-	if (chip_version < 0x3) {
-		/* Chip version is CX or earlier. */
-		switch (chipver[0] >> 4) {
-		case 0:
-			flash_kb = 128;
-			break;
-		case 4:
-			flash_kb = 192;
-			break;
-		case 8:
-			flash_kb = 256;
-			break;
-		default:
-			flash_kb = -2;
-		}
-	} else if (chip_version == 0x3) {
-		/* Chip version is DX. */
-		switch (chipver[0] >> 4) {
-		case 0:
-			flash_kb = 128;
-			break;
-		case 2:
-			flash_kb = 192;
-			break;
-		case 4:
-			flash_kb = 256;
-			break;
-		case 6:
-			flash_kb = 384;
-			break;
-		case 8:
-			flash_kb = 512;
-			break;
-		default:
-			flash_kb = -3;
-		}
-	} else {
-		/* Unrecognized chip version. */
-		flash_kb = -1;
-	}
-
-	ccprintf("ITE EC info: CHIPID1=0x%02X CHIPID2=0x%02X CHIPVER=0x%02X ",
-		chipid1[0], chipid2[0], chipver[0]);
-	ccprintf("version=%d flash_bytes=%d\n", chip_version, flash_kb << 10);
-
-	/*
-	 * IT8320_eflash_SMBus_Programming_Guide.pdf says it is an error if
-	 * CHIPID1 != 0x83.
-	 */
-	if (chipid1[0] != 0x83)
-		ret = EC_ERROR_HW_INTERNAL;
-
-	return ret;
-}
-
-/* Enable ITE direct firmware update (DFU) mode. */
-static int command_enable_ite_dfu(int argc, char **argv)
-{
-	if (argc > 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Ensure we can perform the dfu operation */
-	if (ite_dfu_config.access_allow && !ite_dfu_config.access_allow())
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Enable peripheral clocks. */
-	STM32_RCC_APB2ENR |=
-		STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN;
-
-	/* Reset timer registers which are not otherwise set below. */
-	STM32_TIM_CR2(16) = 0x0000;
-	STM32_TIM_CR2(17) = 0x0000;
-	STM32_TIM_DIER(16) = 0x0000;
-	STM32_TIM_DIER(17) = 0x0000;
-	STM32_TIM_SR(16) = 0x0000;
-	STM32_TIM_SR(17) = 0x0000;
-	STM32_TIM_CNT(16) = 0x0000;
-	STM32_TIM_CNT(17) = 0x0000;
-	STM32_TIM_RCR(16) = 0x0000;
-	STM32_TIM_RCR(17) = 0x0000;
-	STM32_TIM_DCR(16) = 0x0000;
-	STM32_TIM_DCR(17) = 0x0000;
-	STM32_TIM_DMAR(16) = 0x0000;
-	STM32_TIM_DMAR(17) = 0x0000;
-
-	/* Prescale to 1 MHz and use ARR to achieve NNN KHz periods. */
-	/* This approach is seen in STM's documentation. */
-	STM32_TIM_PSC(16) = (CPU_CLOCK / MHz) - 1;
-	STM32_TIM_PSC(17) = (CPU_CLOCK / MHz) - 1;
-
-	/* Set the waveform periods based on 1 MHz prescale. */
-	STM32_TIM_ARR(16) = (MHz / SMCLK_WAVEFORM_PERIOD_HZ) - 1;
-	STM32_TIM_ARR(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) - 1;
-
-	/* Set output compare 1 mode to PWM mode 1 and enable preload. */
-	STM32_TIM_CCMR1(16) =
-		STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
-	STM32_TIM_CCMR1(17) =
-		STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
-
-	/*
-	 * Enable output compare 1 (or its N counterpart). Note that if only
-	 * OC1N is enabled, then it is not complemented. From datasheet:
-	 * "When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented"
-	 *
-	 * Note: we want the rising edge of SDA to be in the middle of SCL, so
-	 * invert the SDA (faster) signal.
-	 */
-	if (ite_dfu_config.use_complement_timer_channel) {
-		STM32_TIM_CCER(16) = STM32_TIM_CCER_CC1NE;
-		STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1NE |
-				     STM32_TIM_CCER_CC1NP;
-	} else {
-		STM32_TIM_CCER(16) = STM32_TIM_CCER_CC1E;
-		STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P;
-	}
-
-	/* Enable main output. */
-	STM32_TIM_BDTR(16) = STM32_TIM_BDTR_MOE;
-	STM32_TIM_BDTR(17) = STM32_TIM_BDTR_MOE;
-
-	/* Update generation (reinitialize counters). */
-	STM32_TIM_EGR(16) = STM32_TIM_EGR_UG;
-	STM32_TIM_EGR(17) = STM32_TIM_EGR_UG;
-
-	/* Set duty cycle to 0% or 100%, pinning each channel low or high. */
-	STM32_TIM_CCR1(16) = SMCLK_PRE_LEVEL ? 0xFFFF : 0x0000;
-	STM32_TIM_CCR1(17) = SMDAT_PRE_LEVEL ? 0xFFFF : 0x0000;
-
-	/* Enable timer counters. */
-	STM32_TIM_CR1(16) = STM32_TIM_CR1_CEN;
-	STM32_TIM_CR1(17) = STM32_TIM_CR1_CEN;
-
-	/* Set GPIO to alternate mode TIM(16|17)_CH1(N)? */
-	gpio_config_pin(MODULE_I2C_TIMERS, ite_dfu_config.scl, 1);
-	gpio_config_pin(MODULE_I2C_TIMERS, ite_dfu_config.sda, 1);
-
-	msleep(START_DELAY_MS);
-
-	/* Set pulse width to half of waveform period. */
-	STM32_TIM_CCR1(16) = (MHz / SMCLK_WAVEFORM_PERIOD_HZ) / 2;
-	STM32_TIM_CCR1(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) / 2;
-
-	msleep(SPECIAL_WAVEFORM_MS);
-
-	/* Set duty cycle to 0% or 100%, pinning each channel low or high. */
-	STM32_TIM_CCR1(16) = SMCLK_POST_LEVEL ? 0xFFFF : 0x0000;
-	STM32_TIM_CCR1(17) = SMDAT_POST_LEVEL ? 0xFFFF : 0x0000;
-
-	msleep(PLL_STABLE_MS);
-
-	/* Set GPIO back to alternate mode I2C. */
-	gpio_config_pin(MODULE_I2C, ite_dfu_config.scl, 1);
-	gpio_config_pin(MODULE_I2C, ite_dfu_config.sda, 1);
-
-	/* Disable timer counters. */
-	STM32_TIM_CR1(16) = 0x0000;
-	STM32_TIM_CR1(17) = 0x0000;
-
-	/* Disable peripheral clocks. */
-	STM32_RCC_APB2ENR &=
-		~(STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN);
-
-	return cprint_ite_chip_id();
-}
-DECLARE_CONSOLE_COMMAND(
-	enable_ite_dfu, command_enable_ite_dfu, "",
-	"Enable ITE Direct Firmware Update (DFU) mode");
-
-/* Read ITE chip ID.  Can be used to verify ITE DFU mode. */
-static int command_get_ite_chipid(int argc, char **argv)
-{
-	if (argc > 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Ensure we can perform the dfu operation */
-	if (ite_dfu_config.access_allow && !ite_dfu_config.access_allow())
-		return EC_ERROR_ACCESS_DENIED;
-
-	return cprint_ite_chip_id();
-}
-DECLARE_CONSOLE_COMMAND(
-	get_ite_chipid, command_get_ite_chipid, "",
-	"Read ITE EC chip ID, version, flash size (must be in DFU mode)");
diff --git a/chip/stm32/keyboard_raw.c b/chip/stm32/keyboard_raw.c
deleted file mode 100644
index 219676968a..0000000000
--- a/chip/stm32/keyboard_raw.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for STM32
- *
- * To make this code portable, we rely heavily on looping over the keyboard
- * input and output entries in the board's gpio_list[]. Each set of inputs or
- * outputs must be listed in consecutive, increasing order so that scan loops
- * can iterate beginning at KB_IN00 or KB_OUT00 for however many GPIOs are
- * utilized (KEYBOARD_ROWS or KEYBOARD_COLS_MAX).
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/* Mask of external interrupts on input lines */
-static unsigned int irq_mask;
-
-static const uint32_t kb_out_ports[] = { KB_OUT_PORT_LIST };
-
-static void set_irq_mask(void)
-{
-	int i;
-
-	for (i = GPIO_KB_IN00; i < GPIO_KB_IN00 + KEYBOARD_ROWS; i++)
-		irq_mask |= gpio_list[i].mask;
-}
-
-void keyboard_raw_init(void)
-{
-	/* Determine EXTI_PR mask to use for the board */
-	set_irq_mask();
-
-	/* Ensure interrupts are disabled in EXTI_PR */
-	keyboard_raw_enable_interrupt(0);
-}
-
-void keyboard_raw_task_start(void)
-{
-	/* Enable interrupts for keyboard matrix inputs */
-	gpio_enable_interrupt(GPIO_KB_IN00);
-	gpio_enable_interrupt(GPIO_KB_IN01);
-	gpio_enable_interrupt(GPIO_KB_IN02);
-	gpio_enable_interrupt(GPIO_KB_IN03);
-	gpio_enable_interrupt(GPIO_KB_IN04);
-	gpio_enable_interrupt(GPIO_KB_IN05);
-	gpio_enable_interrupt(GPIO_KB_IN06);
-	gpio_enable_interrupt(GPIO_KB_IN07);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	int i, done = 0;
-
-	for (i = 0; i < ARRAY_SIZE(kb_out_ports); i++) {
-		uint32_t bsrr = 0;
-		int j;
-
-		for (j = GPIO_KB_OUT00; j <= GPIO_KB_OUT12; j++) {
-			if (gpio_list[j].port != kb_out_ports[i])
-				continue;
-
-			if (out == KEYBOARD_COLUMN_ALL) {
-				/* drive low (clear bit) */
-				bsrr |= gpio_list[j].mask << 16;
-			} else if (out == KEYBOARD_COLUMN_NONE) {
-				/* put output in hi-Z state (set bit) */
-				bsrr |= gpio_list[j].mask;
-			} else if (j - GPIO_KB_OUT00 == out) {
-				/*
-				 * Drive specified output low, others => hi-Z.
-				 *
-				 * To avoid conflict, tri-state all outputs
-				 * first, then assert specified output.
-				 */
-				keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
-				bsrr |= gpio_list[j].mask << 16;
-				done = 1;
-				break;
-			}
-		}
-
-	#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		if (bsrr & (gpio_list[GPIO_KB_OUT02].mask << 16 |
-				 gpio_list[GPIO_KB_OUT02].mask))
-			bsrr ^= (gpio_list[GPIO_KB_OUT02].mask << 16 |
-				 gpio_list[GPIO_KB_OUT02].mask);
-	#endif
-
-		if (bsrr)
-			STM32_GPIO_BSRR(kb_out_ports[i]) = bsrr;
-
-		if (done)
-			break;
-	}
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	int i;
-	unsigned int port, prev_port = 0;
-	int state = 0;
-	uint16_t port_val = 0;
-
-	for (i = 0; i < KEYBOARD_ROWS; i++) {
-		port = gpio_list[GPIO_KB_IN00 + i].port;
-		if (port != prev_port) {
-			port_val = STM32_GPIO_IDR(port);
-			prev_port = port;
-		}
-
-		if (port_val & gpio_list[GPIO_KB_IN00 + i].mask)
-			state |= 1 << i;
-	}
-
-	/* Invert it so 0=not pressed, 1=pressed */
-	return state ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/*
-		 * Assert all outputs would trigger un-wanted interrupts.
-		 * Clear them before enable interrupt.
-		 */
-		STM32_EXTI_PR |= irq_mask;
-		STM32_EXTI_IMR |= irq_mask;	/* 1: unmask interrupt */
-	} else {
-		STM32_EXTI_IMR &= ~irq_mask;	/* 0: mask interrupts */
-	}
-}
-
-void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_KEYSCAN);
-}
diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc
deleted file mode 100644
index 2381c511f2..0000000000
--- a/chip/stm32/memory_regions.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifdef CONFIG_USB_RAM_SIZE
-REGION(usb_ram, rw, CONFIG_USB_RAM_BASE, \
-       CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2)
-#endif /* CONFIG_USB_RAM_SIZE */
-#ifdef CHIP_VARIANT_STM32H7X3
-REGION(itcm,   wx, 0x00000000, 0x10000) /* CPU ITCM: 64kB */
-REGION(dtcm,   rw, 0x20000000, 0x20000) /* CPU DTCM: 128kB */
-REGION(ahb,    rw, 0x30000000, 0x48000) /* AHB-SRAM1-3: 288 kB */
-REGION(ahb4,   rw, 0x38000000, 0x10000) /* AHB-SRAM4: 64kB */
-REGION(backup, rw, 0x38800000, 0x01000) /* Backup RAM: 4kB */
-#endif /* CHIP_VARIANT_STM32H7X3 */
diff --git a/chip/stm32/otp-stm32f4.c b/chip/stm32/otp-stm32f4.c
deleted file mode 100644
index 45ce38d159..0000000000
--- a/chip/stm32/otp-stm32f4.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* OTP implementation for STM32F411 */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "otp.h"
-#include "registers.h"
-#include "util.h"
-
-/*
- * OTP is only used for saving the USB serial number.
- */
-#ifdef CONFIG_SERIALNO_LEN
-/* Which block to use */
-#define OTP_SERIAL_BLOCK 0
-#define OTP_SERIAL_ADDR \
-	REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0))
-
-/* Number of word used in the block */
-#define OTP_SERIAL_BLOCK_SIZE (CONFIG_SERIALNO_LEN / sizeof(uint32_t))
-BUILD_ASSERT(CONFIG_SERIALNO_LEN % sizeof(uint32_t) == 0);
-BUILD_ASSERT(OTP_SERIAL_BLOCK_SIZE < STM32_OTP_BLOCK_SIZE);
-
-/*
- * Write an OTP block
- *
- * @param block         block to write.
- * @param size          Number of words to write.
- * @param data          Destination buffer for data.
- */
-static int otp_write(uint8_t block, int size, const char *data)
-{
-	if (block >= STM32_OTP_BLOCK_NB)
-		return EC_ERROR_PARAM1;
-	if (size >= STM32_OTP_BLOCK_SIZE)
-		return EC_ERROR_PARAM2;
-	return crec_flash_physical_write(STM32_OTP_BLOCK_DATA(block, 0) -
-					 CONFIG_PROGRAM_MEMORY_BASE,
-					 size * sizeof(uint32_t), data);
-}
-
-/*
- * Check if an OTP block is protected.
- *
- * @param block        protected block.
- * @return non-zero if that block is read only.
- */
-static int otp_get_protect(uint8_t block)
-{
-	uint32_t lock;
-
-	lock = REG32(STM32_OTP_LOCK(block));
-	return ((lock & STM32_OPT_LOCK_MASK(block)) == 0);
-}
-
-/*
- * Set a particular OTP block as read only.
- *
- * @param block        block to protect.
- */
-static int otp_set_protect(uint8_t block)
-{
-	int rv;
-	uint32_t lock;
-
-	if (otp_get_protect(block))
-		return EC_SUCCESS;
-
-	lock = REG32(STM32_OTP_LOCK(block));
-	lock &= ~STM32_OPT_LOCK_MASK(block);
-	rv = crec_flash_physical_write(STM32_OTP_LOCK(block) -
-				       CONFIG_PROGRAM_MEMORY_BASE,
-				       sizeof(uint32_t), (char *)&lock);
-	if (rv)
-		return rv;
-	else
-		return EC_SUCCESS;
-}
-
-const char *otp_read_serial(void)
-{
-	int i;
-
-	for (i = 0; i < OTP_SERIAL_BLOCK_SIZE; i++) {
-		if (OTP_SERIAL_ADDR[i] != -1)
-			return (char *)OTP_SERIAL_ADDR;
-	}
-	return NULL;
-}
-
-int otp_write_serial(const char *serialno)
-{
-	int i, ret;
-	char otp_serial[CONFIG_SERIALNO_LEN];
-
-	if (otp_get_protect(OTP_SERIAL_BLOCK))
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Copy in serialno. */
-	for (i = 0; i < CONFIG_SERIALNO_LEN - 1; i++) {
-		otp_serial[i] = serialno[i];
-		if (serialno[i] == 0)
-			break;
-	}
-	for (; i < CONFIG_SERIALNO_LEN; i++)
-		otp_serial[i] = 0;
-
-	ret = otp_write(OTP_SERIAL_BLOCK, OTP_SERIAL_BLOCK_SIZE, otp_serial);
-	if (ret == EC_SUCCESS)
-		return otp_set_protect(OTP_SERIAL_BLOCK);
-	else
-		return ret;
-}
-#endif
diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c
deleted file mode 100644
index 508745199f..0000000000
--- a/chip/stm32/power_led.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Keyboard power button LED state machine.
- *
- * This sets up TIM_POWER_LED to drive the power button LED so that the duty
- * cycle can range from 0-100%. When the lid is closed or turned off, then the
- * PWM is disabled and the GPIO is reconfigured to minimize leakage voltage.
- *
- * In suspend mode, duty cycle transitions progressively slower from 0%
- * to 100%, and progressively faster from 100% back down to 0%. This
- * results in a breathing effect. It takes about 2sec for a full cycle.
- */
-
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "power_led.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define LED_STATE_TIMEOUT_MIN	(15 * MSEC)  /* Minimum of 15ms per step */
-#define LED_HOLD_TIME		(330 * MSEC) /* Hold for 330ms at min/max */
-#define LED_STEP_PERCENT	4	/* Incremental value of each step */
-
-static enum powerled_state led_state = POWERLED_STATE_ON;
-static int power_led_percent = 100;
-
-void powerled_set_state(enum powerled_state new_state)
-{
-	led_state = new_state;
-	/* Wake up the task */
-	task_wake(TASK_ID_POWERLED);
-}
-
-static void power_led_set_duty(int percent)
-{
-	ASSERT((percent >= 0) && (percent <= 100));
-	power_led_percent = percent;
-	pwm_set_duty(PWM_CH_POWER_LED, percent);
-}
-
-static void power_led_use_pwm(void)
-{
-	pwm_enable(PWM_CH_POWER_LED, 1);
-	power_led_set_duty(100);
-}
-
-static void power_led_manual_off(void)
-{
-	pwm_enable(PWM_CH_POWER_LED, 0);
-
-	/*
-	 * Reconfigure GPIO as a floating input. Alternatively we could
-	 * configure it as an open-drain output and set it to high impedance,
-	 * but reconfiguring as an input had better results in testing.
-	 */
-	gpio_config_module(MODULE_POWER_LED, 0);
-}
-
-/**
- * Return the timeout period (in us) for the current step.
- */
-static int power_led_step(void)
-{
-	int state_timeout = 0;
-	static enum { DOWN = -1, UP = 1 } dir = UP;
-
-	if (0 == power_led_percent) {
-		dir = UP;
-		state_timeout = LED_HOLD_TIME;
-	} else if (100 == power_led_percent) {
-		dir = DOWN;
-		state_timeout = LED_HOLD_TIME;
-	} else {
-		/*
-		 * Decreases timeout as duty cycle percentage approaches
-		 * 0%, increase as it approaches 100%.
-		 */
-		state_timeout = LED_STATE_TIMEOUT_MIN +
-			LED_STATE_TIMEOUT_MIN * (power_led_percent / 33);
-	}
-
-	/*
-	 * The next duty cycle will take effect after the timeout has
-	 * elapsed for this duty cycle and the power LED task calls this
-	 * function again.
-	 */
-	power_led_set_duty(power_led_percent);
-	power_led_percent += dir * LED_STEP_PERCENT;
-
-	return state_timeout;
-}
-
-void power_led_task(void)
-{
-	while (1) {
-		int state_timeout = -1;
-
-		switch (led_state) {
-		case POWERLED_STATE_ON:
-			/*
-			 * "ON" implies driving the LED using the PWM with a
-			 * duty duty cycle of 100%. This produces a softer
-			 * brightness than setting the GPIO to solid ON.
-			 */
-			power_led_use_pwm();
-			power_led_set_duty(100);
-			state_timeout = -1;
-			break;
-		case POWERLED_STATE_OFF:
-			/* Reconfigure GPIO to disable the LED */
-			power_led_manual_off();
-			state_timeout = -1;
-			break;
-		case POWERLED_STATE_SUSPEND:
-			/* Drive using PWM with variable duty cycle */
-			power_led_use_pwm();
-			state_timeout = power_led_step();
-			break;
-		default:
-			break;
-		}
-
-		task_wait_event(state_timeout);
-	}
-}
-
-#define CONFIG_CMD_POWERLED
-#ifdef CONFIG_CMD_POWERLED
-static int command_powerled(int argc, char **argv)
-{
-	enum powerled_state state;
-
-	if (argc != 2)
-		return EC_ERROR_INVAL;
-
-	if (!strcasecmp(argv[1], "off"))
-		state = POWERLED_STATE_OFF;
-	else if (!strcasecmp(argv[1], "on"))
-		state = POWERLED_STATE_ON;
-	else if (!strcasecmp(argv[1], "suspend"))
-		state = POWERLED_STATE_SUSPEND;
-	else
-		return EC_ERROR_INVAL;
-
-	powerled_set_state(state);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(powerled, command_powerled,
-		"[off | on | suspend]",
-		"Change power LED state");
-#endif
diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c
deleted file mode 100644
index 0b339399c9..0000000000
--- a/chip/stm32/pwm.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for STM32 */
-
-#include "clock.h"
-#include "clock-f.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "util.h"
-
-/* Bitmap of currently active PWM channels. 1 bit per channel. */
-static uint32_t using_pwm;
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	const struct pwm_t *pwm = pwm_channels + ch;
-	timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
-
-	ASSERT((percent >= 0) && (percent <= 100));
-	tim->ccr[pwm->channel] = percent;
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	const struct pwm_t *pwm = pwm_channels + ch;
-	timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
-	return tim->ccr[pwm->channel];
-}
-
-static void pwm_configure(enum pwm_channel ch)
-{
-	const struct pwm_t *pwm = pwm_channels + ch;
-	timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
-	volatile unsigned *ccmr = NULL;
-	/* Default frequency = 100 Hz */
-	int frequency = pwm->frequency ? pwm->frequency : 100;
-	uint16_t ccer;
-
-	if (using_pwm & BIT(ch))
-		return;
-
-	/* Enable timer */
-	__hw_timer_enable_clock(pwm->tim.id, 1);
-
-	/* Disable counter during setup */
-	tim->cr1 = 0x0000;
-
-	/*
-	 * Timer clock / PSC determines how fast the counter operates.
-	 * ARR determines the wave period, CCRn determines duty cycle.
-	 * Thus, frequency = timer_freq / PSC / ARR. so:
-	 *
-	 * frequency = timer_freq / (timer_freq/10000 + 1) / (99 + 1) = 100 Hz.
-	 */
-	tim->psc = clock_get_timer_freq() / (frequency * 100) - 1;
-	tim->arr = 99;
-
-	if (pwm->channel <= 2) /* Channel ID starts from 1 */
-		ccmr = &tim->ccmr1;
-	else
-		ccmr = &tim->ccmr2;
-
-	/* Output, PWM mode 1, preload enable */
-	if (pwm->channel & 0x1)
-		*ccmr = (6 << 4) | BIT(3);
-	else
-		*ccmr = (6 << 12) | BIT(11);
-
-	/* Output enable. Set active high/low. */
-	if (pwm->flags & PWM_CONFIG_ACTIVE_LOW)
-		ccer = 3 << (pwm->channel * 4 - 4);
-	else
-		ccer = 1 << (pwm->channel * 4 - 4);
-
-	/* Enable complementary output, if present. */
-	if (pwm->flags & PWM_CONFIG_COMPLEMENTARY_OUTPUT)
-		ccer |= (ccer << 2);
-
-	tim->ccer = ccer;
-
-	/*
-	 * Main output enable.
-	 * TODO(shawnn): BDTR is undocumented on STM32L. Verify this isn't
-	 * harmful on STM32L.
-	 */
-	tim->bdtr |= BIT(15);
-
-	/* Generate update event to force loading of shadow registers */
-	tim->egr |= 1;
-
-	/* Enable auto-reload preload, start counting */
-	tim->cr1 |= BIT(7) | BIT(0);
-
-	atomic_or(&using_pwm, 1 << ch);
-
-	/* Prevent sleep */
-	disable_sleep(SLEEP_MASK_PWM);
-}
-
-static void pwm_disable(enum pwm_channel ch)
-{
-	const struct pwm_t *pwm = pwm_channels + ch;
-	timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
-
-	if ((using_pwm & BIT(ch)) == 0)
-		return;
-
-	/* Main output disable */
-	tim->bdtr &= ~BIT(15);
-
-	/* Disable counter */
-	tim->cr1 &= ~0x1;
-
-	/* Disable timer clock */
-	__hw_timer_enable_clock(pwm->tim.id, 0);
-
-	/* Allow sleep */
-	enable_sleep(SLEEP_MASK_PWM);
-
-	atomic_clear_bits(&using_pwm, 1 << ch);
-
-	/* Unless another PWM is active... Then prevent sleep */
-	if (using_pwm)
-		disable_sleep(SLEEP_MASK_PWM);
-}
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	if (enabled)
-		pwm_configure(ch);
-	else
-		pwm_disable(ch);
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return using_pwm & BIT(ch);
-}
-
-static void pwm_reconfigure(enum pwm_channel ch)
-{
-	atomic_clear_bits(&using_pwm, 1 << ch);
-	pwm_configure(ch);
-}
-
-/**
- * Handle clock frequency change
- */
-static void pwm_freq_change(void)
-{
-	int i;
-	for (i = 0; i < PWM_CH_COUNT; ++i)
-		if (pwm_get_enabled(i))
-			pwm_reconfigure(i);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, pwm_freq_change, HOOK_PRIO_DEFAULT);
diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h
deleted file mode 100644
index baa793090a..0000000000
--- a/chip/stm32/pwm_chip.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32-specific PWM module for Chrome EC */
-
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/*
-	 * Timer powering the PWM channel. Must use STM32_TIM(x) to
-	 * initialize
-	 */
-	struct {
-		int id;
-		uintptr_t base;
-	} tim;
-	/* Channel ID within the timer */
-	int channel;
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-	/* PWM frequency (Hz) */
-	int frequency;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-/* Macro to fill in both timer ID and register base */
-#define STM32_TIM(x) {x, STM32_TIM_BASE(x)}
-
-/* Plain ID mapping for readability */
-#define STM32_TIM_CH(x) (x)
-
-#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/stm32/registers-stm32f0.h b/chip/stm32/registers-stm32f0.h
deleted file mode 100644
index ee4963777b..0000000000
--- a/chip/stm32/registers-stm32f0.h
+++ /dev/null
@@ -1,890 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32F0 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32F03X
- * - STM32F05X
- * - STM32F070
- * - STM32F07X
- * - STM32F09X
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_RTC_WAKEUP       2
-#define STM32_IRQ_RTC_ALARM        2
-#define STM32_IRQ_FLASH            3
-#define STM32_IRQ_RCC              4
-#define STM32_IRQ_EXTI0_1          5
-#define STM32_IRQ_EXTI2_3          6
-#define STM32_IRQ_EXTI4_15         7
-#define STM32_IRQ_TSC              8
-#define STM32_IRQ_DMA_CHANNEL_1    9
-#define STM32_IRQ_DMA_CHANNEL_2_3 10
-#define STM32_IRQ_DMA_CHANNEL_4_7 11
-#define STM32_IRQ_ADC_COMP        12
-#define STM32_IRQ_TIM1_BRK_UP_TRG 13
-#define STM32_IRQ_TIM1_CC         14
-#define STM32_IRQ_TIM2            15
-#define STM32_IRQ_TIM3            16
-#define STM32_IRQ_TIM6_DAC        17
-#define STM32_IRQ_TIM7            18
-#define STM32_IRQ_TIM14           19
-#define STM32_IRQ_TIM15           20
-#define STM32_IRQ_TIM16           21
-#define STM32_IRQ_TIM17           22
-#define STM32_IRQ_I2C1            23
-#define STM32_IRQ_I2C2            24
-#define STM32_IRQ_SPI1            25
-#define STM32_IRQ_SPI2            26
-#define STM32_IRQ_USART1          27
-#define STM32_IRQ_USART2          28
-#define STM32_IRQ_USART3_4        29
-#define STM32_IRQ_CEC_CAN         30
-#define STM32_IRQ_USB             31
-/* aliases for easier code sharing */
-#define STM32_IRQ_COMP STM32_IRQ_ADC_COMP
-#define STM32_IRQ_USB_LP STM32_IRQ_USB
-
-
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-#define STM32_COMP_BASE             0x40010000
-
-#define STM32_DBGMCU_BASE           0x40015800
-
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
-
-#define STM32_EXTI_BASE             0x40010400
-
-#define STM32_FLASH_REGS_BASE       0x40022000
-
-#define STM32_GPIOA_BASE            0x48000000
-#define STM32_GPIOB_BASE            0x48000400
-#define STM32_GPIOC_BASE            0x48000800
-#define STM32_GPIOD_BASE            0x48000C00
-#define STM32_GPIOE_BASE            0x48001000
-#define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800 /* only for stm32l4x6 */
-#define STM32_GPIOH_BASE            0x48001C00 /* only for stm32l4 */
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFF800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40021000
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40010000
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
-
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-/* --- GPIO --- */
-
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR                REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWD_PVD_LS_MASK       (0x07 << 5)
-#define STM32_PWD_PVD_LS(n)         ((n & 0x07) << 5)
-#define STM32_PWR_PVDE              BIT(4)
-
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-#define STM32_PWR_CSR_EWUP1         BIT(8)
-#define STM32_PWR_CSR_EWUP2         BIT(9)
-#define STM32_PWR_CSR_EWUP3         BIT(10)
-#define STM32_PWR_CSR_EWUP4         BIT(11) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP5         BIT(12) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP6         BIT(13) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP7         BIT(14) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP8         BIT(15) /* STM32F0xx only */
-
-#define STM32_CRS_CR                REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
-#define STM32_CRS_CR_SYNCOKIE           BIT(0)
-#define STM32_CRS_CR_SYNCWARNIE         BIT(1)
-#define STM32_CRS_CR_ERRIE              BIT(2)
-#define STM32_CRS_CR_ESYNCIE            BIT(3)
-#define STM32_CRS_CR_CEN                BIT(5)
-#define STM32_CRS_CR_AUTOTRIMEN         BIT(6)
-#define STM32_CRS_CR_SWSYNC             BIT(7)
-#define STM32_CRS_CR_TRIM(n)		(((n) & 0x3f) << 8)
-
-#define STM32_CRS_CFGR              REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
-#define STM32_CRS_CFGR_RELOAD(n)	(((n) & 0xffff) << 0)
-#define STM32_CRS_CFGR_FELIM(n)		(((n) & 0xff) << 16)
-#define STM32_CRS_CFGR_SYNCDIV(n)	(((n) & 7) << 24)
-#define STM32_CRS_CFGR_SYNCSRC(n)	(((n) & 3) << 28)
-#define STM32_CRS_CFGR_SYNCPOL		BIT(31)
-
-#define STM32_CRS_ISR               REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
-#define STM32_CRS_ISR_SYNCOKF		BIT(0)
-#define STM32_CRS_ISR_SYNCWARNF		BIT(1)
-#define STM32_CRS_ISR_ERRF		BIT(2)
-#define STM32_CRS_ISR_ESYNCF		BIT(3)
-#define STM32_CRS_ISR_SYNCERR		BIT(8)
-#define STM32_CRS_ISR_SYNCMISS		BIT(9)
-#define STM32_CRS_ISR_TRIMOVF		BIT(10)
-#define STM32_CRS_ISR_FEDIR		BIT(15)
-#define STM32_CRS_ISR_FECAP		(0xffff << 16)
-
-#define STM32_CRS_ICR               REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
-#define STM32_CRS_ICR_SYNCOKC		BIT(0)
-#define STM32_CRS_ICR_SYNCWARINC	BIT(1)
-#define STM32_CRS_ICR_ERRC		BIT(2)
-#define STM32_CRS_ICR_ESYNCC		BIT(3)
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x0c)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_APB2ENR_ADCEN     BIT(9) /* STM32F3/F0 */
-#define STM32_RCC_APB2ENR_TIM16EN   BIT(17)
-#define STM32_RCC_APB2ENR_TIM17EN   BIT(18)
-#define STM32_RCC_DBGMCUEN          BIT(22)
-#define STM32_RCC_SYSCFGEN          BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x1c)
-#define STM32_RCC_DACEN                 BIT(29)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x24)
-/* STM32F373 */
-#define STM32_RCC_CFGR2             REG32(STM32_RCC_BASE + 0x2c)
-/* STM32F0XX and STM32F373 */
-#define STM32_RCC_CFGR3             REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CR2               REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
-
-#define STM32_RCC_HB_DMA1		BIT(0)
-/* STM32F373 */
-#define STM32_RCC_HB_DMA2		BIT(1)
-#define STM32_RCC_PB2_TIM1		BIT(11) /* Except STM32F373 */
-#define STM32_RCC_PB2_TIM15		BIT(16) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM16		BIT(17) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM17		BIT(18) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM19		BIT(19) /* STM32F373 */
-#define STM32_RCC_PB2_PMAD		BIT(11) /* STM32TS */
-#define STM32_RCC_PB2_PMSE		BIT(13) /* STM32TS */
-#define STM32_RCC_PB1_TIM12		BIT(6)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM13		BIT(7)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM14		BIT(8)  /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB1_TIM18		BIT(9)  /* STM32F373 */
-#define STM32_RCC_PB1_USB		BIT(23)
-#define STM32_RCC_PB1_CRS		BIT(27)
-
-#define STM32_SYSCFG_CFGR1          REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CFGR2          REG32(STM32_SYSCFG_BASE + 0x18)
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE           STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR       STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             20
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-#define STM32_FLASH_ACR_PRFTEN      BIT(4)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             FLASH_KEYR_KEY1
-#define  FLASH_OPTKEYR_KEY2             FLASH_KEYR_KEY2
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_BUSY                  BIT(0)
-#define  FLASH_SR_PGERR                 BIT(2)
-#define  FLASH_SR_WRPRTERR              BIT(4)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
-#define  FLASH_SR_EOP                   BIT(5)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_OPTPG                 BIT(4)
-#define  FLASH_CR_OPTER                 BIT(5)
-#define  FLASH_CR_STRT                  BIT(6)
-#define  FLASH_CR_LOCK                  BIT(7)
-#define  FLASH_CR_OPTWRE                BIT(9)
-#define  FLASH_CR_OBL_LAUNCH            BIT(13)
-#define STM32_FLASH_OPT_LOCKED      (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
-#define STM32_FLASH_AR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_OBR_RDP_MASK        (3 << 1)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)           (0x08 + (n&3) * 2)
-#define STM32_OPTB_WRP01                0x08
-#define STM32_OPTB_WRP23                0x0c
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_PVD_EVENT              BIT(16)
-#define EXTI_RTC_ALR_EVENT          BIT(17)
-#define EXTI_COMP2_EVENT            BIT(22)
-
-/* --- ADC --- */
-#define STM32_ADC_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_ISR_ADRDY        BIT(0)
-#define STM32_ADC_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_IER_AWDIE        BIT(7)
-#define STM32_ADC_IER_OVRIE        BIT(4)
-#define STM32_ADC_IER_EOSEQIE      BIT(3)
-#define STM32_ADC_IER_EOCIE        BIT(2)
-#define STM32_ADC_IER_EOSMPIE      BIT(1)
-#define STM32_ADC_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR_ADEN          BIT(0)
-#define STM32_ADC_CR_ADDIS         BIT(1)
-#define STM32_ADC_CR_ADCAL         BIT(31)
-#define STM32_ADC_CFGR1            REG32(STM32_ADC1_BASE + 0x0C)
-/* Analog watchdog channel selection */
-#define STM32_ADC_CFGR1_AWDCH_MASK (0x1f << 26)
-#define STM32_ADC_CFGR1_AWDEN      BIT(23)
-#define STM32_ADC_CFGR1_AWDSGL     BIT(22)
-/* Selects single vs continuous */
-#define STM32_ADC_CFGR1_CONT       BIT(13)
-/* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC_CFGR1_OVRMOD     BIT(12)
-/* External trigger polarity selection */
-#define STM32_ADC_CFGR1_EXTEN_DIS  (0 << 10)
-#define STM32_ADC_CFGR1_EXTEN_RISE (1 << 10)
-#define STM32_ADC_CFGR1_EXTEN_FALL (2 << 10)
-#define STM32_ADC_CFGR1_EXTEN_BOTH (3 << 10)
-#define STM32_ADC_CFGR1_EXTEN_MASK (3 << 10)
-/* External trigger selection */
-#define STM32_ADC_CFGR1_TRG0	   (0 << 6)
-#define STM32_ADC_CFGR1_TRG1	   (1 << 6)
-#define STM32_ADC_CFGR1_TRG2	   (2 << 6)
-#define STM32_ADC_CFGR1_TRG3	   (3 << 6)
-#define STM32_ADC_CFGR1_TRG4	   (4 << 6)
-#define STM32_ADC_CFGR1_TRG5	   (5 << 6)
-#define STM32_ADC_CFGR1_TRG6	   (6 << 6)
-#define STM32_ADC_CFGR1_TRG7	   (7 << 6)
-#define STM32_ADC_CFGR1_TRG_MASK   (7 << 6)
-/* Selects circular vs one-shot */
-#define STM32_ADC_CFGR1_DMACFG     BIT(1)
-#define STM32_ADC_CFGR1_DMAEN      BIT(0)
-#define STM32_ADC_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC_SMPR             REG32(STM32_ADC1_BASE + 0x14)
-/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_CCR              REG32(STM32_ADC1_BASE + 0x308)
-
-/* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x1C)
-
-#define STM32_COMP_CMP2LOCK            BIT(31)
-#define STM32_COMP_CMP2OUT             BIT(30)
-#define STM32_COMP_CMP2HYST_HI         (3 << 28)
-#define STM32_COMP_CMP2HYST_MED        (2 << 28)
-#define STM32_COMP_CMP2HYST_LOW        (1 << 28)
-#define STM32_COMP_CMP2HYST_NO         (0 << 28)
-#define STM32_COMP_CMP2POL             BIT(27)
-
-#define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM2_OCR (5 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM2_IC4 (4 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24)
-#define STM32_COMP_CMP2OUTSEL_NONE     (0 << 24)
-#define STM32_COMP_WNDWEN              BIT(23)
-
-#define STM32_COMP_CMP2INSEL_MASK      (7 << 20)
-#define STM32_COMP_CMP2INSEL_INM7      (6 << 20) /* STM32F373 only */
-#define STM32_COMP_CMP2INSEL_INM6      (6 << 20)
-#define STM32_COMP_CMP2INSEL_INM5      (5 << 20)
-#define STM32_COMP_CMP2INSEL_INM4      (4 << 20)
-#define STM32_COMP_CMP2INSEL_VREF      (3 << 20)
-#define STM32_COMP_CMP2INSEL_VREF34    (2 << 20)
-#define STM32_COMP_CMP2INSEL_VREF12    (1 << 20)
-#define STM32_COMP_CMP2INSEL_VREF14    (0 << 20)
-
-#define STM32_COMP_CMP2MODE_VLSPEED    (3 << 18)
-#define STM32_COMP_CMP2MODE_LSPEED     (2 << 18)
-#define STM32_COMP_CMP2MODE_MSPEED     (1 << 18)
-#define STM32_COMP_CMP2MODE_HSPEED     (0 << 18)
-#define STM32_COMP_CMP2EN              BIT(16)
-
-#define STM32_COMP_CMP1LOCK            BIT(15)
-#define STM32_COMP_CMP1OUT             BIT(14)
-#define STM32_COMP_CMP1HYST_HI         (3 << 12)
-#define STM32_COMP_CMP1HYST_MED        (2 << 12)
-#define STM32_COMP_CMP1HYST_LOW        (1 << 12)
-#define STM32_COMP_CMP1HYST_NO         (0 << 12)
-#define STM32_COMP_CMP1POL             BIT(11)
-
-#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8)
-#define STM32_COMP_CMP1OUTSEL_NONE     (0 << 8)
-
-#define STM32_COMP_CMP1INSEL_MASK      (7 << 4)
-#define STM32_COMP_CMP1INSEL_INM7      (7 << 4) /* STM32F373 only */
-#define STM32_COMP_CMP1INSEL_INM6      (6 << 4)
-#define STM32_COMP_CMP1INSEL_INM5      (5 << 4)
-#define STM32_COMP_CMP1INSEL_INM4      (4 << 4)
-#define STM32_COMP_CMP1INSEL_VREF      (3 << 4)
-#define STM32_COMP_CMP1INSEL_VREF34    (2 << 4)
-#define STM32_COMP_CMP1INSEL_VREF12    (1 << 4)
-#define STM32_COMP_CMP1INSEL_VREF14    (0 << 4)
-
-#define STM32_COMP_CMP1MODE_VLSPEED    (3 << 2)
-#define STM32_COMP_CMP1MODE_LSPEED     (2 << 2)
-#define STM32_COMP_CMP1MODE_MSPEED     (1 << 2)
-#define STM32_COMP_CMP1MODE_HSPEED     (0 << 2)
-#define STM32_COMP_CMP1SW1             BIT(1)
-#define STM32_COMP_CMP1EN              BIT(0)
-
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-
-	/* Channel functions */
-	STM32_DMAC_ADC = STM32_DMAC_CH1,
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2,
-	STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3,
-	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
-	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH4,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH5,
-#if !defined(CHIP_VARIANT_STM32F03X) && !defined(CHIP_VARIANT_STM32F05X)
-	STM32_DMAC_USART2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_USART2_TX = STM32_DMAC_CH7,
-	STM32_DMAC_I2C1_TX = STM32_DMAC_CH6,
-	STM32_DMAC_I2C1_RX = STM32_DMAC_CH7,
-	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH7,
-
-	/* Only DMA1 (with 7 channels) is present on STM32L151x */
-	STM32_DMAC_COUNT = 7,
-
-#else /* stm32f03x and stm32f05x have only 5 channels */
-	STM32_DMAC_COUNT = 5,
-#endif
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-
-#ifdef CHIP_VARIANT_STM32F09X
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-#else
-#define STM32_DMA_REGS(channel) STM32_DMA1_REGS
-#endif
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f3.h b/chip/stm32/registers-stm32f3.h
deleted file mode 100644
index b7e3cfc8af..0000000000
--- a/chip/stm32/registers-stm32f3.h
+++ /dev/null
@@ -1,1013 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32F3 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32F373
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_IRQ_USB_HP          74
-#define STM32_IRQ_USB_LP          75
-#else
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-#endif
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_IRQ_COMP            64
-#else
-#define STM32_IRQ_COMP            22
-#endif
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-#define STM32_COMP_BASE             0x40010000
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
-
-#define STM32_EXTI_BASE             0x40010400
-
-#define STM32_FLASH_REGS_BASE       0x40022000
-
-#define STM32_GPIOA_BASE            0x48000000
-#define STM32_GPIOB_BASE            0x48000400
-#define STM32_GPIOC_BASE            0x48000800
-#define STM32_GPIOD_BASE            0x48000C00
-#define STM32_GPIOE_BASE            0x48001000
-#define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800 /* only for stm32l4x6 */
-#define STM32_GPIOH_BASE            0x48001C00 /* only for stm32l4 */
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFF800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40021000
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40010000
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
-
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-/* --- GPIO --- */
-
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-#define STM32_PWR_CSR_EWUP1         BIT(8)
-#define STM32_PWR_CSR_EWUP2         BIT(9)
-#define STM32_PWR_CSR_EWUP3         BIT(10)
-#define STM32_PWR_CSR_EWUP4         BIT(11) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP5         BIT(12) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP6         BIT(13) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP7         BIT(14) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP8         BIT(15) /* STM32F0xx only */
-
-#define STM32_CRS_CR                REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
-#define STM32_CRS_CR_SYNCOKIE           BIT(0)
-#define STM32_CRS_CR_SYNCWARNIE         BIT(1)
-#define STM32_CRS_CR_ERRIE              BIT(2)
-#define STM32_CRS_CR_ESYNCIE            BIT(3)
-#define STM32_CRS_CR_CEN                BIT(5)
-#define STM32_CRS_CR_AUTOTRIMEN         BIT(6)
-#define STM32_CRS_CR_SWSYNC             BIT(7)
-#define STM32_CRS_CR_TRIM(n)		(((n) & 0x3f) << 8)
-
-#define STM32_CRS_CFGR              REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
-#define STM32_CRS_CFGR_RELOAD(n)	(((n) & 0xffff) << 0)
-#define STM32_CRS_CFGR_FELIM(n)		(((n) & 0xff) << 16)
-#define STM32_CRS_CFGR_SYNCDIV(n)	(((n) & 7) << 24)
-#define STM32_CRS_CFGR_SYNCSRC(n)	(((n) & 3) << 28)
-#define STM32_CRS_CFGR_SYNCPOL		BIT(31)
-
-#define STM32_CRS_ISR               REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
-#define STM32_CRS_ISR_SYNCOKF		BIT(0)
-#define STM32_CRS_ISR_SYNCWARNF		BIT(1)
-#define STM32_CRS_ISR_ERRF		BIT(2)
-#define STM32_CRS_ISR_ESYNCF		BIT(3)
-#define STM32_CRS_ISR_SYNCERR		BIT(8)
-#define STM32_CRS_ISR_SYNCMISS		BIT(9)
-#define STM32_CRS_ISR_TRIMOVF		BIT(10)
-#define STM32_CRS_ISR_FEDIR		BIT(15)
-#define STM32_CRS_ISR_FECAP		(0xffff << 16)
-
-#define STM32_CRS_ICR               REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
-#define STM32_CRS_ICR_SYNCOKC		BIT(0)
-#define STM32_CRS_ICR_SYNCWARINC	BIT(1)
-#define STM32_CRS_ICR_ERRC		BIT(2)
-#define STM32_CRS_ICR_ESYNCC		BIT(3)
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x0c)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_APB2ENR_ADCEN     BIT(9) /* STM32F3/F0 */
-#define STM32_RCC_APB2ENR_TIM16EN   BIT(17)
-#define STM32_RCC_APB2ENR_TIM17EN   BIT(18)
-#define STM32_RCC_DBGMCUEN          BIT(22)
-#define STM32_RCC_SYSCFGEN          BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x1c)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x24)
-/* STM32F373 */
-#define STM32_RCC_CFGR2             REG32(STM32_RCC_BASE + 0x2c)
-/* STM32F0XX and STM32F373 */
-#define STM32_RCC_CFGR3             REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CR2               REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
-
-#define STM32_RCC_HB_DMA1		BIT(0)
-/* STM32F373 */
-#define STM32_RCC_HB_DMA2		BIT(1)
-#define STM32_RCC_PB2_TIM1		BIT(11) /* Except STM32F373 */
-#define STM32_RCC_PB2_TIM15		BIT(16) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM16		BIT(17) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM17		BIT(18) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM19		BIT(19) /* STM32F373 */
-#define STM32_RCC_PB2_PMAD		BIT(11) /* STM32TS */
-#define STM32_RCC_PB2_PMSE		BIT(13) /* STM32TS */
-#define STM32_RCC_PB1_TIM12		BIT(6)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM13		BIT(7)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM14		BIT(8)  /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB1_TIM18		BIT(9)  /* STM32F373 */
-#define STM32_RCC_PB1_USB		BIT(23)
-#define STM32_RCC_PB1_CRS		BIT(27)
-
-#define STM32_SYSCFG_CFGR1          REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CFGR2          REG32(STM32_SYSCFG_BASE + 0x18)
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             64
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-#define STM32_FLASH_ACR_PRFTEN      BIT(4)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             FLASH_KEYR_KEY1
-#define  FLASH_OPTKEYR_KEY2             FLASH_KEYR_KEY2
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_BUSY                  BIT(0)
-#define  FLASH_SR_PGERR                 BIT(2)
-#define  FLASH_SR_WRPRTERR              BIT(4)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
-#define  FLASH_SR_EOP                   BIT(5)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_OPTPG                 BIT(4)
-#define  FLASH_CR_OPTER                 BIT(5)
-#define  FLASH_CR_STRT                  BIT(6)
-#define  FLASH_CR_LOCK                  BIT(7)
-#define  FLASH_CR_OPTWRE                BIT(9)
-#define  FLASH_CR_OBL_LAUNCH            BIT(13)
-#define STM32_FLASH_OPT_LOCKED      (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
-#define STM32_FLASH_AR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_OBR_RDP_MASK        (3 << 1)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)           (0x08 + (n&3) * 2)
-#define STM32_OPTB_WRP01                0x08
-#define STM32_OPTB_WRP23                0x0c
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT BIT(17)
-
-/* --- ADC --- */
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
-#endif
-
-/* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x1C)
-
-#define STM32_COMP_CMP2LOCK            BIT(31)
-#define STM32_COMP_CMP2OUT             BIT(30)
-#define STM32_COMP_CMP2HYST_HI         (3 << 28)
-#define STM32_COMP_CMP2HYST_MED        (2 << 28)
-#define STM32_COMP_CMP2HYST_LOW        (1 << 28)
-#define STM32_COMP_CMP2HYST_NO         (0 << 28)
-#define STM32_COMP_CMP2POL             BIT(27)
-
-#define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM2_OCR (5 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM2_IC4 (4 << 24)
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_COMP_CMP2OUTSEL_TIM4_OCR (3 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM4_IC1 (2 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM16_BRK (1 << 24)
-#else
-#define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24)
-#endif
-#define STM32_COMP_CMP2OUTSEL_NONE     (0 << 24)
-#define STM32_COMP_WNDWEN              BIT(23)
-
-#define STM32_COMP_CMP2INSEL_MASK      (7 << 20)
-#define STM32_COMP_CMP2INSEL_INM7      (6 << 20) /* STM32F373 only */
-#define STM32_COMP_CMP2INSEL_INM6      (6 << 20)
-#define STM32_COMP_CMP2INSEL_INM5      (5 << 20)
-#define STM32_COMP_CMP2INSEL_INM4      (4 << 20)
-#define STM32_COMP_CMP2INSEL_VREF      (3 << 20)
-#define STM32_COMP_CMP2INSEL_VREF34    (2 << 20)
-#define STM32_COMP_CMP2INSEL_VREF12    (1 << 20)
-#define STM32_COMP_CMP2INSEL_VREF14    (0 << 20)
-
-#define STM32_COMP_CMP2MODE_VLSPEED    (3 << 18)
-#define STM32_COMP_CMP2MODE_LSPEED     (2 << 18)
-#define STM32_COMP_CMP2MODE_MSPEED     (1 << 18)
-#define STM32_COMP_CMP2MODE_HSPEED     (0 << 18)
-#define STM32_COMP_CMP2EN              BIT(16)
-
-#define STM32_COMP_CMP1LOCK            BIT(15)
-#define STM32_COMP_CMP1OUT             BIT(14)
-#define STM32_COMP_CMP1HYST_HI         (3 << 12)
-#define STM32_COMP_CMP1HYST_MED        (2 << 12)
-#define STM32_COMP_CMP1HYST_LOW        (1 << 12)
-#define STM32_COMP_CMP1HYST_NO         (0 << 12)
-#define STM32_COMP_CMP1POL             BIT(11)
-
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_COMP_CMP1OUTSEL_TIM5_OCR (7 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM5_IC4 (6 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (3 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (2 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM15_BRK (1 << 8)
-#else
-#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8)
-#endif
-#define STM32_COMP_CMP1OUTSEL_NONE     (0 << 8)
-
-#define STM32_COMP_CMP1INSEL_MASK      (7 << 4)
-#define STM32_COMP_CMP1INSEL_INM7      (7 << 4) /* STM32F373 only */
-#define STM32_COMP_CMP1INSEL_INM6      (6 << 4)
-#define STM32_COMP_CMP1INSEL_INM5      (5 << 4)
-#define STM32_COMP_CMP1INSEL_INM4      (4 << 4)
-#define STM32_COMP_CMP1INSEL_VREF      (3 << 4)
-#define STM32_COMP_CMP1INSEL_VREF34    (2 << 4)
-#define STM32_COMP_CMP1INSEL_VREF12    (1 << 4)
-#define STM32_COMP_CMP1INSEL_VREF14    (0 << 4)
-
-#define STM32_COMP_CMP1MODE_VLSPEED    (3 << 2)
-#define STM32_COMP_CMP1MODE_LSPEED     (2 << 2)
-#define STM32_COMP_CMP1MODE_MSPEED     (1 << 2)
-#define STM32_COMP_CMP1MODE_HSPEED     (0 << 2)
-#define STM32_COMP_CMP1SW1             BIT(1)
-#define STM32_COMP_CMP1EN              BIT(0)
-
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-
-	/* Channel functions */
-	STM32_DMAC_ADC = STM32_DMAC_CH1,
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2,
-	STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3,
-	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
-	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH4,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_USART2_TX = STM32_DMAC_CH7,
-	STM32_DMAC_I2C1_TX = STM32_DMAC_CH6,
-	STM32_DMAC_I2C1_RX = STM32_DMAC_CH7,
-	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
-#ifdef CHIP_VARIANT_STM32F373
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
-	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
-	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
-
-	STM32_DMAC_COUNT = 10,
-#else
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH7,
-
-	/* Only DMA1 (with 7 channels) is present on STM32L151x */
-	STM32_DMAC_COUNT = 7,
-#endif
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h
deleted file mode 100644
index 503a60cc64..0000000000
--- a/chip/stm32/registers-stm32f4.h
+++ /dev/null
@@ -1,1132 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32F4 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32F411
- * - STM32F412
- * - STM32F41X
- * - STM32F446
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#if defined(CHIP_VARIANT_STM32F412)
-#define STM32_IRQ_TIM9            24 /* STM32F412 only */
-#else
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#endif
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-#if defined(CHIP_VARIANT_STM32F411) || defined(CHIP_VARIANT_STM32F412)
-#define CHIP_VARIANT_STM32F41X
-#endif
-
-/*
- * STM32F4 introduces a concept of DMA stream to allow
- * fine allocation of a stream to a channel.
- */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012000
-#define STM32_ADC_BASE              0x40012300
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-#define STM32_DMA2_BASE             0x40026400
-
-#define STM32_EXTI_BASE             0x40013C00
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021400 /* see RM0402/0390 table 1 */
-#define STM32_GPIOG_BASE            0x40021800
-#define STM32_GPIOH_BASE            0x40021C00
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFC000
-#define STM32_OTP_BASE              0x1FFF7800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40013800
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40014000 /* STM32F41x only */
-#define STM32_TIM10_BASE            0x40014400 /* STM32F41x only */
-#define STM32_TIM11_BASE            0x40014800 /* STM32F41x only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1fff7a10
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-#define STM32_USART_DR(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_UE		BIT(13)
-#define STM32_USART_CR1_OVER8		BIT(15) /* STM32L only */
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11) /* STM32L only */
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x18)
-/* register aliases */
-#define STM32_USART_TDR(base)      STM32_USART_DR(base)
-#define STM32_USART_RDR(base)      STM32_USART_DR(base)
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-#define STM32_FMPI2C_CR1(n)        REG32(stm32_i2c_reg(n, 0x00))
-#define  FMPI2C_CR1_PE             BIT(0)
-#define  FMPI2C_CR1_TXDMAEN        BIT(14)
-#define  FMPI2C_CR1_RXDMAEN        BIT(15)
-#define STM32_FMPI2C_CR2(n)        REG32(stm32_i2c_reg(n, 0x04))
-#define  FMPI2C_CR2_RD_WRN         BIT(10)
-#define  FMPI2C_READ               1
-#define  FMPI2C_WRITE              0
-#define  FMPI2C_CR2_START          BIT(13)
-#define  FMPI2C_CR2_STOP           BIT(14)
-#define  FMPI2C_CR2_NACK           BIT(15)
-#define  FMPI2C_CR2_RELOAD         BIT(24)
-#define  FMPI2C_CR2_AUTOEND        BIT(25)
-#define  FMPI2C_CR2_SADD(addr)     ((addr) & 0x3ff)
-#define  FMPI2C_CR2_SADD_MASK      FMPI2C_CR2_SADD(0x3ff)
-#define  FMPI2C_CR2_SIZE(size)     (((size) & 0xff) << 16)
-#define  FMPI2C_CR2_SIZE_MASK      FMPI2C_CR2_SIZE(0xf)
-#define STM32_FMPI2C_OAR1(n)       REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_FMPI2C_OAR2(n)       REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_FMPI2C_TIMINGR(n)    REG32(stm32_i2c_reg(n, 0x10))
-#define  TIMINGR_THE_RIGHT_VALUE   0xC0000E12
-#define  FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28)
-#define  FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20)
-#define  FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16)
-#define  FMPI2C_TIMINGR_SCLH(val)  (((val) & 0xff) << 8)
-#define  FMPI2C_TIMINGR_SCLL(val)  (((val) & 0xff) << 0)
-#define STM32_FMPI2C_TIMEOUTR(n)   REG32(stm32_i2c_reg(n, 0x14))
-
-#define STM32_FMPI2C_ISR(n)        REG32(stm32_i2c_reg(n, 0x18))
-#define  FMPI2C_ISR_TXE            BIT(0)
-#define  FMPI2C_ISR_TXIS           BIT(1)
-#define  FMPI2C_ISR_RXNE           BIT(2)
-#define  FMPI2C_ISR_ADDR           BIT(3)
-#define  FMPI2C_ISR_NACKF          BIT(4)
-#define  FMPI2C_ISR_STOPF          BIT(5)
-#define  FMPI2C_ISR_BERR           BIT(8)
-#define  FMPI2C_ISR_ARLO           BIT(9)
-#define  FMPI2C_ISR_BUSY           BIT(15)
-#define STM32_FMPI2C_ICR(n)        REG32(stm32_i2c_reg(n, 0x1C))
-
-#define STM32_FMPI2C_PECR(n)       REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_FMPI2C_RXDR(n)       REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_FMPI2C_TXDR(n)       REG32(stm32_i2c_reg(n, 0x28))
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-
-#if defined(CHIP_VARIANT_STM32F446)
-/* Required or recommended clocks for stm32f446 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  42000000
-#define STM32F4_USB_REQ 48000000
-#define STM32F4_VCO_CLOCK 336000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK
-#define STM32F4_PLLP_DIV 4
-#define STM32F4_AHB_PRE 0x8
-#define STM32F4_APB1_PRE 0x0
-#define STM32F4_APB2_PRE 0x0
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW      0
-
-#elif defined(CHIP_VARIANT_STM32F412)
-/* Required or recommended clocks for stm32f412 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  48000000
-#define STM32F4_USB_REQ 48000000
-#define STM32F4_VCO_CLOCK 384000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 4
-#define STM32F4_AHB_PRE 0x0
-#define STM32F4_APB1_PRE 0x4
-#define STM32F4_APB2_PRE 0x4
-#define STM32_FLASH_ACR_LATENCY     (3 << 0)
-/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW      0
-
-#elif defined(CHIP_VARIANT_STM32F411)
-/* Required or recommended clocks for stm32f411 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  48000000
-#define STM32F4_USB_REQ 48000000
-#define STM32F4_VCO_CLOCK 384000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK
-#define STM32F4_PLLP_DIV 4
-#define STM32F4_AHB_PRE 0x8
-#define STM32F4_APB1_PRE 0x0
-#define STM32F4_APB2_PRE 0x0
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW    0
-
-#elif defined(CHIP_VARIANT_STM32F76X)
-/* Required or recommended clocks for stm32f767/769 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK 45000000
-#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */
-#define STM32F4_VCO_CLOCK 360000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 2   /* sys = VCO/2  = 180 Mhz */
-#define STM32F4_AHB_PRE 0x0  /* AHB = sysclk = 180 Mhz */
-#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */
-#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */
-#define STM32_FLASH_ACR_LATENCY     (5 << 0)
-/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW      0
-
-#else
-#error "No valid clocks defined"
-#endif
-
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x04)
-/* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		0
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
-/* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		6
-#define  PLLCFGR_PLLN(val)		(((val) & 0x1ff) << PLLCFGR_PLLN_OFF)
-/* Main CPU Clock */
-#define  PLLCFGR_PLLP_OFF		16
-#define  PLLCFGR_PLLP(val)		(((val) & 0x3) << PLLCFGR_PLLP_OFF)
-
-#define  PLLCFGR_PLLSRC_HSI		(0 << 22)
-#define  PLLCFGR_PLLSRC_HSE		BIT(22)
-/* USB OTG FS: Must equal 48MHz */
-#define  PLLCFGR_PLLQ_OFF		24
-#define  PLLCFGR_PLLQ(val)		(((val) & 0xf) << PLLCFGR_PLLQ_OFF)
-/* SYSTEM */
-#define  PLLCFGR_PLLR_OFF		28
-#define  PLLCFGR_PLLR(val)		(((val) & 0x7) << PLLCFGR_PLLR_OFF)
-
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_HSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(1 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL_R		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(1 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL_R	(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-/* AHB Prescalar: nonlinear values, look up in RM0390 */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
-/* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			10
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
-/* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			13
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
-/* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
-
-#define STM32_RCC_CIR                   REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x10)
-#define  RCC_AHB1RSTR_OTGHSRST		BIT(29)
-
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x18)
-
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x24)
-
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_AHB1ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB1ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB1ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB1ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB1ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB1ENR_GPIO_PORTF	BIT(5)
-#define STM32_RCC_AHB1ENR_GPIO_PORTG	BIT(6)
-#define STM32_RCC_AHB1ENR_GPIO_PORTH	BIT(7)
-#define STM32_RCC_AHB1ENR_GPIOMASK	(0xff << 0)
-#define STM32_RCC_AHB1ENR_BKPSRAMEN	BIT(18)
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(21)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(22)
-
-/* TODO(nsanders): normalize naming.*/
-#define STM32_RCC_HB1_DMA1		BIT(21)
-#define STM32_RCC_HB1_DMA2		BIT(22)
-#define STM32_RCC_AHB1ENR_OTGHSEN	BIT(29)
-#define STM32_RCC_AHB1ENR_OTGHSULPIEN	BIT(30)
-
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(6)
-#define STM32_RCC_AHB2ENR_OTGFSEN	BIT(7)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x38)
-
-#define STM32_RCC_APB1ENR               REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_PWREN                 BIT(28)
-#define STM32_RCC_I2C1EN                BIT(21)
-#define STM32_RCC_I2C2EN                BIT(22)
-#define STM32_RCC_I2C3EN                BIT(23)
-#define STM32_RCC_FMPI2C4EN             BIT(24)
-
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_APB2ENR_ADC1EN        BIT(8) /* STM32F4 */
-
-#define STM32_RCC_PB2_USART6            BIT(5)
-#define STM32_RCC_SYSCFGEN		BIT(14)
-
-#define STM32_RCC_AHB1LPENR             REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_AHB2LPENR             REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_AHB3LPENR             REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1LPENR             REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_APB2LPENR             REG32(STM32_RCC_BASE + 0x64)
-
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-#define STM32_RCC_PB2_TIM1		BIT(0)
-#define STM32_RCC_PB2_TIM8		BIT(1)
-#define STM32_RCC_PB2_TIM9		BIT(16)
-#define STM32_RCC_PB2_TIM10		BIT(17)
-#define STM32_RCC_PB2_TIM11		BIT(18)
-
-#define STM32_RCC_DCKCFGR2              REG32(STM32_RCC_BASE + 0x94)
-#define  DCKCFGR2_FMPI2C1SEL(val)       (((val) & 0x3) << 22)
-#define  DCKCFGR2_FMPI2C1SEL_MASK       (0x3 << 22)
-#define  FMPI2C1SEL_APB                 0x0
-
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
-
-/* Peripheral bits for RCC_APB/AHB regs */
-#define STM32_RCC_PB2_USART1		BIT(4)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                (BIT(30)|BIT(29))
-#define  RESET_CAUSE_SFT                BIT(28)
-#define  RESET_CAUSE_POR                BIT(27)
-#define  RESET_CAUSE_PIN                BIT(26)
-#define  RESET_CAUSE_OTHER              (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \
-					 BIT(27)|BIT(26)|BIT(25))
-#define  RESET_CAUSE_RMVF                BIT(24)
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define  RESET_CAUSE_SBF                BIT(1)
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF_CLR            BIT(3)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-
-/* --- Debug --- */
-
-#define  STM32_DBGMCU_CR_SLEEP                      BIT(0)
-#define  STM32_DBGMCU_CR_STOP                       BIT(1)
-#define  STM32_DBGMCU_CR_STBY                       BIT(2)
-#define  STM32_DBGMCU_CR_TRACE_MASK                 (BIT(5)|BIT(6)|BIT(7))
-#define   STM32_DBGMCU_CR_TRACE_EN                   BIT(5)
-#define   STM32_DBGMCU_CR_TRACE_MODE_ASYNC           0
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC1           BIT(6)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC2           BIT(7)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC4           (BIT(6)|BIT(7))
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define  STM32_DBGMCU_APB1FZ_TIM2                   BIT(0)
-#define  STM32_DBGMCU_APB1FZ_TIM3                   BIT(1)
-#define  STM32_DBGMCU_APB1FZ_TIM4                   BIT(2)
-#define  STM32_DBGMCU_APB1FZ_TIM5                   BIT(3)
-#define  STM32_DBGMCU_APB1FZ_TIM6                   BIT(4)
-#define  STM32_DBGMCU_APB1FZ_TIM7                   BIT(5)
-#define  STM32_DBGMCU_APB1FZ_TIM12                  BIT(6)
-#define  STM32_DBGMCU_APB1FZ_TIM13                  BIT(7)
-#define  STM32_DBGMCU_APB1FZ_TIM14                  BIT(8)
-#define  STM32_DBGMCU_APB1FZ_RTC                    BIT(10)
-#define  STM32_DBGMCU_APB1FZ_WWDG                   BIT(11)
-#define  STM32_DBGMCU_APB1FZ_IWDG                   BIT(12)
-#define  STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT     BIT(21)
-#define  STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT     BIT(22)
-#define  STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT     BIT(23)
-#define  STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT   BIT(24)
-#define  STM32_DBGMCU_APB1FZ_CAN1                   BIT(25)
-#define  STM32_DBGMCU_APB1FZ_CAN2                   BIT(26)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-#define  STM32_DBGMCU_APB2FZ_TIM1                   BIT(0)
-#define  STM32_DBGMCU_APB2FZ_TIM8                   BIT(1)
-#define  STM32_DBGMCU_APB2FZ_TIM9                   BIT(16)
-#define  STM32_DBGMCU_APB2FZ_TIM10                  BIT(17)
-#define  STM32_DBGMCU_APB2FZ_TIM11                  BIT(18)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_SHIFT           0
-#define STM32_FLASH_ACR_LAT_MASK        0xf
-#define STM32_FLASH_ACR_PRFTEN          BIT(8)
-#define STM32_FLASH_ACR_ICEN            BIT(9)
-#define STM32_FLASH_ACR_DCEN            BIT(10)
-#define STM32_FLASH_ACR_ICRST           BIT(11)
-#define STM32_FLASH_ACR_DCRST           BIT(12)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             0x08192A3B
-#define  FLASH_OPTKEYR_KEY2             0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_EOP                   BIT(0)
-#define  FLASH_SR_OPERR                 BIT(1)
-#define  FLASH_SR_WRPERR                BIT(4)
-#define  FLASH_SR_PGAERR                BIT(5)
-#define  FLASH_SR_PGPERR                BIT(6)
-#define  FLASH_SR_PGSERR                BIT(7)
-#define  FLASH_SR_RDERR                 BIT(8)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \
-	 FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR)
-#define  FLASH_SR_BUSY                   BIT(16)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_MER                   BIT(2)
-#define STM32_FLASH_CR_SNB_OFFSET       (3)
-#define STM32_FLASH_CR_SNB(sec) \
-	(((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET)
-#define STM32_FLASH_CR_SNB_MASK         (STM32_FLASH_CR_SNB(0xf))
-#define STM32_FLASH_CR_PSIZE_OFFSET     (8)
-#define STM32_FLASH_CR_PSIZE(size) \
-	(((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
-#define STM32_FLASH_CR_PSIZE_MASK       (STM32_FLASH_CR_PSIZE(0x3))
-#define  FLASH_CR_STRT                  BIT(16)
-#define  FLASH_CR_LOCK                  BIT(31)
-#define STM32_FLASH_OPTCR           REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_OPTLOCK                  BIT(0)
-#define  FLASH_OPTSTRT                  BIT(1)
-#define STM32_FLASH_BOR_LEV_OFFSET      (2)
-#define  FLASH_OPTCR_RDP_SHIFT		(8)
-#define  FLASH_OPTCR_RDP_MASK		(0xFF << FLASH_OPTCR_RDP_SHIFT)
-#define  FLASH_OPTCR_RDP_LEVEL_0		(0xAA << FLASH_OPTCR_RDP_SHIFT)
-/* RDP Level 1: Anything but 0xAA/0xCC */
-#define  FLASH_OPTCR_RDP_LEVEL_1		(0x00 << FLASH_OPTCR_RDP_SHIFT)
-#define  FLASH_OPTCR_RDP_LEVEL_2		(0xCC << FLASH_OPTCR_RDP_SHIFT)
-#define STM32_FLASH_nWRP_OFFSET         (16)
-#define STM32_FLASH_nWRP(_bank)         BIT(_bank + STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_nWRP_ALL            (0xFF << STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_OPT_LOCKED      (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
-
-#define STM32_OPTB_RDP_USER         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)       (0x08 + (n&3) * 2)
-#define STM32_OPTB_WP               REG32(STM32_OPTB_BASE + 0x08)
-#define STM32_OPTB_nWRP(_bank)          BIT(_bank)
-#define STM32_OPTB_nWRP_ALL             (0xFF)
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-#define STM32_OTP_BLOCK_NB              16
-#define STM32_OTP_BLOCK_SIZE            32
-#define STM32_OTP_BLOCK_DATA(_block, _offset) \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4)
-#define STM32_OTP_UNLOCK_BYTE           0x00
-#define STM32_OTP_LOCK_BYTE             0xFF
-#define STM32_OTP_LOCK_BASE         \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE)
-#define STM32_OTP_LOCK(_block) \
-	(STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
-#define STM32_OPT_LOCK_MASK(_block)    ((0xFF << ((_block) % 4) * 8))
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT BIT(17)
-
-/* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
-
-/* --- Comparators --- */
-
-
-/* --- DMA --- */
-/*
- * Available DMA streams, numbered from 0.
- *
- * Named channel to respect older interface, but a stream can serve
- * any channels, as long as they are in the same DMA controller.
- *
- * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMA1_STREAM0 = 0,
-	STM32_DMA1_STREAM1 = 1,
-	STM32_DMA1_STREAM2 = 2,
-	STM32_DMA1_STREAM3 = 3,
-	STM32_DMA1_STREAM4 = 4,
-	STM32_DMA1_STREAM5 = 5,
-	STM32_DMA1_STREAM6 = 6,
-	STM32_DMA1_STREAM7 = 7,
-	STM32_DMAS_COUNT = 8,
-	STM32_DMA2_STREAM0 = 8,
-	STM32_DMA2_STREAM1 = 9,
-	STM32_DMA2_STREAM2 = 10,
-	STM32_DMA2_STREAM3 = 11,
-	STM32_DMA2_STREAM4 = 12,
-	STM32_DMA2_STREAM5 = 13,
-	STM32_DMA2_STREAM6 = 14,
-	STM32_DMA2_STREAM7 = 15,
-
-	STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7,
-	STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX,
-	STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX,
-#ifdef CHIP_VARIANT_STM32F41X
-	STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6,
-	STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART2_TX = STM32_DMAS_USART2_TX,
-	STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX,
-#endif
-
-#ifdef CHIP_VARIANT_STM32F41X
-	STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1,
-	STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0,
-
-	STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7,
-	STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3,
-
-	STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4,
-	STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM2,
-#else
-	STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM6,
-	STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0,
-
-	STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7,
-	STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3,
-
-	STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4,
-	STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM1,
-#endif
-
-	STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5,
-	STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2,
-
-	/* Legacy naming for spi_master.c */
-	STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */
-	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
-	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
-	STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */
-	STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */
-	STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */
-	STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */
-	STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */
-};
-
-#define STM32_REQ_USART1_TX 4
-#define STM32_REQ_USART1_RX 4
-
-#define STM32_REQ_USART2_TX 4
-#define STM32_REQ_USART2_RX 4
-
-#define STM32_I2C1_TX_REQ_CH 1
-#define STM32_I2C1_RX_REQ_CH 1
-
-#define STM32_I2C2_TX_REQ_CH 7
-#define STM32_I2C2_RX_REQ_CH 7
-
-#define STM32_I2C3_TX_REQ_CH 3
-#define STM32_I2C3_RX_REQ_CH 1
-
-#define STM32_FMPI2C4_TX_REQ_CH 2
-#define STM32_FMPI2C4_RX_REQ_CH 2
-
-#define STM32_SPI1_TX_REQ_CH 3
-#define STM32_SPI1_RX_REQ_CH 3
-#define STM32_SPI2_TX_REQ_CH 0
-#define STM32_SPI2_RX_REQ_CH 0
-#define STM32_SPI3_TX_REQ_CH 0
-#define STM32_SPI3_RX_REQ_CH 0
-
-#define STM32_DMAS_TOTAL_COUNT 16
-
-/* Registers for a single stream of a DMA controller */
-struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
-};
-
-/* Always use stm32_dma_stream_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_stream_t dma_chan_t;
-struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
-	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
-};
-
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M		(0 << 6)
-#define STM32_DMA_CCR_DIR_M2P		(1 << 6)
-#define STM32_DMA_CCR_DIR_M2M		(2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK		 (0x7 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)		 ((channel) << 25)
-#define STM32_DMA_CCR_RSVD_MASK		(0xF0100000)
-
-
-#define STM32_DMA_SFCR_DMDIS		BIT(2)
-#define STM32_DMA_SFCR_FTH(level)	(((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
-#define STM32_DMA_CH_GETBITS(channel, val) \
-	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h
deleted file mode 100644
index 2245d6775f..0000000000
--- a/chip/stm32/registers-stm32f7.h
+++ /dev/null
@@ -1,1082 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32F7 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32F76X
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-/*
- * STM32F4 introduces a concept of DMA stream to allow
- * fine allocation of a stream to a channel.
- */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012000
-#define STM32_ADC_BASE              0x40012300
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-#define STM32_DMA2_BASE             0x40026400
-
-#define STM32_EXTI_BASE             0x40013C00
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021400 /* see RM0402/0390 table 1 */
-#define STM32_GPIOG_BASE            0x40021800
-#define STM32_GPIOH_BASE            0x40021C00
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFC000
-#define STM32_OTP_BASE              0x1FFF7800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40013800
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40014000 /* STM32F41x only */
-#define STM32_TIM10_BASE            0x40014400 /* STM32F41x only */
-#define STM32_TIM11_BASE            0x40014800 /* STM32F41x only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1fff7a10
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-#define STM32_FMPI2C_CR1(n)        REG32(stm32_i2c_reg(n, 0x00))
-#define  FMPI2C_CR1_PE             BIT(0)
-#define  FMPI2C_CR1_TXDMAEN        BIT(14)
-#define  FMPI2C_CR1_RXDMAEN        BIT(15)
-#define STM32_FMPI2C_CR2(n)        REG32(stm32_i2c_reg(n, 0x04))
-#define  FMPI2C_CR2_RD_WRN         BIT(10)
-#define  FMPI2C_READ               1
-#define  FMPI2C_WRITE              0
-#define  FMPI2C_CR2_START          BIT(13)
-#define  FMPI2C_CR2_STOP           BIT(14)
-#define  FMPI2C_CR2_NACK           BIT(15)
-#define  FMPI2C_CR2_RELOAD         BIT(24)
-#define  FMPI2C_CR2_AUTOEND        BIT(25)
-#define  FMPI2C_CR2_SADD(addr)     ((addr) & 0x3ff)
-#define  FMPI2C_CR2_SADD_MASK      FMPI2C_CR2_SADD(0x3ff)
-#define  FMPI2C_CR2_SIZE(size)     (((size) & 0xff) << 16)
-#define  FMPI2C_CR2_SIZE_MASK      FMPI2C_CR2_SIZE(0xf)
-#define STM32_FMPI2C_OAR1(n)       REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_FMPI2C_OAR2(n)       REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_FMPI2C_TIMINGR(n)    REG32(stm32_i2c_reg(n, 0x10))
-#define  TIMINGR_THE_RIGHT_VALUE   0xC0000E12
-#define  FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28)
-#define  FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20)
-#define  FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16)
-#define  FMPI2C_TIMINGR_SCLH(val)  (((val) & 0xff) << 8)
-#define  FMPI2C_TIMINGR_SCLL(val)  (((val) & 0xff) << 0)
-#define STM32_FMPI2C_TIMEOUTR(n)   REG32(stm32_i2c_reg(n, 0x14))
-
-#define STM32_FMPI2C_ISR(n)        REG32(stm32_i2c_reg(n, 0x18))
-#define  FMPI2C_ISR_TXE            BIT(0)
-#define  FMPI2C_ISR_TXIS           BIT(1)
-#define  FMPI2C_ISR_RXNE           BIT(2)
-#define  FMPI2C_ISR_ADDR           BIT(3)
-#define  FMPI2C_ISR_NACKF          BIT(4)
-#define  FMPI2C_ISR_STOPF          BIT(5)
-#define  FMPI2C_ISR_BERR           BIT(8)
-#define  FMPI2C_ISR_ARLO           BIT(9)
-#define  FMPI2C_ISR_BUSY           BIT(15)
-#define STM32_FMPI2C_ICR(n)        REG32(stm32_i2c_reg(n, 0x1C))
-
-#define STM32_FMPI2C_PECR(n)       REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_FMPI2C_RXDR(n)       REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_FMPI2C_TXDR(n)       REG32(stm32_i2c_reg(n, 0x28))
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-
-#ifdef CHIP_VARIANT_STM32F76X
-/* Required or recommended clocks for stm32f767/769 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK 45000000
-#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */
-#define STM32F4_VCO_CLOCK 360000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 2   /* sys = VCO/2  = 180 Mhz */
-#define STM32F4_AHB_PRE 0x0  /* AHB = sysclk = 180 Mhz */
-#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */
-#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */
-#define STM32_FLASH_ACR_LATENCY     (5 << 0)
-#else
-#error "No valid clocks defined"
-#endif
-
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x04)
-/* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		0
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
-/* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		6
-#define  PLLCFGR_PLLN(val)		(((val) & 0x1ff) << PLLCFGR_PLLN_OFF)
-/* Main CPU Clock */
-#define  PLLCFGR_PLLP_OFF		16
-#define  PLLCFGR_PLLP(val)		(((val) & 0x3) << PLLCFGR_PLLP_OFF)
-
-#define  PLLCFGR_PLLSRC_HSI		(0 << 22)
-#define  PLLCFGR_PLLSRC_HSE		BIT(22)
-/* USB OTG FS: Must equal 48MHz */
-#define  PLLCFGR_PLLQ_OFF		24
-#define  PLLCFGR_PLLQ(val)		(((val) & 0xf) << PLLCFGR_PLLQ_OFF)
-/* SYSTEM */
-#define  PLLCFGR_PLLR_OFF		28
-#define  PLLCFGR_PLLR(val)		(((val) & 0x7) << PLLCFGR_PLLR_OFF)
-
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_HSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(1 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL_R		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(1 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL_R	(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-/* AHB Prescalar: nonlinear values, look up in RM0390 */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
-/* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			10
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
-/* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			13
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
-/* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
-
-#define STM32_RCC_CIR                   REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x10)
-#define  RCC_AHB1RSTR_OTGHSRST		BIT(29)
-
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x18)
-
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x24)
-
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_AHB1ENR_GPIOMASK	(0xff << 0)
-#define STM32_RCC_AHB1ENR_BKPSRAMEN	BIT(18)
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(21)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(22)
-/* TODO(nsanders): normalize naming.*/
-#define STM32_RCC_HB1_DMA1		BIT(21)
-#define STM32_RCC_HB1_DMA2		BIT(22)
-#define STM32_RCC_AHB1ENR_OTGHSEN	BIT(29)
-#define STM32_RCC_AHB1ENR_OTGHSULPIEN	BIT(30)
-
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(6)
-#define STM32_RCC_AHB2ENR_OTGFSEN	BIT(7)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x38)
-
-#define STM32_RCC_APB1ENR               REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_PWREN                 BIT(28)
-#define STM32_RCC_I2C1EN                BIT(21)
-#define STM32_RCC_I2C2EN                BIT(22)
-#define STM32_RCC_I2C3EN                BIT(23)
-#define STM32_RCC_FMPI2C4EN             BIT(24)
-
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_APB2ENR_ADC1EN        BIT(8) /* STM32F4 */
-
-#define STM32_RCC_PB2_USART6            BIT(5)
-#define STM32_RCC_SYSCFGEN		BIT(14)
-
-#define STM32_RCC_AHB1LPENR             REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_AHB2LPENR             REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_AHB3LPENR             REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1LPENR             REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_APB2LPENR             REG32(STM32_RCC_BASE + 0x64)
-
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-#define STM32_RCC_PB2_TIM9		BIT(16)
-#define STM32_RCC_PB2_TIM10		BIT(17)
-#define STM32_RCC_PB2_TIM11		BIT(18)
-
-#define STM32_RCC_DCKCFGR2              REG32(STM32_RCC_BASE + 0x94)
-#define  DCKCFGR2_FMPI2C1SEL(val)       (((val) & 0x3) << 22)
-#define  DCKCFGR2_FMPI2C1SEL_MASK       (0x3 << 22)
-#define  FMPI2C1SEL_APB                 0x0
-
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(4)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_SHIFT           0
-#define STM32_FLASH_ACR_LAT_MASK        0xf
-#define STM32_FLASH_ACR_PRFTEN          BIT(8)
-#define STM32_FLASH_ACR_ICEN            BIT(9)
-#define STM32_FLASH_ACR_DCEN            BIT(10)
-#define STM32_FLASH_ACR_ICRST           BIT(11)
-#define STM32_FLASH_ACR_DCRST           BIT(12)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             0x08192A3B
-#define  FLASH_OPTKEYR_KEY2             0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_EOP                   BIT(0)
-#define  FLASH_SR_OPERR                 BIT(1)
-#define  FLASH_SR_WRPERR                BIT(4)
-#define  FLASH_SR_PGAERR                BIT(5)
-#define  FLASH_SR_PGPERR                BIT(6)
-#define  FLASH_SR_PGSERR                BIT(7)
-#define  FLASH_SR_RDERR                 BIT(8)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \
-	 FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR)
-#define  FLASH_SR_BUSY                   BIT(16)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_MER                   BIT(2)
-#define STM32_FLASH_CR_SNB_OFFSET       (3)
-#define STM32_FLASH_CR_SNB(sec) \
-	(((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET)
-#define STM32_FLASH_CR_SNB_MASK         (STM32_FLASH_CR_SNB(0xf))
-#define STM32_FLASH_CR_PSIZE_OFFSET     (8)
-#define STM32_FLASH_CR_PSIZE(size) \
-	(((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
-#define STM32_FLASH_CR_PSIZE_MASK       (STM32_FLASH_CR_PSIZE(0x3))
-#define  FLASH_CR_STRT                  BIT(16)
-#define  FLASH_CR_LOCK                  BIT(31)
-#define STM32_FLASH_OPTCR           REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_OPTLOCK                  BIT(0)
-#define  FLASH_OPTSTRT                  BIT(1)
-#define STM32_FLASH_BOR_LEV_OFFSET      (2)
-#define STM32_FLASH_RDP_MASK            (0xFF << 8)
-#define STM32_FLASH_nWRP_OFFSET         (16)
-#define STM32_FLASH_nWRP(_bank)         BIT(_bank + STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_nWRP_ALL            (0xFF << STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_OPT_LOCKED      (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
-
-#define STM32_OPTB_RDP_USER         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)       (0x08 + (n&3) * 2)
-#define STM32_OPTB_WP               REG32(STM32_OPTB_BASE + 0x08)
-#define STM32_OPTB_nWRP(_bank)          BIT(_bank)
-#define STM32_OPTB_nWRP_ALL             (0xFF)
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-#define STM32_OTP_BLOCK_NB              16
-#define STM32_OTP_BLOCK_SIZE            32
-#define STM32_OTP_BLOCK_DATA(_block, _offset) \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4)
-#define STM32_OTP_UNLOCK_BYTE           0x00
-#define STM32_OTP_LOCK_BYTE             0xFF
-#define STM32_OTP_LOCK_BASE         \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE)
-#define STM32_OTP_LOCK(_block) \
-	(STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
-#define STM32_OPT_LOCK_MASK(_block)    ((0xFF << ((_block) % 4) * 8))
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT BIT(17)
-
-/* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
-
-/* --- Comparators --- */
-
-
-/* --- DMA --- */
-/*
- * Available DMA streams, numbered from 0.
- *
- * Named channel to respect older interface, but a stream can serve
- * any channels, as long as they are in the same DMA controller.
- *
- * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMA1_STREAM0 = 0,
-	STM32_DMA1_STREAM1 = 1,
-	STM32_DMA1_STREAM2 = 2,
-	STM32_DMA1_STREAM3 = 3,
-	STM32_DMA1_STREAM4 = 4,
-	STM32_DMA1_STREAM5 = 5,
-	STM32_DMA1_STREAM6 = 6,
-	STM32_DMA1_STREAM7 = 7,
-	STM32_DMAS_COUNT = 8,
-	STM32_DMA2_STREAM0 = 8,
-	STM32_DMA2_STREAM1 = 9,
-	STM32_DMA2_STREAM2 = 10,
-	STM32_DMA2_STREAM3 = 11,
-	STM32_DMA2_STREAM4 = 12,
-	STM32_DMA2_STREAM5 = 13,
-	STM32_DMA2_STREAM6 = 14,
-	STM32_DMA2_STREAM7 = 15,
-
-	STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7,
-	STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX,
-	STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX,
-	STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6,
-	STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART2_TX = STM32_DMAS_USART2_TX,
-	STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX,
-	STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1,
-	STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0,
-	STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7,
-	STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3,
-	STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4,
-	STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM2,
-	STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5,
-	STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2,
-
-	/* Legacy naming for spi_master.c */
-	STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */
-	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
-	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
-	STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */
-	STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */
-	STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */
-	STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */
-	STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */
-};
-
-#define STM32_REQ_USART1_TX 4
-#define STM32_REQ_USART1_RX 4
-
-#define STM32_REQ_USART2_TX 4
-#define STM32_REQ_USART2_RX 4
-
-#define STM32_I2C1_TX_REQ_CH 1
-#define STM32_I2C1_RX_REQ_CH 1
-
-#define STM32_I2C2_TX_REQ_CH 7
-#define STM32_I2C2_RX_REQ_CH 7
-
-#define STM32_I2C3_TX_REQ_CH 3
-#define STM32_I2C3_RX_REQ_CH 1
-
-#define STM32_FMPI2C4_TX_REQ_CH 2
-#define STM32_FMPI2C4_RX_REQ_CH 2
-
-#define STM32_SPI1_TX_REQ_CH 3
-#define STM32_SPI1_RX_REQ_CH 3
-#define STM32_SPI2_TX_REQ_CH 0
-#define STM32_SPI2_RX_REQ_CH 0
-#define STM32_SPI3_TX_REQ_CH 0
-#define STM32_SPI3_RX_REQ_CH 0
-
-#define STM32_DMAS_TOTAL_COUNT 16
-
-/* Registers for a single stream of a DMA controller */
-struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
-};
-
-/* Always use stm32_dma_stream_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_stream_t dma_chan_t;
-struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
-	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
-};
-
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M		(0 << 6)
-#define STM32_DMA_CCR_DIR_M2P		(1 << 6)
-#define STM32_DMA_CCR_DIR_M2M		(2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK		 (0x7 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)		 ((channel) << 25)
-#define STM32_DMA_CCR_RSVD_MASK		(0xF0100000)
-
-
-#define STM32_DMA_SFCR_DMDIS		BIT(2)
-#define STM32_DMA_SFCR_FTH(level)	(((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
-#define STM32_DMA_CH_GETBITS(channel, val) \
-	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h
deleted file mode 100644
index e3a73a0fe9..0000000000
--- a/chip/stm32/registers-stm32g4.h
+++ /dev/null
@@ -1,1506 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32G4 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32G431
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_ADC1            18
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-#define STM32_IRQ_FDCAN_IT0       21
-#define STM32_IRQ_FDCAN_IT1       22
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_TIM15           24
-#define STM32_IRQ_TIM16           25
-#define STM32_IRQ_TIM17           26
-#define STM32_IRQ_TIM1_CC         27
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42
-#define STM32_IRQ_TIM8_BREAK      43
-#define STM32_IRQ_TIM8_UP         44
-#define STM32_IRQ_TIM8_TRG_COM    45
-#define STM32_IRQ_TIM8_CC         46
-#define STM32_IRQ_LPTIM1          49
-#define STM32_IRQ_SPI3            51
-#define STM32_IRQ_USART4          52
-#define STM32_IRQ_TIM6_DAC        54
-#define STM32_IRQ_TIM7            55
-#define STM32_IRQ_DMA2_CHANNEL1   56
-#define STM32_IRQ_DMA2_CHANNEL2   57
-#define STM32_IRQ_DMA2_CHANNEL3   58
-#define STM32_IRQ_DMA2_CHANNEL4   59
-#define STM32_IRQ_DMA2_CHANNEL5   60
-#define STM32_IRQ_UCPD1           63
-#define STM32_IRQ_COMP_1_2_3      64
-#define STM32_IRQ_COMP_4          65
-#define STM32_IRQ_CRS             75
-#define STM32_IRQ_SAI1            76
-#define STM32_IRQ_FPU             81
-#define STM32_IRQ_RNG             90
-#define STM32_IRQ_LPUART          91
-#define STM32_IRQ_I2C3_EV         92
-#define STM32_IRQ_I2C3_ER         93
-#define STM32_IRQ_DMAMUX_OVR      94
-#define STM32_IRQ_DMA1_CHANNEL8   96
-#define STM32_IRQ_DMA2_CHANNEL6   97
-#define STM32_IRQ_DMA2_CHANNEL7   98
-#define STM32_IRQ_DMA2_CHANNEL8   99
-#define STM32_IRQ_CORDIC          100
-#define STM32_IRQ_FMAC            101
-
-/* LPUART gets accessed as UART9 in STM32 uart driver */
-#define STM32_IRQ_USART9 STM32_IRQ_LPUART
-
-/* To simplify code generation, define DMA channel 13 - 14 */
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-#ifdef CHIP_VARIANT_STM32G431
-#define CHIP_VARIANT_STM32G431X
-#endif
-
-/* Embedded flash option bytes base address */
-#define STM32_OPTB_BANK1_BASE       0x1FFF7800UL
-#define STM32_OPTB_BANK2_BASE       0x1FFF8000UL
-
-/* Peripheral base addresses */
-#define STM32_PERIPH_BASE           (0x40000000UL)
-/* Peripheral memory map */
-#define STM32_APB1PERIPH_BASE       (STM32_PERIPH_BASE + 0x00000000UL)
-#define STM32_APB2PERIPH_BASE       (STM32_PERIPH_BASE + 0x00010000UL)
-#define STM32_AHB1PERIPH_BASE       (STM32_PERIPH_BASE + 0x00020000UL)
-#define STM32_AHB2PERIPH_BASE       (STM32_PERIPH_BASE + 0x08000000UL)
-
-/* APB1 peripherals */
-#define STM32_APB1PERIPH(offset)    (STM32_APB1PERIPH_BASE + offset)
-#define STM32_TIM2_BASE             STM32_APB1PERIPH(0x0000UL)
-#define STM32_TIM3_BASE             STM32_APB1PERIPH(0x0400UL)
-#define STM32_TIM4_BASE             STM32_APB1PERIPH(0x0800UL)
-#define STM32_TIM6_BASE             STM32_APB1PERIPH(0x1000UL)
-#define STM32_TIM7_BASE             STM32_APB1PERIPH(0x1400UL)
-#define STM32_CRS_BASE              STM32_APB1PERIPH(0x2000UL)
-#define STM32_TAMP_BASE             STM32_APB1PERIPH(0x2400UL)
-#define STM32_RTC_BASE              STM32_APB1PERIPH(0x2800UL)
-#define STM32_WWDG_BASE             STM32_APB1PERIPH(0x2C00UL)
-#define STM32_IWDG_BASE             STM32_APB1PERIPH(0x3000UL)
-#define STM32_SPI2_BASE             STM32_APB1PERIPH(0x3800UL)
-#define STM32_SPI3_BASE             STM32_APB1PERIPH(0x3C00UL)
-#define STM32_USART2_BASE           STM32_APB1PERIPH(0x4400UL)
-#define STM32_USART3_BASE           STM32_APB1PERIPH(0x4800UL)
-#define STM32_UART4_BASE            STM32_APB1PERIPH(0x4C00UL)
-#define STM32_I2C1_BASE             STM32_APB1PERIPH(0x5400UL)
-#define STM32_I2C2_BASE             STM32_APB1PERIPH(0x5800UL)
-/* USB_IP Peripheral Registers base address */
-#define STM32_USB_FS_BASE           STM32_APB1PERIPH(0x5C00UL)
-/* USB_IP Packet Memory Area base address */
-#define STM32_USB_PMAADDR           STM32_APB1PERIPH(0x6000UL)
-#define STM32_FDCAN1_BASE           STM32_APB1PERIPH(0x6400UL)
-/* FDCAN configuration registers base address */
-#define STM32_FDCAN_CONFIG_BASE     STM32_APB1PERIPH(0x6500UL)
-#define STM32_PWR_BASE              STM32_APB1PERIPH(0x7000UL)
-#define STM32_I2C3_BASE             STM32_APB1PERIPH(0x7800UL)
-#define STM32_LPTIM1_BASE           STM32_APB1PERIPH(0x7C00UL)
-#define STM32_LPUART1_BASE          STM32_APB1PERIPH(0x8000UL)
-#define STM32_I2C4_BASE             STM32_APB1PERIPH(0x8400UL)
-/* UART9 is used as link to LPUART in STM32 uart.c implementation */
-#define STM32_USART9_BASE           STM32_APB1PERIPH(0x8000UL)
-#define STM32_I2C4_BASE             STM32_APB1PERIPH(0x8400UL)
-#define STM32_UCPD1_BASE            STM32_APB1PERIPH(0xA000UL)
-#define STM32_SRAMCAN_BASE          STM32_APB1PERIPH(0xA400UL)
-
-/* APB2 peripherals */
-#define STM32_APB2PERIPH(offset)    (STM32_APB2PERIPH_BASE + offset)
-#define STM32_SYSCFG_BASE           STM32_APB2PERIPH(0x0000UL)
-#define STM32_VREFBUF_BASE          STM32_APB2PERIPH(0x0030UL)
-#define STM32_COMP1_BASE            STM32_APB2PERIPH(0x0200UL)
-#define STM32_COMP2_BASE            STM32_APB2PERIPH(0x0204UL)
-#define STM32_COMP3_BASE            STM32_APB2PERIPH(0x0208UL)
-#define STM32_COMP4_BASE            STM32_APB2PERIPH(0x020CUL)
-#define STM32_OPAMP_BASE            STM32_APB2PERIPH(0x0300UL)
-#define STM32_OPAMP1_BASE           STM32_APB2PERIPH(0x0300UL)
-#define STM32_OPAMP2_BASE           STM32_APB2PERIPH(0x0304UL)
-#define STM32_OPAMP3_BASE           STM32_APB2PERIPH(0x0308UL)
-#define STM32_EXTI_BASE             STM32_APB2PERIPH(0x0400UL)
-#define STM32_TIM1_BASE             STM32_APB2PERIPH(0x2C00UL)
-#define STM32_SPI1_BASE             STM32_APB2PERIPH(0x3000UL)
-#define STM32_TIM8_BASE             STM32_APB2PERIPH(0x3400UL)
-#define STM32_USART1_BASE           STM32_APB2PERIPH(0x3800UL)
-#define STM32_TIM15_BASE            STM32_APB2PERIPH(0x4000UL)
-#define STM32_TIM16_BASE            STM32_APB2PERIPH(0x4400UL)
-#define STM32_TIM17_BASE            STM32_APB2PERIPH(0x4800UL)
-#define STM32_SAI1_BASE             STM32_APB2PERIPH(0x5400UL)
-#define STM32_SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
-#define STM32_SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
-
-/* AHB1 peripherals */
-#define STM32_AHB1PERIPH(offset)    (STM32_AHB1PERIPH_BASE + offset)
-#define STM32_DMA1_BASE             STM32_AHB1PERIPH(0x0000UL)
-#define STM32_DMA2_BASE             STM32_AHB1PERIPH(0x0400UL)
-#define STM32_DMAMUX_BASE           STM32_AHB1PERIPH(0x0800UL)
-#define STM32_CORDIC_BASE           STM32_AHB1PERIPH(0x0C00UL)
-#define STM32_RCC_BASE              STM32_AHB1PERIPH(0x1000UL)
-#define STM32_FMAC_BASE             STM32_AHB1PERIPH(0x1400UL)
-#define STM32_FLASH_REGS_BASE       STM32_AHB1PERIPH(0x2000UL)
-#define STM32_CRC_BASE              STM32_AHB1PERIPH(0x3000UL)
-
-#define STM32_DMA1_CHAN(offset)     (STM32_DMA1_BASE + offset)
-#define STM32_DMA1_Channel1_BASE    STM32_DMA1_CHAN(0x0008UL)
-#define STM32_DMA1_Channel2_BASE    STM32_DMA1_CHAN(0x001CUL)
-#define STM32_DMA1_Channel3_BASE    STM32_DMA1_CHAN(0x0030UL)
-#define STM32_DMA1_Channel4_BASE    STM32_DMA1_CHAN(0x0044UL)
-#define STM32_DMA1_Channel5_BASE    STM32_DMA1_CHAN(0x0058UL)
-#define STM32_DMA1_Channel6_BASE    STM32_DMA1_CHAN(0x006CUL)
-
-#define STM32_DMA2_CHAN(offset)     (STM32_DMA2_BASE + offset)
-#define STM32_DMA2_Channel1_BASE    STM32_DMA2_CHAN(0x0008UL)
-#define STM32_DMA2_Channel2_BASE    STM32_DMA2_CHAN(0x001CUL)
-#define STM32_DMA2_Channel3_BASE    STM32_DMA2_CHAN(0x0030UL)
-#define STM32_DMA2_Channel4_BASE    STM32_DMA2_CHAN(0x0044UL)
-#define STM32_DMA2_Channel5_BASE    STM32_DMA2_CHAN(0x0058UL)
-#define STM32_DMA2_Channel6_BASE    STM32_DMA2_CHAN(0x006CUL)
-
-#define STM32_DMAMUX(offset)          (STM32_DMAMUX_BASE + offset)
-#define STM32_DMAMUX_Channel0_BASE    STM32_DMAMUX(0x0000UL)
-#define STM32_DMAMUX_Channel1_BASE    STM32_DMAMUX(0x0004UL)
-#define STM32_DMAMUX_Channel2_BASE    STM32_DMAMUX(0x0008UL)
-#define STM32_DMAMUX_Channel3_BASE    STM32_DMAMUX(0x000CUL)
-#define STM32_DMAMUX_Channel4_BASE    STM32_DMAMUX(0x0010UL)
-#define STM32_DMAMUX_Channel5_BASE    STM32_DMAMUX(0x0014UL)
-#define STM32_DMAMUX_Channel6_BASE    STM32_DMAMUX(0x0020UL)
-#define STM32_DMAMUX_Channel7_BASE    STM32_DMAMUX(0x0024UL)
-#define STM32_DMAMUX_Channel8_BASE    STM32_DMAMUX(0x0028UL)
-#define STM32_DMAMUX_Channel9_BASE    STM32_DMAMUX(0x002CUL)
-#define STM32_DMAMUX_Channel10_BASE   STM32_DMAMUX(0x0030UL)
-#define STM32_DMAMUX_Channel11_BASE   STM32_DMAMUX(0x0034UL)
-#define STM32_DMAMUX_RequestGenerator0_BASE  STM32_DMAMUX(0x0100UL)
-#define STM32_DMAMUX_RequestGenerator1_BASE  STM32_DMAMUX(0x0104UL)
-#define STM32_DMAMUX_RequestGenerator2_BASE  STM32_DMAMUX(0x0108UL)
-#define STM32_DMAMUX_RequestGenerator3_BASE  STM32_DMAMUX(0x010CUL)
-#define STM32_DMAMUX_ChannelStatus_BASE      STM32_DMAMUX(0x0080UL)
-#define STM32_DMAMUX_RequestGenStatus_BASE   STM32_DMAMUX(0x0140UL)
-
-/* AHB2 peripherals */
-#define STM32_AHB2PERIPH(offset)    (STM32_AHB2PERIPH_BASE + offset)
-#define STM32_GPIOA_BASE            STM32_AHB2PERIPH(0x0000UL)
-#define STM32_GPIOB_BASE            STM32_AHB2PERIPH(0x0400UL)
-#define STM32_GPIOC_BASE            STM32_AHB2PERIPH(0x0800UL)
-#define STM32_GPIOD_BASE            STM32_AHB2PERIPH(0x0C00UL)
-#define STM32_GPIOE_BASE            STM32_AHB2PERIPH(0x1000UL)
-#define STM32_GPIOF_BASE            STM32_AHB2PERIPH(0x1400UL)
-#define STM32_GPIOG_BASE            STM32_AHB2PERIPH(0x1800UL)
-#define STM32_ADC1_BASE             STM32_AHB2PERIPH(0x08000000UL)
-#define STM32_ADC2_BASE             STM32_AHB2PERIPH(0x08000100UL)
-#define STM32_ADC12_COMMON_BASE     STM32_AHB2PERIPH(0x08000300UL)
-#define STM32_DAC_BASE              STM32_AHB2PERIPH(0x08000800UL)
-#define STM32_DAC1_BASE             STM32_AHB2PERIPH(0x08000800UL)
-#define STM32_DAC3_BASE             STM32_AHB2PERIPH(0x08001000UL)
-#define STM32_RNG_BASE              STM32_AHB2PERIPH(0x08060800UL)
-
-#define STM32_UNIQUE_ID_BASE        0x1FFF7590
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- UCPD --- */
-#define STM32_UCPD_REG(port, offset) \
-	REG32(((STM32_UCPD1_BASE + ((port) * 0x400)) + (offset)))
-
-#define STM32_UCPD_CFGR1(port)              STM32_UCPD_REG(port, 0x00)
-#define STM32_UCPD_CFGR2(port)              STM32_UCPD_REG(port, 0x04)
-#define STM32_UCPD_CR(port)                 STM32_UCPD_REG(port, 0x0c)
-#define STM32_UCPD_IMR(port)                STM32_UCPD_REG(port, 0x10)
-#define STM32_UCPD_SR(port)                 STM32_UCPD_REG(port, 0x14)
-#define STM32_UCPD_ICR(port)                STM32_UCPD_REG(port, 0x18)
-#define STM32_UCPD_TX_ORDSETR(port)         STM32_UCPD_REG(port, 0x1c)
-#define STM32_UCPD_TX_PAYSZR(port)          STM32_UCPD_REG(port, 0x20)
-#define STM32_UCPD_TXDR(port)               STM32_UCPD_REG(port, 0x24)
-#define STM32_UCPD_RX_ORDSETR(port)         STM32_UCPD_REG(port, 0x28)
-#define STM32_UCPD_RX_PAYSZR(port)          STM32_UCPD_REG(port, 0x2c)
-#define STM32_UCPD_RXDR(port)               STM32_UCPD_REG(port, 0x30)
-#define STM32_UCPD_RX_ORDEXTR1(port)        STM32_UCPD_REG(port, 0x34)
-#define STM32_UCPD_RX_ORDEXTR2(port)        STM32_UCPD_REG(port, 0x38)
-
-/* --- UCPD CFGR1 Bit Definitions --- */
-#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT     0
-#define STM32_UCPD_CFGR1_HBITCLKD_MASK      ((0x3f) << \
-					     (STM32_UCPD_CFGR1_HBITCLKD_SHIFT))
-#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x)    ((x) << \
-					     STM32_UCPD_CFGR1_HBITCLKD_SHIFT)
-#define STM32_UCPD_CFGR1_IFRGAP_SHIFT       6
-#define STM32_UCPD_CFGR1_IFRGAP_MASK        ((0x1f) << \
-					     (STM32_UCPD_CFGR1_IFRGAP_SHIFT))
-#define STM32_UCPD_CFGR1_IFRGAP_VAL(x)      ((x) << \
-					     STM32_UCPD_CFGR1_IFRGAP_SHIFT)
-#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT     11
-#define STM32_UCPD_CFGR1_TRANSWIN_MASK      ((0x1f) << \
-					     (STM32_UCPD_CFGR1_TRANSWIN_SHIFT))
-#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x)    ((x) << \
-					     STM32_UCPD_CFGR1_TRANSWIN_SHIFT)
-#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT      17
-#define STM32_UCPD_CFGR1_PSC_CLK_MASK       ((0x7) << \
-					     STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
-#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x)     ((x) << \
-					     STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
-#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT   20
-#define STM32_UCPD_CFGR1_RXORDSETEN_MASK    ((0x1ff) << \
-					     STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
-#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x)  ((x) << \
-					     STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
-#define STM32_UCPD_CFGR1_TXDMAEN            BIT(29)
-#define STM32_UCPD_CFGR1_RXDMAEN            BIT(30)
-#define STM32_UCPD_CFGR1_UCPDEN             BIT(31)
-
-/* --- UCPD CFGR2 Bit Definitions --- */
-#define STM32_UCPD_CFGR2_RXFILTDIS          BIT(0)
-#define STM32_UCPD_CFGR2_RXFILT2N3          BIT(1)
-#define STM32_UCPD_CFGR2_FORCECLK           BIT(2)
-#define STM32_UCPD_CFGR2_WUPEN              BIT(3)
-
-/* --- UCPD CR Bit Definitions --- */
-#define STM32_UCPD_CR_TXMODE_SHIFT          0
-#define STM32_UCPD_CR_TXMODE_MASK           ((0x3) << \
-					     (STM32_UCPD_CR_TXMODE_SHIFT))
-#define STM32_UCPD_CR_TXMODE_VAL(x)         ((x) << STM32_UCPD_CR_TXMODE_SHIFT)
-#define STM32_UCPD_CR_TXSEND                BIT(2)
-#define STM32_UCPD_CR_TXHRST                BIT(3)
-#define STM32_UCPD_CR_RXMODE                BIT(4)
-#define STM32_UCPD_CR_PHYRXEN               BIT(5)
-#define STM32_UCPD_CR_PHYCCSEL              BIT(6)
-#define STM32_UCPD_CR_ANASUBMODE_SHIFT      7
-#define STM32_UCPD_CR_ANASUBMODE_MASK       ((0x3) << \
-					     (STM32_UCPD_CR_ANASUBMODE_SHIFT))
-#define STM32_UCPD_CR_ANASUBMODE_VAL(x)     ((x) << \
-					     STM32_UCPD_CR_ANASUBMODE_SHIFT)
-#define STM32_UCPD_CR_ANAMODE               BIT(9)
-#define STM32_UCPD_CR_CCENABLE_SHIFT        10
-#define STM32_UCPD_CR_CCENABLE_MASK         ((0x3) << \
-					     (STM32_UCPD_CR_CCENABLE_SHIFT))
-#define STM32_UCPD_CR_CCENABLE_VAL(x)       ((x) << \
-					     STM32_UCPD_CR_CCENABLE_SHIFT)
-#define STM32_UCPD_CR_FRSRXEN               BIT(16)
-#define STM32_UCPD_CR_FRSTX                 BIT(17)
-#define STM32_UCPD_CR_RDCH                  BIT(18)
-#define STM32_UCPD_CR_CC1TCDIS              BIT(20)
-#define STM32_UCPD_CR_CC2TCDIS              BIT(21)
-
-/* TX mode message types */
-#define STM32_UCPD_CR_TXMODE_DEF            0
-#define STM32_UCPD_CR_TXMODE_CBL_RST        1
-#define STM32_UCPD_CR_TXMODE_BIST           2
-
-/* --- UCPD IMR Bit Definitions --- */
-#define STM32_UCPD_IMR_TXISIE               BIT(0)
-#define STM32_UCPD_IMR_TXMSGDISCIE          BIT(1)
-#define STM32_UCPD_IMR_TXMSGSENTIE          BIT(2)
-#define STM32_UCPD_IMR_TXMSGABTIE           BIT(3)
-#define STM32_UCPD_IMR_HRSTDISCIE           BIT(4)
-#define STM32_UCPD_IMR_HRSTSENTIE           BIT(5)
-#define STM32_UCPD_IMR_TXUNDIE              BIT(6)
-#define STM32_UCPD_IMR_RXNEIE               BIT(8)
-#define STM32_UCPD_IMR_RXORDDETIE           BIT(9)
-#define STM32_UCPD_IMR_RXHRSTDETIE          BIT(10)
-#define STM32_UCPD_IMR_RXOVRIE              BIT(11)
-#define STM32_UCPD_IMR_RXMSGENDIE           BIT(12)
-#define STM32_UCPD_IMR_TYPECEVT1IE          BIT(14)
-#define STM32_UCPD_IMR_TYPECEVT2IE          BIT(15)
-#define STM32_UCPD_IMR_FRSEVTIE             BIT(20)
-
-/* --- UCPD SR Bit Definitions --- */
-#define STM32_UCPD_SR_TXIS                  BIT(0)
-#define STM32_UCPD_SR_TXMSGDISC             BIT(1)
-#define STM32_UCPD_SR_TXMSGSENT             BIT(2)
-#define STM32_UCPD_SR_TXMSGABT              BIT(3)
-#define STM32_UCPD_SR_HRSTDISC              BIT(4)
-#define STM32_UCPD_SR_HRSTSENT              BIT(5)
-#define STM32_UCPD_SR_TXUND                 BIT(6)
-#define STM32_UCPD_SR_RXNE                  BIT(8)
-#define STM32_UCPD_SR_RXORDDET              BIT(9)
-#define STM32_UCPD_SR_RXHRSTDET             BIT(10)
-#define STM32_UCPD_SR_RXOVR                 BIT(11)
-#define STM32_UCPD_SR_RXMSGEND              BIT(12)
-#define STM32_UCPD_SR_RXERR                 BIT(13)
-#define STM32_UCPD_SR_TYPECEVT1             BIT(14)
-#define STM32_UCPD_SR_TYPECEVT2             BIT(15)
-#define STM32_UCPD_SR_VSTATE_CC1_SHIFT      16
-#define STM32_UCPD_SR_VSTATE_CC1_MASK       ((0x3) << \
-					       (STM32_UCPD_SR_VSTATE_CC1_SHIFT))
-#define STM32_UCPD_SR_VSTATE_CC1_VAL(x)     ((x) << \
-					     STM32_UCPD_SR_VSTATE_CC1_SHIFT)
-#define STM32_UCPD_SR_VSTATE_CC2_SHIFT      18
-#define STM32_UCPD_SR_VSTATE_CC2_MASK       ((0x3) << \
-					     (STM32_UCPD_SR_VSTATE_CC2_SHIFT))
-#define STM32_UCPD_SR_VSTATE_CC2_VAL(x)     ((x) << \
-					     STM32_UCPD_SR_VSTATE_CC2_SHIFT)
-#define STM32_UCPD_SR_FRSEVT                BIT(20)
-
-#define STM32_UCPD_SR_VSTATE_OPEN           3
-#define STM32_UCPD_SR_VSTATE_RA             0
-
-/* --- UCPD ICR Bit Definitions --- */
-#define STM32_UCPD_ICR_TXMSGDISCCF          BIT(1)
-#define STM32_UCPD_ICR_TXMSGSENTCF          BIT(2)
-#define STM32_UCPD_ICR_TXMSGABTCF           BIT(3)
-#define STM32_UCPD_ICR_HRSTDISCCF           BIT(4)
-#define STM32_UCPD_ICR_HRSTSENTCF           BIT(5)
-#define STM32_UCPD_ICR_TXUNDCF              BIT(6)
-#define STM32_UCPD_ICR_RXORDDETCF           BIT(9)
-#define STM32_UCPD_ICR_RXHRSTDETCF          BIT(10)
-#define STM32_UCPD_ICR_RXOVRCF              BIT(11)
-#define STM32_UCPD_ICR_RXMSGENDCF           BIT(12)
-#define STM32_UCPD_ICR_TYPECEVT1CF          BIT(14)
-#define STM32_UCPD_ICR_TYPECEVT2CF          BIT(15)
-#define STM32_UCPD_ICR_FRSEVTCF             BIT(20)
-
-
-/* --- UCPD TX_ORDSETR Bit Definitions --- */
-#define STM32_UCPD_TX_ORDSETR_SHIFT        0
-#define STM32_UCPD_TX_ORDSETR_MASK         ((0xfffff) << \
-					    (STM32_UCPD_TX_ORDSETR_SHIFT))
-#define STM32_UCPD_TX_ORDSETR_VAL(x)       ((x) << STM32_UCPD_TX_ORDSETR_SHIFT)
-
-/* --- UCPD TX_PAYSZR Bit Definitions --- */
-#define STM32_UCPD_TX_PAYSZR_SHIFT        0
-#define STM32_UCPD_TX_PAYSZR_MASK         ((0x3ff) << \
-					   (STM32_UCPD_TX_PAYSZR_SHIFT))
-#define STM32_UCPD_TX_PAYSZR_VAL(x)       ((x) << STM32_UCPD_TX_PAYSZR_SHIFT)
-
-/* --- UCPD TXDR Bit Definitions --- */
-#define STM32_UCPD_TXDR_SHIFT             0
-#define STM32_UCPD_TXDR_MASK              ((0xff) << \
-					   (STM32_UCPD_TXDR_SHIFT))
-#define STM32_UCPD_TXDR_VAL(x)            ((x) << STM32_UCPD_TXDR_SHIFT)
-
-/* --- UCPD RX_ORDSETR Bit Definitions --- */
-#define STM32_UCPD_RXORDSETR_SHIFT        0
-#define STM32_UCPD_RXORDSETR_MASK         ((0x7) << \
-					   (STM32_UCPD_RXORDSETR_SHIFT))
-#define STM32_UCPD_RXORDSETR_VAL(x)       ((x) << STM32_UCPD_RXORDSETR_SHIFT)
-#define STM32_UCPD_RXSOP3OF4              BIT(3)
-#define STM32_UCPD_RXSOPKINVALID_SHIFT    4
-#define STM32_UCPD_RXSOPKINVALID_MASK     ((0x7) << \
-					   (STM32_UCPD_RXSOPKINVALID_SHIFT))
-#define STM32_UCPD_RXSOPKINVALID_VAL(x)   ((x) << \
-					   STM32_UCPD_RXSOPKINVALID_SHIFT)
-
-/* --- UCPD RX_PAYSZR Bit Definitions --- */
-#define STM32_UCPD_RX_PAYSZR_SHIFT        0
-#define STM32_UCPD_RX_PAYSZR_MASK         ((0x3ff) << \
-					   (STM32_UCPD_RX_PAYSZR_SHIFT))
-#define STM32_UCPD_RX_PAYSZR_VAL(x)       ((x) << STM32_UCPD_RX_PAYSZR_SHIFT)
-
-/* --- UCPD TXDR Bit Definitions --- */
-#define STM32_UCPD_RXDR_SHIFT             0
-#define STM32_UCPD_RXDR_MASK              ((0xff) << \
-					   (STM32_UCPD_RXDR_SHIFT))
-#define STM32_UCPD_RXDR_VAL(x)            ((x) << STM32_UCPD_RXDR_SHIFT)
-
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-
-/* --- USART bit definitions -- */
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_I2C3                0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_LPUART              0xC
-#define GPIO_ALT_SAI1                0xD
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define stm32g4_i2c_reg(base, offset) ((uint16_t *)((base) + (offset)))
-
-#define STM32_I2C_CR1(base)            REG32(stm32g4_i2c_reg(base, 0x00))
-#define STM32_I2C_CR2(base)            REG32(stm32g4_i2c_reg(base, 0x04))
-#define STM32_I2C_OAR1(base)           REG16(stm32g4_i2c_reg(base, 0x08))
-#define STM32_I2C_OAR2(base)           REG16(stm32g4_i2c_reg(base, 0x0C))
-#define STM32_I2C_TIMINGR(base)        REG32(stm32g4_i2c_reg(base, 0x10))
-#define STM32_I2C_TIMEOUTR(base)       REG32(stm32g4_i2c_reg(base, 0x14))
-#define STM32_I2C_ISR(base)            REG32(stm32g4_i2c_reg(base, 0x18))
-#define STM32_I2C_ICR(base)            REG32(stm32g4_i2c_reg(base, 0x1C))
-#define STM32_I2C_PECR(base)           REG32(stm32g4_i2c_reg(base, 0x20))
-#define STM32_I2C_RXDR(base)           REG32(stm32g4_i2c_reg(base, 0x24))
-#define STM32_I2C_TXDR(base)           REG32(stm32g4_i2c_reg(base, 0x28))
-
-/* --- I2C CR1 Bit Definitions --- */
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-
-/* --- I2C CR2 Bit Definitions --- */
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-
-/* --- I2C ISR Bit Definitions --- */
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-
-/* --- I2C ICR Bit Definitions --- */
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-
-/* --- I2C TIMINGR bit Definitions --- */
-#define STM32_I2C_TIMINGR_SCLL_OFF 0
-#define STM32_I2C_TIMINGR_SCLH_OFF 8
-#define STM32_I2C_TIMINGR_SDADEL_OFF 16
-#define STM32_I2C_TIMINGR_SCLDEL_OFF 20
-#define STM32_I2C_TIMINGR_PRESC_OFF 28
-
-/* --- Power / Reset / Clocks --- */
-
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR                 REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_CIER                  REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR                  REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR                  REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_APB1RSTR1             REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2             REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_APB1ENR1              REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2              REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_AHB1SMENR             REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR             REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR             REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_APB1SMENR1            REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2            REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR             REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_CCIPR                 REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR                 REG32(STM32_RCC_BASE + 0x98)
-#define STM32_RCC_CCIPR2                REG32(STM32_RCC_BASE + 0x9C)
-
-#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1
-#define STM32_RCC_AHBENR STM32_RCC_APB1ENR
-
-/* --- RCC CR Bit Definitions --- */
-#define STM32_RCC_CR_HSION		BIT(8)
-#define STM32_RCC_CR_HSIRDY		BIT(10)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-
-/* --- RCC PLLCFGR Bit Definitions --- */
-#define  PLLCFGR_PLLSRC_OFF		0
-#define  PLLCFGR_PLLSRC(val)		(((val) & 0x3) << PLLCFGR_PLLSRC_OFF)
-#define  PLLCFGR_PLLSRC_HSI		2
-#define  PLLCFGR_PLLSRC_HSE		3
-/* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		4
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
-/* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		8
-#define  PLLCFGR_PLLN(val)		(((val) & 0x7f) << PLLCFGR_PLLN_OFF)
-#define  PLLCFGR_PLLQ_EN		BIT(20)
-#define  PLLCFGR_PLLQ_OFF		21
-#define  PLLCFGR_PLLQ(val)		(((val) & 0x3) << PLLCFGR_PLLQ_OFF)
-/* System and main CPU clock */
-#define  PLLCFGR_PLLR_EN		BIT(24)
-#define  PLLCFGR_PLLR_OFF		25
-#define  PLLCFGR_PLLR(val)		(((val) & 0x3) << PLLCFGR_PLLR_OFF)
-#define  PLLCFGR_PLLP_OFF		27
-#define  PLLCFGR_PLLP(val)		(((val) & 0x1f) << PLLCFGR_PLLP_OFF)
-
-/* --- RCC CFGR Bit Definitions --- */
-#define STM32_RCC_CFGR_SW_HSI		(1 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(1 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-/* AHB Prescalar: */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
-/* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			8
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
-/* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			11
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
-/* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
-
-/* --- RCC AHB1ENR Bit Definitions --- */
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(0)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(1)
-#define STM32_RCC_AHB1ENR_DMAMUXEN	BIT(2)
-
-/* --- RCC AHB2ENR Bit Definitions --- */
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTF	BIT(5)
-#define STM32_RCC_AHB2ENR_GPIO_PORTG	BIT(6)
-#define STM32_RCC_AHB2ENR_GPIOMASK	(0x7f << 0)
-#define STM32_RCC_AHB2ENR_ADC12EN	BIT(13)
-#define STM32_RCC_APB2ENR_ADC345EN	BIT(14)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(26)
-
-/* --- RCC APB1ENR1 Bit Definitions --- */
-#define STM32_RCC_APB1ENR1_TIM2EN                BIT(0)
-#define STM32_RCC_APB1ENR1_TIM3EN                BIT(1)
-#define STM32_RCC_APB1ENR1_TIM4EN                BIT(2)
-#define STM32_RCC_APB1ENR1_TIM5EN                BIT(3)
-#define STM32_RCC_APB1ENR1_TIM6EN                BIT(4)
-#define STM32_RCC_APB1ENR1_TIM7EN                BIT(5)
-#define STM32_RCC_APB1ENR1_WWDGEN                BIT(11)
-#define STM32_RCC_APB1ENR1_USART2                BIT(17)
-#define STM32_RCC_APB1ENR1_USART3                BIT(18)
-#define STM32_RCC_APB1ENR1_UART4                 BIT(19)
-#define STM32_RCC_APB1ENR1_UART5                 BIT(20)
-#define STM32_RCC_APB1ENR1_I2C1EN                BIT(21)
-#define STM32_RCC_APB1ENR1_I2C2EN                BIT(22)
-#define STM32_RCC_APB1ENR1_USBEN                 BIT(23)
-#define STM32_RCC_APB1ENR1_PWREN                 BIT(28)
-#define STM32_RCC_APB1ENR1_I2C3EN                BIT(30)
-
-#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
-
-/* --- RCC APB1ENR2 Bit Definitions --- */
-#define STM32_RCC_APB1ENR2_LPUART1EN             BIT(0)
-#define STM32_RCC_APB1ENR2_I2C4EN                BIT(1)
-#define STM32_RCC_APB1ENR2_UPCD1EN               BIT(8)
-
-/* --- RCC APB2ENR Bit Definitions --- */
-#define STM32_RCC_APB2ENR_SYSCFGEN	BIT(0)
-#define STM32_RCC_APB2ENR_TIM1		BIT(11)
-#define STM32_RCC_APB2ENR_SPI1EN	BIT(12)
-#define STM32_RCC_APB2ENR_TIM8		BIT(13)
-#define STM32_RCC_APB2ENR_USART1        BIT(14)
-#define STM32_RCC_APB2ENR_SPI4EN	BIT(15)
-#define STM32_RCC_APB2ENR_TIM15	BIT(16)
-#define STM32_RCC_APB2ENR_TIM16	BIT(17)
-#define STM32_RCC_APB2ENR_TIM17	BIT(18)
-#define STM32_RCC_APB2ENR_TIM20	BIT(20)
-
-#define STM32_RCC_PB2_USART1		STM32_RCC_APB2ENR_USART1
-
-/* gpio.c needs STM32_RCC_SYSCFGEN */
-#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN
-
-/* --- RCC APB1RSTR1 Bit Definitions --- */
-#define STM32_RCC_APB1RSTR1_USB_RST     BIT(23)
-#define STM32_RCC_APB1RSTR              STM32_RCC_APB1RSTR1
-#define STM32_RCC_PB1_USB               STM32_RCC_APB1RSTR1_USB_RST
-
-/* --- RCC CSR Bit Definitions --- */
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-/* --- RCC CCIPR Bit Definitions --- */
-#define STM32_RCC_CCIPR_UART_SYSCLK      0x1
-#define STM32_RCC_CCIPR_USART1SEL_MASK   0x3
-#define STM32_RCC_CCIPR_USART1SEL_SHIFT  0
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  0x3
-#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT 10
-#define STM32_RCC_CCIPR_I2C1SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C1SEL_SHIFT    12
-#define STM32_RCC_CCIPR_I2C2SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C2SEL_SHIFT    14
-#define STM32_RCC_CCIPR_I2C3SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C3SEL_SHIFT    16
-
-#define STM32_RCC_CCIPR2_I2C4SEL_MASK    0x3
-
-#define STM32_RCC_CCIPR_I2CNSEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2CNSEL_SHIFT(n) (STM32_RCC_CCIPR_I2C1SEL_SHIFT + n * 2)
-#define STM32_RCC_CCIPR_I2CNSEL_HSI      0x2
-/* --- RCC CRRCR Bit Definitions */
-#define RCC_CRRCR_HSI48O               BIT(0)
-#define RCC_CRRCR_HSIRDY               BIT(1)
-
-/* Reset causes definitions */
-/*
- * Reset causes in RCC CSR register. The generic names are required
- */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define STM32_RCC_CSR_RMVF              BIT(24)
-#define STM32_RCC_CSR_BORRS             BIT(25)
-#define STM32_RCC_CSR_PIN               BIT(26)
-#define STM32_RCC_CSR_POR               BIT(27)
-#define STM32_RCC_CSR_SFT               BIT(28)
-#define STM32_RCC_CSR_IWDG              BIT(29)
-#define STM32_RCC_CSR_WWDG              BIT(30)
-#define STM32_RCC_CSR_LPWR              BIT(31)
-
-
-#define  RESET_CAUSE_WDG                (STM32_RCC_CSR_WWDG | \
-					 STM32_RCC_CSR_IWDG)
-#define  RESET_CAUSE_SFT                STM32_RCC_CSR_SFT
-#define  RESET_CAUSE_POR                STM32_RCC_CSR_POR
-#define  RESET_CAUSE_PIN                STM32_RCC_CSR_PIN
-#define  RESET_CAUSE_RMVF               STM32_RCC_CSR_RMVF
-#define  RESET_CAUSE_OTHER              (STM32_RCC_CSR_LPWR | \
-					 STM32_RCC_CSR_BORRS)
-/* Power cause in PWR CSR register */
-#define STM32_PWR_CR1                   REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2                   REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CR3                   REG32(STM32_PWR_BASE + 0x08)
-#define STM32_PWR_CR4                   REG32(STM32_PWR_BASE + 0x0C)
-#define STM32_PWR_SR1                   REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SR2                   REG32(STM32_PWR_BASE + 0x14)
-#define STM32_PWR_SCR                   REG32(STM32_PWR_BASE + 0x18)
-#define STM32_PWR_SCR_CSBF              BIT(8)
-#define STM32_PWR_SR1_SBF               BIT(8)
-
-#define STM32_PWR_RESET_CAUSE STM32_PWR_SR1
-#define  RESET_CAUSE_SBF                STM32_PWR_SR1_SBF
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR
-#define  RESET_CAUSE_SBF_CLR            STM32_PWR_SCR_CSBF
-
-#define STM32_PWR_CR1_DBP               BIT(8)
-
-#define STM32_PWR_CR3_UCPD1_STDBY       BIT(13)
-#define STM32_PWR_CR3_UCPD1_DBDIS       BIT(14)
-
-/* --- System Config Registers --- */
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x18)
-
-
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_CALR              REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_SHIFTR            REG32(STM32_RTC_BASE + 0x2C)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TSSSR             REG32(STM32_RTC_BASE + 0x38)
-
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x48)
-#define STM32_RTC_ALRMBSSR          REG32(STM32_RTC_BASE + 0x44)
-
-/* --- RTC CR Bit Definitions --- */
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-/* --- RTC ICSR Bit Definitions --- */
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-/* --- RTC PRER Bit Definitions --- */
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-
-
-/* --- Tamper and Backup --- */
-#define STM32_TAMP_BKPxR(n)         REG32(STM32_TAMP_BASE + 0x100 + 4 * (n))
-#define STM32_BKP_DATA(n)           STM32_TAMP_BKPxR(n)
-#define STM32_BKP_BYTES             64
-
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned int crcpr;
-	unsigned int rxcrcr;
-	unsigned int txcrcr;
-	unsigned int i2scfgr;
-	unsigned int i2spr;
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-
-/* --- Debug --- */
-#define STM32_DBGMCU_IDCODE         REG32(STM32_DBGMCU_BASE + 0x00)
-#define STM32_DBGMCU_CR             REG32(STM32_DBGMCU_BASE + 0x04)
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- DBGMCU CR Bit Definitions --- */
-#define  STM32_DBGMCU_CR_SLEEP                      BIT(0)
-#define  STM32_DBGMCU_CR_STOP                       BIT(1)
-#define  STM32_DBGMCU_CR_STBY                       BIT(2)
-#define  STM32_DBGMCU_CR_TRACE_MASK                 (BIT(5)|BIT(6)|BIT(7))
-#define   STM32_DBGMCU_CR_TRACE_EN                   BIT(5)
-#define   STM32_DBGMCU_CR_TRACE_MODE_ASYNC           0
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC1           BIT(6)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC2           BIT(7)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC4           (BIT(6)|BIT(7))
-/* --- DBGMCU APB1FZ Bit Definitions --- */
-#define  STM32_DBGMCU_APB1FZ_TIM2                   BIT(0)
-#define  STM32_DBGMCU_APB1FZ_TIM3                   BIT(1)
-#define  STM32_DBGMCU_APB1FZ_TIM4                   BIT(2)
-#define  STM32_DBGMCU_APB1FZ_TIM5                   BIT(3)
-#define  STM32_DBGMCU_APB1FZ_TIM6                   BIT(4)
-#define  STM32_DBGMCU_APB1FZ_TIM7                   BIT(5)
-#define  STM32_DBGMCU_APB1FZ_RTC                    BIT(10)
-#define  STM32_DBGMCU_APB1FZ_WWDG                   BIT(11)
-#define  STM32_DBGMCU_APB1FZ_IWDG                   BIT(12)
-#define  STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT     BIT(21)
-#define  STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT     BIT(22)
-#define  STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT     BIT(30)
-/* --- DBGMCU  APB2FZ Bit Definitions --- */
-#define  STM32_DBGMCU_APB2FZ_TIM1                   BIT(11)
-#define  STM32_DBGMCU_APB2FZ_TIM8                   BIT(13)
-#define  STM32_DBGMCU_APB2FZ_TIM15                  BIT(16)
-#define  STM32_DBGMCU_APB2FZ_TIM16                  BIT(17)
-#define  STM32_DBGMCU_APB2FZ_TIM17                  BIT(18)
-#define  STM32_DBGMCU_APB2FZ_TIM20                  BIT(20)
-
-/* --- Flash --- */
-#define STM32_FLASH_REG(off)        REG32(STM32_FLASH_REGS_BASE + (off))
-#define STM32_FLASH_ACR             STM32_FLASH_REG(0x00)
-#define STM32_FLASH_PDKEYR          STM32_FLASH_REG(0x04)
-#define STM32_FLASH_KEYR            STM32_FLASH_REG(0x08)
-#define STM32_FLASH_OPTKEYR         STM32_FLASH_REG(0x0c)
-#define STM32_FLASH_SR              STM32_FLASH_REG(0x10)
-#define STM32_FLASH_CR              STM32_FLASH_REG(0x14)
-#define STM32_FLASH_ECCR            STM32_FLASH_REG(0x18)
-/*
- * Bank 1 Option Byte Copy Registers. These registers are loaded from the option
- * bytes location in flash at reset, assuming that option byte loading has not
- * been disabled.
- */
-#define STM32_FLASH_OPTR            STM32_FLASH_REG(0x20)
-#define STM32_FLASH_PCROP1SR        STM32_FLASH_REG(0x24)
-#define STM32_FLASH_PCROP1ER        STM32_FLASH_REG(0x28)
-#define STM32_FLASH_WRP1AR          STM32_FLASH_REG(0x2C)
-#define STM32_FLASH_WRP1BR          STM32_FLASH_REG(0x30)
-/*
- * Bank 2 Option Byte Copy Registers. These will only exist for category 3
- * devices.
- */
-#define STM32_FLASH_PCROP2SR        STM32_FLASH_REG(0x44)
-#define STM32_FLASH_PCROP2ER        STM32_FLASH_REG(0x48)
-#define STM32_FLASH_WRP2AR          STM32_FLASH_REG(0x4C)
-#define STM32_FLASH_WRP2BR          STM32_FLASH_REG(0x50)
-
-#define STM32_FLASH_SEC_SIZE1       STM32_FLASH_REG(0x70)
-#define STM32_FLASH_SEC_SIZE2       STM32_FLASH_REG(0x74)
-
-/* --- FLASH CR Bit Definitions --- */
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (0xf << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
-
-/* --- FLASH KEYR Bit Definitions --- */
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
-
-/* --- FLASH OPTKEYR Bit Definitions --- */
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
-
-/* --- FLASH SR Bit Definitions --- */
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_OPTVERR           BIT(15)
-#define  FLASH_SR_RDERR             BIT(14)
-#define  FLASH_SR_FASTERR           BIT(9)
-#define  FLASH_SR_MISERR            BIT(8)
-#define  FLASH_SR_PGSERR            BIT(7)
-#define  FLASH_SR_SIZERR            BIT(6)
-#define  FLASH_SR_PGAERR            BIT(5)
-#define  FLASH_SR_WRPERR            BIT(4)
-#define  FLASH_SR_PROGERR           BIT(3)
-#define  FLASH_SR_OPERR             BIT(1)
-#define  FLASH_SR_ERR_MASK          (FLASH_SR_OPTVERR | FLASH_SR_RDERR | \
-				     FLASH_SR_FASTERR | FLASH_SR_PGSERR | \
-				     FLASH_SR_SIZERR | FLASH_SR_PGAERR |  \
-				     FLASH_SR_WRPERR |  FLASH_SR_PROGERR | \
-				     FLASH_SR_OPERR)
-
-/* --- FLASH CR Bit Definitions --- */
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0x7f) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0x7f)
-
-#define STM32_FLASH_MIN_WRITE_SIZE  (CONFIG_FLASH_WRITE_SIZE * 2)
-
-/* --- FLASH Option bytes --- */
-#define STM32_OPTB_USER_RDP         REG32(STM32_OPTB_BANK1_BASE + 0x00)
-#define STM32_OPTB_PCROP1_START     REG32(STM32_OPTB_BANK1_BASE + 0x08)
-#define STM32_OPTB_PCROP1_END       REG32(STM32_OPTB_BANK1_BASE + 0x10)
-#define STM32_OPTB_WRP1AR           REG32(STM32_OPTB_BANK1_BASE + 0x18)
-#define STM32_OPTB_WRP1BR           REG32(STM32_OPTB_BANK1_BASE + 0x20)
-#define STM32_OPTB_SECURE1_MEM      REG32(STM32_OPTB_BANK1_BASE + 0x28)
-
-#define STM32_OPTB_UNUSED           REG32(STM32_OPTB_BANK2_BASE + 0x00)
-#define STM32_OPTB_PCROP2_START     REG32(STM32_OPTB_BANK2_BASE + 0x08)
-#define STM32_OPTB_PCROP2_END       REG32(STM32_OPTB_BANK2_BASE + 0x10)
-#define STM32_OPTB_WRP2AR           REG32(STM32_OPTB_BANK2_BASE + 0x18)
-#define STM32_OPTB_WRP2BR           REG32(STM32_OPTB_BANK2_BASE + 0x20)
-#define STM32_OPTB_SECURE2_MEM      REG32(STM32_OPTB_BANK2_BASE + 0x28)
-
-/* Read option bytes from flash memory for Bank 1 */
-#define STM32_OPTB_BANK1_READ(n)      REG32(STM32_OPTB_BANK1_BASE + ((n) * 8))
-#define STM32_OPTB_BANK1_COMP_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n) * 8) + 0x4)
-#define STM32_OPTB_BANK2_READ(n)      REG32(STM32_OPTB_BANK2_BASE + ((n) * 8))
-#define STM32_OPTB_BANK2_COMP_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n) * 8) + 0x4)
-
-#define STM32_OPTB_USER_DBANK       BIT(22)
-#define STM32_OPTB_USER_nBOOT1      BIT(23)
-#define STM32_OPTB_USER_nSWBOOT0    BIT(26)
-#define STM32_OPTB_USER_nBOOT0      BIT(27)
-#define STM32_OPTB_ENTRY_NUM 6
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT BIT(17)
-
-/* --- ADC --- */
-#define STM32_ADC_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
-#define STM32_ADC_TR1              REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_TR2              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_TR3              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_SQR4             REG32(STM32_ADC1_BASE + 0x3C)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4)
-
-
-/* --- ADC CR Bit Definitions --- */
-#define STM32_ADC_CR_ADEN          BIT(0)
-#define STM32_ADC_CR_ADSTART       BIT(2)
-#define STM32_ADC_CR_ADVREGEN      BIT(28)
-#define STM32_ADC_CR_CAL           BIT(31)
-
-#define STM32_ADC_CFGR_CONT        BIT(13)
-#define STM32_ADC_CR2_ALIGN        BIT(15)
-
-/* --- Comparators --- */
-
-
-/* --- DMA --- */
-/*
- * Available DMA streams, numbered from 0.
- *
- *
- * Channels 0 - 5 are managed by controller DMA1, 6 - 11 by DMA2.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-
-	/* Channel functions */
-	STM32_DMAC_ADC = STM32_DMAC_CH1,
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2,
-	STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3,
-	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
-	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH10,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH11,
-	STM32_DMAC_USART3_RX = STM32_DMAC_CH12,
-	STM32_DMAC_USART3_TX = STM32_DMAC_CH13,
-	STM32_DMAC_I2C1_TX = STM32_DMAC_CH5,
-	STM32_DMAC_I2C1_RX = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
-	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
-	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
-	STM32_DMAC_LPUART_RX = STM32_DMAC_CH9,
-	STM32_DMAC_LPUART_TX = STM32_DMAC_CH10,
-	STM32_DMAC_COUNT = 14,
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-#define STM32_REQ_USART1_TX 4
-#define STM32_REQ_USART1_RX 4
-
-#define STM32_REQ_USART2_TX 4
-#define STM32_REQ_USART2_RX 4
-
-#define STM32_I2C1_TX_REQ_CH 1
-#define STM32_I2C1_RX_REQ_CH 1
-
-#define STM32_I2C2_TX_REQ_CH 7
-#define STM32_I2C2_RX_REQ_CH 7
-
-#define STM32_I2C3_TX_REQ_CH 3
-#define STM32_I2C3_RX_REQ_CH 1
-
-#define STM32_FMPI2C4_TX_REQ_CH 2
-#define STM32_FMPI2C4_RX_REQ_CH 2
-
-#define STM32_SPI1_TX_REQ_CH 3
-#define STM32_SPI1_RX_REQ_CH 3
-#define STM32_SPI2_TX_REQ_CH 0
-#define STM32_SPI2_RX_REQ_CH 0
-#define STM32_SPI3_TX_REQ_CH 0
-#define STM32_SPI3_RX_REQ_CH 0
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */
-/* DMAMUX registers */
-#define STM32_DMAMUX_CxCR(x)      REG32(STM32_DMAMUX_BASE + 4 * (x))
-#define STM32_DMAMUX_CSR          REG32(STM32_DMAMUX_BASE + 0x80)
-#define STM32_DMAMUX_CFR          REG32(STM32_DMAMUX_BASE + 0x84)
-#define STM32_DMAMUX_RGxCR(x)     REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x))
-#define STM32_DMAMUX_RGSR         REG32(STM32_DMAMUX_BASE + 0x140)
-#define STM32_DMAMUX_RGCFR        REG32(STM32_DMAMUX_BASE + 0x144)
-
-enum dmamux1_request {
-	DMAMUX_REQ_ADC1 = 5,
-	DMAMUX_REQ_DAC1_CH1 = 6,
-	DMAMUX_REQ_DAC1_CH2 = 7,
-	DMAMUX_REQ_TIM6_UP = 8,
-	DMAMUX_REQ_TIM7_UP = 9,
-	DMAMUX_REQ_SPI1_RX = 10,
-	DMAMUX_REQ_SPI1_TX = 11,
-	DMAMUX_REQ_SPI2_RX = 12,
-	DMAMUX_REQ_SPI2_TX = 13,
-	DMAMUX_REQ_SPI3_RX = 14,
-	DMAMUX_REQ_SPI3_TX = 15,
-	DMAMUX_REQ_I2C1_RX = 16,
-	DMAMUX_REQ_I2C1_TX = 17,
-	DMAMUX_REQ_I2C2_RX = 18,
-	DMAMUX_REQ_I2C2_TX = 19,
-	DMAMUX_REQ_I2C3_RX = 20,
-	DMAMUX_REQ_I2C3_TX = 21,
-	DMAMUX_REQ_I2C4_RX = 22,
-	DMAMUX_REQ_I2C4_TX = 23,
-	DMAMUX_REQ_USART1_RX = 24,
-	DMAMUX_REQ_USART1_TX = 25,
-	DMAMUX_REQ_USART2_RX = 26,
-	DMAMUX_REQ_USART2_TX = 27,
-	DMAMUX_REQ_USART3_RX = 28,
-	DMAMUX_REQ_USART3_TX = 29,
-	DMAMUX_REQ_UART4_RX = 30,
-	DMAMUX_REQ_UART4_TX = 31,
-	DMAMUX_REQ_USART5_RX = 32,
-	DMAMUX_REQ_UART5_TX = 33,
-	DMAMUX_REQ_LPUART1_RX = 34,
-	DMAMUX_REQ_LPUART1_TX = 35,
-	DMAMUX_REQ_ADC2 = 36,
-	DMAMUX_REQ_ADC3 = 37,
-	DMAMUX_REQ_ADC4 = 38,
-	DMAMUX_REQ_ADC5 = 39,
-	DMAMUX_REQ_QUADSPI = 40,
-	DMAMUX_REQ_DAC2_CH1 = 41,
-	DMAMUX_REQ_TIM1_CH1 = 42,
-	DMAMUX_REQ_TIM1_CH2 = 43,
-	DMAMUX_REQ_TIM1_CH3 = 44,
-	DMAMUX_REQ_TIM1_CH4 = 45,
-	DMAMUX_REQ_TIM1_UP = 46,
-	DMAMUX_REQ_TIM1_TRIG = 47,
-	DMAMUX_REQ_TIM1_COM = 48,
-	DMAMUX_REQ_TIM8_CH1 = 49,
-	DMAMUX_REQ_TIM8_CH2 = 50,
-	DMAMUX_REQ_TIM8_CH3 = 51,
-	DMAMUX_REQ_TIM8_CH4 = 52,
-	DMAMUX_REQ_TIM8_UP = 53,
-	DMAMUX_REQ_TIM8_TRIG = 54,
-	DMAMUX_REQ_TIM8_COM = 55,
-	DMAMUX_REQ_TIM2_CH1 = 56,
-	DMAMUX_REQ_TIM2_CH2 = 57,
-	DMAMUX_REQ_TIM2_CH3 = 58,
-	DMAMUX_REQ_TIM2_CH4 = 59,
-	DMAMUX_REQ_TIM2_UP = 60,
-	DMAMUX_REQ_TIM3_CH1 = 61,
-	DMAMUX_REQ_TIM3_CH2 = 62,
-	DMAMUX_REQ_TIM3_CH3 = 63,
-	DMAMUX_REQ_TIM3_CH4 = 64,
-	DMAMUX_REQ_TIM3_UP = 65,
-	DMAMUX_REQ_TIM3_TRIG = 66,
-	DMAMUX_REQ_TIM4_CH1 = 67,
-	DMAMUX_REQ_TIM4_CH2 = 68,
-	DMAMUX_REQ_TIM4_CH3 = 69,
-	DMAMUX_REQ_TIM4_CH4 = 70,
-	DMAMUX_REQ_TIM4_UP = 71,
-	DMAMUX_REQ_TIM5_CH1 = 72,
-	DMAMUX_REQ_TIM5_CH2 = 73,
-	DMAMUX_REQ_TIM5_CH3 = 74,
-	DMAMUX_REQ_TIM5_CH4 = 75,
-	DMAMUX_REQ_TIM5_UP = 76,
-	DMAMUX_REQ_TIM5_TRIG = 77,
-	DMAMUX_REQ_TIM15_CH1 = 78,
-	DMAMUX_REQ_TIM15_UP = 79,
-	DMAMUX_REQ_TIM15_TRIG = 80,
-	DMAMUX_REQ_TIM15_COM = 81,
-	DMAMUX_REQ_TIM16_CH1 = 82,
-	DMAMUX_REQ_TIM16_UP = 83,
-	DMAMUX_REQ_TIM17_CH1 = 84,
-	DMAMUX_REQ_TIM17_UP = 85,
-	DMAMUX_REQ_TIM20_CH1 = 86,
-	DMAMUX_REQ_TIM20_CH2 = 87,
-	DMAMUX_REQ_TIM20_CH3 = 88,
-	DMAMUX_REQ_TIM20_CH4 = 89,
-	DMAMUX_REQ_TIM20_UP = 90,
-	DMAMUX_REQ_AES_IN = 91,
-	DMAMUX_REQ_AES_OUT = 92,
-	DMAMUX_REQ_TIM20_TRIG = 93,
-	DMAMUX_REQ_TIM20_COM = 94,
-	DMAMUX_REQ_DAC3_CH1 = 102,
-	DMAMUX_REQ_DAC3_CH2 = 103,
-	DMAMUX_REQ_DAC4_CH1 = 104,
-	DMAMUX_REQ_DAC4_CH2 = 105,
-	DMAMUX_REQ_SPI4_RX = 106,
-	DMAMUX_REQ_SPI4_TX = 107,
-	DMAMUX_REQ_SAI1_A = 108,
-	DMAMUX_REQ_SAI1_B = 109,
-};
-/* LPUART gets accessed as UART9 in STM32 uart module */
-#define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX
-#define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-#define STM32_USB_BCDR_DPPU	    BIT(15)
-
-/* --- USB Endpoint bit definitions  --- */
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- RNG CR Bit Definitions --- */
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-/* --- RNG SR_DRDY Bit Definitions --- */
-#define STM32_RNG_SR_DRDY           BIT(0)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
-
diff --git a/chip/stm32/registers-stm32h7.h b/chip/stm32/registers-stm32h7.h
deleted file mode 100644
index d02aaf1249..0000000000
--- a/chip/stm32/registers-stm32h7.h
+++ /dev/null
@@ -1,1228 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32H7 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32H7X3
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-#define STM32_IRQ_LPTIM1         93
-#define STM32_IRQ_TIM15         116
-#define STM32_IRQ_TIM16         117
-#define STM32_IRQ_TIM17         118
-#define STM32_IRQ_LPTIM2        138
-#define STM32_IRQ_LPTIM3        139
-#define STM32_IRQ_LPTIM4        140
-#define STM32_IRQ_LPTIM5        141
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-
-/*
- * STM32F4 introduces a concept of DMA stream to allow
- * fine allocation of a stream to a channel.
- */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
-
-/* Peripheral base addresses */
-
-#define STM32_GPV_BASE              0x51000000
-
-#define STM32_DBGMCU_BASE           0x5C001000
-
-#define STM32_BDMA_BASE             0x58025400
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
-#define STM32_DMA2D_BASE            0x52001000
-#define STM32_DMAMUX1_BASE          0x40020800
-#define STM32_DMAMUX2_BASE          0x58025800
-#define STM32_MDMA_BASE             0x52000000
-
-#define STM32_EXTI_BASE             0x58000000
-
-#define STM32_FLASH_REGS_BASE       0x52002000
-
-#define STM32_GPIOA_BASE            0x58020000
-#define STM32_GPIOB_BASE            0x58020400
-#define STM32_GPIOC_BASE            0x58020800
-#define STM32_GPIOD_BASE            0x58020C00
-#define STM32_GPIOE_BASE            0x58021000
-#define STM32_GPIOF_BASE            0x58021400
-#define STM32_GPIOG_BASE            0x58021800
-#define STM32_GPIOH_BASE            0x58021C00
-#define STM32_GPIOI_BASE            0x58022000
-#define STM32_GPIOJ_BASE            0x58022400
-#define STM32_GPIOK_BASE            0x58022800
-
-#define STM32_IWDG_BASE             0x58004800
-
-#define STM32_LPTIM1_BASE           0x40002400
-#define STM32_LPTIM2_BASE           0x58002400
-#define STM32_LPTIM3_BASE           0x58002800
-#define STM32_LPTIM4_BASE           0x58002C00
-#define STM32_LPTIM5_BASE           0x58003000
-
-#define STM32_PWR_BASE              0x58024800
-#define STM32_RCC_BASE              0x58024400
-#define STM32_RNG_BASE              0x48021800
-#define STM32_RTC_BASE              0x58004000
-
-#define STM32_SYSCFG_BASE           0x58000400
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00
-#define STM32_SPI4_BASE             0x40013400
-#define STM32_SPI5_BASE             0x40015000
-
-#define STM32_TIM1_BASE             0x40010000
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM8_BASE             0x40010400
-#define STM32_TIM12_BASE            0x40001800
-#define STM32_TIM13_BASE            0x40001c00
-#define STM32_TIM14_BASE            0x40002000
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-
-#define STM32_UNIQUE_ID_BASE        0x1ff1e800
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-#define STM32_USART7_BASE           0x40007800
-#define STM32_USART8_BASE           0x40007C00
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)         STM32_USART_REG(base, 0x00)
-#define  STM32_USART_CR1_UE            BIT(0)
-#define  STM32_USART_CR1_UESM          BIT(1)
-#define  STM32_USART_CR1_RE            BIT(2)
-#define  STM32_USART_CR1_TE            BIT(3)
-#define  STM32_USART_CR1_RXNEIE        BIT(5)
-#define  STM32_USART_CR1_TCIE          BIT(6)
-#define  STM32_USART_CR1_TXEIE         BIT(7)
-#define  STM32_USART_CR1_PS            BIT(9)
-#define  STM32_USART_CR1_PCE           BIT(10)
-#define  STM32_USART_CR1_M             BIT(12)
-#define  STM32_USART_CR1_OVER8         BIT(15)
-#define STM32_USART_CR2(base)         STM32_USART_REG(base, 0x04)
-#define  STM32_USART_CR2_SWAP          BIT(15)
-#define STM32_USART_CR3(base)         STM32_USART_REG(base, 0x08)
-#define  STM32_USART_CR3_EIE           BIT(0)
-#define  STM32_USART_CR3_DMAR          BIT(6)
-#define  STM32_USART_CR3_DMAT          BIT(7)
-#define  STM32_USART_CR3_ONEBIT        BIT(11)
-#define  STM32_USART_CR3_OVRDIS        BIT(12)
-#define  STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define  STM32_USART_CR3_WUFIE         BIT(22)
-#define STM32_USART_BRR(base)         STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)        STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)        STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)         STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)         STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)         STM32_USART_REG(base, 0x20)
-#define  STM32_USART_ICR_ORECF         BIT(3)
-#define  STM32_USART_ICR_TCCF          BIT(6)
-#define STM32_USART_RDR(base)         STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)         STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)       STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)          STM32_USART_ISR(base)
-#define  STM32_USART_SR_ORE            BIT(3)
-#define  STM32_USART_SR_RXNE           BIT(5)
-#define  STM32_USART_SR_TC             BIT(6)
-#define  STM32_USART_SR_TXE            BIT(7)
-
-/* --- GPIO --- */
-
-
-#define STM32_GPIO_MODER(b)           REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)          REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)         REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)           REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)             REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)             REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)            REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)            REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)            REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)            REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)              REG16(stm32_i2c_reg(n, 0x00))
-#define  STM32_I2C_CR1_PE              BIT(0)
-#define  STM32_I2C_CR1_START           BIT(8)
-#define  STM32_I2C_CR1_STOP            BIT(9)
-#define  STM32_I2C_CR1_ACK             BIT(10)
-#define  STM32_I2C_CR1_POS             BIT(11)
-#define  STM32_I2C_CR1_SWRST           BIT(15)
-#define STM32_I2C_CR2(n)              REG16(stm32_i2c_reg(n, 0x04))
-#define  STM32_I2C_CR2_ITERREN         BIT(8)
-#define  STM32_I2C_CR2_ITEVTEN         BIT(9)
-#define  STM32_I2C_CR2_ITBUFEN         BIT(10)
-#define  STM32_I2C_CR2_DMAEN           BIT(11)
-#define  STM32_I2C_CR2_LAST            BIT(12)
-#define STM32_I2C_OAR1(n)             REG16(stm32_i2c_reg(n, 0x08))
-#define  STM32_I2C_OAR1_B14            BIT(14)
-#define STM32_I2C_OAR2(n)             REG16(stm32_i2c_reg(n, 0x0C))
-#define  STM32_I2C_OAR2_ENDUAL         BIT(0)
-#define STM32_I2C_DR(n)               REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)              REG16(stm32_i2c_reg(n, 0x14))
-#define  STM32_I2C_SR1_SB              BIT(0)
-#define  STM32_I2C_SR1_ADDR            BIT(1)
-#define  STM32_I2C_SR1_BTF             BIT(2)
-#define  STM32_I2C_SR1_STOPF           BIT(4)
-#define  STM32_I2C_SR1_RXNE            BIT(6)
-#define  STM32_I2C_SR1_TXE             BIT(7)
-#define  STM32_I2C_SR1_BERR            BIT(8)
-#define  STM32_I2C_SR1_ARLO            BIT(9)
-#define  STM32_I2C_SR1_AF              BIT(10)
-
-#define STM32_I2C_SR2(n)              REG16(stm32_i2c_reg(n, 0x18))
-#define  STM32_I2C_SR2_BUSY            BIT(1)
-#define  STM32_I2C_SR2_TRA             BIT(2)
-#define  STM32_I2C_SR2_DUALF           BIT(7)
-
-#define STM32_I2C_CCR(n)              REG16(stm32_i2c_reg(n, 0x1C))
-#define  STM32_I2C_CCR_DUTY            BIT(14)
-#define  STM32_I2C_CCR_FM              BIT(15)
-#define STM32_I2C_TRISE(n)            REG16(stm32_i2c_reg(n, 0x20))
-
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x08)
-#define STM32_PWR_CR3               REG32(STM32_PWR_BASE + 0x0C)
-#define  STM32_PWR_CR3_BYPASS        BIT(0)
-#define  STM32_PWR_CR3_LDOEN         BIT(1)
-#define  STM32_PWR_CR3_SCUEN         BIT(2)
-#define  STM32_PWR_CR3_VBE           BIT(8)
-#define  STM32_PWR_CR3_VBRS          BIT(9)
-#define  STM32_PWR_CR3_USB33DEN      BIT(24)
-#define  STM32_PWR_CR3_USBREGEN      BIT(25)
-#define  STM32_PWR_CR3_USB33RDY      BIT(26)
-#define STM32_PWR_CPUCR             REG32(STM32_PWR_BASE + 0x10)
-#define  STM32_PWR_CPUCR_PDDS_D1     BIT(0)
-#define  STM32_PWR_CPUCR_PDDS_D2     BIT(1)
-#define  STM32_PWR_CPUCR_PDDS_D3     BIT(2)
-#define  STM32_PWR_CPUCR_STOPF       BIT(5)
-#define  STM32_PWR_CPUCR_SBF         BIT(6)
-#define  STM32_PWR_CPUCR_SBF_D1      BIT(7)
-#define  STM32_PWR_CPUCR_SBF_D2      BIT(8)
-#define  STM32_PWR_CPUCR_CSSF        BIT(9)
-#define  STM32_PWR_CPUCR_RUN_D3      BIT(11)
-#define STM32_PWR_D3CR              REG32(STM32_PWR_BASE + 0x18)
-#define  STM32_PWR_D3CR_VOS1         (3 << 14)
-#define  STM32_PWR_D3CR_VOS2         (2 << 14)
-#define  STM32_PWR_D3CR_VOS3         (1 << 14)
-#define  STM32_PWR_D3CR_VOSMASK      (3 << 14)
-#define  STM32_PWR_D3CR_VOSRDY       (1 << 13)
-#define STM32_PWR_WKUPCR            REG32(STM32_PWR_BASE + 0x20)
-#define STM32_PWR_WKUPFR            REG32(STM32_PWR_BASE + 0x24)
-#define STM32_PWR_WKUPEPR           REG32(STM32_PWR_BASE + 0x28)
-
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x000)
-#define STM32_RCC_ICSCR             REG32(STM32_RCC_BASE + 0x004)
-#define STM32_RCC_CRRCR             REG32(STM32_RCC_BASE + 0x008)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x010)
-#define STM32_RCC_D1CFGR            REG32(STM32_RCC_BASE + 0x018)
-#define STM32_RCC_D2CFGR            REG32(STM32_RCC_BASE + 0x01C)
-#define STM32_RCC_D3CFGR            REG32(STM32_RCC_BASE + 0x020)
-#define STM32_RCC_PLLCKSELR         REG32(STM32_RCC_BASE + 0x028)
-#define STM32_RCC_PLLCFGR           REG32(STM32_RCC_BASE + 0x02C)
-#define STM32_RCC_PLL1DIVR          REG32(STM32_RCC_BASE + 0x030)
-#define STM32_RCC_PLL1FRACR         REG32(STM32_RCC_BASE + 0x034)
-#define STM32_RCC_PLL2DIVR          REG32(STM32_RCC_BASE + 0x038)
-#define STM32_RCC_PLL2FRACR         REG32(STM32_RCC_BASE + 0x03C)
-#define STM32_RCC_PLL3DIVR          REG32(STM32_RCC_BASE + 0x040)
-#define STM32_RCC_PLL3FRACR         REG32(STM32_RCC_BASE + 0x044)
-#define STM32_RCC_D1CCIPR           REG32(STM32_RCC_BASE + 0x04C)
-#define STM32_RCC_D2CCIP1R          REG32(STM32_RCC_BASE + 0x050)
-#define STM32_RCC_D2CCIP2R          REG32(STM32_RCC_BASE + 0x054)
-#define STM32_RCC_D3CCIPR           REG32(STM32_RCC_BASE + 0x058)
-#define STM32_RCC_CIER              REG32(STM32_RCC_BASE + 0x060)
-#define STM32_RCC_CIFR              REG32(STM32_RCC_BASE + 0x064)
-#define STM32_RCC_CICR              REG32(STM32_RCC_BASE + 0x068)
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x070)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x074)
-
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x098)
-
-#define STM32_RCC_RSR               REG32(STM32_RCC_BASE + 0x0D0)
-#define STM32_RCC_AHB3ENR           REG32(STM32_RCC_BASE + 0x0D4)
-#define STM32_RCC_AHB1ENR           REG32(STM32_RCC_BASE + 0x0D8)
-#define STM32_RCC_AHB2ENR           REG32(STM32_RCC_BASE + 0x0DC)
-#define STM32_RCC_AHB2ENR_RNGEN     BIT(6)
-#define STM32_RCC_AHB2ENR_HASHEN    BIT(5)
-#define STM32_RCC_AHB2ENR_CRYPTEN   BIT(4)
-#define STM32_RCC_AHB4ENR           REG32(STM32_RCC_BASE + 0x0E0)
-#define STM32_RCC_AHB4ENR_GPIOMASK  0x3ff
-#define STM32_RCC_APB3ENR           REG32(STM32_RCC_BASE + 0x0E4)
-#define STM32_RCC_APB1LENR          REG32(STM32_RCC_BASE + 0x0E8)
-#define STM32_RCC_APB1HENR          REG32(STM32_RCC_BASE + 0x0EC)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x0F0)
-#define STM32_RCC_APB4ENR           REG32(STM32_RCC_BASE + 0x0F4)
-#define STM32_RCC_SYSCFGEN          BIT(1)
-#define STM32_RCC_AHB3LPENR         REG32(STM32_RCC_BASE + 0x0FC)
-#define STM32_RCC_AHB1LPENR         REG32(STM32_RCC_BASE + 0x100)
-#define STM32_RCC_AHB2LPENR         REG32(STM32_RCC_BASE + 0x104)
-#define STM32_RCC_AHB4LPENR         REG32(STM32_RCC_BASE + 0x108)
-#define STM32_RCC_APB3LPENR         REG32(STM32_RCC_BASE + 0x10C)
-#define STM32_RCC_APB1LLPENR        REG32(STM32_RCC_BASE + 0x110)
-#define STM32_RCC_APB1HLPENR        REG32(STM32_RCC_BASE + 0x114)
-#define STM32_RCC_APB2LPENR         REG32(STM32_RCC_BASE + 0x118)
-#define STM32_RCC_APB4LPENR         REG32(STM32_RCC_BASE + 0x11C)
-/* Aliases */
-#define STM32_RCC_APB1ENR           STM32_RCC_APB1LENR
-
-#define STM32_RCC_CR_HSION                     BIT(0)
-#define STM32_RCC_CR_HSIRDY                    BIT(2)
-#define STM32_RCC_CR_CSION                     BIT(7)
-#define STM32_RCC_CR_CSIRDY                    BIT(8)
-#define STM32_RCC_CR_HSI48ON                   BIT(12)
-#define STM32_RCC_CR_HSI48RDY                  BIT(13)
-#define STM32_RCC_CR_PLL1ON                    BIT(24)
-#define STM32_RCC_CR_PLL1RDY                   BIT(25)
-#define STM32_RCC_CR_PLL2ON                    BIT(26)
-#define STM32_RCC_CR_PLL2RDY                   BIT(27)
-#define STM32_RCC_CR_PLL3ON                    BIT(28)
-#define STM32_RCC_CR_PLL3RDY                   BIT(29)
-#define STM32_RCC_CFGR_SW_HSI                  (0 << 0)
-#define STM32_RCC_CFGR_SW_CSI                  (1 << 0)
-#define STM32_RCC_CFGR_SW_HSE                  (2 << 0)
-#define STM32_RCC_CFGR_SW_PLL1                 (3 << 0)
-#define STM32_RCC_CFGR_SW_MASK                 (3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI                 (0 << 3)
-#define STM32_RCC_CFGR_SWS_CSI                 (1 << 3)
-#define STM32_RCC_CFGR_SWS_HSE                 (2 << 3)
-#define STM32_RCC_CFGR_SWS_PLL1                (3 << 3)
-#define STM32_RCC_CFGR_SWS_MASK                (3 << 3)
-#define STM32_RCC_D1CFGR_HPRE_DIV1             (0 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV2             (8 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV4             (9 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV8            (10 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV16           (11 << 0)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV1           (0 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV2           (4 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV4           (5 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV8           (6 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV16          (7 << 4)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV1           (0 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV2           (8 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV4           (9 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV8          (10 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV16         (1BIT(8))
-#define STM32_RCC_PLLCKSEL_PLLSRC_HSI          (0 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_CSI          (1 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_HSE          (2 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_NONE         (3 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_MASK         (3 << 0)
-#define STM32_RCC_PLLCKSEL_DIVM1(m)            ((m) << 4)
-#define STM32_RCC_PLLCKSEL_DIVM2(m)            ((m) << 12)
-#define STM32_RCC_PLLCKSEL_DIVM3(m)            ((m) << 20)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN     BIT(0)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE       (0 << 1)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM     BIT(1)
-#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M         (0 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M         (1 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M         (2 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M        (3 << 2)
-#define STM32_RCC_PLLCFG_DIVP1EN               BIT(16)
-#define STM32_RCC_PLLCFG_DIVQ1EN               BIT(17)
-#define STM32_RCC_PLLCFG_DIVR1EN               BIT(18)
-#define STM32_RCC_PLLDIV_DIVN(n)               (((n) - 1) << 0)
-#define STM32_RCC_PLLDIV_DIVP(p)               (((p) - 1) << 9)
-#define STM32_RCC_PLLDIV_DIVQ(q)               (((q) - 1) << 16)
-#define STM32_RCC_PLLDIV_DIVR(r)               (((r) - 1) << 24)
-#define STM32_RCC_PLLFRAC(n)                   ((n) << 3)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q     (0 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P     (1 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P     (2 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN   (3 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK     (4 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK      (7 << 12)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_APB        (0 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q      (1 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q      (2 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI        (3 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI        (4 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE        (5 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK       (7 << 16)
-#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK  (0 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_PLL2Q (1 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_PLL3Q (2 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_HSI   (3 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_CSI   (4 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_LSE   (5 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_MASK  (7 << 0)
-#define STM32_RCC_D2CCIP2_USART16SEL_PCLK      (0 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q     (1 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q     (2 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_HSI       (3 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_CSI       (4 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_LSE       (5 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_MASK      (7 << 3)
-#define STM32_RCC_D2CCIP2_RNGSEL_HSI48         (0 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q         (1 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_LSE           (2 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_LSI           (3 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_MASK          (3 << 8)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK       (0 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2       (1 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3       (2 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE        (3 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI        (4 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER        (5 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK       (7 << 28)
-#define STM32_RCC_CSR_LSION                    BIT(0)
-#define STM32_RCC_CSR_LSIRDY                   BIT(1)
-
-#define STM32_SYSCFG_PMCR           REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-
-/* Peripheral bits for APB1ENR regs */
-#define STM32_RCC_PB1_LPTIM1            BIT(9)
-
-/* Peripheral bits for APB2ENR regs */
-#define STM32_RCC_PB2_TIM1              BIT(0)
-#define STM32_RCC_PB2_TIM2              BIT(1)
-#define STM32_RCC_PB2_USART1            BIT(4)
-#define STM32_RCC_PB2_SPI1              BIT(12)
-#define STM32_RCC_PB2_SPI4              BIT(13)
-#define STM32_RCC_PB2_TIM15             BIT(16)
-#define STM32_RCC_PB2_TIM16             BIT(17)
-#define STM32_RCC_PB2_TIM17             BIT(18)
-
-/* Peripheral bits for AHB1/2/3/4ENR regs */
-#define STM32_RCC_HB1_DMA1              BIT(0)
-#define STM32_RCC_HB1_DMA2              BIT(1)
-#define STM32_RCC_HB3_MDMA              BIT(0)
-#define STM32_RCC_HB4_BDMA              BIT(21)
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1           BIT(4)
-
-/* Reset causes definitions */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_RSR
-#define  RESET_CAUSE_WDG                (BIT(28)|BIT(26))
-#define  RESET_CAUSE_SFT                BIT(24)
-#define  RESET_CAUSE_POR                BIT(23)
-#define  RESET_CAUSE_PIN                BIT(22)
-#define  RESET_CAUSE_OTHER              (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \
-					 BIT(27)|BIT(26)|BIT(25)|BIT(24)| \
-					 BIT(23)|BIT(22)|BIT(21)|BIT(20)| \
-					 BIT(19)|BIT(18)|BIT(17))
-#define  RESET_CAUSE_RMVF               BIT(16)
-
-/* Power cause in PWR CPUCR register (Standby&Stop modes) */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CPUCR
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CPUCR
-#define  RESET_CAUSE_SBF                BIT(6)
-#define  RESET_CAUSE_SBF_CLR            BIT(9)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define  STM32_RTC_CR_BYPSHAD        BIT(5)
-#define  STM32_RTC_CR_ALRAE          BIT(8)
-#define  STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define  STM32_RTC_ISR_ALRAWF        BIT(0)
-#define  STM32_RTC_ISR_RSF           BIT(5)
-#define  STM32_RTC_ISR_INITF         BIT(6)
-#define  STM32_RTC_ISR_INIT          BIT(7)
-#define  STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define  STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define  STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint32_t cr1;
-	uint32_t cr2;
-	uint32_t cfg1;
-	uint32_t cfg2;
-	uint32_t ier;
-	uint32_t sr;
-	uint32_t ifcr;
-	uint32_t _pad0;
-	uint32_t txdr;
-	uint32_t _pad1[3];
-	uint32_t rxdr;
-	uint32_t _pad2[3];
-	uint32_t crcpoly;
-	uint32_t rxcrcr;
-	uint32_t txcrcr;
-	uint32_t udrdr;
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_SPE                      BIT(0)
-#define STM32_SPI_CR1_CSTART                   BIT(9)
-#define STM32_SPI_CR1_SSI                      BIT(12)
-#define STM32_SPI_CR1_DIV(div)                 ((div) << 28)
-#define STM32_SPI_CFG1_DATASIZE(n)             (((n) - 1) << 0)
-#define STM32_SPI_CFG1_FTHLV(n)                (((n) - 1) << 5)
-#define STM32_SPI_CFG1_UDRCFG_CONST            (0 << 9)
-#define STM32_SPI_CFG1_UDRCFG_LAST_RX          (1 << 9)
-#define STM32_SPI_CFG1_UDRCFG_LAST_TX          (2 << 9)
-#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM        (0 << 11)
-#define STM32_SPI_CFG1_UDRDET_END_FRM          (1 << 11)
-#define STM32_SPI_CFG1_UDRDET_BEGIN_SS         (2 << 11)
-#define STM32_SPI_CFG1_RXDMAEN                 BIT(14)
-#define STM32_SPI_CFG1_TXDMAEN                 BIT(15)
-#define STM32_SPI_CFG1_CRCSIZE(n)              (((n) - 1) << 16)
-#define  STM32_SPI_CFG2_MSTR                   BIT(22)
-#define  STM32_SPI_CFG2_SSM                    BIT(26)
-#define  STM32_SPI_CFG2_AFCNTR                 BIT(31)
-
-#define STM32_SPI_SR_RXNE                      BIT(0)
-#define STM32_SPI_SR_UDR                       BIT(5)
-#define STM32_SPI_SR_FRLVL                     (3 << 13)
-#define STM32_SPI_SR_TXC                       BIT(12)
-
-/* --- Debug --- */
-#define STM32_DBGMCU_APB3FZ         REG32(STM32_DBGMCU_BASE + 0x34)
-#define STM32_DBGMCU_APB1LFZ        REG32(STM32_DBGMCU_BASE + 0x3C)
-#define STM32_DBGMCU_APB1HFZ        REG32(STM32_DBGMCU_BASE + 0x44)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x4C)
-#define STM32_DBGMCU_APB4FZ         REG32(STM32_DBGMCU_BASE + 0x54)
-/* Alias */
-#define STM32_DBGMCU_APB1FZ         STM32_DBGMCU_APB1LFZ
-
-/* --- Flash --- */
-#define STM32_FLASH_REG(bank, offset)     REG32(((bank) ? 0x100 : 0) + \
-					  STM32_FLASH_REGS_BASE + (offset))
-
-#define STM32_FLASH_ACR(bank)             STM32_FLASH_REG(bank, 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ  (0 << 4)
-#define STM32_FLASH_ACR_WRHIGHFREQ_185MHZ (1 << 4)
-#define STM32_FLASH_ACR_WRHIGHFREQ_285MHZ (2 << 4)
-#define STM32_FLASH_ACR_WRHIGHFREQ_385MHZ (3 << 4)
-
-#define STM32_FLASH_KEYR(bank)            STM32_FLASH_REG(bank, 0x04)
-#define  FLASH_KEYR_KEY1                   0x45670123
-#define  FLASH_KEYR_KEY2                   0xCDEF89AB
-#define STM32_FLASH_OPTKEYR(bank)         STM32_FLASH_REG(bank, 0x08)
-#define  FLASH_OPTKEYR_KEY1                0x08192A3B
-#define  FLASH_OPTKEYR_KEY2                0x4C5D6E7F
-#define STM32_FLASH_CR(bank)              STM32_FLASH_REG(bank, 0x0C)
-#define  FLASH_CR_LOCK                     BIT(0)
-#define  FLASH_CR_PG                       BIT(1)
-#define  FLASH_CR_SER                      BIT(2)
-#define  FLASH_CR_BER                      BIT(3)
-#define  FLASH_CR_PSIZE_BYTE               (0 << 4)
-#define  FLASH_CR_PSIZE_HWORD              (1 << 4)
-#define  FLASH_CR_PSIZE_WORD               (2 << 4)
-#define  FLASH_CR_PSIZE_DWORD              (3 << 4)
-#define  FLASH_CR_PSIZE_MASK               (3 << 4)
-#define  FLASH_CR_FW                       BIT(6)
-#define  FLASH_CR_STRT                     BIT(7)
-#define  FLASH_CR_SNB(sec)                 (((sec) & 0x7) << 8)
-#define  FLASH_CR_SNB_MASK                FLASH_CR_SNB(0x7)
-#define STM32_FLASH_SR(bank)              STM32_FLASH_REG(bank, 0x10)
-#define  FLASH_SR_BUSY                     BIT(0)
-#define  FLASH_SR_WBNE                     BIT(1)
-#define  FLASH_SR_QW                       BIT(2)
-#define  FLASH_SR_CRC_BUSY                 BIT(3)
-#define  FLASH_SR_EOP                      BIT(16)
-#define  FLASH_SR_WRPERR                   BIT(17)
-#define  FLASH_SR_PGSERR                   BIT(18)
-#define  FLASH_SR_STRBERR                  BIT(19)
-#define  FLASH_SR_INCERR                   BIT(21)
-#define  FLASH_SR_OPERR                    BIT(22)
-#define  FLASH_SR_RDPERR                   BIT(23)
-#define  FLASH_SR_RDSERR                   BIT(24)
-#define  FLASH_SR_SNECCERR                 BIT(25)
-#define  FLASH_SR_DBECCERR                 BIT(26)
-#define  FLASH_SR_CRCEND                   BIT(27)
-#define STM32_FLASH_CCR(bank)             STM32_FLASH_REG(bank, 0x14)
-#define  FLASH_CCR_ERR_MASK              (FLASH_SR_WRPERR | FLASH_SR_PGSERR \
-					| FLASH_SR_STRBERR | FLASH_SR_INCERR \
-					| FLASH_SR_OPERR | FLASH_SR_RDPERR \
-					| FLASH_SR_RDSERR | FLASH_SR_SNECCERR \
-					| FLASH_SR_DBECCERR)
-#define STM32_FLASH_OPTCR(bank)           STM32_FLASH_REG(bank, 0x18)
-#define  FLASH_OPTCR_OPTLOCK              BIT(0)
-#define  FLASH_OPTCR_OPTSTART             BIT(1)
-#define STM32_FLASH_OPTSR_CUR(bank)       STM32_FLASH_REG(bank, 0x1C)
-#define STM32_FLASH_OPTSR_PRG(bank)       STM32_FLASH_REG(bank, 0x20)
-#define  FLASH_OPTSR_BUSY                 BIT(0)   /* only in OPTSR_CUR */
-#define  FLASH_OPTSR_RDP_MASK             (0xFF << 8)
-#define  FLASH_OPTSR_RDP_LEVEL_0          (0xAA << 8)
-/* RDP Level 1: Anything but 0xAA/0xCC */
-#define  FLASH_OPTSR_RDP_LEVEL_1          (0x00 << 8)
-#define  FLASH_OPTSR_RDP_LEVEL_2          (0xCC << 8)
-#define  FLASH_OPTSR_RSS1                 BIT(26)
-#define  FLASH_OPTSR_RSS2                 BIT(27)
-#define STM32_FLASH_OPTCCR(bank)          STM32_FLASH_REG(bank, 0x24)
-#define STM32_FLASH_PRAR_CUR(bank)        STM32_FLASH_REG(bank, 0x28)
-#define STM32_FLASH_PRAR_PRG(bank)        STM32_FLASH_REG(bank, 0x2C)
-#define STM32_FLASH_SCAR_CUR(bank)        STM32_FLASH_REG(bank, 0x30)
-#define STM32_FLASH_SCAR_PRG(bank)        STM32_FLASH_REG(bank, 0x34)
-#define STM32_FLASH_WPSN_CUR(bank)        STM32_FLASH_REG(bank, 0x38)
-#define STM32_FLASH_WPSN_PRG(bank)        STM32_FLASH_REG(bank, 0x3C)
-#define STM32_FLASH_BOOT_CUR(bank)        STM32_FLASH_REG(bank, 0x40)
-#define STM32_FLASH_BOOT_PRG(bank)        STM32_FLASH_REG(bank, 0x44)
-#define STM32_FLASH_CRC_CR(bank)          STM32_FLASH_REG(bank, 0x50)
-#define STM32_FLASH_CRC_SADDR(bank)       STM32_FLASH_REG(bank, 0x54)
-#define STM32_FLASH_CRC_EADDR(bank)       STM32_FLASH_REG(bank, 0x58)
-#define STM32_FLASH_CRC_DATA(bank)        STM32_FLASH_REG(bank, 0x5C)
-#define STM32_FLASH_ECC_FA(bank)          STM32_FLASH_REG(bank, 0x60)
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_RTSR1            REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_FTSR1            REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_SWIER1           REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_D3PMR1           REG32(STM32_EXTI_BASE + 0x0C)
-#define STM32_EXTI_D3PCR1L          REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_D3PCR1H          REG32(STM32_EXTI_BASE + 0x14)
-#define STM32_EXTI_RTSR2            REG32(STM32_EXTI_BASE + 0x20)
-#define STM32_EXTI_FTSR2            REG32(STM32_EXTI_BASE + 0x24)
-#define STM32_EXTI_SWIER2           REG32(STM32_EXTI_BASE + 0x28)
-#define STM32_EXTI_D3PMR2           REG32(STM32_EXTI_BASE + 0x2C)
-#define STM32_EXTI_D3PCR2L          REG32(STM32_EXTI_BASE + 0x30)
-#define STM32_EXTI_D3PCR2H          REG32(STM32_EXTI_BASE + 0x34)
-#define STM32_EXTI_RTSR3            REG32(STM32_EXTI_BASE + 0x40)
-#define STM32_EXTI_FTSR3            REG32(STM32_EXTI_BASE + 0x44)
-#define STM32_EXTI_SWIER3           REG32(STM32_EXTI_BASE + 0x48)
-#define STM32_EXTI_D3PMR3           REG32(STM32_EXTI_BASE + 0x4C)
-#define STM32_EXTI_D3PCR3L          REG32(STM32_EXTI_BASE + 0x50)
-#define STM32_EXTI_D3PCR3H          REG32(STM32_EXTI_BASE + 0x54)
-#define STM32_EXTI_CPUIMR1          REG32(STM32_EXTI_BASE + 0x80)
-#define STM32_EXTI_CPUIER1          REG32(STM32_EXTI_BASE + 0x84)
-#define STM32_EXTI_CPUPR1           REG32(STM32_EXTI_BASE + 0x88)
-#define STM32_EXTI_CPUIMR2          REG32(STM32_EXTI_BASE + 0x90)
-#define STM32_EXTI_CPUIER2          REG32(STM32_EXTI_BASE + 0x94)
-#define STM32_EXTI_CPUPR2           REG32(STM32_EXTI_BASE + 0x98)
-#define STM32_EXTI_CPUIMR3          REG32(STM32_EXTI_BASE + 0xA0)
-#define STM32_EXTI_CPUIER3          REG32(STM32_EXTI_BASE + 0xA4)
-#define STM32_EXTI_CPUPR3           REG32(STM32_EXTI_BASE + 0xA8)
-/* Aliases */
-#define STM32_EXTI_IMR              STM32_EXTI_CPUIMR1
-#define STM32_EXTI_EMR              STM32_EXTI_CPUIMR1
-#define STM32_EXTI_RTSR             STM32_EXTI_RTSR1
-#define STM32_EXTI_FTSR             STM32_EXTI_FTSR1
-#define STM32_EXTI_SWIER            STM32_EXTI_SWIER1
-#define STM32_EXTI_PR               STM32_EXTI_CPUPR1
-
-
-/* --- ADC --- */
-
-/* --- Comparators --- */
-
-
-/* --- DMA --- */
-/*
- * Available DMA streams, numbered from 0.
- *
- * Named channel to respect older interface, but a stream can serve
- * any channels, as long as they are in the same DMA controller.
- *
- * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMA1_STREAM0 = 0,
-	STM32_DMA1_STREAM1 = 1,
-	STM32_DMA1_STREAM2 = 2,
-	STM32_DMA1_STREAM3 = 3,
-	STM32_DMA1_STREAM4 = 4,
-	STM32_DMA1_STREAM5 = 5,
-	STM32_DMA1_STREAM6 = 6,
-	STM32_DMA1_STREAM7 = 7,
-	STM32_DMAS_COUNT = 8,
-	STM32_DMA2_STREAM0 = 8,
-	STM32_DMA2_STREAM1 = 9,
-	STM32_DMA2_STREAM2 = 10,
-	STM32_DMA2_STREAM3 = 11,
-	STM32_DMA2_STREAM4 = 12,
-	STM32_DMA2_STREAM5 = 13,
-	STM32_DMA2_STREAM6 = 14,
-	STM32_DMA2_STREAM7 = 15,
-
-	STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7,
-	STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX,
-	STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX,
-
-	STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM6,
-	STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0,
-
-	STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7,
-	STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3,
-
-	STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4,
-	STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM1,
-
-	STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5,
-	STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2,
-
-	/* Legacy naming for spi_master.c */
-	STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */
-	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
-	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
-	STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */
-	STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */
-	STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */
-	STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */
-	STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */
-};
-
-#define STM32_REQ_USART1_TX 4
-#define STM32_REQ_USART1_RX 4
-
-#define STM32_REQ_USART2_TX 4
-#define STM32_REQ_USART2_RX 4
-
-#define STM32_I2C1_TX_REQ_CH 1
-#define STM32_I2C1_RX_REQ_CH 1
-
-#define STM32_I2C2_TX_REQ_CH 7
-#define STM32_I2C2_RX_REQ_CH 7
-
-#define STM32_I2C3_TX_REQ_CH 3
-#define STM32_I2C3_RX_REQ_CH 1
-
-#define STM32_FMPI2C4_TX_REQ_CH 2
-#define STM32_FMPI2C4_RX_REQ_CH 2
-
-#define STM32_SPI1_TX_REQ_CH 3
-#define STM32_SPI1_RX_REQ_CH 3
-#define STM32_SPI2_TX_REQ_CH 0
-#define STM32_SPI2_RX_REQ_CH 0
-#define STM32_SPI3_TX_REQ_CH 0
-#define STM32_SPI3_RX_REQ_CH 0
-
-#define STM32_DMAS_TOTAL_COUNT 16
-
-/* Registers for a single stream of a DMA controller */
-struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
-};
-
-/* Always use stm32_dma_stream_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_stream_t dma_chan_t;
-struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
-	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
-};
-
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M           (0 << 6)
-#define STM32_DMA_CCR_DIR_M2P           (1 << 6)
-#define STM32_DMA_CCR_DIR_M2M           (2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)     ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)     ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK      (0 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)  (0)
-#define STM32_DMA_CCR_RSVD_MASK         (0xF0100000)
-#define STM32_DMA_SFCR_DMDIS            BIT(2)
-#define STM32_DMA_SFCR_FTH(level)       (((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
-#define STM32_DMA_CH_GETBITS(channel, val) \
-	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
-/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX1. */
-/* DMAMUX1/2 registers */
-#define DMAMUX1 0
-#define DMAMUX2 1
-#define STM32_DMAMUX_BASE(n)        ((n) ? STM32_DMAMUX2_BASE \
-					 : STM32_DMAMUX1_BASE)
-#define STM32_DMAMUX_REG32(n, off)  REG32(STM32_DMAMUX_BASE(n) + (off))
-#define STM2_DMAMUX_CxCR(n, x)      STM32_DMAMUX_REG32(n, 4 * (x))
-#define STM2_DMAMUX_CSR(n)          STM32_DMAMUX_REG32(n, 0x80)
-#define STM2_DMAMUX_CFR(n)          STM32_DMAMUX_REG32(n, 0x84)
-#define STM2_DMAMUX_RGxCR(n, x)     STM32_DMAMUX_REG32(n, 0x100 + 4 * (x))
-#define STM2_DMAMUX_RGSR(n)         STM32_DMAMUX_REG32(n, 0x140)
-#define STM2_DMAMUX_RGCFR(n)        STM32_DMAMUX_REG32(n, 0x144)
-
-enum dmamux1_request {
-	DMAMUX1_REQ_ADC1 = 9,
-	DMAMUX1_REQ_ADC2 = 10,
-	DMAMUX1_REQ_TIM1_CH1 = 11,
-	DMAMUX1_REQ_TIM1_CH2 = 12,
-	DMAMUX1_REQ_TIM1_CH3 = 13,
-	DMAMUX1_REQ_TIM1_CH4 = 14,
-	DMAMUX1_REQ_TIM1_UP = 15,
-	DMAMUX1_REQ_TIM1_TRIG = 16,
-	DMAMUX1_REQ_TIM1_COM = 17,
-	DMAMUX1_REQ_TIM2_CH1 = 18,
-	DMAMUX1_REQ_TIM2_CH2 = 19,
-	DMAMUX1_REQ_TIM2_CH3 = 20,
-	DMAMUX1_REQ_TIM2_CH4 = 21,
-	DMAMUX1_REQ_TIM2_UP = 22,
-	DMAMUX1_REQ_TIM3_CH1 = 23,
-	DMAMUX1_REQ_TIM3_CH2 = 24,
-	DMAMUX1_REQ_TIM3_CH3 = 25,
-	DMAMUX1_REQ_TIM3_CH4 = 26,
-	DMAMUX1_REQ_TIM3_UP = 27,
-	DMAMUX1_REQ_TIM3_TRIG = 28,
-	DMAMUX1_REQ_TIM4_CH1 = 29,
-	DMAMUX1_REQ_TIM4_CH2 = 30,
-	DMAMUX1_REQ_TIM4_CH3 = 31,
-	DMAMUX1_REQ_TIM4_UP = 32,
-	DMAMUX1_REQ_I2C1_RX = 33,
-	DMAMUX1_REQ_I2C1_TX = 34,
-	DMAMUX1_REQ_I2C2_RX = 35,
-	DMAMUX1_REQ_I2C2_TX = 36,
-	DMAMUX1_REQ_SPI1_RX = 37,
-	DMAMUX1_REQ_SPI1_TX = 38,
-	DMAMUX1_REQ_SPI2_RX = 39,
-	DMAMUX1_REQ_SPI2_TX = 40,
-	DMAMUX1_REQ_USART1_RX = 41,
-	DMAMUX1_REQ_USART1_TX = 42,
-	DMAMUX1_REQ_USART2_RX = 43,
-	DMAMUX1_REQ_USART2_TX = 44,
-	DMAMUX1_REQ_USART3_RX = 45,
-	DMAMUX1_REQ_USART3_TX = 46,
-	DMAMUX1_REQ_TIM8_CH1 = 47,
-	DMAMUX1_REQ_TIM8_CH2 = 48,
-	DMAMUX1_REQ_TIM8_CH3 = 49,
-	DMAMUX1_REQ_TIM8_CH4 = 50,
-	DMAMUX1_REQ_TIM8_UP = 51,
-	DMAMUX1_REQ_TIM8_TRIG = 52,
-	DMAMUX1_REQ_TIM8_COM = 53,
-	DMAMUX1_REQ_TIM5_CH1 = 55,
-	DMAMUX1_REQ_TIM5_CH2 = 56,
-	DMAMUX1_REQ_TIM5_CH3 = 57,
-	DMAMUX1_REQ_TIM5_CH4 = 58,
-	DMAMUX1_REQ_TIM5_UP = 59,
-	DMAMUX1_REQ_TIM5_TRIG = 60,
-	DMAMUX1_REQ_SPI3_RX = 61,
-	DMAMUX1_REQ_SPI3_TX = 62,
-	DMAMUX1_REQ_UART4_RX = 63,
-	DMAMUX1_REQ_UART4_TX = 64,
-	DMAMUX1_REQ_USART5_RX = 65,
-	DMAMUX1_REQ_UART5_TX = 66,
-	DMAMUX1_REQ_DAC1 = 67,
-	DMAMUX1_REQ_DAC2 = 68,
-	DMAMUX1_REQ_TIM6_UP = 69,
-	DMAMUX1_REQ_TIM7_UP = 70,
-	DMAMUX1_REQ_USART6_RX = 71,
-	DMAMUX1_REQ_USART6_TX = 72,
-	DMAMUX1_REQ_I2C3_RX = 73,
-	DMAMUX1_REQ_I2C3_TX = 74,
-	DMAMUX1_REQ_DCMI = 75,
-	DMAMUX1_REQ_CRYP_IN = 76,
-	DMAMUX1_REQ_CRYP_OUT = 77,
-	DMAMUX1_REQ_HASH_IN = 78,
-	DMAMUX1_REQ_UART7_RX = 79,
-	DMAMUX1_REQ_UART7_TX = 80,
-	DMAMUX1_REQ_UART8_RX = 81,
-	DMAMUX1_REQ_UART8_TX = 82,
-	DMAMUX1_REQ_SPI4_RX = 83,
-	DMAMUX1_REQ_SPI4_TX = 84,
-	DMAMUX1_REQ_SPI5_RX = 85,
-	DMAMUX1_REQ_SPI5_TX = 86,
-	DMAMUX1_REQ_SAI1_A = 87,
-	DMAMUX1_REQ_SAI1_B = 88,
-	DMAMUX1_REQ_SAI2_A = 89,
-	DMAMUX1_REQ_SAI2_B = 90,
-	DMAMUX1_REQ_SWPMI_RX = 91,
-	DMAMUX1_REQ_SWPMI_TX = 92,
-	DMAMUX1_REQ_SPDIFRX_DT = 93,
-	DMAMUX1_REQ_SPDIFRX_CS = 94,
-	DMAMUX1_REQ_TIM15_CH1 = 105,
-	DMAMUX1_REQ_TIM15_UP = 106,
-	DMAMUX1_REQ_TIM15_TRIG = 107,
-	DMAMUX1_REQ_TIM15_COM = 108,
-	DMAMUX1_REQ_TIM16_CH1 = 109,
-	DMAMUX1_REQ_TIM16_UP = 110,
-	DMAMUX1_REQ_TIM17_CH1 = 111,
-	DMAMUX1_REQ_TIM17_UP = 112,
-	DMAMUX1_REQ_SAI3_A = 113,
-	DMAMUX1_REQ_SAI3_B = 114,
-	DMAMUX1_REQ_ADC3 = 115,
-};
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define  STM32_CRC_CR_RESET          BIT(0)
-#define  STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define  STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define  STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define  STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define  STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define  STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define  STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define  STM32_CRC_CR_REV_OUT        BIT(7)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-#define  STM32_USB_CNTR_FRES        BIT(0)
-#define  STM32_USB_CNTR_PDWN        BIT(1)
-#define  STM32_USB_CNTR_LP_MODE     BIT(2)
-#define  STM32_USB_CNTR_FSUSP       BIT(3)
-#define  STM32_USB_CNTR_RESUME      BIT(4)
-#define  STM32_USB_CNTR_L1RESUME    BIT(5)
-#define  STM32_USB_CNTR_L1REQM      BIT(7)
-#define  STM32_USB_CNTR_ESOFM       BIT(8)
-#define  STM32_USB_CNTR_SOFM        BIT(9)
-#define  STM32_USB_CNTR_RESETM      BIT(10)
-#define  STM32_USB_CNTR_SUSPM       BIT(11)
-#define  STM32_USB_CNTR_WKUPM       BIT(12)
-#define  STM32_USB_CNTR_ERRM        BIT(13)
-#define  STM32_USB_CNTR_PMAOVRM     BIT(14)
-#define  STM32_USB_CNTR_CTRM        BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-#define  STM32_USB_ISTR_EP_ID_MASK  (0x000f)
-#define  STM32_USB_ISTR_DIR         BIT(4)
-#define  STM32_USB_ISTR_L1REQ       BIT(7)
-#define  STM32_USB_ISTR_ESOF        BIT(8)
-#define  STM32_USB_ISTR_SOF         BIT(9)
-#define  STM32_USB_ISTR_RESET       BIT(10)
-#define  STM32_USB_ISTR_SUSP        BIT(11)
-#define  STM32_USB_ISTR_WKUP        BIT(12)
-#define  STM32_USB_ISTR_ERR         BIT(13)
-#define  STM32_USB_ISTR_PMAOVR      BIT(14)
-#define  STM32_USB_ISTR_CTR         BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-#define  STM32_USB_BCDR_BCDEN       BIT(0)
-#define  STM32_USB_BCDR_DCDEN       BIT(1)
-#define  STM32_USB_BCDR_PDEN        BIT(2)
-#define  STM32_USB_BCDR_SDEN        BIT(3)
-#define  STM32_USB_BCDR_DCDET       BIT(4)
-#define  STM32_USB_BCDR_PDET        BIT(5)
-#define  STM32_USB_BCDR_SDET        BIT(6)
-#define  STM32_USB_BCDR_PS2DET      BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define  STM32_RNG_CR_RNGEN          BIT(2)
-#define  STM32_RNG_CR_IE             BIT(3)
-#define  STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define  STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE          BIT(1)
-#define  READ_ISS_OVERRIDE           BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l.h b/chip/stm32/registers-stm32l.h
deleted file mode 100644
index 37b31ac302..0000000000
--- a/chip/stm32/registers-stm32l.h
+++ /dev/null
@@ -1,871 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32L family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32L100
- * - STM32L15X
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-#define STM32_COMP_BASE             0x40007C00
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-
-#define STM32_EXTI_BASE             0x40010400
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021800 /* see RM0038 table 5 */
-#define STM32_GPIOG_BASE            0x40021C00
-#define STM32_GPIOH_BASE            0x40021400
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1ff80000
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40010000
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40010800 /* STM32L15X only */
-#define STM32_TIM10_BASE            0x40010C00 /* STM32L15X only */
-#define STM32_TIM11_BASE            0x40011000 /* STM32L15X only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
-
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-#define STM32_USART_DR(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_UE		BIT(13)
-#define STM32_USART_CR1_OVER8		BIT(15) /* STM32L only */
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11) /* STM32L only */
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x18)
-/* register aliases */
-#define STM32_USART_TDR(base)      STM32_USART_DR(base)
-#define STM32_USART_RDR(base)      STM32_USART_DR(base)
-
-/* --- GPIO --- */
-
-
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_MSION		BIT(8)
-#define STM32_RCC_CR_MSIRDY		BIT(9)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-#define STM32_RCC_ICSCR             REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_ICSCR_MSIRANGE(n)	((n) << 13)
-#define STM32_RCC_ICSCR_MSIRANGE_1MHZ	STM32_RCC_ICSCR_MSIRANGE(4)
-#define STM32_RCC_ICSCR_MSIRANGE_2MHZ	STM32_RCC_ICSCR_MSIRANGE(5)
-#define STM32_RCC_ICSCR_MSIRANGE_MASK	STM32_RCC_ICSCR_MSIRANGE(7)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_MSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSI		(1 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_MSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSI		(1 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHBRSTR           REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_SYSCFGEN		BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_AHBLPENR          REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_APB2LPENR         REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_APB1LPENR         REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x34)
-
-#define STM32_RCC_HB_DMA1		BIT(24)
-#define STM32_RCC_PB2_TIM9		BIT(2)
-#define STM32_RCC_PB2_TIM10		BIT(3)
-#define STM32_RCC_PB2_TIM11		BIT(4)
-#define STM32_RCC_PB1_USB		BIT(23)
-
-#define STM32_SYSCFG_MEMRMP         REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC            REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY		BIT(0)
-#define STM32_FLASH_ACR_PRFTEN		BIT(1)
-#define STM32_FLASH_ACR_ACC64		BIT(2)
-#define STM32_FLASH_PECR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_PECR_PE_LOCK	BIT(0)
-#define STM32_FLASH_PECR_PRG_LOCK	BIT(1)
-#define STM32_FLASH_PECR_OPT_LOCK	BIT(2)
-#define STM32_FLASH_PECR_PROG		BIT(3)
-#define STM32_FLASH_PECR_ERASE		BIT(9)
-#define STM32_FLASH_PECR_FPRG		BIT(10)
-#define STM32_FLASH_PECR_OBL_LAUNCH	BIT(18)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define STM32_FLASH_PEKEYR          REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define STM32_FLASH_PEKEYR_KEY1		0x89ABCDEF
-#define STM32_FLASH_PEKEYR_KEY2		0x02030405
-#define STM32_FLASH_PRGKEYR         REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define STM32_FLASH_PRGKEYR_KEY1	0x8C9DAEBF
-#define STM32_FLASH_PRGKEYR_KEY2	0x13141516
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OPTKEYR_KEY1	0xFBEAD9C8
-#define STM32_FLASH_OPTKEYR_KEY2	0x24252627
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x18)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP                  0x00
-#define STM32_OPTB_USER                 0x04
-#define STM32_OPTB_WRP1L                0x08
-#define STM32_OPTB_WRP1H                0x0c
-#define STM32_OPTB_WRP2L                0x10
-#define STM32_OPTB_WRP2H                0x14
-#define STM32_OPTB_WRP3L                0x18
-#define STM32_OPTB_WRP3H                0x1c
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-
-/* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_SMPR3            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC_JOFR1            REG32(STM32_ADC1_BASE + 0x18)
-#define STM32_ADC_JOFR2            REG32(STM32_ADC1_BASE + 0x1C)
-#define STM32_ADC_JOFR3            REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_JOFR4            REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x2C + (n) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_SQR4             REG32(STM32_ADC1_BASE + 0x3C)
-#define STM32_ADC_SQR5             REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x44)
-#define STM32_ADC_JDR1             REG32(STM32_ADC1_BASE + 0x48)
-#define STM32_ADC_JDR2             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC_JDR3             REG32(STM32_ADC1_BASE + 0x50)
-#define STM32_ADC_JDR3             REG32(STM32_ADC1_BASE + 0x50)
-#define STM32_ADC_JDR4             REG32(STM32_ADC1_BASE + 0x54)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x58)
-#define STM32_ADC_SMPR0            REG32(STM32_ADC1_BASE + 0x5C)
-
-#define STM32_ADC_CCR              REG32(STM32_ADC_BASE + 0x04)
-
-/* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x00)
-
-#define STM32_COMP_OUTSEL_TIM2_IC4  (0 << 21)
-#define STM32_COMP_OUTSEL_TIM2_OCR  (1 << 21)
-#define STM32_COMP_OUTSEL_TIM3_IC4  (2 << 21)
-#define STM32_COMP_OUTSEL_TIM3_OCR  (3 << 21)
-#define STM32_COMP_OUTSEL_TIM4_IC4  (4 << 21)
-#define STM32_COMP_OUTSEL_TIM4_OCR  (5 << 21)
-#define STM32_COMP_OUTSEL_TIM10_IC1 (6 << 21)
-#define STM32_COMP_OUTSEL_NONE      (7 << 21)
-
-#define STM32_COMP_INSEL_NONE       (0 << 18)
-#define STM32_COMP_INSEL_PB3        (1 << 18)
-#define STM32_COMP_INSEL_VREF       (2 << 18)
-#define STM32_COMP_INSEL_VREF34     (3 << 18)
-#define STM32_COMP_INSEL_VREF12     (4 << 18)
-#define STM32_COMP_INSEL_VREF14     (5 << 18)
-#define STM32_COMP_INSEL_DAC_OUT1   (6 << 18)
-#define STM32_COMP_INSEL_DAC_OUT2   (7 << 18)
-
-#define STM32_COMP_WNDWE            BIT(17)
-#define STM32_COMP_VREFOUTEN        BIT(16)
-#define STM32_COMP_CMP2OUT          BIT(13)
-#define STM32_COMP_SPEED_FAST       BIT(12)
-
-#define STM32_COMP_CMP1OUT          BIT(7)
-#define STM32_COMP_CMP1EN           BIT(4)
-
-#define STM32_COMP_400KPD           BIT(3)
-#define STM32_COMP_10KPD            BIT(2)
-#define STM32_COMP_400KPU           BIT(1)
-#define STM32_COMP_10KPU            BIT(0)
-
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-
-	/* Channel functions */
-	STM32_DMAC_ADC = STM32_DMAC_CH1,
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2,
-	STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3,
-	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
-	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH4,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_USART2_TX = STM32_DMAC_CH7,
-	STM32_DMAC_I2C1_TX = STM32_DMAC_CH6,
-	STM32_DMAC_I2C1_RX = STM32_DMAC_CH7,
-	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH7,
-	/* Only DMA1 (with 7 channels) is present on STM32L151x */
-	STM32_DMAC_COUNT = 7,
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-
-#define STM32_DMA_REGS(channel) STM32_DMA1_REGS
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h
deleted file mode 100644
index 29965fe2ee..0000000000
--- a/chip/stm32/registers-stm32l4.h
+++ /dev/null
@@ -1,2114 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32L4 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32L442
- * - STM32L476
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/******  STM32 specific Interrupt Numbers ********/
-#define   STM32_IRQ_WWDG                    0
-#define   STM32_IRQ_PVD_PVM                 1
-#define   STM32_IRQ_TAMP_STAMP              2
-#define   STM32_IRQ_RTC_WKUP                3
-#define   STM32_IRQ_FLASH                   4
-#define   STM32_IRQ_RCC                     5
-#define   STM32_IRQ_EXTI0                   6
-#define   STM32_IRQ_EXTI1                   7
-#define   STM32_IRQ_EXTI2                   8
-#define   STM32_IRQ_EXTI3                   9
-#define   STM32_IRQ_EXTI4                   10
-#define   STM32_IRQ_DMA_CHANNEL_1           11
-#define   STM32_IRQ_DMA_CHANNEL_2           12
-#define   STM32_IRQ_DMA_CHANNEL_3           13
-#define   STM32_IRQ_DMA_CHANNEL_4           14
-#define   STM32_IRQ_DMA_CHANNEL_5           15
-#define   STM32_IRQ_DMA_CHANNEL_6           16
-#define   STM32_IRQ_DMA_CHANNEL_7           17
-#define   STM32_IRQ_ADC1                    18
-#define   STM32_IRQ_CAN1_TX                 19
-#define   STM32_IRQ_CAN1_RX0                20
-#define   STM32_IRQ_CAN1_RX1                21
-#define   STM32_IRQ_CAN1_SCE                22
-#define   STM32_IRQ_EXTI9_5                 23
-#define   STM32_IRQ_TIM1_BRK_TIM15          24
-#define   STM32_IRQ_TIM1_UP_TIM16           25
-#define   STM32_IRQ_TIM1_TRG_COM            26
-#define   STM32_IRQ_TIM1_CC                 27
-#define   STM32_IRQ_TIM2                    28
-#define   STM32_IRQ_I2C1_EV                 31
-#define   STM32_IRQ_I2C1_ER                 32
-#define   STM32_IRQ_I2C2_EV                 33
-#define   STM32_IRQ_I2C2_ER                 34
-#define   STM32_IRQ_SPI1                    35
-#define   STM32_IRQ_SPI2                    36
-#define   STM32_IRQ_USART1                  37
-#define   STM32_IRQ_USART2                  38
-#define   STM32_IRQ_USART3                  39
-#define   STM32_IRQ_EXTI15_10               40
-#define   STM32_IRQ_RTC_ALARM               41
-#define   STM32_IRQ_SDMMC1                  49
-#define   STM32_IRQ_TIM5                    50
-#define   STM32_IRQ_SPI3                    51
-#define   STM32_IRQ_TIM6_DAC                54
-#define   STM32_IRQ_TIM7                    55
-#define   STM32_IRQ_DMA2_CHANNEL1           56
-#define   STM32_IRQ_DMA2_CHANNEL2           57
-#define   STM32_IRQ_DMA2_CHANNEL3           58
-#define   STM32_IRQ_DMA2_CHANNEL4           59
-#define   STM32_IRQ_DMA2_CHANNEL5           60
-#define   STM32_IRQ_COMP                    64
-#define   LSTM32_IRQ_PTIM1                  65
-#define   STM32_IRQ_LPTIM2                  66
-#define   STM32_IRQ_DMA2_CHANNEL6           68
-#define   STM32_IRQ_DMA2_CHANNEL7           69
-#define   STM32_IRQ_LPUART1                 70
-#define   STM32_IRQ_QUADSPI                 71
-#define   STM32_IRQ_I2C3_EV                 72
-#define   STM32_IRQ_I2C3_ER                 73
-#define   STM32_IRQ_SAI1                    74
-#define   STM32_IRQ_SWPMI1                  76
-#define   STM32_IRQ_TSC                     77
-#define   STM32_IRQ_RNG                     80
-#define   STM32_IRQ_FPU                     81
-#define   STM32_IRQ_CRS                     82
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_11   STM32_IRQ_DMA2_CHANNEL3
-#define STM32_IRQ_DMA_CHANNEL_12   STM32_IRQ_DMA2_CHANNEL4
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL5
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_15   STM32_IRQ_DMA2_CHANNEL7
-#define STM32_IRQ_USART9           STM32_IRQ_LPUART1
-
-
-/* Peripheral base addresses */
-#define FLASH_BASE            0x08000000UL
-#define FLASH_END             0x0803FFFFUL
-#define FLASH_BANK1_END       0x0803FFFFUL
-#define SRAM1_BASE            0x20000000UL
-#define SRAM2_BASE            0x10000000UL
-#define PERIPH_BASE           0x40000000UL
-#define QSPI_BASE             0x90000000UL
-#define QSPI_R_BASE           0xA0001000UL
-#define SRAM1_BB_BASE         0x22000000UL
-#define PERIPH_BB_BASE        0x42000000UL
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-#define SRAM1_SIZE_MAX        0x0000C000UL
-#define SRAM2_SIZE            0x00004000UL
-#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
-#define FLASH_SIZE               (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) \
-			& (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
-			(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & \
-			(0x0000FFFFU)) << 10U))
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
-
-/*!< APB1 peripherals */
-#define STM32_TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
-#define STM32_TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
-#define STM32_TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
-#define STM32_TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
-#define STM32_RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
-#define STM32_WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
-#define STM32_IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
-#define STM32_SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
-#define STM32_SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
-#define STM32_USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
-#define STM32_USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
-#define STM32_I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
-#define STM32_I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
-#define STM32_I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
-#define STM32_CRS_BASE              (APB1PERIPH_BASE + 0x6000UL)
-#define STM32_CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
-#define STM32_PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
-#define STM32_DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_DAC1_BASE             (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_OPAMP_BASE            (APB1PERIPH_BASE + 0x7800UL)
-#define STM32_OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800UL)
-#define STM32_LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
-#define STM32_LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
-#define STM32_SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800UL)
-#define STM32_LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400UL)
-
-#define STM32_USART9_BASE           STM32_LPUART1_BASE
-
-/*!< APB2 peripherals */
-#define STM32_SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
-#define STM32_VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)
-#define STM32_OMP1_BASE             (APB2PERIPH_BASE + 0x0200UL)
-#define STM32_COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
-#define STM32_EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
-#define STM32_FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00UL)
-#define STM32_SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800UL)
-#define STM32_TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
-#define STM32_SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
-#define STM32_USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
-#define STM32_TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
-#define STM32_TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
-#define STM32_SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)
-#define STM32_SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
-#define STM32_SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
-
-/*!< AHB1 peripherals */
-#define STM32_DMA1_BASE             (AHB1PERIPH_BASE)
-#define STM32_DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
-#define STM32_RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
-#define STM32_FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
-#define STM32_CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
-#define STM32_TSC_BASE              (AHB1PERIPH_BASE + 0x4000UL)
-#define STM32_DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
-#define STM32_DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
-#define STM32_DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
-#define STM32_DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
-#define STM32_DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
-#define STM32_DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
-#define STM32_DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
-#define STM32_DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)
-#define STM32_DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
-#define STM32_DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
-#define STM32_DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
-#define STM32_DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
-#define STM32_DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
-#define STM32_DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
-#define STM32_DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
-#define STM32_DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)
-
-/*!< AHB2 peripherals */
-#define STM32_GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
-#define STM32_GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
-#define STM32_GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
-#define STM32_GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
-#define STM32_GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
-#define STM32_GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)
-#define STM32_GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */
-#define STM32_GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00UL)
-#define STM32_ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000UL)
-#define STM32_ADC1_COMMON_BASE      (AHB2PERIPH_BASE + 0x08040300UL)
-#define STM32_RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
-
-/* Debug MCU registers base address */
-#define STM32_DBGMCU_BASE           0xE0042000UL
-#define STM32_PACKAGE_BASE          0x1FFF7500UL
-#define STM32_UID_BASE              0x1FFF7590UL
-#define STM32_FLASHSIZE_BASE        0x1FFF75E0UL
-
-#define STM32_FLASH_REGS_BASE       STM32_FLASH_R_BASE
-#define STM32_UNIQUE_ID_BASE        STM32_UID_BASE
-#define STM32_OPTB_BASE             0x1FFF7800
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE          BIT(0)
-#define STM32_USART_CR1_UESM        BIT(1)
-#define STM32_USART_CR1_RE          BIT(2)
-#define STM32_USART_CR1_TE          BIT(3)
-#define STM32_USART_CR1_RXNEIE      BIT(5)
-#define STM32_USART_CR1_TCIE        BIT(6)
-#define STM32_USART_CR1_TXEIE       BIT(7)
-#define STM32_USART_CR1_PS          BIT(9)
-#define STM32_USART_CR1_PCE         BIT(10)
-#define STM32_USART_CR1_M           BIT(12)
-#define STM32_USART_CR1_OVER8       BIT(15)
-
-#define STM32_USART_CR2(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP        BIT(15)
-
-#define STM32_USART_CR3(base)       STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE         BIT(0)
-#define STM32_USART_CR3_DMAR        BIT(6)
-#define STM32_USART_CR3_DMAT        BIT(7)
-#define STM32_USART_CR3_ONEBIT      BIT(11)
-#define STM32_USART_CR3_OVRDIS      BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define STM32_USART_CR3_WUFIE       BIT(22)
-
-#define STM32_USART_BRR(base)       STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)       STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)       STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF       BIT(3)
-#define STM32_USART_ICR_TCCF        BIT(6)
-#define STM32_USART_RDR(base)       STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)       STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)     STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)        STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE          BIT(3)
-#define STM32_USART_SR_RXNE         BIT(5)
-#define STM32_USART_SR_TC           BIT(6)
-#define STM32_USART_SR_TXE          BIT(7)
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4x6 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR1               REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SCR               REG32(STM32_PWR_BASE + 0x18)
-
-#define PWR_CR1_LPMS_POS             0U
-#define PWR_CR1_LPMS_MSK             (0x7UL << PWR_CR1_LPMS_POS)
-#define PWR_CR1_LPMS                 PWR_CR1_LPMS_MSK
-#define PWR_CR1_LPMS_STOP0           (0x00000000UL)
-#define PWR_CR1_LPMS_STOP1_POS       0U
-#define PWR_CR1_LPMS_STOP1_MSK       (0x1UL << PWR_CR1_LPMS_STOP1_POS)
-#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_MSK
-#define PWR_CR1_LPMS_STOP2_POS       1U
-#define PWR_CR1_LPMS_STOP2_MSK       (0x1UL << PWR_CR1_LPMS_STOP2_POS)
-#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_MSK
-#define PWR_CR1_LPMS_STANDBY_POS     0U
-#define PWR_CR1_LPMS_STANDBY_MSK     (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
-#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_MSK
-#define PWR_CR1_LPMS_SHUTDOWN_POS    2U
-#define PWR_CR1_LPMS_SHUTDOWN_MSK    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
-#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_MSK
-#define PWR_CR1_VOS_POS              9U
-#define PWR_CR1_VOS_MSK              (0x3UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS                  PWR_CR1_VOS_MSK
-#define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_POS)
-
-
-/* --- Macro usage in ec code --- */
-#define STM32_RCC_AHB2ENR_GPIOMASK                               \
-	(STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \
-	 STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \
-	 STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOHEN)
-#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
-#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
-#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_SYSCFGEN            STM32_RCC_APB2ENR_SYSCFGEN
-
-#define STM32_RCC_PB2_TIM1            STM32_RCC_APB2ENR_TIM1EN
-#define STM32_RCC_PB2_TIM15           STM32_RCC_APB2ENR_TIM15EN
-#define STM32_RCC_PB2_TIM16           STM32_RCC_APB2ENR_TIM16EN
-#ifndef CHIP_VARIANT_STM32L431X
-#define STM32_RCC_PB2_TIM8            BIT(13)
-#endif
-#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
-
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTH	BIT(7)
-#define STM32_RCC_CCIPR_USART1SEL_SHIFT (0)
-#define STM32_RCC_CCIPR_USART1SEL_MASK  (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
-#define STM32_RCC_CCIPR_USART2SEL_SHIFT (2)
-#define STM32_RCC_CCIPR_USART2SEL_MASK  (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
-#define STM32_RCC_CCIPR_USART3SEL_SHIFT (4)
-#define STM32_RCC_CCIPR_USART3SEL_MASK  (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
-#define STM32_RCC_CCIPR_UART4SEL_SHIFT (6)
-#define STM32_RCC_CCIPR_UART4SEL_MASK  (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
-#define STM32_RCC_CCIPR_UART5SEL_SHIFT (8)
-#define STM32_RCC_CCIPR_UART5SEL_MASK  (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10)
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12)
-#define STM32_RCC_CCIPR_I2C1SEL_MASK  (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14)
-#define STM32_RCC_CCIPR_I2C2SEL_MASK  (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16)
-#define STM32_RCC_CCIPR_I2C3SEL_MASK  (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18)
-#define STM32_RCC_CCIPR_LPTIM1SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20)
-#define STM32_RCC_CCIPR_LPTIM2SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
-#define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22)
-#define STM32_RCC_CCIPR_SAI1SEL_MASK  (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
-#define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24)
-#define STM32_RCC_CCIPR_SAI2SEL_MASK  (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
-#define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26)
-#define STM32_RCC_CCIPR_CLK48SEL_MASK  (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
-#define STM32_RCC_CCIPR_ADCSEL_SHIFT (28)
-#define STM32_RCC_CCIPR_ADCSEL_MASK  (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
-#define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30)
-#define STM32_RCC_CCIPR_SWPMI1SEL_MASK  BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
-#define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31)
-#define STM32_RCC_CCIPR_DFSDM1SEL_MASK  BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
-/* Possible clock sources for each peripheral */
-#define STM32_RCC_CCIPR_UART_PCLK	0
-#define STM32_RCC_CCIPR_UART_SYSCLK	1
-#define STM32_RCC_CCIPR_UART_HSI16	2
-#define STM32_RCC_CCIPR_UART_LSE	3
-
-#define STM32_RCC_CCIPR_I2C_PCLK	0
-#define STM32_RCC_CCIPR_I2C_SYSCLK	1
-#define STM32_RCC_CCIPR_I2C_HSI16	2
-
-#define STM32_RCC_CCIPR_LPTIM_PCLK	0
-#define STM32_RCC_CCIPR_LPTIM_LSI	1
-#define STM32_RCC_CCIPR_LPTIM_HSI16	2
-#define STM32_RCC_CCIPR_LPTIM_LSE	3
-
-#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK	0
-#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK	1
-#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK	2
-#define STM32_RCC_CCIPR_SAI_EXTCLK		3
-
-#define STM32_RCC_CCIPR_CLK48_NONE			0
-#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK	1
-#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK	2
-#define STM32_RCC_CCIPR_CLK48_MSI			3
-
-#define STM32_RCC_CCIPR_ADC_NONE		0
-#define STM32_RCC_CCIPR_ADC_PLLADC1CLK	1
-#define STM32_RCC_CCIPR_ADC_PLLADC2CLK	2
-#define STM32_RCC_CCIPR_ADC_SYSCLK	3
-
-#define STM32_RCC_CCIPR_SWPMI_PCLK	0
-#define STM32_RCC_CCIPR_SWPMI_HSI16	1
-
-#define STM32_RCC_CCIPR_DFSDM_PCLK		0
-#define STM32_RCC_CCIPR_DFSDM_SYSCLK	1
-
-
-
-#define STM32_RCC_CR          REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR       REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR        REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR     REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_RESERVED    REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_CIER        REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR        REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR        REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_RESERVED0   REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_AHB1RSTR    REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR    REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR    REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_RESERVED1   REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_APB1RSTR1   REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2   REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR    REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_RESERVED2   REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_AHB1ENR     REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR     REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR     REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_RESERVED3   REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_APB1ENR1    REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2    REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR     REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_RESERVED4   REG32(STM32_RCC_BASE + 0x64)
-#define STM32_RCC_AHB1SMENR   REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR   REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR   REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_RESERVED5   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_APB1SMENR1  REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2  REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR   REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_RESERVED6   REG32(STM32_RCC_BASE + 0x84)
-#define STM32_RCC_CCIPR       REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_RESERVED7   REG32(STM32_RCC_BASE + 0x8C)
-#define STM32_RCC_BDCR        REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR         REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR       REG32(STM32_RCC_BASE + 0x98)
-
-#define STM32_RCC_PLLSAI1_SUPPORT
-#define STM32_RCC_PLLP_SUPPORT
-#define STM32_RCC_HSI48_SUPPORT
-#define STM32_RCC_PLLP_DIV_2_31_SUPPORT
-#define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT
-
-#define STM32_RCC_APB1ENR                STM32_RCC_APB1ENR1
-
-/********************  BIT DEFINITION FOR STM32_RCC_CR REGISTER  **************/
-#define STM32_RCC_CR_MSION_POS           0U
-#define STM32_RCC_CR_MSION_MSK           (0x1UL << STM32_RCC_CR_MSION_POS)
-#define STM32_RCC_CR_MSION               STM32_RCC_CR_MSION_MSK
-#define STM32_RCC_CR_MSIRDY_POS          1U
-#define STM32_RCC_CR_MSIRDY_MSK          (0x1UL << STM32_RCC_CR_MSIRDY_POS)
-#define STM32_RCC_CR_MSIRDY              STM32_RCC_CR_MSIRDY_MSK
-#define STM32_RCC_CR_MSIPLLEN_POS        2U
-#define STM32_RCC_CR_MSIPLLEN_MSK        (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
-#define STM32_RCC_CR_MSIPLLEN            STM32_RCC_CR_MSIPLLEN_MSK
-#define STM32_RCC_CR_MSIRGSEL_POS        3U
-#define STM32_RCC_CR_MSIRGSEL_MSK        (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
-#define STM32_RCC_CR_MSIRGSEL            STM32_RCC_CR_MSIRGSEL_MSK
-
-/*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */
-#define STM32_RCC_CR_MSIRANGE_POS        4U
-#define STM32_RCC_CR_MSIRANGE_MSK        (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE            STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_CR_MSIRANGE_0          (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_1          (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_2          (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_3          (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_4          (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_5          (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_6          (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_7          (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_8          (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_9          (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_10         (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_11         (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
-
-#define STM32_RCC_CR_HSION_POS           8U
-#define STM32_RCC_CR_HSION_MSK           (0x1UL << STM32_RCC_CR_HSION_POS)
-#define STM32_RCC_CR_HSION               STM32_RCC_CR_HSION_MSK
-#define STM32_RCC_CR_HSIKERON_POS        9U
-#define STM32_RCC_CR_HSIKERON_MSK        (0x1UL << STM32_RCC_CR_HSIKERON_POS)
-#define STM32_RCC_CR_HSIKERON            STM32_RCC_CR_HSIKERON_MSK
-#define STM32_RCC_CR_HSIRDY_POS          10U
-#define STM32_RCC_CR_HSIRDY_MSK          (0x1UL << STM32_RCC_CR_HSIRDY_POS)
-#define STM32_RCC_CR_HSIRDY              STM32_RCC_CR_HSIRDY_MSK
-#define STM32_RCC_CR_HSIASFS_POS         11U
-#define STM32_RCC_CR_HSIASFS_MSK         (0x1UL << STM32_RCC_CR_HSIASFS_POS)
-#define STM32_RCC_CR_HSIASFS             STM32_RCC_CR_HSIASFS_MSK
-
-#define STM32_RCC_CR_HSEON_POS           16U
-#define STM32_RCC_CR_HSEON_MSK           (0x1UL << STM32_RCC_CR_HSEON_POS)
-#define STM32_RCC_CR_HSEON               STM32_RCC_CR_HSEON_MSK
-#define STM32_RCC_CR_HSERDY_POS          17U
-#define STM32_RCC_CR_HSERDY_MSK          (0x1UL << STM32_RCC_CR_HSERDY_POS)
-#define STM32_RCC_CR_HSERDY              STM32_RCC_CR_HSERDY_MSK
-#define STM32_RCC_CR_HSEBYP_POS          18U
-#define STM32_RCC_CR_HSEBYP_MSK          (0x1UL << STM32_RCC_CR_HSEBYP_POS)
-#define STM32_RCC_CR_HSEBYP              STM32_RCC_CR_HSEBYP_MSK
-#define STM32_RCC_CR_CSSON_POS           19U
-#define STM32_RCC_CR_CSSON_MSK           (0x1UL << STM32_RCC_CR_CSSON_POS)
-#define STM32_RCC_CR_CSSON               STM32_RCC_CR_CSSON_MSK
-
-#define STM32_RCC_CR_PLLON_POS           24U
-#define STM32_RCC_CR_PLLON_MSK           (0x1UL << STM32_RCC_CR_PLLON_POS)
-#define STM32_RCC_CR_PLLON               STM32_RCC_CR_PLLON_MSK
-#define STM32_RCC_CR_PLLRDY_POS          25U
-#define STM32_RCC_CR_PLLRDY_MSK          (0x1UL << STM32_RCC_CR_PLLRDY_POS)
-#define STM32_RCC_CR_PLLRDY              STM32_RCC_CR_PLLRDY_MSK
-#define STM32_RCC_CR_PLLSAI1ON_POS       26U
-#define STM32_RCC_CR_PLLSAI1ON_MSK       (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
-#define STM32_RCC_CR_PLLSAI1ON           STM32_RCC_CR_PLLSAI1ON_MSK
-#define STM32_RCC_CR_PLLSAI1RDY_POS      27U
-#define STM32_RCC_CR_PLLSAI1RDY_MSK      (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
-#define STM32_RCC_CR_PLLSAI1RDY          STM32_RCC_CR_PLLSAI1RDY_MSK
-
-/********************  BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER  ***********/
-/*!< MSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_MSICAL_POS       0U
-#define STM32_RCC_ICSCR_MSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL           STM32_RCC_ICSCR_MSICAL_MSK
-#define STM32_RCC_ICSCR_MSICAL_0         (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_1         (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_2         (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_3         (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_4         (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_5         (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_6         (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_7         (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
-
-/*!< MSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_MSITRIM_POS      8U
-#define STM32_RCC_ICSCR_MSITRIM_MSK      (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM          STM32_RCC_ICSCR_MSITRIM_MSK
-#define STM32_RCC_ICSCR_MSITRIM_0        (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_1        (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_2        (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_3        (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_4        (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_5        (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_6        (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_7        (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
-
-/*!< HSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_HSICAL_POS       16U
-#define STM32_RCC_ICSCR_HSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL           STM32_RCC_ICSCR_HSICAL_MSK
-#define STM32_RCC_ICSCR_HSICAL_0         (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_1         (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_2         (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_3         (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_4         (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_5         (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_6         (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_7         (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
-
-/*!< HSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_HSITRIM_POS      24U
-#define STM32_RCC_ICSCR_HSITRIM_MSK      (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM          STM32_RCC_ICSCR_HSITRIM_MSK
-#define STM32_RCC_ICSCR_HSITRIM_0        (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_1        (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_2        (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_3        (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_4        (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
-
-/****************  BIT DEFINITION FOR STM32_RCC_CFGR REGISTER  **************/
-/*!< SW CONFIGURATION */
-#define STM32_RCC_CFGR_SW_POS            0U
-#define STM32_RCC_CFGR_SW_MSK            (0x3UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW                STM32_RCC_CFGR_SW_MSK
-#define STM32_RCC_CFGR_SW_0              (0x1UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW_1              (0x2UL << STM32_RCC_CFGR_SW_POS)
-
-#define STM32_RCC_CFGR_SW_MSI            (0x00000000UL)
-#define STM32_RCC_CFGR_SW_HSI            (0x00000001UL)
-#define STM32_RCC_CFGR_SW_HSE            (0x00000002UL)
-#define STM32_RCC_CFGR_SW_PLL            (0x00000003UL)
-
-/*!< SWS CONFIGURATION */
-#define STM32_RCC_CFGR_SWS_POS           2U
-#define STM32_RCC_CFGR_SWS_MSK           (0x3UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS               STM32_RCC_CFGR_SWS_MSK
-#define STM32_RCC_CFGR_SWS_0             (0x1UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS_1             (0x2UL << STM32_RCC_CFGR_SWS_POS)
-
-#define STM32_RCC_CFGR_SWS_MSI           (0x00000000UL)
-#define STM32_RCC_CFGR_SWS_HSI           (0x00000004UL)
-#define STM32_RCC_CFGR_SWS_HSE           (0x00000008UL)
-#define STM32_RCC_CFGR_SWS_PLL           (0x0000000CUL)
-
-/*!< HPRE CONFIGURATION */
-#define STM32_RCC_CFGR_HPRE_POS          4U
-#define STM32_RCC_CFGR_HPRE_MSK          (0xFUL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE              STM32_RCC_CFGR_HPRE_MSK
-#define STM32_RCC_CFGR_HPRE_0            (0x1UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_1            (0x2UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_2            (0x4UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_3            (0x8UL << STM32_RCC_CFGR_HPRE_POS)
-
-#define STM32_RCC_CFGR_HPRE_DIV1         (0x00000000UL)
-#define STM32_RCC_CFGR_HPRE_DIV2         (0x00000080UL)
-#define STM32_RCC_CFGR_HPRE_DIV4         (0x00000090UL)
-#define STM32_RCC_CFGR_HPRE_DIV8         (0x000000A0UL)
-#define STM32_RCC_CFGR_HPRE_DIV16        (0x000000B0UL)
-#define STM32_RCC_CFGR_HPRE_DIV64        (0x000000C0UL)
-#define STM32_RCC_CFGR_HPRE_DIV128       (0x000000D0UL)
-#define STM32_RCC_CFGR_HPRE_DIV256       (0x000000E0UL)
-#define STM32_RCC_CFGR_HPRE_DIV512       (0x000000F0UL)
-
-/*!< PPRE1 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE1_POS         8U
-#define STM32_RCC_CFGR_PPRE1_MSK         (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1             STM32_RCC_CFGR_PPRE1_MSK
-#define STM32_RCC_CFGR_PPRE1_0           (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_1           (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_2           (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
-
-#define STM32_RCC_CFGR_PPRE1_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE1_DIV2        (0x00000400UL)
-#define STM32_RCC_CFGR_PPRE1_DIV4        (0x00000500UL)
-#define STM32_RCC_CFGR_PPRE1_DIV8        (0x00000600UL)
-#define STM32_RCC_CFGR_PPRE1_DIV16       (0x00000700UL)
-
-/*!< PPRE2 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE2_POS         11U
-#define STM32_RCC_CFGR_PPRE2_MSK         (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2             STM32_RCC_CFGR_PPRE2_MSK
-#define STM32_RCC_CFGR_PPRE2_0           (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_1           (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_2           (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
-
-#define STM32_RCC_CFGR_PPRE2_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV2        (0x00002000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV4        (0x00002800UL)
-#define STM32_RCC_CFGR_PPRE2_DIV8        (0x00003000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV16       (0x00003800UL)
-
-#define STM32_RCC_CFGR_STOPWUCK_POS      15U
-#define STM32_RCC_CFGR_STOPWUCK_MSK      (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
-#define STM32_RCC_CFGR_STOPWUCK          STM32_RCC_CFGR_STOPWUCK_MSK
-
-/*!< MCOSEL CONFIGURATION */
-#define STM32_RCC_CFGR_MCOSEL_POS        24U
-#define STM32_RCC_CFGR_MCOSEL_MSK        (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL            STM32_RCC_CFGR_MCOSEL_MSK
-#define STM32_RCC_CFGR_MCOSEL_0          (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_1          (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_2          (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_3          (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_POS        28U
-#define STM32_RCC_CFGR_MCOPRE_MSK        (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE            STM32_RCC_CFGR_MCOPRE_MSK
-#define STM32_RCC_CFGR_MCOPRE_0          (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_1          (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_2          (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_DIV1       (0x00000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV2       (0x10000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV4       (0x20000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV8       (0x30000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV16      (0x40000000UL)
-
-/* LEGACY ALIASES */
-#define STM32_RCC_CFGR_MCO_PRE           STM32_RCC_CFGR_MCOPRE
-#define STM32_RCC_CFGR_MCO_PRE_1         STM32_RCC_CFGR_MCOPRE_DIV1
-#define STM32_RCC_CFGR_MCO_PRE_2         STM32_RCC_CFGR_MCOPRE_DIV2
-#define STM32_RCC_CFGR_MCO_PRE_4         STM32_RCC_CFGR_MCOPRE_DIV4
-#define STM32_RCC_CFGR_MCO_PRE_8         STM32_RCC_CFGR_MCOPRE_DIV8
-#define STM32_RCC_CFGR_MCO_PRE_16        STM32_RCC_CFGR_MCOPRE_DIV16
-
-/****************  BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER  ***********/
-#define STM32_RCC_PLLCFGR_PLLSRC_POS     0U
-#define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK
-
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI_POS 0U
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK \
-	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_MSI_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI_POS 1U
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK \
-	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_HSI_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \
-	(0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE     STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
-
-#define STM32_RCC_PLLCFGR_PLLM_POS       4U
-#define STM32_RCC_PLLCFGR_PLLM_MSK       (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM           STM32_RCC_PLLCFGR_PLLM_MSK
-#define STM32_RCC_PLLCFGR_PLLM_0         (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_1         (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_2         (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
-
-#define STM32_RCC_PLLCFGR_PLLN_POS       8U
-#define STM32_RCC_PLLCFGR_PLLN_MSK       (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN           STM32_RCC_PLLCFGR_PLLN_MSK
-#define STM32_RCC_PLLCFGR_PLLN_0         (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_1         (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_2         (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_3         (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_4         (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_5         (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_6         (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPEN_POS     16U
-#define STM32_RCC_PLLCFGR_PLLPEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
-#define STM32_RCC_PLLCFGR_PLLPEN         STM32_RCC_PLLCFGR_PLLPEN_MSK
-#define STM32_RCC_PLLCFGR_PLLP_POS       17U
-#define STM32_RCC_PLLCFGR_PLLP_MSK       (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
-#define STM32_RCC_PLLCFGR_PLLP           STM32_RCC_PLLCFGR_PLLP_MSK
-#define STM32_RCC_PLLCFGR_PLLQEN_POS     20U
-#define STM32_RCC_PLLCFGR_PLLQEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
-#define STM32_RCC_PLLCFGR_PLLQEN         STM32_RCC_PLLCFGR_PLLQEN_MSK
-
-#define STM32_RCC_PLLCFGR_PLLQ_POS       21U
-#define STM32_RCC_PLLCFGR_PLLQ_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ           STM32_RCC_PLLCFGR_PLLQ_MSK
-#define STM32_RCC_PLLCFGR_PLLQ_0         (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ_1         (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-
-#define STM32_RCC_PLLCFGR_PLLREN_POS     24U
-#define STM32_RCC_PLLCFGR_PLLREN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
-#define STM32_RCC_PLLCFGR_PLLREN         STM32_RCC_PLLCFGR_PLLREN_MSK
-#define STM32_RCC_PLLCFGR_PLLR_POS       25U
-#define STM32_RCC_PLLCFGR_PLLR_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR           STM32_RCC_PLLCFGR_PLLR_MSK
-#define STM32_RCC_PLLCFGR_PLLR_0         (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR_1         (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPDIV_POS  27U
-#define STM32_RCC_PLLCFGR_PLLPDIV_MSK  (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV      STM32_RCC_PLLCFGR_PLLPDIV_MSK
-#define STM32_RCC_PLLCFGR_PLLPDIV_0    (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_1    (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_2    (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_3    (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_4    (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-
-/****************  BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER  ********/
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK \
-	(0x7FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_0 \
-	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_1 \
-	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_2 \
-	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_3 \
-	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_4 \
-	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_5 \
-	(0x20UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \
-	(0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS  16U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS 17U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS 20U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS 21U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK \
-	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_0 \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_1 \
-	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS 24U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS 25U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK \
-	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_0 \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_1 \
-	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS 27U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK \
-	(0x1FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 \
-	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 \
-	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 \
-	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 \
-	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 \
-	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-
-/**************  BIT DEFINITION FOR STM32_RCC_CIER REGISTER  ******************/
-#define STM32_RCC_CIER_LSIRDYIE_POS 0U
-#define STM32_RCC_CIER_LSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_LSIRDYIE_POS)
-#define STM32_RCC_CIER_LSIRDYIE STM32_RCC_CIER_LSIRDYIE_MSK
-#define STM32_RCC_CIER_LSERDYIE_POS 1U
-#define STM32_RCC_CIER_LSERDYIE_MSK (0x1UL << STM32_RCC_CIER_LSERDYIE_POS)
-#define STM32_RCC_CIER_LSERDYIE STM32_RCC_CIER_LSERDYIE_MSK
-#define STM32_RCC_CIER_MSIRDYIE_POS 2U
-#define STM32_RCC_CIER_MSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_MSIRDYIE_POS)
-#define STM32_RCC_CIER_MSIRDYIE STM32_RCC_CIER_MSIRDYIE_MSK
-#define STM32_RCC_CIER_HSIRDYIE_POS 3U
-#define STM32_RCC_CIER_HSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_HSIRDYIE_POS)
-#define STM32_RCC_CIER_HSIRDYIE STM32_RCC_CIER_HSIRDYIE_MSK
-#define STM32_RCC_CIER_HSERDYIE_POS 4U
-#define STM32_RCC_CIER_HSERDYIE_MSK (0x1UL << STM32_RCC_CIER_HSERDYIE_POS)
-#define STM32_RCC_CIER_HSERDYIE STM32_RCC_CIER_HSERDYIE_MSK
-#define STM32_RCC_CIER_PLLRDYIE_POS 5U
-#define STM32_RCC_CIER_PLLRDYIE_MSK (0x1UL << STM32_RCC_CIER_PLLRDYIE_POS)
-#define STM32_RCC_CIER_PLLRDYIE STM32_RCC_CIER_PLLRDYIE_MSK
-#define STM32_RCC_CIER_PLLSAI1RDYIE_POS 6U
-#define STM32_RCC_CIER_PLLSAI1RDYIE_MSK \
-	(0x1UL << STM32_RCC_CIER_PLLSAI1RDYIE_POS)
-#define STM32_RCC_CIER_PLLSAI1RDYIE STM32_RCC_CIER_PLLSAI1RDYIE_MSK
-#define STM32_RCC_CIER_LSECSSIE_POS 9U
-#define STM32_RCC_CIER_LSECSSIE_MSK (0x1UL << STM32_RCC_CIER_LSECSSIE_POS)
-#define STM32_RCC_CIER_LSECSSIE STM32_RCC_CIER_LSECSSIE_MSK
-#define STM32_RCC_CIER_HSI48RDYIE_POS 10U
-#define STM32_RCC_CIER_HSI48RDYIE_MSK (0x1UL << STM32_RCC_CIER_HSI48RDYIE_POS)
-#define STM32_RCC_CIER_HSI48RDYIE STM32_RCC_CIER_HSI48RDYIE_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CIFR REGISTER  ******************/
-#define STM32_RCC_CIFR_LSIRDYF_POS 0U
-#define STM32_RCC_CIFR_LSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_LSIRDYF_POS)
-#define STM32_RCC_CIFR_LSIRDYF STM32_RCC_CIFR_LSIRDYF_MSK
-#define STM32_RCC_CIFR_LSERDYF_POS 1U
-#define STM32_RCC_CIFR_LSERDYF_MSK (0x1UL << STM32_RCC_CIFR_LSERDYF_POS)
-#define STM32_RCC_CIFR_LSERDYF STM32_RCC_CIFR_LSERDYF_MSK
-#define STM32_RCC_CIFR_MSIRDYF_POS 2U
-#define STM32_RCC_CIFR_MSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_MSIRDYF_POS)
-#define STM32_RCC_CIFR_MSIRDYF STM32_RCC_CIFR_MSIRDYF_MSK
-#define STM32_RCC_CIFR_HSIRDYF_POS 3U
-#define STM32_RCC_CIFR_HSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_HSIRDYF_POS)
-#define STM32_RCC_CIFR_HSIRDYF STM32_RCC_CIFR_HSIRDYF_MSK
-#define STM32_RCC_CIFR_HSERDYF_POS 4U
-#define STM32_RCC_CIFR_HSERDYF_MSK (0x1UL << STM32_RCC_CIFR_HSERDYF_POS)
-#define STM32_RCC_CIFR_HSERDYF STM32_RCC_CIFR_HSERDYF_MSK
-#define STM32_RCC_CIFR_PLLRDYF_POS 5U
-#define STM32_RCC_CIFR_PLLRDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLRDYF_POS)
-#define STM32_RCC_CIFR_PLLRDYF STM32_RCC_CIFR_PLLRDYF_MSK
-#define STM32_RCC_CIFR_PLLSAI1RDYF_POS 6U
-#define STM32_RCC_CIFR_PLLSAI1RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI1RDYF_POS)
-#define STM32_RCC_CIFR_PLLSAI1RDYF STM32_RCC_CIFR_PLLSAI1RDYF_MSK
-#define STM32_RCC_CIFR_CSSF_POS 8U
-#define STM32_RCC_CIFR_CSSF_MSK (0x1UL << STM32_RCC_CIFR_CSSF_POS)
-#define STM32_RCC_CIFR_CSSF STM32_RCC_CIFR_CSSF_MSK
-#define STM32_RCC_CIFR_LSECSSF_POS 9U
-#define STM32_RCC_CIFR_LSECSSF_MSK (0x1UL << STM32_RCC_CIFR_LSECSSF_POS)
-#define STM32_RCC_CIFR_LSECSSF STM32_RCC_CIFR_LSECSSF_MSK
-#define STM32_RCC_CIFR_HSI48RDYF_POS 10U
-#define STM32_RCC_CIFR_HSI48RDYF_MSK (0x1UL << STM32_RCC_CIFR_HSI48RDYF_POS)
-#define STM32_RCC_CIFR_HSI48RDYF STM32_RCC_CIFR_HSI48RDYF_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CICR REGISTER  ******************/
-#define STM32_RCC_CICR_LSIRDYC_POS 0U
-#define STM32_RCC_CICR_LSIRDYC_MSK (0x1UL << STM32_RCC_CICR_LSIRDYC_POS)
-#define STM32_RCC_CICR_LSIRDYC STM32_RCC_CICR_LSIRDYC_MSK
-#define STM32_RCC_CICR_LSERDYC_POS 1U
-#define STM32_RCC_CICR_LSERDYC_MSK (0x1UL << STM32_RCC_CICR_LSERDYC_POS)
-#define STM32_RCC_CICR_LSERDYC STM32_RCC_CICR_LSERDYC_MSK
-#define STM32_RCC_CICR_MSIRDYC_POS 2U
-#define STM32_RCC_CICR_MSIRDYC_MSK (0x1UL << STM32_RCC_CICR_MSIRDYC_POS)
-#define STM32_RCC_CICR_MSIRDYC STM32_RCC_CICR_MSIRDYC_MSK
-#define STM32_RCC_CICR_HSIRDYC_POS 3U
-#define STM32_RCC_CICR_HSIRDYC_MSK (0x1UL << STM32_RCC_CICR_HSIRDYC_POS)
-#define STM32_RCC_CICR_HSIRDYC STM32_RCC_CICR_HSIRDYC_MSK
-#define STM32_RCC_CICR_HSERDYC_POS 4U
-#define STM32_RCC_CICR_HSERDYC_MSK (0x1UL << STM32_RCC_CICR_HSERDYC_POS)
-#define STM32_RCC_CICR_HSERDYC STM32_RCC_CICR_HSERDYC_MSK
-#define STM32_RCC_CICR_PLLRDYC_POS 5U
-#define STM32_RCC_CICR_PLLRDYC_MSK (0x1UL << STM32_RCC_CICR_PLLRDYC_POS)
-#define STM32_RCC_CICR_PLLRDYC STM32_RCC_CICR_PLLRDYC_MSK
-#define STM32_RCC_CICR_PLLSAI1RDYC_POS 6U
-#define STM32_RCC_CICR_PLLSAI1RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI1RDYC_POS)
-#define STM32_RCC_CICR_PLLSAI1RDYC STM32_RCC_CICR_PLLSAI1RDYC_MSK
-#define STM32_RCC_CICR_CSSC_POS 8U
-#define STM32_RCC_CICR_CSSC_MSK (0x1UL << STM32_RCC_CICR_CSSC_POS)
-#define STM32_RCC_CICR_CSSC STM32_RCC_CICR_CSSC_MSK
-#define STM32_RCC_CICR_LSECSSC_POS 9U
-#define STM32_RCC_CICR_LSECSSC_MSK (0x1UL << STM32_RCC_CICR_LSECSSC_POS)
-#define STM32_RCC_CICR_LSECSSC STM32_RCC_CICR_LSECSSC_MSK
-#define STM32_RCC_CICR_HSI48RDYC_POS 10U
-#define STM32_RCC_CICR_HSI48RDYC_MSK (0x1UL << STM32_RCC_CICR_HSI48RDYC_POS)
-#define STM32_RCC_CICR_HSI48RDYC STM32_RCC_CICR_HSI48RDYC_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB1RSTR REGISTER  **************/
-#define STM32_RCC_AHB1RSTR_DMA1RST_POS 0U
-#define STM32_RCC_AHB1RSTR_DMA1RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA1RST_POS)
-#define STM32_RCC_AHB1RSTR_DMA1RST STM32_RCC_AHB1RSTR_DMA1RST_MSK
-#define STM32_RCC_AHB1RSTR_DMA2RST_POS 1U
-#define STM32_RCC_AHB1RSTR_DMA2RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA2RST_POS)
-#define STM32_RCC_AHB1RSTR_DMA2RST STM32_RCC_AHB1RSTR_DMA2RST_MSK
-#define STM32_RCC_AHB1RSTR_FLASHRST_POS 8U
-#define STM32_RCC_AHB1RSTR_FLASHRST_MSK \
-	(0x1UL << STM32_RCC_AHB1RSTR_FLASHRST_POS)
-#define STM32_RCC_AHB1RSTR_FLASHRST STM32_RCC_AHB1RSTR_FLASHRST_MSK
-#define STM32_RCC_AHB1RSTR_CRCRST_POS 12U
-#define STM32_RCC_AHB1RSTR_CRCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_CRCRST_POS)
-#define STM32_RCC_AHB1RSTR_CRCRST STM32_RCC_AHB1RSTR_CRCRST_MSK
-#define STM32_RCC_AHB1RSTR_TSCRST_POS 16U
-#define STM32_RCC_AHB1RSTR_TSCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_TSCRST_POS)
-#define STM32_RCC_AHB1RSTR_TSCRST STM32_RCC_AHB1RSTR_TSCRST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB2RSTR REGISTER  **************/
-#define STM32_RCC_AHB2RSTR_GPIOARST_POS 0U
-#define STM32_RCC_AHB2RSTR_GPIOARST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOARST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOARST STM32_RCC_AHB2RSTR_GPIOARST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOBRST_POS 1U
-#define STM32_RCC_AHB2RSTR_GPIOBRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOBRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOBRST STM32_RCC_AHB2RSTR_GPIOBRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOCRST_POS 2U
-#define STM32_RCC_AHB2RSTR_GPIOCRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOCRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOCRST STM32_RCC_AHB2RSTR_GPIOCRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIODRST_POS 3U
-#define STM32_RCC_AHB2RSTR_GPIODRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIODRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIODRST STM32_RCC_AHB2RSTR_GPIODRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOERST_POS 4U
-#define STM32_RCC_AHB2RSTR_GPIOERST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOERST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOERST STM32_RCC_AHB2RSTR_GPIOERST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOHRST_POS 7U
-#define STM32_RCC_AHB2RSTR_GPIOHRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOHRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOHRST STM32_RCC_AHB2RSTR_GPIOHRST_MSK
-#define STM32_RCC_AHB2RSTR_ADCRST_POS 13U
-#define STM32_RCC_AHB2RSTR_ADCRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_ADCRST_POS)
-#define STM32_RCC_AHB2RSTR_ADCRST STM32_RCC_AHB2RSTR_ADCRST_MSK
-#define STM32_RCC_AHB2RSTR_AESRST_POS 16U
-#define STM32_RCC_AHB2RSTR_AESRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_AESRST_POS)
-#define STM32_RCC_AHB2RSTR_AESRST STM32_RCC_AHB2RSTR_AESRST_MSK
-#define STM32_RCC_AHB2RSTR_RNGRST_POS 18U
-#define STM32_RCC_AHB2RSTR_RNGRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_RNGRST_POS)
-#define STM32_RCC_AHB2RSTR_RNGRST STM32_RCC_AHB2RSTR_RNGRST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_AHB3RSTR REGISTER  **************/
-#define STM32_RCC_AHB3RSTR_QSPIRST_POS 8U
-#define STM32_RCC_AHB3RSTR_QSPIRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_QSPIRST_POS)
-#define STM32_RCC_AHB3RSTR_QSPIRST STM32_RCC_AHB3RSTR_QSPIRST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR1 REGISTER  **************/
-#define STM32_RCC_APB1RSTR1_TIM2RST_POS 0U
-#define STM32_RCC_APB1RSTR1_TIM2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM2RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM2RST STM32_RCC_APB1RSTR1_TIM2RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM6RST_POS 4U
-#define STM32_RCC_APB1RSTR1_TIM6RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM6RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM6RST STM32_RCC_APB1RSTR1_TIM6RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM7RST_POS 5U
-#define STM32_RCC_APB1RSTR1_TIM7RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM7RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM7RST STM32_RCC_APB1RSTR1_TIM7RST_MSK
-#define STM32_RCC_APB1RSTR1_LCDRST_POS 9U
-#define STM32_RCC_APB1RSTR1_LCDRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_LCDRST_POS)
-#define STM32_RCC_APB1RSTR1_LCDRST STM32_RCC_APB1RSTR1_LCDRST_MSK
-#define STM32_RCC_APB1RSTR1_SPI2RST_POS 14U
-#define STM32_RCC_APB1RSTR1_SPI2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_SPI2RST_POS)
-#define STM32_RCC_APB1RSTR1_SPI2RST STM32_RCC_APB1RSTR1_SPI2RST_MSK
-#define STM32_RCC_APB1RSTR1_SPI3RST_POS 15U
-#define STM32_RCC_APB1RSTR1_SPI3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_SPI3RST_POS)
-#define STM32_RCC_APB1RSTR1_SPI3RST STM32_RCC_APB1RSTR1_SPI3RST_MSK
-#define STM32_RCC_APB1RSTR1_USART2RST_POS 17U
-#define STM32_RCC_APB1RSTR1_USART2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART2RST_POS)
-#define STM32_RCC_APB1RSTR1_USART2RST STM32_RCC_APB1RSTR1_USART2RST_MSK
-#define STM32_RCC_APB1RSTR1_USART3RST_POS 18U
-#define STM32_RCC_APB1RSTR1_USART3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART3RST_POS)
-#define STM32_RCC_APB1RSTR1_USART3RST STM32_RCC_APB1RSTR1_USART3RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C1RST_POS 21U
-#define STM32_RCC_APB1RSTR1_I2C1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C1RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C1RST STM32_RCC_APB1RSTR1_I2C1RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C2RST_POS 22U
-#define STM32_RCC_APB1RSTR1_I2C2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C2RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C2RST STM32_RCC_APB1RSTR1_I2C2RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C3RST_POS 23U
-#define STM32_RCC_APB1RSTR1_I2C3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C3RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C3RST STM32_RCC_APB1RSTR1_I2C3RST_MSK
-#define STM32_RCC_APB1RSTR1_CRSRST_POS 24U
-#define STM32_RCC_APB1RSTR1_CRSRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_CRSRST_POS)
-#define STM32_RCC_APB1RSTR1_CRSRST STM32_RCC_APB1RSTR1_CRSRST_MSK
-#define STM32_RCC_APB1RSTR1_CAN1RST_POS 25U
-#define STM32_RCC_APB1RSTR1_CAN1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_CAN1RST_POS)
-#define STM32_RCC_APB1RSTR1_CAN1RST STM32_RCC_APB1RSTR1_CAN1RST_MSK
-#define STM32_RCC_APB1RSTR1_USBFSRST_POS 26U
-#define STM32_RCC_APB1RSTR1_USBFSRST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USBFSRST_POS)
-#define STM32_RCC_APB1RSTR1_USBFSRST STM32_RCC_APB1RSTR1_USBFSRST_MSK
-#define STM32_RCC_APB1RSTR1_PWRRST_POS 28U
-#define STM32_RCC_APB1RSTR1_PWRRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_PWRRST_POS)
-#define STM32_RCC_APB1RSTR1_PWRRST STM32_RCC_APB1RSTR1_PWRRST_MSK
-#define STM32_RCC_APB1RSTR1_DAC1RST_POS 29U
-#define STM32_RCC_APB1RSTR1_DAC1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_DAC1RST_POS)
-#define STM32_RCC_APB1RSTR1_DAC1RST STM32_RCC_APB1RSTR1_DAC1RST_MSK
-#define STM32_RCC_APB1RSTR1_OPAMPRST_POS 30U
-#define STM32_RCC_APB1RSTR1_OPAMPRST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_OPAMPRST_POS)
-#define STM32_RCC_APB1RSTR1_OPAMPRST STM32_RCC_APB1RSTR1_OPAMPRST_MSK
-#define STM32_RCC_APB1RSTR1_LPTIM1RST_POS 31U
-#define STM32_RCC_APB1RSTR1_LPTIM1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_LPTIM1RST_POS)
-#define STM32_RCC_APB1RSTR1_LPTIM1RST STM32_RCC_APB1RSTR1_LPTIM1RST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
-#define STM32_RCC_APB1RSTR2_LPUART1RST_POS 0U
-#define STM32_RCC_APB1RSTR2_LPUART1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPUART1RST_POS)
-#define STM32_RCC_APB1RSTR2_LPUART1RST STM32_RCC_APB1RSTR2_LPUART1RST_MSK
-#define STM32_RCC_APB1RSTR2_SWPMI1RST_POS 2U
-#define STM32_RCC_APB1RSTR2_SWPMI1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_SWPMI1RST_POS)
-#define STM32_RCC_APB1RSTR2_SWPMI1RST STM32_RCC_APB1RSTR2_SWPMI1RST_MSK
-#define STM32_RCC_APB1RSTR2_LPTIM2RST_POS 5U
-#define STM32_RCC_APB1RSTR2_LPTIM2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPTIM2RST_POS)
-#define STM32_RCC_APB1RSTR2_LPTIM2RST STM32_RCC_APB1RSTR2_LPTIM2RST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB2RSTR REGISTER  **************/
-#define STM32_RCC_APB2RSTR_SYSCFGRST_POS 0U
-#define STM32_RCC_APB2RSTR_SYSCFGRST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_SYSCFGRST_POS)
-#define STM32_RCC_APB2RSTR_SYSCFGRST STM32_RCC_APB2RSTR_SYSCFGRST_MSK
-#define STM32_RCC_APB2RSTR_SDMMC1RST_POS 10U
-#define STM32_RCC_APB2RSTR_SDMMC1RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_SDMMC1RST_POS)
-#define STM32_RCC_APB2RSTR_SDMMC1RST STM32_RCC_APB2RSTR_SDMMC1RST_MSK
-#define STM32_RCC_APB2RSTR_TIM1RST_POS 11U
-#define STM32_RCC_APB2RSTR_TIM1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM1RST_POS)
-#define STM32_RCC_APB2RSTR_TIM1RST STM32_RCC_APB2RSTR_TIM1RST_MSK
-#define STM32_RCC_APB2RSTR_SPI1RST_POS 12U
-#define STM32_RCC_APB2RSTR_SPI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SPI1RST_POS)
-#define STM32_RCC_APB2RSTR_SPI1RST STM32_RCC_APB2RSTR_SPI1RST_MSK
-#define STM32_RCC_APB2RSTR_USART1RST_POS 14U
-#define STM32_RCC_APB2RSTR_USART1RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_USART1RST_POS)
-#define STM32_RCC_APB2RSTR_USART1RST STM32_RCC_APB2RSTR_USART1RST_MSK
-#define STM32_RCC_APB2RSTR_TIM15RST_POS 16U
-#define STM32_RCC_APB2RSTR_TIM15RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM15RST_POS)
-#define STM32_RCC_APB2RSTR_TIM15RST STM32_RCC_APB2RSTR_TIM15RST_MSK
-#define STM32_RCC_APB2RSTR_TIM16RST_POS 17U
-#define STM32_RCC_APB2RSTR_TIM16RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM16RST_POS)
-#define STM32_RCC_APB2RSTR_TIM16RST STM32_RCC_APB2RSTR_TIM16RST_MSK
-#define STM32_RCC_APB2RSTR_SAI1RST_POS 21U
-#define STM32_RCC_APB2RSTR_SAI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI1RST_POS)
-#define STM32_RCC_APB2RSTR_SAI1RST STM32_RCC_APB2RSTR_SAI1RST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB1ENR REGISTER  ***************/
-#define STM32_RCC_AHB1ENR_DMA1EN_POS 0U
-#define STM32_RCC_AHB1ENR_DMA1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA1EN_POS)
-#define STM32_RCC_AHB1ENR_DMA1EN STM32_RCC_AHB1ENR_DMA1EN_MSK
-#define STM32_RCC_AHB1ENR_DMA2EN_POS 1U
-#define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS)
-#define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK
-#define STM32_RCC_AHB1ENR_FLASHEN_POS 8U
-#define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS)
-#define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK
-#define STM32_RCC_AHB1ENR_CRCEN_POS 12U
-#define STM32_RCC_AHB1ENR_CRCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_CRCEN_POS)
-#define STM32_RCC_AHB1ENR_CRCEN STM32_RCC_AHB1ENR_CRCEN_MSK
-#define STM32_RCC_AHB1ENR_TSCEN_POS 16U
-#define STM32_RCC_AHB1ENR_TSCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_TSCEN_POS)
-#define STM32_RCC_AHB1ENR_TSCEN STM32_RCC_AHB1ENR_TSCEN_MSK
-
-/***************  BIT DEFINITION FOR STM32_RCC_AHB2ENR REGISTER  *********/
-#define STM32_RCC_AHB2ENR_GPIOAEN_POS 0U
-#define STM32_RCC_AHB2ENR_GPIOAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOAEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOAEN STM32_RCC_AHB2ENR_GPIOAEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOBEN_POS 1U
-#define STM32_RCC_AHB2ENR_GPIOBEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOBEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOBEN STM32_RCC_AHB2ENR_GPIOBEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOCEN_POS 2U
-#define STM32_RCC_AHB2ENR_GPIOCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOCEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOCEN STM32_RCC_AHB2ENR_GPIOCEN_MSK
-#define STM32_RCC_AHB2ENR_GPIODEN_POS 3U
-#define STM32_RCC_AHB2ENR_GPIODEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIODEN_POS)
-#define STM32_RCC_AHB2ENR_GPIODEN STM32_RCC_AHB2ENR_GPIODEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOEEN_POS 4U
-#define STM32_RCC_AHB2ENR_GPIOEEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOEEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOEEN STM32_RCC_AHB2ENR_GPIOEEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOHEN_POS 7U
-#define STM32_RCC_AHB2ENR_GPIOHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOHEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOHEN STM32_RCC_AHB2ENR_GPIOHEN_MSK
-#define STM32_RCC_AHB2ENR_ADCEN_POS 13U
-#define STM32_RCC_AHB2ENR_ADCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_ADCEN_POS)
-#define STM32_RCC_AHB2ENR_ADCEN STM32_RCC_AHB2ENR_ADCEN_MSK
-#define STM32_RCC_AHB2ENR_AESEN_POS 16U
-#define STM32_RCC_AHB2ENR_AESEN_MSK (0x1UL << STM32_RCC_AHB2ENR_AESEN_POS)
-#define STM32_RCC_AHB2ENR_AESEN STM32_RCC_AHB2ENR_AESEN_MSK
-#define STM32_RCC_AHB2ENR_RNGEN_POS 18U
-#define STM32_RCC_AHB2ENR_RNGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_RNGEN_POS)
-#define STM32_RCC_AHB2ENR_RNGEN STM32_RCC_AHB2ENR_RNGEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB3ENR REGISTER  ***************/
-#define STM32_RCC_AHB3ENR_QSPIEN_POS 8U
-#define STM32_RCC_AHB3ENR_QSPIEN_MSK (0x1UL << STM32_RCC_AHB3ENR_QSPIEN_POS)
-#define STM32_RCC_AHB3ENR_QSPIEN STM32_RCC_AHB3ENR_QSPIEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB1ENR1 REGISTER  **************/
-#define STM32_RCC_APB1ENR1_TIM2EN_POS 0U
-#define STM32_RCC_APB1ENR1_TIM2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM2EN_POS)
-#define STM32_RCC_APB1ENR1_TIM2EN STM32_RCC_APB1ENR1_TIM2EN_MSK
-#define STM32_RCC_APB1ENR1_TIM6EN_POS 4U
-#define STM32_RCC_APB1ENR1_TIM6EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM6EN_POS)
-#define STM32_RCC_APB1ENR1_TIM6EN STM32_RCC_APB1ENR1_TIM6EN_MSK
-#define STM32_RCC_APB1ENR1_TIM7EN_POS 5U
-#define STM32_RCC_APB1ENR1_TIM7EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM7EN_POS)
-#define STM32_RCC_APB1ENR1_TIM7EN STM32_RCC_APB1ENR1_TIM7EN_MSK
-#define STM32_RCC_APB1ENR1_LCDEN_POS 9U
-#define STM32_RCC_APB1ENR1_LCDEN_MSK (0x1UL << STM32_RCC_APB1ENR1_LCDEN_POS)
-#define STM32_RCC_APB1ENR1_LCDEN STM32_RCC_APB1ENR1_LCDEN_MSK
-#define STM32_RCC_APB1ENR1_RTCAPBEN_POS 10U
-#define STM32_RCC_APB1ENR1_RTCAPBEN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_RTCAPBEN_POS)
-#define STM32_RCC_APB1ENR1_RTCAPBEN STM32_RCC_APB1ENR1_RTCAPBEN_MSK
-#define STM32_RCC_APB1ENR1_WWDGEN_POS 11U
-#define STM32_RCC_APB1ENR1_WWDGEN_MSK (0x1UL << STM32_RCC_APB1ENR1_WWDGEN_POS)
-#define STM32_RCC_APB1ENR1_WWDGEN STM32_RCC_APB1ENR1_WWDGEN_MSK
-#define STM32_RCC_APB1ENR1_SPI2EN_POS 14U
-#define STM32_RCC_APB1ENR1_SPI2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI2EN_POS)
-#define STM32_RCC_APB1ENR1_SPI2EN STM32_RCC_APB1ENR1_SPI2EN_MSK
-#define STM32_RCC_APB1ENR1_SPI3EN_POS 15U
-#define STM32_RCC_APB1ENR1_SPI3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI3EN_POS)
-#define STM32_RCC_APB1ENR1_SPI3EN STM32_RCC_APB1ENR1_SPI3EN_MSK
-#define STM32_RCC_APB1ENR1_USART2EN_POS 17U
-#define STM32_RCC_APB1ENR1_USART2EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_USART2EN_POS)
-#define STM32_RCC_APB1ENR1_USART2EN STM32_RCC_APB1ENR1_USART2EN_MSK
-#define STM32_RCC_APB1ENR1_USART3EN_POS 18U
-#define STM32_RCC_APB1ENR1_USART3EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS)
-#define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK
-#define STM32_RCC_APB1ENR1_I2C1EN_POS 21U
-#define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS)
-#define STM32_RCC_APB1ENR1_I2C1EN STM32_RCC_APB1ENR1_I2C1EN_MSK
-#define STM32_RCC_APB1ENR1_I2C2EN_POS 22U
-#define STM32_RCC_APB1ENR1_I2C2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C2EN_POS)
-#define STM32_RCC_APB1ENR1_I2C2EN STM32_RCC_APB1ENR1_I2C2EN_MSK
-#define STM32_RCC_APB1ENR1_I2C3EN_POS 23U
-#define STM32_RCC_APB1ENR1_I2C3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C3EN_POS)
-#define STM32_RCC_APB1ENR1_I2C3EN STM32_RCC_APB1ENR1_I2C3EN_MSK
-#define STM32_RCC_APB1ENR1_CRSEN_POS 24U
-#define STM32_RCC_APB1ENR1_CRSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_CRSEN_POS)
-#define STM32_RCC_APB1ENR1_CRSEN STM32_RCC_APB1ENR1_CRSEN_MSK
-#define STM32_RCC_APB1ENR1_CAN1EN_POS 25U
-#define STM32_RCC_APB1ENR1_CAN1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_CAN1EN_POS)
-#define STM32_RCC_APB1ENR1_CAN1EN STM32_RCC_APB1ENR1_CAN1EN_MSK
-#define STM32_RCC_APB1ENR1_USBFSEN_POS 26U
-#define STM32_RCC_APB1ENR1_USBFSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_USBFSEN_POS)
-#define STM32_RCC_APB1ENR1_USBFSEN STM32_RCC_APB1ENR1_USBFSEN_MSK
-#define STM32_RCC_APB1ENR1_PWREN_POS 28U
-#define STM32_RCC_APB1ENR1_PWREN_MSK (0x1UL << STM32_RCC_APB1ENR1_PWREN_POS)
-#define STM32_RCC_APB1ENR1_PWREN STM32_RCC_APB1ENR1_PWREN_MSK
-#define STM32_RCC_APB1ENR1_DAC1EN_POS 29U
-#define STM32_RCC_APB1ENR1_DAC1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_DAC1EN_POS)
-#define STM32_RCC_APB1ENR1_DAC1EN STM32_RCC_APB1ENR1_DAC1EN_MSK
-#define STM32_RCC_APB1ENR1_OPAMPEN_POS 30U
-#define STM32_RCC_APB1ENR1_OPAMPEN_MSK (0x1UL << STM32_RCC_APB1ENR1_OPAMPEN_POS)
-#define STM32_RCC_APB1ENR1_OPAMPEN STM32_RCC_APB1ENR1_OPAMPEN_MSK
-#define STM32_RCC_APB1ENR1_LPTIM1EN_POS 31U
-#define STM32_RCC_APB1ENR1_LPTIM1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_LPTIM1EN_POS)
-#define STM32_RCC_APB1ENR1_LPTIM1EN STM32_RCC_APB1ENR1_LPTIM1EN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
-#define STM32_RCC_APB1ENR2_LPUART1EN_POS 0U
-#define STM32_RCC_APB1ENR2_LPUART1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS)
-#define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK
-#define STM32_RCC_APB1ENR2_SWPMI1EN_POS 2U
-#define STM32_RCC_APB1ENR2_SWPMI1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_SWPMI1EN_POS)
-#define STM32_RCC_APB1ENR2_SWPMI1EN STM32_RCC_APB1ENR2_SWPMI1EN_MSK
-#define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U
-#define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPTIM2EN_POS)
-#define STM32_RCC_APB1ENR2_LPTIM2EN STM32_RCC_APB1ENR2_LPTIM2EN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER  ***************/
-#define STM32_RCC_APB2ENR_SYSCFGEN_POS 0U
-#define STM32_RCC_APB2ENR_SYSCFGEN_MSK (0x1UL << STM32_RCC_APB2ENR_SYSCFGEN_POS)
-#define STM32_RCC_APB2ENR_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN_MSK
-#define STM32_RCC_APB2ENR_FWEN_POS 7U
-#define STM32_RCC_APB2ENR_FWEN_MSK (0x1UL << STM32_RCC_APB2ENR_FWEN_POS)
-#define STM32_RCC_APB2ENR_FWEN STM32_RCC_APB2ENR_FWEN_MSK
-#define STM32_RCC_APB2ENR_SDMMC1EN_POS 10U
-#define STM32_RCC_APB2ENR_SDMMC1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SDMMC1EN_POS)
-#define STM32_RCC_APB2ENR_SDMMC1EN STM32_RCC_APB2ENR_SDMMC1EN_MSK
-#define STM32_RCC_APB2ENR_TIM1EN_POS 11U
-#define STM32_RCC_APB2ENR_TIM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM1EN_POS)
-#define STM32_RCC_APB2ENR_TIM1EN STM32_RCC_APB2ENR_TIM1EN_MSK
-#define STM32_RCC_APB2ENR_SPI1EN_POS 12U
-#define STM32_RCC_APB2ENR_SPI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SPI1EN_POS)
-#define STM32_RCC_APB2ENR_SPI1EN STM32_RCC_APB2ENR_SPI1EN_MSK
-#define STM32_RCC_APB2ENR_USART1EN_POS 14U
-#define STM32_RCC_APB2ENR_USART1EN_MSK (0x1UL << STM32_RCC_APB2ENR_USART1EN_POS)
-#define STM32_RCC_APB2ENR_USART1EN STM32_RCC_APB2ENR_USART1EN_MSK
-#define STM32_RCC_APB2ENR_TIM15EN_POS 16U
-#define STM32_RCC_APB2ENR_TIM15EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM15EN_POS)
-#define STM32_RCC_APB2ENR_TIM15EN STM32_RCC_APB2ENR_TIM15EN_MSK
-#define STM32_RCC_APB2ENR_TIM16EN_POS 17U
-#define STM32_RCC_APB2ENR_TIM16EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM16EN_POS)
-#define STM32_RCC_APB2ENR_TIM16EN STM32_RCC_APB2ENR_TIM16EN_MSK
-#define STM32_RCC_APB2ENR_SAI1EN_POS 21U
-#define STM32_RCC_APB2ENR_SAI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI1EN_POS)
-#define STM32_RCC_APB2ENR_SAI1EN STM32_RCC_APB2ENR_SAI1EN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_AHB1SMENR REGISTER  ***************/
-#define STM32_RCC_AHB1SMENR_DMA1SMEN_POS 0U
-#define STM32_RCC_AHB1SMENR_DMA1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMA1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMA1SMEN STM32_RCC_AHB1SMENR_DMA1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_DMA2SMEN_POS 1U
-#define STM32_RCC_AHB1SMENR_DMA2SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMA2SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMA2SMEN STM32_RCC_AHB1SMENR_DMA2SMEN_MSK
-#define STM32_RCC_AHB1SMENR_FLASHSMEN_POS 8U
-#define STM32_RCC_AHB1SMENR_FLASHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_FLASHSMEN_POS)
-#define STM32_RCC_AHB1SMENR_FLASHSMEN STM32_RCC_AHB1SMENR_FLASHSMEN_MSK
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN_POS 9U
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_SRAM1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_CRCSMEN_POS 12U
-#define STM32_RCC_AHB1SMENR_CRCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_CRCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_CRCSMEN STM32_RCC_AHB1SMENR_CRCSMEN_MSK
-#define STM32_RCC_AHB1SMENR_TSCSMEN_POS 16U
-#define STM32_RCC_AHB1SMENR_TSCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_TSCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_TSCSMEN STM32_RCC_AHB1SMENR_TSCSMEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB2SMENR REGISTER  *************/
-#define STM32_RCC_AHB2SMENR_GPIOASMEN_POS 0U
-#define STM32_RCC_AHB2SMENR_GPIOASMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOASMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOASMEN STM32_RCC_AHB2SMENR_GPIOASMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN_POS 1U
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOBSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN_POS 2U
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOCSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIODSMEN_POS 3U
-#define STM32_RCC_AHB2SMENR_GPIODSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIODSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIODSMEN STM32_RCC_AHB2SMENR_GPIODSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOESMEN_POS 4U
-#define STM32_RCC_AHB2SMENR_GPIOESMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOESMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOESMEN STM32_RCC_AHB2SMENR_GPIOESMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN_POS 7U
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOHSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN_POS 9U
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_SRAM2SMEN_POS)
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK
-#define STM32_RCC_AHB2SMENR_ADCSMEN_POS 13U
-#define STM32_RCC_AHB2SMENR_ADCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_ADCSMEN_POS)
-#define STM32_RCC_AHB2SMENR_ADCSMEN STM32_RCC_AHB2SMENR_ADCSMEN_MSK
-#define STM32_RCC_AHB2SMENR_AESSMEN_POS 16U
-#define STM32_RCC_AHB2SMENR_AESSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_AESSMEN_POS)
-#define STM32_RCC_AHB2SMENR_AESSMEN STM32_RCC_AHB2SMENR_AESSMEN_MSK
-#define STM32_RCC_AHB2SMENR_RNGSMEN_POS 18U
-#define STM32_RCC_AHB2SMENR_RNGSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_RNGSMEN_POS)
-#define STM32_RCC_AHB2SMENR_RNGSMEN STM32_RCC_AHB2SMENR_RNGSMEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB3SMENR REGISTER  *************/
-#define STM32_RCC_AHB3SMENR_QSPISMEN_POS 8U
-#define STM32_RCC_AHB3SMENR_QSPISMEN_MSK \
-	(0x1UL << STM32_RCC_AHB3SMENR_QSPISMEN_POS)
-#define STM32_RCC_AHB3SMENR_QSPISMEN STM32_RCC_AHB3SMENR_QSPISMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR1 REGISTER  *************/
-#define STM32_RCC_APB1SMENR1_TIM2SMEN_POS 0U
-#define STM32_RCC_APB1SMENR1_TIM2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM2SMEN STM32_RCC_APB1SMENR1_TIM2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM6SMEN_POS 4U
-#define STM32_RCC_APB1SMENR1_TIM6SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM6SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM6SMEN STM32_RCC_APB1SMENR1_TIM6SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM7SMEN_POS 5U
-#define STM32_RCC_APB1SMENR1_TIM7SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM7SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM7SMEN STM32_RCC_APB1SMENR1_TIM7SMEN_MSK
-#define STM32_RCC_APB1SMENR1_LCDSMEN_POS 9U
-#define STM32_RCC_APB1SMENR1_LCDSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_LCDSMEN_POS)
-#define STM32_RCC_APB1SMENR1_LCDSMEN STM32_RCC_APB1SMENR1_LCDSMEN_MSK
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS 10U
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS)
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK
-#define STM32_RCC_APB1SMENR1_WWDGSMEN_POS 11U
-#define STM32_RCC_APB1SMENR1_WWDGSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_WWDGSMEN_POS)
-#define STM32_RCC_APB1SMENR1_WWDGSMEN STM32_RCC_APB1SMENR1_WWDGSMEN_MSK
-#define STM32_RCC_APB1SMENR1_SPI2SMEN_POS 14U
-#define STM32_RCC_APB1SMENR1_SPI2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_SPI2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_SPI2SMEN STM32_RCC_APB1SMENR1_SPI2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_SPI3SMEN_POS 15U
-#define STM32_RCC_APB1SMENR1_SPI3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_SPI3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_SPI3SMEN STM32_RCC_APB1SMENR1_SPI3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART2SMEN_POS 17U
-#define STM32_RCC_APB1SMENR1_USART2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART2SMEN STM32_RCC_APB1SMENR1_USART2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART3SMEN_POS 18U
-#define STM32_RCC_APB1SMENR1_USART3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART3SMEN STM32_RCC_APB1SMENR1_USART3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C1SMEN_POS 21U
-#define STM32_RCC_APB1SMENR1_I2C1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C1SMEN STM32_RCC_APB1SMENR1_I2C1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C2SMEN_POS 22U
-#define STM32_RCC_APB1SMENR1_I2C2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C2SMEN STM32_RCC_APB1SMENR1_I2C2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C3SMEN_POS 23U
-#define STM32_RCC_APB1SMENR1_I2C3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C3SMEN STM32_RCC_APB1SMENR1_I2C3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_CRSSMEN_POS 24U
-#define STM32_RCC_APB1SMENR1_CRSSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_CRSSMEN_POS)
-#define STM32_RCC_APB1SMENR1_CRSSMEN STM32_RCC_APB1SMENR1_CRSSMEN_MSK
-#define STM32_RCC_APB1SMENR1_CAN1SMEN_POS 25U
-#define STM32_RCC_APB1SMENR1_CAN1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_CAN1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_CAN1SMEN STM32_RCC_APB1SMENR1_CAN1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USBFSSMEN_POS 26U
-#define STM32_RCC_APB1SMENR1_USBFSSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USBFSSMEN_POS)
-#define STM32_RCC_APB1SMENR1_USBFSSMEN STM32_RCC_APB1SMENR1_USBFSSMEN_MSK
-#define STM32_RCC_APB1SMENR1_PWRSMEN_POS 28U
-#define STM32_RCC_APB1SMENR1_PWRSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_PWRSMEN_POS)
-#define STM32_RCC_APB1SMENR1_PWRSMEN STM32_RCC_APB1SMENR1_PWRSMEN_MSK
-#define STM32_RCC_APB1SMENR1_DAC1SMEN_POS 29U
-#define STM32_RCC_APB1SMENR1_DAC1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_DAC1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_DAC1SMEN STM32_RCC_APB1SMENR1_DAC1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN_POS 30U
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_OPAMPSMEN_POS)
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS 31U
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR2 REGISTER  *************/
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN_POS 0U
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPUART1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK
-#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS 2U
-#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_SWPMI1SMEN STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS 5U
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_APB2SMENR REGISTER  *************/
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN_POS 0U
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SYSCFGSMEN_POS)
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK
-#define STM32_RCC_APB2SMENR_SDMMC1SMEN_POS 10U
-#define STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SDMMC1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SDMMC1SMEN STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM1SMEN_POS 11U
-#define STM32_RCC_APB2SMENR_TIM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM1SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM1SMEN STM32_RCC_APB2SMENR_TIM1SMEN_MSK
-#define STM32_RCC_APB2SMENR_SPI1SMEN_POS 12U
-#define STM32_RCC_APB2SMENR_SPI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SPI1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SPI1SMEN STM32_RCC_APB2SMENR_SPI1SMEN_MSK
-#define STM32_RCC_APB2SMENR_USART1SMEN_POS 14U
-#define STM32_RCC_APB2SMENR_USART1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_USART1SMEN_POS)
-#define STM32_RCC_APB2SMENR_USART1SMEN STM32_RCC_APB2SMENR_USART1SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM15SMEN_POS 16U
-#define STM32_RCC_APB2SMENR_TIM15SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM15SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM15SMEN STM32_RCC_APB2SMENR_TIM15SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM16SMEN_POS 17U
-#define STM32_RCC_APB2SMENR_TIM16SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM16SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM16SMEN STM32_RCC_APB2SMENR_TIM16SMEN_MSK
-#define STM32_RCC_APB2SMENR_SAI1SMEN_POS 21U
-#define STM32_RCC_APB2SMENR_SAI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SAI1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SAI1SMEN STM32_RCC_APB2SMENR_SAI1SMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_CCIPR REGISTER  ******************/
-#define STM32_RCC_CCIPR_USART1SEL_POS 0U
-#define STM32_RCC_CCIPR_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS)
-#define STM32_RCC_CCIPR_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK
-#define STM32_RCC_CCIPR_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS)
-#define STM32_RCC_CCIPR_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS)
-
-#define STM32_RCC_CCIPR_USART2SEL_POS 2U
-#define STM32_RCC_CCIPR_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS)
-#define STM32_RCC_CCIPR_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK
-#define STM32_RCC_CCIPR_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS)
-#define STM32_RCC_CCIPR_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS)
-
-#define STM32_RCC_CCIPR_USART3SEL_POS 4U
-#define STM32_RCC_CCIPR_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS)
-#define STM32_RCC_CCIPR_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK
-#define STM32_RCC_CCIPR_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS)
-#define STM32_RCC_CCIPR_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS)
-
-#define STM32_RCC_CCIPR_LPUART1SEL_POS 10U
-#define STM32_RCC_CCIPR_LPUART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-#define STM32_RCC_CCIPR_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK
-#define STM32_RCC_CCIPR_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-#define STM32_RCC_CCIPR_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C1SEL_POS 12U
-#define STM32_RCC_CCIPR_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-#define STM32_RCC_CCIPR_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK
-#define STM32_RCC_CCIPR_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-#define STM32_RCC_CCIPR_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C2SEL_POS 14U
-#define STM32_RCC_CCIPR_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-#define STM32_RCC_CCIPR_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK
-#define STM32_RCC_CCIPR_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-#define STM32_RCC_CCIPR_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C3SEL_POS 16U
-#define STM32_RCC_CCIPR_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-#define STM32_RCC_CCIPR_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK
-#define STM32_RCC_CCIPR_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-#define STM32_RCC_CCIPR_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM1SEL_POS 18U
-#define STM32_RCC_CCIPR_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM2SEL_POS 20U
-#define STM32_RCC_CCIPR_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-
-#define STM32_RCC_CCIPR_SAI1SEL_POS 22U
-#define STM32_RCC_CCIPR_SAI1SEL_MSK (0x3UL << STM32_RCC_CCIPR_SAI1SEL_POS)
-#define STM32_RCC_CCIPR_SAI1SEL STM32_RCC_CCIPR_SAI1SEL_MSK
-#define STM32_RCC_CCIPR_SAI1SEL_0 (0x1UL << STM32_RCC_CCIPR_SAI1SEL_POS)
-#define STM32_RCC_CCIPR_SAI1SEL_1 (0x2UL << STM32_RCC_CCIPR_SAI1SEL_POS)
-
-#define STM32_RCC_CCIPR_CLK48SEL_POS 26U
-#define STM32_RCC_CCIPR_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-#define STM32_RCC_CCIPR_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK
-#define STM32_RCC_CCIPR_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-#define STM32_RCC_CCIPR_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-
-#define STM32_RCC_CCIPR_ADCSEL_POS 28U
-#define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS)
-#define STM32_RCC_CCIPR_ADCSEL STM32_RCC_CCIPR_ADCSEL_MSK
-#define STM32_RCC_CCIPR_ADCSEL_0 (0x1UL << STM32_RCC_CCIPR_ADCSEL_POS)
-#define STM32_RCC_CCIPR_ADCSEL_1 (0x2UL << STM32_RCC_CCIPR_ADCSEL_POS)
-
-#define STM32_RCC_CCIPR_SWPMI1SEL_POS 30U
-#define STM32_RCC_CCIPR_SWPMI1SEL_MSK (0x1UL << STM32_RCC_CCIPR_SWPMI1SEL_POS)
-#define STM32_RCC_CCIPR_SWPMI1SEL STM32_RCC_CCIPR_SWPMI1SEL_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_BDCR REGISTER  ******************/
-#define STM32_RCC_BDCR_LSEBYP_POS 2U
-#define STM32_RCC_BDCR_LSEBYP_MSK (0x1UL << STM32_RCC_BDCR_LSEBYP_POS)
-#define STM32_RCC_BDCR_LSEBYP STM32_RCC_BDCR_LSEBYP_MSK
-
-#define STM32_RCC_BDCR_LSEDRV_POS 3U
-#define STM32_RCC_BDCR_LSEDRV_MSK (0x3UL << STM32_RCC_BDCR_LSEDRV_POS)
-#define STM32_RCC_BDCR_LSEDRV STM32_RCC_BDCR_LSEDRV_MSK
-#define STM32_RCC_BDCR_LSEDRV_0 (0x1UL << STM32_RCC_BDCR_LSEDRV_POS)
-#define STM32_RCC_BDCR_LSEDRV_1 (0x2UL << STM32_RCC_BDCR_LSEDRV_POS)
-
-#define STM32_RCC_BDCR_LSECSSON_POS 5U
-#define STM32_RCC_BDCR_LSECSSON_MSK (0x1UL << STM32_RCC_BDCR_LSECSSON_POS)
-#define STM32_RCC_BDCR_LSECSSON STM32_RCC_BDCR_LSECSSON_MSK
-#define STM32_RCC_BDCR_LSECSSD_POS 6U
-#define STM32_RCC_BDCR_LSECSSD_MSK (0x1UL << STM32_RCC_BDCR_LSECSSD_POS)
-#define STM32_RCC_BDCR_LSECSSD STM32_RCC_BDCR_LSECSSD_MSK
-
-#define STM32_RCC_BDCR_RTCSEL_POS 8U
-#define STM32_RCC_BDCR_RTCSEL_MSK (0x3UL << STM32_RCC_BDCR_RTCSEL_POS)
-#define STM32_RCC_BDCR_RTCSEL STM32_RCC_BDCR_RTCSEL_MSK
-#define STM32_RCC_BDCR_RTCSEL_0 (0x1UL << STM32_RCC_BDCR_RTCSEL_POS)
-#define STM32_RCC_BDCR_RTCSEL_1 (0x2UL << STM32_RCC_BDCR_RTCSEL_POS)
-
-#define STM32_RCC_BDCR_LSCOEN_POS 24U
-#define STM32_RCC_BDCR_LSCOEN_MSK (0x1UL << STM32_RCC_BDCR_LSCOEN_POS)
-#define STM32_RCC_BDCR_LSCOEN STM32_RCC_BDCR_LSCOEN_MSK
-#define STM32_RCC_BDCR_LSCOSEL_POS 25U
-#define STM32_RCC_BDCR_LSCOSEL_MSK (0x1UL << STM32_RCC_BDCR_LSCOSEL_POS)
-#define STM32_RCC_BDCR_LSCOSEL STM32_RCC_BDCR_LSCOSEL_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CSR REGISTER  *******************/
-#define STM32_RCC_CSR_LSION_POS 0U
-#define STM32_RCC_CSR_LSION_MSK (0x1UL << STM32_RCC_CSR_LSION_POS)
-#define STM32_RCC_CSR_LSION STM32_RCC_CSR_LSION_MSK
-#define STM32_RCC_CSR_LSIRDY_POS 1U
-#define STM32_RCC_CSR_LSIRDY_MSK (0x1UL << STM32_RCC_CSR_LSIRDY_POS)
-#define STM32_RCC_CSR_LSIRDY STM32_RCC_CSR_LSIRDY_MSK
-
-#define STM32_RCC_CSR_MSISRANGE_POS 8U
-#define STM32_RCC_CSR_MSISRANGE_MSK (0xFUL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE STM32_RCC_CSR_MSISRANGE_MSK
-#define STM32_RCC_CSR_MSISRANGE_1 (0x4UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_2 (0x5UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_4 (0x6UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_8 (0x7UL << STM32_RCC_CSR_MSISRANGE_POS)
-
-#define STM32_RCC_CSR_RMVF_POS 23U
-#define STM32_RCC_CSR_RMVF_MSK (0x1UL << STM32_RCC_CSR_RMVF_POS)
-#define STM32_RCC_CSR_RMVF STM32_RCC_CSR_RMVF_MSK
-#define STM32_RCC_CSR_FWRSTF_POS 24U
-#define STM32_RCC_CSR_FWRSTF_MSK (0x1UL << STM32_RCC_CSR_FWRSTF_POS)
-#define STM32_RCC_CSR_FWRSTF STM32_RCC_CSR_FWRSTF_MSK
-#define STM32_RCC_CSR_OBLRSTF_POS 25U
-#define STM32_RCC_CSR_OBLRSTF_MSK (0x1UL << STM32_RCC_CSR_OBLRSTF_POS)
-#define STM32_RCC_CSR_OBLRSTF STM32_RCC_CSR_OBLRSTF_MSK
-#define STM32_RCC_CSR_PINRSTF_POS 26U
-#define STM32_RCC_CSR_PINRSTF_MSK (0x1UL << STM32_RCC_CSR_PINRSTF_POS)
-#define STM32_RCC_CSR_PINRSTF STM32_RCC_CSR_PINRSTF_MSK
-#define STM32_RCC_CSR_BORRSTF_POS 27U
-#define STM32_RCC_CSR_BORRSTF_MSK (0x1UL << STM32_RCC_CSR_BORRSTF_POS)
-#define STM32_RCC_CSR_BORRSTF STM32_RCC_CSR_BORRSTF_MSK
-#define STM32_RCC_CSR_SFTRSTF_POS 28U
-#define STM32_RCC_CSR_SFTRSTF_MSK (0x1UL << STM32_RCC_CSR_SFTRSTF_POS)
-#define STM32_RCC_CSR_SFTRSTF STM32_RCC_CSR_SFTRSTF_MSK
-#define STM32_RCC_CSR_IWDGRSTF_POS 29U
-#define STM32_RCC_CSR_IWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_IWDGRSTF_POS)
-#define STM32_RCC_CSR_IWDGRSTF STM32_RCC_CSR_IWDGRSTF_MSK
-#define STM32_RCC_CSR_WWDGRSTF_POS 30U
-#define STM32_RCC_CSR_WWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_WWDGRSTF_POS)
-#define STM32_RCC_CSR_WWDGRSTF STM32_RCC_CSR_WWDGRSTF_MSK
-#define STM32_RCC_CSR_LPWRRSTF_POS 31U
-#define STM32_RCC_CSR_LPWRRSTF_MSK (0x1UL << STM32_RCC_CSR_LPWRRSTF_POS)
-#define STM32_RCC_CSR_LPWRRSTF STM32_RCC_CSR_LPWRRSTF_MSK
-
-/**************  Bit definition for STM32_RCC_CRRCR register  *****************/
-#define STM32_RCC_CRRCR_HSI48ON_POS 0U
-#define STM32_RCC_CRRCR_HSI48ON_MSK (0x1UL << STM32_RCC_CRRCR_HSI48ON_POS)
-#define STM32_RCC_CRRCR_HSI48ON STM32_RCC_CRRCR_HSI48ON_MSK
-#define STM32_RCC_CRRCR_HSI48RDY_POS 1U
-#define STM32_RCC_CRRCR_HSI48RDY_MSK (0x1UL << STM32_RCC_CRRCR_HSI48RDY_POS)
-#define STM32_RCC_CRRCR_HSI48RDY STM32_RCC_CRRCR_HSI48RDY_MSK
-
-/*!< HSI48CAL configuration */
-#define STM32_RCC_CRRCR_HSI48CAL_POS 7U
-#define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL STM32_RCC_CRRCR_HSI48CAL_MSK
-#define STM32_RCC_CRRCR_HSI48CAL_0 (0x001UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_1 (0x002UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_2 (0x004UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_3 (0x008UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_4 (0x010UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_5 (0x020UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_6 (0x040UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_7 (0x080UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-
-#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_I2CFMP(n) BIT(n + 21)
-
-/* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_PWREN			BIT(28)
-
-#define STM32_RCC_PB2_SYSCFGEN		BIT(0)
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-#define STM32_RCC_HB1_DMA1		BIT(0)
-#define STM32_RCC_HB1_DMA2		BIT(1)
-
-#define STM32_RCC_HB2_GPIOA		BIT(0)
-#define STM32_RCC_HB2_GPIOB		BIT(1)
-#define STM32_RCC_HB2_GPIOC		BIT(2)
-#define STM32_RCC_HB2_GPIOD		BIT(3)
-#define STM32_RCC_HB2_GPIOE		BIT(4)
-#define STM32_RCC_HB2_GPIOH		BIT(7)
-#define STM32_RCC_HB2_ADC1		BIT(13)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define  STM32_RCC_RESET_CAUSE	STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xff000000
-#define  RESET_CAUSE_RMVF               BIT(23)
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE			STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR		STM32_PWR_SCR
-#define  RESET_CAUSE_SBF                BIT(8)
-#define  RESET_CAUSE_SBF_CLR            BIT(8)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_WUTE           BIT(10)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_CR_WUTIE          BIT(14)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_WUTWF         BIT(2)
-#define STM32_RTC_ISR_INITS         BIT(4)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_ISR_WUTF          BIT(9)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_RTC_CLEAR_FLAG(x)                         \
-			(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
-					(STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
-
-#define RTC_TR_PM_POS                  22U
-#define RTC_TR_PM_MSK                  (0x1UL << RTC_TR_PM_POS)
-#define RTC_TR_PM                      RTC_TR_PM_MSK
-#define RTC_TR_HT_POS                  20U
-#define RTC_TR_HT_MSK                  (0x3UL << RTC_TR_HT_POS)
-#define RTC_TR_HT                      RTC_TR_HT_MSK
-#define RTC_TR_HU_POS                  16U
-#define RTC_TR_HU_MSK                  (0xFUL << RTC_TR_HU_POS)
-#define RTC_TR_HU                      RTC_TR_HU_MSK
-#define RTC_TR_MNT_POS                 12U
-#define RTC_TR_MNT_MSK                 (0x7UL << RTC_TR_MNT_POS)
-#define RTC_TR_MNT                     RTC_TR_MNT_MSK
-#define RTC_TR_MNU_POS                 8U
-#define RTC_TR_MNU_MSK                 (0xFUL << RTC_TR_MNU_POS)
-#define RTC_TR_MNU                     RTC_TR_MNU_MSK
-#define RTC_TR_ST_POS                  4U
-#define RTC_TR_ST_MSK                  (0x7UL << RTC_TR_ST_POS)
-#define RTC_TR_ST                      RTC_TR_ST_MSK
-#define RTC_TR_SU_POS                  0U
-#define RTC_TR_SU_MSK                  (0xFUL << RTC_TR_SU_POS)
-#define RTC_TR_SU                      RTC_TR_SU_MSK
-
-
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned int sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned int crcpr;
-	unsigned int rxcrcr;
-	unsigned int txcrcr;
-	unsigned int i2scfgr;	/* STM32L only */
-	unsigned int i2spr;	/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_ERR_MASK          (0xc3fa)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0xff) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0xff)
-#define STM32_FLASH_ECCR            REG32(STM32_FLASH_REGS_BASE + 0x18)
-#define STM32_FLASH_OPTR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-#define STM32_FLASH_PCROP1SR        REG32(STM32_FLASH_REGS_BASE + 0x24)
-#define STM32_FLASH_PCROP1ER        REG32(STM32_FLASH_REGS_BASE + 0x28)
-#define STM32_FLASH_WRP1AR          REG32(STM32_FLASH_REGS_BASE + 0x2C)
-#define STM32_FLASH_WRP1BR          REG32(STM32_FLASH_REGS_BASE + 0x30)
-/* Minimum number of bytes that can be written to flash */
-#define STM32_FLASH_MIN_WRITE_SIZE  CONFIG_FLASH_WRITE_SIZE
-
-#define STM32_OPTB_USER_RDP         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_WRP1AR           REG32(STM32_OPTB_BASE + 0x18)
-#define STM32_OPTB_WRP1BR           REG32(STM32_OPTB_BASE + 0x20)
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT          BIT(18)
-
-/* --- ADC --- */
-#define STM32_ADC1_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC1_ISR_ADRDY        BIT(0)
-#define STM32_ADC1_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC1_IER_AWDIE        BIT(7)
-#define STM32_ADC1_IER_OVRIE        BIT(4)
-#define STM32_ADC1_IER_EOSEQIE      BIT(3)
-#define STM32_ADC1_IER_EOCIE        BIT(2)
-#define STM32_ADC1_IER_EOSMPIE      BIT(1)
-#define STM32_ADC1_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC1_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC1_CR_ADEN          BIT(0)
-#define STM32_ADC1_CR_ADDIS         BIT(1)
-#define STM32_ADC1_CR_ADSTP         BIT(4)
-#define STM32_ADC1_CR_ADVREGEN      BIT(28)
-#define STM32_ADC1_CR_DEEPPWD	    BIT(29)
-#define STM32_ADC1_CR_ADCAL         BIT(31)
-#define STM32_ADC1_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
-/* Analog watchdog channel selection */
-#define STM32_ADC1_CFGR_AWDCH_MASK  (0x1f << 26)
-#define STM32_ADC1_CFGR_AWDEN       BIT(23)
-#define STM32_ADC1_CFGR_AWDSGL      BIT(22)
-#define STM32_ADC1_CFGR_AUTDLY	    BIT(14)
-/* Selects single vs continuous */
-#define STM32_ADC1_CFGR_CONT        BIT(13)
-/* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC1_CFGR_OVRMOD      BIT(12)
-/* External trigger polarity selection */
-#define STM32_ADC1_CFGR_EXTEN_DIS   (0 << 10)
-#define STM32_ADC1_CFGR_EXTEN_RISE  (1 << 10)
-#define STM32_ADC1_CFGR_EXTEN_FALL  (2 << 10)
-#define STM32_ADC1_CFGR_EXTEN_BOTH  (3 << 10)
-#define STM32_ADC1_CFGR_EXTEN_MASK  (3 << 10)
-#define STM32_ADC1_CFGR_ALIGN	    BIT(5)
-/* External trigger selection */
-#define STM32_ADC1_CFGR_TRG0        (0 << 6)
-#define STM32_ADC1_CFGR_TRG1        (1 << 6)
-#define STM32_ADC1_CFGR_TRG2        (2 << 6)
-#define STM32_ADC1_CFGR_TRG3        (3 << 6)
-#define STM32_ADC1_CFGR_TRG4        (4 << 6)
-#define STM32_ADC1_CFGR_TRG5        (5 << 6)
-#define STM32_ADC1_CFGR_TRG6        (6 << 6)
-#define STM32_ADC1_CFGR_TRG7        (7 << 6)
-#define STM32_ADC1_CFGR_TRG_MASK    (7 << 6)
-/* Selects circular vs one-shot */
-#define STM32_ADC1_CFGR_DMACFG      BIT(1)
-#define STM32_ADC1_CFGR_DMAEN       BIT(0)
-#define STM32_ADC1_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC1_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC1_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
-/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC1_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC1_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC1_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC1_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC1_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC1_JDR1             REG32(STM32_ADC1_BASE + 0x80)
-#define STM32_ADC1_JDR2             REG32(STM32_ADC1_BASE + 0x84)
-#define STM32_ADC1_JDR3             REG32(STM32_ADC1_BASE + 0x88)
-#define STM32_ADC1_JDR4             REG32(STM32_ADC1_BASE + 0x8C)
-#define STM32_ADC1_CCR              REG32(STM32_ADC1_BASE + 0x308)
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-	STM32_DMAC_CH15 = 14,
-
-	/* Channel functions */
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH14,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH15,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
-	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
-	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
-	STM32_DMAC_COUNT = 15,
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-#endif /* !__ASSEMBLER__ */
-
diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h
deleted file mode 100644
index d418362fce..0000000000
--- a/chip/stm32/registers-stm32l5.h
+++ /dev/null
@@ -1,2388 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32L5 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32L552
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/******  STM32 specific Interrupt Numbers ********/
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_RTC_ALARM        2
-#define STM32_IRQ_FLASH            6
-#define STM32_IRQ_FLASH_S          7
-#define STM32_IRQ_RCC              9
-#define STM32_IRQ_RCC_S           10
-#define STM32_IRQ_EXTI0           11
-#define STM32_IRQ_EXTI1           12
-#define STM32_IRQ_EXTI2           13
-#define STM32_IRQ_EXTI3           14
-#define STM32_IRQ_EXTI4           15
-#define STM32_IRQ_EXTI5           16
-#define STM32_IRQ_EXTI6           17
-#define STM32_IRQ_EXTI7           18
-#define STM32_IRQ_EXTI8           19
-#define STM32_IRQ_EXTI9           20
-#define STM32_IRQ_EXTI10          21
-#define STM32_IRQ_EXTI11          22
-#define STM32_IRQ_EXTI12          23
-#define STM32_IRQ_EXTI13          24
-#define STM32_IRQ_EXTI14          25
-#define STM32_IRQ_EXTI15          26
-#define STM32_IRQ_DMAMUX_OVR      27
-#define STM32_IRQ_DMAMUX_OVR_S    28
-#define STM32_IRQ_DMA_CHANNEL_1   29
-#define STM32_IRQ_DMA_CHANNEL_2   30
-#define STM32_IRQ_DMA_CHANNEL_3   31
-#define STM32_IRQ_DMA_CHANNEL_4   32
-#define STM32_IRQ_DMA_CHANNEL_5   33
-#define STM32_IRQ_DMA_CHANNEL_6   34
-#define STM32_IRQ_DMA_CHANNEL_7   35
-#define STM32_IRQ_DMA_CHANNEL_8   36
-#define STM32_IRQ_ADC1            37
-#define STM32_IRQ_TIM1_BRK        41
-#define STM32_IRQ_TIM1_UP         42
-#define STM32_IRQ_TIM1_TRG_COM    43
-#define STM32_IRQ_TIM1_CC         44
-#define STM32_IRQ_TIM2            45
-#define STM32_IRQ_TIM3            46
-#define STM32_IRQ_TIM4            47
-#define STM32_IRQ_TIM5            48
-#define STM32_IRQ_TIM6            49
-#define STM32_IRQ_TIM7            50
-#define STM32_IRQ_TIM8_BRK        51
-#define STM32_IRQ_TIM8_UP         52
-#define STM32_IRQ_TIM8_TRG_COM    53
-#define STM32_IRQ_TIM8_CC         54
-#define STM32_IRQ_I2C1_EV         55
-#define STM32_IRQ_I2C1_ER         56
-#define STM32_IRQ_I2C2_EV         57
-#define STM32_IRQ_I2C2_ER         58
-#define STM32_IRQ_SPI1            59
-#define STM32_IRQ_SPI2            60
-#define STM32_IRQ_USART1          61
-#define STM32_IRQ_USART2          62
-#define STM32_IRQ_USART3          63
-#define STM32_IRQ_USART4          64
-#define STM32_IRQ_USART5          65
-#define STM32_IRQ_LPUART          66
-#define STM32_IRQ_LPTIM1          67
-#define STM32_IRQ_LPTIM2          68
-#define STM32_IRQ_TIM15           69
-#define STM32_IRQ_TIM16           70
-#define STM32_IRQ_TIM17           71
-#define STM32_IRQ_COMP            72
-#define STM32_IRQ_USB_FS          73
-#define STM32_IRQ_CRS             74
-#define STM32_IRQ_FMC             75
-#define STM32_IRQ_DMA2_CHANNEL1   80
-#define STM32_IRQ_DMA2_CHANNEL2   81
-#define STM32_IRQ_DMA2_CHANNEL3   82
-#define STM32_IRQ_DMA2_CHANNEL4   83
-#define STM32_IRQ_DMA2_CHANNEL5   84
-#define STM32_IRQ_DMA2_CHANNEL6   85
-#define STM32_IRQ_DMA2_CHANNEL7   86
-#define STM32_IRQ_DMA2_CHANNEL8   87
-
-/* To simplify code generation, define DMA channel 9..16 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_11   STM32_IRQ_DMA2_CHANNEL3
-#define STM32_IRQ_DMA_CHANNEL_12   STM32_IRQ_DMA2_CHANNEL4
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL5
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_15   STM32_IRQ_DMA2_CHANNEL7
-#define STM32_IRQ_DMA_CHANNEL_16   STM32_IRQ_DMA2_CHANNEL8
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-#define STM32_IRQ_USB_LP STM32_IRQ_USB_FS
-
-
-#define PERIPH_BASE           0x40000000UL
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x02000000UL)
-
-/*!< APB1 peripherals */
-#define STM32_TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
-#define STM32_TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
-#define STM32_TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
-#define STM32_TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
-#define STM32_TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
-#define STM32_TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
-#define STM32_RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
-#define STM32_WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
-#define STM32_IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
-#define STM32_SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
-#define STM32_SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
-#define STM32_USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
-#define STM32_USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
-#define STM32_USART4_BASE           (APB1PERIPH_BASE + 0x4c00UL)
-#define STM32_USART5_BASE           (APB1PERIPH_BASE + 0x5000UL)
-#define STM32_I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
-#define STM32_I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
-#define STM32_I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
-#define STM32_PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
-#define STM32_DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_DAC1_BASE             (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_USB_FS_BASE           (APB1PERIPH_BASE + 0xD400UL)
-#define STM32_USB_CAN_SRAM_BASE     (APB1PERIPH_BASE + 0xD800UL)
-
-/*!< APB2 peripherals */
-#define STM32_SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
-#define STM32_EXTI_BASE             (AHB1PERIPH_BASE + 0xf400UL)
-#define STM32_TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
-#define STM32_SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
-#define STM32_TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)
-#define STM32_USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
-#define STM32_TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
-#define STM32_TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
-#define STM32_TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)
-
-/*!< AHB1 peripherals */
-#define STM32_DMA1_BASE             (AHB1PERIPH_BASE + 0x0000UL)
-#define STM32_DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
-#define STM32_RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
-#define STM32_FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
-#define STM32_CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
-#define STM32_DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
-#define STM32_DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
-#define STM32_DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
-#define STM32_DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
-#define STM32_DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
-#define STM32_DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
-#define STM32_DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
-#define STM32_DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)
-#define STM32_DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
-#define STM32_DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
-#define STM32_DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
-#define STM32_DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
-#define STM32_DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
-#define STM32_DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
-#define STM32_DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
-#define STM32_DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)
-
-/*!< AHB2 peripherals */
-#define STM32_GPIOA_BASE            (AHB2PERIPH_BASE + 0x20000UL)
-#define STM32_GPIOB_BASE            (AHB2PERIPH_BASE + 0x20400UL)
-#define STM32_GPIOC_BASE            (AHB2PERIPH_BASE + 0x20800UL)
-#define STM32_GPIOD_BASE            (AHB2PERIPH_BASE + 0x20C00UL)
-#define STM32_GPIOE_BASE            (AHB2PERIPH_BASE + 0x21000UL)
-#define STM32_GPIOF_BASE            (AHB2PERIPH_BASE + 0x21400UL)
-#define STM32_GPIOG_BASE            (AHB2PERIPH_BASE + 0x21800UL)
-#define STM32_GPIOH_BASE            (AHB2PERIPH_BASE + 0x21C00UL)
-#define STM32_RNG_BASE              (AHB2PERIPH_BASE + 0xC4000UL)
-
-/* Debug MCU registers base address */
-#define STM32_PACKAGE_BASE          0x0BFA0500UL
-#define STM32_UID_BASE              0x0BFA0590UL
-#define STM32_FLASHSIZE_BASE        0x0BFA05E0UL
-
-#define STM32_FLASH_REGS_BASE       STM32_FLASH_R_BASE
-#define STM32_UNIQUE_ID_BASE        STM32_UID_BASE
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE          BIT(0)
-#define STM32_USART_CR1_UESM        BIT(1)
-#define STM32_USART_CR1_RE          BIT(2)
-#define STM32_USART_CR1_TE          BIT(3)
-#define STM32_USART_CR1_RXNEIE      BIT(5)
-#define STM32_USART_CR1_TCIE        BIT(6)
-#define STM32_USART_CR1_TXEIE       BIT(7)
-#define STM32_USART_CR1_PS          BIT(9)
-#define STM32_USART_CR1_PCE         BIT(10)
-#define STM32_USART_CR1_M           BIT(12)
-#define STM32_USART_CR1_OVER8       BIT(15)
-
-#define STM32_USART_CR2(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP        BIT(15)
-
-#define STM32_USART_CR3(base)       STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE         BIT(0)
-#define STM32_USART_CR3_DMAR        BIT(6)
-#define STM32_USART_CR3_DMAT        BIT(7)
-#define STM32_USART_CR3_ONEBIT      BIT(11)
-#define STM32_USART_CR3_OVRDIS      BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define STM32_USART_CR3_WUFIE       BIT(22)
-
-#define STM32_USART_BRR(base)       STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)       STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)       STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF       BIT(3)
-#define STM32_USART_ICR_TCCF        BIT(6)
-#define STM32_USART_RDR(base)       STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)       STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)     STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)        STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE          BIT(3)
-#define STM32_USART_SR_RXNE         BIT(5)
-#define STM32_USART_SR_TC           BIT(6)
-#define STM32_USART_SR_TXE          BIT(7)
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4x6 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR1               REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SCR               REG32(STM32_PWR_BASE + 0x18)
-
-#define PWR_CR1_LPMS_POS             0U
-#define PWR_CR1_LPMS_MSK             (0x7UL << PWR_CR1_LPMS_POS)
-#define PWR_CR1_LPMS                 PWR_CR1_LPMS_MSK
-#define PWR_CR1_LPMS_STOP0           (0x00000000UL)
-#define PWR_CR1_LPMS_STOP1_POS       0U
-#define PWR_CR1_LPMS_STOP1_MSK       (0x1UL << PWR_CR1_LPMS_STOP1_POS)
-#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_MSK
-#define PWR_CR1_LPMS_STOP2_POS       1U
-#define PWR_CR1_LPMS_STOP2_MSK       (0x1UL << PWR_CR1_LPMS_STOP2_POS)
-#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_MSK
-#define PWR_CR1_LPMS_STANDBY_POS     0U
-#define PWR_CR1_LPMS_STANDBY_MSK     (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
-#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_MSK
-#define PWR_CR1_LPMS_SHUTDOWN_POS    2U
-#define PWR_CR1_LPMS_SHUTDOWN_MSK    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
-#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_MSK
-#define PWR_CR1_VOS_POS              9U
-#define PWR_CR1_VOS_MSK              (0x3UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS                  PWR_CR1_VOS_MSK
-#define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_POS)
-
-
-/* --- Macro usage in ec code --- */
-#define STM32_RCC_AHB2ENR_GPIOMASK                               \
-	(STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \
-	 STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \
-	 STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOHEN)
-#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
-#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
-#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_SYSCFGEN            STM32_RCC_APB2ENR_SYSCFGEN
-
-#define STM32_RCC_PB2_TIM1            STM32_RCC_APB2ENR_TIM1EN
-#define STM32_RCC_PB2_TIM15           STM32_RCC_APB2ENR_TIM15EN
-#define STM32_RCC_PB2_TIM16           STM32_RCC_APB2ENR_TIM16EN
-#ifndef CHIP_VARIANT_STM32L431X
-#define STM32_RCC_PB2_TIM8            BIT(13)
-#endif
-#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
-
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTH	BIT(7)
-#define STM32_RCC_CCIPR_USART1SEL_SHIFT (0)
-#define STM32_RCC_CCIPR_USART1SEL_MASK  (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
-#define STM32_RCC_CCIPR_USART2SEL_SHIFT (2)
-#define STM32_RCC_CCIPR_USART2SEL_MASK  (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
-#define STM32_RCC_CCIPR_USART3SEL_SHIFT (4)
-#define STM32_RCC_CCIPR_USART3SEL_MASK  (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
-#define STM32_RCC_CCIPR_UART4SEL_SHIFT (6)
-#define STM32_RCC_CCIPR_UART4SEL_MASK  (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
-#define STM32_RCC_CCIPR_UART5SEL_SHIFT (8)
-#define STM32_RCC_CCIPR_UART5SEL_MASK  (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10)
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12)
-#define STM32_RCC_CCIPR_I2C1SEL_MASK  (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14)
-#define STM32_RCC_CCIPR_I2C2SEL_MASK  (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16)
-#define STM32_RCC_CCIPR_I2C3SEL_MASK  (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18)
-#define STM32_RCC_CCIPR_LPTIM1SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20)
-#define STM32_RCC_CCIPR_LPTIM2SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
-#define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22)
-#define STM32_RCC_CCIPR_SAI1SEL_MASK  (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
-#define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24)
-#define STM32_RCC_CCIPR_SAI2SEL_MASK  (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
-#define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26)
-#define STM32_RCC_CCIPR_CLK48SEL_MASK  (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
-#define STM32_RCC_CCIPR_ADCSEL_SHIFT (28)
-#define STM32_RCC_CCIPR_ADCSEL_MASK  (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
-#define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30)
-#define STM32_RCC_CCIPR_SWPMI1SEL_MASK  BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
-#define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31)
-#define STM32_RCC_CCIPR_DFSDM1SEL_MASK  BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
-/* Possible clock sources for each peripheral */
-#define STM32_RCC_CCIPR_UART_PCLK	0
-#define STM32_RCC_CCIPR_UART_SYSCLK	1
-#define STM32_RCC_CCIPR_UART_HSI16	2
-#define STM32_RCC_CCIPR_UART_LSE	3
-
-#define STM32_RCC_CCIPR_I2C_PCLK	0
-#define STM32_RCC_CCIPR_I2C_SYSCLK	1
-#define STM32_RCC_CCIPR_I2C_HSI16	2
-
-#define STM32_RCC_CCIPR_LPTIM_PCLK	0
-#define STM32_RCC_CCIPR_LPTIM_LSI	1
-#define STM32_RCC_CCIPR_LPTIM_HSI16	2
-#define STM32_RCC_CCIPR_LPTIM_LSE	3
-
-#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK	0
-#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK	1
-#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK	2
-#define STM32_RCC_CCIPR_SAI_EXTCLK		3
-
-#define STM32_RCC_CCIPR_CLK48_NONE			0
-#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK	1
-#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK	2
-#define STM32_RCC_CCIPR_CLK48_MSI			3
-
-#define STM32_RCC_CCIPR_ADC_NONE		0
-#define STM32_RCC_CCIPR_ADC_PLLADC1CLK	1
-#define STM32_RCC_CCIPR_ADC_PLLADC2CLK	2
-#define STM32_RCC_CCIPR_ADC_SYSCLK	3
-
-#define STM32_RCC_CCIPR_SWPMI_PCLK	0
-#define STM32_RCC_CCIPR_SWPMI_HSI16	1
-
-#define STM32_RCC_CCIPR_DFSDM_PCLK		0
-#define STM32_RCC_CCIPR_DFSDM_SYSCLK	1
-
-
-
-#define STM32_RCC_CR          REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR       REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR        REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR     REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_RESERVED    REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_CIER        REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR        REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR        REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_RESERVED0   REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_AHB1RSTR    REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR    REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR    REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_RESERVED1   REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_APB1RSTR1   REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2   REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR    REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_RESERVED2   REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_AHB1ENR     REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR     REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR     REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_RESERVED3   REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_APB1ENR1    REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2    REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR     REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_RESERVED4   REG32(STM32_RCC_BASE + 0x64)
-#define STM32_RCC_AHB1SMENR   REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR   REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR   REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_RESERVED5   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_APB1SMENR1  REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2  REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR   REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_RESERVED6   REG32(STM32_RCC_BASE + 0x84)
-#define STM32_RCC_CCIPR       REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_RESERVED7   REG32(STM32_RCC_BASE + 0x8C)
-#define STM32_RCC_BDCR        REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR         REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR       REG32(STM32_RCC_BASE + 0x98)
-
-#define STM32_RCC_PLLSAI1_SUPPORT
-#define STM32_RCC_PLLP_SUPPORT
-#define STM32_RCC_HSI48_SUPPORT
-#define STM32_RCC_PLLP_DIV_2_31_SUPPORT
-#define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT
-
-#define STM32_RCC_APB1ENR                STM32_RCC_APB1ENR1
-
-/********************  BIT DEFINITION FOR STM32_RCC_CR REGISTER  **************/
-#define STM32_RCC_CR_MSION_POS           0U
-#define STM32_RCC_CR_MSION_MSK           (0x1UL << STM32_RCC_CR_MSION_POS)
-#define STM32_RCC_CR_MSION               STM32_RCC_CR_MSION_MSK
-#define STM32_RCC_CR_MSIRDY_POS          1U
-#define STM32_RCC_CR_MSIRDY_MSK          (0x1UL << STM32_RCC_CR_MSIRDY_POS)
-#define STM32_RCC_CR_MSIRDY              STM32_RCC_CR_MSIRDY_MSK
-#define STM32_RCC_CR_MSIPLLEN_POS        2U
-#define STM32_RCC_CR_MSIPLLEN_MSK        (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
-#define STM32_RCC_CR_MSIPLLEN            STM32_RCC_CR_MSIPLLEN_MSK
-#define STM32_RCC_CR_MSIRGSEL_POS        3U
-#define STM32_RCC_CR_MSIRGSEL_MSK        (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
-#define STM32_RCC_CR_MSIRGSEL            STM32_RCC_CR_MSIRGSEL_MSK
-
-/*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */
-#define STM32_RCC_CR_MSIRANGE_POS        4U
-#define STM32_RCC_CR_MSIRANGE_MSK        (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE            STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_CR_MSIRANGE_0          (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_1          (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_2          (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_3          (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_4          (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_5          (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_6          (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_7          (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_8          (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_9          (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_10         (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_11         (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
-
-#define STM32_RCC_CR_HSION_POS           8U
-#define STM32_RCC_CR_HSION_MSK           (0x1UL << STM32_RCC_CR_HSION_POS)
-#define STM32_RCC_CR_HSION               STM32_RCC_CR_HSION_MSK
-#define STM32_RCC_CR_HSIKERON_POS        9U
-#define STM32_RCC_CR_HSIKERON_MSK        (0x1UL << STM32_RCC_CR_HSIKERON_POS)
-#define STM32_RCC_CR_HSIKERON            STM32_RCC_CR_HSIKERON_MSK
-#define STM32_RCC_CR_HSIRDY_POS          10U
-#define STM32_RCC_CR_HSIRDY_MSK          (0x1UL << STM32_RCC_CR_HSIRDY_POS)
-#define STM32_RCC_CR_HSIRDY              STM32_RCC_CR_HSIRDY_MSK
-#define STM32_RCC_CR_HSIASFS_POS         11U
-#define STM32_RCC_CR_HSIASFS_MSK         (0x1UL << STM32_RCC_CR_HSIASFS_POS)
-#define STM32_RCC_CR_HSIASFS             STM32_RCC_CR_HSIASFS_MSK
-
-#define STM32_RCC_CR_HSEON_POS           16U
-#define STM32_RCC_CR_HSEON_MSK           (0x1UL << STM32_RCC_CR_HSEON_POS)
-#define STM32_RCC_CR_HSEON               STM32_RCC_CR_HSEON_MSK
-#define STM32_RCC_CR_HSERDY_POS          17U
-#define STM32_RCC_CR_HSERDY_MSK          (0x1UL << STM32_RCC_CR_HSERDY_POS)
-#define STM32_RCC_CR_HSERDY              STM32_RCC_CR_HSERDY_MSK
-#define STM32_RCC_CR_HSEBYP_POS          18U
-#define STM32_RCC_CR_HSEBYP_MSK          (0x1UL << STM32_RCC_CR_HSEBYP_POS)
-#define STM32_RCC_CR_HSEBYP              STM32_RCC_CR_HSEBYP_MSK
-#define STM32_RCC_CR_CSSON_POS           19U
-#define STM32_RCC_CR_CSSON_MSK           (0x1UL << STM32_RCC_CR_CSSON_POS)
-#define STM32_RCC_CR_CSSON               STM32_RCC_CR_CSSON_MSK
-
-#define STM32_RCC_CR_PLLON_POS           24U
-#define STM32_RCC_CR_PLLON_MSK           (0x1UL << STM32_RCC_CR_PLLON_POS)
-#define STM32_RCC_CR_PLLON               STM32_RCC_CR_PLLON_MSK
-#define STM32_RCC_CR_PLLRDY_POS          25U
-#define STM32_RCC_CR_PLLRDY_MSK          (0x1UL << STM32_RCC_CR_PLLRDY_POS)
-#define STM32_RCC_CR_PLLRDY              STM32_RCC_CR_PLLRDY_MSK
-#define STM32_RCC_CR_PLLSAI1ON_POS       26U
-#define STM32_RCC_CR_PLLSAI1ON_MSK       (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
-#define STM32_RCC_CR_PLLSAI1ON           STM32_RCC_CR_PLLSAI1ON_MSK
-#define STM32_RCC_CR_PLLSAI1RDY_POS      27U
-#define STM32_RCC_CR_PLLSAI1RDY_MSK      (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
-#define STM32_RCC_CR_PLLSAI1RDY          STM32_RCC_CR_PLLSAI1RDY_MSK
-
-/********************  BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER  ***********/
-/*!< MSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_MSICAL_POS       0U
-#define STM32_RCC_ICSCR_MSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL           STM32_RCC_ICSCR_MSICAL_MSK
-#define STM32_RCC_ICSCR_MSICAL_0         (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_1         (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_2         (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_3         (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_4         (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_5         (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_6         (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_7         (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
-
-/*!< MSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_MSITRIM_POS      8U
-#define STM32_RCC_ICSCR_MSITRIM_MSK      (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM          STM32_RCC_ICSCR_MSITRIM_MSK
-#define STM32_RCC_ICSCR_MSITRIM_0        (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_1        (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_2        (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_3        (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_4        (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_5        (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_6        (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_7        (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
-
-/*!< HSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_HSICAL_POS       16U
-#define STM32_RCC_ICSCR_HSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL           STM32_RCC_ICSCR_HSICAL_MSK
-#define STM32_RCC_ICSCR_HSICAL_0         (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_1         (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_2         (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_3         (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_4         (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_5         (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_6         (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_7         (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
-
-/*!< HSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_HSITRIM_POS      24U
-#define STM32_RCC_ICSCR_HSITRIM_MSK      (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM          STM32_RCC_ICSCR_HSITRIM_MSK
-#define STM32_RCC_ICSCR_HSITRIM_0        (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_1        (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_2        (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_3        (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_4        (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
-
-/****************  BIT DEFINITION FOR STM32_RCC_CFGR REGISTER  **************/
-/*!< SW CONFIGURATION */
-#define STM32_RCC_CFGR_SW_POS            0U
-#define STM32_RCC_CFGR_SW_MSK            (0x3UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW                STM32_RCC_CFGR_SW_MSK
-#define STM32_RCC_CFGR_SW_0              (0x1UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW_1              (0x2UL << STM32_RCC_CFGR_SW_POS)
-
-#define STM32_RCC_CFGR_SW_MSI            (0x00000000UL)
-#define STM32_RCC_CFGR_SW_HSI            (0x00000001UL)
-#define STM32_RCC_CFGR_SW_HSE            (0x00000002UL)
-#define STM32_RCC_CFGR_SW_PLL            (0x00000003UL)
-
-/*!< SWS CONFIGURATION */
-#define STM32_RCC_CFGR_SWS_POS           2U
-#define STM32_RCC_CFGR_SWS_MSK           (0x3UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS               STM32_RCC_CFGR_SWS_MSK
-#define STM32_RCC_CFGR_SWS_0             (0x1UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS_1             (0x2UL << STM32_RCC_CFGR_SWS_POS)
-
-#define STM32_RCC_CFGR_SWS_MSI           (0x00000000UL)
-#define STM32_RCC_CFGR_SWS_HSI           (0x00000004UL)
-#define STM32_RCC_CFGR_SWS_HSE           (0x00000008UL)
-#define STM32_RCC_CFGR_SWS_PLL           (0x0000000CUL)
-
-/*!< HPRE CONFIGURATION */
-#define STM32_RCC_CFGR_HPRE_POS          4U
-#define STM32_RCC_CFGR_HPRE_MSK          (0xFUL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE              STM32_RCC_CFGR_HPRE_MSK
-#define STM32_RCC_CFGR_HPRE_0            (0x1UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_1            (0x2UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_2            (0x4UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_3            (0x8UL << STM32_RCC_CFGR_HPRE_POS)
-
-#define STM32_RCC_CFGR_HPRE_DIV1         (0x00000000UL)
-#define STM32_RCC_CFGR_HPRE_DIV2         (0x00000080UL)
-#define STM32_RCC_CFGR_HPRE_DIV4         (0x00000090UL)
-#define STM32_RCC_CFGR_HPRE_DIV8         (0x000000A0UL)
-#define STM32_RCC_CFGR_HPRE_DIV16        (0x000000B0UL)
-#define STM32_RCC_CFGR_HPRE_DIV64        (0x000000C0UL)
-#define STM32_RCC_CFGR_HPRE_DIV128       (0x000000D0UL)
-#define STM32_RCC_CFGR_HPRE_DIV256       (0x000000E0UL)
-#define STM32_RCC_CFGR_HPRE_DIV512       (0x000000F0UL)
-
-/*!< PPRE1 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE1_POS         8U
-#define STM32_RCC_CFGR_PPRE1_MSK         (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1             STM32_RCC_CFGR_PPRE1_MSK
-#define STM32_RCC_CFGR_PPRE1_0           (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_1           (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_2           (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
-
-#define STM32_RCC_CFGR_PPRE1_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE1_DIV2        (0x00000400UL)
-#define STM32_RCC_CFGR_PPRE1_DIV4        (0x00000500UL)
-#define STM32_RCC_CFGR_PPRE1_DIV8        (0x00000600UL)
-#define STM32_RCC_CFGR_PPRE1_DIV16       (0x00000700UL)
-
-/*!< PPRE2 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE2_POS         11U
-#define STM32_RCC_CFGR_PPRE2_MSK         (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2             STM32_RCC_CFGR_PPRE2_MSK
-#define STM32_RCC_CFGR_PPRE2_0           (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_1           (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_2           (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
-
-#define STM32_RCC_CFGR_PPRE2_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV2        (0x00002000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV4        (0x00002800UL)
-#define STM32_RCC_CFGR_PPRE2_DIV8        (0x00003000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV16       (0x00003800UL)
-
-#define STM32_RCC_CFGR_STOPWUCK_POS      15U
-#define STM32_RCC_CFGR_STOPWUCK_MSK      (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
-#define STM32_RCC_CFGR_STOPWUCK          STM32_RCC_CFGR_STOPWUCK_MSK
-
-/*!< MCOSEL CONFIGURATION */
-#define STM32_RCC_CFGR_MCOSEL_POS        24U
-#define STM32_RCC_CFGR_MCOSEL_MSK        (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL            STM32_RCC_CFGR_MCOSEL_MSK
-#define STM32_RCC_CFGR_MCOSEL_0          (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_1          (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_2          (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_3          (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_POS        28U
-#define STM32_RCC_CFGR_MCOPRE_MSK        (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE            STM32_RCC_CFGR_MCOPRE_MSK
-#define STM32_RCC_CFGR_MCOPRE_0          (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_1          (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_2          (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_DIV1       (0x00000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV2       (0x10000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV4       (0x20000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV8       (0x30000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV16      (0x40000000UL)
-
-/* LEGACY ALIASES */
-#define STM32_RCC_CFGR_MCO_PRE           STM32_RCC_CFGR_MCOPRE
-#define STM32_RCC_CFGR_MCO_PRE_1         STM32_RCC_CFGR_MCOPRE_DIV1
-#define STM32_RCC_CFGR_MCO_PRE_2         STM32_RCC_CFGR_MCOPRE_DIV2
-#define STM32_RCC_CFGR_MCO_PRE_4         STM32_RCC_CFGR_MCOPRE_DIV4
-#define STM32_RCC_CFGR_MCO_PRE_8         STM32_RCC_CFGR_MCOPRE_DIV8
-#define STM32_RCC_CFGR_MCO_PRE_16        STM32_RCC_CFGR_MCOPRE_DIV16
-
-/****************  BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER  ***********/
-#define STM32_RCC_PLLCFGR_PLLSRC_POS     0U
-#define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK
-
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI_POS 0U
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK \
-	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_MSI_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI_POS 1U
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK \
-	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_HSI_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \
-	(0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE     STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
-
-#define STM32_RCC_PLLCFGR_PLLM_POS       4U
-#define STM32_RCC_PLLCFGR_PLLM_MSK       (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM           STM32_RCC_PLLCFGR_PLLM_MSK
-#define STM32_RCC_PLLCFGR_PLLM_0         (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_1         (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_2         (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
-
-#define STM32_RCC_PLLCFGR_PLLN_POS       8U
-#define STM32_RCC_PLLCFGR_PLLN_MSK       (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN           STM32_RCC_PLLCFGR_PLLN_MSK
-#define STM32_RCC_PLLCFGR_PLLN_0         (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_1         (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_2         (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_3         (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_4         (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_5         (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_6         (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPEN_POS     16U
-#define STM32_RCC_PLLCFGR_PLLPEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
-#define STM32_RCC_PLLCFGR_PLLPEN         STM32_RCC_PLLCFGR_PLLPEN_MSK
-#define STM32_RCC_PLLCFGR_PLLP_POS       17U
-#define STM32_RCC_PLLCFGR_PLLP_MSK       (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
-#define STM32_RCC_PLLCFGR_PLLP           STM32_RCC_PLLCFGR_PLLP_MSK
-#define STM32_RCC_PLLCFGR_PLLQEN_POS     20U
-#define STM32_RCC_PLLCFGR_PLLQEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
-#define STM32_RCC_PLLCFGR_PLLQEN         STM32_RCC_PLLCFGR_PLLQEN_MSK
-
-#define STM32_RCC_PLLCFGR_PLLQ_POS       21U
-#define STM32_RCC_PLLCFGR_PLLQ_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ           STM32_RCC_PLLCFGR_PLLQ_MSK
-#define STM32_RCC_PLLCFGR_PLLQ_0         (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ_1         (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-
-#define STM32_RCC_PLLCFGR_PLLREN_POS     24U
-#define STM32_RCC_PLLCFGR_PLLREN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
-#define STM32_RCC_PLLCFGR_PLLREN         STM32_RCC_PLLCFGR_PLLREN_MSK
-#define STM32_RCC_PLLCFGR_PLLR_POS       25U
-#define STM32_RCC_PLLCFGR_PLLR_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR           STM32_RCC_PLLCFGR_PLLR_MSK
-#define STM32_RCC_PLLCFGR_PLLR_0         (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR_1         (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPDIV_POS  27U
-#define STM32_RCC_PLLCFGR_PLLPDIV_MSK  (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV      STM32_RCC_PLLCFGR_PLLPDIV_MSK
-#define STM32_RCC_PLLCFGR_PLLPDIV_0    (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_1    (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_2    (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_3    (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_4    (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-
-/****************  BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER  ********/
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK \
-	(0x7FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_0 \
-	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_1 \
-	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_2 \
-	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_3 \
-	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_4 \
-	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_5 \
-	(0x20UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \
-	(0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS  16U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS 17U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS 20U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS 21U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK \
-	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_0 \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_1 \
-	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS 24U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS 25U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK \
-	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_0 \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_1 \
-	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS 27U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK \
-	(0x1FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 \
-	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 \
-	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 \
-	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 \
-	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 \
-	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-
-/**************  BIT DEFINITION FOR STM32_RCC_CIER REGISTER  ******************/
-#define STM32_RCC_CIER_LSIRDYIE_POS 0U
-#define STM32_RCC_CIER_LSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_LSIRDYIE_POS)
-#define STM32_RCC_CIER_LSIRDYIE STM32_RCC_CIER_LSIRDYIE_MSK
-#define STM32_RCC_CIER_LSERDYIE_POS 1U
-#define STM32_RCC_CIER_LSERDYIE_MSK (0x1UL << STM32_RCC_CIER_LSERDYIE_POS)
-#define STM32_RCC_CIER_LSERDYIE STM32_RCC_CIER_LSERDYIE_MSK
-#define STM32_RCC_CIER_MSIRDYIE_POS 2U
-#define STM32_RCC_CIER_MSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_MSIRDYIE_POS)
-#define STM32_RCC_CIER_MSIRDYIE STM32_RCC_CIER_MSIRDYIE_MSK
-#define STM32_RCC_CIER_HSIRDYIE_POS 3U
-#define STM32_RCC_CIER_HSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_HSIRDYIE_POS)
-#define STM32_RCC_CIER_HSIRDYIE STM32_RCC_CIER_HSIRDYIE_MSK
-#define STM32_RCC_CIER_HSERDYIE_POS 4U
-#define STM32_RCC_CIER_HSERDYIE_MSK (0x1UL << STM32_RCC_CIER_HSERDYIE_POS)
-#define STM32_RCC_CIER_HSERDYIE STM32_RCC_CIER_HSERDYIE_MSK
-#define STM32_RCC_CIER_PLLRDYIE_POS 5U
-#define STM32_RCC_CIER_PLLRDYIE_MSK (0x1UL << STM32_RCC_CIER_PLLRDYIE_POS)
-#define STM32_RCC_CIER_PLLRDYIE STM32_RCC_CIER_PLLRDYIE_MSK
-#define STM32_RCC_CIER_PLLSAI1RDYIE_POS 6U
-#define STM32_RCC_CIER_PLLSAI1RDYIE_MSK \
-	(0x1UL << STM32_RCC_CIER_PLLSAI1RDYIE_POS)
-#define STM32_RCC_CIER_PLLSAI1RDYIE STM32_RCC_CIER_PLLSAI1RDYIE_MSK
-#define STM32_RCC_CIER_PLLSAI2RDYIE_POS 7U
-#define STM32_RCC_CIER_PLLSAI2RDYIE_MSK \
-	(0x1UL << STM32_RCC_CIER_PLLSAI2RDYIE_POS)
-#define STM32_RCC_CIER_PLLSAI2RDYIE STM32_RCC_CIER_PLLSAI2RDYIE_MSK
-#define STM32_RCC_CIER_HSI48RDYIE_POS 10U
-#define STM32_RCC_CIER_HSI48RDYIE_MSK (0x1UL << STM32_RCC_CIER_HSI48RDYIE_POS)
-#define STM32_RCC_CIER_HSI48RDYIE STM32_RCC_CIER_HSI48RDYIE_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CIFR REGISTER  ******************/
-#define STM32_RCC_CIFR_LSIRDYF_POS 0U
-#define STM32_RCC_CIFR_LSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_LSIRDYF_POS)
-#define STM32_RCC_CIFR_LSIRDYF STM32_RCC_CIFR_LSIRDYF_MSK
-#define STM32_RCC_CIFR_LSERDYF_POS 1U
-#define STM32_RCC_CIFR_LSERDYF_MSK (0x1UL << STM32_RCC_CIFR_LSERDYF_POS)
-#define STM32_RCC_CIFR_LSERDYF STM32_RCC_CIFR_LSERDYF_MSK
-#define STM32_RCC_CIFR_MSIRDYF_POS 2U
-#define STM32_RCC_CIFR_MSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_MSIRDYF_POS)
-#define STM32_RCC_CIFR_MSIRDYF STM32_RCC_CIFR_MSIRDYF_MSK
-#define STM32_RCC_CIFR_HSIRDYF_POS 3U
-#define STM32_RCC_CIFR_HSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_HSIRDYF_POS)
-#define STM32_RCC_CIFR_HSIRDYF STM32_RCC_CIFR_HSIRDYF_MSK
-#define STM32_RCC_CIFR_HSERDYF_POS 4U
-#define STM32_RCC_CIFR_HSERDYF_MSK (0x1UL << STM32_RCC_CIFR_HSERDYF_POS)
-#define STM32_RCC_CIFR_HSERDYF STM32_RCC_CIFR_HSERDYF_MSK
-#define STM32_RCC_CIFR_PLLRDYF_POS 5U
-#define STM32_RCC_CIFR_PLLRDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLRDYF_POS)
-#define STM32_RCC_CIFR_PLLRDYF STM32_RCC_CIFR_PLLRDYF_MSK
-#define STM32_RCC_CIFR_PLLSAI1RDYF_POS 6U
-#define STM32_RCC_CIFR_PLLSAI1RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI1RDYF_POS)
-#define STM32_RCC_CIFR_PLLSAI1RDYF STM32_RCC_CIFR_PLLSAI1RDYF_MSK
-#define STM32_RCC_CIFR_PLLSAI2RDYF_POS 7U
-#define STM32_RCC_CIFR_PLLSAI2RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI2RDYF_POS)
-#define STM32_RCC_CIFR_PLLSAI2RDYF STM32_RCC_CIFR_PLLSAI2RDYF_MSK
-#define STM32_RCC_CIFR_CSSF_POS 8U
-#define STM32_RCC_CIFR_CSSF_MSK (0x1UL << STM32_RCC_CIFR_CSSF_POS)
-#define STM32_RCC_CIFR_CSSF STM32_RCC_CIFR_CSSF_MSK
-#define STM32_RCC_CIFR_HSI48RDYF_POS 10U
-#define STM32_RCC_CIFR_HSI48RDYF_MSK (0x1UL << STM32_RCC_CIFR_HSI48RDYF_POS)
-#define STM32_RCC_CIFR_HSI48RDYF STM32_RCC_CIFR_HSI48RDYF_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CICR REGISTER  ******************/
-#define STM32_RCC_CICR_LSIRDYC_POS 0U
-#define STM32_RCC_CICR_LSIRDYC_MSK (0x1UL << STM32_RCC_CICR_LSIRDYC_POS)
-#define STM32_RCC_CICR_LSIRDYC STM32_RCC_CICR_LSIRDYC_MSK
-#define STM32_RCC_CICR_LSERDYC_POS 1U
-#define STM32_RCC_CICR_LSERDYC_MSK (0x1UL << STM32_RCC_CICR_LSERDYC_POS)
-#define STM32_RCC_CICR_LSERDYC STM32_RCC_CICR_LSERDYC_MSK
-#define STM32_RCC_CICR_MSIRDYC_POS 2U
-#define STM32_RCC_CICR_MSIRDYC_MSK (0x1UL << STM32_RCC_CICR_MSIRDYC_POS)
-#define STM32_RCC_CICR_MSIRDYC STM32_RCC_CICR_MSIRDYC_MSK
-#define STM32_RCC_CICR_HSIRDYC_POS 3U
-#define STM32_RCC_CICR_HSIRDYC_MSK (0x1UL << STM32_RCC_CICR_HSIRDYC_POS)
-#define STM32_RCC_CICR_HSIRDYC STM32_RCC_CICR_HSIRDYC_MSK
-#define STM32_RCC_CICR_HSERDYC_POS 4U
-#define STM32_RCC_CICR_HSERDYC_MSK (0x1UL << STM32_RCC_CICR_HSERDYC_POS)
-#define STM32_RCC_CICR_HSERDYC STM32_RCC_CICR_HSERDYC_MSK
-#define STM32_RCC_CICR_PLLRDYC_POS 5U
-#define STM32_RCC_CICR_PLLRDYC_MSK (0x1UL << STM32_RCC_CICR_PLLRDYC_POS)
-#define STM32_RCC_CICR_PLLRDYC STM32_RCC_CICR_PLLRDYC_MSK
-#define STM32_RCC_CICR_PLLSAI1RDYC_POS 6U
-#define STM32_RCC_CICR_PLLSAI1RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI1RDYC_POS)
-#define STM32_RCC_CICR_PLLSAI1RDYC STM32_RCC_CICR_PLLSAI1RDYC_MSK
-#define STM32_RCC_CICR_PLLSAI2RDYC_POS 7U
-#define STM32_RCC_CICR_PLLSAI2RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI2RDYC_POS)
-#define STM32_RCC_CICR_PLLSAI2RDYC STM32_RCC_CICR_PLLSAI2RDYC_MSK
-#define STM32_RCC_CICR_CSSC_POS 8U
-#define STM32_RCC_CICR_CSSC_MSK (0x1UL << STM32_RCC_CICR_CSSC_POS)
-#define STM32_RCC_CICR_CSSC STM32_RCC_CICR_CSSC_MSK
-#define STM32_RCC_CICR_HSI48RDYC_POS 10U
-#define STM32_RCC_CICR_HSI48RDYC_MSK (0x1UL << STM32_RCC_CICR_HSI48RDYC_POS)
-#define STM32_RCC_CICR_HSI48RDYC STM32_RCC_CICR_HSI48RDYC_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB1RSTR REGISTER  **************/
-#define STM32_RCC_AHB1RSTR_DMA1RST_POS 0U
-#define STM32_RCC_AHB1RSTR_DMA1RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA1RST_POS)
-#define STM32_RCC_AHB1RSTR_DMA1RST STM32_RCC_AHB1RSTR_DMA1RST_MSK
-#define STM32_RCC_AHB1RSTR_DMA2RST_POS 1U
-#define STM32_RCC_AHB1RSTR_DMA2RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA2RST_POS)
-#define STM32_RCC_AHB1RSTR_DMA2RST STM32_RCC_AHB1RSTR_DMA2RST_MSK
-#define STM32_RCC_AHB1RSTR_DMAMUX1RST_POS 2U
-#define STM32_RCC_AHB1RSTR_DMAMUX1RST_MSK \
-	(0x1UL << STM32_RCC_AHB1RSTR_DMAMUX1RST_POS)
-#define STM32_RCC_AHB1RSTR_DMAMUX1RST STM32_RCC_AHB1RSTR_DMAMUX1RST_MSK
-#define STM32_RCC_AHB1RSTR_FLASHRST_POS 8U
-#define STM32_RCC_AHB1RSTR_FLASHRST_MSK \
-	(0x1UL << STM32_RCC_AHB1RSTR_FLASHRST_POS)
-#define STM32_RCC_AHB1RSTR_FLASHRST STM32_RCC_AHB1RSTR_FLASHRST_MSK
-#define STM32_RCC_AHB1RSTR_CRCRST_POS 12U
-#define STM32_RCC_AHB1RSTR_CRCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_CRCRST_POS)
-#define STM32_RCC_AHB1RSTR_CRCRST STM32_RCC_AHB1RSTR_CRCRST_MSK
-#define STM32_RCC_AHB1RSTR_TSCRST_POS 16U
-#define STM32_RCC_AHB1RSTR_TSCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_TSCRST_POS)
-#define STM32_RCC_AHB1RSTR_TSCRST STM32_RCC_AHB1RSTR_TSCRST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB2RSTR REGISTER  **************/
-#define STM32_RCC_AHB2RSTR_GPIOARST_POS 0U
-#define STM32_RCC_AHB2RSTR_GPIOARST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOARST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOARST STM32_RCC_AHB2RSTR_GPIOARST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOBRST_POS 1U
-#define STM32_RCC_AHB2RSTR_GPIOBRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOBRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOBRST STM32_RCC_AHB2RSTR_GPIOBRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOCRST_POS 2U
-#define STM32_RCC_AHB2RSTR_GPIOCRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOCRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOCRST STM32_RCC_AHB2RSTR_GPIOCRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIODRST_POS 3U
-#define STM32_RCC_AHB2RSTR_GPIODRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIODRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIODRST STM32_RCC_AHB2RSTR_GPIODRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOERST_POS 4U
-#define STM32_RCC_AHB2RSTR_GPIOERST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOERST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOERST STM32_RCC_AHB2RSTR_GPIOERST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOFRST_POS 5U
-#define STM32_RCC_AHB2RSTR_GPIOFRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOFRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOFRST STM32_RCC_AHB2RSTR_GPIOFRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOGRST_POS 6U
-#define STM32_RCC_AHB2RSTR_GPIOGRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOGRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOGRST STM32_RCC_AHB2RSTR_GPIOGRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOHRST_POS 7U
-#define STM32_RCC_AHB2RSTR_GPIOHRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOHRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOHRST STM32_RCC_AHB2RSTR_GPIOHRST_MSK
-#define STM32_RCC_AHB2RSTR_ADCRST_POS 13U
-#define STM32_RCC_AHB2RSTR_ADCRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_ADCRST_POS)
-#define STM32_RCC_AHB2RSTR_ADCRST STM32_RCC_AHB2RSTR_ADCRST_MSK
-#define STM32_RCC_AHB2RSTR_AESRST_POS 16U
-#define STM32_RCC_AHB2RSTR_AESRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_AESRST_POS)
-#define STM32_RCC_AHB2RSTR_AESRST STM32_RCC_AHB2RSTR_AESRST_MSK
-#define STM32_RCC_AHB2RSTR_HASHRST_POS 17U
-#define STM32_RCC_AHB2RSTR_HASHRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_HASHRST_POS)
-#define STM32_RCC_AHB2RSTR_HASHRST STM32_RCC_AHB2RSTR_HASHRST_MSK
-#define STM32_RCC_AHB2RSTR_RNGRST_POS 18U
-#define STM32_RCC_AHB2RSTR_RNGRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_RNGRST_POS)
-#define STM32_RCC_AHB2RSTR_RNGRST STM32_RCC_AHB2RSTR_RNGRST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_AHB3RSTR REGISTER  **************/
-#define STM32_RCC_AHB3RSTR_FMCRST_POS 0U
-#define STM32_RCC_AHB3RSTR_FMCRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_FMCRST_POS)
-#define STM32_RCC_AHB3RSTR_FMCRST STM32_RCC_AHB3RSTR_FMCRST_MSK
-#define STM32_RCC_AHB3RSTR_QSPIRST_POS 8U
-#define STM32_RCC_AHB3RSTR_QSPIRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_QSPIRST_POS)
-#define STM32_RCC_AHB3RSTR_QSPIRST STM32_RCC_AHB3RSTR_QSPIRST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR1 REGISTER  **************/
-#define STM32_RCC_APB1RSTR1_TIM2RST_POS 0U
-#define STM32_RCC_APB1RSTR1_TIM2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM2RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM2RST STM32_RCC_APB1RSTR1_TIM2RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM3RST_POS 1U
-#define STM32_RCC_APB1RSTR1_TIM3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM3RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM3RST STM32_RCC_APB1RSTR1_TIM3RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM4RST_POS 2U
-#define STM32_RCC_APB1RSTR1_TIM4RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM4RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM4RST STM32_RCC_APB1RSTR1_TIM4RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM5RST_POS 3U
-#define STM32_RCC_APB1RSTR1_TIM5RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM5RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM5RST STM32_RCC_APB1RSTR1_TIM5RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM6RST_POS 4U
-#define STM32_RCC_APB1RSTR1_TIM6RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM6RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM6RST STM32_RCC_APB1RSTR1_TIM6RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM7RST_POS 5U
-#define STM32_RCC_APB1RSTR1_TIM7RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM7RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM7RST STM32_RCC_APB1RSTR1_TIM7RST_MSK
-#define STM32_RCC_APB1RSTR1_SPI2RST_POS 14U
-#define STM32_RCC_APB1RSTR1_SPI2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_SPI2RST_POS)
-#define STM32_RCC_APB1RSTR1_SPI2RST STM32_RCC_APB1RSTR1_SPI2RST_MSK
-#define STM32_RCC_APB1RSTR1_SPI3RST_POS 15U
-#define STM32_RCC_APB1RSTR1_SPI3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_SPI3RST_POS)
-#define STM32_RCC_APB1RSTR1_SPI3RST STM32_RCC_APB1RSTR1_SPI3RST_MSK
-#define STM32_RCC_APB1RSTR1_USART2RST_POS 17U
-#define STM32_RCC_APB1RSTR1_USART2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART2RST_POS)
-#define STM32_RCC_APB1RSTR1_USART2RST STM32_RCC_APB1RSTR1_USART2RST_MSK
-#define STM32_RCC_APB1RSTR1_USART3RST_POS 18U
-#define STM32_RCC_APB1RSTR1_USART3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART3RST_POS)
-#define STM32_RCC_APB1RSTR1_USART3RST STM32_RCC_APB1RSTR1_USART3RST_MSK
-#define STM32_RCC_APB1RSTR1_USART4RST_POS 19U
-#define STM32_RCC_APB1RSTR1_USART4RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART4RST_POS)
-#define STM32_RCC_APB1RSTR1_USART4RST STM32_RCC_APB1RSTR1_USART4RST_MSK
-#define STM32_RCC_APB1RSTR1_USART5RST_POS 20U
-#define STM32_RCC_APB1RSTR1_USART5RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART5RST_POS)
-#define STM32_RCC_APB1RSTR1_USART5RST STM32_RCC_APB1RSTR1_USART5RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C1RST_POS 21U
-#define STM32_RCC_APB1RSTR1_I2C1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C1RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C1RST STM32_RCC_APB1RSTR1_I2C1RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C2RST_POS 22U
-#define STM32_RCC_APB1RSTR1_I2C2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C2RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C2RST STM32_RCC_APB1RSTR1_I2C2RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C3RST_POS 23U
-#define STM32_RCC_APB1RSTR1_I2C3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C3RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C3RST STM32_RCC_APB1RSTR1_I2C3RST_MSK
-#define STM32_RCC_APB1RSTR1_CRSRST_POS 24U
-#define STM32_RCC_APB1RSTR1_CRSRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_CRSRST_POS)
-#define STM32_RCC_APB1RSTR1_CRSRST STM32_RCC_APB1RSTR1_CRSRST_MSK
-#define STM32_RCC_APB1RSTR1_PWRRST_POS 28U
-#define STM32_RCC_APB1RSTR1_PWRRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_PWRRST_POS)
-#define STM32_RCC_APB1RSTR1_PWRRST STM32_RCC_APB1RSTR1_PWRRST_MSK
-#define STM32_RCC_APB1RSTR1_DAC1RST_POS 29U
-#define STM32_RCC_APB1RSTR1_DAC1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_DAC1RST_POS)
-#define STM32_RCC_APB1RSTR1_DAC1RST STM32_RCC_APB1RSTR1_DAC1RST_MSK
-#define STM32_RCC_APB1RSTR1_OPAMPRST_POS 30U
-#define STM32_RCC_APB1RSTR1_OPAMPRST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_OPAMPRST_POS)
-#define STM32_RCC_APB1RSTR1_OPAMPRST STM32_RCC_APB1RSTR1_OPAMPRST_MSK
-#define STM32_RCC_APB1RSTR1_LPTIM1RST_POS 31U
-#define STM32_RCC_APB1RSTR1_LPTIM1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_LPTIM1RST_POS)
-#define STM32_RCC_APB1RSTR1_LPTIM1RST STM32_RCC_APB1RSTR1_LPTIM1RST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
-#define STM32_RCC_APB1RSTR2_LPUART1RST_POS 0U
-#define STM32_RCC_APB1RSTR2_LPUART1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPUART1RST_POS)
-#define STM32_RCC_APB1RSTR2_LPUART1RST STM32_RCC_APB1RSTR2_LPUART1RST_MSK
-#define STM32_RCC_APB1RSTR2_I2C4RST_POS 1U
-#define STM32_RCC_APB1RSTR2_I2C4RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_I2C4RST_POS)
-#define STM32_RCC_APB1RSTR2_I2C4RST STM32_RCC_APB1RSTR2_I2C4RST_MSK
-#define STM32_RCC_APB1RSTR2_LPTIM2RST_POS 5U
-#define STM32_RCC_APB1RSTR2_LPTIM2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPTIM2RST_POS)
-#define STM32_RCC_APB1RSTR2_LPTIM2RST STM32_RCC_APB1RSTR2_LPTIM2RST_MSK
-#define STM32_RCC_APB1RSTR2_LPTIM3RST_POS 6U
-#define STM32_RCC_APB1RSTR2_LPTIM3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPTIM3RST_POS)
-#define STM32_RCC_APB1RSTR2_LPTIM3RST STM32_RCC_APB1RSTR2_LPTIM3RST_MSK
-#define STM32_RCC_APB1RSTR2_FDCAN1RST_POS 9U
-#define STM32_RCC_APB1RSTR2_FDCAN1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_FDCAN1RST_POS)
-#define STM32_RCC_APB1RSTR2_FDCAN1RST STM32_RCC_APB1RSTR2_FDCAN1RST_MSK
-#define STM32_RCC_APB1RSTR2_USBFSRST_POS 21U
-#define STM32_RCC_APB1RSTR2_USBFSRST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_USBFSRST_POS)
-#define STM32_RCC_APB1RSTR2_USBFSRST STM32_RCC_APB1RSTR2_USBFSRST_MSK
-#define STM32_RCC_APB1RSTR2_UCPD1RST_POS 23U
-#define STM32_RCC_APB1RSTR2_UCPD1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_UCPD1RST_POS)
-#define STM32_RCC_APB1RSTR2_UCPD1RST STM32_RCC_APB1RSTR2_UCPD1RST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB2RSTR REGISTER  **************/
-#define STM32_RCC_APB2RSTR_SYSCFGRST_POS 0U
-#define STM32_RCC_APB2RSTR_SYSCFGRST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_SYSCFGRST_POS)
-#define STM32_RCC_APB2RSTR_SYSCFGRST STM32_RCC_APB2RSTR_SYSCFGRST_MSK
-#define STM32_RCC_APB2RSTR_TIM1RST_POS 11U
-#define STM32_RCC_APB2RSTR_TIM1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM1RST_POS)
-#define STM32_RCC_APB2RSTR_TIM1RST STM32_RCC_APB2RSTR_TIM1RST_MSK
-#define STM32_RCC_APB2RSTR_SPI1RST_POS 12U
-#define STM32_RCC_APB2RSTR_SPI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SPI1RST_POS)
-#define STM32_RCC_APB2RSTR_SPI1RST STM32_RCC_APB2RSTR_SPI1RST_MSK
-#define STM32_RCC_APB2RSTR_TIM8RST_POS 13U
-#define STM32_RCC_APB2RSTR_TIM8RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM8RST_POS)
-#define STM32_RCC_APB2RSTR_TIM8RST STM32_RCC_APB2RSTR_TIM8RST_MSK
-#define STM32_RCC_APB2RSTR_USART1RST_POS 14U
-#define STM32_RCC_APB2RSTR_USART1RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_USART1RST_POS)
-#define STM32_RCC_APB2RSTR_USART1RST STM32_RCC_APB2RSTR_USART1RST_MSK
-#define STM32_RCC_APB2RSTR_TIM15RST_POS 16U
-#define STM32_RCC_APB2RSTR_TIM15RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM15RST_POS)
-#define STM32_RCC_APB2RSTR_TIM15RST STM32_RCC_APB2RSTR_TIM15RST_MSK
-#define STM32_RCC_APB2RSTR_TIM16RST_POS 17U
-#define STM32_RCC_APB2RSTR_TIM16RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM16RST_POS)
-#define STM32_RCC_APB2RSTR_TIM16RST STM32_RCC_APB2RSTR_TIM16RST_MSK
-#define STM32_RCC_APB2RSTR_TIM17RST_POS 18U
-#define STM32_RCC_APB2RSTR_TIM17RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM17RST_POS)
-#define STM32_RCC_APB2RSTR_TIM17RST STM32_RCC_APB2RSTR_TIM17RST_MSK
-#define STM32_RCC_APB2RSTR_SAI1RST_POS 21U
-#define STM32_RCC_APB2RSTR_SAI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI1RST_POS)
-#define STM32_RCC_APB2RSTR_SAI1RST STM32_RCC_APB2RSTR_SAI1RST_MSK
-#define STM32_RCC_APB2RSTR_SAI2RST_POS 22U
-#define STM32_RCC_APB2RSTR_SAI2RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI2RST_POS)
-#define STM32_RCC_APB2RSTR_SAI2RST STM32_RCC_APB2RSTR_SAI2RST_MSK
-#define STM32_RCC_APB2RSTR_DFSDM1RST_POS 24U
-#define STM32_RCC_APB2RSTR_DFSDM1RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_DFSDM1RST_POS)
-#define STM32_RCC_APB2RSTR_DFSDM1RST STM32_RCC_APB2RSTR_DFSDM1RST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB1ENR REGISTER  ***************/
-#define STM32_RCC_AHB1ENR_DMA1EN_POS 0U
-#define STM32_RCC_AHB1ENR_DMA1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA1EN_POS)
-#define STM32_RCC_AHB1ENR_DMA1EN STM32_RCC_AHB1ENR_DMA1EN_MSK
-#define STM32_RCC_AHB1ENR_DMA2EN_POS 1U
-#define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS)
-#define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK
-#define STM32_RCC_AHB1ENR_DMAMUX1EN_POS 2U
-#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS)
-#define STM32_RCC_AHB1ENR_DMAMUX1EN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK
-#define STM32_RCC_AHB1ENR_FLASHEN_POS 8U
-#define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS)
-#define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK
-#define STM32_RCC_AHB1ENR_CRCEN_POS 12U
-#define STM32_RCC_AHB1ENR_CRCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_CRCEN_POS)
-#define STM32_RCC_AHB1ENR_CRCEN STM32_RCC_AHB1ENR_CRCEN_MSK
-#define STM32_RCC_AHB1ENR_TSCEN_POS 16U
-#define STM32_RCC_AHB1ENR_TSCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_TSCEN_POS)
-#define STM32_RCC_AHB1ENR_TSCEN STM32_RCC_AHB1ENR_TSCEN_MSK
-#define STM32_RCC_AHB1ENR_GTZCEN_POS 22U
-#define STM32_RCC_AHB1ENR_GTZCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_GTZCEN_POS)
-#define STM32_RCC_AHB1ENR_GTZCEN STM32_RCC_AHB1ENR_GTZCEN_MSK
-
-/***************  BIT DEFINITION FOR STM32_RCC_AHB2ENR REGISTER  *********/
-#define STM32_RCC_AHB2ENR_GPIOAEN_POS 0U
-#define STM32_RCC_AHB2ENR_GPIOAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOAEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOAEN STM32_RCC_AHB2ENR_GPIOAEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOBEN_POS 1U
-#define STM32_RCC_AHB2ENR_GPIOBEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOBEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOBEN STM32_RCC_AHB2ENR_GPIOBEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOCEN_POS 2U
-#define STM32_RCC_AHB2ENR_GPIOCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOCEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOCEN STM32_RCC_AHB2ENR_GPIOCEN_MSK
-#define STM32_RCC_AHB2ENR_GPIODEN_POS 3U
-#define STM32_RCC_AHB2ENR_GPIODEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIODEN_POS)
-#define STM32_RCC_AHB2ENR_GPIODEN STM32_RCC_AHB2ENR_GPIODEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOEEN_POS 4U
-#define STM32_RCC_AHB2ENR_GPIOEEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOEEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOEEN STM32_RCC_AHB2ENR_GPIOEEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOFEN_POS 5U
-#define STM32_RCC_AHB2ENR_GPIOFEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOFEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOFEN STM32_RCC_AHB2ENR_GPIOFEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOGEN_POS 6U
-#define STM32_RCC_AHB2ENR_GPIOGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOGEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOGEN STM32_RCC_AHB2ENR_GPIOGEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOHEN_POS 7U
-#define STM32_RCC_AHB2ENR_GPIOHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOHEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOHEN STM32_RCC_AHB2ENR_GPIOHEN_MSK
-#define STM32_RCC_AHB2ENR_ADCEN_POS 13U
-#define STM32_RCC_AHB2ENR_ADCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_ADCEN_POS)
-#define STM32_RCC_AHB2ENR_ADCEN STM32_RCC_AHB2ENR_ADCEN_MSK
-#define STM32_RCC_AHB2ENR_AESEN_POS 16U
-#define STM32_RCC_AHB2ENR_AESEN_MSK (0x1UL << STM32_RCC_AHB2ENR_AESEN_POS)
-#define STM32_RCC_AHB2ENR_AESEN STM32_RCC_AHB2ENR_AESEN_MSK
-#define STM32_RCC_AHB2ENR_HASHEN_POS 17U
-#define STM32_RCC_AHB2ENR_HASHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_HASHEN_POS)
-#define STM32_RCC_AHB2ENR_HASHEN STM32_RCC_AHB2ENR_HASHEN_MSK
-#define STM32_RCC_AHB2ENR_RNGEN_POS 18U
-#define STM32_RCC_AHB2ENR_RNGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_RNGEN_POS)
-#define STM32_RCC_AHB2ENR_RNGEN STM32_RCC_AHB2ENR_RNGEN_MSK
-#define STM32_RCC_AHB2ENR_PKAEN_POS 19U
-#define STM32_RCC_AHB2ENR_PKAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_PKAEN_POS)
-#define STM32_RCC_AHB2ENR_PKAEN STM32_RCC_AHB2ENR_PKAEN_MSK
-#define STM32_RCC_AHB2ENR_OTFDEC1EN_POS 21U
-#define STM32_RCC_AHB2ENR_OTFDEC1EN_MSK \
-	(0x1UL << STM32_RCC_AHB2ENR_OTFDEC1EN_POS)
-#define STM32_RCC_AHB2ENR_OTFDEC1EN STM32_RCC_AHB2ENR_OTFDEC1EN_MSK
-#define STM32_RCC_AHB2ENR_SDMMC1EN_POS 22U
-#define STM32_RCC_AHB2ENR_SDMMC1EN_MSK (0x1UL << STM32_RCC_AHB2ENR_SDMMC1EN_POS)
-#define STM32_RCC_AHB2ENR_SDMMC1EN STM32_RCC_AHB2ENR_SDMMC1EN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB3ENR REGISTER  ***************/
-#define STM32_RCC_AHB3ENR_FMCEN_POS 0U
-#define STM32_RCC_AHB3ENR_FMCEN_MSK (0x1UL << STM32_RCC_AHB3ENR_FMCEN_POS)
-#define STM32_RCC_AHB3ENR_FMCEN STM32_RCC_AHB3ENR_FMCEN_MSK
-#define STM32_RCC_AHB3ENR_QSPIEN_POS 8U
-#define STM32_RCC_AHB3ENR_QSPIEN_MSK (0x1UL << STM32_RCC_AHB3ENR_QSPIEN_POS)
-#define STM32_RCC_AHB3ENR_QSPIEN STM32_RCC_AHB3ENR_QSPIEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB1ENR1 REGISTER  **************/
-#define STM32_RCC_APB1ENR1_TIM2EN_POS 0U
-#define STM32_RCC_APB1ENR1_TIM2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM2EN_POS)
-#define STM32_RCC_APB1ENR1_TIM2EN STM32_RCC_APB1ENR1_TIM2EN_MSK
-#define STM32_RCC_APB1ENR1_TIM3EN_POS 1U
-#define STM32_RCC_APB1ENR1_TIM3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM3EN_POS)
-#define STM32_RCC_APB1ENR1_TIM3EN STM32_RCC_APB1ENR1_TIM3EN_MSK
-#define STM32_RCC_APB1ENR1_TIM4EN_POS 2U
-#define STM32_RCC_APB1ENR1_TIM4EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM4EN_POS)
-#define STM32_RCC_APB1ENR1_TIM4EN STM32_RCC_APB1ENR1_TIM4EN_MSK
-#define STM32_RCC_APB1ENR1_TIM5EN_POS 3U
-#define STM32_RCC_APB1ENR1_TIM5EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM5EN_POS)
-#define STM32_RCC_APB1ENR1_TIM5EN STM32_RCC_APB1ENR1_TIM5EN_MSK
-#define STM32_RCC_APB1ENR1_TIM6EN_POS 4U
-#define STM32_RCC_APB1ENR1_TIM6EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM6EN_POS)
-#define STM32_RCC_APB1ENR1_TIM6EN STM32_RCC_APB1ENR1_TIM6EN_MSK
-#define STM32_RCC_APB1ENR1_TIM7EN_POS 5U
-#define STM32_RCC_APB1ENR1_TIM7EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM7EN_POS)
-#define STM32_RCC_APB1ENR1_TIM7EN STM32_RCC_APB1ENR1_TIM7EN_MSK
-#define STM32_RCC_APB1ENR1_RTCAPBEN_POS 10U
-#define STM32_RCC_APB1ENR1_RTCAPBEN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_RTCAPBEN_POS)
-#define STM32_RCC_APB1ENR1_RTCAPBEN STM32_RCC_APB1ENR1_RTCAPBEN_MSK
-#define STM32_RCC_APB1ENR1_WWDGEN_POS 11U
-#define STM32_RCC_APB1ENR1_WWDGEN_MSK (0x1UL << STM32_RCC_APB1ENR1_WWDGEN_POS)
-#define STM32_RCC_APB1ENR1_WWDGEN STM32_RCC_APB1ENR1_WWDGEN_MSK
-#define STM32_RCC_APB1ENR1_SPI2EN_POS 14U
-#define STM32_RCC_APB1ENR1_SPI2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI2EN_POS)
-#define STM32_RCC_APB1ENR1_SPI2EN STM32_RCC_APB1ENR1_SPI2EN_MSK
-#define STM32_RCC_APB1ENR1_SPI3EN_POS 15U
-#define STM32_RCC_APB1ENR1_SPI3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI3EN_POS)
-#define STM32_RCC_APB1ENR1_SPI3EN STM32_RCC_APB1ENR1_SPI3EN_MSK
-#define STM32_RCC_APB1ENR1_USART2EN_POS 17U
-#define STM32_RCC_APB1ENR1_USART2EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_USART2EN_POS)
-#define STM32_RCC_APB1ENR1_USART2EN STM32_RCC_APB1ENR1_USART2EN_MSK
-#define STM32_RCC_APB1ENR1_USART3EN_POS 18U
-#define STM32_RCC_APB1ENR1_USART3EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS)
-#define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK
-#define STM32_RCC_APB1ENR1_UART4EN_POS 19U
-#define STM32_RCC_APB1ENR1_UART4EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS)
-#define STM32_RCC_APB1ENR1_UART4EN STM32_RCC_APB1ENR1_UART4EN_MSK
-#define STM32_RCC_APB1ENR1_UART5EN_POS 20U
-#define STM32_RCC_APB1ENR1_UART5EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS)
-#define STM32_RCC_APB1ENR1_UART5EN STM32_RCC_APB1ENR1_UART5EN_MSK
-#define STM32_RCC_APB1ENR1_I2C1EN_POS 21U
-#define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS)
-#define STM32_RCC_APB1ENR1_I2C1EN STM32_RCC_APB1ENR1_I2C1EN_MSK
-#define STM32_RCC_APB1ENR1_I2C2EN_POS 22U
-#define STM32_RCC_APB1ENR1_I2C2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C2EN_POS)
-#define STM32_RCC_APB1ENR1_I2C2EN STM32_RCC_APB1ENR1_I2C2EN_MSK
-#define STM32_RCC_APB1ENR1_I2C3EN_POS 23U
-#define STM32_RCC_APB1ENR1_I2C3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C3EN_POS)
-#define STM32_RCC_APB1ENR1_I2C3EN STM32_RCC_APB1ENR1_I2C3EN_MSK
-#define STM32_RCC_APB1ENR1_CRSEN_POS 24U
-#define STM32_RCC_APB1ENR1_CRSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_CRSEN_POS)
-#define STM32_RCC_APB1ENR1_CRSEN STM32_RCC_APB1ENR1_CRSEN_MSK
-#define STM32_RCC_APB1ENR1_PWREN_POS 28U
-#define STM32_RCC_APB1ENR1_PWREN_MSK (0x1UL << STM32_RCC_APB1ENR1_PWREN_POS)
-#define STM32_RCC_APB1ENR1_PWREN STM32_RCC_APB1ENR1_PWREN_MSK
-#define STM32_RCC_APB1ENR1_DAC1EN_POS 29U
-#define STM32_RCC_APB1ENR1_DAC1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_DAC1EN_POS)
-#define STM32_RCC_APB1ENR1_DAC1EN STM32_RCC_APB1ENR1_DAC1EN_MSK
-#define STM32_RCC_APB1ENR1_OPAMPEN_POS 30U
-#define STM32_RCC_APB1ENR1_OPAMPEN_MSK (0x1UL << STM32_RCC_APB1ENR1_OPAMPEN_POS)
-#define STM32_RCC_APB1ENR1_OPAMPEN STM32_RCC_APB1ENR1_OPAMPEN_MSK
-#define STM32_RCC_APB1ENR1_LPTIM1EN_POS 31U
-#define STM32_RCC_APB1ENR1_LPTIM1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_LPTIM1EN_POS)
-#define STM32_RCC_APB1ENR1_LPTIM1EN STM32_RCC_APB1ENR1_LPTIM1EN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
-#define STM32_RCC_APB1ENR2_LPUART1EN_POS 0U
-#define STM32_RCC_APB1ENR2_LPUART1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS)
-#define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK
-#define STM32_RCC_APB1ENR2_I2C4EN_POS 1U
-#define STM32_RCC_APB1ENR2_I2C4EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS)
-#define STM32_RCC_APB1ENR2_I2C4EN STM32_RCC_APB1ENR2_I2C4EN_MSK
-#define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U
-#define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPTIM2EN_POS)
-#define STM32_RCC_APB1ENR2_LPTIM2EN STM32_RCC_APB1ENR2_LPTIM2EN_MSK
-#define STM32_RCC_APB1ENR2_LPTIM3EN_POS 6U
-#define STM32_RCC_APB1ENR2_LPTIM3EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPTIM3EN_POS)
-#define STM32_RCC_APB1ENR2_LPTIM3EN STM32_RCC_APB1ENR2_LPTIM3EN_MSK
-#define STM32_RCC_APB1ENR2_FDCAN1EN_POS 9U
-#define STM32_RCC_APB1ENR2_FDCAN1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_FDCAN1EN_POS)
-#define STM32_RCC_APB1ENR2_FDCAN1EN STM32_RCC_APB1ENR2_FDCAN1EN_MSK
-#define STM32_RCC_APB1ENR2_USBFSEN_POS 21U
-#define STM32_RCC_APB1ENR2_USBFSEN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS)
-#define STM32_RCC_APB1ENR2_USBFSEN STM32_RCC_APB1ENR2_USBFSEN_MSK
-#define STM32_RCC_APB1ENR2_UCPD1EN_POS 23U
-#define STM32_RCC_APB1ENR2_UCPD1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS)
-#define STM32_RCC_APB1ENR2_UCPD1EN STM32_RCC_APB1ENR2_UCPD1EN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER  ***************/
-#define STM32_RCC_APB2ENR_SYSCFGEN_POS 0U
-#define STM32_RCC_APB2ENR_SYSCFGEN_MSK (0x1UL << STM32_RCC_APB2ENR_SYSCFGEN_POS)
-#define STM32_RCC_APB2ENR_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN_MSK
-#define STM32_RCC_APB2ENR_TIM1EN_POS 11U
-#define STM32_RCC_APB2ENR_TIM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM1EN_POS)
-#define STM32_RCC_APB2ENR_TIM1EN STM32_RCC_APB2ENR_TIM1EN_MSK
-#define STM32_RCC_APB2ENR_SPI1EN_POS 12U
-#define STM32_RCC_APB2ENR_SPI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SPI1EN_POS)
-#define STM32_RCC_APB2ENR_SPI1EN STM32_RCC_APB2ENR_SPI1EN_MSK
-#define STM32_RCC_APB2ENR_TIM8EN_POS 13U
-#define STM32_RCC_APB2ENR_TIM8EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM8EN_POS)
-#define STM32_RCC_APB2ENR_TIM8EN STM32_RCC_APB2ENR_TIM8EN_MSK
-#define STM32_RCC_APB2ENR_USART1EN_POS 14U
-#define STM32_RCC_APB2ENR_USART1EN_MSK (0x1UL << STM32_RCC_APB2ENR_USART1EN_POS)
-#define STM32_RCC_APB2ENR_USART1EN STM32_RCC_APB2ENR_USART1EN_MSK
-#define STM32_RCC_APB2ENR_TIM15EN_POS 16U
-#define STM32_RCC_APB2ENR_TIM15EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM15EN_POS)
-#define STM32_RCC_APB2ENR_TIM15EN STM32_RCC_APB2ENR_TIM15EN_MSK
-#define STM32_RCC_APB2ENR_TIM16EN_POS 17U
-#define STM32_RCC_APB2ENR_TIM16EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM16EN_POS)
-#define STM32_RCC_APB2ENR_TIM16EN STM32_RCC_APB2ENR_TIM16EN_MSK
-#define STM32_RCC_APB2ENR_TIM17EN_POS 18U
-#define STM32_RCC_APB2ENR_TIM17EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM17EN_POS)
-#define STM32_RCC_APB2ENR_TIM17EN STM32_RCC_APB2ENR_TIM17EN_MSK
-#define STM32_RCC_APB2ENR_SAI1EN_POS 21U
-#define STM32_RCC_APB2ENR_SAI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI1EN_POS)
-#define STM32_RCC_APB2ENR_SAI1EN STM32_RCC_APB2ENR_SAI1EN_MSK
-#define STM32_RCC_APB2ENR_SAI2EN_POS 22U
-#define STM32_RCC_APB2ENR_SAI2EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI2EN_POS)
-#define STM32_RCC_APB2ENR_SAI2EN STM32_RCC_APB2ENR_SAI2EN_MSK
-#define STM32_RCC_APB2ENR_DFSDM1EN_POS 24U
-#define STM32_RCC_APB2ENR_DFSDM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_DFSDM1EN_POS)
-#define STM32_RCC_APB2ENR_DFSDM1EN STM32_RCC_APB2ENR_DFSDM1EN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_AHB1SMENR REGISTER  ***************/
-#define STM32_RCC_AHB1SMENR_DMA1SMEN_POS 0U
-#define STM32_RCC_AHB1SMENR_DMA1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMA1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMA1SMEN STM32_RCC_AHB1SMENR_DMA1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_DMA2SMEN_POS 1U
-#define STM32_RCC_AHB1SMENR_DMA2SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMA2SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMA2SMEN STM32_RCC_AHB1SMENR_DMA2SMEN_MSK
-#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN_POS 2U
-#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMAMUX1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN STM32_RCC_AHB1SMENR_DMAMUX1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_FLASHSMEN_POS 8U
-#define STM32_RCC_AHB1SMENR_FLASHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_FLASHSMEN_POS)
-#define STM32_RCC_AHB1SMENR_FLASHSMEN STM32_RCC_AHB1SMENR_FLASHSMEN_MSK
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN_POS 9U
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_SRAM1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_CRCSMEN_POS 12U
-#define STM32_RCC_AHB1SMENR_CRCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_CRCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_CRCSMEN STM32_RCC_AHB1SMENR_CRCSMEN_MSK
-#define STM32_RCC_AHB1SMENR_TSCSMEN_POS 16U
-#define STM32_RCC_AHB1SMENR_TSCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_TSCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_TSCSMEN STM32_RCC_AHB1SMENR_TSCSMEN_MSK
-#define STM32_RCC_AHB1SMENR_GTZCSMEN_POS 22U
-#define STM32_RCC_AHB1SMENR_GTZCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_GTZCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_GTZCSMEN STM32_RCC_AHB1SMENR_GTZCSMEN_MSK
-#define STM32_RCC_AHB1SMENR_ICACHESMEN_POS 23U
-#define STM32_RCC_AHB1SMENR_ICACHESMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_ICACHESMEN_POS)
-#define STM32_RCC_AHB1SMENR_ICACHESMEN STM32_RCC_AHB1SMENR_ICACHESMEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB2SMENR REGISTER  *************/
-#define STM32_RCC_AHB2SMENR_GPIOASMEN_POS 0U
-#define STM32_RCC_AHB2SMENR_GPIOASMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOASMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOASMEN STM32_RCC_AHB2SMENR_GPIOASMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN_POS 1U
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOBSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN_POS 2U
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOCSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIODSMEN_POS 3U
-#define STM32_RCC_AHB2SMENR_GPIODSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIODSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIODSMEN STM32_RCC_AHB2SMENR_GPIODSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOESMEN_POS 4U
-#define STM32_RCC_AHB2SMENR_GPIOESMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOESMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOESMEN STM32_RCC_AHB2SMENR_GPIOESMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOFSMEN_POS 5U
-#define STM32_RCC_AHB2SMENR_GPIOFSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOFSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOFSMEN STM32_RCC_AHB2SMENR_GPIOFSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOGSMEN_POS 6U
-#define STM32_RCC_AHB2SMENR_GPIOGSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOGSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOGSMEN STM32_RCC_AHB2SMENR_GPIOGSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN_POS 7U
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOHSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN_POS 9U
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_SRAM2SMEN_POS)
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK
-#define STM32_RCC_AHB2SMENR_ADCSMEN_POS 13U
-#define STM32_RCC_AHB2SMENR_ADCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_ADCSMEN_POS)
-#define STM32_RCC_AHB2SMENR_ADCSMEN STM32_RCC_AHB2SMENR_ADCSMEN_MSK
-#define STM32_RCC_AHB2SMENR_AESSMEN_POS 16U
-#define STM32_RCC_AHB2SMENR_AESSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_AESSMEN_POS)
-#define STM32_RCC_AHB2SMENR_AESSMEN STM32_RCC_AHB2SMENR_AESSMEN_MSK
-#define STM32_RCC_AHB2SMENR_HASHSMEN_POS 17U
-#define STM32_RCC_AHB2SMENR_HASHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_HASHSMEN_POS)
-#define STM32_RCC_AHB2SMENR_HASHSMEN STM32_RCC_AHB2SMENR_HASHSMEN_MSK
-#define STM32_RCC_AHB2SMENR_RNGSMEN_POS 18U
-#define STM32_RCC_AHB2SMENR_RNGSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_RNGSMEN_POS)
-#define STM32_RCC_AHB2SMENR_RNGSMEN STM32_RCC_AHB2SMENR_RNGSMEN_MSK
-#define STM32_RCC_AHB2SMENR_PKASMEN_POS 19U
-#define STM32_RCC_AHB2SMENR_PKASMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_PKASMEN_POS)
-#define STM32_RCC_AHB2SMENR_PKASMEN STM32_RCC_AHB2SMENR_PKASMEN_MSK
-#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN_POS 21U
-#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_OTFDEC1SMEN_POS)
-#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN STM32_RCC_AHB2SMENR_OTFDEC1SMEN_MSK
-#define STM32_RCC_AHB2SMENR_SDMMC1SMEN_POS 22U
-#define STM32_RCC_AHB2SMENR_SDMMC1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_SDMMC1SMEN_POS)
-#define STM32_RCC_AHB2SMENR_SDMMC1SMEN STM32_RCC_AHB2SMENR_SDMMC1SMEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB3SMENR REGISTER  *************/
-#define STM32_RCC_AHB3SMENR_FMCSMEN_POS 0U
-#define STM32_RCC_AHB3SMENR_FMCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB3SMENR_FMCSMEN_POS)
-#define STM32_RCC_AHB3SMENR_FMCSMEN STM32_RCC_AHB3SMENR_FMCSMEN_MSK
-#define STM32_RCC_AHB3SMENR_QSPISMEN_POS 8U
-#define STM32_RCC_AHB3SMENR_QSPISMEN_MSK \
-	(0x1UL << STM32_RCC_AHB3SMENR_QSPISMEN_POS)
-#define STM32_RCC_AHB3SMENR_QSPISMEN STM32_RCC_AHB3SMENR_QSPISMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR1 REGISTER  *************/
-#define STM32_RCC_APB1SMENR1_TIM2SMEN_POS 0U
-#define STM32_RCC_APB1SMENR1_TIM2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM2SMEN STM32_RCC_APB1SMENR1_TIM2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM3SMEN_POS 1U
-#define STM32_RCC_APB1SMENR1_TIM3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM3SMEN STM32_RCC_APB1SMENR1_TIM3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM4SMEN_POS 2U
-#define STM32_RCC_APB1SMENR1_TIM4SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM4SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM4SMEN STM32_RCC_APB1SMENR1_TIM4SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM5SMEN_POS 3U
-#define STM32_RCC_APB1SMENR1_TIM5SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM5SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM5SMEN STM32_RCC_APB1SMENR1_TIM5SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM6SMEN_POS 4U
-#define STM32_RCC_APB1SMENR1_TIM6SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM6SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM6SMEN STM32_RCC_APB1SMENR1_TIM6SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM7SMEN_POS 5U
-#define STM32_RCC_APB1SMENR1_TIM7SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM7SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM7SMEN STM32_RCC_APB1SMENR1_TIM7SMEN_MSK
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS 10U
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS)
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK
-#define STM32_RCC_APB1SMENR1_WWDGSMEN_POS 11U
-#define STM32_RCC_APB1SMENR1_WWDGSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_WWDGSMEN_POS)
-#define STM32_RCC_APB1SMENR1_WWDGSMEN STM32_RCC_APB1SMENR1_WWDGSMEN_MSK
-#define STM32_RCC_APB1SMENR1_SPI2SMEN_POS 14U
-#define STM32_RCC_APB1SMENR1_SPI2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_SPI2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_SPI2SMEN STM32_RCC_APB1SMENR1_SPI2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_SPI3SMEN_POS 15U
-#define STM32_RCC_APB1SMENR1_SPI3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_SPI3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_SPI3SMEN STM32_RCC_APB1SMENR1_SPI3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART2SMEN_POS 17U
-#define STM32_RCC_APB1SMENR1_USART2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART2SMEN STM32_RCC_APB1SMENR1_USART2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART3SMEN_POS 18U
-#define STM32_RCC_APB1SMENR1_USART3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART3SMEN STM32_RCC_APB1SMENR1_USART3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART4SMEN_POS 19U
-#define STM32_RCC_APB1SMENR1_USART4SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART4SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART4SMEN STM32_RCC_APB1SMENR1_USART4SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART5SMEN_POS 20U
-#define STM32_RCC_APB1SMENR1_USART5SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART5SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART5SMEN STM32_RCC_APB1SMENR1_USART5SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C1SMEN_POS 21U
-#define STM32_RCC_APB1SMENR1_I2C1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C1SMEN STM32_RCC_APB1SMENR1_I2C1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C2SMEN_POS 22U
-#define STM32_RCC_APB1SMENR1_I2C2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C2SMEN STM32_RCC_APB1SMENR1_I2C2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C3SMEN_POS 23U
-#define STM32_RCC_APB1SMENR1_I2C3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C3SMEN STM32_RCC_APB1SMENR1_I2C3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_CRSSMEN_POS 24U
-#define STM32_RCC_APB1SMENR1_CRSSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_CRSSMEN_POS)
-#define STM32_RCC_APB1SMENR1_CRSSMEN STM32_RCC_APB1SMENR1_CRSSMEN_MSK
-#define STM32_RCC_APB1SMENR1_PWRSMEN_POS 28U
-#define STM32_RCC_APB1SMENR1_PWRSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_PWRSMEN_POS)
-#define STM32_RCC_APB1SMENR1_PWRSMEN STM32_RCC_APB1SMENR1_PWRSMEN_MSK
-#define STM32_RCC_APB1SMENR1_DAC1SMEN_POS 29U
-#define STM32_RCC_APB1SMENR1_DAC1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_DAC1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_DAC1SMEN STM32_RCC_APB1SMENR1_DAC1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN_POS 30U
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_OPAMPSMEN_POS)
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS 31U
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR2 REGISTER  *************/
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN_POS 0U
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPUART1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK
-#define STM32_RCC_APB1SMENR2_I2C4SMEN_POS 1U
-#define STM32_RCC_APB1SMENR2_I2C4SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_I2C4SMEN_POS)
-#define STM32_RCC_APB1SMENR2_I2C4SMEN STM32_RCC_APB1SMENR2_I2C4SMEN_MSK
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS 5U
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK
-#define STM32_RCC_APB1SMENR2_LPTIM3SMEN_POS 6U
-#define STM32_RCC_APB1SMENR2_LPTIM3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPTIM3SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPTIM3SMEN STM32_RCC_APB1SMENR2_LPTIM3SMEN_MSK
-#define STM32_RCC_APB1SMENR2_FDCAN1SMEN_POS 9U
-#define STM32_RCC_APB1SMENR2_FDCAN1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_FDCAN1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_FDCAN1SMEN STM32_RCC_APB1SMENR2_FDCAN1SMEN_MSK
-#define STM32_RCC_APB1SMENR2_USBFSSMEN_POS 21U
-#define STM32_RCC_APB1SMENR2_USBFSSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_USBFSSMEN_POS)
-#define STM32_RCC_APB1SMENR2_USBFSSMEN STM32_RCC_APB1SMENR2_USBFSSMEN_MSK
-#define STM32_RCC_APB1SMENR2_UCPD1SMEN_POS 23U
-#define STM32_RCC_APB1SMENR2_UCPD1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_UCPD1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_UCPD1SMEN STM32_RCC_APB1SMENR2_UCPD1SMEN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_APB2SMENR REGISTER  *************/
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN_POS 0U
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SYSCFGSMEN_POS)
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM1SMEN_POS 11U
-#define STM32_RCC_APB2SMENR_TIM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM1SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM1SMEN STM32_RCC_APB2SMENR_TIM1SMEN_MSK
-#define STM32_RCC_APB2SMENR_SPI1SMEN_POS 12U
-#define STM32_RCC_APB2SMENR_SPI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SPI1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SPI1SMEN STM32_RCC_APB2SMENR_SPI1SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM8SMEN_POS 13U
-#define STM32_RCC_APB2SMENR_TIM8SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM8SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM8SMEN STM32_RCC_APB2SMENR_TIM8SMEN_MSK
-#define STM32_RCC_APB2SMENR_USART1SMEN_POS 14U
-#define STM32_RCC_APB2SMENR_USART1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_USART1SMEN_POS)
-#define STM32_RCC_APB2SMENR_USART1SMEN STM32_RCC_APB2SMENR_USART1SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM15SMEN_POS 16U
-#define STM32_RCC_APB2SMENR_TIM15SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM15SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM15SMEN STM32_RCC_APB2SMENR_TIM15SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM16SMEN_POS 17U
-#define STM32_RCC_APB2SMENR_TIM16SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM16SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM16SMEN STM32_RCC_APB2SMENR_TIM16SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM17SMEN_POS 18U
-#define STM32_RCC_APB2SMENR_TIM17SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM17SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM17SMEN STM32_RCC_APB2SMENR_TIM17SMEN_MSK
-#define STM32_RCC_APB2SMENR_SAI1SMEN_POS 21U
-#define STM32_RCC_APB2SMENR_SAI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SAI1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SAI1SMEN STM32_RCC_APB2SMENR_SAI1SMEN_MSK
-#define STM32_RCC_APB2SMENR_SAI2SMEN_POS 22U
-#define STM32_RCC_APB2SMENR_SAI2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SAI2SMEN_POS)
-#define STM32_RCC_APB2SMENR_SAI2SMEN STM32_RCC_APB2SMENR_SAI2SMEN_MSK
-#define STM32_RCC_APB2SMENR_DFSDM1SMEN_POS 24U
-#define STM32_RCC_APB2SMENR_DFSDM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_DFSDM1SMEN_POS)
-#define STM32_RCC_APB2SMENR_DFSDM1SMEN STM32_RCC_APB2SMENR_DFSDM1SMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_CCIPR REGISTER  ******************/
-#define STM32_RCC_CCIPR_USART1SEL_POS 0U
-#define STM32_RCC_CCIPR_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS)
-#define STM32_RCC_CCIPR_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK
-#define STM32_RCC_CCIPR_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS)
-#define STM32_RCC_CCIPR_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS)
-
-#define STM32_RCC_CCIPR_USART2SEL_POS 2U
-#define STM32_RCC_CCIPR_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS)
-#define STM32_RCC_CCIPR_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK
-#define STM32_RCC_CCIPR_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS)
-#define STM32_RCC_CCIPR_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS)
-
-#define STM32_RCC_CCIPR_USART3SEL_POS 4U
-#define STM32_RCC_CCIPR_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS)
-#define STM32_RCC_CCIPR_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK
-#define STM32_RCC_CCIPR_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS)
-#define STM32_RCC_CCIPR_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS)
-
-#define STM32_RCC_CCIPR_USART4SEL_POS 6U
-#define STM32_RCC_CCIPR_USART4SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART4SEL_POS)
-#define STM32_RCC_CCIPR_USART4SEL STM32_RCC_CCIPR_USART4SEL_MSK
-#define STM32_RCC_CCIPR_USART4SEL_0 (0x1UL << STM32_RCC_CCIPR_USART4SEL_POS)
-#define STM32_RCC_CCIPR_USART4SEL_1 (0x2UL << STM32_RCC_CCIPR_USART4SEL_POS)
-
-#define STM32_RCC_CCIPR_USART5SEL_POS 8U
-#define STM32_RCC_CCIPR_USART5SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART5SEL_POS)
-#define STM32_RCC_CCIPR_USART5SEL STM32_RCC_CCIPR_USART5SEL_MSK
-#define STM32_RCC_CCIPR_USART5SEL_0 (0x1UL << STM32_RCC_CCIPR_USART5SEL_POS)
-#define STM32_RCC_CCIPR_USART5SEL_1 (0x2UL << STM32_RCC_CCIPR_USART5SEL_POS)
-
-#define STM32_RCC_CCIPR_LPUART1SEL_POS 10U
-#define STM32_RCC_CCIPR_LPUART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-#define STM32_RCC_CCIPR_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK
-#define STM32_RCC_CCIPR_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-#define STM32_RCC_CCIPR_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C1SEL_POS 12U
-#define STM32_RCC_CCIPR_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-#define STM32_RCC_CCIPR_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK
-#define STM32_RCC_CCIPR_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-#define STM32_RCC_CCIPR_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C2SEL_POS 14U
-#define STM32_RCC_CCIPR_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-#define STM32_RCC_CCIPR_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK
-#define STM32_RCC_CCIPR_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-#define STM32_RCC_CCIPR_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C3SEL_POS 16U
-#define STM32_RCC_CCIPR_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-#define STM32_RCC_CCIPR_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK
-#define STM32_RCC_CCIPR_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-#define STM32_RCC_CCIPR_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM1SEL_POS 18U
-#define STM32_RCC_CCIPR_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM2SEL_POS 20U
-#define STM32_RCC_CCIPR_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM3SEL_POS 22U
-#define STM32_RCC_CCIPR_LPTIM3SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM3SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM3SEL STM32_RCC_CCIPR_LPTIM3SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM3SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM3SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM3SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM3SEL_POS)
-
-#define STM32_RCC_CCIPR_FDCANSEL_POS 24U
-#define STM32_RCC_CCIPR_FDCANSEL_MSK (0x3UL << STM32_RCC_CCIPR_FDCANSEL_POS)
-#define STM32_RCC_CCIPR_FDCANSEL STM32_RCC_CCIPR_FDCANSEL_MSK
-#define STM32_RCC_CCIPR_FDCANSEL_0 (0x1UL << STM32_RCC_CCIPR_FDCANSEL_POS)
-#define STM32_RCC_CCIPR_FDCANSEL_1 (0x2UL << STM32_RCC_CCIPR_FDCANSEL_POS)
-
-#define STM32_RCC_CCIPR_CLK48SEL_POS 26U
-#define STM32_RCC_CCIPR_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-#define STM32_RCC_CCIPR_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK
-#define STM32_RCC_CCIPR_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-#define STM32_RCC_CCIPR_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-
-#define STM32_RCC_CCIPR_ADCSEL_POS 28U
-#define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS)
-#define STM32_RCC_CCIPR_ADCSEL STM32_RCC_CCIPR_ADCSEL_MSK
-#define STM32_RCC_CCIPR_ADCSEL_0 (0x1UL << STM32_RCC_CCIPR_ADCSEL_POS)
-#define STM32_RCC_CCIPR_ADCSEL_1 (0x2UL << STM32_RCC_CCIPR_ADCSEL_POS)
-
-/**************  BIT DEFINITION FOR STM32_RCC_BDCR REGISTER  ******************/
-#define STM32_RCC_BDCR_LSEBYP_POS 2U
-#define STM32_RCC_BDCR_LSEBYP_MSK (0x1UL << STM32_RCC_BDCR_LSEBYP_POS)
-#define STM32_RCC_BDCR_LSEBYP STM32_RCC_BDCR_LSEBYP_MSK
-
-#define STM32_RCC_BDCR_LSEDRV_POS 3U
-#define STM32_RCC_BDCR_LSEDRV_MSK (0x3UL << STM32_RCC_BDCR_LSEDRV_POS)
-#define STM32_RCC_BDCR_LSEDRV STM32_RCC_BDCR_LSEDRV_MSK
-#define STM32_RCC_BDCR_LSEDRV_0 (0x1UL << STM32_RCC_BDCR_LSEDRV_POS)
-#define STM32_RCC_BDCR_LSEDRV_1 (0x2UL << STM32_RCC_BDCR_LSEDRV_POS)
-
-#define STM32_RCC_BDCR_LSECSSON_POS 5U
-#define STM32_RCC_BDCR_LSECSSON_MSK (0x1UL << STM32_RCC_BDCR_LSECSSON_POS)
-#define STM32_RCC_BDCR_LSECSSON STM32_RCC_BDCR_LSECSSON_MSK
-#define STM32_RCC_BDCR_LSECSSD_POS 6U
-#define STM32_RCC_BDCR_LSECSSD_MSK (0x1UL << STM32_RCC_BDCR_LSECSSD_POS)
-#define STM32_RCC_BDCR_LSECSSD STM32_RCC_BDCR_LSECSSD_MSK
-#define STM32_RCC_BDCR_LSESYSEN_POS 7U
-#define STM32_RCC_BDCR_LSESYSEN_MSK (0x1UL << STM32_RCC_BDCR_LSESYSEN_POS)
-#define STM32_RCC_BDCR_LSESYSEN STM32_RCC_BDCR_LSESYSEN_MSK
-
-#define STM32_RCC_BDCR_RTCSEL_POS 8U
-#define STM32_RCC_BDCR_RTCSEL_MSK (0x3UL << STM32_RCC_BDCR_RTCSEL_POS)
-#define STM32_RCC_BDCR_RTCSEL STM32_RCC_BDCR_RTCSEL_MSK
-#define STM32_RCC_BDCR_RTCSEL_0 (0x1UL << STM32_RCC_BDCR_RTCSEL_POS)
-#define STM32_RCC_BDCR_RTCSEL_1 (0x2UL << STM32_RCC_BDCR_RTCSEL_POS)
-
-#define STM32_RCC_BDCR_LSESYSRDY_POS 11U
-#define STM32_RCC_BDCR_LSESYSRDY_MSK (0x1UL << STM32_RCC_BDCR_LSESYSRDY_POS)
-#define STM32_RCC_BDCR_LSESYSRDY STM32_RCC_BDCR_LSESYSRDY_MSK
-#define STM32_RCC_BDCR_LSCOEN_POS 24U
-#define STM32_RCC_BDCR_LSCOEN_MSK (0x1UL << STM32_RCC_BDCR_LSCOEN_POS)
-#define STM32_RCC_BDCR_LSCOEN STM32_RCC_BDCR_LSCOEN_MSK
-#define STM32_RCC_BDCR_LSCOSEL_POS 25U
-#define STM32_RCC_BDCR_LSCOSEL_MSK (0x1UL << STM32_RCC_BDCR_LSCOSEL_POS)
-#define STM32_RCC_BDCR_LSCOSEL STM32_RCC_BDCR_LSCOSEL_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CSR REGISTER  *******************/
-#define STM32_RCC_CSR_LSION_POS 0U
-#define STM32_RCC_CSR_LSION_MSK (0x1UL << STM32_RCC_CSR_LSION_POS)
-#define STM32_RCC_CSR_LSION STM32_RCC_CSR_LSION_MSK
-#define STM32_RCC_CSR_LSIRDY_POS 1U
-#define STM32_RCC_CSR_LSIRDY_MSK (0x1UL << STM32_RCC_CSR_LSIRDY_POS)
-#define STM32_RCC_CSR_LSIRDY STM32_RCC_CSR_LSIRDY_MSK
-#define STM32_RCC_CSR_LSIPRE_POS 4U
-#define STM32_RCC_CSR_LSIPRE_MSK (0x1UL << STM32_RCC_CSR_LSIPRE_POS)
-#define STM32_RCC_CSR_LSIPRE STM32_RCC_CSR_LSIPRE_MSK
-
-#define STM32_RCC_CSR_MSISRANGE_POS 8U
-#define STM32_RCC_CSR_MSISRANGE_MSK (0xFUL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE STM32_RCC_CSR_MSISRANGE_MSK
-#define STM32_RCC_CSR_MSISRANGE_1 (0x4UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_2 (0x5UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_4 (0x6UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_8 (0x7UL << STM32_RCC_CSR_MSISRANGE_POS)
-
-#define STM32_RCC_CSR_RMVF_POS 23U
-#define STM32_RCC_CSR_RMVF_MSK (0x1UL << STM32_RCC_CSR_RMVF_POS)
-#define STM32_RCC_CSR_RMVF STM32_RCC_CSR_RMVF_MSK
-#define STM32_RCC_CSR_OBLRSTF_POS 25U
-#define STM32_RCC_CSR_OBLRSTF_MSK (0x1UL << STM32_RCC_CSR_OBLRSTF_POS)
-#define STM32_RCC_CSR_OBLRSTF STM32_RCC_CSR_OBLRSTF_MSK
-#define STM32_RCC_CSR_PINRSTF_POS 26U
-#define STM32_RCC_CSR_PINRSTF_MSK (0x1UL << STM32_RCC_CSR_PINRSTF_POS)
-#define STM32_RCC_CSR_PINRSTF STM32_RCC_CSR_PINRSTF_MSK
-#define STM32_RCC_CSR_BORRSTF_POS 27U
-#define STM32_RCC_CSR_BORRSTF_MSK (0x1UL << STM32_RCC_CSR_BORRSTF_POS)
-#define STM32_RCC_CSR_BORRSTF STM32_RCC_CSR_BORRSTF_MSK
-#define STM32_RCC_CSR_SFTRSTF_POS 28U
-#define STM32_RCC_CSR_SFTRSTF_MSK (0x1UL << STM32_RCC_CSR_SFTRSTF_POS)
-#define STM32_RCC_CSR_SFTRSTF STM32_RCC_CSR_SFTRSTF_MSK
-#define STM32_RCC_CSR_IWDGRSTF_POS 29U
-#define STM32_RCC_CSR_IWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_IWDGRSTF_POS)
-#define STM32_RCC_CSR_IWDGRSTF STM32_RCC_CSR_IWDGRSTF_MSK
-#define STM32_RCC_CSR_WWDGRSTF_POS 30U
-#define STM32_RCC_CSR_WWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_WWDGRSTF_POS)
-#define STM32_RCC_CSR_WWDGRSTF STM32_RCC_CSR_WWDGRSTF_MSK
-#define STM32_RCC_CSR_LPWRRSTF_POS 31U
-#define STM32_RCC_CSR_LPWRRSTF_MSK (0x1UL << STM32_RCC_CSR_LPWRRSTF_POS)
-#define STM32_RCC_CSR_LPWRRSTF STM32_RCC_CSR_LPWRRSTF_MSK
-
-/**************  Bit definition for STM32_RCC_CRRCR register  *****************/
-#define STM32_RCC_CRRCR_HSI48ON_POS 0U
-#define STM32_RCC_CRRCR_HSI48ON_MSK (0x1UL << STM32_RCC_CRRCR_HSI48ON_POS)
-#define STM32_RCC_CRRCR_HSI48ON STM32_RCC_CRRCR_HSI48ON_MSK
-#define STM32_RCC_CRRCR_HSI48RDY_POS 1U
-#define STM32_RCC_CRRCR_HSI48RDY_MSK (0x1UL << STM32_RCC_CRRCR_HSI48RDY_POS)
-#define STM32_RCC_CRRCR_HSI48RDY STM32_RCC_CRRCR_HSI48RDY_MSK
-
-/**************  Bit definition for STM32_RCC_CRRCR2 register  ****************/
-/* TODO */
-
-/**************  Bit definition for STM32_RCC_DLYCFGR register  ***************/
-/* TODO */
-
-/**************  Bit definition for STM32_RCC_CCIPR2 register  ****************/
-/* TODO */
-
-
-/*!< HSI48CAL configuration */
-#define STM32_RCC_CRRCR_HSI48CAL_POS 7U
-#define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL STM32_RCC_CRRCR_HSI48CAL_MSK
-#define STM32_RCC_CRRCR_HSI48CAL_0 (0x001UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_1 (0x002UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_2 (0x004UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_3 (0x008UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_4 (0x010UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_5 (0x020UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_6 (0x040UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_7 (0x080UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-
-#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_I2CFMP(n) BIT(n + 21)
-
-/* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_PWREN			BIT(28)
-
-#define STM32_RCC_PB2_SYSCFGEN		BIT(0)
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-#define STM32_RCC_HB1_DMA1		BIT(0)
-#define STM32_RCC_HB1_DMA2		BIT(1)
-
-#define STM32_RCC_HB2_GPIOA		BIT(0)
-#define STM32_RCC_HB2_GPIOB		BIT(1)
-#define STM32_RCC_HB2_GPIOC		BIT(2)
-#define STM32_RCC_HB2_GPIOD		BIT(3)
-#define STM32_RCC_HB2_GPIOE		BIT(4)
-#define STM32_RCC_HB2_GPIOH		BIT(7)
-#define STM32_RCC_HB2_ADC1		BIT(13)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define  STM32_RCC_RESET_CAUSE	STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xff000000
-#define  RESET_CAUSE_RMVF               BIT(23)
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE			STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR		STM32_PWR_SCR
-#define  RESET_CAUSE_SBF                BIT(8)
-#define  RESET_CAUSE_SBF_CLR            BIT(8)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_WUTE           BIT(10)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_CR_WUTIE          BIT(14)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_WUTWF         BIT(2)
-#define STM32_RTC_ISR_INITS         BIT(4)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_ISR_WUTF          BIT(9)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_RTC_CLEAR_FLAG(x)                         \
-			(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
-					(STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
-
-#define RTC_TR_PM_POS                  22U
-#define RTC_TR_PM_MSK                  (0x1UL << RTC_TR_PM_POS)
-#define RTC_TR_PM                      RTC_TR_PM_MSK
-#define RTC_TR_HT_POS                  20U
-#define RTC_TR_HT_MSK                  (0x3UL << RTC_TR_HT_POS)
-#define RTC_TR_HT                      RTC_TR_HT_MSK
-#define RTC_TR_HU_POS                  16U
-#define RTC_TR_HU_MSK                  (0xFUL << RTC_TR_HU_POS)
-#define RTC_TR_HU                      RTC_TR_HU_MSK
-#define RTC_TR_MNT_POS                 12U
-#define RTC_TR_MNT_MSK                 (0x7UL << RTC_TR_MNT_POS)
-#define RTC_TR_MNT                     RTC_TR_MNT_MSK
-#define RTC_TR_MNU_POS                 8U
-#define RTC_TR_MNU_MSK                 (0xFUL << RTC_TR_MNU_POS)
-#define RTC_TR_MNU                     RTC_TR_MNU_MSK
-#define RTC_TR_ST_POS                  4U
-#define RTC_TR_ST_MSK                  (0x7UL << RTC_TR_ST_POS)
-#define RTC_TR_ST                      RTC_TR_ST_MSK
-#define RTC_TR_SU_POS                  0U
-#define RTC_TR_SU_MSK                  (0xFUL << RTC_TR_SU_POS)
-#define RTC_TR_SU                      RTC_TR_SU_MSK
-
-
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned int sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned int crcpr;
-	unsigned int rxcrcr;
-	unsigned int txcrcr;
-	unsigned int i2scfgr;	/* STM32L only */
-	unsigned int i2spr;	/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x20)
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_ERR_MASK          (0xc3fa)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x28)
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0xff) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0xff)
-#define STM32_FLASH_ECCR            REG32(STM32_FLASH_REGS_BASE + 0x30)
-#define STM32_FLASH_OPTR            REG32(STM32_FLASH_REGS_BASE + 0x40)
-#define STM32_FLASH_WRP1AR          REG32(STM32_FLASH_REGS_BASE + 0x58)
-#define STM32_FLASH_WRP1BR          REG32(STM32_FLASH_REGS_BASE + 0x5C)
-/* Minimum number of bytes that can be written to flash */
-#define STM32_FLASH_MIN_WRITE_SIZE  CONFIG_FLASH_WRITE_SIZE
-
-#define STM32_OPTB_WRP1AR           STM32_FLASH_WRP1AR
-#define STM32_OPTB_WRP1BR           STM32_FLASH_WRP1BR
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT          BIT(18)
-
-/* --- ADC --- */
-#define STM32_ADC1_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC1_ISR_ADRDY        BIT(0)
-#define STM32_ADC1_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC1_IER_AWDIE        BIT(7)
-#define STM32_ADC1_IER_OVRIE        BIT(4)
-#define STM32_ADC1_IER_EOSEQIE      BIT(3)
-#define STM32_ADC1_IER_EOCIE        BIT(2)
-#define STM32_ADC1_IER_EOSMPIE      BIT(1)
-#define STM32_ADC1_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC1_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC1_CR_ADEN          BIT(0)
-#define STM32_ADC1_CR_ADDIS         BIT(1)
-#define STM32_ADC1_CR_ADSTP         BIT(4)
-#define STM32_ADC1_CR_ADVREGEN      BIT(28)
-#define STM32_ADC1_CR_DEEPPWD	    BIT(29)
-#define STM32_ADC1_CR_ADCAL         BIT(31)
-#define STM32_ADC1_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
-/* Analog watchdog channel selection */
-#define STM32_ADC1_CFGR_AWDCH_MASK  (0x1f << 26)
-#define STM32_ADC1_CFGR_AWDEN       BIT(23)
-#define STM32_ADC1_CFGR_AWDSGL      BIT(22)
-#define STM32_ADC1_CFGR_AUTDLY	    BIT(14)
-/* Selects single vs continuous */
-#define STM32_ADC1_CFGR_CONT        BIT(13)
-/* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC1_CFGR_OVRMOD      BIT(12)
-/* External trigger polarity selection */
-#define STM32_ADC1_CFGR_EXTEN_DIS   (0 << 10)
-#define STM32_ADC1_CFGR_EXTEN_RISE  (1 << 10)
-#define STM32_ADC1_CFGR_EXTEN_FALL  (2 << 10)
-#define STM32_ADC1_CFGR_EXTEN_BOTH  (3 << 10)
-#define STM32_ADC1_CFGR_EXTEN_MASK  (3 << 10)
-#define STM32_ADC1_CFGR_ALIGN	    BIT(5)
-/* External trigger selection */
-#define STM32_ADC1_CFGR_TRG0        (0 << 6)
-#define STM32_ADC1_CFGR_TRG1        (1 << 6)
-#define STM32_ADC1_CFGR_TRG2        (2 << 6)
-#define STM32_ADC1_CFGR_TRG3        (3 << 6)
-#define STM32_ADC1_CFGR_TRG4        (4 << 6)
-#define STM32_ADC1_CFGR_TRG5        (5 << 6)
-#define STM32_ADC1_CFGR_TRG6        (6 << 6)
-#define STM32_ADC1_CFGR_TRG7        (7 << 6)
-#define STM32_ADC1_CFGR_TRG_MASK    (7 << 6)
-/* Selects circular vs one-shot */
-#define STM32_ADC1_CFGR_DMACFG      BIT(1)
-#define STM32_ADC1_CFGR_DMAEN       BIT(0)
-#define STM32_ADC1_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC1_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC1_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
-/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC1_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC1_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC1_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC1_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC1_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC1_JDR1             REG32(STM32_ADC1_BASE + 0x80)
-#define STM32_ADC1_JDR2             REG32(STM32_ADC1_BASE + 0x84)
-#define STM32_ADC1_JDR3             REG32(STM32_ADC1_BASE + 0x88)
-#define STM32_ADC1_JDR4             REG32(STM32_ADC1_BASE + 0x8C)
-#define STM32_ADC1_CCR              REG32(STM32_ADC1_BASE + 0x308)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-#define STM32_USB_BCDR_DPPU	    BIT(15)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-	STM32_DMAC_CH15 = 14,
-
-	/* Channel functions */
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH14,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH15,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
-	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
-	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
-	STM32_DMAC_COUNT = 15,
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-#endif /* !__ASSEMBLER__ */
-
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
deleted file mode 100644
index 74a195a54e..0000000000
--- a/chip/stm32/registers.h
+++ /dev/null
@@ -1,492 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32 family of chips
- *
- * This header file should only contain register definitions and
- * functionality that are common to all STM32 chips.
- * Any chip/family specific macros must be placed in their family
- * specific registers file, which is conditionally included at the
- * end of this file.
- * Include this file directly for all STM32 register definitions.
- *
- * ### History and Reasoning ###
- * In a time before chip family register file separation,
- * long long ago, there lived a single file called `registers.h`,
- * which housed register definitions for all STM32 chip family and variants.
- * This poor file was 3000 lines of register macros and C definitions,
- * swiss-cheesed by nested preprocessor conditional logic.
- * Adding a single new chip variant required splitting multiple,
- * already nested, conditional sections throughout the file.
- * Readability was on the difficult side and refactoring was dangerous.
- *
- * The number of STM32 variants had outgrown the single registers file model.
- * The minor gains of sharing a set of registers between a subset of chip
- * variants no longer outweighed the complexity of the following operations:
- * - Adding a new chip variant or variant feature
- * - Determining if a register was properly setup for a variant or if it
- *   was simply not unset
- *
- * To strike a balance between shared registers and chip specific registers,
- * the registers.h file remains a place for common definitions, but family
- * specific definitions were moved to their own files.
- * These family specific files contain a much reduced level of preprocessor
- * logic for variant specific registers.
- *
- * See https://crrev.com/c/1674679 to witness the separation steps.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_BASE(n)           CONCAT3(STM32_USART, n, _BASE)
-#define STM32_USART_REG(base, offset) REG32((base) + (offset))
-
-#define STM32_IRQ_USART(n)         CONCAT2(STM32_IRQ_USART, n)
-
-/* --- TIMERS --- */
-#define STM32_TIM_BASE(n)          CONCAT3(STM32_TIM, n, _BASE)
-
-#define STM32_TIM_REG(n, offset) \
-		REG16(STM32_TIM_BASE(n) + (offset))
-#define STM32_TIM_REG32(n, offset) \
-		REG32(STM32_TIM_BASE(n) + (offset))
-
-#define STM32_TIM_CR1(n)           STM32_TIM_REG(n, 0x00)
-#define STM32_TIM_CR1_CEN		BIT(0)
-#define STM32_TIM_CR2(n)           STM32_TIM_REG(n, 0x04)
-#define STM32_TIM_SMCR(n)          STM32_TIM_REG(n, 0x08)
-#define STM32_TIM_DIER(n)          STM32_TIM_REG(n, 0x0C)
-#define STM32_TIM_SR(n)            STM32_TIM_REG(n, 0x10)
-#define STM32_TIM_EGR(n)           STM32_TIM_REG(n, 0x14)
-#define STM32_TIM_EGR_UG		BIT(0)
-#define STM32_TIM_CCMR1(n)         STM32_TIM_REG(n, 0x18)
-#define STM32_TIM_CCMR1_OC1PE		BIT(2)
-/* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */
-#define STM32_TIM_CCMR1_OC1M(n)    (((n) & 0x7) << 4)
-#define STM32_TIM_CCMR1_OC1M_MASK              STM32_TIM_CCMR1_OC1M(~0)
-#define STM32_TIM_CCMR1_OC1M_FROZEN            STM32_TIM_CCMR1_OC1M(0x0)
-#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH   STM32_TIM_CCMR1_OC1M(0x1)
-#define STM32_TIM_CCMR1_OC1M_INACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x2)
-#define STM32_TIM_CCMR1_OC1M_TOGGLE            STM32_TIM_CCMR1_OC1M(0x3)
-#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE    STM32_TIM_CCMR1_OC1M(0x4)
-#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE      STM32_TIM_CCMR1_OC1M(0x5)
-#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1        STM32_TIM_CCMR1_OC1M(0x6)
-#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2        STM32_TIM_CCMR1_OC1M(0x7)
-#define STM32_TIM_CCMR2(n)         STM32_TIM_REG(n, 0x1C)
-#define STM32_TIM_CCER(n)          STM32_TIM_REG(n, 0x20)
-#define STM32_TIM_CCER_CC1E		BIT(0)
-#define STM32_TIM_CCER_CC1P		BIT(1)
-#define STM32_TIM_CCER_CC1NE		BIT(2)
-#define STM32_TIM_CCER_CC1NP		BIT(3)
-#define STM32_TIM_CNT(n)           STM32_TIM_REG(n, 0x24)
-#define STM32_TIM_PSC(n)           STM32_TIM_REG(n, 0x28)
-#define STM32_TIM_ARR(n)           STM32_TIM_REG(n, 0x2C)
-#define STM32_TIM_RCR(n)           STM32_TIM_REG(n, 0x30)
-#define STM32_TIM_CCR1(n)          STM32_TIM_REG(n, 0x34)
-#define STM32_TIM_CCR2(n)          STM32_TIM_REG(n, 0x38)
-#define STM32_TIM_CCR3(n)          STM32_TIM_REG(n, 0x3C)
-#define STM32_TIM_CCR4(n)          STM32_TIM_REG(n, 0x40)
-#define STM32_TIM_BDTR(n)          STM32_TIM_REG(n, 0x44)
-#define STM32_TIM_BDTR_MOE		BIT(15)
-#define STM32_TIM_DCR(n)           STM32_TIM_REG(n, 0x48)
-#define STM32_TIM_DMAR(n)          STM32_TIM_REG(n, 0x4C)
-#define STM32_TIM_OR(n)            STM32_TIM_REG(n, 0x50)
-
-#define STM32_TIM_CCRx(n, x)       STM32_TIM_REG(n, 0x34 + ((x) - 1) * 4)
-
-#define STM32_TIM32_CNT(n)         STM32_TIM_REG32(n, 0x24)
-#define STM32_TIM32_ARR(n)         STM32_TIM_REG32(n, 0x2C)
-#define STM32_TIM32_CCR1(n)        STM32_TIM_REG32(n, 0x34)
-#define STM32_TIM32_CCR2(n)        STM32_TIM_REG32(n, 0x38)
-#define STM32_TIM32_CCR3(n)        STM32_TIM_REG32(n, 0x3C)
-#define STM32_TIM32_CCR4(n)        STM32_TIM_REG32(n, 0x40)
-/* Timer registers as struct */
-struct timer_ctlr {
-	unsigned cr1;
-	unsigned cr2;
-	unsigned smcr;
-	unsigned dier;
-
-	unsigned sr;
-	unsigned egr;
-	unsigned ccmr1;
-	unsigned ccmr2;
-
-	unsigned ccer;
-	unsigned cnt;
-	unsigned psc;
-	unsigned arr;
-
-	unsigned ccr[5]; /* ccr[0] = reserved30 */
-
-	unsigned bdtr;
-	unsigned dcr;
-	unsigned dmar;
-
-	unsigned option_register;
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct timer_ctlr timer_ctlr_t;
-
-/* --- Low power timers --- */
-#define STM32_LPTIM_BASE(n)          CONCAT3(STM32_LPTIM, n, _BASE)
-
-#define STM32_LPTIM_REG(n, offset)   REG32(STM32_LPTIM_BASE(n) + (offset))
-
-#define STM32_LPTIM_ISR(n)           STM32_LPTIM_REG(n, 0x00)
-#define STM32_LPTIM_ICR(n)           STM32_LPTIM_REG(n, 0x04)
-#define STM32_LPTIM_IER(n)           STM32_LPTIM_REG(n, 0x08)
-#define STM32_LPTIM_INT_DOWN		BIT(6)
-#define STM32_LPTIM_INT_UP		BIT(5)
-#define STM32_LPTIM_INT_ARROK		BIT(4)
-#define STM32_LPTIM_INT_CMPOK		BIT(3)
-#define STM32_LPTIM_INT_EXTTRIG		BIT(2)
-#define STM32_LPTIM_INT_ARRM		BIT(1)
-#define STM32_LPTIM_INT_CMPM		BIT(0)
-#define STM32_LPTIM_CFGR(n)          STM32_LPTIM_REG(n, 0x0C)
-#define STM32_LPTIM_CR(n)            STM32_LPTIM_REG(n, 0x10)
-#define STM32_LPTIM_CR_RSTARE		BIT(4)
-#define STM32_LPTIM_CR_COUNTRST		BIT(3)
-#define STM32_LPTIM_CR_CNTSTRT		BIT(2)
-#define STM32_LPTIM_CR_SNGSTRT		BIT(1)
-#define STM32_LPTIM_CR_ENABLE		BIT(0)
-#define STM32_LPTIM_CMP(n)           STM32_LPTIM_REG(n, 0x14)
-#define STM32_LPTIM_ARR(n)           STM32_LPTIM_REG(n, 0x18)
-#define STM32_LPTIM_CNT(n)           STM32_LPTIM_REG(n, 0x1C)
-#define STM32_LPTIM_CFGR2(n)         STM32_LPTIM_REG(n, 0x24)
-
-/* --- GPIO --- */
-
-#define GPIO_A                       STM32_GPIOA_BASE
-#define GPIO_B                       STM32_GPIOB_BASE
-#define GPIO_C                       STM32_GPIOC_BASE
-#define GPIO_D                       STM32_GPIOD_BASE
-#define GPIO_E                       STM32_GPIOE_BASE
-#define GPIO_F                       STM32_GPIOF_BASE
-#define GPIO_G                       STM32_GPIOG_BASE
-#define GPIO_H                       STM32_GPIOH_BASE
-#define GPIO_I                       STM32_GPIOI_BASE
-#define GPIO_J                       STM32_GPIOJ_BASE
-#define GPIO_K                       STM32_GPIOK_BASE
-
-#define UNIMPLEMENTED_GPIO_BANK GPIO_A
-
-
-/* --- I2C --- */
-#define STM32_I2C1_PORT             0
-#define STM32_I2C2_PORT             1
-#define STM32_I2C3_PORT             2
-#define STM32_FMPI2C4_PORT          3
-
-#define stm32_i2c_reg(port, offset) \
-	((uint16_t *)((STM32_I2C1_BASE + ((port) * 0x400)) + (offset)))
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR                REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR_LPSDSR		(1 << 0)
-#define STM32_PWR_CR_FLPS		(1 << 9)
-#define STM32_PWR_CR_SVOS5		(1 << 14)
-#define STM32_PWR_CR_SVOS4		(2 << 14)
-#define STM32_PWR_CR_SVOS3		(3 << 14)
-#define STM32_PWR_CR_SVOS_MASK		(3 << 14)
-
-/* RTC domain control register */
-#define STM32_RCC_BDCR_BDRST		BIT(16)
-#define STM32_RCC_BDCR_RTCEN		BIT(15)
-#define STM32_RCC_BDCR_LSERDY		BIT(1)
-#define STM32_RCC_BDCR_LSEON		BIT(0)
-#define  BDCR_RTCSEL_MASK		((0x3) << 8)
-#define  BDCR_RTCSEL(source)		(((source) << 8) & BDCR_RTCSEL_MASK)
-#define  BDCR_SRC_LSE			0x1
-#define  BDCR_SRC_LSI			0x2
-#define  BDCR_SRC_HSE			0x3
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_TIM2		BIT(0)
-#define STM32_RCC_PB1_TIM3		BIT(1)
-#define STM32_RCC_PB1_TIM4		BIT(2)
-#define STM32_RCC_PB1_TIM5		BIT(3)
-#define STM32_RCC_PB1_TIM6		BIT(4)
-#define STM32_RCC_PB1_TIM7		BIT(5)
-#define STM32_RCC_PB1_TIM12             BIT(6) /* STM32H7 */
-#define STM32_RCC_PB1_TIM13             BIT(7) /* STM32H7 */
-#define STM32_RCC_PB1_TIM14             BIT(8) /* STM32H7 */
-#define STM32_RCC_PB1_RTC		BIT(10) /* DBGMCU only */
-#define STM32_RCC_PB1_WWDG		BIT(11)
-#define STM32_RCC_PB1_IWDG		BIT(12) /* DBGMCU only */
-#define STM32_RCC_PB1_SPI2		BIT(14)
-#define STM32_RCC_PB1_SPI3		BIT(15)
-#define STM32_RCC_PB1_USART2		BIT(17)
-#define STM32_RCC_PB1_USART3		BIT(18)
-#define STM32_RCC_PB1_USART4		BIT(19)
-#define STM32_RCC_PB1_USART5		BIT(20)
-#define STM32_RCC_PB1_PWREN		BIT(28)
-#define STM32_RCC_PB2_SPI1		BIT(12)
-/* Reset causes definitions */
-
-/* --- Watchdogs --- */
-
-#define STM32_WWDG_CR               REG32(STM32_WWDG_BASE + 0x00)
-#define STM32_WWDG_CFR              REG32(STM32_WWDG_BASE + 0x04)
-#define STM32_WWDG_SR               REG32(STM32_WWDG_BASE + 0x08)
-
-#define STM32_WWDG_TB_8             (3 << 7)
-#define STM32_WWDG_EWI              BIT(9)
-
-#define STM32_IWDG_KR               REG32(STM32_IWDG_BASE + 0x00)
-#define STM32_IWDG_KR_UNLOCK		0x5555
-#define STM32_IWDG_KR_RELOAD		0xaaaa
-#define STM32_IWDG_KR_START		0xcccc
-#define STM32_IWDG_PR               REG32(STM32_IWDG_BASE + 0x04)
-#define STM32_IWDG_RLR              REG32(STM32_IWDG_BASE + 0x08)
-#define STM32_IWDG_RLR_MAX		0x0fff
-#define STM32_IWDG_SR               REG32(STM32_IWDG_BASE + 0x0C)
-#define STM32_IWDG_SR_WVU		BIT(2)
-#define STM32_IWDG_SR_RVU		BIT(1)
-#define STM32_IWDG_SR_PVU		BIT(0)
-#define STM32_IWDG_WINR             REG32(STM32_IWDG_BASE + 0x10)
-
-/* --- Real-Time Clock --- */
-/* --- Debug --- */
-#define STM32_DBGMCU_IDCODE         REG32(STM32_DBGMCU_BASE + 0x00)
-#define STM32_DBGMCU_CR             REG32(STM32_DBGMCU_BASE + 0x04)
-/* --- Routing interface --- */
-/* STM32L1xx only */
-#define STM32_RI_ICR                REG32(STM32_COMP_BASE + 0x04)
-#define STM32_RI_ASCR1              REG32(STM32_COMP_BASE + 0x08)
-#define STM32_RI_ASCR2              REG32(STM32_COMP_BASE + 0x0C)
-#define STM32_RI_HYSCR1             REG32(STM32_COMP_BASE + 0x10)
-#define STM32_RI_HYSCR2             REG32(STM32_COMP_BASE + 0x14)
-#define STM32_RI_HYSCR3             REG32(STM32_COMP_BASE + 0x18)
-#define STM32_RI_AMSR1              REG32(STM32_COMP_BASE + 0x1C)
-#define STM32_RI_CMR1               REG32(STM32_COMP_BASE + 0x20)
-#define STM32_RI_CICR1              REG32(STM32_COMP_BASE + 0x24)
-#define STM32_RI_AMSR2              REG32(STM32_COMP_BASE + 0x28)
-#define STM32_RI_CMR2               REG32(STM32_COMP_BASE + 0x30)
-#define STM32_RI_CICR2              REG32(STM32_COMP_BASE + 0x34)
-#define STM32_RI_AMSR3              REG32(STM32_COMP_BASE + 0x38)
-#define STM32_RI_CMR3               REG32(STM32_COMP_BASE + 0x3C)
-#define STM32_RI_CICR3              REG32(STM32_COMP_BASE + 0x40)
-#define STM32_RI_AMSR4              REG32(STM32_COMP_BASE + 0x44)
-#define STM32_RI_CMR4               REG32(STM32_COMP_BASE + 0x48)
-#define STM32_RI_CICR4              REG32(STM32_COMP_BASE + 0x4C)
-#define STM32_RI_AMSR5              REG32(STM32_COMP_BASE + 0x50)
-#define STM32_RI_CMR5               REG32(STM32_COMP_BASE + 0x54)
-#define STM32_RI_CICR5              REG32(STM32_COMP_BASE + 0x58)
-
-/* --- DAC --- */
-#define STM32_DAC_CR               REG32(STM32_DAC_BASE + 0x00)
-#define STM32_DAC_SWTRIGR          REG32(STM32_DAC_BASE + 0x04)
-#define STM32_DAC_DHR12R1          REG32(STM32_DAC_BASE + 0x08)
-#define STM32_DAC_DHR12L1          REG32(STM32_DAC_BASE + 0x0C)
-#define STM32_DAC_DHR8R1           REG32(STM32_DAC_BASE + 0x10)
-#define STM32_DAC_DHR12R2          REG32(STM32_DAC_BASE + 0x14)
-#define STM32_DAC_DHR12L2          REG32(STM32_DAC_BASE + 0x18)
-#define STM32_DAC_DHR8R2           REG32(STM32_DAC_BASE + 0x1C)
-#define STM32_DAC_DHR12RD          REG32(STM32_DAC_BASE + 0x20)
-#define STM32_DAC_DHR12LD          REG32(STM32_DAC_BASE + 0x24)
-#define STM32_DAC_DHR8RD           REG32(STM32_DAC_BASE + 0x28)
-#define STM32_DAC_DOR1             REG32(STM32_DAC_BASE + 0x2C)
-#define STM32_DAC_DOR2             REG32(STM32_DAC_BASE + 0x30)
-#define STM32_DAC_SR               REG32(STM32_DAC_BASE + 0x34)
-
-#define STM32_DAC_CR_DMAEN2        BIT(28)
-#define STM32_DAC_CR_TSEL2_SWTRG   (7 << 19)
-#define STM32_DAC_CR_TSEL2_TMR4    (5 << 19)
-#define STM32_DAC_CR_TSEL2_TMR2    (4 << 19)
-#define STM32_DAC_CR_TSEL2_TMR9    (3 << 19)
-#define STM32_DAC_CR_TSEL2_TMR7    (2 << 19)
-#define STM32_DAC_CR_TSEL2_TMR6    (0 << 19)
-#define STM32_DAC_CR_TSEL2_MASK    (7 << 19)
-#define STM32_DAC_CR_TEN2          BIT(18)
-#define STM32_DAC_CR_BOFF2         BIT(17)
-#define STM32_DAC_CR_EN2           BIT(16)
-#define STM32_DAC_CR_DMAEN1        BIT(12)
-#define STM32_DAC_CR_TSEL1_SWTRG   (7 << 3)
-#define STM32_DAC_CR_TSEL1_TMR4    (5 << 3)
-#define STM32_DAC_CR_TSEL1_TMR2    (4 << 3)
-#define STM32_DAC_CR_TSEL1_TMR9    (3 << 3)
-#define STM32_DAC_CR_TSEL1_TMR7    (2 << 3)
-#define STM32_DAC_CR_TSEL1_TMR6    (0 << 3)
-#define STM32_DAC_CR_TSEL1_MASK    (7 << 3)
-#define STM32_DAC_CR_TEN1          BIT(2)
-#define STM32_DAC_CR_BOFF1         BIT(1)
-#define STM32_DAC_CR_EN1           BIT(0)
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK  (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-#define EP_TX_RX_NAK   (EP_TX_NAK | EP_RX_NAK)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN		BIT(2)
-#define STM32_RNG_CR_IE			BIT(3)
-#define STM32_RNG_CR_CED		BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY		BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
-
-#if defined(CHIP_FAMILY_STM32F0)
-#include "registers-stm32f0.h"
-#elif defined(CHIP_FAMILY_STM32F3)
-#include "registers-stm32f3.h"
-#elif defined(CHIP_FAMILY_STM32F4)
-#include "registers-stm32f4.h"
-#elif defined(CHIP_FAMILY_STM32F7)
-#include "registers-stm32f7.h"
-#elif defined(CHIP_FAMILY_STM32G4)
-#include "registers-stm32g4.h"
-#elif defined(CHIP_FAMILY_STM32H7)
-#include "registers-stm32h7.h"
-#elif defined(CHIP_FAMILY_STM32L)
-#include "registers-stm32l.h"
-#elif defined(CHIP_FAMILY_STM32L4)
-#include "registers-stm32l4.h"
-#elif defined(CHIP_FAMILY_STM32L5)
-#include "registers-stm32l5.h"
-#else
-#error "Unsupported chip family"
-#endif
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
deleted file mode 100644
index 3dbbbc4fa9..0000000000
--- a/chip/stm32/spi.c
+++ /dev/null
@@ -1,747 +0,0 @@
-/*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI driver for Chrome EC.
- *
- * This uses DMA to handle transmission and reception.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "spi.h"
-#include "stm32-dma.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-
-/* SPI FIFO registers */
-#ifdef CHIP_FAMILY_STM32H7
-#define SPI_TXDR REG8(&STM32_SPI1_REGS->txdr)
-#define SPI_RXDR REG8(&STM32_SPI1_REGS->rxdr)
-#else
-#define SPI_TXDR STM32_SPI1_REGS->dr
-#define SPI_RXDR STM32_SPI1_REGS->dr
-#endif
-
-/* DMA channel option */
-static const struct dma_option dma_tx_option = {
-	STM32_DMAC_SPI1_TX, (void *)&SPI_TXDR,
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-#ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH)
-#endif
-};
-
-static const struct dma_option dma_rx_option = {
-	STM32_DMAC_SPI1_RX, (void *)&SPI_RXDR,
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-#ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH)
-#endif
-};
-
-/*
- * Timeout to wait for SPI request packet
- *
- * This affects the slowest SPI clock we can support.  A delay of 8192 us
- * permits a 512-byte request at 500 KHz, assuming the master starts sending
- * bytes as soon as it asserts chip select.  That's as slow as we would
- * practically want to run the SPI interface, since running it slower
- * significantly impacts firmware update times.
- */
-#define SPI_CMD_RX_TIMEOUT_US 8192
-
-#ifdef CONFIG_SPI_PROTOCOL_V2
-/*
- * Offset of output parameters needs to account for pad and framing bytes and
- * one last past-end byte at the end so any additional bytes clocked out by
- * the AP will have a known and identifiable value.
- */
-#define SPI_PROTO2_OFFSET (EC_PROTO2_RESPONSE_HEADER_BYTES + 2)
-#define SPI_PROTO2_OVERHEAD (SPI_PROTO2_OFFSET +		\
-			     EC_PROTO2_RESPONSE_TRAILER_BYTES + 1)
-#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
-/*
- * Max data size for a version 3 request/response packet.  This is big enough
- * to handle a request/response header, flash write offset/size, and 512 bytes
- * of flash data.
- */
-#define SPI_MAX_REQUEST_SIZE 0x220
-#define SPI_MAX_RESPONSE_SIZE 0x220
-
-/*
- * The AP blindly clocks back bytes over the SPI interface looking for a
- * framing byte.  So this preamble must always precede the actual response
- * packet.  Search for "spi-frame-header" in U-boot to see how that's
- * implemented.
- *
- * The preamble must be 32-bit aligned so that the response buffer is also
- * 32-bit aligned.
- */
-static const uint8_t out_preamble[4] = {
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_FRAME_START,  /* This is the byte which matters */
-};
-
-/*
- * Space allocation of the past-end status byte (EC_SPI_PAST_END) in the out_msg
- * buffer. This seems to be dynamic because the F0 family needs to send it 4
- * times in order to make sure it actually stays at the repeating byte after DMA
- * ends.
- *
- * See crosbug.com/p/31390
- */
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-#define EC_SPI_PAST_END_LENGTH 4
-#else
-#define EC_SPI_PAST_END_LENGTH 1
-#endif
-
-/*
- * Our input and output buffers. These must be large enough for our largest
- * message, including protocol overhead, and must be 32-bit aligned.
- */
-static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble) +
-	EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached;
-static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4) __uncached;
-static uint8_t enabled;
-#ifdef CONFIG_SPI_PROTOCOL_V2
-static struct host_cmd_handler_args args;
-#endif
-static struct host_packet spi_packet;
-
-/*
- * This is set if SPI NSS raises to high while EC is still processing a
- * command.
- */
-static int setup_transaction_later;
-
-enum spi_state {
-	/* SPI not enabled (initial state, and when chipset is off) */
-	SPI_STATE_DISABLED = 0,
-
-	/* Setting up receive DMA */
-	SPI_STATE_PREPARE_RX,
-
-	/* Ready to receive next request */
-	SPI_STATE_READY_TO_RX,
-
-	/* Receiving request */
-	SPI_STATE_RECEIVING,
-
-	/* Processing request */
-	SPI_STATE_PROCESSING,
-
-	/* Sending response */
-	SPI_STATE_SENDING,
-
-	/*
-	 * Received bad data - transaction started before we were ready, or
-	 * packet header from host didn't parse properly.  Ignoring received
-	 * data.
-	 */
-	SPI_STATE_RX_BAD,
-} state;
-
-/**
- * Wait until we have received a certain number of bytes
- *
- * Watch the DMA receive channel until it has the required number of bytes,
- * or a timeout occurs
- *
- * We keep an eye on the NSS line - if this goes high then the transaction is
- * over so there is no point in trying to receive the bytes.
- *
- * @param rxdma		RX DMA channel to watch
- * @param needed	Number of bytes that are needed
- * @param nss		GPIO signal for NSS control line
- * @return 0 if bytes received, -1 if we hit a timeout or NSS went high
- */
-static int wait_for_bytes(dma_chan_t *rxdma, int needed,
-			  enum gpio_signal nss)
-{
-	timestamp_t deadline;
-
-	ASSERT(needed <= sizeof(in_msg));
-	deadline.val = 0;
-	while (1) {
-		if (dma_bytes_done(rxdma, sizeof(in_msg)) >= needed)
-			return 0;
-		if (gpio_get_level(nss))
-			return -1;
-		if (!deadline.val) {
-			deadline = get_time();
-			deadline.val += SPI_CMD_RX_TIMEOUT_US;
-		}
-		if (timestamp_expired(deadline, NULL))
-			return -1;
-	}
-}
-
-#ifdef CONFIG_SPI_PROTOCOL_V2
-/**
- * Send a reply on a given port.
- *
- * The format of a reply is as per the command interface, with a number of
- * preamble bytes before it.
- *
- * The format of a reply is a sequence of bytes:
- *
- * <hdr> <status> <len> <msg bytes> <sum> [<preamble byte>...]
- *
- * The hdr byte is just a tag to indicate that the real message follows. It
- * signals the end of any preamble required by the interface.
- *
- * The length is the entire packet size, including the header, length bytes,
- * message payload, checksum, and postamble byte.
- *
- * The preamble is at least 2 bytes, but can be longer if the STM takes ages
- * to react to the incoming message. Since we send our first byte as the AP
- * sends us the command, we clearly can't send anything sensible for that
- * byte. The second byte must be written to the output register just when the
- * command byte is ready (I think), so we can't do anything there either.
- * Any processing we do may increase this delay. That's the reason for the
- * preamble.
- *
- * It is interesting to note that it seems to be possible to run the SPI
- * interface faster than the CPU clock with this approach.
- *
- * We keep an eye on the NSS line - if this goes high then the transaction is
- * over so there is no point in trying to send the reply.
- *
- * @param txdma		TX DMA channel to send on
- * @param status	Status result to send
- * @param msg_ptr	Message payload to send, which normally starts
- *			SPI_PROTO2_OFFSET bytes into out_msg
- * @param msg_len	Number of message bytes to send
- */
-static void reply(dma_chan_t *txdma,
-		  enum ec_status status, char *msg_ptr, int msg_len)
-{
-	char *msg = out_msg;
-	int need_copy = msg_ptr != msg + SPI_PROTO2_OFFSET;
-	int sum, i;
-
-	ASSERT(msg_len + SPI_PROTO2_OVERHEAD <= sizeof(out_msg));
-
-	/* Add our header bytes - the first one might not actually be sent */
-	msg[0] = EC_SPI_PROCESSING;
-	msg[1] = EC_SPI_FRAME_START;
-	msg[2] = status;
-	msg[3] = msg_len & 0xff;
-
-	/*
-	 * Calculate the checksum; includes the status and message length bytes
-	 * but not the pad and framing bytes since those are stripped by the AP
-	 * driver.
-	 */
-	sum = status + msg_len;
-	for (i = 0; i < msg_len; i++) {
-		int ch = msg_ptr[i];
-		sum += ch;
-		if (need_copy)
-			msg[i + SPI_PROTO2_OFFSET] = ch;
-	}
-
-	/* Add the checksum and get ready to send */
-	msg[SPI_PROTO2_OFFSET + msg_len] = sum & 0xff;
-	msg[SPI_PROTO2_OFFSET + msg_len + 1] = EC_SPI_PAST_END;
-	dma_prepare_tx(&dma_tx_option, msg_len + SPI_PROTO2_OVERHEAD, msg);
-
-	/* Kick off the DMA to send the data */
-	dma_go(txdma);
-}
-#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
-
-/**
- * Sends a byte over SPI without DMA
- *
- * This is mostly used when we want to relay status bytes to the AP while we're
- * receiving the message and we're thinking about it.
- *
- * @note It may be sent 0, 1, or >1 times, depending on whether the host clocks
- * the bus or not. Basically, the EC is saying "if you ask me what my status is,
- * you'll get this value.  But you're not required to ask, or you can ask
- * multiple times."
- *
- * @param byte	status byte to send, one of the EC_SPI_* #defines from
- *		ec_commands.h
- */
-static void tx_status(uint8_t byte)
-{
-	stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS;
-
-	SPI_TXDR = byte;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-	/* It sends the byte 4 times in order to be sure it bypassed the FIFO
-	 * from the STM32F0 line.
-	 */
-	spi->dr = byte;
-	spi->dr = byte;
-	spi->dr = byte;
-#elif defined(CHIP_FAMILY_STM32H7)
-	spi->udrdr = byte;
-#endif
-}
-
-/**
- * Get ready to receive a message from the master.
- *
- * Set up our RX DMA and disable our TX DMA. Set up the data output so that
- * we will send preamble bytes.
- */
-static void setup_for_transaction(void)
-{
-	stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS;
-	volatile uint8_t unused __attribute__((unused));
-
-	/* clear this as soon as possible */
-	setup_transaction_later = 0;
-
-#ifndef CHIP_FAMILY_STM32H7 /* H7 is not ready to set status here */
-	/* Not ready to receive yet */
-	tx_status(EC_SPI_NOT_READY);
-#endif
-
-	/* We are no longer actively processing a transaction */
-	state = SPI_STATE_PREPARE_RX;
-
-	/* Stop sending response, if any */
-	dma_disable(STM32_DMAC_SPI1_TX);
-
-	/*
-	 * Read unused bytes in case there are some pending; this prevents the
-	 * receive DMA from getting that byte right when we start it.
-	 */
-	unused = SPI_RXDR;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-	/* 4 Bytes makes sure the RX FIFO on the F0 is empty as well. */
-	unused = spi->dr;
-	unused = spi->dr;
-	unused = spi->dr;
-#endif
-
-	/* Start DMA */
-	dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg);
-
-	/* Ready to receive */
-	state = SPI_STATE_READY_TO_RX;
-	tx_status(EC_SPI_OLD_READY);
-
-#ifdef CHIP_FAMILY_STM32H7
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-#endif
-}
-
-/* Forward declaration */
-static void spi_init(void);
-
-/*
- * If a setup_for_transaction() was postponed, call it now.
- * Note that setup_for_transaction() cancels Tx DMA.
- */
-static void check_setup_transaction_later(void)
-{
-	if (setup_transaction_later) {
-		spi_init(); /* Fix for bug chrome-os-partner:31390 */
-		/*
-		 * 'state' is set to SPI_STATE_READY_TO_RX. Somehow AP
-		 * de-asserted the SPI NSS during the handler was running.
-		 * Thus, the pending result will be dropped anyway.
-		 */
-	}
-}
-
-#ifdef CONFIG_SPI_PROTOCOL_V2
-/**
- * Called for V2 protocol to indicate that a command has completed
- *
- * Some commands can continue for a while. This function is called by
- * host_command when it completes.
- *
- */
-static void spi_send_response(struct host_cmd_handler_args *args)
-{
-	enum ec_status result = args->result;
-	dma_chan_t *txdma;
-
-	/*
-	 * If we're not processing, then the AP has already terminated the
-	 * transaction, and won't be listening for a response.
-	 */
-	if (state != SPI_STATE_PROCESSING)
-		return;
-
-	/* state == SPI_STATE_PROCESSING */
-
-	if (args->response_size > args->response_max)
-		result = EC_RES_INVALID_RESPONSE;
-
-	/* Transmit the reply */
-	txdma = dma_get_channel(STM32_DMAC_SPI1_TX);
-	reply(txdma, result, args->response, args->response_size);
-
-	/*
-	 * Before the state is set to SENDING, any CS de-assertion would
-	 * set setup_transaction_later to 1.
-	 */
-	state = SPI_STATE_SENDING;
-	check_setup_transaction_later();
-}
-#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
-
-/**
- * Called to send a response back to the host.
- *
- * Some commands can continue for a while. This function is called by
- * host_command when it completes.
- *
- */
-static void spi_send_response_packet(struct host_packet *pkt)
-{
-	dma_chan_t *txdma;
-
-	/*
-	 * If we're not processing, then the AP has already terminated the
-	 * transaction, and won't be listening for a response.
-	 */
-	if (state != SPI_STATE_PROCESSING)
-		return;
-
-	/* state == SPI_STATE_PROCESSING */
-
-	/* Append our past-end byte, which we reserved space for. */
-	((uint8_t *)pkt->response)[pkt->response_size + 0] = EC_SPI_PAST_END;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-	/* Make sure we are going to be outputting it properly when the DMA
-	 * ends due to the TX FIFO bug on the F0. See crosbug.com/p/31390
-	 */
-	((uint8_t *)pkt->response)[pkt->response_size + 1] = EC_SPI_PAST_END;
-	((uint8_t *)pkt->response)[pkt->response_size + 2] = EC_SPI_PAST_END;
-	((uint8_t *)pkt->response)[pkt->response_size + 3] = EC_SPI_PAST_END;
-#endif
-
-	/* Transmit the reply */
-	txdma = dma_get_channel(STM32_DMAC_SPI1_TX);
-	dma_prepare_tx(&dma_tx_option, sizeof(out_preamble) + pkt->response_size
-		+ EC_SPI_PAST_END_LENGTH, out_msg);
-	dma_go(txdma);
-#ifdef CHIP_FAMILY_STM32H7
-	/* clear any previous underrun */
-	STM32_SPI1_REGS->ifcr = STM32_SPI_SR_UDR;
-#endif /* CHIP_FAMILY_STM32H7 */
-
-	/*
-	 * Before the state is set to SENDING, any CS de-assertion would
-	 * set setup_transaction_later to 1.
-	 */
-	state = SPI_STATE_SENDING;
-	check_setup_transaction_later();
-}
-
-/**
- * Handle an event on the NSS pin
- *
- * A falling edge of NSS indicates that the master is starting a new
- * transaction. A rising edge indicates that we have finished.
- *
- * @param signal	GPIO signal for the NSS pin
- */
-void spi_event(enum gpio_signal signal)
-{
-	dma_chan_t *rxdma;
-	uint16_t i;
-
-	/* If not enabled, ignore glitches on NSS */
-	if (!enabled)
-		return;
-
-	/* Check chip select.  If it's high, the AP ended a transaction. */
-	if (gpio_get_level(GPIO_SPI1_NSS)) {
-		enable_sleep(SLEEP_MASK_SPI);
-
-		/*
-		 * If the buffer is still used by the host command, postpone
-		 * the DMA rx setup.
-		 */
-		if (state == SPI_STATE_PROCESSING) {
-			setup_transaction_later = 1;
-			return;
-		}
-
-		/* Set up for the next transaction */
-		spi_init(); /* Fix for bug chrome-os-partner:31390 */
-		return;
-	}
-	disable_sleep(SLEEP_MASK_SPI);
-
-	/* Chip select is low = asserted */
-	if (state != SPI_STATE_READY_TO_RX) {
-		/*
-		 * AP started a transaction but we weren't ready for it.
-		 * Tell AP we weren't ready, and ignore the received data.
-		 */
-		CPRINTS("SPI not ready");
-		tx_status(EC_SPI_NOT_READY);
-		state = SPI_STATE_RX_BAD;
-		return;
-	}
-
-	/* We're now inside a transaction */
-	state = SPI_STATE_RECEIVING;
-	tx_status(EC_SPI_RECEIVING);
-	rxdma = dma_get_channel(STM32_DMAC_SPI1_RX);
-
-	/* Wait for version, command, length bytes */
-	if (wait_for_bytes(rxdma, 3, GPIO_SPI1_NSS))
-		goto spi_event_error;
-
-	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
-		/* Protocol version 3 */
-		struct ec_host_request *r = (struct ec_host_request *)in_msg;
-		int pkt_size;
-
-		/* Wait for the rest of the command header */
-		if (wait_for_bytes(rxdma, sizeof(*r), GPIO_SPI1_NSS))
-			goto spi_event_error;
-
-		/*
-		 * Check how big the packet should be.  We can't just wait to
-		 * see how much data the host sends, because it will keep
-		 * sending extra data until we respond.
-		 */
-		pkt_size = host_request_expected_size(r);
-		if (pkt_size == 0 || pkt_size > sizeof(in_msg))
-			goto spi_event_error;
-
-		/* Wait for the packet data */
-		if (wait_for_bytes(rxdma, pkt_size, GPIO_SPI1_NSS))
-			goto spi_event_error;
-
-		spi_packet.send_response = spi_send_response_packet;
-
-		spi_packet.request = in_msg;
-		spi_packet.request_temp = NULL;
-		spi_packet.request_max = sizeof(in_msg);
-		spi_packet.request_size = pkt_size;
-
-		/* Response must start with the preamble */
-		memcpy(out_msg, out_preamble, sizeof(out_preamble));
-		spi_packet.response = out_msg + sizeof(out_preamble);
-		/* Reserve space for the preamble and trailing past-end byte */
-		spi_packet.response_max = sizeof(out_msg)
-			- sizeof(out_preamble) - EC_SPI_PAST_END_LENGTH;
-		spi_packet.response_size = 0;
-
-		spi_packet.driver_result = EC_RES_SUCCESS;
-
-		/* Move to processing state */
-		state = SPI_STATE_PROCESSING;
-		tx_status(EC_SPI_PROCESSING);
-
-		host_packet_receive(&spi_packet);
-		return;
-
-	} else if (in_msg[0] >= EC_CMD_VERSION0) {
-#ifdef CONFIG_SPI_PROTOCOL_V2
-		/*
-		 * Protocol version 2
-		 *
-		 * TODO(crosbug.com/p/20257): Remove once kernel supports
-		 * version 3.
-		 */
-
-#ifdef CHIP_FAMILY_STM32F0
-		CPRINTS("WARNING: Protocol version 2 is not supported on the F0"
-			" line due to crosbug.com/p/31390");
-#endif
-
-		args.version = in_msg[0] - EC_CMD_VERSION0;
-		args.command = in_msg[1];
-		args.params_size = in_msg[2];
-
-		/* Wait for parameters */
-		if (wait_for_bytes(rxdma, 3 + args.params_size, GPIO_SPI1_NSS))
-			goto spi_event_error;
-
-		/*
-		 * Params are not 32-bit aligned in protocol version 2.  As a
-		 * workaround, move them to the beginning of the input buffer
-		 * so they are aligned.
-		 */
-		if (args.params_size)
-			memmove(in_msg, in_msg + 3, args.params_size);
-
-		args.params = in_msg;
-		args.send_response = spi_send_response;
-
-		/* Allow room for the header bytes */
-		args.response = out_msg + SPI_PROTO2_OFFSET;
-		args.response_max = sizeof(out_msg) - SPI_PROTO2_OVERHEAD;
-		args.response_size = 0;
-		args.result = EC_RES_SUCCESS;
-
-		/* Move to processing state */
-		state = SPI_STATE_PROCESSING;
-		tx_status(EC_SPI_PROCESSING);
-
-		host_command_received(&args);
-		return;
-#else /* !defined(CONFIG_SPI_PROTOCOL_V2) */
-		/* Protocol version 2 is deprecated. */
-		CPRINTS("ERROR: Protocol V2 is not supported!");
-#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
-	}
-
- spi_event_error:
-	/* Error, timeout, or protocol we can't handle.  Ignore data. */
-	tx_status(EC_SPI_RX_BAD_DATA);
-	state = SPI_STATE_RX_BAD;
-	CPRINTS("SPI rx bad data");
-
-	CPRINTF("in_msg=[");
-	for (i = 0; i < dma_bytes_done(rxdma, sizeof(in_msg)); i++)
-		CPRINTF("%02x ", in_msg[i]);
-	CPRINTF("]\n");
-}
-
-static void spi_chipset_startup(void)
-{
-	/* Enable pullup and interrupts on NSS */
-	gpio_set_flags(GPIO_SPI1_NSS, GPIO_INT_BOTH | GPIO_PULL_UP);
-
-	/* Set SPI pins to alternate function */
-	gpio_config_module(MODULE_SPI, 1);
-
-	/* Set up for next transaction */
-	setup_for_transaction();
-
-	enabled = 1;
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, spi_chipset_startup, HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, spi_chipset_startup, HOOK_PRIO_DEFAULT);
-#endif
-
-static void spi_chipset_shutdown(void)
-{
-	enabled = 0;
-	state = SPI_STATE_DISABLED;
-
-	/* Disable pullup and interrupts on NSS */
-	gpio_set_flags(GPIO_SPI1_NSS, GPIO_INPUT);
-
-	/* Set SPI pins to inputs so we don't leak power when AP is off */
-	gpio_config_module(MODULE_SPI, 0);
-
-	/* Allow deep sleep when AP off */
-	enable_sleep(SLEEP_MASK_SPI);
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND_COMPLETE, spi_chipset_shutdown,
-	     HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, spi_chipset_shutdown, HOOK_PRIO_DEFAULT);
-#endif
-
-static void spi_init(void)
-{
-	stm32_spi_regs_t *spi = STM32_SPI1_REGS;
-	uint8_t was_enabled = enabled;
-
-	/* Reset the SPI Peripheral to clear any existing weird states. */
-	/* Fix for bug chrome-os-partner:31390 */
-	enabled = 0;
-	state = SPI_STATE_DISABLED;
-	STM32_RCC_APB2RSTR |= STM32_RCC_PB2_SPI1;
-	STM32_RCC_APB2RSTR &= ~STM32_RCC_PB2_SPI1;
-
-	/* 40 MHz pin speed */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00;
-
-	/* Enable clocks to SPI1 module */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Select the right DMA request for the variants using it.
-	 * This is not required for STM32F4 since the channel (aka request) is
-	 * set directly in the respective dma_option. In fact, it would be
-	 * overridden in dma-stm32f4::prepare_stream().
-	 */
-#ifdef CHIP_FAMILY_STM32L4
-	dma_select_channel(STM32_DMAC_SPI1_TX, 1);
-	dma_select_channel(STM32_DMAC_SPI1_RX, 1);
-#elif defined(CHIP_FAMILY_STM32H7)
-	dma_select_channel(STM32_DMAC_SPI1_TX, DMAMUX1_REQ_SPI1_TX);
-	dma_select_channel(STM32_DMAC_SPI1_RX, DMAMUX1_REQ_SPI1_RX);
-#endif
-	/*
-	 * Enable rx/tx DMA and get ready to receive our first transaction and
-	 * "disable" FIFO by setting event to happen after only 1 byte
-	 */
-#ifdef CHIP_FAMILY_STM32H7
-	spi->cfg2 = 0;
-	spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) |
-			STM32_SPI_CFG1_CRCSIZE(8) |
-			STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN |
-			STM32_SPI_CFG1_UDRCFG_CONST |
-			STM32_SPI_CFG1_UDRDET_BEGIN_FRM;
-	spi->cr1 = 0;
-#else /* !CHIP_FAMILY_STM32H7 */
-	spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN |
-		STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
-
-	/* Enable the SPI peripheral */
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-#endif /* !CHIP_FAMILY_STM32H7 */
-
-	gpio_enable_interrupt(GPIO_SPI1_NSS);
-
-	/*
-	 * If we were already enabled or chipset is already on,
-	 * prepare for transaction
-	 */
-	if (was_enabled || chipset_in_state(CHIPSET_STATE_ON))
-		spi_chipset_startup();
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
-
-/**
- * Get protocol information
- */
-enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-#ifdef CONFIG_SPI_PROTOCOL_V2
-	r->protocol_versions |= BIT(2);
-#endif
-	r->protocol_versions |= BIT(3);
-	r->max_request_packet_size = SPI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
diff --git a/chip/stm32/spi_master-stm32h7.c b/chip/stm32/spi_master-stm32h7.c
deleted file mode 100644
index 4195dc595a..0000000000
--- a/chip/stm32/spi_master-stm32h7.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI master driver.
- */
-
-#include "common.h"
-#include "dma.h"
-#include "gpio.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "stm32-dma.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* SPI ports are used as master */
-static stm32_spi_regs_t *SPI_REGS[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	STM32_SPI1_REGS,
-#endif
-	STM32_SPI2_REGS,
-	STM32_SPI3_REGS,
-	STM32_SPI4_REGS,
-};
-
-/* DMA request mapping on channels */
-static uint8_t dma_req_tx[ARRAY_SIZE(SPI_REGS)] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	DMAMUX1_REQ_SPI1_TX,
-#endif
-	DMAMUX1_REQ_SPI2_TX,
-	DMAMUX1_REQ_SPI3_TX,
-	DMAMUX1_REQ_SPI4_TX,
-};
-static uint8_t dma_req_rx[ARRAY_SIZE(SPI_REGS)] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	DMAMUX1_REQ_SPI1_RX,
-#endif
-	DMAMUX1_REQ_SPI2_RX,
-	DMAMUX1_REQ_SPI3_RX,
-	DMAMUX1_REQ_SPI4_RX,
-};
-
-static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
-
-#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
-
-static const struct dma_option dma_tx_option[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-};
-
-static const struct dma_option dma_rx_option[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-};
-
-static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
-
-/**
- * Initialize SPI module, registers, and clocks
- * @param spi_device  device to initialize.
- */
-static void spi_master_config(const struct spi_device_t *spi_device)
-{
-	int port = spi_device->port;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/*
-	 * Set SPI master, baud rate, and software slave control.
-	 */
-	spi->cr1 = STM32_SPI_CR1_SSI;
-	spi->cfg2 = STM32_SPI_CFG2_MSTR | STM32_SPI_CFG2_SSM |
-		    STM32_SPI_CFG2_AFCNTR;
-	spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) |
-		    STM32_SPI_CFG1_CRCSIZE(8) |
-		    STM32_SPI_CR1_DIV(spi_device->div);
-
-	dma_select_channel(dma_tx_option[port].channel, dma_req_tx[port]);
-	dma_select_channel(dma_rx_option[port].channel, dma_req_rx[port]);
-}
-
-static int spi_master_initialize(const struct spi_device_t *spi_device)
-{
-	spi_master_config(spi_device);
-
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	/* Set flag */
-	spi_enabled[spi_device->port] = 1;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Shutdown SPI module
- */
-static int spi_master_shutdown(const struct spi_device_t *spi_device)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/* Set flag */
-	spi_enabled[port] = 0;
-
-	/* Disable DMA streams */
-	dma_disable(dma_tx_option[port].channel);
-	dma_disable(dma_rx_option[port].channel);
-
-	/* Disable SPI */
-	spi->cr1 &= ~STM32_SPI_CR1_SPE;
-
-	/* Disable DMA buffers */
-	spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN);
-
-	return rv;
-}
-
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	int port = spi_device->port;
-	if (enable == spi_enabled[port])
-		return EC_SUCCESS;
-	if (enable)
-		return spi_master_initialize(spi_device);
-	else
-		return spi_master_shutdown(spi_device);
-}
-
-static int spi_dma_start(const struct spi_device_t *spi_device,
-			 const uint8_t *txdata, uint8_t *rxdata, int len)
-{
-	dma_chan_t *txdma;
-	int port = spi_device->port;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/*
-	 * Workaround for STM32H7 errata: without resetting the SPI controller,
-	 * the RX DMA requests will happen too early on the 2nd transfer.
-	 */
-	STM32_RCC_APB2RSTR = STM32_RCC_PB2_SPI4;
-	STM32_RCC_APB2RSTR = 0;
-	dma_clear_isr(dma_tx_option[port].channel);
-	dma_clear_isr(dma_rx_option[port].channel);
-	/* restore proper SPI configuration registers. */
-	spi_master_config(spi_device);
-
-	spi->cr2 = len;
-	spi->cfg1 |= STM32_SPI_CFG1_RXDMAEN;
-	/* Set up RX DMA */
-	if (rxdata)
-		dma_start_rx(&dma_rx_option[port], len, rxdata);
-
-	/* Set up TX DMA */
-	if (txdata) {
-		txdma = dma_get_channel(dma_tx_option[port].channel);
-		dma_prepare_tx(&dma_tx_option[port], len, txdata);
-		dma_go(txdma);
-	}
-
-	spi->cfg1 |= STM32_SPI_CFG1_TXDMAEN;
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-	spi->cr1 |= STM32_SPI_CR1_CSTART;
-
-	return EC_SUCCESS;
-}
-
-static inline bool dma_is_enabled_(const struct dma_option *option)
-{
-	return dma_is_enabled(dma_get_channel(option->channel));
-}
-
-static int spi_dma_wait(int port)
-{
-	timestamp_t timeout;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-	int rv = EC_SUCCESS;
-
-	/* Wait for DMA transmission to complete */
-	if (dma_is_enabled_(&dma_tx_option[port])) {
-		rv = dma_wait(dma_tx_option[port].channel);
-		if (rv)
-			return rv;
-
-		timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
-		/* Wait for FIFO empty and BSY bit clear */
-		while (!(spi->sr & (STM32_SPI_SR_TXC)))
-			if (get_time().val > timeout.val)
-				return EC_ERROR_TIMEOUT;
-
-		/* Disable TX DMA */
-		dma_disable(dma_tx_option[port].channel);
-	}
-
-	/* Wait for DMA reception to complete */
-	if (dma_is_enabled_(&dma_rx_option[port])) {
-		rv = dma_wait(dma_rx_option[port].channel);
-		if (rv)
-			return rv;
-
-		timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
-		/* Wait for FRLVL[1:0] to indicate FIFO empty */
-		while (spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE))
-			if (get_time().val > timeout.val)
-				return EC_ERROR_TIMEOUT;
-
-		/* Disable RX DMA */
-		dma_disable(dma_rx_option[port].channel);
-	}
-
-	spi->cr1 &= ~STM32_SPI_CR1_SPE;
-	spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN);
-
-	return rv;
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	int full_readback = 0;
-
-	char *buf = NULL;
-
-#ifndef CONFIG_SPI_HALFDUPLEX
-	if (rxlen == SPI_READBACK_ALL) {
-		buf = rxdata;
-		full_readback = 1;
-	} else {
-		rv = shared_mem_acquire(MAX(txlen, rxlen), &buf);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-#endif
-
-	/* Drive SS low */
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	rv = spi_dma_start(spi_device, txdata, buf, txlen);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
-	if (full_readback)
-		return EC_SUCCESS;
-
-	if (rxlen) {
-		rv = spi_dma_wait(port);
-		if (rv != EC_SUCCESS)
-			goto err_free;
-
-		rv = spi_dma_start(spi_device, buf, rxdata, rxlen);
-		if (rv != EC_SUCCESS)
-			goto err_free;
-	}
-
-err_free:
-	if (!full_readback)
-		shared_mem_release(buf);
-	return rv;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int rv = spi_dma_wait(spi_device->port);
-
-	/* Drive SS high */
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return rv;
-}
-
-int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	return spi_dma_wait(spi_device->port);
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int rv;
-	int port = spi_device->port;
-
-	mutex_lock(spi_mutex + port);
-	rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	rv |= spi_transaction_flush(spi_device);
-	mutex_unlock(spi_mutex + port);
-
-	return rv;
-}
diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c
deleted file mode 100644
index 8943c0c682..0000000000
--- a/chip/stm32/spi_master.c
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI master driver.
- */
-
-#include "common.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "stm32-dma.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#if defined(CHIP_VARIANT_STM32F373)  || \
-	defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_VARIANT_STM32F76X)
-#define HAS_SPI3
-#else
-#undef  HAS_SPI3
-#endif
-
-/* The second (and third if available) SPI port are used as master */
-static stm32_spi_regs_t *SPI_REGS[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	STM32_SPI1_REGS,
-#endif
-	STM32_SPI2_REGS,
-#ifdef HAS_SPI3
-	STM32_SPI3_REGS,
-#endif
-};
-
-#ifdef CHIP_FAMILY_STM32L4
-/* DMA request mapping on channels */
-static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	/* SPI1 */ 1,
-#endif
-	/* SPI2 */ 1,
-	/* SPI3 */ 3,
-};
-#endif
-
-static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
-
-#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
-
-/* Default DMA channel options */
-#ifdef CHIP_FAMILY_STM32F4
-#define F4_CHANNEL(ch)	STM32_DMA_CCR_CHANNEL(ch)
-#else
-#define F4_CHANNEL(ch)	0
-#endif
-
-static const struct dma_option dma_tx_option[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI1_TX_REQ_CH)
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI2_TX_REQ_CH)
-	},
-#ifdef HAS_SPI3
-	{
-		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI3_TX_REQ_CH)
-	},
-#endif
-};
-
-static const struct dma_option dma_rx_option[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI1_RX_REQ_CH)
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI2_RX_REQ_CH)
-	},
-#ifdef HAS_SPI3
-	{
-		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI3_RX_REQ_CH)
-	},
-#endif
-};
-
-static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
-
-static int spi_tx_done(stm32_spi_regs_t *spi)
-{
-	return !(spi->sr & (STM32_SPI_SR_FTLVL | STM32_SPI_SR_BSY));
-}
-
-static int spi_rx_done(stm32_spi_regs_t *spi)
-{
-	return !(spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE));
-}
-
-/* Read until RX FIFO is empty (i.e. RX done) */
-static int spi_clear_rx_fifo(stm32_spi_regs_t *spi)
-{
-	uint8_t unused __attribute__((unused));
-	uint32_t start = __hw_clock_source_read(), delta;
-
-	while (!spi_rx_done(spi)) {
-		unused = spi->dr;  /* Read one byte from FIFO */
-		delta = __hw_clock_source_read() - start;
-		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
-			return EC_ERROR_TIMEOUT;
-	}
-	return EC_SUCCESS;
-}
-
-/* Wait until TX FIFO is empty (i.e. TX done) */
-static int spi_clear_tx_fifo(stm32_spi_regs_t *spi)
-{
-	uint32_t start = __hw_clock_source_read(), delta;
-
-	while (!spi_tx_done(spi)) {
-		/* wait for TX complete */
-		delta = __hw_clock_source_read() - start;
-		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
-			return EC_ERROR_TIMEOUT;
-	}
-	return EC_SUCCESS;
-}
-
-/**
- * Initialize SPI module, registers, and clocks
- *
- * - port: which port to initialize.
- */
-static int spi_master_initialize(const struct spi_device_t *spi_device)
-{
-	int port = spi_device->port;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/*
-	 * Set SPI master, baud rate, and software slave control.
-	 * */
-
-	/*
-	 * STM32F412
-	 * Section 26.3.5 Slave select (NSS) pin management and Figure 276
-	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=817
-	 *
-	 * The documentation in this section is a bit confusing, so here's a
-	 * summary based on discussion with ST:
-	 *
-	 * Software NSS management (SSM = 1):
-	 *   - In master mode, the NSS output is deactivated. You need to use a
-	 *     GPIO in output mode for slave select. This is generally used for
-	 *     multi-slave operation, but you can also use it for single slave
-	 *     operation. In this case, you should make sure to configure a GPIO
-	 *     for NSS, but *not* activate the SPI alternate function on that
-	 *     same pin since that will enable hardware NSS management (see
-	 *     below).
-	 *   - In slave mode, the NSS input level is equal to the SSI bit value.
-	 *
-	 * Hardware NSS management (SSM = 0):
-	 *   - In slave mode, when NSS pin is detected low the slave (MCU) is
-	 *     selected.
-	 *   - In master mode, there are two configurations, depending on the
-	 *     SSOE bit in register SPIx_CR1.
-	 *       - NSS output enable (SSM=0, SSOE=1):
-	 *         The MCU (master) drives NSS low as soon as SPI is enabled
-	 *         (SPE=1) and releases it when SPI is disabled (SPE=0).
-	 *
-	 *       - NSS output disable (SSM=0, SSOE=0):
-	 *         Allows multimaster capability. The MCU (master) drives NSS
-	 *         low.  If another master tries to takes control of the bus and
-	 *         NSS is pulled low, a mode fault is generated and the MCU
-	 *         changes to slave mode.
-	 *
-	 *   - NSS output disable (SSM=0, SSOE=0): if the MCU is acting as
-	 *     master on the bus, this config allows multimaster capability. If
-	 *     the NSS pin is pulled low in this mode, the SPI enters master
-	 *     mode fault state and the device is automatically reconfigured in
-	 *     slave mode.  In slave mode, the NSS pin works as a standard "chip
-	 *     select" input and the slave is selected while NSS lin is at low
-	 *     level.
-	 */
-	spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI |
-		   (spi_device->div << 3);
-
-#ifdef CHIP_FAMILY_STM32L4
-	dma_select_channel(dma_tx_option[port].channel, dma_req[port]);
-	dma_select_channel(dma_rx_option[port].channel, dma_req[port]);
-#endif
-	/*
-	 * Configure 8-bit datasize, set FRXTH, enable DMA,
-	 * and set data size (applies to STM32F0 only).
-	 *
-	 * STM32F412:
-	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=852
-	 *
-	 *
-	 * STM32F0:
-	 * https://www.st.com/resource/en/reference_manual/dm00031936.pdf#page=803
-	 */
-	spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN |
-			STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
-
-#ifdef CONFIG_SPI_HALFDUPLEX
-	spi->cr1 |= STM32_SPI_CR1_BIDIMODE | STM32_SPI_CR1_BIDIOE;
-#endif
-
-	/* Drive Chip Select high before turning on SPI module */
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	/* Enable SPI hardware module. This will actively drive the CLK pin */
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-
-	/* Set flag */
-	spi_enabled[port] = 1;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Shutdown SPI module
- */
-static int spi_master_shutdown(const struct spi_device_t *spi_device)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/* Set flag */
-	spi_enabled[port] = 0;
-
-	/* Disable DMA streams */
-	dma_disable(dma_tx_option[port].channel);
-	dma_disable(dma_rx_option[port].channel);
-
-	/* Disable SPI. Let the CLK pin float. */
-	spi->cr1 &= ~STM32_SPI_CR1_SPE;
-
-	spi_clear_rx_fifo(spi);
-
-	/* Disable DMA buffers */
-	spi->cr2 &= ~(STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN);
-
-	return rv;
-}
-
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	if (enable == spi_enabled[spi_device->port])
-		return EC_SUCCESS;
-	if (enable)
-		return spi_master_initialize(spi_device);
-	else
-		return spi_master_shutdown(spi_device);
-}
-
-static int spi_dma_start(int port, const uint8_t *txdata,
-			 uint8_t *rxdata, int len)
-{
-	dma_chan_t *txdma;
-
-	/* Set up RX DMA */
-	if (rxdata)
-		dma_start_rx(&dma_rx_option[port], len, rxdata);
-
-	/* Set up TX DMA */
-	if (txdata) {
-		txdma = dma_get_channel(dma_tx_option[port].channel);
-		dma_prepare_tx(&dma_tx_option[port], len, txdata);
-		dma_go(txdma);
-	}
-
-	return EC_SUCCESS;
-}
-
-static bool dma_is_enabled_(const struct dma_option *option)
-{
-	return dma_is_enabled(dma_get_channel(option->channel));
-}
-
-static int spi_dma_wait(int port)
-{
-	int rv = EC_SUCCESS;
-
-	/* Wait for DMA transmission to complete */
-	if (dma_is_enabled_(&dma_tx_option[port])) {
-		/*
-		 * In TX mode, SPI only generates clock when we write to FIFO.
-		 * Therefore, even though `dma_wait` polls with interval 0.1ms,
-		 * we won't send extra bytes.
-		 */
-		rv = dma_wait(dma_tx_option[port].channel);
-		if (rv)
-			return rv;
-		/* Disable TX DMA */
-		dma_disable(dma_tx_option[port].channel);
-	}
-
-	/* Wait for DMA reception to complete */
-	if (dma_is_enabled_(&dma_rx_option[port])) {
-		/*
-		 * Because `dma_wait` polls with interval 0.1ms, we will read at
-		 * least ~100 bytes (with 8MHz clock).  If you don't want this
-		 * overhead, you can use interrupt handler
-		 * (`dma_enable_tc_interrupt_callback`) and disable SPI
-		 * interface in callback function.
-		 */
-		rv = dma_wait(dma_rx_option[port].channel);
-		if (rv)
-			return rv;
-		/* Disable RX DMA */
-		dma_disable(dma_rx_option[port].channel);
-	}
-	return rv;
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	int full_readback = 0;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-	char *buf = NULL;
-
-	/* We should not ever be called when disabled, but fail early if so. */
-	if (!spi_enabled[port])
-		return EC_ERROR_BUSY;
-
-#ifndef CONFIG_SPI_HALFDUPLEX
-	if (rxlen == SPI_READBACK_ALL) {
-		buf = rxdata;
-		full_readback = 1;
-	} else {
-		rv = shared_mem_acquire(MAX(txlen, rxlen), &buf);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-#endif
-
-	/* Drive SS low */
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	spi_clear_rx_fifo(spi);
-
-	rv = spi_dma_start(port, txdata, buf, txlen);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
-#ifdef CONFIG_SPI_HALFDUPLEX
-	spi->cr1 |= STM32_SPI_CR1_BIDIOE;
-#endif
-
-	if (full_readback)
-		return EC_SUCCESS;
-
-	rv = spi_dma_wait(port);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
-	spi_clear_tx_fifo(spi);
-
-	if (rxlen) {
-		rv = spi_dma_start(port, buf, rxdata, rxlen);
-		if (rv != EC_SUCCESS)
-			goto err_free;
-#ifdef CONFIG_SPI_HALFDUPLEX
-		spi->cr1 &= ~STM32_SPI_CR1_BIDIOE;
-#endif
-	}
-
-err_free:
-#ifndef CONFIG_SPI_HALFDUPLEX
-	if (!full_readback)
-		shared_mem_release(buf);
-#endif
-	return rv;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int rv = spi_dma_wait(spi_device->port);
-
-	/* Drive SS high */
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return rv;
-}
-
-int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	return spi_dma_wait(spi_device->port);
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int rv;
-	int port = spi_device->port;
-
-	mutex_lock(spi_mutex + port);
-	rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	rv |= spi_transaction_flush(spi_device);
-	mutex_unlock(spi_mutex + port);
-
-	return rv;
-}
diff --git a/chip/stm32/stm32-dma.h b/chip/stm32/stm32-dma.h
deleted file mode 100644
index 06233b9c93..0000000000
--- a/chip/stm32/stm32-dma.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * Select DMA stream-channel mapping
- *
- * This selects which stream (peripheral) to be used on a specific channel.
- * Some STM32 chips simply logically OR requests, thus do not require this
- * selection.
- *
- * @param channel: (Global) channel # base 0 (Note some STM32s use base 1)
- * @param peripheral: Refer to the TRM for 'peripheral request signals'
- */
-void dma_select_channel(enum dma_channel channel, unsigned char stream);
diff --git a/chip/stm32/system.c b/chip/stm32/system.c
deleted file mode 100644
index 03e9a74ac4..0000000000
--- a/chip/stm32/system.c
+++ /dev/null
@@ -1,631 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : hardware specific implementation */
-
-#include "bkpdata.h"
-#include "clock.h"
-#include "console.h"
-#include "cpu.h"
-#include "cros_version.h"
-#include "flash.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "panic.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-#ifdef CONFIG_STM32_CLOCK_LSE
-#define BDCR_SRC BDCR_SRC_LSE
-#define BDCR_RDY STM32_RCC_BDCR_LSERDY
-#else
-#define BDCR_SRC BDCR_SRC_LSI
-#define BDCR_RDY 0
-#endif
-#define BDCR_ENABLE_VALUE (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | \
-			BDCR_RDY)
-#define BDCR_ENABLE_MASK (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | \
-			STM32_RCC_BDCR_BDRST)
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= 3);
-#endif
-
-void __no_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-#ifdef CONFIG_COMMON_RUNTIME
-	/*
-	 * Hibernate not implemented on this platform.
-	 *
-	 * Until then, treat this as a request to hard-reboot.
-	 */
-	cprints(CC_SYSTEM, "hibernate not supported, so rebooting");
-	cflush();
-	system_reset(SYSTEM_RESET_HARD);
-#endif
-}
-
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-	__attribute__((weak, alias("__no_hibernate")));
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-#ifdef CONFIG_HOSTCMD_PD
-	/* Inform the PD MCU that we are going to hibernate. */
-	host_command_pd_request_hibernate();
-	/* Wait to ensure exchange with PD before hibernating. */
-	msleep(100);
-#endif
-
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* chip specific standby mode */
-	__enter_hibernate(seconds, microseconds);
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return bkpdata_read_reset_flags();
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	bkpdata_write_reset_flags(flags);
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t flags = chip_read_reset_flags();
-	uint32_t raw_cause = STM32_RCC_RESET_CAUSE;
-#ifdef STM32_PWR_RESET_CAUSE
-	uint32_t pwr_status = STM32_PWR_RESET_CAUSE;
-#endif
-
-	/* Clear the hardware reset cause by setting the RMVF bit */
-	STM32_RCC_RESET_CAUSE |= RESET_CAUSE_RMVF;
-#ifdef STM32_PWR_RESET_CAUSE
-	/* Clear SBF in PWR_CSR */
-	STM32_PWR_RESET_CAUSE_CLR |= RESET_CAUSE_SBF_CLR;
-#endif
-	/* Clear saved reset flags */
-	chip_save_reset_flags(0);
-
-	if (raw_cause & RESET_CAUSE_WDG) {
-		/*
-		 * IWDG or WWDG, if the watchdog was not used as an hard reset
-		 * mechanism
-		 */
-		if (!(flags & EC_RESET_FLAG_HARD))
-			flags |= EC_RESET_FLAG_WATCHDOG;
-	}
-
-	if (raw_cause & RESET_CAUSE_SFT)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (raw_cause & RESET_CAUSE_POR)
-		flags |= EC_RESET_FLAG_POWER_ON;
-
-	if (raw_cause & RESET_CAUSE_PIN)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-#ifdef STM32_PWR_RESET_CAUSE
-	if (pwr_status & RESET_CAUSE_SBF)
-		/* Hibernated and subsequently awakened */
-		flags |= EC_RESET_FLAG_HIBERNATE;
-#endif
-
-	if (!flags && (raw_cause & RESET_CAUSE_OTHER))
-		flags |= EC_RESET_FLAG_OTHER;
-
-	/*
-	 * WORKAROUND: as we cannot de-activate the watchdog during
-	 * long hibernation, we are woken-up once by the watchdog and
-	 * go back to hibernate if we detect that condition, without
-	 * watchdog initialized this time.
-	 * The RTC deadline (if any) is already set.
-	 */
-	if ((flags & EC_RESET_FLAG_HIBERNATE) &&
-	    (flags & EC_RESET_FLAG_WATCHDOG)) {
-		__enter_hibernate(0, 0);
-	}
-
-	system_set_reset_flags(flags);
-}
-
-/* Stop all timers and WDGs we might use when JTAG stops the CPU. */
-void chip_pre_init(void)
-{
-	uint32_t apb1fz_reg = 0;
-	uint32_t apb2fz_reg = 0;
-
-#if defined(CHIP_FAMILY_STM32F0)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 |
-		STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 |
-		STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1;
-
-	/* enable clock to debug module before writing */
-	STM32_RCC_APB2ENR |= STM32_RCC_DBGMCUEN;
-#elif defined(CHIP_FAMILY_STM32F3)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17;
-#elif defined(CHIP_FAMILY_STM32F4)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2  | STM32_RCC_PB1_TIM3  | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5  | STM32_RCC_PB1_TIM6  | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | STM32_RCC_PB1_TIM14|
-		STM32_RCC_PB1_RTC   | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM1  | STM32_RCC_PB2_TIM8  | STM32_RCC_PB2_TIM9 |
-		STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11;
-#elif defined(CHIP_FAMILY_STM32L4)
-
-#ifdef	CHIP_VARIANT_STM32L431X
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_TIM6 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16;
-#else
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8;
-#endif
-#elif defined(CHIP_FAMILY_STM32L)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 |
-		STM32_RCC_PB2_TIM11;
-#elif defined(CHIP_FAMILY_STM32G4)
-	apb1fz_reg =
-		STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 |
-		STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 |
-		STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 |
-		STM32_DBGMCU_APB1FZ_RTC  | STM32_DBGMCU_APB1FZ_WWDG |
-		STM32_DBGMCU_APB1FZ_IWDG;
-	apb2fz_reg =
-		STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 |
-		STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 |
-		STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20;
-#elif defined(CHIP_FAMILY_STM32H7)
-	/* TODO(b/67081508) */
-#endif
-#if defined(CHIP_FAMILY_STM32L5)
-	(void)apb1fz_reg;
-	(void)apb2fz_reg;
-#else
-	if (apb1fz_reg)
-		STM32_DBGMCU_APB1FZ |= apb1fz_reg;
-	if (apb2fz_reg)
-		STM32_DBGMCU_APB2FZ |= apb2fz_reg;
-#endif
-}
-
-#ifdef CONFIG_PVD
-/******************************************************************************
- * Detects sagging Vdd voltage and resets the system via the programmable
- * voltage detector interrupt.
- */
-static void configure_pvd(void)
-{
-	/* Clear Interrupt Enable Mask Register. */
-	STM32_EXTI_IMR &= ~EXTI_PVD_EVENT;
-
-	/* Clear Rising and Falling Trigger Selection Registers. */
-	STM32_EXTI_RTSR &= ~EXTI_PVD_EVENT;
-	STM32_EXTI_FTSR &= ~EXTI_PVD_EVENT;
-
-	/* Clear the value of the PVD Level Selection. */
-	STM32_PWR_CR &= ~STM32_PWD_PVD_LS_MASK;
-
-	/* Set the new value of the PVD Level Selection. */
-	STM32_PWR_CR |= STM32_PWD_PVD_LS(PVD_THRESHOLD);
-
-	/* Enable Power Clock. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_PWREN;
-
-	/* Configure the NVIC for PVD. */
-	task_enable_irq(STM32_IRQ_PVD);
-
-	/* Configure interrupt mode. */
-	STM32_EXTI_IMR |= EXTI_PVD_EVENT;
-	STM32_EXTI_RTSR |= EXTI_PVD_EVENT;
-
-	/* Enable the PVD Output. */
-	STM32_PWR_CR |= STM32_PWR_PVDE;
-}
-
-void pvd_interrupt(void)
-{
-	/* Clear Pending Register */
-	STM32_EXTI_PR = EXTI_PVD_EVENT;
-	/* Handle recovery by rebooting the system */
-	system_reset(0);
-}
-DECLARE_IRQ(STM32_IRQ_PVD, pvd_interrupt, HOOK_PRIO_FIRST);
-
-#endif /* CONFIG_PVD */
-
-void system_pre_init(void)
-{
-#ifdef CONFIG_SOFTWARE_PANIC
-	uint16_t reason, info;
-	uint8_t exception, panic_flags;
-#endif
-
-	/* enable clock on Power module */
-#ifndef CHIP_FAMILY_STM32H7
-#ifdef	CHIP_FAMILY_STM32L4
-	STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN;
-#else
-	STM32_RCC_APB1ENR |= STM32_RCC_PWREN;
-#endif
-#endif
-#if defined(CHIP_FAMILY_STM32F4)
-	/* enable backup registers */
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN;
-#elif defined(CHIP_FAMILY_STM32H7)
-	/* enable backup registers */
-	STM32_RCC_AHB4ENR |= BIT(28);
-#elif defined(CHIP_FAMILY_STM32L4)
-	/* enable RTC APB clock */
-	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_RTCAPBEN;
-#else
-	/* enable backup registers */
-	STM32_RCC_APB1ENR |= BIT(27);
-#endif
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-	/* Enable access to RCC CSR register and RTC backup registers */
-	STM32_PWR_CR |= BIT(8);
-#ifdef CHIP_VARIANT_STM32L476
-	/* Enable Vddio2 */
-	STM32_PWR_CR2 |= BIT(9);
-#endif
-
-	/* switch on LSI */
-	STM32_RCC_CSR |= BIT(0);
-	/* Wait for LSI to be ready */
-	while (!(STM32_RCC_CSR & BIT(1)))
-		;
-
-#if defined(CHIP_FAMILY_STM32G4)
-	/* Make sure PWR clock is enabled */
-	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN;
-	/* Enable access to backup domain registers */
-	STM32_PWR_CR1 |= STM32_PWR_CR1_DBP;
-#endif
-	/* re-configure RTC if needed */
-#ifdef CHIP_FAMILY_STM32L
-	if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) {
-		/* The RTC settings are bad, we need to reset it */
-		STM32_RCC_CSR |= 0x00800000;
-		/* Enable RTC and use LSI as clock source */
-		STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000;
-	}
-#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-	defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_FAMILY_STM32L5) || defined(CHIP_FAMILY_STM32F4) ||	\
-	defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32G4)
-	if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) {
-		/* The RTC settings are bad, we need to reset it */
-		STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
-		STM32_RCC_BDCR = STM32_RCC_BDCR & ~BDCR_ENABLE_MASK;
-#ifdef CONFIG_STM32_CLOCK_LSE
-		/* Turn on LSE */
-		STM32_RCC_BDCR |= STM32_RCC_BDCR_LSEON;
-		/* Wait for LSE to be ready */
-		while (!(STM32_RCC_BDCR & STM32_RCC_BDCR_LSERDY))
-			;
-#endif
-		/* Select clock source and enable RTC */
-		STM32_RCC_BDCR |= BDCR_RTCSEL(BDCR_SRC) | STM32_RCC_BDCR_RTCEN;
-	}
-#else
-#error "Unsupported chip family"
-#endif
-
-	check_reset_cause();
-
-#ifdef CONFIG_SOFTWARE_PANIC
-	/* Restore then clear saved panic reason */
-	reason = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_REASON);
-	info = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_INFO);
-	exception = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION);
-	panic_flags = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_FLAGS);
-	if (reason || info || exception || panic_flags) {
-		panic_set_reason(reason, info, exception);
-		panic_get_data()->flags = panic_flags;
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, 0);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, 0);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, 0);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS, 0);
-	}
-#endif
-
-#ifdef CONFIG_PVD
-	configure_pvd();
-#endif
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/*
-	 * TODO(crbug.com/1045283): Change this part of code to use
-	 * system_encode_save_flags, like all other system_reset functions.
-	 *
-	 * system_encode_save_flags(flags, &save_flags);
-	 */
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	/* Remember that the software asked us to hard reboot */
-	if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-
-	/* Add in stay in RO flag into saved flags. */
-	if (flags & SYSTEM_RESET_STAY_IN_RO)
-		save_flags |= EC_RESET_FLAG_STAY_IN_RO;
-
-	if (flags & SYSTEM_RESET_AP_WATCHDOG)
-		save_flags |= EC_RESET_FLAG_AP_WATCHDOG;
-
-	chip_save_reset_flags(save_flags);
-
-#ifdef CONFIG_ARMV7M_CACHE
-	/*
-	 * Disable caches (D-cache is also flushed and invalidated)
-	 * so changes that lives in cache are saved in memory now.
-	 * Any subsequent writes will be done immediately.
-	 */
-	cpu_disable_caches();
-#endif
-
-	if (flags & SYSTEM_RESET_HARD) {
-#ifdef CONFIG_SOFTWARE_PANIC
-		uint32_t reason, info;
-		uint8_t exception;
-		uint8_t panic_flags = panic_get_data()->flags;
-
-		/* Panic data will be wiped by hard reset, so save it */
-		panic_get_reason(&reason, &info, &exception);
-		/* 16 bits stored - upper 16 bits of reason / info are lost */
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, reason);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, info);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, exception);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS, panic_flags);
-#endif
-
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4)
-		/*
-		 * Ask the flash module to reboot, so that we reload the
-		 * option bytes.
-		 */
-		crec_flash_physical_force_reload();
-
-		/* Fall through to watchdog if that fails */
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-		/*
-		 * On some chips, a reboot doesn't always reload the option
-		 * bytes, and we need to explicitly request for a reload.
-		 * The reload request triggers a chip reset, so let's just
-		 * use this for hard reset.
-		 */
-		STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH;
-#elif defined(CHIP_FAMILY_STM32G4)
-		STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
-		STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
-		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
-		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
-		STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH;
-#else
-		/*
-		 * RM0433 Rev 6
-		 * Section 44.3.3
-		 * https://www.st.com/resource/en/reference_manual/dm00314099.pdf#page=1898
-		 *
-		 * When the window option is not used, the IWDG can be
-		 * configured as follows:
-		 *
-		 * 1. Enable the IWDG by writing 0x0000 CCCC in the Key
-		 *    register (IWDG_KR).
-		 * 2. Enable register access by writing 0x0000 5555 in the Key
-		 *    register (IWDG_KR).
-		 * 3. Write the prescaler by programming the Prescaler register
-		 *    (IWDG_PR) from 0 to 7.
-		 * 4. Write the Reload register (IWDG_RLR).
-		 * 5. Wait for the registers to be updated
-		 *    (IWDG_SR = 0x0000 0000).
-		 * 6. Refresh the counter value with IWDG_RLR
-		 *    (IWDG_KR = 0x0000 AAAA)
-		 */
-
-		/*
-		 * RM0433 Rev 7
-		 * Section 45.4.4 Page 1920
-		 * https://www.st.com/resource/en/reference_manual/dm00314099.pdf
-		 * If several reload, prescaler, or window values are used by
-		 * the application, it is mandatory to wait until RVU bit is
-		 * reset before changing the reload value, to wait until PVU bit
-		 * is reset before changing the prescaler value, and to wait
-		 * until WVU bit is reset before changing the window value.
-		 *
-		 * Here we should wait to finish previous IWDG_RLR register
-		 * update (see watchdog_init()) before starting next update,
-		 * otherwise new IWDG_RLR value will be lost.
-		 */
-		while (STM32_IWDG_SR & STM32_IWDG_SR_RVU)
-			;
-
-		/*
-		 * Enable IWDG, which shouldn't be necessary since the IWDG
-		 * only needs to be started once, but STM32F412 hangs unless
-		 * this is added.
-		 *
-		 * See http://b/137045370.
-		 */
-		STM32_IWDG_KR = STM32_IWDG_KR_START;
-
-		/* Ask the watchdog to trigger a hard reboot */
-		STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK;
-		STM32_IWDG_RLR = 0x1;
-		/* Wait for value to be updated. */
-		while (STM32_IWDG_SR & STM32_IWDG_SR_RVU)
-			;
-
-		/* Reload IWDG counter, it also locks registers */
-		STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
-#endif
-		/* wait for the chip to reboot */
-		while (1)
-			;
-	} else {
-		if (flags & SYSTEM_RESET_WAIT_EXT) {
-			int i;
-
-			/* Wait 10 seconds for external reset */
-			for (i = 0; i < 1000; i++) {
-				watchdog_reload();
-				udelay(10000);
-			}
-		}
-
-		/* Request a soft system reset from the core. */
-		CPU_NVIC_APINT = CPU_NVIC_APINT_KEY_WR | CPU_NVIC_APINT_SYSRST;
-	}
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	/* Check if value fits in 16 bits */
-	if (value & 0xffff0000)
-		return EC_ERROR_INVAL;
-	return bkpdata_write(BKPDATA_INDEX_SCRATCHPAD, (uint16_t)value);
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = (uint32_t)bkpdata_read(BKPDATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "stm";
-}
-
-const char *system_get_chip_name(void)
-{
-	return STRINGIFY(CHIP_VARIANT);
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-int system_get_chip_unique_id(uint8_t **id)
-{
-	*id = (uint8_t *)STM32_UNIQUE_ID_ADDRESS;
-	return STM32_UNIQUE_ID_LENGTH;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int msb = 0;
-	int bkpdata_index = bkpdata_index_lookup(idx, &msb);
-
-	if (bkpdata_index < 0)
-		return EC_ERROR_INVAL;
-
-	*value = (bkpdata_read(bkpdata_index) >> (8 * msb)) & 0xff;
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	uint16_t read;
-	int msb = 0;
-	int bkpdata_index = bkpdata_index_lookup(idx, &msb);
-
-	if (bkpdata_index < 0)
-		return EC_ERROR_INVAL;
-
-	read = bkpdata_read(bkpdata_index);
-	if (msb)
-		read = (read & 0xff) | (value << 8);
-	else
-		read = (read & 0xff00) | value;
-
-	bkpdata_write(bkpdata_index, read);
-	return EC_SUCCESS;
-}
-
-int system_is_reboot_warm(void)
-{
-	/*
-	 * Detecting if the system is warm is relevant for a
-	 * few reasons.
-	 * One such reason is that some firmwares transition from
-	 * RO to RW images. When this happens, we may not need to
-	 * restart certain clocks. On the flip side, we may need
-	 * to restart the clocks if the RW requires a different
-	 * set of clocks. Thus, the clock configurations need to
-	 * be checked for a perfect match.
-	 */
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-	return ((STM32_RCC_AHBENR & 0x7e0000) == 0x7e0000);
-#elif defined(CHIP_FAMILY_STM32L)
-	return ((STM32_RCC_AHBENR & 0x3f) == 0x3f);
-#elif defined(CHIP_FAMILY_STM32L4)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== STM32_RCC_AHB2ENR_GPIOMASK);
-#elif defined(CHIP_FAMILY_STM32L5)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== STM32_RCC_AHB2ENR_GPIOMASK);
-#elif defined(CHIP_FAMILY_STM32F4)
-	return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK)
-			== gpio_required_clocks());
-#elif defined(CHIP_FAMILY_STM32G4)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== gpio_required_clocks());
-#elif defined(CHIP_FAMILY_STM32H7)
-	return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK)
-			== STM32_RCC_AHB4ENR_GPIOMASK);
-#endif
-}
diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c
deleted file mode 100644
index 48d5335c53..0000000000
--- a/chip/stm32/trng.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware Random Number Generator */
-
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "panic.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "trng.h"
-#include "util.h"
-
-uint32_t rand(void)
-{
-	int tries = 300;
-	/* Wait for a valid random number */
-	while (!(STM32_RNG_SR & STM32_RNG_SR_DRDY) && --tries)
-		;
-	/* we cannot afford to feed the caller with an arbitrary number */
-	if (!tries)
-		software_panic(PANIC_SW_BAD_RNG, task_get_current());
-	/* Finally the 32-bit of entropy */
-	return STM32_RNG_DR;
-}
-
-test_mockable void rand_bytes(void *buffer, size_t len)
-{
-	while (len) {
-		uint32_t number = rand();
-		size_t cnt = 4;
-		/* deal with the lack of alignment guarantee in the API */
-		uintptr_t align = (uintptr_t)buffer & 3;
-
-		if (len < 4 || align) {
-			cnt = MIN(4 - align, len);
-			memcpy(buffer, &number, cnt);
-		} else {
-			*(uint32_t *)buffer = number;
-		}
-		len -= cnt;
-		buffer += cnt;
-	}
-}
-
-test_mockable void init_trng(void)
-{
-#ifdef CHIP_FAMILY_STM32L4
-	/* Enable the 48Mhz internal RC oscillator */
-	STM32_RCC_CRRCR |= STM32_RCC_CRRCR_HSI48ON;
-	/* no timeout: we watchdog if the oscillator doesn't start */
-	while (!(STM32_RCC_CRRCR & STM32_RCC_CRRCR_HSI48RDY))
-		;
-
-	/* Clock the TRNG using the HSI48 */
-	STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK)
-			| (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT);
-#elif defined(CHIP_FAMILY_STM32H7)
-	/* Enable the 48Mhz internal RC oscillator */
-	STM32_RCC_CR |= STM32_RCC_CR_HSI48ON;
-	/* no timeout: we watchdog if the oscillator doesn't start */
-	while (!(STM32_RCC_CR & STM32_RCC_CR_HSI48RDY))
-		;
-
-	/* Clock the TRNG using the HSI48 */
-	STM32_RCC_D2CCIP2R =
-		(STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK)
-			| STM32_RCC_D2CCIP2_RNGSEL_HSI48;
-#elif defined(CHIP_FAMILY_STM32F4)
-	/*
-	 * The RNG clock is the same as the SDIO/USB OTG clock, already set at
-	 * 48 MHz during clock initialisation. Nothing to do.
-	 */
-#else
-#error "Please add support for CONFIG_RNG on this chip family."
-#endif
-	/* Enable the RNG logic */
-	STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_RNGEN;
-	/* Start the random number generation */
-	STM32_RNG_CR |= STM32_RNG_CR_RNGEN;
-}
-
-test_mockable void exit_trng(void)
-{
-	STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN;
-	STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN;
-#ifdef CHIP_FAMILY_STM32L4
-	STM32_RCC_CRRCR &= ~STM32_RCC_CRRCR_HSI48ON;
-#elif defined(CHIP_FAMILY_STM32H7)
-	STM32_RCC_CR &= ~STM32_RCC_CR_HSI48ON;
-#elif defined(CHIP_FAMILY_STM32F4)
-	/* Nothing to do */
-#endif
-}
-
-#if defined(CONFIG_CMD_RAND)
-/*
- * We want to avoid accidentally exposing debug commands in RO since we can't
- * update RO once in production.
- */
-#if defined(SECTION_IS_RW)
-static int command_rand(int argc, char **argv)
-{
-	uint8_t data[32];
-
-	init_trng();
-	rand_bytes(data, sizeof(data));
-	exit_trng();
-
-	ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data)));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rand, command_rand,
-			NULL, "Output random bytes to console.");
-
-static enum ec_status host_command_rand(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rand_num *p = args->params;
-	struct ec_response_rand_num *r = args->response;
-	uint16_t num_rand_bytes = p->num_rand_bytes;
-
-	if (system_is_locked())
-		return EC_RES_ACCESS_DENIED;
-
-	if (num_rand_bytes > args->response_max)
-		return EC_RES_OVERFLOW;
-
-	init_trng();
-	rand_bytes(r->rand, num_rand_bytes);
-	exit_trng();
-
-	args->response_size = num_rand_bytes;
-
-	return EC_SUCCESS;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_RAND_NUM, host_command_rand,
-		     EC_VER_MASK(EC_VER_RAND_NUM));
-#endif /* SECTION_IS_RW */
-#endif /* CONFIG_CMD_RAND */
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c
deleted file mode 100644
index 0632fc6687..0000000000
--- a/chip/stm32/uart.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USART driver for Chrome EC */
-
-#include "common.h"
-#include "clock.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-#include "stm32-dma.h"
-
-/* Console USART index */
-#define UARTN      CONFIG_UART_CONSOLE
-#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
-
-#ifdef CONFIG_UART_TX_DMA
-#define UART_TX_INT_ENABLE STM32_USART_CR1_TCIE
-
-#ifndef CONFIG_UART_TX_DMA_CH
-#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX
-#endif
-
-/* DMA channel options; assumes UART1 */
-static const struct dma_option dma_tx_option = {
-	CONFIG_UART_TX_DMA_CH, (void *)&STM32_USART_TDR(UARTN_BASE),
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-#ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH)
-#endif
-};
-
-#else
-#define UART_TX_INT_ENABLE STM32_USART_CR1_TXEIE
-#endif
-
-#ifdef CONFIG_UART_RX_DMA
-
-#ifndef CONFIG_UART_RX_DMA_CH
-#define CONFIG_UART_RX_DMA_CH STM32_DMAC_USART1_RX
-#endif
-/* DMA channel options; assumes UART1 */
-static const struct dma_option dma_rx_option = {
-	CONFIG_UART_RX_DMA_CH, (void *)&STM32_USART_RDR(UARTN_BASE),
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-#ifdef CHIP_FAMILY_STM32F4
-	STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) |
-#endif
-	STM32_DMA_CCR_CIRC
-};
-
-static int dma_rx_len;   /* Size of receive DMA circular buffer */
-#endif
-
-static int init_done;    /* Initialization done? */
-static int should_stop;  /* Last TX control action */
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (STM32_USART_CR1(UARTN_BASE) & UART_TX_INT_ENABLE)
-		return;
-
-	disable_sleep(SLEEP_MASK_UART);
-	should_stop = 0;
-	STM32_USART_CR1(UARTN_BASE) |= UART_TX_INT_ENABLE |
-				       STM32_USART_CR1_TCIE;
-	task_trigger_irq(STM32_IRQ_USART(UARTN));
-}
-
-void uart_tx_stop(void)
-{
-	STM32_USART_CR1(UARTN_BASE) &= ~UART_TX_INT_ENABLE;
-	should_stop = 1;
-#ifdef CONFIG_UART_TX_DMA
-	enable_sleep(SLEEP_MASK_UART);
-#endif
-}
-
-void uart_tx_flush(void)
-{
-	while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE;
-}
-
-#ifdef CONFIG_UART_TX_DMA
-
-int uart_tx_dma_ready(void)
-{
-	return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC;
-}
-
-void uart_tx_dma_start(const char *src, int len)
-{
-	/* Prepare DMA */
-	dma_prepare_tx(&dma_tx_option, len, src);
-
-	/* Force clear TC so we don't re-interrupt */
-	STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC;
-
-	/* Enable TCIE (chrome-os-partner:28837) */
-	STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TCIE;
-
-	/* Start DMA */
-	dma_go(dma_get_channel(dma_tx_option.channel));
-}
-
-#endif /* CONFIG_UART_TX_DMA */
-
-int uart_rx_available(void)
-{
-	return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_RXNE;
-}
-
-#ifdef CONFIG_UART_RX_DMA
-
-void uart_rx_dma_start(char *dest, int len)
-{
-	/* Start receiving */
-	dma_rx_len = len;
-	dma_start_rx(&dma_rx_option, len, dest);
-}
-
-int uart_rx_dma_head(void)
-{
-	return dma_bytes_done(dma_get_channel(CONFIG_UART_RX_DMA_CH),
-			      dma_rx_len);
-}
-
-#endif
-
-void uart_write_char(char c)
-{
-	/* Wait for space */
-	while (!uart_tx_ready())
-		;
-
-	STM32_USART_TDR(UARTN_BASE) = c;
-}
-
-int uart_read_char(void)
-{
-	return STM32_USART_RDR(UARTN_BASE);
-}
-
-/* Interrupt handler for console USART */
-void uart_interrupt(void)
-{
-#ifndef CONFIG_UART_TX_DMA
-	/*
-	 * When transmission completes, enable sleep if we are done with Tx.
-	 * After that, proceed if there is other interrupt to handle.
-	 */
-	if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC) {
-		if (should_stop) {
-			STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE;
-			enable_sleep(SLEEP_MASK_UART);
-		}
-#if defined(CHIP_FAMILY_STM32F4)
-		STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC;
-#else
-		STM32_USART_ICR(UARTN_BASE) |= STM32_USART_SR_TC;
-#endif
-		if (!(STM32_USART_SR(UARTN_BASE) & ~STM32_USART_SR_TC))
-			return;
-	}
-#endif
-
-#ifdef CONFIG_UART_TX_DMA
-	/* Disable transmission complete interrupt if DMA done */
-	if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC)
-		STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE;
-#else
-	/*
-	 * Disable the TX empty interrupt before filling the TX buffer since it
-	 * needs an actual write to DR to be cleared.
-	 */
-	STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TXEIE;
-#endif
-
-#ifndef CONFIG_UART_RX_DMA
-	/*
-	 * Read input FIFO until empty.  DMA-based receive does this from a
-	 * hook in the UART buffering module.
-	 */
-	uart_process_input();
-#endif
-
-	/* Fill output FIFO */
-	uart_process_output();
-
-#ifndef CONFIG_UART_TX_DMA
-	/*
-	 * Re-enable TX empty interrupt only if it was not disabled by
-	 * uart_process_output().
-	 */
-	if (!should_stop)
-		STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TXEIE;
-#endif
-}
-DECLARE_IRQ(STM32_IRQ_USART(UARTN), uart_interrupt, 2);
-
-/**
- * Handle clock frequency changes
- */
-static void uart_freq_change(void)
-{
-	int freq;
-	int div;
-
-#if (defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)) && \
-	(UARTN <= 2)
-	/*
-	 * UART is clocked from HSI (8MHz) to allow it to work when waking
-	 * up from sleep
-	 */
-	freq = 8000000;
-#elif defined(CHIP_FAMILY_STM32H7)
-	freq = 64000000; /* from 64 Mhz HSI */
-#elif defined(CHIP_FAMILY_STM32L4)
-	/* UART clocked from HSI 16 */
-	freq = 16000000;
-#else
-	/* UART clocked from the main clock */
-	freq = clock_get_freq();
-#endif
-
-#if (UARTN == 9)	/* LPUART */
-	div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE) * 256;
-#else
-	div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE);
-#endif
-
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \
-	defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32G4)
-	if (div / 16 > 0) {
-		/*
-		 * CPU clock is high enough to support x16 oversampling.
-		 * BRR = (div mantissa)<<4 | (4-bit div fraction)
-		 */
-		STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_OVER8;
-		STM32_USART_BRR(UARTN_BASE) = div;
-	} else {
-		/*
-		 * CPU clock is low; use x8 oversampling.
-		 * BRR = (div mantissa)<<4 | (3-bit div fraction)
-		 */
-		STM32_USART_BRR(UARTN_BASE) = ((div / 8) << 4) | (div & 7);
-		STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_OVER8;
-	}
-#else
-	/* STM32F only supports x16 oversampling */
-	STM32_USART_BRR(UARTN_BASE) = div;
-#endif
-
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT);
-
-void uart_init(void)
-{
-	/* Select clock source */
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-#if (UARTN == 1)
-	STM32_RCC_CFGR3 |= 0x0003;   /* USART1 clock source from HSI(8MHz) */
-#elif (UARTN == 2)
-	STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */
-#endif /* UARTN */
-#elif defined(CHIP_FAMILY_STM32H7) /* Clocked from 64 Mhz HSI */
-#if ((UARTN == 1) || (UARTN == 6))
-	STM32_RCC_D2CCIP2R |= STM32_RCC_D2CCIP2_USART16SEL_HSI;
-#else
-	STM32_RCC_D2CCIP2R |= STM32_RCC_D2CCIP2_USART234578SEL_HSI;
-#endif /* UARTN */
-#elif defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32G4)
-	/* USART1 clock source from SYSCLK */
-	STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_USART1SEL_MASK;
-#ifdef CHIP_FAMILY_STM32L4
-	/* For STM32L4, use HSI for UART, to wake up from low power mode */
-	STM32_RCC_CCIPR |=
-		(STM32_RCC_CCIPR_UART_HSI16 << STM32_RCC_CCIPR_USART1SEL_SHIFT);
-#else
-	STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_UART_SYSCLK
-			    << STM32_RCC_CCIPR_USART1SEL_SHIFT);
-#endif
-	/* LPUART1 clock source from SYSCLK */
-	STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_LPUART1SEL_MASK;
-	STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_UART_SYSCLK
-			    << STM32_RCC_CCIPR_LPUART1SEL_SHIFT);
-#endif /* CHIP_FAMILY_STM32F0 || CHIP_FAMILY_STM32F3 */
-
-	/* Enable USART clock */
-#if (UARTN == 1)
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1;
-#ifdef CHIP_FAMILY_STM32L4
-#if defined(CONFIG_UART_RX_DMA) || defined(CONFIG_UART_TX_DMA)
-	STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA1;
-	STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA2;
-#endif
-#endif
-#elif (UARTN == 6)
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART6;
-#elif (UARTN == 9)
-	STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_LPUART1EN;
-#else
-	STM32_RCC_APB1ENR |= CONCAT2(STM32_RCC_PB1_USART, UARTN);
-#endif
-
-	/*
-	 * For STM32F3, A delay of 1 APB clock cycles is needed before we
-	 * can access any USART register. Fortunately, we have
-	 * gpio_config_module() below and thus don't need to add the delay.
-	 */
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_UART, 1);
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \
-|| defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4)
-	/*
-	 * Wake up on start bit detection. WUS can only be written when UE=0,
-	 * so clear UE first.
-	 */
-	STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UE;
-
-	/*
-	 * Also disable the RX overrun interrupt, since we don't care about it
-	 * and we don't want to clear an extra flag in the interrupt
-	 */
-	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT |
-	                               STM32_USART_CR3_OVRDIS;
-#endif
-
-	/*
-	 * UART enabled, 8 Data bits, oversampling x16, no parity,
-	 * TX and RX enabled.
-	 */
-#ifdef CHIP_FAMILY_STM32L4
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_TE | STM32_USART_CR1_RE;
-#else
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
-#endif
-
-	/* 1 stop bit, no fancy stuff */
-	STM32_USART_CR2(UARTN_BASE) = 0x0000;
-
-#ifdef CONFIG_UART_TX_DMA
-	/* Enable DMA transmitter */
-	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAT;
-#ifdef CONFIG_UART_TX_DMA_PH
-	dma_select_channel(CONFIG_UART_TX_DMA_CH, CONFIG_UART_TX_DMA_PH);
-#endif
-#else
-	/* DMA disabled, special modes disabled, error interrupt disabled */
-	STM32_USART_CR3(UARTN_BASE) &= ~STM32_USART_CR3_DMAR &
-				       ~STM32_USART_CR3_DMAT &
-				       ~STM32_USART_CR3_EIE;
-#endif
-
-#ifdef CONFIG_UART_RX_DMA
-	/* Enable DMA receiver */
-	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAR;
-#else
-	/* Enable receive-not-empty interrupt */
-	STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_RXNEIE;
-#endif
-
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4)
-	/* Use single-bit sampling */
-	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_ONEBIT;
-#endif
-
-	/* Set initial baud rate */
-	uart_freq_change();
-
-	/* Enable interrupts */
-	task_enable_irq(STM32_IRQ_USART(UARTN));
-
-#ifdef CHIP_FAMILY_STM32L4
-	STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UE;
-#endif
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_FORCE_CONSOLE_RESUME
-void uart_enable_wakeup(int enable)
-{
-	if (enable) {
-		/*
-		 * Allow UART wake up from STOP mode. Note, UART clock must
-		 * be HSI(8MHz) for wakeup to work.
-		 */
-		STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UESM;
-		STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUFIE;
-	} else {
-		/* Disable wake up from STOP mode. */
-		STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UESM;
-	}
-}
-#endif
diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c
deleted file mode 100644
index ef6ec92a89..0000000000
--- a/chip/stm32/ucpd-stm32gx.c
+++ /dev/null
@@ -1,1615 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32GX UCPD module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "driver/tcpm/tcpm.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "ucpd-stm32gx.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define USB_VID_STM32 0x0483
-
-/*
- * USB PD message buffer length. Absent extended messages, the longest PD
- * message will be 7 objects (4 bytes each) plus a 2 byte header. TCPMv2
- * suports extended messages via chunking so the data buffer length is
- * set assumign that extended messages are chunked.
- */
-#define UCPD_BUF_LEN 30
-
-#define UCPD_IMR_RX_INT_MASK (STM32_UCPD_IMR_RXNEIE| \
-			      STM32_UCPD_IMR_RXORDDETIE | \
-			      STM32_UCPD_IMR_RXHRSTDETIE |	\
-			      STM32_UCPD_IMR_RXOVRIE |		\
-			      STM32_UCPD_IMR_RXMSGENDIE)
-
-#define UCPD_IMR_TX_INT_MASK (STM32_UCPD_IMR_TXISIE | \
-			      STM32_UCPD_IMR_TXMSGDISCIE |     \
-			      STM32_UCPD_IMR_TXMSGSENTIE |     \
-			      STM32_UCPD_IMR_TXMSGABTIE |      \
-			      STM32_UCPD_IMR_TXUNDIE)
-
-#define UCPD_ICR_TX_INT_MASK (STM32_UCPD_ICR_TXMSGDISCCF | \
-			      STM32_UCPD_ICR_TXMSGSENTCF |     \
-			      STM32_UCPD_ICR_TXMSGABTCF |     \
-			      STM32_UCPD_ICR_TXUNDCF)
-
-#define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3)
-#define UCPD_RP_TO_ANASUB(r) ((r + 1) & 0x3)
-
-struct msg_header_info {
-	enum pd_power_role pr;
-	enum pd_data_role dr;
-};
-static struct msg_header_info msg_header;
-
-/* States for managing tx messages in ucpd task */
-enum ucpd_state {
-	STATE_IDLE,
-	STATE_ACTIVE_TCPM,
-	STATE_ACTIVE_CRC,
-	STATE_HARD_RESET,
-	STATE_WAIT_CRC_ACK,
-};
-
-/* Events for pd_interrupt_handler_task */
-#define UCPD_EVT_GOOD_CRC_REQ   BIT(0)
-#define UCPD_EVT_TCPM_MSG_REQ   BIT(1)
-#define UCPD_EVT_HR_REQ         BIT(2)
-#define UCPD_EVT_TX_MSG_FAIL    BIT(3)
-#define UCPD_EVT_TX_MSG_DISC    BIT(4)
-#define UCPD_EVT_TX_MSG_SUCCESS BIT(5)
-#define UCPD_EVT_HR_DONE        BIT(6)
-#define UCPD_EVT_HR_FAIL        BIT(7)
-#define UCPD_EVT_RX_GOOD_CRC    BIT(8)
-#define UCPD_EVT_RX_MSG         BIT(9)
-
-#define UCPD_T_RECEIVE_US (1 * MSEC)
-
-#define UCPD_N_RETRY_COUNT_REV20 3
-#define UCPD_N_RETRY_COUNT_REV30 2
-
-/*
- * Tx messages are iniated either by TCPM/PRL layer or from ucpd when a GoodCRC
- * ack message needs to be sent.
- */
-enum ucpd_tx_msg {
-	TX_MSG_NONE = -1,
-	TX_MSG_TCPM = 0,
-	TX_MSG_GOOD_CRC = 1,
-	TX_MSG_TOTAL = 2,
-};
-
-#define MSG_TCPM_MASK BIT(TX_MSG_TCPM)
-#define MSG_GOOD_CRC_MASK BIT(TX_MSG_GOOD_CRC)
-
-union buffer {
-	uint16_t header;
-	uint8_t msg[UCPD_BUF_LEN];
-};
-
-struct ucpd_tx_desc {
-	enum tcpci_msg_type type;
-	int msg_len;
-	int msg_index;
-	union buffer data;
-};
-
-/* Track VCONN on/off state */
-static int ucpd_vconn_enable;
-
-/* Tx message variables */
-struct ucpd_tx_desc ucpd_tx_buffers[TX_MSG_TOTAL];
-struct ucpd_tx_desc *ucpd_tx_active_buffer;
-static int ucpd_tx_request;
-static int ucpd_timeout_us;
-static enum ucpd_state ucpd_tx_state;
-static int msg_id_match;
-static int tx_retry_count;
-static int tx_retry_max;
-
-static int ucpd_txorderset[] = {
-	TX_ORDERSET_SOP,
-	TX_ORDERSET_SOP_PRIME,
-	TX_ORDERSET_SOP_PRIME_PRIME,
-	TX_ORDERSET_SOP_PRIME_DEBUG,
-	TX_ORDERSET_SOP_PRIME_PRIME_DEBUG,
-	TX_ORDERSET_HARD_RESET,
-	TX_ORDERSET_CABLE_RESET,
-};
-
-/* PD Rx variables */
-static int ucpd_rx_byte_count;
-static uint8_t ucpd_rx_buffer[UCPD_BUF_LEN];
-static int ucpd_crc_id;
-static bool ucpd_rx_sop_prime_enabled;
-static int ucpd_rx_msg_active;
-static bool ucpd_rx_bist_mode;
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-/* Defines and macros for ucpd state logging */
-#define TX_STATE_LOG_LEN BIT(5)
-#define TX_STATE_LOG_MASK (TX_STATE_LOG_LEN - 1)
-
-struct ucpd_tx_state {
-	uint32_t ts;
-	int tx_request;
-	int timeout_us;
-	enum ucpd_state enter_state;
-	enum ucpd_state exit_state;
-	uint32_t evt;
-};
-
-struct ucpd_tx_state ucpd_tx_statelog[TX_STATE_LOG_LEN];
-int ucpd_tx_state_log_idx;
-int ucpd_tx_state_log_freeze;
-
-static char ucpd_names[][12] = {
-	"TX_IDLE",
-	"ACT_TCPM",
-	"ACT_CRC",
-	"HARD_RST",
-	"WAIT_CRC",
-};
-/* Defines and macros used for ucpd pd message logging */
-#define MSG_LOG_LEN 64
-#define MSG_BUF_LEN 10
-
-struct msg_info {
-	uint8_t dir;
-	uint8_t comp;
-	uint8_t crc;
-	uint16_t header;
-	uint32_t ts;
-	uint8_t buf[MSG_BUF_LEN];
-};
-static int msg_log_cnt;
-static int msg_log_idx;
-static struct msg_info msg_log[MSG_LOG_LEN];
-
-#define UCPD_CC_STRING_LEN 5
-
-static char ccx[4][UCPD_CC_STRING_LEN] = {
-	"Ra",
-	"Rp",
-	"Rd",
-	"Open",
-};
-static char rp_string[][8] = {
-	"Rp_usb",
-	"Rp_1.5",
-	"Rp_3.0",
-	"Open",
-};
-static int ucpd_sr_cc_event;
-static int ucpd_cc_set_save;
-static int ucpd_cc_change_log;
-
-static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line);
-
-static void ucpd_log_add_msg(uint16_t header, int dir)
-{
-	uint32_t ts = __hw_clock_source_read();
-	int idx = msg_log_idx;
-	uint8_t *buf = dir ? ucpd_rx_buffer : ucpd_tx_active_buffer->data.msg;
-
-	/*
-	 * Add a msg entry in the history log. The log is currently designed to
-	 * be from reset until MSG_LOG_LEN messages have been added.
-	 * ts -> lower 32 bits of 1 uSec running clock
-	 * dir -> 0 = tx message, 1 = rx message
-	 * comp -> ucpd transmit success
-	 * crc -> GoodCrc received following tx message
-	 */
-	if (msg_log_cnt++ < MSG_LOG_LEN) {
-		int msg_bytes = MIN((PD_HEADER_CNT(header) << 2) + 2,
-				    MSG_BUF_LEN);
-
-		msg_log[idx].header = header;
-		msg_log[idx].ts = ts;
-		msg_log[idx].dir = dir;
-		msg_log[idx].comp = 0;
-		msg_log[idx].crc = 0;
-		msg_log_idx++;
-		memcpy(msg_log[idx].buf, buf, msg_bytes);
-	}
-}
-
-static void ucpd_log_mark_tx_comp(void)
-{
-	/*
-	 * This msg logging utility function is used to mark when a message was
-	 * successfully transmitted when transmit interrupt occurs and the tx
-	 * message sent status was set. Because the transmit message is added
-	 * before it's sent by ucpd, the index has to back up one to mark the
-	 * correct log entry.
-	 */
-	if (msg_log_cnt < MSG_LOG_LEN) {
-		if (msg_log_idx > 0)
-			msg_log[msg_log_idx - 1].comp = 1;
-	}
-}
-
-static void ucpd_log_mark_crc(void)
-{
-	/*
-	 * This msg logging utility function is used to mark when a GoodCRC
-	 * message is received following a tx message. This status is displayed
-	 * in column s2. Because this indication follows both transmit message
-	 * and GoodCRC rx, the index must be back up 2 rows to mark the correct
-	 * tx message entry.
-	 */
-	if (msg_log_cnt < MSG_LOG_LEN) {
-		if (msg_log_idx >= 2)
-			msg_log[msg_log_idx - 2].crc = 1;
-	}
-}
-
-static void ucpd_cc_status(int port)
-{
-	int rc = stm32gx_ucpd_get_role_control(port);
-	int cc1_pull, cc2_pull;
-	enum tcpc_cc_voltage_status v_cc1, v_cc2;
-	int rv;
-	char *rp_name;
-
-	cc1_pull = rc & 0x3;
-	cc2_pull = (rc >> 2) & 0x3;
-
-	/*
-	 * This function is used to display CC settings, including pull type,
-	 * and if Rp, what the Rp value is set to. In addition, the current
-	 * values of CC voltage detector, polarity, and PD enable status are
-	 * displayed.
-	 */
-	rv = stm32gx_ucpd_get_cc(port,&v_cc1, &v_cc2);
-	rp_name = rp_string[(rc >> 4) % 0x3];
-	ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n",
-		 ccx[cc1_pull], ccx[cc2_pull], rp_name);
-	if (!rv)
-		ccprintf("\tcc1_v\t = %d\n\tcc2_v\t = %d\n", v_cc1, v_cc2);
-}
-
-void ucpd_cc_detect_notify_enable(int enable)
-{
-	/*
-	 * This variable is used to control when a CC detach detector is
-	 * active.
-	 */
-	ucpd_cc_change_log = enable;
-}
-
-static void ucpd_log_invalidate_entry(void)
-{
-	/*
-	 * This is a msg log utility function which is triggered when an
-	 * unexpected detach event is detected.
-	 */
-	if (msg_log_idx < (MSG_LOG_LEN - 1)) {
-		int idx = msg_log_idx;
-
-		msg_log[idx].header = 0xabcd;
-		msg_log[idx].ts = __hw_clock_source_read();
-		msg_log[idx].dir = 0;
-		msg_log[idx].comp = 0;
-		msg_log[idx].crc = 0;
-		msg_log_cnt++;
-		msg_log_idx++;
-	}
-}
-
-/*
- * This function will mark in the msg log when a detach event occurs. It will
- * only be active if ucpd_cc_change_log is set which can be controlled via the
- * ucpd console command.
- */
-static void ucpd_cc_change_notify(void)
-{
-	if (ucpd_cc_change_log) {
-		uint32_t sr = ucpd_sr_cc_event;
-
-		ucpd_log_invalidate_entry();
-
-		ccprintf("vstate: cc1 = %x, cc2 = %x, Rp = %d\n",
-			 (sr >> STM32_UCPD_SR_VSTATE_CC1_SHIFT) & 0x3,
-			 (sr >> STM32_UCPD_SR_VSTATE_CC2_SHIFT) & 0x3,
-			 (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT)
-			 & 0x3);
-		/* Display CC status on EC console */
-		ucpd_cc_status(0);
-	}
-}
-DECLARE_DEFERRED(ucpd_cc_change_notify);
-#endif /* CONFIG_STM32G4_UCPD_DEBUG */
-
-static int ucpd_msg_is_good_crc(uint16_t header)
-{
-	/*
-	 * Good CRC is a control message (no data objects) with GOOD_CRC message
-	 * type in the header.
-	 */
-	return ((PD_HEADER_CNT(header) == 0) && (PD_HEADER_EXT(header) == 0) &&
-		(PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ? 1 : 0;
-}
-
-static void ucpd_hard_reset_rx_log(void)
-{
-	CPRINTS("ucpd: hard reset recieved");
-}
-DECLARE_DEFERRED(ucpd_hard_reset_rx_log);
-
-static void ucpd_port_enable(int port, int enable)
-{
-	if (enable)
-		STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_UCPDEN;
-	else
-		STM32_UCPD_CFGR1(port) &= ~STM32_UCPD_CFGR1_UCPDEN;
-}
-
-static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line)
-{
-	int cc_enable = (STM32_UCPD_CR(port) & STM32_UCPD_CR_CCENABLE_MASK) >>
-					       STM32_UCPD_CR_CCENABLE_SHIFT;
-
-	return ((cc_enable >> cc_line) & 0x1);
-}
-
-static void ucpd_tx_data_byte(int port)
-{
-	int index = ucpd_tx_active_buffer->msg_index++;
-
-	STM32_UCPD_TXDR(port) = ucpd_tx_active_buffer->data.msg[index];
-}
-
-static void ucpd_rx_data_byte(int port)
-{
-	if (ucpd_rx_byte_count < UCPD_BUF_LEN)
-		ucpd_rx_buffer[ucpd_rx_byte_count++] = STM32_UCPD_RXDR(port);
-}
-
-static void ucpd_tx_interrupts_enable(int port, int enable)
-{
-	if (enable) {
-		STM32_UCPD_ICR(port) = UCPD_ICR_TX_INT_MASK;
-		STM32_UCPD_IMR(port) |= UCPD_IMR_TX_INT_MASK;
-	} else {
-		STM32_UCPD_IMR(port) &= ~UCPD_IMR_TX_INT_MASK;
-	}
-}
-
-static void ucpd_rx_enque_error(void)
-{
-	CPRINTS("ucpd: TCPM Enque Error!!");
-}
-DECLARE_DEFERRED(ucpd_rx_enque_error);
-
-static void stm32gx_ucpd_state_init(int port)
-{
-	/* Init variables used to manage tx process */
-	ucpd_tx_request = 0;
-	tx_retry_count = 0;
-	ucpd_tx_state = STATE_IDLE;
-	ucpd_timeout_us = -1;
-
-	/* Init variables used to manage rx */
-	ucpd_rx_sop_prime_enabled = 0;
-	ucpd_rx_msg_active = 0;
-	ucpd_rx_bist_mode = 0;
-
-	/* Vconn tracking variable */
-	ucpd_vconn_enable = 0;
-}
-
-int stm32gx_ucpd_init(int port)
-{
-	uint32_t cfgr1_reg;
-	uint32_t moder_reg;
-
-	/* Disable UCPD interrupts */
-	task_disable_irq(STM32_IRQ_UCPD1);
-
-	/*
-	* After exiting reset, stm32gx will have dead battery mode enabled by
-	* default which connects Rd to CC1/CC2. This should be disabled when EC
-	* is powered up.
-	*/
-	STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS;
-
-	/* Ensure that clock to UCPD is enabled */
-	STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_UPCD1EN;
-
-	/* Make sure CC1/CC2 pins PB4/PB6 are set for analog mode */
-	moder_reg = STM32_GPIO_MODER(GPIO_B);
-	moder_reg |= 0x3300;
-	STM32_GPIO_MODER(GPIO_B) = moder_reg;
-	/*
-	 * CFGR1 must be written when UCPD peripheral is disabled. Note that
-	 * disabling ucpd causes the peripheral to quit any ongoing activity and
-	 * sets all ucpd registers back their default values.
-	 */
-	ucpd_port_enable(port, 0);
-
-	cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) |
-		STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
-		STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
-		STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
-	STM32_UCPD_CFGR1(port) = cfgr1_reg;
-
-	/*
-	 * Set RXORDSETEN field to control which types of ordered sets the PD
-	 * receiver must receive.
-	 * SOP, SOP', Hard Reset Det, Cable Reset Det enabled
-	 */
-	STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_RXORDSETEN_VAL(0x1B);
-
-	/* Enable ucpd  */
-	ucpd_port_enable(port, 1);
-
-	/* Configure CC change interrupts */
-	STM32_UCPD_IMR(port) = STM32_UCPD_IMR_TYPECEVT1IE |
-		STM32_UCPD_IMR_TYPECEVT2IE;
-	STM32_UCPD_ICR(port) = STM32_UCPD_ICR_TYPECEVT1CF |
-		STM32_UCPD_ICR_TYPECEVT2CF;
-
-	/* SOP'/SOP'' must be enabled via TCPCI call */
-	ucpd_rx_sop_prime_enabled = false;
-
-	stm32gx_ucpd_state_init(port);
-
-	/* Enable UCPD interrupts */
-	task_enable_irq(STM32_IRQ_UCPD1);
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_release(int port)
-{
-	ucpd_port_enable(port, 0);
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	int vstate_cc1;
-	int vstate_cc2;
-	int anamode;
-	uint32_t sr;
-
-	/*
-	 * cc_voltage_status is determined from vstate_cc bit field in the
-	 * status register. The meaning of the value vstate_cc depends on
-	 * current value of ANAMODE (src/snk).
-	 *
-	 * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1,
-	 * but needs to be modified slightly for case ANAMODE = 0.
-         *
-	 * If presenting Rp (source), then need to to a circular shift of
-	 * vstate_ccx value:
-	 *     vstate_cc | cc_state
-	 *     ------------------
-	 *        0     ->    1
-	 *        1     ->    2
-	 *        2     ->    0
-	 */
-
-	/* Get vstate_ccx values and power role */
-	sr = STM32_UCPD_SR(port);
-	/* Get Rp or Rd active */
-	anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
-	vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC1_SHIFT;
-	vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC2_SHIFT;
-
-	/* Do circular shift if port == source */
-	if (anamode) {
-		if (vstate_cc1 != STM32_UCPD_SR_VSTATE_RA)
-			vstate_cc1 += 4;
-		if (vstate_cc2 != STM32_UCPD_SR_VSTATE_RA)
-			vstate_cc2 += 4;
-	} else {
-		if (vstate_cc1 != STM32_UCPD_SR_VSTATE_OPEN)
-			vstate_cc1 = (vstate_cc1 + 1) % 3;
-		if (vstate_cc2 != STM32_UCPD_SR_VSTATE_OPEN)
-			vstate_cc2 = (vstate_cc2 + 1) % 3;
-	}
-
-	*cc1 = vstate_cc1;
-	*cc2 = vstate_cc2;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_get_role_control(int port)
-{
-	int role_control;
-	int cc1;
-	int cc2;
-	int anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
-	int anasubmode = (STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK)
-		>> STM32_UCPD_CR_ANASUBMODE_SHIFT;
-
-	/*
-	 * Role control register is defined as:
-	 *     R_cc1 -> b 1:0
-	 *     R_cc2 -> b 3:2
-	 *     Rp    -> b 5:4
-	 *
-	 * In TCPCI, CCx is defined as:
-	 *    00b -> Ra
-	 *    01b -> Rp
-	 *    10b -> Rd
-	 *    11b -> Open (don't care)
-	 *
-	 * For ucpd, this information is encoded in ANAMODE and ANASUBMODE
-	 * fields as follows:
-	 *   ANAMODE            CCx
-	 *     0   ->    Rp   -> 1
-	 *     1   ->    Rd   -> 2
-	 *
-	 *   ANASUBMODE:
-	 *     00b -> TYPEC_RP_RESERVED (open)
-	 *     01b -> TYPEC_RP_USB
-	 *     10b -> TYPEC_RP_1A5
-	 *     11b -> TYPEC_RP_3A0
-	 *
-	 *   CCx = ANAMODE + 1, if CCx is enabled
-	 *   Rp  = (ANASUBMODE - 1) & 0x3
-	 */
-	cc1 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_1) ? anamode + 1 :
-		TYPEC_CC_OPEN;
-	cc2 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_2) ? anamode + 1 :
-		TYPEC_CC_OPEN;
-	role_control = cc1 | (cc2 << 2);
-	/* Circular shift anasubmode to convert to Rp range */
-	role_control |= (UCPD_ANASUB_TO_RP(anasubmode) << 4);
-
-	return role_control;
-}
-
-static uint32_t ucpd_get_cc_enable_mask(int port)
-{
-	uint32_t mask = STM32_UCPD_CR_CCENABLE_MASK;
-
-	if (ucpd_vconn_enable) {
-		uint32_t cr = STM32_UCPD_CR(port);
-		int pol = !!(cr & STM32_UCPD_CR_PHYCCSEL);
-
-		mask &= ~(1 << (STM32_UCPD_CR_CCENABLE_SHIFT + !pol));
-	}
-
-	return mask;
-}
-
-int stm32gx_ucpd_vconn_disc_rp(int port, int enable)
-{
-	int cr;
-
-	/* Update VCONN on/off status. Do this before getting cc enable mask */
-	ucpd_vconn_enable = enable;
-
-	cr = STM32_UCPD_CR(port);
-	cr &= ~STM32_UCPD_CR_CCENABLE_MASK;
-	cr |= ucpd_get_cc_enable_mask(port);
-
-	/* Apply cc pull resistor change */
-	STM32_UCPD_CR(port) = cr;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp)
-{
-	uint32_t cr = STM32_UCPD_CR(port);
-
-	/*
-	 * Always set ANASUBMODE to match desired Rp. TCPM layer has a valid
-	 * range of 0, 1, or 2. This range maps to 1, 2, or 3 in ucpd for
-	 * ANASUBMODE.
-	 */
-	cr &= ~STM32_UCPD_CR_ANASUBMODE_MASK;
-	cr |= STM32_UCPD_CR_ANASUBMODE_VAL(UCPD_RP_TO_ANASUB(rp));
-
-	/* Disconnect both pull from both CC lines for R_open case */
-	cr &= ~STM32_UCPD_CR_CCENABLE_MASK;
-	/* Set ANAMODE if cc_pull is Rd */
-	if (cc_pull == TYPEC_CC_RD) {
-		cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK;
-	/* Clear ANAMODE if cc_pull is Rp */
-	} else if (cc_pull == TYPEC_CC_RP) {
-		cr &= ~(STM32_UCPD_CR_ANAMODE);
-		cr |= ucpd_get_cc_enable_mask(port);
-	}
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-	if (ucpd_cc_change_log) {
-		CPRINTS("ucpd: set_cc: pull = %d, rp = %d", cc_pull, rp);
-	}
-#endif
-	/* Update pull values */
-	STM32_UCPD_CR(port) = cr;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity) {
-	/*
-	 * Polarity impacts the PHYCCSEL, CCENABLE, and CCxTCDIS fields. This
-	 * function is called when polarity is updated at TCPM layer. STM32Gx
-	 * only supports POLARITY_CC1 or POLARITY_CC2 and this is stored in the
-	 * PHYCCSEL bit in the CR register.
-	 */
-	if (polarity > POLARITY_CC2)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	if (polarity == POLARITY_CC1)
-		STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_PHYCCSEL;
-	else if (polarity == POLARITY_CC2)
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_PHYCCSEL;
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-	ucpd_cc_set_save = STM32_UCPD_CR(port);
-#endif
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_set_rx_enable(int port, int enable)
-{
-	/*
-	 * USB PD receiver enable is controlled by the bit PHYRXEN in
-	 * UCPD_CR. Enable Rx interrupts when RX PD decoder is active.
-	 */
-	if (enable) {
-		STM32_UCPD_ICR(port) = UCPD_IMR_RX_INT_MASK;
-		STM32_UCPD_IMR(port) |= UCPD_IMR_RX_INT_MASK;
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_PHYRXEN;
-	} else {
-		STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_PHYRXEN;
-		STM32_UCPD_IMR(port) &= ~UCPD_IMR_RX_INT_MASK;
-	}
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role)
-{
-	msg_header.pr = power_role;
-	msg_header.dr = data_role;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_sop_prime_enable(int port, bool enable)
-{
-	/* Update static varialbe used to filter SOP//SOP'' messages */
-	ucpd_rx_sop_prime_enabled = enable;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
-{
-	chip_info->vendor_id = USB_VID_STM32;
-	chip_info->product_id = 0;
-	chip_info->device_id = STM32_DBGMCU_IDCODE & 0xfff;
-	chip_info->fw_version_number = 0xEC;
-
-	return EC_SUCCESS;
-}
-
-static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type)
-{
-	enum tcpci_msg_type type;
-
-	/* Select the correct tx desciptor */
-	ucpd_tx_active_buffer = &ucpd_tx_buffers[msg_type];
-	type = ucpd_tx_active_buffer->type;
-
-	if (type == TCPCI_MSG_TX_HARD_RESET) {
-				/*
-		 * From RM0440 45.4.4:
-		 * In order to facilitate generation of a Hard Reset, a special
-		 * code of TXMODE field is used. No other fields need to be
-		 * written. On writing the correct code, the hardware forces
-		 * Hard Reset Tx under the correct (optimal) timings with
-		 * respect to an on-going Tx message, which (if still in
-		 * progress) is cleanly terminated by truncating the current
-		 * sequence and directly appending an EOP K-code sequence. No
-		 * specific interrupt is generated relating to this truncation
-		 * event.
-		 *
-		 * Because Hard Reset can interrupt ongoing Tx operations, it is
-		 * started differently than all other tx messages. Only need to
-		 * enable hard reset interrupts, and then set a bit in the CR
-		 * register to initiate.
-		 */
-		/* Enable interrupt for Hard Reset sent/discarded */
-		STM32_UCPD_ICR(port) = STM32_UCPD_ICR_HRSTDISCCF |
-			STM32_UCPD_ICR_HRSTSENTCF;
-		STM32_UCPD_IMR(port) |= STM32_UCPD_IMR_HRSTDISCIE |
-			STM32_UCPD_IMR_HRSTSENTIE;
-		/* Initiate Hard Reset */
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXHRST;
-	} else if (type != TCPCI_MSG_INVALID) {
-		int msg_len = 0;
-		int mode;
-
-		/*
-		 * These types are normal transmission, TXMODE = 0. To transmit
-		 * regular message, control or data, requires the following:
-		 *     1. Set TXMODE:
-		 *          Normal -> 0
-		 *          Cable Reset -> 1
-		 *          Bist -> 2
-		 *     2. Set TX_ORDSETR based on message type
-		 *     3. Set TX_PAYSZR which must account for 2 bytes of header
-		 *     4. Configure DMA (optional if DMA is desired)
-		 *     5. Enable transmit interrupts
-		 *     6. Start TX by setting TXSEND in CR
-		 *
-		 */
-
-		/*
-		 * Set tx length parameter (in bytes). Note the count field in
-		 * the header is number of 32 bit objects. Also, the length
-		 * field must account for the 2 header bytes.
-		 */
-		if (type == TCPCI_MSG_TX_BIST_MODE_2) {
-			mode = STM32_UCPD_CR_TXMODE_BIST;
-		} else if (type == TCPCI_MSG_CABLE_RESET) {
-			mode = STM32_UCPD_CR_TXMODE_CBL_RST;
-		} else {
-			mode = STM32_UCPD_CR_TXMODE_DEF;
-			msg_len = ucpd_tx_active_buffer->msg_len;
-		}
-
-		STM32_UCPD_TX_PAYSZR(port) = msg_len;
-
-		/* Set tx mode */
-		STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_TXMODE_MASK;
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXMODE_VAL(mode);
-
-		/* Index into ordset enum for start of packet */
-		if (type <= TCPCI_MSG_CABLE_RESET)
-			STM32_UCPD_TX_ORDSETR(port) = ucpd_txorderset[type];
-		else
-			STM32_UCPD_TX_ORDSETR(port) =
-				ucpd_txorderset[TX_ORDERSET_SOP];
-
-		/* Reset msg byte index */
-		ucpd_tx_active_buffer-> msg_index = 0;
-
-		/* Enable interrupts */
-		ucpd_tx_interrupts_enable(port, 1);
-
-		/* Trigger ucpd peripheral to start pd message transmit */
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXSEND;
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-		ucpd_log_add_msg(ucpd_tx_active_buffer->data.header, 0);
-#endif
-	}
-
-	return EC_SUCCESS;
-}
-
-static void ucpd_set_tx_state(enum ucpd_state state)
-{
-	ucpd_tx_state = state;
-}
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-static void ucpd_task_log(int timeout, enum ucpd_state enter,
-			  enum ucpd_state exit, int req, uint32_t evt)
-{
-	static int same_count = 0;
-	int idx = ucpd_tx_state_log_idx;
-
-	if (ucpd_tx_state_log_freeze)
-		return;
-
-	ucpd_tx_statelog[idx].ts = get_time().le.lo;
-	ucpd_tx_statelog[idx].tx_request = req;
-	ucpd_tx_statelog[idx].timeout_us = timeout;
-	ucpd_tx_statelog[idx].enter_state = enter;
-	ucpd_tx_statelog[idx].exit_state = exit;
-	ucpd_tx_statelog[idx].evt = evt;
-
-	ucpd_tx_state_log_idx = (idx + 1) & TX_STATE_LOG_MASK;
-
-	if (enter == exit) {
-		same_count++;
-	} else {
-		same_count = 0;
-	}
-
-	/*
-	 * Should not have same enter/exit states. If this happens, then freeze
-	 * state log to help in debugging.
-	 */
-	if (same_count > 5)
-		ucpd_tx_state_log_freeze = 1;
-}
-
-static void ucpd_task_log_dump(void)
-{
-	int n;
-	int idx;
-
-	ucpd_tx_state_log_freeze = 1;
-
-	/* current index will be oldest entry in the log */
-	idx = ucpd_tx_state_log_idx;
-
-	ccprintf("\n\t UCDP Task Log\n");
-	for (n = 0; n < TX_STATE_LOG_LEN; n++) {
-		ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n",
-			 n,
-			 ucpd_names[ucpd_tx_statelog[idx].enter_state],
-			 ucpd_names[ucpd_tx_statelog[idx].exit_state],
-			 ucpd_tx_statelog[idx].tx_request,
-			 ucpd_tx_statelog[idx].evt,
-			 ucpd_tx_statelog[idx].ts,
-			 ucpd_tx_statelog[idx].timeout_us);
-
-		idx = (idx + 1) & TX_STATE_LOG_MASK;
-		msleep(5);
-	}
-
-	ucpd_tx_state_log_freeze = 0;
-}
-#endif
-
-static void ucpd_manage_tx(int port, int evt)
-{
-	enum ucpd_tx_msg msg_src = TX_MSG_NONE;
-	uint16_t hdr;
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-	enum ucpd_state enter = ucpd_tx_state;
-	int req = ucpd_tx_request;
-#endif
-
-	if (evt & UCPD_EVT_HR_REQ) {
-		/*
-		 * Hard reset control messages are treated as a priority. The
-		 * control message will already be set up as it comes from the
-		 * PRL layer like any other PD ctrl/data message. So just need
-		 * to indicate the correct message source and set the state to
-		 * hard reset here.
-		 */
-		ucpd_set_tx_state(STATE_HARD_RESET);
-		msg_src = TX_MSG_TCPM;
-		ucpd_tx_request &= ~(1 << msg_src);
-	}
-
-	switch (ucpd_tx_state) {
-	case STATE_IDLE:
-		if (ucpd_tx_request & MSG_GOOD_CRC_MASK) {
-			ucpd_set_tx_state(STATE_ACTIVE_CRC);
-			msg_src = TX_MSG_GOOD_CRC;
-		} else if (ucpd_tx_request & MSG_TCPM_MASK) {
-			if (evt & UCPD_EVT_RX_MSG) {
-				/*
-				 * USB-PD Specification rev 3.0, section 6.10
-				 * On receiving a received message, the protocol
-				 * layer shall discard any pending message.
-				 *
-				 * Since the pending message from the PRL has
-				 * not been sent yet, it needs to be discarded
-				 * based on the received message event.
-				 */
-				pd_transmit_complete(port,
-						     TCPC_TX_COMPLETE_DISCARDED);
-				ucpd_tx_request &= ~MSG_TCPM_MASK;
-			} else if (!ucpd_rx_msg_active) {
-				ucpd_set_tx_state(STATE_ACTIVE_TCPM);
-				msg_src = TX_MSG_TCPM;
-				/* Save msgID required for GoodCRC check */
-				hdr = ucpd_tx_buffers[TX_MSG_TCPM].data.header;
-				msg_id_match = PD_HEADER_ID(hdr);
-				tx_retry_max = PD_HEADER_REV(hdr) == PD_REV30 ?
-					UCPD_N_RETRY_COUNT_REV30 :
-					UCPD_N_RETRY_COUNT_REV20;
-			}
-		}
-
-		/* If state is not idle, then start tx message */
-		if (ucpd_tx_state != STATE_IDLE) {
-			ucpd_tx_request &= ~(1 << msg_src);
-			tx_retry_count = 0;
-		}
-		break;
-
-	case STATE_ACTIVE_TCPM:
-		/*
-		 * Check if tx msg has finsihed. For TCPM messages
-		 * transmit is not complete until a GoodCRC message
-		 * matching the msgID just sent is received. But, a tx
-		 * message can fail due to collision or underrun,
-		 * etc. If that failure occurs, dont' wait for GoodCrc
-		 * and just go to failure path.
-		 */
-		if (evt & UCPD_EVT_TX_MSG_SUCCESS) {
-			ucpd_set_tx_state(STATE_WAIT_CRC_ACK);
-			ucpd_timeout_us = UCPD_T_RECEIVE_US;
-		} else if (evt & UCPD_EVT_TX_MSG_DISC ||
-			   evt & UCPD_EVT_TX_MSG_FAIL) {
-			if (tx_retry_count < tx_retry_max) {
-				if (evt & UCPD_EVT_RX_MSG) {
-					/*
-					 * A message was received so there is no
-					 * need to retry this tx message which
-					 * had failed to send previously.
-					 * Likely, due to the wire
-					 * being active from the message that
-					 * was just received.
-					 */
-					ucpd_set_tx_state(STATE_IDLE);
-					pd_transmit_complete(port,
-							     TCPC_TX_COMPLETE_DISCARDED);
-					ucpd_set_tx_state(STATE_IDLE);
-				} else {
-					/*
-					 * Tx attempt failed. Remain in this
-					 * state, but trigger new tx attempt.
-					 */
-					msg_src = TX_MSG_TCPM;
-					tx_retry_count++;
-				}
-			} else {
-				enum tcpc_transmit_complete status;
-
-				status = (evt & UCPD_EVT_TX_MSG_FAIL) ?
-					TCPC_TX_COMPLETE_FAILED :
-					TCPC_TX_COMPLETE_DISCARDED;
-				ucpd_set_tx_state(STATE_IDLE);
-				pd_transmit_complete(port, status);
-			}
-		}
-		break;
-
-	case STATE_ACTIVE_CRC:
-		if (evt & (UCPD_EVT_TX_MSG_SUCCESS | UCPD_EVT_TX_MSG_FAIL |
-			   UCPD_EVT_TX_MSG_DISC)) {
-			ucpd_set_tx_state(STATE_IDLE);
-			if (evt & UCPD_EVT_TX_MSG_FAIL)
-				CPRINTS("ucpd: Failed to send GoodCRC!");
-			else if (evt & UCPD_EVT_TX_MSG_DISC)
-				CPRINTS("ucpd: GoodCRC message discarded!");
-		}
-		break;
-
-	case STATE_WAIT_CRC_ACK:
-		if (evt & UCPD_EVT_RX_GOOD_CRC &&
-		    ucpd_crc_id == msg_id_match) {
-			/* GoodCRC with matching ID was received */
-			pd_transmit_complete(port,
-					     TCPC_TX_COMPLETE_SUCCESS);
-			ucpd_set_tx_state(STATE_IDLE);
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-			ucpd_log_mark_crc();
-#endif
-		} else if ((evt & UCPD_EVT_RX_GOOD_CRC) ||
-			   (evt & TASK_EVENT_TIMER)) {
-			/* GoodCRC w/out match or timeout waiting */
-			if (tx_retry_count < tx_retry_max) {
-				ucpd_set_tx_state(STATE_ACTIVE_TCPM);
-				msg_src = TX_MSG_TCPM;
-				tx_retry_count++;
-			} else {
-				ucpd_set_tx_state(STATE_IDLE);
-				pd_transmit_complete(port,
-						     TCPC_TX_COMPLETE_FAILED);
-			}
-		} else if (evt & UCPD_EVT_RX_MSG) {
-			/*
-			 * In the case of a collsion, it's possible the port
-			 * partner may not send a GoodCRC and instead send the
-			 * message that was colliding. If a message is received
-			 * in this state, then treat it as a discard from an
-			 * incoming message.
-			 */
-			pd_transmit_complete(port,
-					     TCPC_TX_COMPLETE_DISCARDED);
-			ucpd_set_tx_state(STATE_IDLE);
-		}
-		break;
-
-	case STATE_HARD_RESET:
-		if (evt & UCPD_EVT_HR_DONE) {
-			/* HR complete, reset tx state values */
-			ucpd_set_tx_state(STATE_IDLE);
-			ucpd_tx_request = 0;
-			tx_retry_count = 0;
-		} else if (evt & UCPD_EVT_HR_FAIL) {
-			ucpd_set_tx_state(STATE_IDLE);
-			ucpd_tx_request = 0;
-			tx_retry_count = 0;
-		}
-		break;
-	}
-
-	/* If msg_src is valid, then start transmit */
-	if (msg_src > TX_MSG_NONE) {
-		stm32gx_ucpd_start_transmit(port, msg_src);
-	}
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-	ucpd_task_log(ucpd_timeout_us, enter, ucpd_tx_state, req, evt);
-#endif
-}
-
-/*
- * Main task entry point for UCPD task
- *
- * @param p The PD port number for which to handle interrupts (pointer is
- * reinterpreted as an integer directly).
- */
-void ucpd_task(void *p)
-{
-	const int port = (int) ((intptr_t) p);
-
-	/* Init variables used to manage tx process */
-	stm32gx_ucpd_state_init(port);
-
-	while (1) {
-		/*
-		 * Note that ucpd_timeout_us is file scope and may be modified
-		 * in the tx state machine when entering the STATE_WAIT_CRC_ACK
-		 * state. Otherwise, the expectation is that the task is woken
-		 * only upon non-timer events.
-		 */
-		int evt = task_wait_event(ucpd_timeout_us);
-
-		/*
-		 * USB-PD messages are intiated in TCPM stack (PRL
-		 * layer). However, GoodCRC messages are initiated within the
-		 * UCPD driver based on USB-PD rx messages. These 2 types of
-		 * transmit paths are managed via task events.
-		 *
-		 * UCPD generated GoodCRC messages, are the priority path as
-		 * they must be sent immediately following a successful USB-PD
-		 * rx message. As long as a transmit operation is not underway,
-		 * then a transmit message will be started upon request. The ISR
-		 * routine sets the event to indicate that the transmit
-		 * operation is complete.
-		 *
-		 * Hard reset requests are sent as a TCPM message, but in terms
-		 * of the ucpd transmitter, they are treated as a 3rd tx msg
-		 * source since they can interrupt an ongoing tx msg, and there
-		 * is no requirement to wait for a GoodCRC reply message.
-		 */
-
-		/* Assume there is no timer for next task wake */
-		ucpd_timeout_us = -1;
-
-		if (evt & UCPD_EVT_GOOD_CRC_REQ)
-			ucpd_tx_request |= MSG_GOOD_CRC_MASK;
-
-		if (evt & UCPD_EVT_TCPM_MSG_REQ)
-			ucpd_tx_request |= MSG_TCPM_MASK;
-
-		/*
-		 * Manage PD tx messages. The state machine may need to be
-		 * called more than once when the task wakes. For instance, if
-		 * the task is woken at the completion of sending a GoodCRC,
-		 * there may be a TCPM message request pending and just changing
-		 * the state back to idle would not trigger start of transmit.
-		 */
-		do {
-			ucpd_manage_tx(port, evt);
-			/* Look at task events only once. */
-			evt = 0;
-		} while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE
-			 && !ucpd_rx_msg_active);
-	}
-}
-
-static void ucpd_send_good_crc(int port, uint16_t rx_header)
-{
-	int msg_id;
-	int rev_id;
-	uint16_t tx_header;
-	enum tcpci_msg_type tx_type;
-	enum pd_power_role pr = 0;
-	enum pd_data_role dr = 0;
-
-	/*
-	 * A GoodCRC message shall be sent by receiver to ack that the previous
-	 * message was correctly received. The GoodCRC message shall return the
-	 * rx message's msg_id field. The one exception is for GoodCRC messages,
-	 * which do not generate a GoodCRC response
-	 */
-	if (ucpd_msg_is_good_crc(rx_header)) {
-		return;
-	}
-
-	/*
-	 * Get the rx ordered set code just detected. SOP -> SOP''_Debug are in
-	 * the same order as enum tcpci_msg_type and so can be used
-	 * directly.
-	 */
-	tx_type = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK;
-
-	/*
-	 * PD Header(SOP):
-	 *   Extended   b15    -> set to 0 for control messages
-	 *   Count      b14:12 -> number of 32 bit data objects = 0 for ctrl msg
-	 *   MsgID      b11:9  -> running byte counter (extracted from rx msg)
-	 *   Power Role b8     -> stored in static, from set_msg_header()
-	 *   Spec Rev   b7:b6  -> PD spec revision (extracted from rx msg)
-	 *   Data Role  b5     -> stored in static, from set_msg_header
-	 *   Msg Type   b4:b0  -> data or ctrl type = PD_CTRL_GOOD_CRC
-	 */
-	/* construct header message */
-	msg_id = PD_HEADER_ID(rx_header);
-	rev_id = PD_HEADER_REV(rx_header);
-	if (tx_type == TCPCI_MSG_SOP) {
-		pr = msg_header.pr;
-		dr = msg_header.dr;
-	}
-	tx_header = PD_HEADER(PD_CTRL_GOOD_CRC, pr, dr, msg_id, 0, rev_id, 0);
-
-	/* Good CRC is header with no other objects */
-	ucpd_tx_buffers[TX_MSG_GOOD_CRC].msg_len = 2;
-	ucpd_tx_buffers[TX_MSG_GOOD_CRC].data.header = tx_header;
-	ucpd_tx_buffers[TX_MSG_GOOD_CRC].type = tx_type;
-
-	/* Notify ucpd task that a GoodCRC message tx request is pending */
-	task_set_event(TASK_ID_UCPD, UCPD_EVT_GOOD_CRC_REQ);
-}
-
-int stm32gx_ucpd_transmit(int port,
-			  enum tcpci_msg_type type,
-			  uint16_t header,
-			  const uint32_t *data)
-{
-	/* Length in bytes = (4 * object len) + 2 header byes */
-	int len = (PD_HEADER_CNT(header) << 2) + 2;
-
-	if (len > UCPD_BUF_LEN)
-		return EC_ERROR_OVERFLOW;
-
-	/* Store tx msg info in TCPM msg descriptor */
-	ucpd_tx_buffers[TX_MSG_TCPM].msg_len = len;
-	ucpd_tx_buffers[TX_MSG_TCPM].type = type;
-	ucpd_tx_buffers[TX_MSG_TCPM].data.header = header;
-	/* Copy msg objects to ucpd data buffer, after 2 header bytes */
-	memcpy(ucpd_tx_buffers[TX_MSG_TCPM].data.msg + 2, (uint8_t *)data,
-	       len - 2);
-
-	/*
-	 * Check for hard reset message here. A different event is used for hard
-	 * resets as they are able to interrupt ongoing transmit, and should
-	 * have priority over any pending message.
-	 */
-	if (type == TCPCI_MSG_TX_HARD_RESET)
-		task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_REQ);
-	else
-		task_set_event(TASK_ID_UCPD, UCPD_EVT_TCPM_MSG_REQ);
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head)
-{
-	uint16_t *rx_header = (uint16_t *)ucpd_rx_buffer;
-	int rxpaysz;
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	int sop;
-#endif
-
-	/* First 2 bytes of data buffer are the header */
-	*head = *rx_header;
-
-#ifdef CONFIG_USB_PD_DECODE_SOP
-/*
- * The message header is a 16-bit value that's stored in a 32-bit data type.
- * SOP* is encoded in bits 31 to 28 of the 32-bit data type.
- * NOTE: The 4 byte header is not part of the PD spec.
- */
-	/* Get SOP value */
-	sop = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK;
-	/* Put SOP in bits 31:28 of 32 bit header */
-	*head |= PD_HEADER_SOP(sop);
-#endif
-	rxpaysz = STM32_UCPD_RX_PAYSZR(port) & STM32_UCPD_RX_PAYSZR_MASK;
-	/* This size includes 2 bytes for message header */
-	rxpaysz -= 2;
-	/* Copy payload (src/dst are both 32 bit aligned) */
-	memcpy(payload, ucpd_rx_buffer + 2, rxpaysz);
-
-	return EC_SUCCESS;
-}
-
-enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port,
-						   const bool enable)
-{
-	ucpd_rx_bist_mode = enable;
-	CPRINTS("ucpd: Bist test mode = %d", enable);
-
-	return EC_SUCCESS;
-}
-
-void stm32gx_ucpd1_irq(void)
-{
-	/* STM32_IRQ_UCPD indicates this is from UCPD1, so port = 0 */
-	int port = 0;
-	uint32_t sr = STM32_UCPD_SR(port);
-	uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT | STM32_UCPD_SR_TXMSGABT
-		| STM32_UCPD_SR_TXMSGDISC | STM32_UCPD_SR_HRSTSENT |
-		STM32_UCPD_SR_HRSTDISC;
-
-	/* Check for CC events, set event to wake PD task */
-	if (sr & (STM32_UCPD_SR_TYPECEVT1 | STM32_UCPD_SR_TYPECEVT2)) {
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-		ucpd_sr_cc_event = sr;
-		hook_call_deferred(&ucpd_cc_change_notify_data, 0);
-#endif
-	}
-
-	/*
-	 * Check for Tx events. tx_mask includes all status bits related to the
-	 * end of a USB-PD tx message. If any of these bits are set, the
-	 * transmit attempt is completed. Set an event to notify ucpd tx state
-	 * machine that transmit operation is complete.
-	 */
-	if (sr & tx_done_mask) {
-		/* Check for tx message complete */
-		if (sr & STM32_UCPD_SR_TXMSGSENT) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_SUCCESS);
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-			ucpd_log_mark_tx_comp();
-#endif
-		} else if (sr & (STM32_UCPD_SR_TXMSGABT |
-				 STM32_UCPD_SR_TXUND)) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_FAIL);
-		} else if (sr & STM32_UCPD_SR_TXMSGDISC) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_DISC);
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-			ucpd_log_mark_tx_comp();
-#endif
-		} else if (sr & STM32_UCPD_SR_HRSTSENT) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_DONE);
-		} else if (sr & STM32_UCPD_SR_HRSTDISC) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_FAIL);
-		}
-		/* Disable Tx interrupts */
-		ucpd_tx_interrupts_enable(port, 0);
-	}
-
-	/* Check for data register empty */
-	if (sr & STM32_UCPD_SR_TXIS)
-		ucpd_tx_data_byte(port);
-
-	/* Check for Rx Events */
-	/* Check first for start of new message */
-	if (sr & STM32_UCPD_SR_RXORDDET) {
-		ucpd_rx_byte_count = 0;
-		ucpd_rx_msg_active = 1;
-	}
-	/* Check for byte received */
-	if (sr & STM32_UCPD_SR_RXNE)
-		ucpd_rx_data_byte(port);
-
-	/* Check for end of message */
-	if (sr & STM32_UCPD_SR_RXMSGEND) {
-		ucpd_rx_msg_active = 0;
-		/* Check for errors */
-		if (!(sr & STM32_UCPD_SR_RXERR)) {
-			uint16_t *rx_header = (uint16_t *)ucpd_rx_buffer;
-			enum tcpci_msg_type type;
-			int good_crc = 0;
-
-			type = STM32_UCPD_RX_ORDSETR(port) &
-				STM32_UCPD_RXORDSETR_MASK;
-
-			good_crc = ucpd_msg_is_good_crc(*rx_header);
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-			ucpd_log_add_msg(*rx_header, 1);
-#endif
-			/*
-			 * Don't pass GoodCRC control messages to the TCPM
-			 * layer. In addition, need to filter for SOP'/SOP''
-			 * packets if those are not enabled. SOP'/SOP''
-			 * reception is controlled by a static variable. The
-			 * hardware orderset detection pattern can't be changed
-			 * without disabling the ucpd peripheral.
-			 */
-			if (!good_crc && (ucpd_rx_sop_prime_enabled ||
-					  type == TCPCI_MSG_SOP)) {
-
-				/*
-				 * If BIST test mode is active, then still need
-				 * to send GoodCRC reply, but there is no need
-				 * to send the message up to the tcpm layer.
-				 */
-				if(!ucpd_rx_bist_mode) {
-					if (tcpm_enqueue_message(port))
-						hook_call_deferred(&ucpd_rx_enque_error_data,
-							   0);
-				}
-
-				task_set_event(TASK_ID_UCPD,
-						       UCPD_EVT_RX_MSG);
-
-				/* Send GoodCRC message (if required) */
-				ucpd_send_good_crc(port, *rx_header);
-			} else if (good_crc) {
-				task_set_event(TASK_ID_UCPD,
-						       UCPD_EVT_RX_GOOD_CRC);
-				ucpd_crc_id = PD_HEADER_ID(*rx_header);
-			}
-		} else {
-			/* Rx message is complete, but there were bit errors */
-			CPRINTS("ucpd: rx message error");
-		}
-	}
-	/* Check for fault conditions */
-	if (sr & STM32_UCPD_SR_RXHRSTDET) {
-		/* hard reset received */
-		pd_execute_hard_reset(port);
-		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
-		hook_call_deferred(&ucpd_hard_reset_rx_log_data, 0);
-	}
-
-	/* Clear interrupts now that PD events have been set */
-	STM32_UCPD_ICR(port) = sr;
-}
-DECLARE_IRQ(STM32_IRQ_UCPD1, stm32gx_ucpd1_irq, 1);
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-static char ctrl_names[][12] = {
-	"rsvd",
-	"GoodCRC",
-	"Goto Min",
-	"Accept",
-	"Reject",
-	"Ping",
-	"PS_Rdy",
-	"Get_SRC",
-	"Get_SNK",
-	"DR_Swap",
-	"PR_Swap",
-	"VCONN_Swp",
-	"Wait",
-	"Soft_Rst",
-	"RSVD",
-	"RSVD",
-	"Not_Sup",
-	"Get_SRC_Ext",
-	"Get_Status",
-};
-
-static char data_names[][10] = {
-	"RSVD",
-	"SRC_CAP",
-	"REQUEST",
-	"BIST",
-	"SINK_CAP",
-	"BATTERY",
-        "ALERT",
-	"GET_INFO",
-	"ENTER_USB",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"VDM",
-};
-
-static void ucpd_dump_msg_log(void)
-{
-	int i;
-	int type;
-	int len;
-	int dir;
-	uint16_t header;
-	char *name;
-
-
-	ccprintf("ucpd: msg_total = %d\n", msg_log_cnt);
-	ccprintf("Idx\t  Delta(us)\tDir\t   Type\t\tLen\t s1  s2   PR\t DR\n");
-	ccprintf("-----------------------------------------------------------"
-		 "-----------------\n");
-
-	for (i = 0; i < msg_log_idx; i++) {
-		uint32_t delta_ts = 0;
-		int j;
-
-		header = msg_log[i].header;
-
-		if (header != 0xabcd) {
-			type = PD_HEADER_TYPE(header);
-			len = PD_HEADER_CNT(header);
-			name = len ? data_names[type] : ctrl_names[type];
-			dir = msg_log[i].dir;
-			if (i) {
-				delta_ts = msg_log[i].ts - msg_log[i-1].ts;
-			}
-
-			ccprintf("msg[%02d]: %08d\t %s\t %8s\t %02d\t %d  %d\t"
-				 "%s\t %s",
-				 i,
-				 delta_ts,
-				 dir ? "Rx" : "Tx",
-				 name,
-				 len,
-				 msg_log[i].comp,
-				 msg_log[i].crc,
-				 PD_HEADER_PROLE(header) ? "SRC" : "SNK",
-				 PD_HEADER_DROLE(header) ? "DFP" : "UFP");
-			len = MIN((len * 4) + 2, MSG_BUF_LEN);
-			for (j = 0; j < len; j++)
-				ccprintf(" %02x", msg_log[i].buf[j]);
-		} else {
-			if (i) {
-				delta_ts = msg_log[i].ts - msg_log[i-1].ts;
-			}
-			ccprintf("msg[%02d]: %08d\t CC Voltage Change!",
-				 i, delta_ts);
-		}
-		ccprintf("\n");
-		msleep(5);
-	}
-}
-
-static void stm32gx_ucpd_set_cc_debug(int port, int cc_mask, int pull, int rp)
-{
-	int cc_enable;
-	uint32_t cr = STM32_UCPD_CR(port);
-
-	/*
-	 * Only update ANASUBMODE if specified pull type is Rp.
-	 */
-	if (pull == TYPEC_CC_RP) {
-		cr &= ~STM32_UCPD_CR_ANASUBMODE_MASK;
-		cr |= STM32_UCPD_CR_ANASUBMODE_VAL(UCPD_RP_TO_ANASUB(rp));
-	}
-
-	/*
-	 * Can't independently set pull value for CC1 from CC2. But, can
-	 * independently connect or disconnect pull for CC1 and CC2. Enable here
-	 * the CC lines specified by cc_mask. If desired pull is TYPEC_CC_OPEN,
-	 * then the CC lines specified in cc_mask will be disabled.
-	 */
-	/* Get existing cc enable value */
-	cc_enable = (cr & STM32_UCPD_CR_CCENABLE_MASK) >>
-		STM32_UCPD_CR_CCENABLE_SHIFT;
-	/* Apply cc_mask (enable CC line specified) */
-	cc_enable |= cc_mask;
-
-	/* Set ANAMODE if cc_pull is Rd */
-	if (pull == TYPEC_CC_RD)
-		cr |= STM32_UCPD_CR_ANAMODE;
-	/* Clear ANAMODE if cc_pull is Rp */
-	else if (pull == TYPEC_CC_RP)
-		cr &= ~(STM32_UCPD_CR_ANAMODE);
-	else if (pull == TYPEC_CC_OPEN)
-		cc_enable &= ~cc_mask;
-
-	/* The value for this field needs to be OR'd in */
-	cr &= ~STM32_UCPD_CR_CCENABLE_MASK;
-	cr |= STM32_UCPD_CR_CCENABLE_VAL(cc_enable);
-	/* Update pull values */
-	STM32_UCPD_CR(port) = cr;
-	/* Display updated settings */
-	ucpd_cc_status(port);
-}
-
-void ucpd_info(int port)
-{
-	ucpd_cc_status(port);
-	ccprintf("\trx_en\t = %d\n\tpol\t = %d\n",
-		 !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_PHYRXEN),
-		 !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_PHYCCSEL));
-
-	/* Dump ucpd task state info */
-	ccprintf("ucpd: tx_state = %s, tx_req = %02x, timeout_us = %d\n",
-		ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us);
-
-	ucpd_task_log_dump();
-}
-
-static int command_ucpd(int argc, char **argv)
-{
-	uint32_t tx_data = 0;
-	char *e;
-	int val;
-	int port = 0;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "rst")) {
-		/* Force reset of ucpd peripheral */
-		stm32gx_ucpd_init(port);
-		pd_execute_hard_reset(port);
-		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
-	} else if (!strcasecmp(argv[1], "info")) {
-		ucpd_info(port);
-	} else if (!strcasecmp(argv[1], "bist")) {
-		/* Need to initiate via DPM to have a timer */
-		/* TODO(b/182861002): uncomment when Gingerbread has
-		 * full PD support landed.
-		 * pd_dpm_request(port, DPM_REQUEST_BIST_TX);
-		 */
-	} else if (!strcasecmp(argv[1], "hard")) {
-		stm32gx_ucpd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0,
-				      &tx_data);
-	} else if (!strcasecmp(argv[1], "pol")) {
-		if (argc < 3)
-			return EC_ERROR_PARAM_COUNT;
-		val = strtoi(argv[2], &e, 10);
-		if (val > 1)
-			val = 0;
-		stm32gx_ucpd_set_polarity(port, val);
-		stm32gx_ucpd_set_rx_enable(port, 1);
-		ccprintf("ucpd: set pol = %d, PHYRXEN = 1\n", val);
-	} else if (!strcasecmp(argv[1], "cc")) {
-		int cc_mask;
-		int pull;
-		int rp = 0; /* needs to be initialized */
-
-		if (argc < 3) {
-			ucpd_cc_status(port);
-			return EC_SUCCESS;
-		}
-		cc_mask = strtoi(argv[2], &e, 10);
-		if (cc_mask < 1 || cc_mask > 3)
-			return EC_ERROR_PARAM2;
-		/* cc_mask has determines which cc setting to apply */
-		if (!strcasecmp(argv[3], "rd")) {
-			pull = TYPEC_CC_RD;
-		} else if (!strcasecmp(argv[3], "rp")) {
-			pull = TYPEC_CC_RP;
-			rp = strtoi(argv[4], &e, 10);
-			if (rp < 0 || rp > 2)
-				return EC_ERROR_PARAM4;
-		} else if (!strcasecmp(argv[3], "open")) {
-			pull = TYPEC_CC_OPEN;
-		} else {
-			return EC_ERROR_PARAM3;
-		}
-		stm32gx_ucpd_set_cc_debug(port, cc_mask, pull, rp);
-
-	} else if (!strcasecmp(argv[1], "log")) {
-		if (argc < 3) {
-			ucpd_dump_msg_log();
-		} else if (!strcasecmp(argv[2], "clr")) {
-			msg_log_cnt = 0;
-			msg_log_idx = 0;
-		}
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ucpd, command_ucpd,
-			"[rst|info|bist|hard|pol <0|1>|cc xx <rd|rp|open>|log",
-			"ucpd peripheral debug and control options");
-#endif
diff --git a/chip/stm32/ucpd-stm32gx.h b/chip/stm32/ucpd-stm32gx.h
deleted file mode 100644
index d3af41e5bc..0000000000
--- a/chip/stm32/ucpd-stm32gx.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_UCPD_STM32GX_H
-#define __CROS_EC_UCPD_STM32GX_H
-
-/* STM32 UCPD driver for Chrome EC */
-
-#include "usb_pd_tcpm.h"
-
-/*
- * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
- * a prescaler who's output feeds the 'half-bit' divider which is used
- * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
- * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
- * range is 9 <--> 18 MHz.
- *
- *          ------- @ 16 MHz ---------   @ ~600 kHz   -------------
- * HSI ---->| /psc |-------->| /hbit |--------------->| trans_cnt |
- *          -------          ---------    |           -------------
- *                                        |           -------------
- *                                        |---------->| ifrgap_cnt|
- *                                                    -------------
- * Requirements:
- *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
- *   2. tTransitionWindow - 12 to 20 uSec
- *   3. tInterframGap - uSec
- *
- * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
- * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
- * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
- */
-
-#define UCPD_PSC_DIV 1
-#define UCPD_HBIT_DIV 27
-#define UCPD_TRANSWIN_CNT 8
-#define UCPD_IFRGAP_CNT 17
-
-
-/*
- * K-codes and ordered set defines. These codes and sets are used to encode
- * which type of USB-PD message is being sent. This information can be found in
- * the USB-PD spec section 5.4 - 5.6. This info is also included in the STM32G4
- * TRM (RM0440) 45.4.3
- */
-#define UCPD_SYNC1 0x18u
-#define UCPD_SYNC2 0x11u
-#define UCPD_SYNC3 0x06u
-#define UCPD_RST1  0x07u
-#define UCPD_RST2  0x19u
-#define UCPD_EOP   0x0Du
-
-/* This order of this enum matches tcpm_sop_type */
-enum ucpd_tx_ordset {
-	TX_ORDERSET_SOP =	(UCPD_SYNC1 |
-				(UCPD_SYNC1<<5u) |
-				(UCPD_SYNC1<<10u) |
-				(UCPD_SYNC2<<15u)),
-
-	TX_ORDERSET_SOP_PRIME =	(UCPD_SYNC1 |
-				(UCPD_SYNC1<<5u) |
-				(UCPD_SYNC3<<10u) |
-				(UCPD_SYNC3<<15u)),
-
-	TX_ORDERSET_SOP_PRIME_PRIME =	(UCPD_SYNC1 |
-				(UCPD_SYNC3<<5u) |
-				(UCPD_SYNC1<<10u) |
-				(UCPD_SYNC3<<15u)),
-
-	TX_ORDERSET_SOP_PRIME_DEBUG =	(UCPD_SYNC1 |
-					(UCPD_RST2<<5u) |
-					(UCPD_RST2<<10u) |
-					(UCPD_SYNC3<<15u)),
-
-	TX_ORDERSET_SOP_PRIME_PRIME_DEBUG =	(UCPD_SYNC1 |
-					(UCPD_RST2<<5u) |
-					(UCPD_SYNC3<<10u) |
-					(UCPD_SYNC2<<15u)),
-
-	TX_ORDERSET_HARD_RESET =	(UCPD_RST1  |
-					(UCPD_RST1<<5u) |
-					(UCPD_RST1<<10u)  |
-					(UCPD_RST2<<15u)),
-
-	TX_ORDERSET_CABLE_RESET =	(UCPD_RST1 |
-					(UCPD_SYNC1<<5u) |
-					(UCPD_RST1<<10u)  |
-					(UCPD_SYNC3<<15u)),
-};
-
-
-/**
- * STM32Gx UCPD implementation of tcpci .init method
- *
- * @param usbc_port -> USB-C Port number
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_init(int usbc_port);
-
-/**
- * STM32Gx UCPD implementation of tcpci .release method
- *
- * @param usbc_port -> USB-C Port number
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_release(int usbc_port);
-
-/**
- * STM32Gx UCPD implementation of tcpci .get_cc method
- *
- * @param usbc_port -> USB-C Port number
- * @param *cc1 -> pointer to cc1 result
- * @param *cc2 -> pointer to cc2 result
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_get_cc(int usbc_port, enum tcpc_cc_voltage_status *cc1,
-			enum tcpc_cc_voltage_status *cc2);
-
-/**
- * STM32Gx equivalent for TCPCI role_control register
- *
- * @param usbc_port -> USB-C Port number
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_get_role_control(int usbc_port);
-
-/**
- * STM32Gx UCPD implementation of tcpci .set_cc method
- *
- * @param usbc_port -> USB-C Port number
- * @param cc_pull -> Rp or Rd selection
- * @param rp -> value of Rp (if cc_pull == Rp)
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_set_cc(int usbc_port, int cc_pull, int rp);
-
-/**
- * STM32Gx UCPD implementation of tcpci .set_cc method
- *
- * @param usbc_port -> USB-C Port number
- * @param polarity -> CC1 or CC2 selection
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_set_polarity(int usbc_port, enum tcpc_cc_polarity polarity);
-
-/**
- * STM32Gx UCPD implementation of tcpci .set_rx_enable method
- *
- * @param usbc_port -> USB-C Port number
- * @param enable -> on/off for USB-PD messages
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_set_rx_enable(int port, int enable);
-
-/**
- * STM32Gx UCPD implementation of tcpci .set_msg_header method
- *
- * @param usbc_port -> USB-C Port number
- * @param power_role -> port's current power role
- * @param data_role -> port's current data role
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role);
-
-/**
- * STM32Gx UCPD implementation of tcpci .transmit method
- *
- * @param usbc_port -> USB-C Port number
- * @param type -> SOP/SOP'/SOP'' etc
- * @param header -> usb pd message header
- * @param *data -> pointer to message contents
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_transmit(int port,
-			enum tcpci_msg_type type,
-			uint16_t header,
-			  const uint32_t *data);
-
-/**
- * STM32Gx UCPD implementation of tcpci .get_message_raw method
- *
- * @param usbc_port -> USB-C Port number
- * @param *payload -> pointer to where message should be written
- * @param *head -> pointer to message header
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head);
-
-/**
- * STM32Gx method to remove Rp when VCONN is being supplied
- *
- * @param usbc_port -> USB-C Port number
- * @param enable -> connect/disc Rp
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_vconn_disc_rp(int port, int enable);
-
-/**
- * STM32Gx UCPD implementation of tcpci .sop_prime_enable method
- *
- * @param usbc_port -> USB-C Port number
- * @param enable -> control of SOP'/SOP'' messages
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_sop_prime_enable(int port, bool enable);
-
-int stm32gx_ucpd_get_chip_info(int port, int live,
-			       struct ec_response_pd_chip_info_v1 *chip_info);
-
-/**
- * This function is used to enable/disable a ucpd debug feature that is used to
- * mark the ucpd message log when there is a usbc detach event.
- *
- * @param enable -> on/off control for debug feature
- */
-void ucpd_cc_detect_notify_enable(int enable);
-
-/**
- * This function is used to enable/disable rx bist test mode in the ucpd
- * driver. This mode is controlled at the PE layer. When this mode is enabled,
- * the ucpd receiver will not pass BIST data messages to the protocol layer and
- * only send GoodCRC replies.
- *
- * @param usbc_port -> USB-C Port number
- * @param enable -> on/off control for rx bist mode
- */
-enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port,
-						   const bool enable);
-
-#endif /* __CROS_EC_UCPD_STM32GX_H */
diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c
deleted file mode 100644
index 908542146f..0000000000
--- a/chip/stm32/usart-stm32f0.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart-stm32f0.h"
-
-#include "clock.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 4
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	/*
-	 * Make sure we register this config before enabling the HW.
-	 * If we did it the other way around the FREQ_CHANGE hook could be
-	 * called before we update the configs array and we would miss the
-	 * clock frequency change event, leaving our baud rate divisor wrong.
-	 */
-	configs[config->hw->index] = config;
-
-	usart_set_baud(config, config->baud);
-
-	task_enable_irq(config->hw->irq);
-}
-
-void usart_set_baud(struct usart_config const *config, int baud)
-{
-	usart_set_baud_f0_l(config, baud, clock_get_freq());
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	int index = config->hw->index;
-
-	/*
-	 * Only disable the shared interrupt for USART3/4 if both USARTs are
-	 * now disabled.
-	 */
-	if ((index == 0) ||
-	    (index == 1) ||
-	    (index == 2 && configs[3] == NULL) ||
-	    (index == 3 && configs[2] == NULL))
-		task_disable_irq(config->hw->irq);
-
-	configs[index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-static void freq_change(void)
-{
-	size_t	i;
-
-	for (i = 0; i < ARRAY_SIZE(configs); ++i)
-		if (configs[i])
-			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
-}
-
-DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
-
-void usart_clear_tc(struct usart_config const *config)
-{
-	STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF;
-}
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3_4,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-#endif
-
-#if defined(CONFIG_STREAM_USART4)
-struct usart_hw_config const usart4_hw = {
-	.index          = 3,
-	.base           = STM32_USART4_BASE,
-	.irq            = STM32_IRQ_USART3_4,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART4,
-	.ops            = &usart_variant_hw_ops,
-};
-#endif
-
-#if defined(CONFIG_STREAM_USART3) || defined(CONFIG_STREAM_USART4)
-void usart3_4_interrupt(void)
-{
-	/*
-	 * This interrupt handler could be called with one of these configs
-	 * not initialized, so we need to check here and only call the generic
-	 * USART interrupt handler for initialized configs.
-	 */
-	if (configs[2])
-		usart_interrupt(configs[2]);
-
-	if (configs[3])
-		usart_interrupt(configs[3]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART3_4, usart3_4_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32f0.h b/chip/stm32/usart-stm32f0.h
deleted file mode 100644
index 1b7eee95a7..0000000000
--- a/chip/stm32/usart-stm32f0.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32F0_H
-#define __CROS_EC_USART_STM32F0_H
-
-#include "usart.h"
-
-/*
- * The STM32F0 series can have as many as four UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-extern struct usart_hw_config const usart4_hw;
-
-#endif /* __CROS_EC_USART_STM32F0_H */
diff --git a/chip/stm32/usart-stm32f3.c b/chip/stm32/usart-stm32f3.c
deleted file mode 100644
index 42a0cf310e..0000000000
--- a/chip/stm32/usart-stm32f3.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart-stm32f3.h"
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 3
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	configs[config->hw->index] = config;
-
-	/*
-	 * All three USARTS are clocked from the HSI(8MHz) source.  This is
-	 * done because the clock sources elsewhere are setup so that the result
-	 * of clock_get_freq() is not the input clock frequency to the USARTs
-	 * baud rate divisors.
-	 */
-	STM32_RCC_CFGR3 |= 0x000f0003;
-
-	usart_set_baud_f0_l(config, config->baud, 8000000);
-
-	task_enable_irq(config->hw->irq);
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	task_disable_irq(config->hw->irq);
-
-	configs[config->hw->index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-void usart_clear_tc(struct usart_config const *config)
-{
-	STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF;
-}
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-void usart3_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32f3.h b/chip/stm32/usart-stm32f3.h
deleted file mode 100644
index 09f1ba608c..0000000000
--- a/chip/stm32/usart-stm32f3.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32F3_H
-#define __CROS_EC_USART_STM32F3_H
-
-#include "usart.h"
-
-/*
- * The STM32F3 series can have as many as three UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-
-#endif /* __CROS_EC_USART_STM32F3_H */
diff --git a/chip/stm32/usart-stm32f4.c b/chip/stm32/usart-stm32f4.c
deleted file mode 100644
index a554da147a..0000000000
--- a/chip/stm32/usart-stm32f4.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "usart-stm32f4.h"
-
-#include "clock.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 3
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	configs[config->hw->index] = config;
-
-
-	/* Use single-bit sampling */
-	STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT;
-
-	usart_set_baud_f0_l(config, config->baud, clock_get_freq());
-
-	task_enable_irq(config->hw->irq);
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	task_disable_irq(config->hw->irq);
-
-	configs[config->hw->index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-void usart3_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32f4.h b/chip/stm32/usart-stm32f4.h
deleted file mode 100644
index 49af2af405..0000000000
--- a/chip/stm32/usart-stm32f4.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32F4_H
-#define __CROS_EC_USART_STM32F4_H
-
-#include "usart.h"
-
-/*
- * The STM32F4 series can have as many as three UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- * CONFIG_STREAM_USART<X> enables the corresponding hardware instance.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-
-#endif /* __CROS_EC_USART_STM32F4_H */
diff --git a/chip/stm32/usart-stm32l.c b/chip/stm32/usart-stm32l.c
deleted file mode 100644
index 2b7406a0a4..0000000000
--- a/chip/stm32/usart-stm32l.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart-stm32l.h"
-
-#include "clock.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 3
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	/* Use single-bit sampling */
-	STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT;
-
-	/*
-	 * Make sure we register this config before enabling the HW.
-	 * If we did it the other way around the FREQ_CHANGE hook could be
-	 * called before we update the configs array and we would miss the
-	 * clock frequency change event, leaving our baud rate divisor wrong.
-	 */
-	configs[config->hw->index] = config;
-
-	usart_set_baud_f0_l(config, config->baud, clock_get_freq());
-
-	task_enable_irq(config->hw->irq);
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	task_disable_irq(config->hw->irq);
-
-	configs[config->hw->index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-static void freq_change(void)
-{
-	size_t	i;
-
-	for (i = 0; i < ARRAY_SIZE(configs); ++i)
-		if (configs[i])
-			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
-}
-
-DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
-
-void usart_clear_tc(struct usart_config const *config)
-{
-	STM32_USART_SR(config->hw->base) &= ~STM32_USART_SR_TC;
-}
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart3_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32l.h b/chip/stm32/usart-stm32l.h
deleted file mode 100644
index eb1ae9db1d..0000000000
--- a/chip/stm32/usart-stm32l.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32L_H
-#define __CROS_EC_USART_STM32L_H
-
-#include "usart.h"
-
-/*
- * The STM32L series can have as many as three UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-
-#endif /* __CROS_EC_USART_STM32L_H */
diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c
deleted file mode 100644
index 0245718e21..0000000000
--- a/chip/stm32/usart-stm32l5.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart-stm32l.h"
-
-#include "clock.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 4
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	/* Use single-bit sampling */
-	STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT;
-
-	/*
-	 * Make sure we register this config before enabling the HW.
-	 * If we did it the other way around the FREQ_CHANGE hook could be
-	 * called before we update the configs array and we would miss the
-	 * clock frequency change event, leaving our baud rate divisor wrong.
-	 */
-	configs[config->hw->index] = config;
-
-	usart_set_baud_f0_l(config, config->baud, clock_get_freq());
-
-	task_enable_irq(config->hw->irq);
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	task_disable_irq(config->hw->irq);
-
-	configs[config->hw->index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-static void freq_change(void)
-{
-	size_t	i;
-
-	for (i = 0; i < ARRAY_SIZE(configs); ++i)
-		if (configs[i])
-			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
-}
-
-DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
-
-void usart_clear_tc(struct usart_config const *config)
-{
-	STM32_USART_SR(config->hw->base) &= ~STM32_USART_SR_TC;
-}
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart3_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART4)
-struct usart_hw_config const usart4_hw = {
-	.index          = 2,
-	.base           = STM32_USART4_BASE,
-	.irq            = STM32_IRQ_USART4,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART4,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart4_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32l5.h b/chip/stm32/usart-stm32l5.h
deleted file mode 100644
index 564ffbc580..0000000000
--- a/chip/stm32/usart-stm32l5.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32L5_H
-#define __CROS_EC_USART_STM32L5_H
-
-#include "usart.h"
-
-/*
- * The STM32L5 series can have as many as four UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-extern struct usart_hw_config const usart4_hw;
-
-#endif /* __CROS_EC_USART_STM32L5_H */
diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c
deleted file mode 100644
index 7f8c55aaa6..0000000000
--- a/chip/stm32/usart.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USART driver for Chrome EC */
-
-#include "atomic.h"
-#include "common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "usart.h"
-#include "util.h"
-
-void usart_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-	uint32_t cr2, cr3;
-
-	/*
-	 * Enable clock to USART, this must be done first, before attempting
-	 * to configure the USART.
-	 */
-	*(config->hw->clock_register) |= config->hw->clock_enable;
-
-	/*
-	 * For STM32F3, A delay of 1 APB clock cycles is needed before we
-	 * can access any USART register. Fortunately, we have
-	 * gpio_config_module() below and thus don't need to add the delay.
-	 */
-
-	/*
-	 * Switch all GPIOs assigned to the USART module over to their USART
-	 * alternate functions.
-	 */
-	gpio_config_module(MODULE_USART, 1);
-
-	/*
-	 * 8N1, 16 samples per bit. error interrupts, and special modes
-	 * disabled.
-	 */
-
-	cr2 = 0x0000;
-	cr3 = 0x0000;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-    defined(CHIP_FAMILY_STM32L4)
-	if (config->flags & USART_CONFIG_FLAG_RX_INV)
-		cr2 |= BIT(16);
-	if (config->flags & USART_CONFIG_FLAG_TX_INV)
-		cr2 |= BIT(17);
-#endif
-	if (config->flags & USART_CONFIG_FLAG_HDSEL)
-		cr3 |= BIT(3);
-
-	STM32_USART_CR1(base) = 0x0000;
-	STM32_USART_CR2(base) = cr2;
-	STM32_USART_CR3(base) = cr3;
-
-	/*
-	 * Enable the RX, TX, and variant specific HW.
-	 */
-	config->rx->init(config);
-	config->tx->init(config);
-	config->hw->ops->enable(config);
-
-	/*
-	 * Clear error counts.
-	 */
-	config->state->rx_overrun = 0;
-	config->state->rx_dropped = 0;
-
-	/*
-	 * Enable the USART, this must be done last since most of the
-	 * configuration bits require that the USART be disabled for writes to
-	 * succeed.
-	 */
-	STM32_USART_CR1(base) |= STM32_USART_CR1_UE;
-}
-
-void usart_shutdown(struct usart_config const *config)
-{
-	STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_UE;
-
-	config->hw->ops->disable(config);
-}
-
-void usart_set_baud_f0_l(struct usart_config const *config, int baud,
-			int frequency_hz)
-{
-	int      div  = DIV_ROUND_NEAREST(frequency_hz, baud);
-	intptr_t base = config->hw->base;
-
-	if (div / 16 > 0) {
-		/*
-		 * CPU clock is high enough to support x16 oversampling.
-		 * BRR = (div mantissa)<<4 | (4-bit div fraction)
-		 */
-		STM32_USART_CR1(base) &= ~STM32_USART_CR1_OVER8;
-		STM32_USART_BRR(base) = div;
-	} else {
-		/*
-		 * CPU clock is low; use x8 oversampling.
-		 * BRR = (div mantissa)<<4 | (3-bit div fraction)
-		 */
-		STM32_USART_BRR(base) = ((div / 8) << 4) | (div & 7);
-		STM32_USART_CR1(base) |= STM32_USART_CR1_OVER8;
-	}
-}
-
-void usart_set_baud_f(struct usart_config const *config, int baud,
-		int frequency_hz)
-{
-	int div = DIV_ROUND_NEAREST(frequency_hz, baud);
-
-	/* STM32F only supports x16 oversampling */
-	STM32_USART_BRR(config->hw->base) = div;
-}
-
-int usart_get_parity(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	if (!(STM32_USART_CR1(base) & STM32_USART_CR1_PCE))
-		return 0;
-	if (STM32_USART_CR1(base) & STM32_USART_CR1_PS)
-		return 1;
-	return 2;
-}
-
-/*
- * We only allow 8 bit word. CR1_PCE modifies parity enable,
- * CR1_PS modifies even/odd, CR1_M modifies total word length
- * to make room for parity.
- */
-void usart_set_parity(struct usart_config const *config, int parity)
-{
-	uint32_t ue;
-	intptr_t base = config->hw->base;
-
-	if ((parity < 0) || (parity > 2))
-		return;
-
-	/* Record active state and disable the UART. */
-	ue = STM32_USART_CR1(base) & STM32_USART_CR1_UE;
-	STM32_USART_CR1(base) &= ~STM32_USART_CR1_UE;
-
-	if (parity) {
-		/* Set parity control enable. */
-		STM32_USART_CR1(base) |=
-			(STM32_USART_CR1_PCE | STM32_USART_CR1_M);
-		/* Set parity select even/odd bit. */
-		if (parity == 2)
-			STM32_USART_CR1(base) &= ~STM32_USART_CR1_PS;
-		else
-			STM32_USART_CR1(base) |= STM32_USART_CR1_PS;
-	} else {
-		STM32_USART_CR1(base) &=
-			~(STM32_USART_CR1_PCE | STM32_USART_CR1_PS |
-			  STM32_USART_CR1_M);
-	}
-
-	/* Restore active state. */
-	STM32_USART_CR1(base) |= ue;
-}
-
-void usart_interrupt(struct usart_config const *config)
-{
-	config->tx->interrupt(config);
-	config->rx->interrupt(config);
-}
diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h
deleted file mode 100644
index 491bd66a04..0000000000
--- a/chip/stm32/usart.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_H
-#define __CROS_EC_USART_H
-
-/* STM32 USART driver for Chrome EC */
-
-#include "common.h"
-#include "consumer.h"
-#include "producer.h"
-#include "queue.h"
-
-#include <stdint.h>
-
-/*
- * Per-USART state stored in RAM.  This structure will be zero initialized by
- * BSS init.
- */
-struct usart_state {
-	/*
-	 * Counter of bytes received and then dropped because of lack of space
-	 * in the RX queue.
-	 */
-	uint32_t rx_dropped;
-
-	/*
-	 * Counter of the number of times an receive overrun condition is
-	 * detected.  This will not usually be a count of the number of bytes
-	 * that were lost due to overrun conditions.
-	 */
-	uint32_t rx_overrun;
-};
-
-struct usart_config;
-
-struct usart_hw_ops {
-	/*
-	 * The generic USART initialization code calls this function to allow
-	 * the variant HW specific code to perform any initialization.  This
-	 * function is called before the USART is enabled, and should among
-	 * other things enable the USARTs interrupt.
-	 */
-	void (*enable)(struct usart_config const *config);
-
-	/*
-	 * The generic USART shutdown code calls this function, allowing the
-	 * variant specific code an opportunity to do any variant specific
-	 * shutdown tasks.
-	 */
-	void (*disable)(struct usart_config const *config);
-};
-
-/*
- * The usart_rx/usart_tx structures contain functions pointers for the
- * interrupt handler and producer/consumer operations required to implement a
- * particular RX/TX strategy.
- *
- * These structures are defined by the various RX/TX implementations, and are
- * used to initialize the usart_config structure to configure the USART driver
- * for interrupt or DMA based transfer.
- */
-struct usart_rx {
-	void (*init)(struct usart_config const *config);
-	void (*interrupt)(struct usart_config const *config);
-
-	/*
-	 * Print to the console any per-strategy diagnostic information, this
-	 * is used by the usart_info command.  This can be NULL if there is
-	 * nothing interesting to display.
-	 */
-	void (*info)(struct usart_config const *config);
-
-	struct producer_ops producer_ops;
-};
-
-struct usart_tx {
-	void (*init)(struct usart_config const *config);
-	void (*interrupt)(struct usart_config const *config);
-
-	/*
-	 * Print to the console any per-strategy diagnostic information, this
-	 * is used by the usart_info command.  This can be NULL if there is
-	 * nothing interesting to display.
-	 */
-	void (*info)(struct usart_config const *config);
-
-	struct consumer_ops consumer_ops;
-};
-
-extern struct usart_rx const usart_rx_interrupt;
-extern struct usart_tx const usart_tx_interrupt;
-
-/*
- * Per-USART hardware configuration stored in flash.  Instances of this
- * structure are provided by each variants driver, one per physical USART.
- */
-struct usart_hw_config {
-	int      index;
-	intptr_t base;
-	int      irq;
-
-	uint32_t volatile *clock_register;
-	uint32_t           clock_enable;
-
-	struct usart_hw_ops const *ops;
-};
-
-/*
- * Compile time Per-USART configuration stored in flash.  Instances of this
- * structure are provided by the user of the USART.  This structure binds
- * together all information required to operate a USART.
- */
-struct usart_config {
-	/*
-	 * Pointer to USART HW configuration.  There is one HW configuration
-	 * per physical USART.
-	 */
-	struct usart_hw_config const *hw;
-
-	struct usart_rx const *rx;
-	struct usart_tx const *tx;
-
-	/*
-	 * Pointer to USART state structure.  The state structure maintains per
-	 * USART information.
-	 */
-	struct usart_state volatile *state;
-
-	/*
-	 * Baud rate for USART.
-	 */
-	int baud;
-
-	/* Other flags (rx/tx inversion, half-duplex). */
-#define USART_CONFIG_FLAG_RX_INV BIT(0)
-#define USART_CONFIG_FLAG_TX_INV BIT(1)
-#define USART_CONFIG_FLAG_HDSEL BIT(2)
-	unsigned int flags;
-
-	struct consumer consumer;
-	struct producer producer;
-};
-
-/*
- * Convenience macro for defining USARTs and their associated state and buffers.
- * NAME is used to construct the names of the usart_state struct, and
- * usart_config struct, the latter is just called NAME.
- *
- * HW is the name of the usart_hw_config provided by the variant specific code.
- *
- * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this USART
- * should write to and read from respectively.
- */
-/*
- * The following assertions can not be made because they require access to
- * non-const fields, but should be kept in mind.
- *
- * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
- * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
- */
-#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE)	\
-	((struct usart_config const) {					\
-		.hw       = &HW,					\
-		.rx       = &RX,					\
-		.tx       = &TX,					\
-		.state    = &((struct usart_state){}),			\
-		.baud     = BAUD,					\
-		.flags    = FLAGS,					\
-		.consumer = {						\
-			.queue = &TX_QUEUE,				\
-			.ops   = &TX.consumer_ops,			\
-		},							\
-		.producer = {						\
-			.queue = &RX_QUEUE,				\
-			.ops   = &RX.producer_ops,			\
-		},							\
-	})
-
-/*
- * Initialize the given USART.  Once init is finished the USART streams are
- * available for operating on.
- */
-void usart_init(struct usart_config const *config);
-
-/*
- * Shutdown the given USART.
- */
-void usart_shutdown(struct usart_config const *config);
-
-/*
- * Handle a USART interrupt.  The per-variant USART code creates bindings
- * for the variants interrupts to call this generic USART interrupt handler
- * with the appropriate usart_config.
- */
-void usart_interrupt(struct usart_config const *config);
-
-/*
- * Trigger tx interrupt to process tx data. Calling this function will set
- * TXIEIE of USART HW instance and trigger associated IRQ.
- */
-void usart_tx_start(struct usart_config const *config);
-
-/*
- * These are HW specific baud rate calculation and setting functions that the
- * peripheral variant code uses during initialization and clock frequency
- * change.  The baud rate divisor input frequency is passed in Hertz.
- */
-void usart_set_baud_f0_l(struct usart_config const *config, int baud,
-			int frequency_hz);
-void usart_set_baud_f(struct usart_config const *config, int baud,
-		int frequency_hz);
-
-/*
- * Allow specification of parity for this usart.
- * parity is 0: none, 1: odd, 2: even.
- */
-void usart_set_parity(struct usart_config const *config, int parity);
-
-/*
- * Check parity for this usart.
- * parity is 0: none, 1: odd, 2: even.
- */
-int usart_get_parity(struct usart_config const *config);
-
-/*
- * Set baud rate for this usart. Note that baud rate will get reset on
- * core frequency change, so this only makes sense if the board never
- * goes to deep idle.
- */
-void usart_set_baud(struct usart_config const *config, int baud);
-
-/*
- * Different families provide different ways of clearing the transmit complete
- * flag.  This function will be provided by the family specific implementation.
- */
-void usart_clear_tc(struct usart_config const *config);
-
-/*
- * Each family implementation provides the usart_get_configs function to access
- * a read only list of the configs that are currently enabled.
- */
-struct usart_configs {
-	/*
-	 * The family's usart_config array, entries in the array for disabled
-	 * configs will be NULL, enabled configs will point to the usart_config
-	 * that was enabled.  And the following will be true:
-	 *
-	 * configs[i]->hw->index == i;
-	 */
-	struct usart_config const * const *configs;
-
-	/*
-	 * The total possible number of configs that this family supports.
-	 * This will be the same as the number of usart_hw structs that the
-	 * family provides in its family specific usart header.
-	 */
-	size_t count;
-};
-
-struct usart_configs usart_get_configs(void);
-
-/*
- * This usart_tx structure contains function pointer to interrupt
- * handler implemented to send host response. Generic queue based
- * interrupt handler is not used for usart host transport.
- */
-extern struct usart_tx const usart_host_command_tx_interrupt;
-
-#endif /* __CROS_EC_USART_H */
diff --git a/chip/stm32/usart_host_command.c b/chip/stm32/usart_host_command.c
deleted file mode 100644
index f4d6a65fc4..0000000000
--- a/chip/stm32/usart_host_command.c
+++ /dev/null
@@ -1,616 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "clock.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "usart_rx_dma.h"
-#include "usart_host_command.h"
-#include "usart-stm32f4.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args)
-
-/*
- * Timeout to wait for complete request packet
- *
- * This value determines how long we should wait for entire packet to arrive.
- * USART host command handler should wait for at least 75% of
- * EC_MSG_DEADLINE_MS, before declaring timeout and dropping the packet.
- *
- * This timeout should be less than host's driver timeout to make sure that
- * last packet can be successfully discarded before AP attempts to resend
- * request. AP driver waits for EC_MSG_DEADLINE_MS = 200 before attempting a
- * retry.
- */
-#define USART_REQ_RX_TIMEOUT (150 * MSEC)
-
-/*
- * Timeout to wait for overrun bytes on USART
- *
- * This values determines how long call to process_request should be deferred
- * in case host is sending extra bytes. This value is based on DMA buffer size.
- *
- * There is no guarantee that AP will send continuous bytes on usart. Wait
- * for USART_DEFERRED_PROCESS_REQ_TIMEOUT_US to check if host is sending
- * extra bytes.
- * Note: This value affects the response latency.
- */
-#define USART_DEFERRED_PROCESS_REQ_TIMEOUT 300
-
-/*
- * Max data size for a version 3 request/response packet.  This is big enough
- * to handle a request/response header, flash write offset/size and 512 bytes 
- * of request payload or 224 bytes of response payload.
- */
-#define USART_MAX_REQUEST_SIZE 0x220
-#define USART_MAX_RESPONSE_SIZE 0x100
-
-/*
- * FIFO size for USART DMA. Should be big enough to handle worst case
- * data processing
- */
-#define USART_DMA_FIFO_SIZE 0x110
-
-/* Local definitions */
-
-/*
- * Raw USART RX/TX byte buffers.
- */
-static uint8_t usart_in_buffer[USART_MAX_REQUEST_SIZE] __aligned(4);
-static uint8_t usart_out_buffer[USART_MAX_RESPONSE_SIZE] __aligned(4);
-
-/*
- * Maintain head position of in buffer
- * Head always starts with zero and goes up to max bytes.
- * Once the buffer contents are read, it should go back to zero.
- */
-static uint16_t usart_in_head;
-
-/*
- * Maintain head position of out buffer
- * Head always starts from zero and goes up to max bytes.
- * Head is moved by tx interrupt handler to response size sent by host command
- * task. Once all the bytes are sent (head == tail) both should go back to 0.
- */
-static uint16_t usart_out_head;
-
-/*
- * Once the response is ready, get the datalen
- */
-static uint16_t usart_out_datalen;
-
-/*
- * Enumeration to maintain different states of incoming request from
- * host
- */
-static enum uart_host_command_state {
-	/*
-	 * USART host command handler not enabled.
-	 */
-	USART_HOST_CMD_STATE_DISABLED,
-
-	/*
-	 * Ready to receive next request
-	 * This state represents USART layer is initialized and ready to
-	 * receive host request. Once the response is sent, current_state is
-	 * reset to this state to accept next packet.
-	 */
-	USART_HOST_CMD_READY_TO_RX,
-
-	/*
-	 * Receiving request
-	 * After first byte is received current_state is moved to receiving
-	 * state until all the header bytes + datalen bytes are received.
-	 * If host_request_timeout was called in this state, it would be
-	 * because of an underrun situation.
-	 */
-	USART_HOST_CMD_RECEIVING,
-
-	/*
-	 * Receiving complete
-	 * Once all the header bytes + datalen bytes are received, current_state
-	 * is moved to complete. Ideally, host should wait for response or retry
-	 * timeout before sending anymore bytes, otherwise current_state will
-	 * be moved to overrun to represent extra bytes sent by host.
-	 */
-	USART_HOST_CMD_COMPLETE,
-
-	/*
-	 * Processing request
-	 * Once the process_request starts processing usart_in_buffer,
-	 * current_state is moved to processing state. Host should not send
-	 * any bytes in this state as it would be considered contiguous
-	 * request.
-	 */
-	USART_HOST_CMD_PROCESSING,
-
-	/*
-	 * Sending response
-	 * Once host task is ready with the response bytes, current_state is
-	 * moved to sending state.
-	 */
-	USART_HOST_CMD_SENDING,
-
-	/*
-	 * Received bad data
-	 * If bad packet header is received, current_state is moved to rx_bad
-	 * state and after rx_timeout all the bytes are dropped.
-	 */
-	USART_HOST_CMD_RX_BAD,
-
-	/*
-	 * Receiving data overrun bytes
-	 * If extra bytes are received after current_state is in complete,
-	 * host is sending extra bytes which indicates data overrun.
-	 */
-	USART_HOST_CMD_RX_OVERRUN,
-
-} current_state __aligned(4);
-
-/*
- * This diagram is the state machine representation of USART host
- * command layer.
- *
- * This layer is responsible for checking packet integrity of incoming bytes
- * on usart transceiver. It will only process packet header to check version,
- * data_len. This layer will not process payload bytes.
- *
- * STATE = USART_HOST_CMD_STATE_DISABLED
- *
- * Initialize USART and local variables
- *
- * STATE = USART_HOST_CMD_READY_TO_RX
- *
- *     |<---------- HOST RETRY TIMEOUT = 200 ms ---------->|
- *     |
- *     |--------------USART_REQ_RX_TIMEOUT------>|
- *     |     Underrun if request not complete -->|
- *     |                                         |<-- USART ready to rx
- *     |____REQUEST____                                      ____REQUEST____
- *     |     |         |                                    |     |         |
- *     | HDR | DATA    |                                    | HDR | DATA    |
- *     |_____|_________|                                    |_____|_________|
- *     |
- *     |<-- Request packet start
- *           |
- * STATE = USART_HOST_CMD_RECEIVING
- *           |
- *           |<-- HDR received, now we will wait for data len bytes
- *                     |
- * If bad packet is received, move state to rx_bad
- * STATE = USART_HOST_CMD_RX_BAD
- * Ignore data processing, print status on console and reset layer -----------
- *                     |                                                     |
- *                     |<-- Request packet end (data rx complete)            |
- *                     |                                                     |
- * If request_timeout is called, it represents packet underrun               |
- * Ignore data processing, print status on console and reset layer -----------
- *                     |                                                     |
- * STATE = USART_HOST_CMD_COMPLETE                                           |
- *                     |                                                     |
- *                     |<-- Deferred call to process request                 |
- *                     |                                                     |
- * If extra byte is received, move state to overrun                          |
- * STATE = USART_HOST_CMD_RX_OVERRUN                                         |
- * Ignore data processing, print status on console and reset layer -----------
- *                     |                                                     |
- *                  -->|  |<-- USART_DEFERRED_PROCESS_REQ_TIMEOUT            |
- *                        |    Start process request                         |
- *                        |                                                  |
- * STATE = USART_HOST_CMD_PROCESSING                                         |
- *                        |                                                  |
- * Send ec_host_request to host command task                                 |
- *                        |<-- Packet sent to host command task              |
- *                       >|  |<-- host command task process time             |
- *                           |<-- host command task ready for response       |
- *                           |                                               |
- * STATE = USART_HOST_CMD_SENDING                                            |
- *                           |                                               |
- *                           |____RESPONSE____                               |
- *                           |     |          |                              |
- *                           | HDR | DATA     |                              |
- *                           |_____|__________|                              |
- *                                            |                              |
- *                                            |<-- Response send complete    |
- *                                                                           |
- * STATE = USART_HOST_CMD_READY_TO_RX          <------------------------------
- */
-
-/*
- * Local function definition
- */
-static void usart_host_command_reset(void);
-static void usart_host_command_request_timeout(void);
-static void usart_host_command_process_request(void);
-static void usart_host_command_process_response(struct host_packet *pkt);
-/*
- * Local variable declaration
- */
-
-/*
- * Configure dma instance for rx
- *
- * STM32_DMAS_USART1_RX is the DMA channel to be used for reception. This DMA
- * channel is for the USART peripheral.
- *
- * A unnamed, valid, empty usart_rx_dma_state structure is required to manage
- * DMA based transmission.
- *
- * USART_DMA_FIFO_SIZE is size of the valid, unnamed  DMA circular buffer.
- * This buffer is large enough to process worst case interrupt latency this
- * layer can encounter.
- */
-static struct usart_rx_dma const usart_host_command_rx_dma = {
-	.usart_rx = {
-		.producer_ops = {
-				.read = NULL,
-			},
-		.init      = usart_rx_dma_init,
-		.interrupt = usart_host_command_rx_dma_interrupt,
-		.info      = USART_RX_DMA_INFO,
-	},
-	.state       = &((struct usart_rx_dma_state) {}),
-	.fifo_buffer = ((uint8_t[USART_DMA_FIFO_SIZE]) {}),
-	.fifo_size   = USART_DMA_FIFO_SIZE,
-	.channel     = STM32_DMAS_USART1_RX,
-};
-
-/*
- * Configure USART structure with hardware, interrupt handlers, baudrate.
- */
-static struct usart_config const tl_usart = {
-	.hw	= &CONFIG_UART_HOST_COMMAND_HW,
-	.rx	= &usart_host_command_rx_dma.usart_rx,
-	.tx	= &usart_host_command_tx_interrupt,
-	.state	= &((struct usart_state){}),
-	.baud	= CONFIG_UART_HOST_COMMAND_BAUD_RATE,
-	.flags	= 0,
-};
-
-/*
- * Local function declaration
- */
-
-/*
- * This function will be called only if request rx timed out.
- * Drop the packet and put tl state into RX_READY
- */
-static void usart_host_command_request_timeout(void)
-{
-	switch (current_state) {
-	case USART_HOST_CMD_RECEIVING:
-		/* If state is receiving then timeout was hit due to underrun */
-		CPRINTS("USART HOST CMD ERROR: Request underrun detected.");
-		break;
-
-	case USART_HOST_CMD_RX_OVERRUN:
-		/* If state is rx_overrun then timeout was hit because
-		 * process request was cancelled and extra rx bytes were
-		 * dropped
-		 */
-		CPRINTS("USART HOST CMD ERROR: Request overrun detected.");
-		break;
-
-	case USART_HOST_CMD_RX_BAD:
-		/* If state is rx_bad then packet header was bad and process
-		 * request was cancelled to drop all incoming bytes.
-		 */
-		CPRINTS("USART HOST CMD ERROR: Bad packet header detected.");
-		break;
-
-	default:
-		CPRINTS("USART HOST CMD ERROR: Request timeout mishandled");
-	}
-
-	/* Reset host command layer to accept new request */
-	usart_host_command_reset();
-}
-DECLARE_DEFERRED(usart_host_command_request_timeout);
-
-/*
- * This function is called from interrupt handler after entire packet is
- * received.
- */
-static void usart_host_command_process_request(void)
-{
-	/* Handle usart_in_buffer as ec_host_request */
-	struct ec_host_request *ec_request =
-			(struct ec_host_request *)usart_in_buffer;
-
-	/* Prepare host_packet for host command task */
-	static struct host_packet uart_packet;
-
-	/*
-	 * Disable interrupts before processing request to be sent
-	 * to host command task.
-	 */
-	interrupt_disable();
-
-	/*
-	 * In case rx interrupt handler was called in this function's prologue,
-	 * host was trying to send extra byte(s) exactly when
-	 * USART_DEFERRED_PROCESS_REQ_TIMEOUT expired. If state is
-	 * not USART_HOST_CMD_COMPLETE, overrun condition is already
-	 * handled.
-	 */
-	if (current_state != USART_HOST_CMD_COMPLETE) {
-		/* Enable interrupts before exiting this function. */
-		interrupt_enable();
-
-		return;
-	}
-
-	/* Move current_state to USART_HOST_CMD_PROCESSING */
-	current_state = USART_HOST_CMD_PROCESSING;
-
-	/* Enable interrupts as current_state is safely handled. */
-	interrupt_enable();
-
-	/*
-	 * Cancel deferred call to timeout handler as request
-	 * received was good.
-	 */
-	hook_call_deferred(
-		&usart_host_command_request_timeout_data,
-		-1);
-
-	uart_packet.send_response = usart_host_command_process_response;
-	uart_packet.request = usart_in_buffer;
-	uart_packet.request_temp = NULL;
-	uart_packet.request_max = sizeof(usart_in_buffer);
-	uart_packet.request_size =
-			host_request_expected_size(ec_request);
-	uart_packet.response = usart_out_buffer;
-	uart_packet.response_max = sizeof(usart_out_buffer);
-	uart_packet.response_size = 0;
-	uart_packet.driver_result = EC_RES_SUCCESS;
-
-	/* Process usart_packet */
-	host_packet_receive(&uart_packet);
-}
-DECLARE_DEFERRED(usart_host_command_process_request);
-
-/*
- * This function is called from host command task after it is ready with a
- * response.
- */
-static void usart_host_command_process_response(struct host_packet *pkt)
-{
-	/* Disable interrupts before entering critical section. */
-	interrupt_disable();
-
-	/*
-	 * Send host command response in usart_out_buffer via
-	 * tx_interrupt_handler.
-	 *
-	 * Send response if current state is USART_HOST_CMD_PROCESSING
-	 * state. If this layer is in any other state drop response and
-	 * let request timeout handler handle state transitions.
-	 */
-	if (current_state != USART_HOST_CMD_PROCESSING) {
-		/* Enable interrupts before exiting critical section. */
-		interrupt_enable();
-
-		return;
-	}
-
-	/* Move to sending state. */
-	current_state = USART_HOST_CMD_SENDING;
-
-	/* Enable interrupts before exiting critical section. */
-	interrupt_enable();
-
-	usart_out_datalen = pkt->response_size;
-	usart_out_head = 0;
-
-	/* Start sending response to host via usart tx by
-	 * triggering tx interrupt.
-	 */
-	usart_tx_start(&tl_usart);
-}
-
-/*
- * This function will drop current request, clear buffers.
- */
-static void usart_host_command_reset(void)
-{
-	/* Cancel deferred call to process_request. */
-	hook_call_deferred(
-		&usart_host_command_process_request_data,
-		-1);
-
-	/* Cancel deferred call to timeout handler. */
-	hook_call_deferred(
-		&usart_host_command_request_timeout_data,
-		-1);
-
-	/*
-	 * Disable interrupts before entering critical region
-	 * Operations in this section should be minimum to avoid
-	 * harming the real-time characteristics of the runtime.
-	 */
-	interrupt_disable();
-
-	/* Clear in buffer, head and datalen */
-	usart_in_head = 0;
-
-	/* Clear out buffer, head and datalen */
-	usart_out_datalen = 0;
-	usart_out_head = 0;
-
-	/* Move to ready state*/
-	current_state = USART_HOST_CMD_READY_TO_RX;
-
-	/* Enable interrupts before exiting critical region
-	 */
-	interrupt_enable();
-}
-
-/*
- * Exported functions
- */
-
-/*
- * Initialize USART host command layer.
- */
-void usart_host_command_init(void)
-{
-	/* USART host command layer starts in DISABLED state */
-	current_state = USART_HOST_CMD_STATE_DISABLED;
-
-	/* Initialize transport uart */
-	usart_init(&tl_usart);
-
-	/* Initialize local variables */
-	usart_in_head = 0;
-	usart_out_head = 0;
-	usart_out_datalen = 0;
-
-	/* Move to ready state */
-	current_state = USART_HOST_CMD_READY_TO_RX;
-}
-
-/*
- * Function to handle incoming bytes from DMA interrupt handler
- *
- */
-size_t usart_host_command_rx_append_data(struct usart_config const *config,
-					 const uint8_t *src, size_t count)
-{
-	/* Define ec_host_request pointer to process in bytes later*/
-	struct ec_host_request *ec_request =
-			(struct ec_host_request *) usart_in_buffer;
-
-	/* Once the header is received, store the datalen */
-	static int usart_in_datalen;
-
-	/*
-	 * Host can send extra bytes than in header data_len
-	 * Only copy valid bytes in buffer
-	 */
-	if (current_state == USART_HOST_CMD_READY_TO_RX ||
-	    current_state == USART_HOST_CMD_RECEIVING ||
-	    (usart_in_head + count) < USART_MAX_REQUEST_SIZE) {
-		/* Copy all the bytes from DMA FIFO */
-		memcpy(usart_in_buffer + usart_in_head,
-			src, count);
-	}
-
-	/*
-	 * Add incoming byte count to usart_in_head.
-	 * Even if overflow bytes are not copied in buffer, maintain
-	 * the overflow count so that packet can be dropped later in this
-	 * function.
-	 */
-	usart_in_head += count;
-
-	if (current_state == USART_HOST_CMD_READY_TO_RX) {
-		/* Kick deferred call to request timeout handler */
-		hook_call_deferred(&usart_host_command_request_timeout_data,
-			USART_REQ_RX_TIMEOUT);
-
-		/* Move current state to receiving */
-		current_state = USART_HOST_CMD_RECEIVING;
-	}
-
-	if (usart_in_head >= sizeof(struct ec_host_request)) {
-		/* Buffer has request header. Check header and get data_len */
-		usart_in_datalen = host_request_expected_size(ec_request);
-
-		if (usart_in_datalen == 0 ||
-		    usart_in_datalen > USART_MAX_REQUEST_SIZE) {
-			/* EC host request version not compatible or
-			 * reserved byte is not zero.
-			 */
-			current_state = USART_HOST_CMD_RX_BAD;
-		} else if (usart_in_head == usart_in_datalen) {
-			/*
-			 * Once all the datalen bytes are received, wait for
-			 * USART_DEFERRED_PROCESS_REQ_TIMEOUT to call
-			 * process_request function. This is to catch overrun
-			 * bytes before processing the packet.
-			 */
-			hook_call_deferred(
-				&usart_host_command_process_request_data,
-				USART_DEFERRED_PROCESS_REQ_TIMEOUT);
-
-			/* If no data in request, packet is complete */
-			current_state = USART_HOST_CMD_COMPLETE;
-		} else if (usart_in_head > usart_in_datalen) {
-			/* Cancel deferred call to process_request */
-			hook_call_deferred(
-				&usart_host_command_process_request_data,
-				-1);
-
-			/* Move state to overrun*/
-			current_state = USART_HOST_CMD_RX_OVERRUN;
-		}
-	}
-
-	if (current_state == USART_HOST_CMD_PROCESSING)
-		/* Host should not send data before receiving a response.
-		 * Since the request was already sent to host command task,
-		 * just notify console about this. After response is sent
-		 * dma will be cleared to handle next packet
-		 */
-		CPRINTS("USART HOST CMD ERROR: Contiguous packets detected.");
-
-	/* Return count to show all incoming bytes were processed */
-	return count;
-}
-
-/*
- * This function processes the outgoing bytes from tl usart.
- */
-size_t usart_host_command_tx_remove_data(struct usart_config const *config,
-					 uint8_t *dest)
-{
-	size_t bytes_remaining = 0;
-
-	if (current_state == USART_HOST_CMD_SENDING &&
-	    usart_out_datalen != 0) {
-		/* Calculate byte_remaining in out_buffer */
-		bytes_remaining = usart_out_datalen - usart_out_head;
-
-		/* Get char on the head */
-		*((uint8_t *) dest) = usart_out_buffer[usart_out_head++];
-
-		/* If no bytes remaining, reset layer to accept next
-		 * request.
-		 */
-		if (bytes_remaining == 0)
-			usart_host_command_reset();
-	}
-
-	/* Return count of bytes remaining in out buffer */
-	return bytes_remaining;
-}
-
-/*
- * Get protocol information
- */
-enum ec_status usart_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions |= BIT(3);
-	r->max_request_packet_size = USART_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = USART_MAX_RESPONSE_SIZE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
diff --git a/chip/stm32/usart_host_command.h b/chip/stm32/usart_host_command.h
deleted file mode 100644
index ee41d8a59b..0000000000
--- a/chip/stm32/usart_host_command.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USART_HOST_COMMAND_H
-#define __CROS_EC_USART_HOST_COMMAND_H
-
-#include <stdarg.h>  /* For va_list */
-#include "common.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "usart.h"
-
-/*
- * Add data to host command layer buffer.
- */
-size_t usart_host_command_rx_append_data(struct usart_config const *config,
-					 const uint8_t *src, size_t count);
-
-/*
- * Remove data from the host command layer buffer.
- */
-size_t usart_host_command_tx_remove_data(struct usart_config const *config,
-					 uint8_t *dest);
-
-/*
- * Get USART protocol information. This function is called in runtime if
- * board's host command transport is USART.
- */
-enum ec_status usart_get_protocol_info(struct host_cmd_handler_args *args);
-
-/*
- * Initialize USART host command layer.
- */
-void usart_host_command_init(void);
-
-#endif /* __CROS_EC_USART_HOST_COMMAND_H */
diff --git a/chip/stm32/usart_info_command.c b/chip/stm32/usart_info_command.c
deleted file mode 100644
index 2649a97351..0000000000
--- a/chip/stm32/usart_info_command.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Console command to query USART state
- */
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "usart.h"
-
-static int command_usart_info(int argc, char **argv)
-{
-	struct usart_configs configs = usart_get_configs();
-	size_t i;
-
-	for (i = 0; i < configs.count; i++) {
-		struct usart_config const *config = configs.configs[i];
-
-		if (config == NULL)
-			continue;
-
-		ccprintf(
-			"USART%d\n"
-			"    dropped %d bytes\n"
-			"    overran %d times\n",
-			config->hw->index + 1,
-			atomic_clear((uint32_t *)&(config->state->rx_dropped)),
-			atomic_clear((uint32_t *)&(config->state->rx_overrun)));
-
-		if (config->rx->info)
-			config->rx->info(config);
-
-		if (config->tx->info)
-			config->tx->info(config);
-	}
-
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(usart_info,
-			command_usart_info,
-			NULL,
-			"Display USART info");
diff --git a/chip/stm32/usart_rx_dma.c b/chip/stm32/usart_rx_dma.c
deleted file mode 100644
index a185878261..0000000000
--- a/chip/stm32/usart_rx_dma.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "usart_rx_dma.h"
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "registers.h"
-#include "system.h"
-#include "usart_host_command.h"
-#include "util.h"
-
-typedef size_t (*add_data_t)(struct usart_config const *config,
-	const uint8_t *src, size_t count);
-
-void usart_rx_dma_init(struct usart_config const *config)
-{
-	struct usart_rx_dma const *dma_config =
-		DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx);
-
-	intptr_t base = config->hw->base;
-
-	struct dma_option options = {
-		.channel = dma_config->channel,
-		.periph  = (void *)&STM32_USART_RDR(base),
-		.flags   = (STM32_DMA_CCR_MSIZE_8_BIT |
-			    STM32_DMA_CCR_PSIZE_8_BIT |
-			    STM32_DMA_CCR_CIRC),
-	};
-
-	if (IS_ENABLED(CHIP_FAMILY_STM32F4))
-		options.flags |= STM32_DMA_CCR_CHANNEL(STM32_REQ_USART1_RX);
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
-	STM32_USART_CR3(base) |= STM32_USART_CR3_DMAR;
-
-	dma_config->state->index     = 0;
-	dma_config->state->max_bytes = 0;
-
-	dma_start_rx(&options, dma_config->fifo_size, dma_config->fifo_buffer);
-}
-
-static void usart_rx_dma_interrupt_common(
-		struct usart_config const *config,
-		add_data_t add_data)
-{
-	struct usart_rx_dma const *dma_config =
-		DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx);
-
-	dma_chan_t *channel  = dma_get_channel(dma_config->channel);
-	size_t     new_index = dma_bytes_done(channel, dma_config->fifo_size);
-	size_t     old_index = dma_config->state->index;
-	size_t     new_bytes = 0;
-	size_t     added     = 0;
-
-	if (new_index > old_index) {
-		new_bytes = new_index - old_index;
-
-		added = add_data(config,
-				dma_config->fifo_buffer + old_index,
-				new_bytes);
-	} else if (new_index < old_index) {
-		/*
-		 * Handle the case where the received bytes are not contiguous
-		 * in the circular DMA buffer.  This is done with two queue
-		 * adds.
-		 */
-		new_bytes = dma_config->fifo_size - (old_index - new_index);
-
-		added = add_data(config,
-				dma_config->fifo_buffer + old_index,
-				dma_config->fifo_size - old_index) +
-			add_data(config,
-				dma_config->fifo_buffer,
-				new_index);
-	} else {
-		/* (new_index == old_index): nothing to add to the queue. */
-	}
-
-	atomic_add((uint32_t *)&(config->state->rx_dropped), new_bytes - added);
-
-	if (dma_config->state->max_bytes < new_bytes)
-		dma_config->state->max_bytes = new_bytes;
-
-	dma_config->state->index = new_index;
-}
-
-static size_t queue_add(struct usart_config const *config,
-			const uint8_t *src, size_t count)
-{
-	return queue_add_units(config->producer.queue, (void *)src, count);
-}
-
-void usart_rx_dma_interrupt(struct usart_config const *config)
-{
-	usart_rx_dma_interrupt_common(config, &queue_add);
-}
-
-
-#if defined(CONFIG_USART_HOST_COMMAND)
-void usart_host_command_rx_dma_interrupt(struct usart_config const *config)
-{
-	usart_rx_dma_interrupt_common(config,
-				      &usart_host_command_rx_append_data);
-}
-#endif /* CONFIG_USART_HOST_COMMAND */
-
-void usart_rx_dma_info(struct usart_config const *config)
-{
-	struct usart_rx_dma const *dma_config =
-		DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx);
-
-	ccprintf("    DMA RX max_bytes %d\n",
-		 atomic_clear((uint32_t *)&dma_config->state->max_bytes));
-}
diff --git a/chip/stm32/usart_rx_dma.h b/chip/stm32/usart_rx_dma.h
deleted file mode 100644
index 064ab8046c..0000000000
--- a/chip/stm32/usart_rx_dma.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Hybrid DMA/Interrupt based USART RX driver for STM32
- */
-#ifndef __CROS_EC_USART_RX_DMA_H
-#define __CROS_EC_USART_RX_DMA_H
-
-#include "producer.h"
-#include "dma.h"
-#include "queue.h"
-#include "usart.h"
-
-/*
- * Only reference the usart_rx_dma_info function if CONFIG_CMD_USART_INFO
- * is defined.  This allows the compiler to remove this function as dead code
- * when CONFIG_CMD_USART_INFO is not defined.
- */
-#ifdef CONFIG_CMD_USART_INFO
-#define USART_RX_DMA_INFO usart_rx_dma_info
-#else
-#define USART_RX_DMA_INFO NULL
-#endif
-
-/*
- * Construct a USART RX instance for DMA using the given DMA channel.
- *
- * This macro creates a new usart_rx_dma struct, complete with in RAM state,
- * the contained usart_rx struct can be used in initializing a usart_config
- * struct.
- *
- * CHANNEL is the DMA channel to be used for reception.  This must be a valid
- * DMA channel for the USART peripheral and any alternate channel mappings must
- * be handled by the board specific code.
- *
- * FIFO_SIZE is the number of bytes (which does not need to be a power of two)
- * to use for the DMA circular buffer.  This buffer must be large enough to
- * hide the worst case interrupt latency the system will encounter.  The DMA
- * RX driver adds to the output of the usart_info command a high water mark
- * of how many bytes were transferred out of this FIFO on any one interrupt.
- * This value can be used to correctly size the FIFO by setting the FIFO_SIZE
- * to something large, stress test the USART, and run usart_info.  After a
- * reasonable stress test the "DMA RX max_bytes" value will be a reasonable
- * size for the FIFO (perhaps +10% for safety).
- */
-#define USART_RX_DMA(CHANNEL, FIFO_SIZE)				\
-	((struct usart_rx_dma const) {					\
-		.usart_rx = {						\
-			.producer_ops = {				\
-				.read = NULL,				\
-			},						\
-									\
-			.init      = usart_rx_dma_init,			\
-			.interrupt = usart_rx_dma_interrupt,		\
-			.info      = USART_RX_DMA_INFO,			\
-		},							\
-									\
-		.state       = &((struct usart_rx_dma_state) {}),	\
-		 .fifo_buffer = ((uint8_t[FIFO_SIZE]) {}),		\
-		 .fifo_size   = FIFO_SIZE,				\
-		 .channel     = CHANNEL,				\
-	})
-
-/*
- * In RAM state required to manage DMA based transmission.
- */
-struct usart_rx_dma_state {
-	/*
-	 * Previous value of dma_bytes_done.  This will wrap when the DMA fills
-	 * the queue.
-	 */
-	size_t index;
-
-	/*
-	 * Maximum number of bytes transferred in any one RX interrupt.
-	 */
-	uint32_t max_bytes;
-};
-
-/*
- * Extension of the usart_rx struct to include required configuration for
- * DMA based transmission.
- */
-struct usart_rx_dma {
-	struct usart_rx usart_rx;
-
-	struct usart_rx_dma_state volatile *state;
-
-	uint8_t *fifo_buffer;
-	size_t  fifo_size;
-
-	enum dma_channel channel;
-};
-
-/*
- * Function pointers needed to initialize a usart_rx struct.  These shouldn't
- * be called in any other context as they assume that the producer or config
- * that they are passed was initialized with a complete usart_rx_dma struct.
- */
-void usart_rx_dma_init(struct usart_config const *config);
-void usart_rx_dma_interrupt(struct usart_config const *config);
-
-/*
- * Function pointers needed to initialize host command rx dma interrupt.
- * This should be only called from usart host command layer.
- */
-void usart_host_command_rx_dma_interrupt(struct usart_config const *config);
-
-/*
- * Debug function, used to print DMA RX statistics to the console.
- */
-void usart_rx_dma_info(struct usart_config const *config);
-
-#endif /* __CROS_EC_USART_RX_DMA_H */
diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c
deleted file mode 120000
index a756455f9b..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32f0.c
+++ /dev/null
@@ -1 +0,0 @@
-usart_rx_interrupt.c
\ No newline at end of file
diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c
deleted file mode 120000
index a756455f9b..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32f3.c
+++ /dev/null
@@ -1 +0,0 @@
-usart_rx_interrupt.c
\ No newline at end of file
diff --git a/chip/stm32/usart_rx_interrupt-stm32f4.c b/chip/stm32/usart_rx_interrupt-stm32f4.c
deleted file mode 100644
index 198c6dd180..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32f4.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupt based USART RX driver for STM32F0 and STM32F4 */
-
-#include "usart.h"
-
-#include "atomic.h"
-#include "common.h"
-#include "queue.h"
-#include "registers.h"
-
-static void usart_rx_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-	defined(CHIP_FAMILY_STM32L4)
-	STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS;
-#endif
-}
-
-static void usart_rx_interrupt_handler(struct usart_config const *config)
-{
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
-
-	if (status & STM32_USART_SR_RXNE) {
-		uint8_t byte = STM32_USART_RDR(base);
-
-		if (!queue_add_unit(config->producer.queue, &byte))
-			atomic_add((uint32_t *)&(config->state->rx_dropped), 1);
-	}
-}
-
-struct usart_rx const usart_rx_interrupt = {
-	.producer_ops = {
-		/*
-		 * Nothing to do here, we either had enough space in the queue
-		 * when a character came in or we dropped it already.
-		 */
-		.read = NULL,
-	},
-
-	.init      = usart_rx_init,
-	.interrupt = usart_rx_interrupt_handler,
-	.info      = NULL,
-};
diff --git a/chip/stm32/usart_rx_interrupt-stm32l.c b/chip/stm32/usart_rx_interrupt-stm32l.c
deleted file mode 100644
index 24ca7a0487..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32l.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupt based USART RX driver for STM32L */
-
-#include "usart.h"
-
-#include "atomic.h"
-#include "common.h"
-#include "queue.h"
-#include "registers.h"
-
-static void usart_rx_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
-}
-
-static void usart_rx_interrupt_handler(struct usart_config const *config)
-{
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
-
-	/*
-	 * We have to check and clear the overrun error flag on STM32L because
-	 * we can't disable it.
-	 */
-	if (status & STM32_USART_SR_ORE) {
-		/*
-		 * In the unlikely event that the overrun error bit was set but
-		 * the RXNE bit was not (possibly because a read was done from
-		 * RDR without first reading the status register) we do a read
-		 * here to clear the overrun error bit.
-		 */
-		if (!(status & STM32_USART_SR_RXNE))
-			(void)STM32_USART_RDR(config->hw->base);
-
-		atomic_add((uint32_t *)&(config->state->rx_overrun), 1);
-	}
-
-	if (status & STM32_USART_SR_RXNE) {
-		uint8_t byte = STM32_USART_RDR(base);
-
-		if (!queue_add_unit(config->producer.queue, &byte))
-			atomic_add((uint32_t *)&(config->state->rx_dropped), 1);
-	}
-}
-
-struct usart_rx const usart_rx_interrupt = {
-	.producer_ops = {
-		/*
-		 * Nothing to do here, we either had enough space in the queue
-		 * when a character came in or we dropped it already.
-		 */
-		.read = NULL,
-	},
-
-	.init      = usart_rx_init,
-	.interrupt = usart_rx_interrupt_handler,
-	.info      = NULL,
-};
diff --git a/chip/stm32/usart_rx_interrupt-stm32l5.c b/chip/stm32/usart_rx_interrupt-stm32l5.c
deleted file mode 100644
index fa644b6baf..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32l5.c
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "usart_rx_interrupt-stm32l.c"
diff --git a/chip/stm32/usart_rx_interrupt.c b/chip/stm32/usart_rx_interrupt.c
deleted file mode 100644
index 3bc30d4aaf..0000000000
--- a/chip/stm32/usart_rx_interrupt.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupt based USART RX driver for STM32F0 and STM32F3 */
-
-#include "usart.h"
-
-#include "atomic.h"
-#include "common.h"
-#include "queue.h"
-#include "registers.h"
-
-static void usart_rx_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
-	STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS;
-}
-
-static void usart_rx_interrupt_handler(struct usart_config const *config)
-{
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
-
-	if (status & STM32_USART_SR_RXNE) {
-		uint8_t byte = STM32_USART_RDR(base);
-
-		if (!queue_add_unit(config->producer.queue, &byte))
-			atomic_add((uint32_t *)&(config->state->rx_dropped), 1);
-	}
-}
-
-struct usart_rx const usart_rx_interrupt = {
-	.producer_ops = {
-		/*
-		 * Nothing to do here, we either had enough space in the queue
-		 * when a character came in or we dropped it already.
-		 */
-		.read = NULL,
-	},
-
-	.init      = usart_rx_init,
-	.interrupt = usart_rx_interrupt_handler,
-	.info      = NULL,
-};
diff --git a/chip/stm32/usart_tx_dma.c b/chip/stm32/usart_tx_dma.c
deleted file mode 100644
index 0c8e2c73d6..0000000000
--- a/chip/stm32/usart_tx_dma.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart_tx_dma.h"
-
-#include "usart.h"
-#include "common.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-void usart_tx_dma_written(struct consumer const *consumer, size_t count)
-{
-	struct usart_config const *config =
-		DOWNCAST(consumer, struct usart_config, consumer);
-
-	task_trigger_irq(config->hw->irq);
-}
-
-void usart_tx_dma_init(struct usart_config const *config)
-{
-	struct usart_tx_dma const *dma_config =
-		DOWNCAST(config->tx, struct usart_tx_dma const, usart_tx);
-
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_TE;
-	STM32_USART_CR3(base) |= STM32_USART_CR3_DMAT;
-
-	dma_config->state->dma_active = 0;
-}
-
-static void usart_tx_dma_start(struct usart_config const *config,
-			       struct usart_tx_dma const *dma_config)
-{
-	struct usart_tx_dma_state volatile *state = dma_config->state;
-	intptr_t                           base   = config->hw->base;
-
-	struct dma_option options = {
-		.channel = dma_config->channel,
-		.periph  = (void *)&STM32_USART_TDR(base),
-		.flags   = (STM32_DMA_CCR_MSIZE_8_BIT |
-			    STM32_DMA_CCR_PSIZE_8_BIT),
-	};
-
-	/*
-	 * Limit our DMA transfer.  If we didn't do this then it would be
-	 * possible to start a large DMA transfer of an entirely full buffer
-	 * that would hold up any additional writes to the TX queue
-	 * unnecessarily.
-	 */
-	state->chunk.count = MIN(state->chunk.count, dma_config->max_bytes);
-
-	dma_prepare_tx(&options, state->chunk.count, state->chunk.buffer);
-
-	state->dma_active = 1;
-
-	usart_clear_tc(config);
-	STM32_USART_CR1(base) |= STM32_USART_CR1_TCIE;
-
-	dma_go(dma_get_channel(options.channel));
-}
-
-static void usart_tx_dma_stop(struct usart_config const *config,
-			      struct usart_tx_dma const *dma_config)
-{
-	dma_config->state->dma_active = 0;
-
-	STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_TCIE;
-}
-
-void usart_tx_dma_interrupt(struct usart_config const *config)
-{
-	struct usart_tx_dma const *dma_config =
-		DOWNCAST(config->tx, struct usart_tx_dma const, usart_tx);
-	struct usart_tx_dma_state volatile *state = dma_config->state;
-
-	/*
-	 * If we have completed a DMA transaction, or if we haven't yet started
-	 * one then we clean up and start one now.
-	 */
-	if ((STM32_USART_SR(config->hw->base) & STM32_USART_SR_TC) ||
-	    !state->dma_active) {
-		struct queue const *queue = config->consumer.queue;
-
-		/*
-		 * Only advance the queue head (indicating that we have read
-		 * units from the queue if we had an active DMA transfer.
-		 */
-		if (state->dma_active)
-			queue_advance_head(queue, state->chunk.count);
-
-		state->chunk = queue_get_read_chunk(queue);
-
-		if (state->chunk.count)
-			usart_tx_dma_start(config, dma_config);
-		else
-			usart_tx_dma_stop(config, dma_config);
-	}
-}
diff --git a/chip/stm32/usart_tx_dma.h b/chip/stm32/usart_tx_dma.h
deleted file mode 100644
index c17164e04a..0000000000
--- a/chip/stm32/usart_tx_dma.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * DMA based USART TX driver for STM32
- */
-#ifndef __CROS_EC_USART_TX_DMA_H
-#define __CROS_EC_USART_TX_DMA_H
-
-#include "consumer.h"
-#include "dma.h"
-#include "queue.h"
-#include "usart.h"
-
-/*
- * Construct a USART TX instance for DMA using the given DMA channel.
- *
- * This macro creates a new usart_tx_dma struct, complete with in RAM state,
- * the contained usart_tx struct can be used in initializing a usart_config
- * struct.
- *
- * CHANNEL is the DMA channel to be used for transmission.  This must be a
- * valid DMA channel for the USART peripheral and any alternate channel
- * mappings must be handled by the board specific code.
- *
- * MAX_BYTES is the maximum size in bytes of a single DMA transfer.  This
- * allows the board to tune how often the TX engine updates the queue state.
- * A larger number here could cause the queue to appear full for longer than
- * required because the queue isn't notified that it has been read from until
- * after the DMA transfer completes.
- */
-#define USART_TX_DMA(CHANNEL, MAX_BYTES)			\
-	((struct usart_tx_dma const) {				\
-		.usart_tx = {					\
-			.consumer_ops = {			\
-				.written = usart_tx_dma_written,\
-			},					\
-								\
-			.init      = usart_tx_dma_init,		\
-			.interrupt = usart_tx_dma_interrupt,	\
-			.info      = NULL,			\
-		},						\
-								\
-		.state     = &((struct usart_tx_dma_state){}),	\
-		.channel   = CHANNEL,				\
-		.max_bytes = MAX_BYTES,				\
-	})
-
-/*
- * In RAM state required to manage DMA based transmission.
- */
-struct usart_tx_dma_state {
-	/*
-	 * The current chunk of queue buffer being used for transmission.  Once
-	 * the transfer is complete, this is used to update the TX queue head
-	 * pointer as well.
-	 */
-	struct queue_chunk chunk;
-
-	/*
-	 * Flag indicating whether a DMA transfer is currently active.
-	 */
-	int dma_active;
-};
-
-/*
- * Extension of the usart_tx struct to include required configuration for
- * DMA based transmission.
- */
-struct usart_tx_dma {
-	struct usart_tx usart_tx;
-
-	struct usart_tx_dma_state volatile *state;
-
-	enum dma_channel channel;
-
-	size_t max_bytes;
-};
-
-/*
- * Function pointers needed to initialize a usart_tx struct.  These shouldn't
- * be called in any other context as they assume that the consumer or config
- * that they are passed was initialized with a complete usart_tx_dma struct.
- */
-void usart_tx_dma_written(struct consumer const *consumer, size_t count);
-void usart_tx_dma_flush(struct consumer const *consumer);
-void usart_tx_dma_init(struct usart_config const *config);
-void usart_tx_dma_interrupt(struct usart_config const *config);
-
-#endif /* __CROS_EC_USART_TX_DMA_H */
diff --git a/chip/stm32/usart_tx_interrupt.c b/chip/stm32/usart_tx_interrupt.c
deleted file mode 100644
index d8d441ba1b..0000000000
--- a/chip/stm32/usart_tx_interrupt.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupt based USART TX driver for STM32 */
-
-#include "usart.h"
-
-#include "common.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "usart_host_command.h"
-#include "util.h"
-
-typedef size_t (*remove_data_t)(struct usart_config const *config,
-				uint8_t *dest);
-
-static void usart_tx_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_TE;
-}
-
-static void usart_written(struct consumer const *consumer, size_t count)
-{
-	struct usart_config const *config =
-		DOWNCAST(consumer, struct usart_config, consumer);
-
-	/*
-	 * Enable USART interrupt.  This causes the USART interrupt handler to
-	 * start fetching from the TX queue if it wasn't already.
-	 */
-	if (count)
-		STM32_USART_CR1(config->hw->base) |= STM32_USART_CR1_TXEIE;
-}
-
-static void usart_tx_interrupt_handler_common(
-		struct usart_config const *config,
-		remove_data_t remove_data)
-{
-	intptr_t base = config->hw->base;
-	uint8_t  byte;
-
-	if (!(STM32_USART_SR(base) & STM32_USART_SR_TXE))
-		return;
-
-	if (remove_data(config, &byte)) {
-		STM32_USART_TDR(base) = byte;
-
-		/*
-		 * Make sure the TXE interrupt is enabled and that we won't go
-		 * into deep sleep.  This invocation of the USART interrupt
-		 * handler may have been manually triggered to start
-		 * transmission.
-		 */
-		disable_sleep(SLEEP_MASK_UART);
-
-		STM32_USART_CR1(base) |= STM32_USART_CR1_TXEIE;
-	} else {
-		/*
-		 * The TX queue is empty, disable the TXE interrupt and enable
-		 * deep sleep mode. The TXE interrupt will remain disabled
-		 * until a write call happens.
-		 */
-		enable_sleep(SLEEP_MASK_UART);
-
-		STM32_USART_CR1(base) &= ~STM32_USART_CR1_TXEIE;
-	}
-}
-
-static size_t queue_remove(struct usart_config const *config, uint8_t *dest)
-{
-	return queue_remove_unit(config->consumer.queue, (void *) dest);
-}
-
-static void usart_tx_interrupt_handler(struct usart_config const *config)
-{
-	usart_tx_interrupt_handler_common(config, &queue_remove);
-}
-
-void usart_tx_start(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	/* If interrupt is already enabled, nothing to do */
-	if (STM32_USART_CR1(base) & STM32_USART_CR1_TXEIE)
-		return;
-
-	disable_sleep(SLEEP_MASK_UART);
-	STM32_USART_CR1(base) |= (STM32_USART_CR1_TXEIE);
-
-	task_trigger_irq(config->hw->irq);
-}
-
-struct usart_tx const usart_tx_interrupt = {
-	.consumer_ops = {
-		.written = usart_written,
-	},
-
-	.init      = usart_tx_init,
-	.interrupt = usart_tx_interrupt_handler,
-	.info      = NULL,
-};
-
-#if defined(CONFIG_USART_HOST_COMMAND)
-
-static void usart_host_command_tx_interrupt_handler(
-		struct usart_config const *config)
-{
-	usart_tx_interrupt_handler_common(config,
-		&usart_host_command_tx_remove_data);
-}
-
-struct usart_tx const usart_host_command_tx_interrupt = {
-	.consumer_ops = {
-		.written = usart_written,
-	},
-
-	.init      = usart_tx_init,
-	.interrupt = usart_host_command_tx_interrupt_handler,
-	.info      = NULL,
-};
-#endif /* CONFIG_USART_HOST_COMMAND */
diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c
deleted file mode 100644
index 08c0a17455..0000000000
--- a/chip/stm32/usb-stm32f0.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32F0 Family specific USB functionality
- */
-
-#include "registers.h"
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	STM32_USB_BCDR |= BIT(15) /* DPPU */;
-}
-
-void usb_disconnect(void)
-{
-	/* disable pull-up on DP to disconnect */
-	STM32_USB_BCDR &= ~BIT(15) /* DPPU */;
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stm32f3.c b/chip/stm32/usb-stm32f3.c
deleted file mode 100644
index 2376d00b41..0000000000
--- a/chip/stm32/usb-stm32f3.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32F3 Family specific USB functionality
- */
-
-#include "usb-stm32f3.h"
-
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	usb_board_connect();
-}
-
-void usb_disconnect(void)
-{
-	usb_board_disconnect();
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stm32f3.h b/chip/stm32/usb-stm32f3.h
deleted file mode 100644
index 196c43a53a..0000000000
--- a/chip/stm32/usb-stm32f3.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32F3 Family specific USB functionality
- */
-
-/*
- * A device that uses an STM32F3 part will need to define these two functions
- * which are used to connect and disconnect the device from the USB bus.  This
- * is usually accomplished by enabling a pullup on the DP USB line.  The pullup
- * should be enabled by default so that the STM32 will enumerate correctly in
- * DFU mode (which doesn't know how to enable the DP pullup, so it assumes that
- * the pullup is always there).
- */
-void usb_board_connect(void);
-void usb_board_disconnect(void);
diff --git a/chip/stm32/usb-stm32g4.c b/chip/stm32/usb-stm32g4.c
deleted file mode 100644
index b4402f670d..0000000000
--- a/chip/stm32/usb-stm32g4.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32G4 Family specific USB functionality
- */
-
-#include "registers.h"
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	STM32_USB_BCDR |= STM32_USB_BCDR_DPPU;
-}
-
-void usb_disconnect(void)
-{
-	/* disable pull-up on DP to disconnect */
-	STM32_USB_BCDR &= ~STM32_USB_BCDR_DPPU;
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stm32l.c b/chip/stm32/usb-stm32l.c
deleted file mode 100644
index bb9838531b..0000000000
--- a/chip/stm32/usb-stm32l.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32L Family specific USB functionality
- */
-
-#include "registers.h"
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	STM32_SYSCFG_PMC |= 1;
-}
-
-void usb_disconnect(void)
-{
-	/* disable pull-up on DP to disconnect */
-	STM32_SYSCFG_PMC &= ~1;
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stm32l5.c b/chip/stm32/usb-stm32l5.c
deleted file mode 100644
index 9eaa622815..0000000000
--- a/chip/stm32/usb-stm32l5.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "registers.h"
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	STM32_USB_BCDR |= STM32_USB_BCDR_DPPU;
-}
-
-void usb_disconnect(void)
-{
-	/* disable pull-up on DP to disconnect */
-	STM32_USB_BCDR &= ~STM32_USB_BCDR_DPPU;
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stream.c b/chip/stm32/usb-stream.c
deleted file mode 100644
index 7429832f10..0000000000
--- a/chip/stm32/usb-stream.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "common.h"
-#include "config.h"
-#include "link_defs.h"
-#include "printf.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usart.h"
-#include "usb_hw.h"
-#include "usb-stream.h"
-
-static size_t rx_read(struct usb_stream_config const *config)
-{
-	uintptr_t address = btable_ep[config->endpoint].rx_addr;
-	size_t count = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK;
-
-	/*
-	 * Only read the received USB packet if there is enough space in the
-	 * receive queue.
-	 */
-	if (count > queue_space(config->producer.queue))
-		return 0;
-
-	return queue_add_memcpy(config->producer.queue,
-				(void *) address,
-				count,
-				memcpy_from_usbram);
-}
-
-static size_t tx_write(struct usb_stream_config const *config)
-{
-	uintptr_t address = btable_ep[config->endpoint].tx_addr;
-	size_t    count   = queue_remove_memcpy(config->consumer.queue,
-						(void *) address,
-						config->tx_size,
-						memcpy_to_usbram);
-
-	btable_ep[config->endpoint].tx_count = count;
-
-	return count;
-}
-
-static int tx_valid(struct usb_stream_config const *config)
-{
-	return (STM32_USB_EP(config->endpoint) & EP_TX_MASK) == EP_TX_VALID;
-}
-
-static int rx_valid(struct usb_stream_config const *config)
-{
-	return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) == EP_RX_VALID;
-}
-
-static int rx_disabled(struct usb_stream_config const *config)
-{
-	return config->state->rx_disabled;
-}
-
-static void usb_read(struct producer const *producer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(producer, struct usb_stream_config, producer);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-static void usb_written(struct consumer const *consumer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(consumer, struct usb_stream_config, consumer);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-struct producer_ops const usb_stream_producer_ops = {
-	.read = usb_read,
-};
-
-struct consumer_ops const usb_stream_consumer_ops = {
-	.written = usb_written,
-};
-
-void usb_stream_deferred(struct usb_stream_config const *config)
-{
-	if (!tx_valid(config) && tx_write(config))
-		STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0);
-
-	if (!rx_valid(config) && !rx_disabled(config) && rx_read(config))
-		STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0);
-}
-
-void usb_stream_tx(struct usb_stream_config const *config)
-{
-	STM32_TOGGLE_EP(config->endpoint, 0, 0, 0);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-void usb_stream_rx(struct usb_stream_config const *config)
-{
-	STM32_TOGGLE_EP(config->endpoint, 0, 0, 0);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-static usb_uint usb_ep_rx_size(size_t bytes)
-{
-	if (bytes < 64)
-		return bytes << 9;
-	else
-		return 0x8000 | ((bytes - 32) << 5);
-}
-
-void usb_stream_event(struct usb_stream_config const *config,
-		      enum usb_ep_event evt)
-{
-	int i;
-
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	i = config->endpoint;
-
-	btable_ep[i].tx_addr  = usb_sram_addr(config->tx_ram);
-	btable_ep[i].tx_count = 0;
-
-	btable_ep[i].rx_addr  = usb_sram_addr(config->rx_ram);
-	btable_ep[i].rx_count = usb_ep_rx_size(config->rx_size);
-
-	config->state->rx_waiting = 0;
-
-	STM32_USB_EP(i) = ((i <<  0) | /* Endpoint Addr*/
-			   (2 <<  4) | /* TX NAK */
-			   (0 <<  9) | /* Bulk EP */
-			   (rx_disabled(config) ? EP_RX_NAK : EP_RX_VALID));
-}
-
-int usb_usart_interface(struct usb_stream_config const *config,
-			struct usart_config const *usart,
-			int interface,
-			usb_uint *rx_buf, usb_uint *tx_buf)
-{
-	struct usb_setup_packet req;
-
-	usb_read_setup_packet(rx_buf, &req);
-
-	if (req.bmRequestType != (USB_DIR_OUT |
-				  USB_TYPE_VENDOR |
-				  USB_RECIP_INTERFACE))
-		return -1;
-
-	if (req.wIndex  != interface ||
-	    req.wLength != 0)
-		return -1;
-
-	switch (req.bRequest) {
-	/* Set parity. */
-	case USB_USART_SET_PARITY:
-		usart_set_parity(usart, req.wValue);
-		break;
-	case USB_USART_SET_BAUD:
-		usart_set_baud(usart, req.wValue * 100);
-		break;
-
-	/* TODO(nsanders): support reading parity. */
-	/* TODO(nsanders): support reading baud. */
-	default:
-		return -1;
-	}
-
-	btable_ep[0].tx_count = 0;
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, EP_STATUS_OUT);
-	return 0;
-}
diff --git a/chip/stm32/usb-stream.h b/chip/stm32/usb-stream.h
deleted file mode 100644
index 915d8905cd..0000000000
--- a/chip/stm32/usb-stream.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_STREAM_H
-#define __CROS_EC_USB_STREAM_H
-
-#if defined(CHIP_FAMILY_STM32F4)
-#include "usb_dwc_stream.h"
-#else
-
-/* STM32 USB STREAM driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "consumer.h"
-#include "hooks.h"
-#include "producer.h"
-#include "queue.h"
-#include "usart.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-#include <stdint.h>
-
-/*
- * Per-USB stream state stored in RAM.  Zero initialization of this structure
- * by the BSS initialization leaves it in a valid and correctly initialized
- * state, so there is no need currently for a usb_stream_init style function.
- */
-struct usb_stream_state {
-	/*
-	 * Flag indicating that there is a full RX buffer in the USB packet RAM
-	 * that we were not able to move into the RX queue because there was
-	 * not enough room when the packet was initially received.  The
-	 * producer read operation checks this flag so that once there is
-	 * room in the queue it can copy the RX buffer into the queue and
-	 * restart USB reception by marking the RX buffer as VALID.
-	 */
-	int rx_waiting;
-	/*
-	 * Flag indicating that the incoming data on the USB link are discarded.
-	 */
-	int rx_disabled;
-};
-
-/*
- * Compile time Per-USB stream configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB stream.  This structure binds
- * together all information required to operate a USB stream.
- */
-struct usb_stream_config {
-	/*
-	 * Pointer to usb_stream_state structure.  The state structure
-	 * maintains per USB stream information.
-	 */
-	struct usb_stream_state volatile *state;
-
-	/*
-	 * Endpoint index, and pointers to the USB packet RAM buffers.
-	 */
-	int endpoint;
-
-	/*
-	 * Deferred function to call to handle USB and Queue request.
-	 */
-	const struct deferred_data *deferred;
-
-	size_t rx_size;
-	size_t tx_size;
-
-	usb_uint *rx_ram;
-	usb_uint *tx_ram;
-
-	struct consumer consumer;
-	struct producer producer;
-};
-
-/*
- * These function tables are defined by the USB Stream driver and are used to
- * initialize the consumer and producer in the usb_stream_config.
- */
-extern struct consumer_ops const usb_stream_consumer_ops;
-extern struct producer_ops const usb_stream_producer_ops;
-
-/*
- * Convenience macro for defining USB streams and their associated state and
- * buffers.
- *
- * NAME is used to construct the names of the packet RAM buffers, trampoline
- * functions, usb_stream_state struct, and usb_stream_config struct, the
- * latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * stream.
- *
- * INTERFACE_CLASS, INTERFACE_SUBCLASS, INTERFACE_PROTOCOL are the
- * .bInterfaceClass, .bInterfaceSubClass, and .bInterfaceProtocol fields
- * respectively in the USB interface descriptor.
- *
- * INTERFACE_NAME is the index of the USB string descriptor (iInterface).
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- *
- * RX_SIZE and TX_SIZE are the number of bytes of USB packet RAM to allocate
- * for the RX and TX packets respectively.  The valid values for these
- * parameters are dictated by the USB peripheral.
- *
- * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this driver
- * should write to and read from respectively.
- */
-/*
- * The following assertions can not be made because they require access to
- * non-const fields, but should be kept in mind.
- *
- * BUILD_ASSERT(RX_QUEUE.buffer_units >= RX_SIZE);
- * BUILD_ASSERT(TX_QUEUE.buffer_units >= TX_SIZE);
- * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
- * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
- */
-#define USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       INTERFACE_CLASS,				\
-			       INTERFACE_SUBCLASS,			\
-			       INTERFACE_PROTOCOL,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)				\
-									\
-	BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE);			\
-	BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE);			\
-	BUILD_ASSERT(RX_SIZE > 0);					\
-	BUILD_ASSERT(TX_SIZE > 0);					\
-	BUILD_ASSERT((RX_SIZE <   64 && (RX_SIZE & 0x01) == 0) ||	\
-		     (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0));	\
-	BUILD_ASSERT((TX_SIZE <   64 && (TX_SIZE & 0x01) == 0) ||	\
-		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));	\
-									\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \
-	static struct usb_stream_state CONCAT2(NAME, _state);		\
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	struct usb_stream_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state),			\
-		.endpoint  = ENDPOINT,					\
-		.deferred  = &CONCAT2(NAME, _deferred__data),		\
-		.rx_size   = RX_SIZE,					\
-		.tx_size   = TX_SIZE,					\
-		.rx_ram    = CONCAT2(NAME, _ep_rx_buffer),		\
-		.tx_ram    = CONCAT2(NAME, _ep_tx_buffer),		\
-		.consumer  = {						\
-			.queue = &TX_QUEUE,				\
-			.ops   = &usb_stream_consumer_ops,		\
-		},							\
-		.producer  = {						\
-			.queue = &RX_QUEUE,				\
-			.ops   = &usb_stream_producer_ops,		\
-		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = RX_SIZE,				\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_stream_tx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_stream_rx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_stream_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
-		       CONCAT2(NAME, _ep_event));			\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_stream_deferred(&NAME); }
-
-/* This is a short version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG(NAME,						\
-			  INTERFACE,					\
-			  INTERFACE_NAME,				\
-			  ENDPOINT,					\
-			  RX_SIZE,					\
-			  TX_SIZE,					\
-			  RX_QUEUE,					\
-			  TX_QUEUE)					\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)
-
-/* Declare a utility interface for setting parity/baud. */
-#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG)			\
-	static int CONCAT2(NAME,  _interface_)(usb_uint *rx_buf,	\
-					      usb_uint *tx_buf)		\
-	{ return usb_usart_interface(&NAME, &USART_CFG, INTERFACE,	\
-					rx_buf, tx_buf); }		\
-	USB_DECLARE_IFACE(INTERFACE,					\
-			  CONCAT2(NAME, _interface_))
-
-/* This is a medium version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG_USART_IFACE(NAME,				\
-				      INTERFACE,			\
-				      INTERFACE_NAME,			\
-				      ENDPOINT,				\
-				      RX_SIZE,				\
-				      TX_SIZE,				\
-				      RX_QUEUE,				\
-				      TX_QUEUE,				\
-				      USART_CFG)			\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE);				\
-	USB_USART_IFACE(NAME, INTERFACE, USART_CFG)
-
-/*
- * Handle USB and Queue request in a deferred callback.
- */
-void usb_stream_deferred(struct usb_stream_config const *config);
-
-/*
- * Handle control interface requests.
- */
-enum usb_usart {
-	USB_USART_REQ_PARITY = 0,
-	USB_USART_SET_PARITY = 1,
-	USB_USART_REQ_BAUD = 2,
-	USB_USART_SET_BAUD = 3,
-};
-
-/*
- * baud rate is req/set in multiples of 100, to avoid overflowing
- * 16-bit integer.
- */
-#define USB_USART_BAUD_MULTIPLIER 100
-
-int usb_usart_interface(struct usb_stream_config const *config,
-		    struct usart_config const *usart,
-		    int interface, usb_uint *rx_buf, usb_uint *tx_buf);
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB stream driver.
- */
-void usb_stream_tx(struct usb_stream_config const *config);
-void usb_stream_rx(struct usb_stream_config const *config);
-void usb_stream_event(struct usb_stream_config const *config,
-		      enum usb_ep_event evt);
-
-#endif /* defined(CHIP_FAMILY_STM32F4) */
-#endif /* __CROS_EC_USB_STREAM_H */
diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c
deleted file mode 100644
index 0077815a27..0000000000
--- a/chip/stm32/usb.c
+++ /dev/null
@@ -1,957 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "flash.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-#ifdef CONFIG_USB_BOS
-/* v2.10 (vs 2.00) BOS Descriptor provided */
-#define USB_DEV_BCDUSB 0x0210
-#else
-#define USB_DEV_BCDUSB 0x0200
-#endif
-
-#ifndef USB_DEV_CLASS
-#define USB_DEV_CLASS USB_CLASS_PER_INTERFACE
-#endif
-
-#ifndef CONFIG_USB_BCD_DEV
-#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */
-#endif
-
-#ifndef CONFIG_USB_SERIALNO
-#define USB_STR_SERIALNO 0
-#else
-static int usb_load_serial(void);
-#endif
-
-#define USB_RESUME_TIMEOUT_MS 3000
-
-/* USB Standard Device Descriptor */
-static const struct usb_device_descriptor dev_desc = {
-	.bLength = USB_DT_DEVICE_SIZE,
-	.bDescriptorType = USB_DT_DEVICE,
-	.bcdUSB = USB_DEV_BCDUSB,
-	.bDeviceClass = USB_DEV_CLASS,
-	.bDeviceSubClass = 0x00,
-	.bDeviceProtocol = 0x00,
-	.bMaxPacketSize0 = USB_MAX_PACKET_SIZE,
-	.idVendor = CONFIG_USB_VID,
-	.idProduct = CONFIG_USB_PID,
-	.bcdDevice = CONFIG_USB_BCD_DEV,
-	.iManufacturer = USB_STR_VENDOR,
-	.iProduct = USB_STR_PRODUCT,
-	.iSerialNumber = USB_STR_SERIALNO,
-	.bNumConfigurations = 1
-};
-
-/* USB Configuration Descriptor */
-const struct usb_config_descriptor USB_CONF_DESC(conf) = {
-	.bLength = USB_DT_CONFIG_SIZE,
-	.bDescriptorType = USB_DT_CONFIGURATION,
-	.wTotalLength = 0x0BAD, /* no of returned bytes, set at runtime */
-	.bNumInterfaces = USB_IFACE_COUNT,
-	.bConfigurationValue = 1,
-	.iConfiguration = USB_STR_VERSION,
-	.bmAttributes = 0x80 /* Reserved bit */
-#ifdef CONFIG_USB_SELF_POWERED  /* bus or self powered */
-		      | 0x40
-#endif
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-		      | 0x20
-#endif
-	,
-	.bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2),
-};
-
-const uint8_t usb_string_desc[] = {
-	4, /* Descriptor size */
-	USB_DT_STRING,
-	0x09, 0x04 /* LangID = 0x0409: U.S. English */
-};
-
-/* Endpoint table in USB controller RAM */
-struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable;
-/* Control endpoint (EP0) buffers */
-static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
-static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
-
-#define EP0_BUF_TX_SRAM_ADDR ((void *) usb_sram_addr(ep0_buf_tx))
-
-static int set_addr;
-/* remaining size of descriptor data to transfer */
-static int desc_left;
-/* pointer to descriptor data if any */
-static const uint8_t *desc_ptr;
-/* interface that should handle the next tx transaction */
-static uint8_t iface_next = USB_IFACE_COUNT;
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-/* remote wake up feature enabled */
-static int remote_wakeup_enabled;
-#endif
-
-void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet)
-{
-	packet->bmRequestType = buffer[0] & 0xff;
-	packet->bRequest      = buffer[0] >> 8;
-	packet->wValue        = buffer[1];
-	packet->wIndex        = buffer[2];
-	packet->wLength       = buffer[3];
-}
-
-struct usb_descriptor_patch {
-	const void *address;
-	uint16_t data;
-};
-
-static struct usb_descriptor_patch desc_patches[USB_DESC_PATCH_COUNT];
-
-void set_descriptor_patch(enum usb_desc_patch_type type,
-			  const void *address, uint16_t data)
-{
-	desc_patches[type].address = address;
-	desc_patches[type].data = data;
-}
-
-void *memcpy_to_usbram_ep0_patch(const void *src, size_t n)
-{
-	int i;
-	void *ret;
-
-	ret = memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), src, n);
-
-	for (i = 0; i < USB_DESC_PATCH_COUNT; i++) {
-		unsigned int offset = desc_patches[i].address - src;
-
-		if (offset >= n)
-			continue;
-
-		memcpy_to_usbram((void *)(usb_sram_addr(ep0_buf_tx) + offset),
-			&desc_patches[i].data, sizeof(desc_patches[i].data));
-	}
-
-	return ret;
-}
-
-static void ep0_send_descriptor(const uint8_t *desc, int len,
-				uint16_t fixup_size)
-{
-	/* do not send more than what the host asked for */
-	len = MIN(ep0_buf_rx[3], len);
-	/*
-	 * if we cannot transmit everything at once,
-	 * keep the remainder for the next IN packet
-	 */
-	if (len >= USB_MAX_PACKET_SIZE) {
-		desc_left = len - USB_MAX_PACKET_SIZE;
-		desc_ptr = desc + USB_MAX_PACKET_SIZE;
-		len = USB_MAX_PACKET_SIZE;
-	}
-	memcpy_to_usbram_ep0_patch(desc, len);
-	if (fixup_size) /* set the real descriptor size */
-		ep0_buf_tx[1] = fixup_size;
-	btable_ep[0].tx_count = len;
-	/* send the null OUT transaction if the transfer is complete */
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-			desc_left ? 0 : EP_STATUS_OUT);
-}
-
-/* Requests on the control endpoint (aka EP0) */
-static void ep0_rx(void)
-{
-	uint16_t req = ep0_buf_rx[0]; /* bRequestType | bRequest */
-
-	/* reset any incomplete descriptor transfer */
-	desc_ptr = NULL;
-	iface_next = USB_IFACE_COUNT;
-
-	/* interface specific requests */
-	if ((req & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
-		uint8_t iface = ep0_buf_rx[2] & 0xff;
-		if (iface < USB_IFACE_COUNT) {
-			int ret;
-
-			ret = usb_iface_request[iface](ep0_buf_rx, ep0_buf_tx);
-			if (ret < 0)
-				goto unknown_req;
-			if (ret == 1)
-				iface_next = iface;
-			return;
-		}
-	}
-	/* vendor specific request */
-	if ((req & USB_TYPE_MASK) == USB_TYPE_VENDOR) {
-#ifdef CONFIG_WEBUSB_URL
-		uint8_t b_req = req >> 8; /* bRequest in the transfer */
-		uint16_t idx = ep0_buf_rx[2]; /* wIndex in the transfer */
-
-		if (b_req == 0x01 && idx == WEBUSB_REQ_GET_URL) {
-			int len = *(uint8_t *)webusb_url;
-
-			ep0_send_descriptor(webusb_url, len, 0);
-			return;
-		}
-#endif
-		goto unknown_req;
-	}
-
-	/* TODO check setup bit ? */
-	if (req == (USB_DIR_IN | (USB_REQ_GET_DESCRIPTOR << 8))) {
-		uint8_t type = ep0_buf_rx[1] >> 8;
-		uint8_t idx = ep0_buf_rx[1] & 0xff;
-		const uint8_t *desc;
-		int len;
-
-		switch (type) {
-		case USB_DT_DEVICE: /* Setup : Get device descriptor */
-			desc = (void *)&dev_desc;
-			len = sizeof(dev_desc);
-			break;
-		case USB_DT_CONFIGURATION: /* Setup : Get configuration desc */
-			desc = __usb_desc;
-			len = USB_DESC_SIZE;
-			break;
-#ifdef CONFIG_USB_BOS
-		case USB_DT_BOS: /* Setup : Get BOS descriptor */
-			desc = bos_ctx.descp;
-			len = bos_ctx.size;
-			break;
-#endif
-		case USB_DT_STRING: /* Setup : Get string descriptor */
-			if (idx >= USB_STR_COUNT)
-				/* The string does not exist : STALL */
-				goto unknown_req;
-#ifdef CONFIG_USB_SERIALNO
-			if (idx == USB_STR_SERIALNO)
-				desc = (uint8_t *)usb_serialno_desc;
-			else
-#endif
-				desc = usb_strings[idx];
-			len = desc[0];
-			break;
-		case USB_DT_DEVICE_QUALIFIER: /* Get device qualifier desc */
-			/* Not high speed : STALL next IN used as handshake */
-			goto unknown_req;
-		default: /* unhandled descriptor */
-			goto unknown_req;
-		}
-		ep0_send_descriptor(desc, len, type == USB_DT_CONFIGURATION ?
-						USB_DESC_SIZE : 0);
-	} else if (req == (USB_DIR_IN | (USB_REQ_GET_STATUS << 8))) {
-		uint16_t data = 0;
-		/* Get status */
-#ifdef CONFIG_USB_SELF_POWERED
-		data |= USB_REQ_GET_STATUS_SELF_POWERED;
-#endif
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-		if (remote_wakeup_enabled)
-			data |= USB_REQ_GET_STATUS_REMOTE_WAKEUP;
-#endif
-		memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, (void *)&data, 2);
-		btable_ep[0].tx_count = 2;
-		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-			  EP_STATUS_OUT /*null OUT transaction */);
-	} else if ((req & 0xff) == USB_DIR_OUT) {
-		switch (req >> 8) {
-		case USB_REQ_SET_FEATURE:
-		case USB_REQ_CLEAR_FEATURE:
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-			if (ep0_buf_rx[1] ==
-					USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) {
-				remote_wakeup_enabled =
-					((req >> 8) == USB_REQ_SET_FEATURE);
-				btable_ep[0].tx_count = 0;
-				STM32_TOGGLE_EP(0, EP_TX_RX_MASK,
-						EP_TX_RX_VALID, 0);
-				break;
-			}
-#endif
-			goto unknown_req;
-		case USB_REQ_SET_ADDRESS:
-			/* set the address after we got IN packet handshake */
-			set_addr = ep0_buf_rx[1] & 0xff;
-			/* need null IN transaction -> TX Valid */
-			btable_ep[0].tx_count = 0;
-			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-			break;
-		case USB_REQ_SET_CONFIGURATION:
-			/* uint8_t cfg = ep0_buf_rx[1] & 0xff; */
-			/* null IN for handshake */
-			btable_ep[0].tx_count = 0;
-			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-			break;
-		default: /* unhandled request */
-			goto unknown_req;
-		}
-
-	} else {
-		goto unknown_req;
-	}
-
-	return;
-unknown_req:
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_RX_VALID | EP_TX_STALL, 0);
-}
-
-static void ep0_tx(void)
-{
-	if (set_addr) {
-		STM32_USB_DADDR = set_addr | 0x80;
-		set_addr = 0;
-		CPRINTF("SETAD %02x\n", STM32_USB_DADDR);
-	}
-	if (desc_ptr) {
-		/* we have an on-going descriptor transfer */
-		int len = MIN(desc_left, USB_MAX_PACKET_SIZE);
-		memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, desc_ptr, len);
-		btable_ep[0].tx_count = len;
-		desc_left -= len;
-		desc_ptr += len;
-		STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID,
-				desc_left ? 0 : EP_STATUS_OUT);
-		/* send the null OUT transaction if the transfer is complete */
-		return;
-	}
-	if (iface_next < USB_IFACE_COUNT) {
-		int ret;
-
-		ret = usb_iface_request[iface_next](NULL, ep0_buf_tx);
-		if (ret < 0)
-			goto error;
-		if (ret == 0)
-			iface_next = USB_IFACE_COUNT;
-		return;
-	}
-
-error:
-	STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID, 0);
-}
-
-static void ep0_event(enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	STM32_USB_EP(0) = BIT(9) /* control EP */ |
-			  (2 << 4) /* TX NAK */ |
-			  (3 << 12) /* RX VALID */;
-
-	btable_ep[0].tx_addr = usb_sram_addr(ep0_buf_tx);
-	btable_ep[0].rx_addr = usb_sram_addr(ep0_buf_rx);
-	btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE/32-1) << 10);
-	btable_ep[0].tx_count = 0;
-}
-USB_DECLARE_EP(0, ep0_tx, ep0_rx, ep0_event);
-
-static void usb_reset(void)
-{
-	int ep;
-
-	for (ep = 0; ep < USB_EP_COUNT; ep++)
-		usb_ep_event[ep](USB_EVENT_RESET);
-
-	/*
-	 * set the default address : 0
-	 * as we are not configured yet
-	 */
-	STM32_USB_DADDR = 0 | 0x80;
-	CPRINTF("RST EP0 %04x\n", STM32_USB_EP(0));
-}
-
-#ifdef CONFIG_USB_SUSPEND
-static void usb_pm_change_notify_hooks(void)
-{
-	hook_notify(HOOK_USB_PM_CHANGE);
-}
-DECLARE_DEFERRED(usb_pm_change_notify_hooks);
-
-/* See RM0091 Reference Manual 30.5.5 Suspend/Resume events */
-static void usb_suspend(void)
-{
-	CPRINTF("SUS%d\n", remote_wakeup_enabled);
-
-	/*
-	 * usb_suspend can be called from hook task, make sure no interrupt is
-	 * modifying CNTR at the same time.
-	 */
-	interrupt_disable();
-	/* Set FSUSP bit to activate suspend mode */
-	STM32_USB_CNTR |= STM32_USB_CNTR_FSUSP;
-
-	/* Set USB low power mode */
-	STM32_USB_CNTR |= STM32_USB_CNTR_LP_MODE;
-	interrupt_enable();
-
-	clock_enable_module(MODULE_USB, 0);
-
-	/* USB is not in use anymore, we can (hopefully) sleep now. */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	hook_call_deferred(&usb_pm_change_notify_hooks_data, 0);
-}
-
-/*
- * SOF was received (set in interrupt), reset in usb_resume in the
- * unexpected state case.
- */
-static volatile int sof_received;
-
-static void usb_resume_deferred(void)
-{
-	uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-		>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
-
-	CPRINTF("RSMd %d %04x %d\n", state, STM32_USB_CNTR, sof_received);
-	if (sof_received == 0 && (state == 2 || state == 3))
-		usb_suspend();
-	else
-		hook_call_deferred(&usb_pm_change_notify_hooks_data, 0);
-}
-DECLARE_DEFERRED(usb_resume_deferred);
-
-static void usb_resume(void)
-{
-	uint32_t state;
-
-	clock_enable_module(MODULE_USB, 1);
-
-	/* Clear FSUSP bit to exit suspend mode */
-	STM32_USB_CNTR &= ~STM32_USB_CNTR_FSUSP;
-
-	/* USB is in use again */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-		>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
-
-	CPRINTF("RSM %d %04x\n", state, STM32_USB_CNTR);
-
-	/*
-	 * Reference manual tells we should go back to sleep if state is 10 or
-	 * 11. However, setting FSUSP and LP_MODE in this interrupt routine
-	 * seems to lock the USB controller (see b/35775088 and b/71688150).
-	 * Instead, we do it in a deferred routine. The host must assert the
-	 * reset condition for 20ms, so reading D+/D- after ~3ms should be safe
-	 * (there is no chance we end up sampling during a bus transaction).
-	 */
-	if (state == 2 || state == 3) {
-		/*
-		 * This function is already called from interrupt context so
-		 * there is no risk of race here.
-		 */
-		sof_received = 0;
-		STM32_USB_CNTR |= STM32_USB_CNTR_SOFM;
-		hook_call_deferred(&usb_resume_deferred_data, 3 * MSEC);
-	} else {
-		hook_call_deferred(&usb_pm_change_notify_hooks_data, 0);
-	}
-}
-
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-/*
- * Makes sure usb_wake is only run once. When 0, wake is in progress.
- */
-static volatile int usb_wake_done = 1;
-
-/*
- * ESOF counter (incremented in interrupt), RESUME bit is cleared when
- * this reaches 0. Also used to detect resume timeout.
- */
-static volatile int esof_count;
-
-__attribute__((weak))
-void board_usb_wake(void)
-{
-	/* Side-band USB wake, do nothing by default. */
-}
-
-/* Called 10ms after usb_wake started. */
-static void usb_wake_deferred(void)
-{
-	if (esof_count == 3) {
-		/*
-		 * If we reach here, it means that we are not counting ESOF/SOF
-		 * properly (either of these interrupts should occur every 1ms).
-		 * This should never happen if we implemented the resume logic
-		 * correctly.
-		 *
-		 * We reset the controller in that case, which recovers the
-		 * interface.
-		 */
-		CPRINTF("USB stuck\n");
-#if defined(STM32_RCC_APB1RSTR2_USBFSRST)
-		STM32_RCC_APB1RSTR2 |= STM32_RCC_APB1RSTR2_USBFSRST;
-		STM32_RCC_APB1RSTR2 &= STM32_RCC_APB1RSTR2_USBFSRST;
-#else
-		STM32_RCC_APB1RSTR |= STM32_RCC_PB1_USB;
-		STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_USB;
-#endif
-		usb_init();
-	}
-}
-DECLARE_DEFERRED(usb_wake_deferred);
-
-void usb_wake(void)
-{
-	if (!remote_wakeup_enabled ||
-	    !(STM32_USB_CNTR & STM32_USB_CNTR_FSUSP)) {
-		/*
-		 * USB wake not enabled, or already woken up, or already waking
-		 * up, nothing to do.
-		 */
-		return;
-	}
-
-	/* Only allow one caller at a time. */
-	if (!atomic_clear((int *)&usb_wake_done))
-		return;
-
-	CPRINTF("WAKE\n");
-
-	/*
-	 * Sometimes the USB controller gets stuck, and does not count SOF/ESOF
-	 * frames anymore, detect that.
-	 */
-	hook_call_deferred(&usb_wake_deferred_data, 10 * MSEC);
-
-	/*
-	 * Set RESUME bit for 1 to 15 ms, then clear it. We ask the interrupt
-	 * routine to count 3 ESOF interrupts, which should take between
-	 * 2 and 3 ms.
-	 */
-	esof_count = 3;
-
-	/* STM32_USB_CNTR can also be updated from interrupt context. */
-	interrupt_disable();
-	STM32_USB_CNTR |= STM32_USB_CNTR_RESUME |
-		STM32_USB_CNTR_ESOFM | STM32_USB_CNTR_SOFM;
-	interrupt_enable();
-
-	/* Try side-band wake as well. */
-	board_usb_wake();
-}
-#endif
-
-int usb_is_suspended(void)
-{
-	/* Either hardware block is suspended... */
-	if (STM32_USB_CNTR & STM32_USB_CNTR_FSUSP)
-		return 1;
-
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-	/* ... or we are currently waking up. */
-	if (!usb_wake_done)
-		return 1;
-#endif
-
-	return 0;
-}
-
-int usb_is_remote_wakeup_enabled(void)
-{
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-	return remote_wakeup_enabled;
-#else
-	return 0;
-#endif
-}
-#endif /* CONFIG_USB_SUSPEND */
-
-#if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_USB_REMOTE_WAKEUP)
-/*
- * Called by usb_interrupt when usb_wake is asking us to count esof_count ESOF
- * interrupts (one per millisecond), then disable RESUME, then wait for resume
- * to complete.
- */
-static void usb_interrupt_handle_wake(uint16_t status)
-{
-	int state;
-	int good;
-
-	esof_count--;
-
-	/* Keep counting. */
-	if (esof_count > 0)
-		return;
-
-	/* Clear RESUME bit. */
-	if (esof_count == 0)
-		STM32_USB_CNTR &= ~STM32_USB_CNTR_RESUME;
-
-	/* Then count down until state is resumed. */
-	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-				>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
-
-	/*
-	 * state 2, or receiving an SOF, means resume
-	 * completed successfully.
-	 */
-	good = (status & STM32_USB_ISTR_SOF) || (state == 2);
-
-	/* Either: state is ready, or we timed out. */
-	if (good || state == 3 || esof_count <= -USB_RESUME_TIMEOUT_MS) {
-		int ep;
-
-		STM32_USB_CNTR &= ~STM32_USB_CNTR_ESOFM;
-		usb_wake_done = 1;
-		if (!good) {
-			CPRINTF("wake error: cnt=%d state=%d\n",
-				esof_count, state);
-			usb_suspend();
-			return;
-		}
-
-		CPRINTF("RSMOK%d %d\n",	-esof_count, state);
-
-		for (ep = 1; ep < USB_EP_COUNT; ep++)
-			usb_ep_event[ep](USB_EVENT_DEVICE_RESUME);
-	}
-}
-#endif /* CONFIG_USB_SUSPEND && CONFIG_USB_REMOTE_WAKEUP */
-
-void usb_interrupt(void)
-{
-	uint16_t status = STM32_USB_ISTR;
-
-	if (status & STM32_USB_ISTR_RESET)
-		usb_reset();
-
-#ifdef CONFIG_USB_SUSPEND
-	if (status & STM32_USB_ISTR_SOF) {
-		sof_received = 1;
-		/*
-		 * The wake handler also only cares about the _first_ SOF that
-		 * is received, so we can disable that interrupt.
-		 */
-		STM32_USB_CNTR &= ~STM32_USB_CNTR_SOFM;
-	}
-
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-	if (status & (STM32_USB_ISTR_ESOF | STM32_USB_ISTR_SOF) &&
-			!usb_wake_done)
-		usb_interrupt_handle_wake(status);
-#endif
-
-	if (status & STM32_USB_ISTR_SUSP)
-		usb_suspend();
-
-	if (status & STM32_USB_ISTR_WKUP)
-		usb_resume();
-#endif
-
-	if (status & STM32_USB_ISTR_CTR) {
-		int ep = status & STM32_USB_ISTR_EP_ID_MASK;
-		if (ep < USB_EP_COUNT) {
-			if (status & STM32_USB_ISTR_DIR)
-				usb_ep_rx[ep]();
-			else
-				usb_ep_tx[ep]();
-		}
-		/* TODO: do it in a USB task */
-		/* task_set_event(, 1 << ep_task); */
-	}
-
-	/* ack only interrupts that we handled */
-	STM32_USB_ISTR = ~status;
-}
-DECLARE_IRQ(STM32_IRQ_USB_LP, usb_interrupt, 1);
-
-void usb_init(void)
-{
-	/* Enable USB device clock, possibly increasing system clock to 48MHz */
-	clock_enable_module(MODULE_USB, 1);
-
-	/* configure the pinmux */
-	gpio_config_module(MODULE_USB, 1);
-
-	/* power on sequence */
-
-	/* keep FRES (USB reset) and remove PDWN (power down) */
-	STM32_USB_CNTR = STM32_USB_CNTR_FRES;
-	udelay(1); /* startup time */
-	/* reset FRES and keep interrupts masked */
-	STM32_USB_CNTR = 0x00;
-	/* clear pending interrupts */
-	STM32_USB_ISTR = 0;
-
-	/* set descriptors table offset in dedicated SRAM */
-	STM32_USB_BTABLE = 0;
-
-	/* EXTI18 is USB wake up interrupt */
-	/* STM32_EXTI_RTSR |= BIT(18); */
-	/* STM32_EXTI_IMR |= BIT(18); */
-
-	/* Enable interrupt handlers */
-	task_enable_irq(STM32_IRQ_USB_LP);
-	/* set interrupts mask : reset/correct transfer/errors */
-	STM32_USB_CNTR = STM32_USB_CNTR_CTRM |
-			 STM32_USB_CNTR_PMAOVRM |
-			 STM32_USB_CNTR_ERRM |
-#ifdef CONFIG_USB_SUSPEND
-			 STM32_USB_CNTR_WKUPM |
-			 STM32_USB_CNTR_SUSPM |
-#endif
-			 STM32_USB_CNTR_RESETM;
-
-#ifdef CONFIG_USB_SERIALNO
-	usb_load_serial();
-#endif
-#ifndef CONFIG_USB_INHIBIT_CONNECT
-	usb_connect();
-#endif
-
-	CPRINTF("USB init done\n");
-}
-
-#ifndef CONFIG_USB_INHIBIT_INIT
-DECLARE_HOOK(HOOK_INIT, usb_init, HOOK_PRIO_DEFAULT);
-#endif
-
-void usb_release(void)
-{
-	/* signal disconnect to host */
-	usb_disconnect();
-
-	/* power down USB */
-	STM32_USB_CNTR = 0;
-
-	/* disable interrupt handlers */
-	task_disable_irq(STM32_IRQ_USB_LP);
-
-	/* unset pinmux */
-	gpio_config_module(MODULE_USB, 0);
-
-	/* disable USB device clock, possibly slowing down system clock */
-	clock_enable_module(MODULE_USB, 0);
-}
-/* ensure the host disconnects and reconnects over a sysjump */
-DECLARE_HOOK(HOOK_SYSJUMP, usb_release, HOOK_PRIO_DEFAULT);
-
-int usb_is_enabled(void)
-{
-	return clock_is_module_enabled(MODULE_USB);
-}
-
-void *memcpy_to_usbram(void *dest, const void *src, size_t n)
-{
-	int       unaligned =                 (((uintptr_t) dest) & 1);
-	usb_uint *d         = &__usb_ram_start[((uintptr_t) dest) / 2];
-	uint8_t  *s         = (uint8_t *) src;
-	int       i;
-
-	/*
-	 * Handle unaligned leading byte via read/modify/write.
-	 */
-	if (unaligned && n) {
-		*d = (*d & ~0xff00) | (*s << 8);
-		n--;
-		s++;
-		d++;
-	}
-
-	for (i = 0; i < n / 2; i++, s += 2)
-		*d++ = (s[1] << 8) | s[0];
-
-	/*
-	 * There is a trailing byte to write into a final USB packet memory
-	 * location, use a read/modify/write to be safe.
-	 */
-	if (n & 1)
-		*d = (*d & ~0x00ff) | *s;
-
-	return dest;
-}
-
-void *memcpy_from_usbram(void *dest, const void *src, size_t n)
-{
-	int             unaligned =                 (((uintptr_t) src) & 1);
-	usb_uint const *s         = &__usb_ram_start[((uintptr_t) src) / 2];
-	uint8_t        *d         = (uint8_t *) dest;
-	int             i;
-
-	if (unaligned && n) {
-		*d = *s >> 8;
-		n--;
-		s++;
-		d++;
-	}
-
-	for (i = 0; i < n / 2; i++) {
-		usb_uint value = *s++;
-
-		*d++ = (value >> 0) & 0xff;
-		*d++ = (value >> 8) & 0xff;
-	}
-
-	if (n & 1)
-		*d = *s;
-
-	return dest;
-}
-
-#ifdef CONFIG_USB_SERIALNO
-/* This will be subbed into USB_STR_SERIALNO. */
-struct usb_string_desc *usb_serialno_desc =
-	USB_WR_STRING_DESC(DEFAULT_SERIALNO);
-
-/* Update serial number */
-static int usb_set_serial(const char *serialno)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	int i;
-
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	/* Convert into unicode usb string desc. */
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++) {
-		sd->_data[i] = serialno[i];
-		if (serialno[i] == 0)
-			break;
-	}
-	/* Count wchars (w/o null terminator) plus size & type bytes. */
-	sd->_len = (i * 2) + 2;
-	sd->_type = USB_DT_STRING;
-
-	return EC_SUCCESS;
-}
-
-/* Retrieve serial number from pstate flash. */
-static int usb_load_serial(void)
-{
-	const char *serialno;
-	int rv;
-
-	serialno = board_read_serial();
-	if (!serialno)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = usb_set_serial(serialno);
-	return rv;
-}
-
-/* Save serial number into pstate region. */
-static int usb_save_serial(const char *serialno)
-{
-	int rv;
-
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	/* Save this new serial number to flash. */
-	rv = board_write_serial(serialno);
-	if (rv)
-		return rv;
-
-	/* Load this new serial number to memory. */
-	rv = usb_load_serial();
-	return rv;
-}
-
-static int command_serialno(int argc, char **argv)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	char buf[CONFIG_SERIALNO_LEN];
-	int rv = EC_SUCCESS;
-	int i;
-
-	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
-			ccprintf("Saving serial number\n");
-			rv = usb_save_serial(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
-			ccprintf("Loading serial number\n");
-			rv = usb_load_serial();
-		} else
-			return EC_ERROR_INVAL;
-	}
-
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++)
-		buf[i] = sd->_data[i];
-	ccprintf("Serial number: %s\n", buf);
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(serialno, command_serialno,
-	"load/set [value]",
-	"Read and write USB serial number");
-
-#endif  /* CONFIG_USB_SERIALNO */
-
-#ifdef CONFIG_MAC_ADDR
-
-/* Save MAC address into pstate region. */
-static int usb_save_mac_addr(const char *mac_addr)
-{
-	int rv;
-
-	if (!mac_addr) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Save this new MAC address to flash. */
-	rv = board_write_mac_addr(mac_addr);
-	if (rv) {
-		return rv;
-	}
-
-	/* Load this new MAC address to memory. */
-	if (board_read_mac_addr() != NULL) {
-		return EC_SUCCESS;
-	} else {
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-static int command_macaddr(int argc, char **argv)
-{
-	const char* buf;
-	int rv = EC_SUCCESS;
-
-	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
-			ccprintf("Saving MAC address\n");
-			rv = usb_save_mac_addr(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
-			ccprintf("Loading MAC address\n");
-		} else {
-			return EC_ERROR_INVAL;
-		}
-	}
-
-	buf = board_read_mac_addr();
-	if (buf == NULL) {
-		buf = DEFAULT_MAC_ADDR;
-	}
-	ccprintf("MAC address: %s\n", buf);
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr,
-	"load/set [value]",
-	"Read and write MAC address");
-
-#endif  /* CONFIG_MAC_ADDR */
diff --git a/chip/stm32/usb_console.c b/chip/stm32/usb_console.c
deleted file mode 100644
index b5666c8fbf..0000000000
--- a/chip/stm32/usb_console.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "link_defs.h"
-#include "printf.h"
-#include "queue.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
-
-static struct queue const tx_q = QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE,
-					    uint8_t);
-static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t);
-
-static int last_tx_ok = 1;
-
-static int is_reset;
-static int is_enabled = 1;
-static int is_readonly;
-
-/* USB-Serial descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = {
-	.bLength            = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType    = USB_DT_INTERFACE,
-	.bInterfaceNumber   = USB_IFACE_CONSOLE,
-	.bAlternateSetting  = 0,
-	.bNumEndpoints      = 2,
-	.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL,
-	.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL,
-	.iInterface         = USB_STR_CONSOLE_NAME,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = {
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = 0x80 | USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk IN */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 10
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = {
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk OUT */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 0
-};
-
-static usb_uint ep_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
-static usb_uint ep_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
-
-/* Forward declaration */
-static void handle_output(void);
-
-static void con_ep_tx(void)
-{
-	/* clear IT */
-	STM32_TOGGLE_EP(USB_EP_CONSOLE, 0, 0, 0);
-
-	/* Check bytes in the FIFO needed to transmitted */
-	handle_output();
-}
-
-static void con_ep_rx(void)
-{
-	int i;
-
-	for (i = 0; i < (btable_ep[USB_EP_CONSOLE].rx_count & RX_COUNT_MASK);
-	     i++) {
-		int val = ((i & 1) ?
-			   (ep_buf_rx[i >> 1] >> 8) :
-			   (ep_buf_rx[i >> 1] & 0xff));
-
-		QUEUE_ADD_UNITS(&rx_q, &val, 1);
-	}
-
-	/* clear IT */
-	STM32_TOGGLE_EP(USB_EP_CONSOLE, EP_RX_MASK, EP_RX_VALID, 0);
-
-	/* wake-up the console task */
-	console_has_input();
-}
-
-static void ep_event(enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	btable_ep[USB_EP_CONSOLE].tx_addr  = usb_sram_addr(ep_buf_tx);
-	btable_ep[USB_EP_CONSOLE].tx_count = 0;
-
-	btable_ep[USB_EP_CONSOLE].rx_addr  = usb_sram_addr(ep_buf_rx);
-	btable_ep[USB_EP_CONSOLE].rx_count =
-		0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
-
-	STM32_USB_EP(USB_EP_CONSOLE) = (USB_EP_CONSOLE | /* Endpoint Addr */
-					(2 << 4)       | /* TX NAK        */
-					(0 << 9)       | /* Bulk EP       */
-					(is_readonly ? EP_RX_NAK
-						     : EP_RX_VALID));
-
-	is_reset = 1;
-}
-
-USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event);
-
-static int __tx_char(void *context, int c)
-{
-	/* Do newline to CRLF translation */
-	if (c == '\n' && __tx_char(context, '\r'))
-		return 1;
-
-	/* Return 0 on success */
-	return !QUEUE_ADD_UNITS(&tx_q, &c, 1);
-}
-
-static void usb_enable_tx(int len)
-{
-	if (!is_enabled)
-		return;
-
-	btable_ep[USB_EP_CONSOLE].tx_count = len;
-	STM32_TOGGLE_EP(USB_EP_CONSOLE, EP_TX_MASK, EP_TX_VALID, 0);
-}
-
-static inline int usb_console_tx_valid(void)
-{
-	return (STM32_USB_EP(USB_EP_CONSOLE) & EP_TX_MASK) == EP_TX_VALID;
-}
-
-static int usb_wait_console(void)
-{
-	timestamp_t deadline = get_time();
-	int wait_time_us = 1;
-
-	if (!is_enabled || !usb_is_enabled())
-		return EC_SUCCESS;
-
-	deadline.val += USB_CONSOLE_TIMEOUT_US;
-
-	/*
-	 * If the USB console is not used, Tx buffer would never free up.
-	 * In this case, let's drop characters immediately instead of sitting
-	 * for some time just to time out. On the other hand, if the last
-	 * Tx is good, it's likely the host is there to receive data, and
-	 * we should wait so that we don't clobber the buffer.
-	 */
-	if (last_tx_ok) {
-		while (usb_console_tx_valid() || !is_reset) {
-			if (timestamp_expired(deadline, NULL)) {
-				last_tx_ok = 0;
-				return EC_ERROR_TIMEOUT;
-			}
-			if (wait_time_us < MSEC)
-				udelay(wait_time_us);
-			else
-				usleep(wait_time_us);
-			wait_time_us *= 2;
-		}
-
-		return EC_SUCCESS;
-	} else {
-		last_tx_ok = !usb_console_tx_valid();
-		return EC_SUCCESS;
-	}
-}
-
-/* Try to send some bytes from the Tx FIFO to the host */
-static void tx_fifo_handler(void)
-{
-	int ret;
-	size_t count;
-	usb_uint *buf = (usb_uint *)ep_buf_tx;
-
-	if (!is_reset)
-		return;
-
-	ret = usb_wait_console();
-	if (ret)
-		return;
-
-	count = 0;
-	while (count < USB_MAX_PACKET_SIZE) {
-		int val = 0;
-
-		if (!QUEUE_REMOVE_UNITS(&tx_q, &val, 1))
-			break;
-
-		if (!(count & 1))
-			buf[count/2] = val;
-		else
-			buf[count/2] |= val << 8;
-		count++;
-	}
-
-	if (count)
-		usb_enable_tx(count);
-}
-DECLARE_DEFERRED(tx_fifo_handler);
-
-static void handle_output(void)
-{
-	/* Wake up the Tx FIFO handler */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-}
-
-/*
- * Public USB console implementation below.
- */
-int usb_getc(void)
-{
-	int c = 0;
-
-	if (!is_enabled)
-		return -1;
-
-	if (!QUEUE_REMOVE_UNITS(&rx_q, &c, 1))
-		return -1;
-
-	return c;
-}
-
-int usb_putc(int c)
-{
-	int ret;
-
-	ret = __tx_char(NULL, c);
-	handle_output();
-
-	return ret;
-}
-
-int usb_puts(const char *outstr)
-{
-	/* Put all characters in the output buffer */
-	while (*outstr) {
-		if (__tx_char(NULL, *outstr++) != 0)
-			break;
-	}
-	handle_output();
-
-	/* Successful if we consumed all output */
-	return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS;
-}
-
-int usb_vprintf(const char *format, va_list args)
-{
-	int ret;
-
-	ret = vfnprintf(__tx_char, NULL, format, args);
-	handle_output();
-
-	return ret;
-}
-
-void usb_console_enable(int enabled, int readonly)
-{
-	is_enabled = enabled;
-	is_readonly = readonly;
-}
-
-int usb_console_tx_blocked(void)
-{
-	return is_enabled && usb_console_tx_valid();
-}
diff --git a/chip/stm32/usb_dwc.c b/chip/stm32/usb_dwc.c
deleted file mode 100644
index f4ee89f1f0..0000000000
--- a/chip/stm32/usb_dwc.c
+++ /dev/null
@@ -1,1423 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "flash.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "usb_hw.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_descriptor.h"
-#include "watchdog.h"
-
-
-/****************************************************************************/
-/* Debug output */
-
-/* Console output macro */
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-/* TODO: Something unexpected happened. Figure out how to report & fix it. */
-#define report_error(val)						\
-	CPRINTS("Unhandled USB event at %s line %d: 0x%x",		\
-		__FILE__, __LINE__, val)
-
-
-/****************************************************************************/
-/* Standard USB stuff */
-
-#ifdef CONFIG_USB_BOS
-/* v2.10 (vs 2.00) BOS Descriptor provided */
-#define USB_DEV_BCDUSB 0x0210
-#else
-#define USB_DEV_BCDUSB 0x0200
-#endif
-
-#ifndef USB_DEV_CLASS
-#define USB_DEV_CLASS USB_CLASS_PER_INTERFACE
-#endif
-
-#ifndef CONFIG_USB_BCD_DEV
-#define CONFIG_USB_BCD_DEV 0x0100		/* 1.00 */
-#endif
-
-#ifndef CONFIG_USB_SERIALNO
-#define USB_STR_SERIALNO 0
-#else
-static int usb_load_serial(void);
-#endif
-
-
-/* USB Standard Device Descriptor */
-static const struct usb_device_descriptor dev_desc = {
-	.bLength = USB_DT_DEVICE_SIZE,
-	.bDescriptorType = USB_DT_DEVICE,
-	.bcdUSB = USB_DEV_BCDUSB,
-	.bDeviceClass = USB_DEV_CLASS,
-	.bDeviceSubClass = 0x00,
-	.bDeviceProtocol = 0x00,
-	.bMaxPacketSize0 = USB_MAX_PACKET_SIZE,
-	.idVendor = USB_VID_GOOGLE,
-	.idProduct = CONFIG_USB_PID,
-	.bcdDevice = CONFIG_USB_BCD_DEV,
-	.iManufacturer = USB_STR_VENDOR,
-	.iProduct = USB_STR_PRODUCT,
-	.iSerialNumber = USB_STR_SERIALNO,
-	.bNumConfigurations = 1
-};
-
-/* USB Configuration Descriptor */
-const struct usb_config_descriptor USB_CONF_DESC(conf) = {
-	.bLength = USB_DT_CONFIG_SIZE,
-	.bDescriptorType = USB_DT_CONFIGURATION,
-	.wTotalLength = 0x0BAD,	 /* number of returned bytes, set at runtime */
-	.bNumInterfaces = USB_IFACE_COUNT,
-	.bConfigurationValue = 1,		/* Caution: hard-coded value */
-	.iConfiguration = USB_STR_VERSION,
-	.bmAttributes = 0x80 /* Reserved bit */
-#ifdef CONFIG_USB_SELF_POWERED  /* bus or self powered */
-		      | 0x40
-#endif
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-		      | 0x20
-#endif
-	,
-	.bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2),
-};
-
-const uint8_t usb_string_desc[] = {
-	4,					/* Descriptor size */
-	USB_DT_STRING,
-	0x09, 0x04			    /* LangID = 0x0409: U.S. English */
-};
-
-/****************************************************************************/
-/* Packet-handling stuff, specific to this SoC */
-
-/* Some internal state to keep track of what's going on */
-static enum {
-	WAITING_FOR_SETUP_PACKET,
-	DATA_STAGE_IN,
-	NO_DATA_STAGE,
-} what_am_i_doing;
-
-#ifdef DEBUG_ME
-static const char * const wat[3] = {
-	[WAITING_FOR_SETUP_PACKET] = "wait_for_setup",
-	[DATA_STAGE_IN] = "data_in",
-	[NO_DATA_STAGE] = "no_data",
-};
-#endif
-
-/* Programmer's Guide, Table 10-7 */
-enum table_case {
-	BAD_0,
-	TABLE_CASE_COMPLETE,
-	TABLE_CASE_SETUP,
-	TABLE_CASE_WTF,
-	TABLE_CASE_D,
-	TABLE_CASE_E,
-	BAD_6,
-	BAD_7,
-};
-
-static enum table_case decode_table_10_7(uint32_t doepint)
-{
-	enum table_case val = BAD_0;
-
-	/* Bits: SI, SPD, IOC */
-	if (doepint & DOEPINT_XFERCOMPL)
-		val += 1;
-	if (doepint & DOEPINT_SETUP)
-		val += 2;
-	return val;
-}
-
-/* For STATUS/OUT: Use two DMA descriptors, each with one-packet buffers */
-#define NUM_OUT_BUFFERS 2
-static uint8_t __aligned(4) ep0_setup_buf[USB_MAX_PACKET_SIZE];
-
-/* For IN: Several DMA descriptors, all pointing into one large buffer, so that
- * we can return the configuration descriptor as one big blob.
- */
-#define NUM_IN_PACKETS_AT_ONCE 4
-#define IN_BUF_SIZE (NUM_IN_PACKETS_AT_ONCE * USB_MAX_PACKET_SIZE)
-static uint8_t __aligned(4) ep0_in_buf[IN_BUF_SIZE];
-
-struct dwc_usb_ep ep0_ctl = {
-	.max_packet = USB_MAX_PACKET_SIZE,
-	.tx_fifo = 0,
-	.out_pending = 0,
-	.out_expected = 0,
-	.out_data = 0,
-	.out_databuffer = ep0_setup_buf,
-	.out_databuffer_max = sizeof(ep0_setup_buf),
-	.rx_deferred = 0,
-	.in_packets = 0,
-	.in_pending = 0,
-	.in_data = 0,
-	.in_databuffer = ep0_in_buf,
-	.in_databuffer_max = sizeof(ep0_in_buf),
-	.tx_deferred = 0,
-};
-
-/* Overall device state (USB 2.0 spec, section 9.1.1).
- * We only need a few, though.
- */
-static enum {
-	DS_DEFAULT,
-	DS_ADDRESS,
-	DS_CONFIGURED,
-} device_state;
-static uint8_t configuration_value;
-
-
-/* True if the HW Rx/OUT FIFO is currently listening. */
-int rx_ep_is_active(uint32_t ep_num)
-{
-	return (GR_USB_DOEPCTL(ep_num) & DXEPCTL_EPENA) ? 1 : 0;
-}
-
-/* Number of bytes the HW Rx/OUT FIFO has for us.
- *
- * @param ep_num	USB endpoint
- *
- * @returns		number of bytes ready, zero if none.
- */
-int rx_ep_pending(uint32_t ep_num)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-
-	return ep->out_pending;
-}
-
-/* True if the Tx/IN FIFO can take some bytes from us. */
-int tx_ep_is_ready(uint32_t ep_num)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-	int ready;
-
-	/* Is the tx hw idle? */
-	ready = !(GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA);
-
-	/* Is there no pending data? */
-	ready &= (ep->in_pending == 0);
-	return ready;
-}
-
-/* Write packets of data IN to the host.
- *
- * This function uses DMA, so the *data write buffer
- * must persist until the write completion event.
- *
- * @param ep_num	USB endpoint to write
- * @param len		number of bytes to write
- * @param data		pointer of data to write
- *
- * @return		bytes written
- */
-int usb_write_ep(uint32_t ep_num, int len, void *data)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-
-	if (GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA) {
-		CPRINTS("usb_write_ep ep%d: FAIL: tx already in progress!",
-			ep_num);
-		return 0;
-	}
-
-	/* We will send as many packets as necessary, including a final
-	 * packet of < USB_MAX_PACKET_SIZE (maybe zero length)
-	 */
-	ep->in_packets = (len + USB_MAX_PACKET_SIZE - 1) / USB_MAX_PACKET_SIZE;
-	ep->in_pending = len;
-	ep->in_data = data;
-
-	GR_USB_DIEPTSIZ(ep_num) = 0;
-
-	GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(ep->in_packets);
-	GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DIEPDMA(ep_num) = (uint32_t)(ep->in_data);
-
-	/* We could support longer multi-dma transfers here. */
-	ep->in_pending -= len;
-	ep->in_packets -= ep->in_packets;
-	ep->in_data += len;
-
-	/* We are ready to enable this endpoint to start transferring data. */
-	GR_USB_DIEPCTL(ep_num) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-	return len;
-}
-
-/* Tx/IN interrupt handler */
-void usb_epN_tx(uint32_t ep_num)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-	uint32_t dieptsiz = GR_USB_DIEPTSIZ(ep_num);
-
-	if (GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA) {
-		CPRINTS("usb_epN_tx ep%d: tx still active.", ep_num);
-		return;
-	}
-
-	/* clear the Tx/IN interrupts */
-	GR_USB_DIEPINT(ep_num) = 0xffffffff;
-
-	/*
-	 * Let's assume this is actually true.
-	 * We could support multi-dma transfers here.
-	 */
-	ep->in_packets = 0;
-	ep->in_pending = dieptsiz & GC_USB_DIEPTSIZ1_XFERSIZE_MASK;
-
-	if (ep->tx_deferred)
-		hook_call_deferred(ep->tx_deferred, 0);
-}
-
-/* Read a packet of data OUT from the host.
- *
- * This function uses DMA, so the *data write buffer
- * must persist until the read completion event.
- *
- * @param ep_num	USB endpoint to read
- * @param len		number of bytes to read
- * @param data		pointer of data to read
- *
- * @return		EC_SUCCESS on success
- */
-int usb_read_ep(uint32_t ep_num, int len, void *data)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-	int packets = (len + USB_MAX_PACKET_SIZE - 1) / USB_MAX_PACKET_SIZE;
-
-	ep->out_data = data;
-	ep->out_pending = 0;
-	ep->out_expected = len;
-
-	GR_USB_DOEPTSIZ(ep_num) = 0;
-	GR_USB_DOEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(packets);
-	GR_USB_DOEPTSIZ(ep_num) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DOEPDMA(ep_num) = (uint32_t)ep->out_data;
-
-	GR_USB_DOEPCTL(ep_num) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-	return EC_SUCCESS;
-}
-
-/* Rx/OUT endpoint interrupt handler */
-void usb_epN_rx(uint32_t ep_num)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-
-	/* Still receiving data. Let's wait. */
-	if (rx_ep_is_active(ep_num))
-		return;
-
-	/* Bytes received decrement DOEPTSIZ XFERSIZE */
-	if (GR_USB_DOEPINT(ep_num) & DOEPINT_XFERCOMPL) {
-		if (ep->out_expected > 0) {
-			ep->out_pending =
-				ep->out_expected -
-				(GR_USB_DOEPTSIZ(ep_num) &
-				 GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
-		} else {
-			CPRINTF("usb_ep%d_rx: unexpected RX DOEPTSIZ %08x\n",
-				ep_num, GR_USB_DOEPTSIZ(ep_num));
-			ep->out_pending = 0;
-		}
-		ep->out_expected = 0;
-		GR_USB_DOEPTSIZ(ep_num) = 0;
-	}
-
-	/* clear the RX/OUT interrupts */
-	GR_USB_DOEPINT(ep_num) = 0xffffffff;
-
-	if (ep->rx_deferred)
-		hook_call_deferred(ep->rx_deferred, 0);
-}
-
-/* Reset endpoint HW block. */
-void epN_reset(uint32_t ep_num)
-{
-	GR_USB_DOEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) |
-		DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK;
-	GR_USB_DIEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) |
-		DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK |
-		DXEPCTL_TXFNUM(ep_num);
-	GR_USB_DAINTMSK |= DAINT_INEP(ep_num) |
-			   DAINT_OUTEP(ep_num);
-}
-
-
-/******************************************************************************
- * Internal and EP0 functions.
- */
-
-
-static void flush_all_fifos(void)
-{
-	/* Flush all FIFOs according to Section 2.1.1.2 */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
-		| GRSTCTL_RXFFLSH;
-	while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
-		;
-}
-
-int send_in_packet(uint32_t ep_num)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[ep_num];
-	int len = MIN(USB_MAX_PACKET_SIZE, ep->in_pending);
-
-	if (ep->in_packets == 0) {
-		report_error(ep_num);
-		return -1;
-	}
-
-	GR_USB_DIEPTSIZ(ep_num) = 0;
-
-	GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(1);
-	GR_USB_DIEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DIEPDMA(0) = (uint32_t)ep->in_data;
-
-
-	/* We're sending this much. */
-	ep->in_pending -= len;
-	ep->in_packets -= 1;
-	ep->in_data += len;
-
-	/* We are ready to enable this endpoint to start transferring data. */
-	return len;
-}
-
-
-/* Load the EP0 IN FIFO buffer with some data (zero-length works too). Returns
- * len, or negative on error.
- */
-int initialize_in_transfer(const void *source, uint32_t len)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-
-#ifdef CONFIG_USB_DWC_FS
-	/* FS OTG port does not support DMA or external phy */
-	ASSERT(!(usb->dma_en));
-	ASSERT(usb->phy_type == USB_PHY_INTERNAL);
-	ASSERT(usb->speed == USB_SPEED_FS);
-	ASSERT(usb->irq == STM32_IRQ_OTG_FS);
-#else
-	/* HS OTG port requires an external phy to support HS */
-	ASSERT(!((usb->phy_type == USB_PHY_INTERNAL) &&
-		(usb->speed == USB_SPEED_HS)));
-	ASSERT(usb->irq == STM32_IRQ_OTG_HS);
-#endif
-
-	/* Copy the data into our FIFO buffer */
-	if (len >= IN_BUF_SIZE) {
-		report_error(len);
-		return -1;
-	}
-
-	/* Stage data in DMA buffer. */
-	memcpy(ep->in_databuffer, source, len);
-	ep->in_data = ep->in_databuffer;
-
-	/* We will send as many packets as necessary, including a final
-	 * packet of < USB_MAX_PACKET_SIZE (maybe zero length)
-	 */
-	ep->in_packets = (len + USB_MAX_PACKET_SIZE)/USB_MAX_PACKET_SIZE;
-	ep->in_pending = len;
-
-	send_in_packet(0);
-	return len;
-}
-
-/* Prepare the EP0 OUT FIFO buffer to accept some data. Returns len, or
- * negative on error.
- */
-int accept_out_fifo(uint32_t len)
-{
-	/* TODO: This is not yet implemented */
-	report_error(len);
-	return -1;
-}
-
-/* The next packet from the host should be a Setup packet. Get ready for it. */
-static void expect_setup_packet(void)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-
-	what_am_i_doing = WAITING_FOR_SETUP_PACKET;
-	ep->out_data = ep->out_databuffer;
-
-	/* We don't care about IN packets right now, only OUT. */
-	GR_USB_DAINTMSK |= DAINT_OUTEP(0);
-	GR_USB_DAINTMSK &= ~DAINT_INEP(0);
-
-	GR_USB_DOEPTSIZ(0) = 0;
-	GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_PKTCNT(1);
-	GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(0x18);
-	GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_SUPCNT(1);
-	GR_USB_DOEPCTL(0) = DXEPCTL_USBACTEP | DXEPCTL_EPENA;
-	GR_USB_DOEPDMA(0) = (uint32_t)ep->out_data;
-}
-
-/* We're complaining about something by stalling both IN and OUT packets,
- * but a SETUP packet will get through anyway, so prepare for it.
- */
-static void stall_both_fifos(void)
-{
-	what_am_i_doing = WAITING_FOR_SETUP_PACKET;
-	/* We don't care about IN packets right now, only OUT. */
-	GR_USB_DAINTMSK |= DAINT_OUTEP(0);
-	GR_USB_DAINTMSK &= ~DAINT_INEP(0);
-
-	GR_USB_DOEPCTL(0) |= DXEPCTL_STALL;
-	GR_USB_DIEPCTL(0) |= DXEPCTL_STALL;
-	expect_setup_packet();
-}
-
-/* The TX FIFO buffer is loaded. Start the Data phase. */
-static void expect_data_phase_in(enum table_case tc)
-{
-	what_am_i_doing = DATA_STAGE_IN;
-
-	/* Send the reply (data phase in) */
-	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP |
-					DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA;
-
-	/* We'll receive an empty packet back as a ack, I guess. */
-	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DOEPCTL(0) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DOEPCTL(0) |= DXEPCTL_EPENA;
-
-	/* Get an interrupt when either IN or OUT arrives */
-	GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0));
-
-}
-
-static void expect_data_phase_out(enum table_case tc)
-{
-	/* TODO: This is not yet supported */
-	report_error(tc);
-	expect_setup_packet();
-}
-
-/* No Data phase, just Status phase (which is IN, since Setup is OUT) */
-static void expect_status_phase_in(enum table_case tc)
-{
-	what_am_i_doing = NO_DATA_STAGE;
-
-	/* Expect a zero-length IN for the Status phase */
-	(void) initialize_in_transfer(0, 0);
-
-	/* Blindly following instructions here, too. */
-	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP
-			| DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA;
-
-	/* Get an interrupt when either IN or OUT arrives */
-	GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0));
-}
-
-/* Handle a Setup packet that expects us to send back data in reply. Return the
- * length of the data we're returning, or negative to indicate an error.
- */
-static int handle_setup_with_in_stage(enum table_case tc,
-				      struct usb_setup_packet *req)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-
-	const void *data = 0;
-	uint32_t len = 0;
-	int ugly_hack = 0;
-	static const uint16_t zero;		/* == 0 */
-
-	switch (req->bRequest) {
-	case USB_REQ_GET_DESCRIPTOR: {
-		uint8_t type = req->wValue >> 8;
-		uint8_t idx = req->wValue & 0xff;
-
-		switch (type) {
-		case USB_DT_DEVICE:
-			data = &dev_desc;
-			len = sizeof(dev_desc);
-			break;
-		case USB_DT_CONFIGURATION:
-			data = __usb_desc;
-			len = USB_DESC_SIZE;
-			ugly_hack = 1;		/* see below */
-			break;
-#ifdef CONFIG_USB_BOS
-		case USB_DT_BOS:
-			data = bos_ctx.descp;
-			len = bos_ctx.size;
-			break;
-#endif
-		case USB_DT_STRING:
-			if (idx >= USB_STR_COUNT)
-				return -1;
-#ifdef CONFIG_USB_SERIALNO
-			if (idx == USB_STR_SERIALNO)
-				data = (uint8_t *)usb_serialno_desc;
-			else
-#endif
-				data = usb_strings[idx];
-			len = *(uint8_t *)data;
-			break;
-		case USB_DT_DEVICE_QUALIFIER:
-			/* We're not high speed */
-			return -1;
-		case USB_DT_DEBUG:
-			/* Not supported */
-			return -1;
-		default:
-			report_error(type);
-			return -1;
-		}
-		break;
-	}
-	case USB_REQ_GET_STATUS: {
-		/* TODO: Device Status: Remote Wakeup? Self Powered? */
-		data = &zero;
-		len = sizeof(zero);
-		break;
-	}
-	case USB_REQ_GET_CONFIGURATION:
-		data = &configuration_value;
-		len = sizeof(configuration_value);
-		break;
-
-	case USB_REQ_SYNCH_FRAME:
-		/* Unimplemented */
-		return -1;
-
-	default:
-		report_error(req->bRequest);
-		return -1;
-	}
-
-	/* Don't send back more than we were asked for. */
-	len = MIN(req->wLength, len);
-
-	/* Prepare the TX FIFO. If we haven't preallocated enough room in the
-	 * TX FIFO for the largest reply, we'll have to stall. This is a bug in
-	 * our code, but detecting it easily at compile time is related to the
-	 * ugly_hack directly below.
-	 */
-	if (initialize_in_transfer(data, len) < 0)
-		return -1;
-
-	if (ugly_hack) {
-		/*
-		 * TODO: Somebody figure out how to fix this, please.
-		 *
-		 * The USB configuration descriptor request is unique in that
-		 * it not only returns the configuration descriptor, but also
-		 * all the interface descriptors and all their endpoint
-		 * descriptors as one enormous blob. We've set up some macros
-		 * so we can declare and implement separate interfaces in
-		 * separate files just by compiling them, and all the relevant
-		 * descriptors are sorted and bundled up by the linker. But the
-		 * total length of the entire blob needs to appear in the first
-		 * configuration descriptor struct and because we don't know
-		 * that value until after linking, it can't be initialized as a
-		 * constant. So we have to compute it at run-time and shove it
-		 * in here, which also means that we have to copy the whole
-		 * blob into our TX FIFO buffer so that it's mutable. Otherwise
-		 * we could just point at it (or pretty much any other constant
-		 * struct that we wanted to send to the host). Bah.
-		 */
-		struct usb_config_descriptor *cfg =
-			(struct usb_config_descriptor *)ep->in_databuffer;
-		/* set the real descriptor size */
-		cfg->wTotalLength = USB_DESC_SIZE;
-	}
-
-	return len;
-}
-
-/* Handle a Setup that comes with additional data for us. */
-static int handle_setup_with_out_stage(enum table_case tc,
-					struct usb_setup_packet *req)
-{
-	/* TODO: We don't support any of these. We should. */
-	report_error(-1);
-	return -1;
-}
-
-/* Some Setup packets don't have a data stage at all. */
-static int handle_setup_with_no_data_stage(enum table_case tc,
-					   struct usb_setup_packet *req)
-{
-	uint8_t set_addr;
-
-	switch (req->bRequest) {
-	case USB_REQ_SET_ADDRESS:
-		/*
-		 * Set the address after the IN packet handshake.
-		 *
-		 * From the USB 2.0 spec, section 9.4.6:
-		 *
-		 * As noted elsewhere, requests actually may result in
-		 * up to three stages. In the first stage, the Setup
-		 * packet is sent to the device. In the optional second
-		 * stage, data is transferred between the host and the
-		 * device. In the final stage, status is transferred
-		 * between the host and the device. The direction of
-		 * data and status transfer depends on whether the host
-		 * is sending data to the device or the device is
-		 * sending data to the host. The Status stage transfer
-		 * is always in the opposite direction of the Data
-		 * stage. If there is no Data stage, the Status stage
-		 * is from the device to the host.
-		 *
-		 * Stages after the initial Setup packet assume the
-		 * same device address as the Setup packet. The USB
-		 * device does not change its device address until
-		 * after the Status stage of this request is completed
-		 * successfully. Note that this is a difference between
-		 * this request and all other requests. For all other
-		 * requests, the operation indicated must be completed
-		 * before the Status stage
-		 */
-		set_addr = req->wValue & 0xff;
-		/*
-		 * NOTE: Now that we've said that, we don't do it. The
-		 * hardware for this SoC knows that an IN packet will
-		 * be following the SET ADDRESS, so it waits until it
-		 * sees that happen before the address change takes
-		 * effect. If we wait until after the IN packet to
-		 * change the register, the hardware gets confused and
-		 * doesn't respond to anything.
-		 */
-		GWRITE_FIELD(USB, DCFG, DEVADDR, set_addr);
-		CPRINTS("SETAD 0x%02x (%d)", set_addr, set_addr);
-		device_state = DS_ADDRESS;
-		break;
-
-	case USB_REQ_SET_CONFIGURATION:
-		switch (req->wValue) {
-		case 0:
-			configuration_value = req->wValue;
-			device_state = DS_ADDRESS;
-			break;
-		case 1:	    /* Caution: Only one config descriptor TODAY */
-			/* TODO: All endpoints set to DATA0 toggle state */
-			configuration_value = req->wValue;
-			device_state = DS_CONFIGURED;
-			break;
-		default:
-			/* Nope. That's a paddlin. */
-			report_error(-1);
-			return -1;
-		}
-		break;
-
-	case USB_REQ_CLEAR_FEATURE:
-	case USB_REQ_SET_FEATURE:
-		/* TODO: Handle DEVICE_REMOTE_WAKEUP, ENDPOINT_HALT? */
-		break;
-
-	default:
-		/* Anything else is unsupported */
-		report_error(-1);
-		return -1;
-	}
-
-	/* No data to transfer, go straight to the Status phase. */
-	return 0;
-}
-
-/* Dispatch an incoming Setup packet according to its type */
-static void handle_setup(enum table_case tc)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-	struct usb_setup_packet *req =
-		(struct usb_setup_packet *)ep->out_databuffer;
-	int data_phase_in = req->bmRequestType & USB_DIR_IN;
-	int data_phase_out = !data_phase_in && req->wLength;
-	int bytes = -1;				/* default is to stall */
-
-	if (0 == (req->bmRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))) {
-		/* Standard Device requests */
-		if (data_phase_in)
-			bytes = handle_setup_with_in_stage(tc, req);
-		else if (data_phase_out)
-			bytes = handle_setup_with_out_stage(tc, req);
-		else
-			bytes = handle_setup_with_no_data_stage(tc, req);
-	} else if (USB_RECIP_INTERFACE ==
-		   (req->bmRequestType & USB_RECIP_MASK)) {
-		/* Interface-specific requests */
-		uint8_t iface = req->wIndex & 0xff;
-
-		if (iface < USB_IFACE_COUNT)
-			bytes = usb_iface_request[iface](req);
-	} else {
-		/* Something we need to add support for? */
-		report_error(-1);
-	}
-
-	/* We say "no" to unsupported and intentionally unhandled requests by
-	 * stalling the Data and/or Status stage.
-	 */
-	if (bytes < 0) {
-		/* Stall both IN and OUT. SETUP will come through anyway. */
-		stall_both_fifos();
-	} else {
-		if (data_phase_in)
-			expect_data_phase_in(tc);
-		else if (data_phase_out)
-			expect_data_phase_out(tc);
-		else
-			expect_status_phase_in(tc);
-	}
-}
-
-/* This handles both IN and OUT interrupts for EP0 */
-static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-	uint32_t doepint, diepint;
-	enum table_case tc;
-	int out_complete, out_setup, in_complete;
-
-	/* Determine the interrupt cause and clear the bits quickly, but only
-	 * if they really apply. I don't think they're trustworthy if we didn't
-	 * actually get an interrupt.
-	 */
-	doepint = GR_USB_DOEPINT(0) & GR_USB_DOEPMSK;
-	if (intr_on_out)
-		GR_USB_DOEPINT(0) = doepint;
-	diepint = GR_USB_DIEPINT(0) & GR_USB_DIEPMSK;
-	if (intr_on_in)
-		GR_USB_DIEPINT(0) = diepint;
-
-	out_complete = doepint & DOEPINT_XFERCOMPL;
-	out_setup = doepint & DOEPINT_SETUP;
-	in_complete = diepint & DIEPINT_XFERCOMPL;
-
-	/* Decode the situation according to Table 10-7 */
-	tc = decode_table_10_7(doepint);
-
-	switch (what_am_i_doing) {
-	case WAITING_FOR_SETUP_PACKET:
-		if (out_setup)
-			handle_setup(tc);
-		else
-			report_error(-1);
-		break;
-
-	case DATA_STAGE_IN:
-		if (intr_on_in && in_complete) {
-			/* A packet is sent. Should we send another? */
-			if (ep->in_packets > 0) {
-				/* Send another packet. */
-				send_in_packet(0);
-				expect_data_phase_in(tc);
-			}
-		}
-
-		/* But we should ignore the OUT endpoint if we didn't actually
-		 * get an OUT interrupt.
-		 */
-		if (!intr_on_out)
-			break;
-
-		if (out_setup) {
-			/* The first IN packet has been seen. Keep going. */
-			break;
-		}
-		if (out_complete) {
-			/* We've handled the Status phase. All done. */
-			expect_setup_packet();
-			break;
-		}
-
-		/* Anything else should be ignorable. Right? */
-		break;
-
-	case NO_DATA_STAGE:
-		if (intr_on_in && in_complete) {
-			/* We are not expecting an empty packet in
-			 * return for our empty packet.
-			 */
-			expect_setup_packet();
-		}
-
-		/* Done unless we got an OUT interrupt */
-		if (!intr_on_out)
-			break;
-
-		if (out_setup) {
-			report_error(-1);
-			break;
-		}
-
-		/* Anything else means get ready for a Setup packet */
-		report_error(-1);
-		expect_setup_packet();
-		break;
-	}
-}
-
-/****************************************************************************/
-/* USB device initialization and shutdown routines */
-
-/*
- * DATA FIFO Setup. There is an internal SPRAM used to buffer the IN/OUT
- * packets and track related state without hammering the AHB and system RAM
- * during USB transactions. We have to specify where and how much of that SPRAM
- * to use for what.
- *
- * See Programmer's Guide chapter 2, "Calculating FIFO Size".
- * We're using Dedicated TxFIFO Operation, without enabling thresholding.
- *
- * Section 2.1.1.2, page 30: RXFIFO size is the same as for Shared FIFO, which
- * is Section 2.1.1.1, page 28. This is also the same as Method 2 on page 45.
- *
- * We support up to 3 control EPs, no periodic IN EPs, up to 16 TX EPs. Max
- * data packet size is 64 bytes. Total SPRAM available is 1024 slots.
- */
-#define MAX_CONTROL_EPS   3
-#define MAX_NORMAL_EPS    16
-#define FIFO_RAM_DEPTH    1024
-/*
- * Device RX FIFO size is thus:
- *   (4 * 3 + 6) + 2 * ((64 / 4) + 1) + (2 * 16) + 1 == 85
- */
-#define RXFIFO_SIZE  ((4 * MAX_CONTROL_EPS + 6) + \
-		      2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \
-		      (2 * MAX_NORMAL_EPS) + 1)
-/*
- * Device TX FIFO size is 2 * (64 / 4) == 32 for each IN EP (Page 46).
- */
-#define TXFIFO_SIZE  (2 * (USB_MAX_PACKET_SIZE / 4))
-/*
- * We need 4 slots per endpoint direction for endpoint status stuff (Table 2-1,
- * unconfigurable).
- */
-#define EP_STATUS_SIZE (4 * MAX_NORMAL_EPS * 2)
-/*
- * Make sure all that fits.
- */
-BUILD_ASSERT(RXFIFO_SIZE + TXFIFO_SIZE * MAX_NORMAL_EPS + EP_STATUS_SIZE <
-	     FIFO_RAM_DEPTH);
-
-
-/* Now put those constants into the correct registers */
-static void setup_data_fifos(void)
-{
-	int i;
-
-	/* Programmer's Guide, p31 */
-	GR_USB_GRXFSIZ = RXFIFO_SIZE;			      /* RXFIFO */
-	GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */
-
-	/* TXFIFO 1..15 */
-	for (i = 1; i < MAX_NORMAL_EPS; i++)
-		GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) |
-				     (RXFIFO_SIZE + i * TXFIFO_SIZE));
-
-	/*
-	 * TODO: The Programmer's Guide is confusing about when or whether to
-	 * flush the FIFOs. Section 2.1.1.2 (p31) just says to flush. Section
-	 * 2.2.2 (p55) says to stop all the FIFOs first, then flush. Section
-	 * 7.5.4 (p162) says that flushing the RXFIFO at reset is not
-	 * recommended at all.
-	 *
-	 * I'm also unclear on whether or not the individual EPs are expected
-	 * to be disabled already (DIEPCTLn/DOEPCTLn.EPENA == 0), and if so,
-	 * whether by firmware or hardware.
-	 */
-
-	/* Flush all FIFOs according to Section 2.1.1.2 */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
-		| GRSTCTL_RXFFLSH;
-	while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
-		;				/* TODO: timeout 100ms */
-}
-
-static void usb_init_endpoints(void)
-{
-	int ep;
-
-	/* Prepare to receive packets on EP0 */
-	expect_setup_packet();
-
-	/* Reset the other endpoints */
-	for (ep = 1; ep < USB_EP_COUNT; ep++)
-		usb_ep_event[ep](USB_EVENT_RESET);
-}
-
-static void usb_reset(void)
-{
-	/* Clear our internal state */
-	device_state = DS_DEFAULT;
-	configuration_value = 0;
-
-	/* Clear the device address */
-	GWRITE_FIELD(USB, DCFG, DEVADDR, 0);
-
-	/* Reinitialize all the endpoints */
-	usb_init_endpoints();
-}
-
-static void usb_resetdet(void)
-{
-	/* TODO: Same as normal reset, right? I think we only get this if we're
-	 * suspended (sleeping) and the host resets us. Try it and see.
-	 */
-	usb_reset();
-}
-
-static void usb_enumdone(void)
-{
-	/* We can change to HS here. We will not go to HS today */
-	GR_USB_DCTL |= DCTL_CGOUTNAK;
-}
-
-
-void usb_interrupt(void)
-{
-	uint32_t status = GR_USB_GINTSTS & GR_USB_GINTMSK;
-	uint32_t oepint = status & GINTSTS(OEPINT);
-	uint32_t iepint = status & GINTSTS(IEPINT);
-	int ep;
-
-	if (status & GINTSTS(ENUMDONE))
-		usb_enumdone();
-
-	if (status & GINTSTS(RESETDET))
-		usb_resetdet();
-
-	if (status & GINTSTS(USBRST))
-		usb_reset();
-
-	/* Endpoint interrupts */
-	if (oepint || iepint) {
-		/* Note: It seems that the DAINT bits are only trustworthy for
-		 * identifying interrupts when selected by the corresponding
-		 * OEPINT and IEPINT bits from GINTSTS.
-		 */
-		uint32_t daint = GR_USB_DAINT;
-
-		/* EP0 has a combined IN/OUT handler. Only call it once, but
-		 * let it know which direction(s) had an interrupt.
-		 */
-		if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) {
-			uint32_t intr_on_out = (oepint &&
-						(daint & DAINT_OUTEP(0)));
-			uint32_t intr_on_in = (iepint &&
-						(daint & DAINT_INEP(0)));
-			ep0_interrupt(intr_on_out, intr_on_in);
-		}
-
-		/* Invoke the unidirectional IN and OUT functions for the other
-		 * endpoints. Each handler must clear their own bits in
-		 * DIEPINTn/DOEPINTn.
-		 */
-		for (ep = 1; ep < USB_EP_COUNT; ep++) {
-			if (oepint && (daint & DAINT_OUTEP(ep)))
-				usb_ep_rx[ep]();
-			if (iepint && (daint & DAINT_INEP(ep)))
-				usb_ep_tx[ep]();
-		}
-	}
-
-	GR_USB_GINTSTS = status;
-}
-DECLARE_IRQ(STM32_IRQ_OTG_FS, usb_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_OTG_HS, usb_interrupt, 1);
-
-static void usb_softreset(void)
-{
-	int timeout;
-
-	CPRINTS("%s", __func__);
-
-	/* Wait for bus idle */
-	timeout = 10000;
-	while (!(GR_USB_GRSTCTL & GRSTCTL_AHBIDLE) && timeout-- > 0)
-		;
-
-	/* Reset and wait for clear */
-	GR_USB_GRSTCTL = GRSTCTL_CSFTRST;
-	timeout = 10000;
-	while ((GR_USB_GRSTCTL & GRSTCTL_CSFTRST) && timeout-- > 0)
-		;
-	if (GR_USB_GRSTCTL & GRSTCTL_CSFTRST) {
-		CPRINTF("USB: reset failed\n");
-		return;
-	}
-
-	/* Some more idle? */
-	timeout = 10000;
-	while (!(GR_USB_GRSTCTL & GRSTCTL_AHBIDLE) && timeout-- > 0)
-		;
-
-	if (!timeout) {
-		CPRINTF("USB: reset timeout\n");
-		return;
-	}
-	/* TODO: Wait 3 PHY clocks before returning */
-}
-
-void usb_connect(void)
-{
-	GR_USB_DCTL &= ~DCTL_SFTDISCON;
-}
-
-void usb_disconnect(void)
-{
-	GR_USB_DCTL |= DCTL_SFTDISCON;
-
-	device_state = DS_DEFAULT;
-	configuration_value = 0;
-}
-
-void usb_reset_init_phy(void)
-{
-	struct dwc_usb *usb = &usb_ctl;
-
-	if (usb->phy_type == USB_PHY_ULPI) {
-		GR_USB_GCCFG &= ~GCCFG_PWRDWN;
-		GR_USB_GUSBCFG &= ~(GUSBCFG_TSDPS |
-			GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
-		GR_USB_GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
-		/* No suspend */
-		GR_USB_GUSBCFG |= GUSBCFG_ULPICSM | GUSBCFG_ULPIAR;
-
-		usb_softreset();
-	} else {
-		GR_USB_GUSBCFG |= GUSBCFG_PHYSEL;
-		usb_softreset();
-		GR_USB_GCCFG |= GCCFG_PWRDWN;
-	}
-}
-
-void usb_init(void)
-{
-	int i;
-	struct dwc_usb *usb = &usb_ctl;
-
-	CPRINTS("%s", __func__);
-
-#ifdef CONFIG_USB_SERIALNO
-	usb_load_serial();
-#endif
-
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	/* Enable clocks */
-	clock_enable_module(MODULE_USB, 0);
-	clock_enable_module(MODULE_USB, 1);
-
-	/* TODO(crbug.com/496888): set up pinmux */
-	gpio_config_module(MODULE_USB, 1);
-
-	/* Make sure interrupts are disabled */
-	GR_USB_GINTMSK = 0;
-	GR_USB_DAINTMSK = 0;
-	GR_USB_DIEPMSK = 0;
-	GR_USB_DOEPMSK = 0;
-
-	/* Full-Speed Serial PHY */
-	usb_reset_init_phy();
-
-	/* Global + DMA configuration */
-	GR_USB_GAHBCFG = GAHBCFG_GLB_INTR_EN;
-	GR_USB_GAHBCFG |= GAHBCFG_HBSTLEN_INCR4;
-	if (usb->dma_en)
-		GR_USB_GAHBCFG |= GAHBCFG_DMA_EN;
-
-	/* Device only, no SRP */
-	GR_USB_GUSBCFG |= GUSBCFG_FDMOD;
-	GR_USB_GUSBCFG |= GUSBCFG_SRPCAP | GUSBCFG_HNPCAP;
-
-	GR_USB_GCCFG &= ~GCCFG_VBDEN;
-	GR_USB_GOTGCTL |= GOTGCTL_BVALOEN;
-	GR_USB_GOTGCTL |= GOTGCTL_BVALOVAL;
-
-	GR_USB_PCGCCTL = 0;
-
-	if (usb->phy_type == USB_PHY_ULPI) {
-		/* TODO(nsanders): add HS support like so.
-		 * GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-		 * | DCFG_DEVSPD_HSULPI;
-		 */
-		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-			| DCFG_DEVSPD_FSULPI;
-	} else {
-		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-			| DCFG_DEVSPD_FS48;
-	}
-
-	GR_USB_DCFG |= DCFG_NZLSOHSK;
-
-	flush_all_fifos();
-
-	/* Clear pending interrupts again */
-	GR_USB_GINTMSK = 0;
-	GR_USB_DIEPMSK = 0;
-	GR_USB_DOEPMSK = 0;
-	GR_USB_DAINT = 0xffffffff;
-	GR_USB_DAINTMSK = 0;
-
-	/* TODO: What about the AHB Burst Length Field? It's 0 now. */
-	GR_USB_GAHBCFG |= GAHBCFG_TXFELVL | GAHBCFG_PTXFELVL;
-
-	/* Device only, no SRP */
-	GR_USB_GUSBCFG |= GUSBCFG_FDMOD
-		| GUSBCFG_TOUTCAL(7)
-		/* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */
-		| GUSBCFG_USBTRDTIM(14);
-
-	/* Be in disconnected state until we are ready */
-	usb_disconnect();
-
-	/* If we've restored a nonzero device address, update our state. */
-	if (GR_USB_DCFG & GC_USB_DCFG_DEVADDR_MASK) {
-		/* Caution: We only have one config TODAY, so there's no real
-		 * difference between DS_CONFIGURED and DS_ADDRESS.
-		 */
-		device_state = DS_CONFIGURED;
-		configuration_value = 1;
-	} else {
-		device_state = DS_DEFAULT;
-		configuration_value = 0;
-	}
-
-	/* Now that DCFG.DesDMA is accurate, prepare the FIFOs */
-	setup_data_fifos();
-
-	usb_init_endpoints();
-
-	/* Clear any pending interrupts */
-	for (i = 0; i < 16; i++) {
-		GR_USB_DIEPINT(i) = 0xffffffff;
-		GR_USB_DIEPTSIZ(i) = 0;
-		GR_USB_DOEPINT(i) = 0xffffffff;
-		GR_USB_DOEPTSIZ(i) = 0;
-	}
-
-	if (usb->dma_en) {
-		GR_USB_DTHRCTL = DTHRCTL_TXTHRLEN_6 | DTHRCTL_RXTHRLEN_6;
-		GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN
-			| DTHRCTL_NONISOTHREN;
-		i = GR_USB_DTHRCTL;
-	}
-
-	GR_USB_GINTSTS = 0xFFFFFFFF;
-
-	GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL
-		| GAHBCFG_PTXFELVL;
-
-	if (!(usb->dma_en))
-		GR_USB_GINTMSK |= GINTMSK(RXFLVL);
-
-	/* Unmask some endpoint interrupt causes */
-	GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK;
-	GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK |
-		DOEPMSK_SETUPMSK;
-
-	/* Enable interrupt handlers */
-	task_enable_irq(usb->irq);
-
-	/* Allow USB interrupts to come in */
-	GR_USB_GINTMSK |=
-		/* NAK bits that must be cleared by the DCTL register */
-		GINTMSK(GOUTNAKEFF) | GINTMSK(GINNAKEFF) |
-		/* Initialization events */
-		GINTMSK(USBRST) | GINTMSK(ENUMDONE) |
-		/* Reset detected while suspended. Need to wake up. */
-		GINTMSK(RESETDET) |		/* TODO: Do we need this? */
-		/* Idle, Suspend detected. Should go to sleep. */
-		GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP);
-
-	GR_USB_GINTMSK |=
-		/* Endpoint activity, cleared by the DOEPINT/DIEPINT regs */
-		GINTMSK(OEPINT) | GINTMSK(IEPINT);
-
-	/* Device registers have been setup */
-	GR_USB_DCTL |= DCTL_PWRONPRGDONE;
-	udelay(10);
-	GR_USB_DCTL &= ~DCTL_PWRONPRGDONE;
-
-	/* Clear global NAKs */
-	GR_USB_DCTL |= DCTL_CGOUTNAK | DCTL_CGNPINNAK;
-
-#ifndef CONFIG_USB_INHIBIT_CONNECT
-	/* Indicate our presence to the USB host */
-	usb_connect();
-#endif
-}
-#ifndef CONFIG_USB_INHIBIT_INIT
-DECLARE_HOOK(HOOK_INIT, usb_init, HOOK_PRIO_DEFAULT);
-#endif
-
-void usb_release(void)
-{
-	struct dwc_usb *usb = &usb_ctl;
-
-	/* signal disconnect to host */
-	usb_disconnect();
-
-	/* disable interrupt handlers */
-	task_disable_irq(usb->irq);
-
-	/* disable clocks */
-	clock_enable_module(MODULE_USB, 0);
-	/* TODO: pin-mux */
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
-
-/* Print USB info and stats */
-static void usb_info(void)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	int i;
-
-	CPRINTF("USB settings: %s%s%s\n",
-		usb->speed == USB_SPEED_FS ? "FS " : "HS ",
-		usb->phy_type == USB_PHY_INTERNAL ? "Internal Phy " : "ULPI ",
-		usb->dma_en ? "DMA " : "");
-
-	for (i = 0; i < USB_EP_COUNT; i++) {
-		CPRINTF("Endpoint %d activity: %s%s\n", i,
-			rx_ep_is_active(i) ? "RX " : "",
-			tx_ep_is_ready(i) ? "" : "TX ");
-	}
-}
-
-static int command_usb(int argc, char **argv)
-{
-	if (argc > 1) {
-		if (!strcasecmp("on", argv[1]))
-			usb_init();
-		else if (!strcasecmp("off", argv[1]))
-			usb_release();
-		else if (!strcasecmp("info", argv[1]))
-			usb_info();
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_PARAM1;
-}
-DECLARE_CONSOLE_COMMAND(usb, command_usb,
-			"[on|off|info]",
-			"Get/set the USB connection state and PHY selection");
-
-#ifdef CONFIG_USB_SERIALNO
-/* This will be subbed into USB_STR_SERIALNO. */
-struct usb_string_desc *usb_serialno_desc =
-	USB_WR_STRING_DESC(DEFAULT_SERIALNO);
-
-/* Update serial number */
-static int usb_set_serial(const char *serialno)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	int i;
-
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	/* Convert into unicode usb string desc. */
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++) {
-		sd->_data[i] = serialno[i];
-		if (serialno[i] == 0)
-			break;
-	}
-	/* Count wchars (w/o null terminator) plus size & type bytes. */
-	sd->_len = (i * 2) + 2;
-	sd->_type = USB_DT_STRING;
-
-	return EC_SUCCESS;
-}
-
-/* Retrieve serial number from pstate flash. */
-static int usb_load_serial(void)
-{
-	const char *serialno;
-	int rv;
-
-	serialno = board_read_serial();
-	if (!serialno)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = usb_set_serial(serialno);
-	return rv;
-}
-
-/* Save serial number into pstate region. */
-static int usb_save_serial(const char *serialno)
-{
-	int rv;
-
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	/* Save this new serial number to flash. */
-	rv = board_write_serial(serialno);
-	if (rv)
-		return rv;
-
-	/* Load this new serial number to memory. */
-	rv = usb_load_serial();
-	return rv;
-}
-
-static int command_serialno(int argc, char **argv)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	char buf[CONFIG_SERIALNO_LEN];
-	int rv = EC_SUCCESS;
-	int i;
-
-	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
-			ccprintf("Saving serial number\n");
-			rv = usb_save_serial(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
-			ccprintf("Loading serial number\n");
-			rv = usb_load_serial();
-		} else
-			return EC_ERROR_INVAL;
-	}
-
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++)
-		buf[i] = sd->_data[i];
-	ccprintf("Serial number: %s\n", buf);
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(serialno, command_serialno,
-	"load/set [value]",
-	"Read and write USB serial number");
-#endif  /* CONFIG_USB_SERIALNO */
diff --git a/chip/stm32/usb_dwc_console.c b/chip/stm32/usb_dwc_console.c
deleted file mode 100644
index 0d1340fb83..0000000000
--- a/chip/stm32/usb_dwc_console.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "link_defs.h"
-#include "printf.h"
-#include "queue.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
-
-static int last_tx_ok = 1;
-
-static int is_reset;
-static int is_enabled = 1;
-static int is_readonly;
-
-/* USB-Serial descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = {
-	.bLength		= USB_DT_INTERFACE_SIZE,
-	.bDescriptorType	= USB_DT_INTERFACE,
-	.bInterfaceNumber	= USB_IFACE_CONSOLE,
-	.bAlternateSetting	= 0,
-	.bNumEndpoints		= 2,
-	.bInterfaceClass	= USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass	= USB_SUBCLASS_GOOGLE_SERIAL,
-	.bInterfaceProtocol	= USB_PROTOCOL_GOOGLE_SERIAL,
-	.iInterface		= USB_STR_CONSOLE_NAME,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = {
-	.bLength		= USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType	= USB_DT_ENDPOINT,
-	.bEndpointAddress	= 0x80 | USB_EP_CONSOLE,
-	.bmAttributes		= 0x02 /* Bulk IN */,
-	.wMaxPacketSize		= USB_MAX_PACKET_SIZE,
-	.bInterval		 = 10,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = {
-	.bLength	    = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk OUT */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval	  = 0
-};
-
-static uint8_t ep_buf_tx[USB_MAX_PACKET_SIZE];
-static uint8_t ep_buf_rx[USB_MAX_PACKET_SIZE];
-
-static struct queue const tx_q = QUEUE_NULL(256, uint8_t);
-static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t);
-
-
-struct dwc_usb_ep ep_console_ctl = {
-	.max_packet = USB_MAX_PACKET_SIZE,
-	.tx_fifo = USB_EP_CONSOLE,
-	.out_pending = 0,
-	.out_data = 0,
-	.out_databuffer = ep_buf_tx,
-	.out_databuffer_max = sizeof(ep_buf_tx),
-	.in_packets = 0,
-	.in_pending = 0,
-	.in_data = 0,
-	.in_databuffer = ep_buf_rx,
-	.in_databuffer_max = sizeof(ep_buf_rx),
-};
-
-
-
-/* Let the USB HW IN-to-host FIFO transmit some bytes */
-static void usb_enable_tx(int len)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	ep->in_data = ep->in_databuffer;
-	ep->in_packets = 1;
-	ep->in_pending = len;
-
-	GR_USB_DIEPTSIZ(USB_EP_CONSOLE) = 0;
-
-	GR_USB_DIEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_PKTCNT(1);
-	GR_USB_DIEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DIEPDMA(USB_EP_CONSOLE) = (uint32_t)ep->in_data;
-
-	GR_USB_DIEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-/* Let the USB HW OUT-from-host FIFO receive some bytes */
-static void usb_enable_rx(int len)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	ep->out_data = ep->out_databuffer;
-	ep->out_pending = 0;
-
-	GR_USB_DOEPTSIZ(USB_EP_CONSOLE) = 0;
-	GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_PKTCNT(1);
-	GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DOEPDMA(USB_EP_CONSOLE) = (uint32_t)ep->out_data;
-
-	GR_USB_DOEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-/* True if the HW Rx/OUT FIFO has bytes for us. */
-static inline int rx_fifo_is_ready(void)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	return ep->out_pending;
-}
-
-/*
- * This function tries to shove new bytes from the USB host into the queue for
- * consumption elsewhere. It is invoked either by a HW interrupt (telling us we
- * have new bytes from the USB host), or by whoever is reading bytes out of the
- * other end of the queue (telling us that there's now more room in the queue
- * if we still have bytes to shove in there).
- */
-char buffer[65];
-static void rx_fifo_handler(void)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	int rx_in_fifo;
-	size_t added;
-
-	if (!rx_fifo_is_ready())
-		return;
-
-	rx_in_fifo = ep->out_pending;
-	added = QUEUE_ADD_UNITS(&rx_q, ep->out_databuffer, rx_in_fifo);
-
-	if (added != rx_in_fifo)
-		CPRINTF("DROP CONSOLE: %d/%d process\n", added, rx_in_fifo);
-
-	/* wake-up the console task */
-	console_has_input();
-
-	usb_enable_rx(USB_MAX_PACKET_SIZE);
-}
-DECLARE_DEFERRED(rx_fifo_handler);
-
-/* Rx/OUT interrupt handler */
-static void con_ep_rx(void)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	if (GR_USB_DOEPCTL(USB_EP_CONSOLE) & DXEPCTL_EPENA)
-		return;
-
-	/* Bytes received decrement DOEPTSIZ XFERSIZE */
-	if (GR_USB_DOEPINT(USB_EP_CONSOLE) & DOEPINT_XFERCOMPL) {
-		ep->out_pending =
-			ep->max_packet -
-			(GR_USB_DOEPTSIZ(USB_EP_CONSOLE) &
-			 GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
-	}
-
-	/* Wake up the Rx FIFO handler */
-	hook_call_deferred(&rx_fifo_handler_data, 0);
-
-	/* clear the RX/OUT interrupts */
-	GR_USB_DOEPINT(USB_EP_CONSOLE) = 0xffffffff;
-}
-
-/* True if the Tx/IN FIFO can take some bytes from us. */
-static inline int tx_fifo_is_ready(void)
-{
-	return !(GR_USB_DIEPCTL(USB_EP_CONSOLE) & DXEPCTL_EPENA);
-}
-
-/* Try to send some bytes to the host */
-static void tx_fifo_handler(void)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-	size_t count;
-
-	if (!is_reset)
-		return;
-
-	/* If the HW FIFO isn't ready, then we can't do anything right now. */
-	if (!tx_fifo_is_ready())
-		return;
-
-	count = QUEUE_REMOVE_UNITS(&tx_q,
-		ep->in_databuffer, USB_MAX_PACKET_SIZE);
-	if (count)
-		usb_enable_tx(count);
-}
-DECLARE_DEFERRED(tx_fifo_handler);
-
-static void handle_output(void)
-{
-	/* Wake up the Tx FIFO handler */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-}
-
-/* Tx/IN interrupt handler */
-static void con_ep_tx(void)
-{
-	/* Wake up the Tx FIFO handler */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-
-	/* clear the Tx/IN interrupts */
-	GR_USB_DIEPINT(USB_EP_CONSOLE) = 0xffffffff;
-}
-
-static void ep_event(enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	epN_reset(USB_EP_CONSOLE);
-
-	is_reset = 1;
-
-	/* Flush any queued data */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-	hook_call_deferred(&rx_fifo_handler_data, 0);
-
-	usb_enable_rx(USB_MAX_PACKET_SIZE);
-}
-
-
-USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event);
-
-static int usb_wait_console(void)
-{
-	timestamp_t deadline = get_time();
-	int wait_time_us = 1;
-
-	if (!is_enabled || !tx_fifo_is_ready())
-		return EC_SUCCESS;
-
-	deadline.val += USB_CONSOLE_TIMEOUT_US;
-
-	/*
-	 * If the USB console is not used, Tx buffer would never free up.
-	 * In this case, let's drop characters immediately instead of sitting
-	 * for some time just to time out. On the other hand, if the last
-	 * Tx is good, it's likely the host is there to receive data, and
-	 * we should wait so that we don't clobber the buffer.
-	 */
-	if (last_tx_ok) {
-		while (queue_space(&tx_q) < USB_MAX_PACKET_SIZE || !is_reset) {
-			if (timestamp_expired(deadline, NULL) ||
-			    in_interrupt_context()) {
-				last_tx_ok = 0;
-				return EC_ERROR_TIMEOUT;
-			}
-			if (wait_time_us < MSEC)
-				udelay(wait_time_us);
-			else
-				usleep(wait_time_us);
-			wait_time_us *= 2;
-		}
-
-		return EC_SUCCESS;
-	}
-
-	last_tx_ok = queue_space(&tx_q);
-	return EC_SUCCESS;
-}
-static int __tx_char(void *context, int c)
-{
-	struct queue *state =
-			(struct queue *) context;
-
-	if (c == '\n' && __tx_char(state, '\r'))
-		return 1;
-
-	QUEUE_ADD_UNITS(state, &c, 1);
-	return 0;
-}
-
-/*
- * Public USB console implementation below.
- */
-int usb_getc(void)
-{
-	int c;
-
-	if (!is_enabled)
-		return -1;
-
-	if (QUEUE_REMOVE_UNITS(&rx_q, &c, 1))
-		return c;
-
-	return -1;
-}
-
-int usb_puts(const char *outstr)
-{
-	int ret;
-	struct queue state;
-
-	if (is_readonly)
-		return EC_SUCCESS;
-
-	ret  = usb_wait_console();
-	if (ret)
-		return ret;
-
-	state = tx_q;
-	while (*outstr)
-		if (__tx_char(&state, *outstr++))
-			break;
-
-	if (queue_count(&state))
-		handle_output();
-
-	return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS;
-}
-
-int usb_putc(int c)
-{
-	char string[2];
-
-	string[0] = c;
-	string[1] = '\0';
-	return usb_puts(string);
-}
-
-int usb_vprintf(const char *format, va_list args)
-{
-	int ret;
-	struct queue state;
-
-	if (is_readonly)
-		return EC_SUCCESS;
-
-	ret = usb_wait_console();
-	if (ret)
-		return ret;
-
-	state = tx_q;
-	ret = vfnprintf(__tx_char, &state, format, args);
-
-	if (queue_count(&state))
-		handle_output();
-
-	return ret;
-}
-
-void usb_console_enable(int enabled, int readonly)
-{
-	is_enabled = enabled;
-	is_readonly = readonly;
-}
diff --git a/chip/stm32/usb_dwc_console.h b/chip/stm32/usb_dwc_console.h
deleted file mode 100644
index ab2206d359..0000000000
--- a/chip/stm32/usb_dwc_console.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CHIP_STM32_USB_DWC_CONSOLE_H
-#define __CHIP_STM32_USB_DWC_CONSOLE_H
-
-#include "usb_hw.h"
-
-extern struct dwc_usb_ep ep_console_ctl;
-
-#endif  /* __CHIP_STM32_USB_DWC_CONSOLE_H */
diff --git a/chip/stm32/usb_dwc_hw.h b/chip/stm32/usb_dwc_hw.h
deleted file mode 100644
index d1fe07cb87..0000000000
--- a/chip/stm32/usb_dwc_hw.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_DWC_HW_H
-#define __CROS_EC_USB_DWC_HW_H
-
-#include "usb_dwc_registers.h"
-
-/* Helpers for endpoint declaration */
-#define _EP_HANDLER2(num, suffix) CONCAT3(ep_, num, suffix)
-#define _EP_TX_HANDLER(num) _EP_HANDLER2(num, _tx)
-#define _EP_RX_HANDLER(num) _EP_HANDLER2(num, _rx)
-#define _EP_EVENT_HANDLER(num) _EP_HANDLER2(num, _evt)
-/* Used to check function types are correct (attribute alias does not do it) */
-#define _EP_TX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _tx_typecheck)
-#define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck)
-#define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck)
-
-#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)  \
-	void _EP_TX_HANDLER(num)(void)				  \
-		__attribute__ ((alias(STRINGIFY(tx_handler))));	  \
-	void _EP_RX_HANDLER(num)(void)                            \
-		__attribute__ ((alias(STRINGIFY(rx_handler))));	  \
-	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)	  \
-		__attribute__ ((alias(STRINGIFY(evt_handler))));  \
-	static __unused void					  \
-	(*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler;	  \
-	static __unused void					  \
-	(*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler;	  \
-	static __unused void					  \
-	(*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\
-			= evt_handler
-
-/* Endpoint callbacks */
-extern void (*usb_ep_tx[]) (void);
-extern void (*usb_ep_rx[]) (void);
-extern void (*usb_ep_event[]) (enum usb_ep_event evt);
-struct usb_setup_packet;
-/* EP0 Interface handler callbacks */
-extern int (*usb_iface_request[]) (struct usb_setup_packet *req);
-
-
-/* True if the HW Rx/OUT FIFO is currently listening. */
-int rx_ep_is_active(uint32_t ep_num);
-
-/* Number of bytes the HW Rx/OUT FIFO has for us.
- *
- * @param ep_num        USB endpoint
- *
- * @returns             number of bytes ready, zero if none.
- */
-int rx_ep_pending(uint32_t ep_num);
-
-/* True if the Tx/IN FIFO can take some bytes from us. */
-int tx_ep_is_ready(uint32_t ep_num);
-
-/* Write packets of data IN to the host.
- *
- * This function uses DMA, so the *data write buffer
- * must persist until the write completion event.
- *
- * @param ep_num        USB endpoint to write
- * @param len           number of bytes to write
- * @param data          pointer of data to write
- *
- * @return              bytes written
- */
-int usb_write_ep(uint32_t ep_num, int len, void *data);
-
-/* Read a packet of data OUT from the host.
- *
- * This function uses DMA, so the *data write buffer
- * must persist until the read completion event.
- *
- * @param ep_num        USB endpoint to read
- * @param len           number of bytes to read
- * @param data          pointer of data to read
- *
- * @return              EC_SUCCESS on success
- */
-int usb_read_ep(uint32_t ep_num, int len, void *data);
-
-/* Tx/IN interrupt handler */
-void usb_epN_tx(uint32_t ep_num);
-
-/* Rx/OUT endpoint interrupt handler */
-void usb_epN_rx(uint32_t ep_num);
-
-/* Reset endpoint HW block. */
-void epN_reset(uint32_t ep_num);
-
-/*
- * Declare any interface-specific control request handlers. These Setup packets
- * arrive on the control endpoint (EP0), but are handled by the interface code.
- * The callback must prepare the EP0 IN or OUT FIFOs and return the number of
- * bytes placed in the IN FIFO. A negative return value will STALL the response
- * (and thus indicate error to the host).
- */
-#define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request)
-#define USB_DECLARE_IFACE(num, handler)				\
-	int _IFACE_HANDLER(num)(struct usb_setup_packet *req)	\
-		__attribute__ ((alias(STRINGIFY(handler))))
-
-#endif	/* __CROS_EC_USB_DWC_HW_H */
diff --git a/chip/stm32/usb_dwc_i2c.h b/chip/stm32/usb_dwc_i2c.h
deleted file mode 100644
index e44002268a..0000000000
--- a/chip/stm32/usb_dwc_i2c.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_DWC_I2C_H
-#define __CROS_EC_USB_DWC_I2C_H
-#include "usb_i2c.h"
-
-/* I2C over USB interface. This gets declared in usb_i2c.c */
-extern struct dwc_usb_ep i2c_usb__ep_ctl;
-
-#endif /* __CROS_EC_USB_DWC_I2C_H */
diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h
deleted file mode 100644
index faac9ca775..0000000000
--- a/chip/stm32/usb_dwc_registers.h
+++ /dev/null
@@ -1,7533 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for STM32F446 USB
- */
-
-#ifndef __CHIP_STM32_USB_DWC_REGISTERS_H
-#define __CHIP_STM32_USB_DWC_REGISTERS_H
-
-/* Endpoint state */
-struct dwc_usb_ep {
-	int max_packet;
-	int tx_fifo;
-
-	int out_pending;
-	int out_expected;
-	uint8_t *out_data;
-	uint8_t *out_databuffer;
-	int out_databuffer_max;
-	const struct deferred_data *rx_deferred;
-
-	int in_packets;
-	int in_pending;
-	uint8_t *in_data;
-	uint8_t *in_databuffer;
-	int in_databuffer_max;
-	const struct deferred_data *tx_deferred;
-};
-
-/* USB state */
-enum dwc_usb_speed {
-	USB_SPEED_FS = 0,
-	USB_SPEED_HS,
-};
-
-enum dwc_usb_phy {
-	USB_PHY_INTERNAL = 0,
-	USB_PHY_ULPI,
-};
-
-struct dwc_usb {
-	struct dwc_usb_ep *ep[USB_EP_COUNT];
-	enum dwc_usb_speed speed;
-	enum dwc_usb_phy phy_type;
-	int dma_en;
-	/* IRQ must be STM32_IRQ_OTG_FS / STM32_IRQ_OTG_HS */
-	int irq;
-};
-
-extern struct dwc_usb_ep ep0_ctl;
-extern struct dwc_usb usb_ctl;
-
-/*
- * Added Alias Module Family Base Address to 0-instance Module Base Address
- * Simplify GBASE(mname) macro
- */
-#define GC_MODULE_OFFSET         0x10000
-
-#define GBASE(mname)      \
-	GC_ ## mname ## _BASE_ADDR
-#define GOFFSET(mname, rname)  \
-	GC_ ## mname ## _ ## rname ## _OFFSET
-
-#define GREG8(mname, rname) \
-	REG8(GBASE(mname) + GOFFSET(mname, rname))
-#define GREG32(mname, rname) \
-	REG32(GBASE(mname) + GOFFSET(mname, rname))
-#define GREG32_ADDR(mname, rname) \
-	REG32_ADDR(GBASE(mname) + GOFFSET(mname, rname))
-#define GWRITE(mname, rname, value) (GREG32(mname, rname) = (value))
-#define GREAD(mname, rname)	    GREG32(mname, rname)
-
-#define GFIELD_MASK(mname, rname, fname) \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _MASK
-
-#define GFIELD_LSB(mname, rname, fname)  \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _LSB
-
-#define GREAD_FIELD(mname, rname, fname) \
-	((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
-
-#define GWRITE_FIELD(mname, rname, fname, fval) \
-	(GREG32(mname, rname) = \
-	((GREG32(mname, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
-
-
-#define GBASE_I(mname, i)     (GBASE(mname) + i*GC_MODULE_OFFSET)
-
-#define GREG32_I(mname, i, rname) \
-		REG32(GBASE_I(mname, i) + GOFFSET(mname, rname))
-
-#define GREG32_ADDR_I(mname, i, rname) \
-		REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname))
-
-#define GWRITE_I(mname, i, rname, value) (GREG32_I(mname, i, rname) = (value))
-#define GREAD_I(mname, i, rname)	        GREG32_I(mname, i, rname)
-
-#define GREAD_FIELD_I(mname, i, rname, fname) \
-	((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
-
-#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \
-	(GREG32_I(mname, i, rname) = \
-	((GREG32_I(mname, i, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
-
-/* Replace masked bits with val << lsb */
-#define REG_WRITE_MLV(reg, mask, lsb, val) \
-		(reg = ((reg & ~mask) | ((val << lsb) & mask)))
-
-
-/* USB device controller */
-#define GR_USB_REG(off)               REG32(GC_USB_BASE_ADDR + (off))
-#define GR_USB_GOTGCTL                GR_USB_REG(GC_USB_GOTGCTL_OFFSET)
-#define GR_USB_GOTGINT                GR_USB_REG(GC_USB_GOTGINT_OFFSET)
-#define GR_USB_GAHBCFG                GR_USB_REG(GC_USB_GAHBCFG_OFFSET)
-#define GR_USB_GUSBCFG                GR_USB_REG(GC_USB_GUSBCFG_OFFSET)
-#define GR_USB_GRSTCTL                GR_USB_REG(GC_USB_GRSTCTL_OFFSET)
-#define GR_USB_GINTSTS                GR_USB_REG(GC_USB_GINTSTS_OFFSET)
-#define   GINTSTS(bit)                (1 << GC_USB_GINTSTS_ ## bit ## _LSB)
-#define GR_USB_GINTMSK                GR_USB_REG(GC_USB_GINTMSK_OFFSET)
-#define   GINTMSK(bit)                (1 << GC_USB_GINTMSK_ ## bit ## MSK_LSB)
-#define GR_USB_GRXSTSR                GR_USB_REG(GC_USB_GRXSTSR_OFFSET)
-#define GR_USB_GRXSTSP                GR_USB_REG(GC_USB_GRXSTSP_OFFSET)
-#define GR_USB_GRXFSIZ                GR_USB_REG(GC_USB_GRXFSIZ_OFFSET)
-#define GR_USB_GNPTXFSIZ              GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET)
-/*#define GR_USB_GGPIO                  GR_USB_REG(GC_USB_GGPIO_OFFSET)*/
-#define GR_USB_GCCFG                  GR_USB_REG(GC_USB_GCCFG_OFFSET)
-#define  GCCFG_VBDEN            BIT(21)
-#define  GCCFG_PWRDWN           BIT(16)
-#define GR_USB_PCGCCTL                GR_USB_REG(GC_USB_PCGCCTL_OFFSET)
-
-#define GR_USB_GSNPSID                GR_USB_REG(GC_USB_GSNPSID_OFFSET)
-#define GR_USB_GHWCFG1                GR_USB_REG(GC_USB_GHWCFG1_OFFSET)
-#define GR_USB_GHWCFG2                GR_USB_REG(GC_USB_GHWCFG2_OFFSET)
-#define GR_USB_GHWCFG3                GR_USB_REG(GC_USB_GHWCFG3_OFFSET)
-#define GR_USB_GHWCFG4                GR_USB_REG(GC_USB_GHWCFG4_OFFSET)
-#define GR_USB_GDFIFOCFG              GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET)
-#define GR_USB_DIEPTXF(n)	\
-	GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4)
-#define GR_USB_DCFG                   GR_USB_REG(GC_USB_DCFG_OFFSET)
-#define GR_USB_DCTL                   GR_USB_REG(GC_USB_DCTL_OFFSET)
-#define GR_USB_DSTS                   GR_USB_REG(GC_USB_DSTS_OFFSET)
-#define GR_USB_DIEPMSK                GR_USB_REG(GC_USB_DIEPMSK_OFFSET)
-#define GR_USB_DOEPMSK                GR_USB_REG(GC_USB_DOEPMSK_OFFSET)
-#define GR_USB_DAINT                  GR_USB_REG(GC_USB_DAINT_OFFSET)
-#define GR_USB_DAINTMSK               GR_USB_REG(GC_USB_DAINTMSK_OFFSET)
-#define  DAINT_INEP(ep)               (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB))
-#define  DAINT_OUTEP(ep)	\
-	(1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB))
-#define GR_USB_DTHRCTL                GR_USB_REG(GC_USB_DTHRCTL_OFFSET)
-#define  DTHRCTL_TXTHRLEN_6           (0x40 << 2)
-#define  DTHRCTL_RXTHRLEN_6           (0x40 << 17)
-#define  DTHRCTL_RXTHREN              BIT(16)
-#define  DTHRCTL_ISOTHREN             BIT(1)
-#define  DTHRCTL_NONISOTHREN          BIT(0)
-#define GR_USB_DIEPEMPMSK             GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET)
-
-#define GR_USB_EPIREG(off, n)         GR_USB_REG(0x900 + (n) * 0x20 + (off))
-#define GR_USB_EPOREG(off, n)         GR_USB_REG(0xb00 + (n) * 0x20 + (off))
-#define GR_USB_DIEPCTL(n)             GR_USB_EPIREG(0x00, n)
-#define GR_USB_DIEPINT(n)             GR_USB_EPIREG(0x08, n)
-#define GR_USB_DIEPTSIZ(n)            GR_USB_EPIREG(0x10, n)
-#define GR_USB_DIEPDMA(n)             GR_USB_EPIREG(0x14, n)
-#define GR_USB_DTXFSTS(n)             GR_USB_EPIREG(0x18, n)
-#define GR_USB_DIEPDMAB(n)            GR_USB_EPIREG(0x1c, n)
-#define GR_USB_DOEPCTL(n)             GR_USB_EPOREG(0x00, n)
-#define GR_USB_DOEPINT(n)             GR_USB_EPOREG(0x08, n)
-#define GR_USB_DOEPTSIZ(n)            GR_USB_EPOREG(0x10, n)
-#define GR_USB_DOEPDMA(n)             GR_USB_EPOREG(0x14, n)
-#define GR_USB_DOEPDMAB(n)            GR_USB_EPOREG(0x1c, n)
-
-#define GOTGCTL_BVALOEN               BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB)
-#define GOTGCTL_BVALOVAL              BIT(7)
-
-/* Bit 5 */
-#define GAHBCFG_DMA_EN                BIT(GC_USB_GAHBCFG_DMAEN_LSB)
-/* Bit 1 */
-#define GAHBCFG_GLB_INTR_EN           BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB)
-/* HS Burst Len */
-#define GAHBCFG_HBSTLEN_INCR4         (3 << GC_USB_GAHBCFG_HBSTLEN_LSB)
-/* Bit 7 */
-#define GAHBCFG_NP_TXF_EMP_LVL        (1 <<  GC_USB_GAHBCFG_NPTXFEMPLVL_LSB)
-#define GAHBCFG_TXFELVL               GAHBCFG_NP_TXF_EMP_LVL
-#define GAHBCFG_PTXFELVL              BIT(8)
-
-#define GUSBCFG_TOUTCAL(n)            (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \
-				       & GC_USB_GUSBCFG_TOUTCAL_MASK)
-#define GUSBCFG_USBTRDTIM(n)          (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \
-				       & GC_USB_GUSBCFG_USBTRDTIM_MASK)
-/* Force device mode */
-#define GUSBCFG_FDMOD                 BIT(GC_USB_GUSBCFG_FDMOD_LSB)
-#define GUSBCFG_PHYSEL                BIT(6)
-#define GUSBCFG_SRPCAP                BIT(8)
-#define GUSBCFG_HNPCAP                BIT(9)
-#define GUSBCFG_ULPIFSLS              BIT(17)
-#define GUSBCFG_ULPIAR                BIT(18)
-#define GUSBCFG_ULPICSM               BIT(19)
-#define GUSBCFG_ULPIEVBUSD            BIT(20)
-#define GUSBCFG_ULPIEVBUSI            BIT(21)
-#define GUSBCFG_TSDPS                 BIT(22)
-#define GUSBCFG_PCCI                  BIT(23)
-#define GUSBCFG_PTCI                  BIT(24)
-#define GUSBCFG_ULPIIPD               BIT(25)
-#define GUSBCFG_TSDPS                 BIT(22)
-
-
-#define GRSTCTL_CSFTRST               BIT(GC_USB_GRSTCTL_CSFTRST_LSB)
-#define GRSTCTL_AHBIDLE               BIT(GC_USB_GRSTCTL_AHBIDLE_LSB)
-#define GRSTCTL_TXFFLSH               BIT(GC_USB_GRSTCTL_TXFFLSH_LSB)
-#define GRSTCTL_RXFFLSH               BIT(GC_USB_GRSTCTL_RXFFLSH_LSB)
-#define GRSTCTL_TXFNUM(n)	\
-	(((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK)
-
-#define DCFG_DEVSPD_HSULPI            (0 << GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVSPD_FSULPI            BIT(GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVSPD_FS48              (3 << GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVADDR(a)	\
-	(((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK)
-#define DCFG_NZLSOHSK                 BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB)
-
-#define DCTL_SFTDISCON                BIT(GC_USB_DCTL_SFTDISCON_LSB)
-#define DCTL_CGOUTNAK                 BIT(GC_USB_DCTL_CGOUTNAK_LSB)
-#define DCTL_CGNPINNAK                BIT(GC_USB_DCTL_CGNPINNAK_LSB)
-#define DCTL_PWRONPRGDONE             BIT(GC_USB_DCTL_PWRONPRGDONE_LSB)
-
-/* Device Endpoint Common IN Interrupt Mask bits */
-#define DIEPMSK_AHBERRMSK             BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB)
-#define DIEPMSK_BNAININTRMSK          BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB)
-#define DIEPMSK_EPDISBLDMSK           BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB)
-#define DIEPMSK_INEPNAKEFFMSK         BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB)
-#define DIEPMSK_INTKNEPMISMSK         BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB)
-#define DIEPMSK_INTKNTXFEMPMSK        BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB)
-#define DIEPMSK_NAKMSK                BIT(GC_USB_DIEPMSK_NAKMSK_LSB)
-#define DIEPMSK_TIMEOUTMSK            BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB)
-#define DIEPMSK_TXFIFOUNDRNMSK        BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB)
-#define DIEPMSK_XFERCOMPLMSK          BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB)
-
-/* Device Endpoint Common OUT Interrupt Mask bits */
-#define DOEPMSK_AHBERRMSK             BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB)
-#define DOEPMSK_BBLEERRMSK            BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB)
-#define DOEPMSK_BNAOUTINTRMSK         BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB)
-#define DOEPMSK_EPDISBLDMSK           BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB)
-#define DOEPMSK_NAKMSK                BIT(GC_USB_DOEPMSK_NAKMSK_LSB)
-#define DOEPMSK_NYETMSK               BIT(GC_USB_DOEPMSK_NYETMSK_LSB)
-#define DOEPMSK_OUTPKTERRMSK          BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB)
-#define DOEPMSK_OUTTKNEPDISMSK        BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB)
-#define DOEPMSK_SETUPMSK              BIT(GC_USB_DOEPMSK_SETUPMSK_LSB)
-#define DOEPMSK_STSPHSERCVDMSK        BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB)
-#define DOEPMSK_XFERCOMPLMSK          BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB)
-
-/* Device Endpoint-n IN Interrupt Register bits */
-#define DIEPINT_AHBERR             BIT(GC_USB_DIEPINT0_AHBERR_LSB)
-#define DIEPINT_BBLEERR            BIT(GC_USB_DIEPINT0_BBLEERR_LSB)
-#define DIEPINT_BNAINTR            BIT(GC_USB_DIEPINT0_BNAINTR_LSB)
-#define DIEPINT_EPDISBLD           BIT(GC_USB_DIEPINT0_EPDISBLD_LSB)
-#define DIEPINT_INEPNAKEFF         BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB)
-#define DIEPINT_INTKNEPMIS         BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB)
-#define DIEPINT_INTKNTXFEMP        BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB)
-#define DIEPINT_NAKINTRPT          BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB)
-#define DIEPINT_NYETINTRPT         BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB)
-#define DIEPINT_PKTDRPSTS          BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB)
-#define DIEPINT_TIMEOUT            BIT(GC_USB_DIEPINT0_TIMEOUT_LSB)
-#define DIEPINT_TXFEMP             BIT(GC_USB_DIEPINT0_TXFEMP_LSB)
-#define DIEPINT_TXFIFOUNDRN        BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB)
-#define DIEPINT_XFERCOMPL          BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB)
-
-/* Device Endpoint-n OUT Interrupt Register bits */
-#define DOEPINT_AHBERR             BIT(GC_USB_DOEPINT0_AHBERR_LSB)
-#define DOEPINT_BACK2BACKSETUP     BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB)
-#define DOEPINT_BBLEERR            BIT(GC_USB_DOEPINT0_BBLEERR_LSB)
-#define DOEPINT_BNAINTR            BIT(GC_USB_DOEPINT0_BNAINTR_LSB)
-#define DOEPINT_EPDISBLD           BIT(GC_USB_DOEPINT0_EPDISBLD_LSB)
-#define DOEPINT_NAKINTRPT          BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB)
-#define DOEPINT_NYETINTRPT         BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB)
-#define DOEPINT_OUTPKTERR          BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB)
-#define DOEPINT_OUTTKNEPDIS        BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB)
-#define DOEPINT_PKTDRPSTS          BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB)
-#define DOEPINT_SETUP              BIT(GC_USB_DOEPINT0_SETUP_LSB)
-#define DOEPINT_STSPHSERCVD        BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB)
-#define DOEPINT_STUPPKTRCVD        BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB)
-#define DOEPINT_XFERCOMPL          BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB)
-
-#define DXEPCTL_EPTYPE_CTRL           (0 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_ISO            (1 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_BULK           (2 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_INT            (3 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_MASK           GC_USB_DIEPCTL0_EPTYPE_MASK
-#define DXEPCTL_TXFNUM(n)             ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB)
-#define DXEPCTL_STALL                 BIT(GC_USB_DIEPCTL0_STALL_LSB)
-#define DXEPCTL_CNAK                  BIT(GC_USB_DIEPCTL0_CNAK_LSB)
-#define DXEPCTL_DPID                  BIT(GC_USB_DIEPCTL0_DPID_LSB)
-#define DXEPCTL_SNAK                  BIT(GC_USB_DIEPCTL0_SNAK_LSB)
-#define DXEPCTL_NAKSTS                BIT(GC_USB_DIEPCTL0_NAKSTS_LSB)
-#define DXEPCTL_EPENA                 BIT(GC_USB_DIEPCTL0_EPENA_LSB)
-#define DXEPCTL_EPDIS                 BIT(GC_USB_DIEPCTL0_EPDIS_LSB)
-#define DXEPCTL_USBACTEP              BIT(GC_USB_DIEPCTL0_USBACTEP_LSB)
-#define DXEPCTL_MPS64                 (0 << GC_USB_DIEPCTL0_MPS_LSB)
-#define DXEPCTL_MPS(cnt)              ((cnt) << GC_USB_DIEPCTL1_MPS_LSB)
-
-#define DXEPTSIZ_SUPCNT(n)            ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB)
-#define DXEPTSIZ_PKTCNT(n)            ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB)
-#define DXEPTSIZ_XFERSIZE(n)          ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB)
-
-#define DOEPDMA_BS_HOST_RDY           (0 << 30)
-#define DOEPDMA_BS_DMA_BSY            (1 << 30)
-#define DOEPDMA_BS_DMA_DONE           (2 << 30)
-#define DOEPDMA_BS_HOST_BSY           (3 << 30)
-#define DOEPDMA_BS_MASK               (3 << 30)
-#define DOEPDMA_RXSTS_MASK            (3 << 28)
-#define DOEPDMA_LAST                  BIT(27)
-#define DOEPDMA_SP                    BIT(26)
-#define DOEPDMA_IOC                   BIT(25)
-#define DOEPDMA_SR                    BIT(24)
-#define DOEPDMA_MTRF                  BIT(23)
-#define DOEPDMA_NAK                   BIT(16)
-#define DOEPDMA_RXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DOEPDMA_RXBYTES_MASK          (0xFFFF << 0)
-
-#define DIEPDMA_BS_HOST_RDY           (0 << 30)
-#define DIEPDMA_BS_DMA_BSY            (1 << 30)
-#define DIEPDMA_BS_DMA_DONE           (2 << 30)
-#define DIEPDMA_BS_HOST_BSY           (3 << 30)
-#define DIEPDMA_BS_MASK               (3 << 30)
-#define DIEPDMA_TXSTS_MASK            (3 << 28)
-#define DIEPDMA_LAST                  BIT(27)
-#define DIEPDMA_SP                    BIT(26)
-#define DIEPDMA_IOC                   BIT(25)
-#define DIEPDMA_TXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DIEPDMA_TXBYTES_MASK          (0xFFFF << 0)
-
-
-
-/* Register defs referenced from DWC block in CR50. This is not a native
- * ST block, so we'll use this modified regdefs list.
- */
-
-#define GC_USB_FS_BASE_ADDR                        0x50000000
-#define GC_USB_HS_BASE_ADDR                        0x40040000
-#ifdef CONFIG_USB_DWC_FS
-#define GC_USB_BASE_ADDR                         GC_USB_FS_BASE_ADDR
-#else
-#define GC_USB_BASE_ADDR                         GC_USB_HS_BASE_ADDR
-#endif
-
-#define GC_USB_GOTGCTL_OFFSET                    0x0
-#define GC_USB_GOTGCTL_DEFAULT                   0x0
-#define GC_USB_GOTGINT_OFFSET                    0x4
-#define GC_USB_GOTGINT_DEFAULT                   0x0
-#define GC_USB_GAHBCFG_OFFSET                    0x8
-#define GC_USB_GAHBCFG_DEFAULT                   0x0
-#define GC_USB_GUSBCFG_OFFSET                    0xc
-#define GC_USB_GUSBCFG_DEFAULT                   0x0
-#define GC_USB_GRSTCTL_OFFSET                    0x10
-#define GC_USB_GRSTCTL_DEFAULT                   0x0
-#define GC_USB_GINTSTS_OFFSET                    0x14
-#define GC_USB_GINTSTS_DEFAULT                   0x0
-#define GC_USB_GINTMSK_OFFSET                    0x18
-#define GC_USB_GINTMSK_DEFAULT                   0x0
-#define GC_USB_GRXSTSR_OFFSET                    0x1c
-#define GC_USB_GRXSTSR_DEFAULT                   0x0
-#define GC_USB_GRXSTSP_OFFSET                    0x20
-#define GC_USB_GRXSTSP_DEFAULT                   0x0
-#define GC_USB_GRXFSIZ_OFFSET                    0x24
-#define GC_USB_GRXFSIZ_DEFAULT                   0x0
-#define GC_USB_GNPTXFSIZ_OFFSET                  0x28
-#define GC_USB_GNPTXFSIZ_DEFAULT                 0x0
-
-#define GC_USB_GCCFG_OFFSET                      0x38
-#define GC_USB_GCCFG_DEFAULT                     0x0
-#define GC_USB_GUID_OFFSET                       0x3c
-#define GC_USB_GUID_DEFAULT                      0x0
-#define GC_USB_GSNPSID_OFFSET                    0x40
-#define GC_USB_GSNPSID_DEFAULT                   0x0
-#define GC_USB_GHWCFG1_OFFSET                    0x44
-#define GC_USB_GHWCFG1_DEFAULT                   0x0
-#define GC_USB_GHWCFG2_OFFSET                    0x48
-#define GC_USB_GHWCFG2_DEFAULT                   0x0
-#define GC_USB_GHWCFG3_OFFSET                    0x4c
-#define GC_USB_GHWCFG3_DEFAULT                   0x0
-#define GC_USB_GHWCFG4_OFFSET                    0x50
-#define GC_USB_GHWCFG4_DEFAULT                   0x0
-#define GC_USB_GDFIFOCFG_OFFSET                  0x5c
-#define GC_USB_GDFIFOCFG_DEFAULT                 0x0
-#define GC_USB_DIEPTXF1_OFFSET                   0x104
-#define GC_USB_DIEPTXF1_DEFAULT                  0x1000
-#define GC_USB_DIEPTXF2_OFFSET                   0x108
-#define GC_USB_DIEPTXF2_DEFAULT                  0x0
-#define GC_USB_DIEPTXF3_OFFSET                   0x10c
-#define GC_USB_DIEPTXF3_DEFAULT                  0x0
-#define GC_USB_DIEPTXF4_OFFSET                   0x110
-#define GC_USB_DIEPTXF4_DEFAULT                  0x0
-#define GC_USB_DIEPTXF5_OFFSET                   0x114
-#define GC_USB_DIEPTXF5_DEFAULT                  0x0
-#define GC_USB_DIEPTXF6_OFFSET                   0x118
-#define GC_USB_DIEPTXF6_DEFAULT                  0x0
-#define GC_USB_DIEPTXF7_OFFSET                   0x11c
-#define GC_USB_DIEPTXF7_DEFAULT                  0x0
-#define GC_USB_DIEPTXF8_OFFSET                   0x120
-#define GC_USB_DIEPTXF8_DEFAULT                  0x0
-#define GC_USB_DIEPTXF9_OFFSET                   0x124
-#define GC_USB_DIEPTXF9_DEFAULT                  0x0
-#define GC_USB_DIEPTXF10_OFFSET                  0x128
-#define GC_USB_DIEPTXF10_DEFAULT                 0x0
-#define GC_USB_DIEPTXF11_OFFSET                  0x12c
-#define GC_USB_DIEPTXF11_DEFAULT                 0x0
-#define GC_USB_DIEPTXF12_OFFSET                  0x130
-#define GC_USB_DIEPTXF12_DEFAULT                 0x0
-#define GC_USB_DIEPTXF13_OFFSET                  0x134
-#define GC_USB_DIEPTXF13_DEFAULT                 0x0
-#define GC_USB_DIEPTXF14_OFFSET                  0x138
-#define GC_USB_DIEPTXF14_DEFAULT                 0x0
-#define GC_USB_DIEPTXF15_OFFSET                  0x13c
-#define GC_USB_DIEPTXF15_DEFAULT                 0x0
-#define GC_USB_DCFG_OFFSET                       0x800
-#define GC_USB_DCFG_DEFAULT                      0x8000000
-#define GC_USB_DCTL_OFFSET                       0x804
-#define GC_USB_DCTL_DEFAULT                      0x0
-#define GC_USB_DSTS_OFFSET                       0x808
-#define GC_USB_DSTS_DEFAULT                      0x0
-#define GC_USB_DIEPMSK_OFFSET                    0x810
-#define GC_USB_DIEPMSK_DEFAULT                   0x80
-#define GC_USB_DOEPMSK_OFFSET                    0x814
-#define GC_USB_DOEPMSK_DEFAULT                   0x0
-#define GC_USB_DAINT_OFFSET                      0x818
-#define GC_USB_DAINT_DEFAULT                     0x0
-#define GC_USB_DAINTMSK_OFFSET                   0x81c
-#define GC_USB_DAINTMSK_DEFAULT                  0x0
-#define GC_USB_DVBUSDIS_OFFSET                   0x828
-#define GC_USB_DVBUSDIS_DEFAULT                  0x0
-#define GC_USB_DVBUSPULSE_OFFSET                 0x82c
-#define GC_USB_DVBUSPULSE_DEFAULT                0x0
-#define GC_USB_DTHRCTL_OFFSET                    0x830
-#define GC_USB_DTHRCTL_DEFAULT                   0x0
-#define GC_USB_DIEPEMPMSK_OFFSET                 0x834
-#define GC_USB_DIEPEMPMSK_DEFAULT                0x0
-#define GC_USB_DIEPCTL0_OFFSET                   0x900
-#define GC_USB_DIEPCTL0_DEFAULT                  0x0
-#define GC_USB_DIEPINT0_OFFSET                   0x908
-#define GC_USB_DIEPINT0_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ0_OFFSET                  0x910
-#define GC_USB_DIEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DIEPDMA0_OFFSET                   0x914
-#define GC_USB_DIEPDMA0_DEFAULT                  0x0
-#define GC_USB_DTXFSTS0_OFFSET                   0x918
-#define GC_USB_DTXFSTS0_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB0_OFFSET                  0x91c
-#define GC_USB_DIEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DIEPCTL1_OFFSET                   0x920
-#define GC_USB_DIEPCTL1_DEFAULT                  0x0
-#define GC_USB_DIEPINT1_OFFSET                   0x928
-#define GC_USB_DIEPINT1_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ1_OFFSET                  0x930
-#define GC_USB_DIEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DIEPDMA1_OFFSET                   0x934
-#define GC_USB_DIEPDMA1_DEFAULT                  0x0
-#define GC_USB_DTXFSTS1_OFFSET                   0x938
-#define GC_USB_DTXFSTS1_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB1_OFFSET                  0x93c
-#define GC_USB_DIEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DIEPCTL2_OFFSET                   0x940
-#define GC_USB_DIEPCTL2_DEFAULT                  0x0
-#define GC_USB_DIEPINT2_OFFSET                   0x948
-#define GC_USB_DIEPINT2_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ2_OFFSET                  0x950
-#define GC_USB_DIEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DIEPDMA2_OFFSET                   0x954
-#define GC_USB_DIEPDMA2_DEFAULT                  0x0
-#define GC_USB_DTXFSTS2_OFFSET                   0x958
-#define GC_USB_DTXFSTS2_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB2_OFFSET                  0x95c
-#define GC_USB_DIEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DIEPCTL3_OFFSET                   0x960
-#define GC_USB_DIEPCTL3_DEFAULT                  0x0
-#define GC_USB_DIEPINT3_OFFSET                   0x968
-#define GC_USB_DIEPINT3_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ3_OFFSET                  0x970
-#define GC_USB_DIEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DIEPDMA3_OFFSET                   0x974
-#define GC_USB_DIEPDMA3_DEFAULT                  0x0
-#define GC_USB_DTXFSTS3_OFFSET                   0x978
-#define GC_USB_DTXFSTS3_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB3_OFFSET                  0x97c
-#define GC_USB_DIEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DIEPCTL4_OFFSET                   0x980
-#define GC_USB_DIEPCTL4_DEFAULT                  0x0
-#define GC_USB_DIEPINT4_OFFSET                   0x988
-#define GC_USB_DIEPINT4_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ4_OFFSET                  0x990
-#define GC_USB_DIEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DIEPDMA4_OFFSET                   0x994
-#define GC_USB_DIEPDMA4_DEFAULT                  0x0
-#define GC_USB_DTXFSTS4_OFFSET                   0x998
-#define GC_USB_DTXFSTS4_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB4_OFFSET                  0x99c
-#define GC_USB_DIEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DIEPCTL5_OFFSET                   0x9a0
-#define GC_USB_DIEPCTL5_DEFAULT                  0x0
-#define GC_USB_DIEPINT5_OFFSET                   0x9a8
-#define GC_USB_DIEPINT5_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ5_OFFSET                  0x9b0
-#define GC_USB_DIEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DIEPDMA5_OFFSET                   0x9b4
-#define GC_USB_DIEPDMA5_DEFAULT                  0x0
-#define GC_USB_DTXFSTS5_OFFSET                   0x9b8
-#define GC_USB_DTXFSTS5_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB5_OFFSET                  0x9bc
-#define GC_USB_DIEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DIEPCTL6_OFFSET                   0x9c0
-#define GC_USB_DIEPCTL6_DEFAULT                  0x0
-#define GC_USB_DIEPINT6_OFFSET                   0x9c8
-#define GC_USB_DIEPINT6_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ6_OFFSET                  0x9d0
-#define GC_USB_DIEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DIEPDMA6_OFFSET                   0x9d4
-#define GC_USB_DIEPDMA6_DEFAULT                  0x0
-#define GC_USB_DTXFSTS6_OFFSET                   0x9d8
-#define GC_USB_DTXFSTS6_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB6_OFFSET                  0x9dc
-#define GC_USB_DIEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DIEPCTL7_OFFSET                   0x9e0
-#define GC_USB_DIEPCTL7_DEFAULT                  0x0
-#define GC_USB_DIEPINT7_OFFSET                   0x9e8
-#define GC_USB_DIEPINT7_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ7_OFFSET                  0x9f0
-#define GC_USB_DIEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DIEPDMA7_OFFSET                   0x9f4
-#define GC_USB_DIEPDMA7_DEFAULT                  0x0
-#define GC_USB_DTXFSTS7_OFFSET                   0x9f8
-#define GC_USB_DTXFSTS7_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB7_OFFSET                  0x9fc
-#define GC_USB_DIEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DIEPCTL8_OFFSET                   0xa00
-#define GC_USB_DIEPCTL8_DEFAULT                  0x0
-#define GC_USB_DIEPINT8_OFFSET                   0xa08
-#define GC_USB_DIEPINT8_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ8_OFFSET                  0xa10
-#define GC_USB_DIEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DIEPDMA8_OFFSET                   0xa14
-#define GC_USB_DIEPDMA8_DEFAULT                  0x0
-#define GC_USB_DTXFSTS8_OFFSET                   0xa18
-#define GC_USB_DTXFSTS8_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB8_OFFSET                  0xa1c
-#define GC_USB_DIEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DIEPCTL9_OFFSET                   0xa20
-#define GC_USB_DIEPCTL9_DEFAULT                  0x0
-#define GC_USB_DIEPINT9_OFFSET                   0xa28
-#define GC_USB_DIEPINT9_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ9_OFFSET                  0xa30
-#define GC_USB_DIEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DIEPDMA9_OFFSET                   0xa34
-#define GC_USB_DIEPDMA9_DEFAULT                  0x0
-#define GC_USB_DTXFSTS9_OFFSET                   0xa38
-#define GC_USB_DTXFSTS9_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB9_OFFSET                  0xa3c
-#define GC_USB_DIEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DIEPCTL10_OFFSET                  0xa40
-#define GC_USB_DIEPCTL10_DEFAULT                 0x0
-#define GC_USB_DIEPINT10_OFFSET                  0xa48
-#define GC_USB_DIEPINT10_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ10_OFFSET                 0xa50
-#define GC_USB_DIEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DIEPDMA10_OFFSET                  0xa54
-#define GC_USB_DIEPDMA10_DEFAULT                 0x0
-#define GC_USB_DTXFSTS10_OFFSET                  0xa58
-#define GC_USB_DTXFSTS10_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB10_OFFSET                 0xa5c
-#define GC_USB_DIEPDMAB10_DEFAULT                0x0
-#define GC_USB_DIEPCTL11_OFFSET                  0xa60
-#define GC_USB_DIEPCTL11_DEFAULT                 0x0
-#define GC_USB_DIEPINT11_OFFSET                  0xa68
-#define GC_USB_DIEPINT11_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ11_OFFSET                 0xa70
-#define GC_USB_DIEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DIEPDMA11_OFFSET                  0xa74
-#define GC_USB_DIEPDMA11_DEFAULT                 0x0
-#define GC_USB_DTXFSTS11_OFFSET                  0xa78
-#define GC_USB_DTXFSTS11_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB11_OFFSET                 0xa7c
-#define GC_USB_DIEPDMAB11_DEFAULT                0x0
-#define GC_USB_DIEPCTL12_OFFSET                  0xa80
-#define GC_USB_DIEPCTL12_DEFAULT                 0x0
-#define GC_USB_DIEPINT12_OFFSET                  0xa88
-#define GC_USB_DIEPINT12_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ12_OFFSET                 0xa90
-#define GC_USB_DIEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DIEPDMA12_OFFSET                  0xa94
-#define GC_USB_DIEPDMA12_DEFAULT                 0x0
-#define GC_USB_DTXFSTS12_OFFSET                  0xa98
-#define GC_USB_DTXFSTS12_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB12_OFFSET                 0xa9c
-#define GC_USB_DIEPDMAB12_DEFAULT                0x0
-#define GC_USB_DIEPCTL13_OFFSET                  0xaa0
-#define GC_USB_DIEPCTL13_DEFAULT                 0x0
-#define GC_USB_DIEPINT13_OFFSET                  0xaa8
-#define GC_USB_DIEPINT13_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ13_OFFSET                 0xab0
-#define GC_USB_DIEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DIEPDMA13_OFFSET                  0xab4
-#define GC_USB_DIEPDMA13_DEFAULT                 0x0
-#define GC_USB_DTXFSTS13_OFFSET                  0xab8
-#define GC_USB_DTXFSTS13_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB13_OFFSET                 0xabc
-#define GC_USB_DIEPDMAB13_DEFAULT                0x0
-#define GC_USB_DIEPCTL14_OFFSET                  0xac0
-#define GC_USB_DIEPCTL14_DEFAULT                 0x0
-#define GC_USB_DIEPINT14_OFFSET                  0xac8
-#define GC_USB_DIEPINT14_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ14_OFFSET                 0xad0
-#define GC_USB_DIEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DIEPDMA14_OFFSET                  0xad4
-#define GC_USB_DIEPDMA14_DEFAULT                 0x0
-#define GC_USB_DTXFSTS14_OFFSET                  0xad8
-#define GC_USB_DTXFSTS14_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB14_OFFSET                 0xadc
-#define GC_USB_DIEPDMAB14_DEFAULT                0x0
-#define GC_USB_DIEPCTL15_OFFSET                  0xae0
-#define GC_USB_DIEPCTL15_DEFAULT                 0x0
-#define GC_USB_DIEPINT15_OFFSET                  0xae8
-#define GC_USB_DIEPINT15_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ15_OFFSET                 0xaf0
-#define GC_USB_DIEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DIEPDMA15_OFFSET                  0xaf4
-#define GC_USB_DIEPDMA15_DEFAULT                 0x0
-#define GC_USB_DTXFSTS15_OFFSET                  0xaf8
-#define GC_USB_DTXFSTS15_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB15_OFFSET                 0xafc
-#define GC_USB_DIEPDMAB15_DEFAULT                0x0
-#define GC_USB_DOEPCTL0_OFFSET                   0xb00
-#define GC_USB_DOEPCTL0_DEFAULT                  0x0
-#define GC_USB_DOEPINT0_OFFSET                   0xb08
-#define GC_USB_DOEPINT0_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ0_OFFSET                  0xb10
-#define GC_USB_DOEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DOEPDMA0_OFFSET                   0xb14
-#define GC_USB_DOEPDMA0_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB0_OFFSET                  0xb1c
-#define GC_USB_DOEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DOEPCTL1_OFFSET                   0xb20
-#define GC_USB_DOEPCTL1_DEFAULT                  0x0
-#define GC_USB_DOEPINT1_OFFSET                   0xb28
-#define GC_USB_DOEPINT1_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ1_OFFSET                  0xb30
-#define GC_USB_DOEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DOEPDMA1_OFFSET                   0xb34
-#define GC_USB_DOEPDMA1_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB1_OFFSET                  0xb3c
-#define GC_USB_DOEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DOEPCTL2_OFFSET                   0xb40
-#define GC_USB_DOEPCTL2_DEFAULT                  0x0
-#define GC_USB_DOEPINT2_OFFSET                   0xb48
-#define GC_USB_DOEPINT2_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ2_OFFSET                  0xb50
-#define GC_USB_DOEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DOEPDMA2_OFFSET                   0xb54
-#define GC_USB_DOEPDMA2_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB2_OFFSET                  0xb5c
-#define GC_USB_DOEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DOEPCTL3_OFFSET                   0xb60
-#define GC_USB_DOEPCTL3_DEFAULT                  0x0
-#define GC_USB_DOEPINT3_OFFSET                   0xb68
-#define GC_USB_DOEPINT3_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ3_OFFSET                  0xb70
-#define GC_USB_DOEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DOEPDMA3_OFFSET                   0xb74
-#define GC_USB_DOEPDMA3_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB3_OFFSET                  0xb7c
-#define GC_USB_DOEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DOEPCTL4_OFFSET                   0xb80
-#define GC_USB_DOEPCTL4_DEFAULT                  0x0
-#define GC_USB_DOEPINT4_OFFSET                   0xb88
-#define GC_USB_DOEPINT4_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ4_OFFSET                  0xb90
-#define GC_USB_DOEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DOEPDMA4_OFFSET                   0xb94
-#define GC_USB_DOEPDMA4_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB4_OFFSET                  0xb9c
-#define GC_USB_DOEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DOEPCTL5_OFFSET                   0xba0
-#define GC_USB_DOEPCTL5_DEFAULT                  0x0
-#define GC_USB_DOEPINT5_OFFSET                   0xba8
-#define GC_USB_DOEPINT5_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ5_OFFSET                  0xbb0
-#define GC_USB_DOEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DOEPDMA5_OFFSET                   0xbb4
-#define GC_USB_DOEPDMA5_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB5_OFFSET                  0xbbc
-#define GC_USB_DOEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DOEPCTL6_OFFSET                   0xbc0
-#define GC_USB_DOEPCTL6_DEFAULT                  0x0
-#define GC_USB_DOEPINT6_OFFSET                   0xbc8
-#define GC_USB_DOEPINT6_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ6_OFFSET                  0xbd0
-#define GC_USB_DOEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DOEPDMA6_OFFSET                   0xbd4
-#define GC_USB_DOEPDMA6_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB6_OFFSET                  0xbdc
-#define GC_USB_DOEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DOEPCTL7_OFFSET                   0xbe0
-#define GC_USB_DOEPCTL7_DEFAULT                  0x0
-#define GC_USB_DOEPINT7_OFFSET                   0xbe8
-#define GC_USB_DOEPINT7_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ7_OFFSET                  0xbf0
-#define GC_USB_DOEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DOEPDMA7_OFFSET                   0xbf4
-#define GC_USB_DOEPDMA7_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB7_OFFSET                  0xbfc
-#define GC_USB_DOEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DOEPCTL8_OFFSET                   0xc00
-#define GC_USB_DOEPCTL8_DEFAULT                  0x0
-#define GC_USB_DOEPINT8_OFFSET                   0xc08
-#define GC_USB_DOEPINT8_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ8_OFFSET                  0xc10
-#define GC_USB_DOEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DOEPDMA8_OFFSET                   0xc14
-#define GC_USB_DOEPDMA8_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB8_OFFSET                  0xc1c
-#define GC_USB_DOEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DOEPCTL9_OFFSET                   0xc20
-#define GC_USB_DOEPCTL9_DEFAULT                  0x0
-#define GC_USB_DOEPINT9_OFFSET                   0xc28
-#define GC_USB_DOEPINT9_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ9_OFFSET                  0xc30
-#define GC_USB_DOEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DOEPDMA9_OFFSET                   0xc34
-#define GC_USB_DOEPDMA9_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB9_OFFSET                  0xc3c
-#define GC_USB_DOEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DOEPCTL10_OFFSET                  0xc40
-#define GC_USB_DOEPCTL10_DEFAULT                 0x0
-#define GC_USB_DOEPINT10_OFFSET                  0xc48
-#define GC_USB_DOEPINT10_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ10_OFFSET                 0xc50
-#define GC_USB_DOEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DOEPDMA10_OFFSET                  0xc54
-#define GC_USB_DOEPDMA10_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB10_OFFSET                 0xc5c
-#define GC_USB_DOEPDMAB10_DEFAULT                0x0
-#define GC_USB_DOEPCTL11_OFFSET                  0xc60
-#define GC_USB_DOEPCTL11_DEFAULT                 0x0
-#define GC_USB_DOEPINT11_OFFSET                  0xc68
-#define GC_USB_DOEPINT11_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ11_OFFSET                 0xc70
-#define GC_USB_DOEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DOEPDMA11_OFFSET                  0xc74
-#define GC_USB_DOEPDMA11_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB11_OFFSET                 0xc7c
-#define GC_USB_DOEPDMAB11_DEFAULT                0x0
-#define GC_USB_DOEPCTL12_OFFSET                  0xc80
-#define GC_USB_DOEPCTL12_DEFAULT                 0x0
-#define GC_USB_DOEPINT12_OFFSET                  0xc88
-#define GC_USB_DOEPINT12_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ12_OFFSET                 0xc90
-#define GC_USB_DOEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DOEPDMA12_OFFSET                  0xc94
-#define GC_USB_DOEPDMA12_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB12_OFFSET                 0xc9c
-#define GC_USB_DOEPDMAB12_DEFAULT                0x0
-#define GC_USB_DOEPCTL13_OFFSET                  0xca0
-#define GC_USB_DOEPCTL13_DEFAULT                 0x0
-#define GC_USB_DOEPINT13_OFFSET                  0xca8
-#define GC_USB_DOEPINT13_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ13_OFFSET                 0xcb0
-#define GC_USB_DOEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DOEPDMA13_OFFSET                  0xcb4
-#define GC_USB_DOEPDMA13_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB13_OFFSET                 0xcbc
-#define GC_USB_DOEPDMAB13_DEFAULT                0x0
-#define GC_USB_DOEPCTL14_OFFSET                  0xcc0
-#define GC_USB_DOEPCTL14_DEFAULT                 0x0
-#define GC_USB_DOEPINT14_OFFSET                  0xcc8
-#define GC_USB_DOEPINT14_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ14_OFFSET                 0xcd0
-#define GC_USB_DOEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DOEPDMA14_OFFSET                  0xcd4
-#define GC_USB_DOEPDMA14_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB14_OFFSET                 0xcdc
-#define GC_USB_DOEPDMAB14_DEFAULT                0x0
-#define GC_USB_DOEPCTL15_OFFSET                  0xce0
-#define GC_USB_DOEPCTL15_DEFAULT                 0x0
-#define GC_USB_DOEPINT15_OFFSET                  0xce8
-#define GC_USB_DOEPINT15_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ15_OFFSET                 0xcf0
-#define GC_USB_DOEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DOEPDMA15_OFFSET                  0xcf4
-#define GC_USB_DOEPDMA15_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB15_OFFSET                 0xcfc
-#define GC_USB_DOEPDMAB15_DEFAULT                0x0
-#define GC_USB_PCGCCTL_OFFSET                    0xe00
-#define GC_USB_PCGCCTL_DEFAULT                   0x0
-#define GC_USB_DFIFO_OFFSET                      0x20000
-#define GC_USB_GOTGCTL_BVALIDOVEN_LSB            0x6
-#define GC_USB_GOTGCTL_BVALIDOVEN_MASK           0x40
-#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE           0x1
-#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT        0x0
-#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET         0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB           0x7
-#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK          0x80
-#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE          0x1
-#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT       0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET        0x0
-#define GC_USB_GOTGCTL_CONIDSTS_LSB              0x10
-#define GC_USB_GOTGCTL_CONIDSTS_MASK             0x10000
-#define GC_USB_GOTGCTL_CONIDSTS_SIZE             0x1
-#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT          0x0
-#define GC_USB_GOTGCTL_CONIDSTS_OFFSET           0x0
-#define GC_USB_GOTGCTL_BSESVLD_LSB               0x13
-#define GC_USB_GOTGCTL_BSESVLD_MASK              0x80000
-#define GC_USB_GOTGCTL_BSESVLD_SIZE              0x1
-#define GC_USB_GOTGCTL_BSESVLD_DEFAULT           0x0
-#define GC_USB_GOTGCTL_BSESVLD_OFFSET            0x0
-#define GC_USB_GOTGCTL_OTGVER_LSB                0x14
-#define GC_USB_GOTGCTL_OTGVER_MASK               0x100000
-#define GC_USB_GOTGCTL_OTGVER_SIZE               0x1
-#define GC_USB_GOTGCTL_OTGVER_DEFAULT            0x0
-#define GC_USB_GOTGCTL_OTGVER_OFFSET             0x0
-#define GC_USB_GOTGCTL_CURMOD_LSB                0x15
-#define GC_USB_GOTGCTL_CURMOD_MASK               0x200000
-#define GC_USB_GOTGCTL_CURMOD_SIZE               0x1
-#define GC_USB_GOTGCTL_CURMOD_DEFAULT            0x0
-#define GC_USB_GOTGCTL_CURMOD_OFFSET             0x0
-#define GC_USB_GOTGINT_SESENDDET_LSB             0x2
-#define GC_USB_GOTGINT_SESENDDET_MASK            0x4
-#define GC_USB_GOTGINT_SESENDDET_SIZE            0x1
-#define GC_USB_GOTGINT_SESENDDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_SESENDDET_OFFSET          0x4
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB      0x8
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK     0x100
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB      0x9
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK     0x200
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGDET_LSB             0x11
-#define GC_USB_GOTGINT_HSTNEGDET_MASK            0x20000
-#define GC_USB_GOTGINT_HSTNEGDET_SIZE            0x1
-#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_HSTNEGDET_OFFSET          0x4
-#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB           0x12
-#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK          0x40000
-#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE          0x1
-#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT       0x0
-#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET        0x4
-#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB           0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT       0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET        0x8
-#define GC_USB_GAHBCFG_HBSTLEN_LSB               0x1
-#define GC_USB_GAHBCFG_HBSTLEN_MASK              0x1e
-#define GC_USB_GAHBCFG_HBSTLEN_SIZE              0x4
-#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT           0x0
-#define GC_USB_GAHBCFG_HBSTLEN_OFFSET            0x8
-#define GC_USB_GAHBCFG_DMAEN_LSB                 0x5
-#define GC_USB_GAHBCFG_DMAEN_MASK                0x20
-#define GC_USB_GAHBCFG_DMAEN_SIZE                0x1
-#define GC_USB_GAHBCFG_DMAEN_DEFAULT             0x0
-#define GC_USB_GAHBCFG_DMAEN_OFFSET              0x8
-
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB           0x7
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK          0x80
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE          0x1
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT       0x0
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET        0x8
-
-#define GC_USB_GAHBCFG_REMMEMSUPP_LSB            0x15
-#define GC_USB_GAHBCFG_REMMEMSUPP_MASK           0x200000
-#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE           0x1
-#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT        0x0
-#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET         0x8
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB        0x16
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK       0x400000
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE       0x1
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT    0x0
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET     0x8
-#define GC_USB_GAHBCFG_AHBSINGLE_LSB             0x17
-#define GC_USB_GAHBCFG_AHBSINGLE_MASK            0x800000
-#define GC_USB_GAHBCFG_AHBSINGLE_SIZE            0x1
-#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT         0x0
-#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET          0x8
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB      0x18
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK     0x1000000
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE     0x1
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT  0x0
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET   0x8
-#define GC_USB_GUSBCFG_TOUTCAL_LSB               0x0
-#define GC_USB_GUSBCFG_TOUTCAL_MASK              0x7
-#define GC_USB_GUSBCFG_TOUTCAL_SIZE              0x3
-#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT           0x0
-#define GC_USB_GUSBCFG_TOUTCAL_OFFSET            0xc
-
-#define GC_USB_GUSBCFG_USBTRDTIM_LSB             0xa
-#define GC_USB_GUSBCFG_USBTRDTIM_MASK            0x3c00
-#define GC_USB_GUSBCFG_USBTRDTIM_SIZE            0x4
-#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT         0x0
-#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET          0xc
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB         15
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK        0x8000
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE        0x1
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT     0x0
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET      0xc
-#define GC_USB_GUSBCFG_ULPIFSLS_LSB              17
-#define GC_USB_GUSBCFG_ULPIFSLS_MASK             0x20000
-#define GC_USB_GUSBCFG_ULPIFSLS_SIZE             0x1
-#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT          0x0
-#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET           0xc
-#define GC_USB_GUSBCFG_ULPIAUTORES_LSB           18
-#define GC_USB_GUSBCFG_ULPIAUTORES_MASK          0x40000
-#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET        0xc
-#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB           19
-#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK          0x80000
-#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET        0xc
-
-#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB            20
-#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK           0x100000
-#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE           0x1
-#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT        0x0
-#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET         0xc
-
-#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB            21
-#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK           0x200000
-#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE           0x1
-#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT        0x0
-#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET         0xc
-
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB        22
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK       0x400000
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE       0x1
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT    0x0
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET     0xc
-
-#define GC_USB_GUSBCFG_PCCI_LSB                  23
-#define GC_USB_GUSBCFG_PCCI_MASK                 BIT(23)
-#define GC_USB_GUSBCFG_PCCI_SIZE                 0x1
-#define GC_USB_GUSBCFG_PCCI_DEFAULT              0x0
-#define GC_USB_GUSBCFG_PCCI_OFFSET               0xc
-
-#define GC_USB_GUSBCFG_PTCI_LSB                  24
-#define GC_USB_GUSBCFG_PTCI_MASK                 BIT(24)
-#define GC_USB_GUSBCFG_PTCI_SIZE                 0x1
-#define GC_USB_GUSBCFG_PTCI_DEFAULT              0x0
-#define GC_USB_GUSBCFG_PTCI_OFFSET               0xc
-
-#define GC_USB_GUSBCFG_ULPIIPD_LSB               25
-#define GC_USB_GUSBCFG_ULPIIPD_MASK              BIT(25)
-#define GC_USB_GUSBCFG_ULPIIPD_SIZE              0x1
-#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT           0x0
-#define GC_USB_GUSBCFG_ULPIIPD_OFFSET            0xc
-
-#define GC_USB_GUSBCFG_FHMOD_LSB                 29
-#define GC_USB_GUSBCFG_FHMOD_MASK                BIT(29)
-#define GC_USB_GUSBCFG_FHMOD_SIZE                0x1
-#define GC_USB_GUSBCFG_FHMOD_DEFAULT             0x0
-#define GC_USB_GUSBCFG_FHMOD_OFFSET              0xc
-
-#define GC_USB_GUSBCFG_FDMOD_LSB                 30
-#define GC_USB_GUSBCFG_FDMOD_MASK                BIT(30)
-#define GC_USB_GUSBCFG_FDMOD_SIZE                0x1
-#define GC_USB_GUSBCFG_FDMOD_DEFAULT             0x0
-#define GC_USB_GUSBCFG_FDMOD_OFFSET              0xc
-
-#define GC_USB_GRSTCTL_CSFTRST_LSB               0x0
-#define GC_USB_GRSTCTL_CSFTRST_MASK              0x1
-#define GC_USB_GRSTCTL_CSFTRST_SIZE              0x1
-#define GC_USB_GRSTCTL_CSFTRST_DEFAULT           0x0
-#define GC_USB_GRSTCTL_CSFTRST_OFFSET            0x10
-#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB           0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK          0x2
-#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE          0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT       0x0
-#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET        0x10
-#define GC_USB_GRSTCTL_RXFFLSH_LSB               0x4
-#define GC_USB_GRSTCTL_RXFFLSH_MASK              0x10
-#define GC_USB_GRSTCTL_RXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_RXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFFLSH_LSB               0x5
-#define GC_USB_GRSTCTL_TXFFLSH_MASK              0x20
-#define GC_USB_GRSTCTL_TXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_TXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFNUM_LSB                0x6
-#define GC_USB_GRSTCTL_TXFNUM_MASK               0x7c0
-#define GC_USB_GRSTCTL_TXFNUM_SIZE               0x5
-#define GC_USB_GRSTCTL_TXFNUM_DEFAULT            0x0
-#define GC_USB_GRSTCTL_TXFNUM_OFFSET             0x10
-#define GC_USB_GRSTCTL_DMAREQ_LSB                0x1e
-#define GC_USB_GRSTCTL_DMAREQ_MASK               0x40000000
-#define GC_USB_GRSTCTL_DMAREQ_SIZE               0x1
-#define GC_USB_GRSTCTL_DMAREQ_DEFAULT            0x0
-#define GC_USB_GRSTCTL_DMAREQ_OFFSET             0x10
-#define GC_USB_GRSTCTL_AHBIDLE_LSB               0x1f
-#define GC_USB_GRSTCTL_AHBIDLE_MASK              0x80000000
-#define GC_USB_GRSTCTL_AHBIDLE_SIZE              0x1
-#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT           0x0
-#define GC_USB_GRSTCTL_AHBIDLE_OFFSET            0x10
-#define GC_USB_GINTSTS_CURMOD_LSB                0x0
-#define GC_USB_GINTSTS_CURMOD_MASK               0x1
-#define GC_USB_GINTSTS_CURMOD_SIZE               0x1
-#define GC_USB_GINTSTS_CURMOD_DEFAULT            0x0
-#define GC_USB_GINTSTS_CURMOD_OFFSET             0x14
-#define GC_USB_GINTSTS_MODEMIS_LSB               0x1
-#define GC_USB_GINTSTS_MODEMIS_MASK              0x2
-#define GC_USB_GINTSTS_MODEMIS_SIZE              0x1
-#define GC_USB_GINTSTS_MODEMIS_DEFAULT           0x0
-#define GC_USB_GINTSTS_MODEMIS_OFFSET            0x14
-#define GC_USB_GINTSTS_OTGINT_LSB                0x2
-#define GC_USB_GINTSTS_OTGINT_MASK               0x4
-#define GC_USB_GINTSTS_OTGINT_SIZE               0x1
-#define GC_USB_GINTSTS_OTGINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OTGINT_OFFSET             0x14
-#define GC_USB_GINTSTS_SOF_LSB                   0x3
-#define GC_USB_GINTSTS_SOF_MASK                  0x8
-#define GC_USB_GINTSTS_SOF_SIZE                  0x1
-#define GC_USB_GINTSTS_SOF_DEFAULT               0x0
-#define GC_USB_GINTSTS_SOF_OFFSET                0x14
-#define GC_USB_GINTSTS_RXFLVL_LSB                0x4
-#define GC_USB_GINTSTS_RXFLVL_MASK               0x10
-#define GC_USB_GINTSTS_RXFLVL_SIZE               0x1
-#define GC_USB_GINTSTS_RXFLVL_DEFAULT            0x0
-#define GC_USB_GINTSTS_RXFLVL_OFFSET             0x14
-#define GC_USB_GINTSTS_GINNAKEFF_LSB             0x6
-#define GC_USB_GINTSTS_GINNAKEFF_MASK            0x40
-#define GC_USB_GINTSTS_GINNAKEFF_SIZE            0x1
-#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT         0x0
-#define GC_USB_GINTSTS_GINNAKEFF_OFFSET          0x14
-#define GC_USB_GINTSTS_GOUTNAKEFF_LSB            0x7
-#define GC_USB_GINTSTS_GOUTNAKEFF_MASK           0x80
-#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE           0x1
-#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT        0x0
-#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET         0x14
-#define GC_USB_GINTSTS_ERLYSUSP_LSB              0xa
-#define GC_USB_GINTSTS_ERLYSUSP_MASK             0x400
-#define GC_USB_GINTSTS_ERLYSUSP_SIZE             0x1
-#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT          0x0
-#define GC_USB_GINTSTS_ERLYSUSP_OFFSET           0x14
-#define GC_USB_GINTSTS_USBSUSP_LSB               0xb
-#define GC_USB_GINTSTS_USBSUSP_MASK              0x800
-#define GC_USB_GINTSTS_USBSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_USBSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_USBSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_USBRST_LSB                0xc
-#define GC_USB_GINTSTS_USBRST_MASK               0x1000
-#define GC_USB_GINTSTS_USBRST_SIZE               0x1
-#define GC_USB_GINTSTS_USBRST_DEFAULT            0x0
-#define GC_USB_GINTSTS_USBRST_OFFSET             0x14
-#define GC_USB_GINTSTS_ENUMDONE_LSB              0xd
-#define GC_USB_GINTSTS_ENUMDONE_MASK             0x2000
-#define GC_USB_GINTSTS_ENUMDONE_SIZE             0x1
-#define GC_USB_GINTSTS_ENUMDONE_DEFAULT          0x0
-#define GC_USB_GINTSTS_ENUMDONE_OFFSET           0x14
-#define GC_USB_GINTSTS_ISOOUTDROP_LSB            0xe
-#define GC_USB_GINTSTS_ISOOUTDROP_MASK           0x4000
-#define GC_USB_GINTSTS_ISOOUTDROP_SIZE           0x1
-#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT        0x0
-#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET         0x14
-#define GC_USB_GINTSTS_EOPF_LSB                  0xf
-#define GC_USB_GINTSTS_EOPF_MASK                 0x8000
-#define GC_USB_GINTSTS_EOPF_SIZE                 0x1
-#define GC_USB_GINTSTS_EOPF_DEFAULT              0x0
-#define GC_USB_GINTSTS_EOPF_OFFSET               0x14
-#define GC_USB_GINTSTS_EPMIS_LSB                 0x11
-#define GC_USB_GINTSTS_EPMIS_MASK                0x20000
-#define GC_USB_GINTSTS_EPMIS_SIZE                0x1
-#define GC_USB_GINTSTS_EPMIS_DEFAULT             0x0
-#define GC_USB_GINTSTS_EPMIS_OFFSET              0x14
-#define GC_USB_GINTSTS_IEPINT_LSB                0x12
-#define GC_USB_GINTSTS_IEPINT_MASK               0x40000
-#define GC_USB_GINTSTS_IEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_IEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_IEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_OEPINT_LSB                0x13
-#define GC_USB_GINTSTS_OEPINT_MASK               0x80000
-#define GC_USB_GINTSTS_OEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_OEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_LSB           0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_MASK          0x100000
-#define GC_USB_GINTSTS_INCOMPISOIN_SIZE          0x1
-#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT       0x0
-#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET        0x14
-#define GC_USB_GINTSTS_INCOMPLP_LSB              0x15
-#define GC_USB_GINTSTS_INCOMPLP_MASK             0x200000
-#define GC_USB_GINTSTS_INCOMPLP_SIZE             0x1
-#define GC_USB_GINTSTS_INCOMPLP_DEFAULT          0x0
-#define GC_USB_GINTSTS_INCOMPLP_OFFSET           0x14
-#define GC_USB_GINTSTS_FETSUSP_LSB               0x16
-#define GC_USB_GINTSTS_FETSUSP_MASK              0x400000
-#define GC_USB_GINTSTS_FETSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_FETSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_FETSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_RESETDET_LSB              0x17
-#define GC_USB_GINTSTS_RESETDET_MASK             0x800000
-#define GC_USB_GINTSTS_RESETDET_SIZE             0x1
-#define GC_USB_GINTSTS_RESETDET_DEFAULT          0x0
-#define GC_USB_GINTSTS_RESETDET_OFFSET           0x14
-#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB          0x1c
-#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK         0x10000000
-#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE         0x1
-#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT      0x0
-#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET       0x14
-#define GC_USB_GINTSTS_SESSREQINT_LSB            0x1e
-#define GC_USB_GINTSTS_SESSREQINT_MASK           0x40000000
-#define GC_USB_GINTSTS_SESSREQINT_SIZE           0x1
-#define GC_USB_GINTSTS_SESSREQINT_DEFAULT        0x0
-#define GC_USB_GINTSTS_SESSREQINT_OFFSET         0x14
-#define GC_USB_GINTSTS_WKUPINT_LSB               0x1f
-#define GC_USB_GINTSTS_WKUPINT_MASK              0x80000000
-#define GC_USB_GINTSTS_WKUPINT_SIZE              0x1
-#define GC_USB_GINTSTS_WKUPINT_DEFAULT           0x0
-#define GC_USB_GINTSTS_WKUPINT_OFFSET            0x14
-#define GC_USB_GINTMSK_MODEMISMSK_LSB            0x1
-#define GC_USB_GINTMSK_MODEMISMSK_MASK           0x2
-#define GC_USB_GINTMSK_MODEMISMSK_SIZE           0x1
-#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_MODEMISMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_OTGINTMSK_LSB             0x2
-#define GC_USB_GINTMSK_OTGINTMSK_MASK            0x4
-#define GC_USB_GINTMSK_OTGINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OTGINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_SOFMSK_LSB                0x3
-#define GC_USB_GINTMSK_SOFMSK_MASK               0x8
-#define GC_USB_GINTMSK_SOFMSK_SIZE               0x1
-#define GC_USB_GINTMSK_SOFMSK_DEFAULT            0x0
-#define GC_USB_GINTMSK_SOFMSK_OFFSET             0x18
-#define GC_USB_GINTMSK_RXFLVLMSK_LSB             0x4
-#define GC_USB_GINTMSK_RXFLVLMSK_MASK            0x10
-#define GC_USB_GINTMSK_RXFLVLMSK_SIZE            0x1
-#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_UNKNOWN5_LSB              0x5
-#define GC_USB_GINTMSK_UNKNOWN5_MASK             0x20
-#define GC_USB_GINTMSK_UNKNOWN5_SIZE             0x1
-#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT          0x0
-#define GC_USB_GINTMSK_UNKNOWN5_OFFSET           0x18
-#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB          0x6
-#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK         0x40
-#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE         0x1
-#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT      0x0
-#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET       0x18
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB         0x7
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK        0x80
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE        0x1
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB           0xa
-#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK          0x400
-#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_USBSUSPMSK_LSB            0xb
-#define GC_USB_GINTMSK_USBSUSPMSK_MASK           0x800
-#define GC_USB_GINTMSK_USBSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_USBRSTMSK_LSB             0xc
-#define GC_USB_GINTMSK_USBRSTMSK_MASK            0x1000
-#define GC_USB_GINTMSK_USBRSTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_USBRSTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_ENUMDONEMSK_LSB           0xd
-#define GC_USB_GINTMSK_ENUMDONEMSK_MASK          0x2000
-#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB         0xe
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK        0x4000
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE        0x1
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_EOPFMSK_LSB               0xf
-#define GC_USB_GINTMSK_EOPFMSK_MASK              0x8000
-#define GC_USB_GINTMSK_EOPFMSK_SIZE              0x1
-#define GC_USB_GINTMSK_EOPFMSK_DEFAULT           0x0
-#define GC_USB_GINTMSK_EOPFMSK_OFFSET            0x18
-#define GC_USB_GINTMSK_UNKNOWN16_LSB             0x10
-#define GC_USB_GINTMSK_UNKNOWN16_MASK            0x10000
-#define GC_USB_GINTMSK_UNKNOWN16_SIZE            0x1
-#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT         0x0
-#define GC_USB_GINTMSK_UNKNOWN16_OFFSET          0x18
-#define GC_USB_GINTMSK_EPMISMSK_LSB              0x11
-#define GC_USB_GINTMSK_EPMISMSK_MASK             0x20000
-#define GC_USB_GINTMSK_EPMISMSK_SIZE             0x1
-#define GC_USB_GINTMSK_EPMISMSK_DEFAULT          0x0
-#define GC_USB_GINTMSK_EPMISMSK_OFFSET           0x18
-#define GC_USB_GINTMSK_IEPINTMSK_LSB             0x12
-#define GC_USB_GINTMSK_IEPINTMSK_MASK            0x40000
-#define GC_USB_GINTMSK_IEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_IEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_OEPINTMSK_LSB             0x13
-#define GC_USB_GINTMSK_OEPINTMSK_MASK            0x80000
-#define GC_USB_GINTMSK_OEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB        0x14
-#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK       0x100000
-#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE       0x1
-#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT    0x0
-#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET     0x18
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB      0x15
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK     0x200000
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE     0x1
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT  0x0
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET   0x18
-#define GC_USB_GINTMSK_FETSUSPMSK_LSB            0x16
-#define GC_USB_GINTMSK_FETSUSPMSK_MASK           0x400000
-#define GC_USB_GINTMSK_FETSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_RESETDETMSK_LSB           0x17
-#define GC_USB_GINTMSK_RESETDETMSK_MASK          0x800000
-#define GC_USB_GINTMSK_RESETDETMSK_SIZE          0x1
-#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_RESETDETMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB       0x1c
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK      0x10000000
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE      0x1
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT   0x0
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET    0x18
-#define GC_USB_GINTMSK_DISCONNINTMSK_LSB         0x1d
-#define GC_USB_GINTMSK_DISCONNINTMSK_MASK        0x20000000
-#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_SESSREQINTMSK_LSB         0x1e
-#define GC_USB_GINTMSK_SESSREQINTMSK_MASK        0x40000000
-#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_WKUPINTMSK_LSB            0x1f
-#define GC_USB_GINTMSK_WKUPINTMSK_MASK           0x80000000
-#define GC_USB_GINTMSK_WKUPINTMSK_SIZE           0x1
-#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET         0x18
-#define GC_USB_GRXSTSR_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSR_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSR_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSR_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSR_CHNUM_OFFSET              0x1c
-#define GC_USB_GRXSTSR_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSR_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSR_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSR_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSR_BCNT_OFFSET               0x1c
-#define GC_USB_GRXSTSR_DPID_LSB                  0xf
-#define GC_USB_GRXSTSR_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSR_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSR_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSR_DPID_OFFSET               0x1c
-#define GC_USB_GRXSTSR_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSR_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSR_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSR_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSR_PKTSTS_OFFSET             0x1c
-#define GC_USB_GRXSTSR_FN_LSB                    0x15
-#define GC_USB_GRXSTSR_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSR_FN_SIZE                   0x4
-#define GC_USB_GRXSTSR_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSR_FN_OFFSET                 0x1c
-#define GC_USB_GRXSTSP_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSP_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSP_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSP_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSP_CHNUM_OFFSET              0x20
-#define GC_USB_GRXSTSP_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSP_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSP_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSP_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSP_BCNT_OFFSET               0x20
-#define GC_USB_GRXSTSP_DPID_LSB                  0xf
-#define GC_USB_GRXSTSP_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSP_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSP_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSP_DPID_OFFSET               0x20
-#define GC_USB_GRXSTSP_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSP_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSP_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSP_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSP_PKTSTS_OFFSET             0x20
-#define GC_USB_GRXSTSP_FN_LSB                    0x15
-#define GC_USB_GRXSTSP_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSP_FN_SIZE                   0x4
-#define GC_USB_GRXSTSP_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSP_FN_OFFSET                 0x20
-#define GC_USB_GRXFSIZ_RXFDEP_LSB                0x0
-#define GC_USB_GRXFSIZ_RXFDEP_MASK               0x7ff
-#define GC_USB_GRXFSIZ_RXFDEP_SIZE               0xb
-#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT            0x0
-#define GC_USB_GRXFSIZ_RXFDEP_OFFSET             0x24
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB      0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK     0xffff
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE     0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT  0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET   0x28
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB         0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK        0xffff0000
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE        0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT     0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET      0x28
-
-#define GC_USB_GUID_GUID_LSB                     0x0
-#define GC_USB_GUID_GUID_MASK                    0xffffffff
-#define GC_USB_GUID_GUID_SIZE                    0x20
-#define GC_USB_GUID_GUID_DEFAULT                 0x0
-#define GC_USB_GUID_GUID_OFFSET                  0x3c
-#define GC_USB_GSNPSID_SYNOPSYSID_LSB            0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_MASK           0xffffffff
-#define GC_USB_GSNPSID_SYNOPSYSID_SIZE           0x20
-#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT        0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET         0x40
-#define GC_USB_GHWCFG1_EPDIR_LSB                 0x0
-#define GC_USB_GHWCFG1_EPDIR_MASK                0xffffffff
-#define GC_USB_GHWCFG1_EPDIR_SIZE                0x20
-#define GC_USB_GHWCFG1_EPDIR_DEFAULT             0x0
-#define GC_USB_GHWCFG1_EPDIR_OFFSET              0x44
-#define GC_USB_GHWCFG2_OTGMODE_LSB               0x0
-#define GC_USB_GHWCFG2_OTGMODE_MASK              0x7
-#define GC_USB_GHWCFG2_OTGMODE_SIZE              0x3
-#define GC_USB_GHWCFG2_OTGMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGMODE_OFFSET            0x48
-#define GC_USB_GHWCFG2_OTGARCH_LSB               0x3
-#define GC_USB_GHWCFG2_OTGARCH_MASK              0x18
-#define GC_USB_GHWCFG2_OTGARCH_SIZE              0x2
-#define GC_USB_GHWCFG2_OTGARCH_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGARCH_OFFSET            0x48
-#define GC_USB_GHWCFG2_SINGPNT_LSB               0x5
-#define GC_USB_GHWCFG2_SINGPNT_MASK              0x20
-#define GC_USB_GHWCFG2_SINGPNT_SIZE              0x1
-#define GC_USB_GHWCFG2_SINGPNT_DEFAULT           0x0
-#define GC_USB_GHWCFG2_SINGPNT_OFFSET            0x48
-#define GC_USB_GHWCFG2_HSPHYTYPE_LSB             0x6
-#define GC_USB_GHWCFG2_HSPHYTYPE_MASK            0xc0
-#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_FSPHYTYPE_LSB             0x8
-#define GC_USB_GHWCFG2_FSPHYTYPE_MASK            0x300
-#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMDEVEPS_LSB             0xa
-#define GC_USB_GHWCFG2_NUMDEVEPS_MASK            0x3c00
-#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE            0x4
-#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB            0xe
-#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK           0x3c000
-#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE           0x4
-#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET         0x48
-#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB          0x12
-#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK         0x40000
-#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE         0x1
-#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT      0x0
-#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET       0x48
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB         0x13
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK        0x80000
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE        0x1
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT     0x0
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET      0x48
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB       0x14
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK      0x100000
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE      0x1
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT   0x0
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET    0x48
-#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB            0x16
-#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK           0xc00000
-#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE           0x2
-#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET         0x48
-#define GC_USB_GHWCFG2_PTXQDEPTH_LSB             0x18
-#define GC_USB_GHWCFG2_PTXQDEPTH_MASK            0x3000000
-#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE            0x2
-#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG2_TKNQDEPTH_LSB             0x1a
-#define GC_USB_GHWCFG2_TKNQDEPTH_MASK            0x7c000000
-#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE            0x5
-#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB         0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK        0xf
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE        0x4
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT     0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET      0x4c
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB          0x4
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK         0x70
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE         0x3
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET       0x4c
-#define GC_USB_GHWCFG3_OTGEN_LSB                 0x7
-#define GC_USB_GHWCFG3_OTGEN_MASK                0x80
-#define GC_USB_GHWCFG3_OTGEN_SIZE                0x1
-#define GC_USB_GHWCFG3_OTGEN_DEFAULT             0x0
-#define GC_USB_GHWCFG3_OTGEN_OFFSET              0x4c
-#define GC_USB_GHWCFG3_I2CINTSEL_LSB             0x8
-#define GC_USB_GHWCFG3_I2CINTSEL_MASK            0x100
-#define GC_USB_GHWCFG3_I2CINTSEL_SIZE            0x1
-#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT         0x0
-#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET          0x4c
-#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB            0x9
-#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK           0x200
-#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE           0x1
-#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_OPTFEATURE_LSB            0xa
-#define GC_USB_GHWCFG3_OPTFEATURE_MASK           0x400
-#define GC_USB_GHWCFG3_OPTFEATURE_SIZE           0x1
-#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT        0x0
-#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET         0x4c
-#define GC_USB_GHWCFG3_RSTTYPE_LSB               0xb
-#define GC_USB_GHWCFG3_RSTTYPE_MASK              0x800
-#define GC_USB_GHWCFG3_RSTTYPE_SIZE              0x1
-#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_RSTTYPE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_ADPSUPPORT_LSB            0xc
-#define GC_USB_GHWCFG3_ADPSUPPORT_MASK           0x1000
-#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE           0x1
-#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_HSICMODE_LSB              0xd
-#define GC_USB_GHWCFG3_HSICMODE_MASK             0x2000
-#define GC_USB_GHWCFG3_HSICMODE_SIZE             0x1
-#define GC_USB_GHWCFG3_HSICMODE_DEFAULT          0x0
-#define GC_USB_GHWCFG3_HSICMODE_OFFSET           0x4c
-#define GC_USB_GHWCFG3_BCSUPPORT_LSB             0xe
-#define GC_USB_GHWCFG3_BCSUPPORT_MASK            0x4000
-#define GC_USB_GHWCFG3_BCSUPPORT_SIZE            0x1
-#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT         0x0
-#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET          0x4c
-#define GC_USB_GHWCFG3_LPMMODE_LSB               0xf
-#define GC_USB_GHWCFG3_LPMMODE_MASK              0x8000
-#define GC_USB_GHWCFG3_LPMMODE_SIZE              0x1
-#define GC_USB_GHWCFG3_LPMMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_LPMMODE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_DFIFODEPTH_LSB            0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_MASK           0xffff0000
-#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE           0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET         0x4c
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB        0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK       0xf
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE       0x4
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT    0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET     0x50
-#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB          0x4
-#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK         0x10
-#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE         0x1
-#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET       0x50
-#define GC_USB_GHWCFG4_AHBFREQ_LSB               0x5
-#define GC_USB_GHWCFG4_AHBFREQ_MASK              0x20
-#define GC_USB_GHWCFG4_AHBFREQ_SIZE              0x1
-#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT           0x0
-#define GC_USB_GHWCFG4_AHBFREQ_OFFSET            0x50
-#define GC_USB_GHWCFG4_HIBERNATION_LSB           0x6
-#define GC_USB_GHWCFG4_HIBERNATION_MASK          0x40
-#define GC_USB_GHWCFG4_HIBERNATION_SIZE          0x1
-#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT       0x0
-#define GC_USB_GHWCFG4_HIBERNATION_OFFSET        0x50
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB   0x7
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK  0x80
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE  0x1
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB          0xe
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK         0xc000
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE         0x2
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET       0x50
-#define GC_USB_GHWCFG4_NUMCTLEPS_LSB             0x10
-#define GC_USB_GHWCFG4_NUMCTLEPS_MASK            0xf0000
-#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE            0x4
-#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET          0x50
-#define GC_USB_GHWCFG4_IDDGFLTR_LSB              0x14
-#define GC_USB_GHWCFG4_IDDGFLTR_MASK             0x100000
-#define GC_USB_GHWCFG4_IDDGFLTR_SIZE             0x1
-#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT          0x0
-#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET           0x50
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB         0x15
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK        0x200000
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE        0x1
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT     0x0
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET      0x50
-#define GC_USB_GHWCFG4_AVALIDFLTR_LSB            0x16
-#define GC_USB_GHWCFG4_AVALIDFLTR_MASK           0x400000
-#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_BVALIDFLTR_LSB            0x17
-#define GC_USB_GHWCFG4_BVALIDFLTR_MASK           0x800000
-#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_SESSENDFLTR_LSB           0x18
-#define GC_USB_GHWCFG4_SESSENDFLTR_MASK          0x1000000
-#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE          0x1
-#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT       0x0
-#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET        0x50
-#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB           0x19
-#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK          0x2000000
-#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE          0x1
-#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT       0x0
-#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET        0x50
-#define GC_USB_GHWCFG4_INEPS_LSB                 0x1a
-#define GC_USB_GHWCFG4_INEPS_MASK                0x3c000000
-#define GC_USB_GHWCFG4_INEPS_SIZE                0x4
-#define GC_USB_GHWCFG4_INEPS_DEFAULT             0x0
-#define GC_USB_GHWCFG4_INEPS_OFFSET              0x50
-#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB        0x1e
-#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK       0x40000000
-#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE       0x1
-#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT    0x0
-#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET     0x50
-#define GC_USB_GHWCFG4_DESCDMA_LSB               0x1f
-#define GC_USB_GHWCFG4_DESCDMA_MASK              0x80000000
-#define GC_USB_GHWCFG4_DESCDMA_SIZE              0x1
-#define GC_USB_GHWCFG4_DESCDMA_DEFAULT           0x0
-#define GC_USB_GHWCFG4_DESCDMA_OFFSET            0x50
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB           0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK          0xffff
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE          0x10
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT       0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET        0x5c
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB      0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK     0xffff0000
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE     0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT  0x0
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET   0x5c
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET    0x104
-#define GC_USB_DIEPTXF1_RESERVED11_LSB           0xc
-#define GC_USB_DIEPTXF1_RESERVED11_MASK          0x1000
-#define GC_USB_DIEPTXF1_RESERVED11_SIZE          0x1
-#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT       0x1
-#define GC_USB_DIEPTXF1_RESERVED11_OFFSET        0x104
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET       0x104
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET    0x108
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET       0x108
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET    0x10c
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET       0x10c
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET    0x110
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET       0x110
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET    0x114
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET       0x114
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET    0x118
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET       0x118
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET    0x11c
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET       0x11c
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET    0x120
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET       0x120
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET    0x124
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET       0x124
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET   0x128
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET      0x128
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET   0x12c
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET      0x12c
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET   0x130
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET      0x130
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET   0x134
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET      0x134
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET   0x138
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET      0x138
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET   0x13c
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET      0x13c
-#define GC_USB_DCFG_DEVSPD_LSB                   0x0
-#define GC_USB_DCFG_DEVSPD_MASK                  0x3
-#define GC_USB_DCFG_DEVSPD_SIZE                  0x2
-#define GC_USB_DCFG_DEVSPD_DEFAULT               0x0
-#define GC_USB_DCFG_DEVSPD_OFFSET                0x800
-#define GC_USB_DCFG_NZSTSOUTHSHK_LSB             0x2
-#define GC_USB_DCFG_NZSTSOUTHSHK_MASK            0x4
-#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE            0x1
-#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT         0x0
-#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET          0x800
-#define GC_USB_DCFG_ENA32KHZSUSP_LSB             0x3
-#define GC_USB_DCFG_ENA32KHZSUSP_MASK            0x8
-#define GC_USB_DCFG_ENA32KHZSUSP_SIZE            0x1
-#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT         0x0
-#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET          0x800
-#define GC_USB_DCFG_DEVADDR_LSB                  0x4
-#define GC_USB_DCFG_DEVADDR_MASK                 0x7f0
-#define GC_USB_DCFG_DEVADDR_SIZE                 0x7
-#define GC_USB_DCFG_DEVADDR_DEFAULT              0x0
-#define GC_USB_DCFG_DEVADDR_OFFSET               0x800
-#define GC_USB_DCFG_PERFRINT_LSB                 0xb
-#define GC_USB_DCFG_PERFRINT_MASK                0x1800
-#define GC_USB_DCFG_PERFRINT_SIZE                0x2
-#define GC_USB_DCFG_PERFRINT_DEFAULT             0x0
-#define GC_USB_DCFG_PERFRINT_OFFSET              0x800
-#define GC_USB_DCFG_ENDEVOUTNAK_LSB              0xd
-#define GC_USB_DCFG_ENDEVOUTNAK_MASK             0x2000
-#define GC_USB_DCFG_ENDEVOUTNAK_SIZE             0x1
-#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT          0x0
-#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET           0x800
-#define GC_USB_DCFG_XCVRDLY_LSB                  0xe
-#define GC_USB_DCFG_XCVRDLY_MASK                 0x4000
-#define GC_USB_DCFG_XCVRDLY_SIZE                 0x1
-#define GC_USB_DCFG_XCVRDLY_DEFAULT              0x0
-#define GC_USB_DCFG_XCVRDLY_OFFSET               0x800
-#define GC_USB_DCFG_ERRATICINTMSK_LSB            0xf
-#define GC_USB_DCFG_ERRATICINTMSK_MASK           0x8000
-#define GC_USB_DCFG_ERRATICINTMSK_SIZE           0x1
-#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT        0x0
-#define GC_USB_DCFG_ERRATICINTMSK_OFFSET         0x800
-#define GC_USB_DCFG_DESCDMA_LSB                  0x17
-#define GC_USB_DCFG_DESCDMA_MASK                 0x800000
-#define GC_USB_DCFG_DESCDMA_SIZE                 0x1
-#define GC_USB_DCFG_DESCDMA_DEFAULT              0x0
-#define GC_USB_DCFG_DESCDMA_OFFSET               0x800
-#define GC_USB_DCFG_PERSCHINTVL_LSB              0x18
-#define GC_USB_DCFG_PERSCHINTVL_MASK             0x3000000
-#define GC_USB_DCFG_PERSCHINTVL_SIZE             0x2
-#define GC_USB_DCFG_PERSCHINTVL_DEFAULT          0x0
-#define GC_USB_DCFG_PERSCHINTVL_OFFSET           0x800
-#define GC_USB_DCFG_RESVALID_LSB                 0x1a
-#define GC_USB_DCFG_RESVALID_MASK                0xfc000000
-#define GC_USB_DCFG_RESVALID_SIZE                0x6
-#define GC_USB_DCFG_RESVALID_DEFAULT             0x2
-#define GC_USB_DCFG_RESVALID_OFFSET              0x800
-#define GC_USB_DCTL_RMTWKUPSIG_LSB               0x0
-#define GC_USB_DCTL_RMTWKUPSIG_MASK              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_SIZE              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT           0x0
-#define GC_USB_DCTL_RMTWKUPSIG_OFFSET            0x804
-#define GC_USB_DCTL_SFTDISCON_LSB                0x1
-#define GC_USB_DCTL_SFTDISCON_MASK               0x2
-#define GC_USB_DCTL_SFTDISCON_SIZE               0x1
-#define GC_USB_DCTL_SFTDISCON_DEFAULT            0x0
-#define GC_USB_DCTL_SFTDISCON_OFFSET             0x804
-#define GC_USB_DCTL_GNPINNAKSTS_LSB              0x2
-#define GC_USB_DCTL_GNPINNAKSTS_MASK             0x4
-#define GC_USB_DCTL_GNPINNAKSTS_SIZE             0x1
-#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT          0x0
-#define GC_USB_DCTL_GNPINNAKSTS_OFFSET           0x804
-#define GC_USB_DCTL_GOUTNAKSTS_LSB               0x3
-#define GC_USB_DCTL_GOUTNAKSTS_MASK              0x8
-#define GC_USB_DCTL_GOUTNAKSTS_SIZE              0x1
-#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT           0x0
-#define GC_USB_DCTL_GOUTNAKSTS_OFFSET            0x804
-#define GC_USB_DCTL_TSTCTL_LSB                   0x4
-#define GC_USB_DCTL_TSTCTL_MASK                  0x70
-#define GC_USB_DCTL_TSTCTL_SIZE                  0x3
-#define GC_USB_DCTL_TSTCTL_DEFAULT               0x0
-#define GC_USB_DCTL_TSTCTL_OFFSET                0x804
-#define GC_USB_DCTL_SGNPINNAK_LSB                0x7
-#define GC_USB_DCTL_SGNPINNAK_MASK               0x80
-#define GC_USB_DCTL_SGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_SGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_SGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_CGNPINNAK_LSB                0x8
-#define GC_USB_DCTL_CGNPINNAK_MASK               0x100
-#define GC_USB_DCTL_CGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_CGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_CGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_SGOUTNAK_LSB                 0x9
-#define GC_USB_DCTL_SGOUTNAK_MASK                0x200
-#define GC_USB_DCTL_SGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_SGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_SGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_CGOUTNAK_LSB                 0xa
-#define GC_USB_DCTL_CGOUTNAK_MASK                0x400
-#define GC_USB_DCTL_CGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_CGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_CGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_PWRONPRGDONE_LSB             0xb
-#define GC_USB_DCTL_PWRONPRGDONE_MASK            0x800
-#define GC_USB_DCTL_PWRONPRGDONE_SIZE            0x1
-#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT         0x0
-#define GC_USB_DCTL_PWRONPRGDONE_OFFSET          0x804
-#define GC_USB_DCTL_GMC_LSB                      0xd
-#define GC_USB_DCTL_GMC_MASK                     0x6000
-#define GC_USB_DCTL_GMC_SIZE                     0x2
-#define GC_USB_DCTL_GMC_DEFAULT                  0x0
-#define GC_USB_DCTL_GMC_OFFSET                   0x804
-#define GC_USB_DCTL_IGNRFRMNUM_LSB               0xf
-#define GC_USB_DCTL_IGNRFRMNUM_MASK              0x8000
-#define GC_USB_DCTL_IGNRFRMNUM_SIZE              0x1
-#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT           0x0
-#define GC_USB_DCTL_IGNRFRMNUM_OFFSET            0x804
-#define GC_USB_DCTL_NAKONBBLE_LSB                0x10
-#define GC_USB_DCTL_NAKONBBLE_MASK               0x10000
-#define GC_USB_DCTL_NAKONBBLE_SIZE               0x1
-#define GC_USB_DCTL_NAKONBBLE_DEFAULT            0x0
-#define GC_USB_DCTL_NAKONBBLE_OFFSET             0x804
-#define GC_USB_DCTL_ENCONTONBNA_LSB              0x11
-#define GC_USB_DCTL_ENCONTONBNA_MASK             0x20000
-#define GC_USB_DCTL_ENCONTONBNA_SIZE             0x1
-#define GC_USB_DCTL_ENCONTONBNA_DEFAULT          0x0
-#define GC_USB_DCTL_ENCONTONBNA_OFFSET           0x804
-#define GC_USB_DSTS_SUSPSTS_LSB                  0x0
-#define GC_USB_DSTS_SUSPSTS_MASK                 0x1
-#define GC_USB_DSTS_SUSPSTS_SIZE                 0x1
-#define GC_USB_DSTS_SUSPSTS_DEFAULT              0x0
-#define GC_USB_DSTS_SUSPSTS_OFFSET               0x808
-#define GC_USB_DSTS_ENUMSPD_LSB                  0x1
-#define GC_USB_DSTS_ENUMSPD_MASK                 0x6
-#define GC_USB_DSTS_ENUMSPD_SIZE                 0x2
-#define GC_USB_DSTS_ENUMSPD_DEFAULT              0x0
-#define GC_USB_DSTS_ENUMSPD_OFFSET               0x808
-#define GC_USB_DSTS_ERRTICERR_LSB                0x3
-#define GC_USB_DSTS_ERRTICERR_MASK               0x8
-#define GC_USB_DSTS_ERRTICERR_SIZE               0x1
-#define GC_USB_DSTS_ERRTICERR_DEFAULT            0x0
-#define GC_USB_DSTS_ERRTICERR_OFFSET             0x808
-#define GC_USB_DSTS_SOFFN_LSB                    0x8
-#define GC_USB_DSTS_SOFFN_MASK                   0x3fff00
-#define GC_USB_DSTS_SOFFN_SIZE                   0xe
-#define GC_USB_DSTS_SOFFN_DEFAULT                0x0
-#define GC_USB_DSTS_SOFFN_OFFSET                 0x808
-#define GC_USB_DSTS_DEVLNSTS_LSB                 0x16
-#define GC_USB_DSTS_DEVLNSTS_MASK                0xc00000
-#define GC_USB_DSTS_DEVLNSTS_SIZE                0x2
-#define GC_USB_DSTS_DEVLNSTS_DEFAULT             0x0
-#define GC_USB_DSTS_DEVLNSTS_OFFSET              0x808
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET        0x810
-#define GC_USB_DIEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DIEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DIEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET          0x810
-#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB            0x3
-#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK           0x8
-#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE           0x1
-#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT        0x0
-#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET         0x810
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB        0x4
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK       0x10
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB         0x5
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK        0x20
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB         0x6
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK        0x40
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_RESERVED7_LSB             0x7
-#define GC_USB_DIEPMSK_RESERVED7_MASK            0x80
-#define GC_USB_DIEPMSK_RESERVED7_SIZE            0x1
-#define GC_USB_DIEPMSK_RESERVED7_DEFAULT         0x1
-#define GC_USB_DIEPMSK_RESERVED7_OFFSET          0x810
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB        0x8
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK       0x100
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_BNAININTRMSK_LSB          0x9
-#define GC_USB_DIEPMSK_BNAININTRMSK_MASK         0x200
-#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DIEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DIEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DIEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DIEPMSK_NAKMSK_OFFSET             0x810
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET        0x814
-#define GC_USB_DOEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DOEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DOEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET          0x814
-#define GC_USB_DOEPMSK_SETUPMSK_LSB              0x3
-#define GC_USB_DOEPMSK_SETUPMSK_MASK             0x8
-#define GC_USB_DOEPMSK_SETUPMSK_SIZE             0x1
-#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT          0x0
-#define GC_USB_DOEPMSK_SETUPMSK_OFFSET           0x814
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB        0x4
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK       0x10
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB        0x5
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK       0x20
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB        0x6
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK       0x40
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE       0x1
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT    0x0
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET     0x814
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB          0x8
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK         0x100
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB         0x9
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK        0x200
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE        0x1
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT     0x0
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET      0x814
-#define GC_USB_DOEPMSK_BBLEERRMSK_LSB            0xc
-#define GC_USB_DOEPMSK_BBLEERRMSK_MASK           0x1000
-#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE           0x1
-#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT        0x0
-#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET         0x814
-#define GC_USB_DOEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DOEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DOEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DOEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DOEPMSK_NAKMSK_OFFSET             0x814
-#define GC_USB_DOEPMSK_NYETMSK_LSB               0xe
-#define GC_USB_DOEPMSK_NYETMSK_MASK              0x4000
-#define GC_USB_DOEPMSK_NYETMSK_SIZE              0x1
-#define GC_USB_DOEPMSK_NYETMSK_DEFAULT           0x0
-#define GC_USB_DOEPMSK_NYETMSK_OFFSET            0x814
-#define GC_USB_DAINT_INEPINT0_LSB                0x0
-#define GC_USB_DAINT_INEPINT0_MASK               0x1
-#define GC_USB_DAINT_INEPINT0_SIZE               0x1
-#define GC_USB_DAINT_INEPINT0_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT0_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT1_LSB                0x1
-#define GC_USB_DAINT_INEPINT1_MASK               0x2
-#define GC_USB_DAINT_INEPINT1_SIZE               0x1
-#define GC_USB_DAINT_INEPINT1_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT1_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT2_LSB                0x2
-#define GC_USB_DAINT_INEPINT2_MASK               0x4
-#define GC_USB_DAINT_INEPINT2_SIZE               0x1
-#define GC_USB_DAINT_INEPINT2_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT2_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT3_LSB                0x3
-#define GC_USB_DAINT_INEPINT3_MASK               0x8
-#define GC_USB_DAINT_INEPINT3_SIZE               0x1
-#define GC_USB_DAINT_INEPINT3_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT3_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT4_LSB                0x4
-#define GC_USB_DAINT_INEPINT4_MASK               0x10
-#define GC_USB_DAINT_INEPINT4_SIZE               0x1
-#define GC_USB_DAINT_INEPINT4_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT4_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT5_LSB                0x5
-#define GC_USB_DAINT_INEPINT5_MASK               0x20
-#define GC_USB_DAINT_INEPINT5_SIZE               0x1
-#define GC_USB_DAINT_INEPINT5_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT5_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT6_LSB                0x6
-#define GC_USB_DAINT_INEPINT6_MASK               0x40
-#define GC_USB_DAINT_INEPINT6_SIZE               0x1
-#define GC_USB_DAINT_INEPINT6_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT6_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT7_LSB                0x7
-#define GC_USB_DAINT_INEPINT7_MASK               0x80
-#define GC_USB_DAINT_INEPINT7_SIZE               0x1
-#define GC_USB_DAINT_INEPINT7_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT7_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT8_LSB                0x8
-#define GC_USB_DAINT_INEPINT8_MASK               0x100
-#define GC_USB_DAINT_INEPINT8_SIZE               0x1
-#define GC_USB_DAINT_INEPINT8_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT8_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT9_LSB                0x9
-#define GC_USB_DAINT_INEPINT9_MASK               0x200
-#define GC_USB_DAINT_INEPINT9_SIZE               0x1
-#define GC_USB_DAINT_INEPINT9_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT9_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT10_LSB               0xa
-#define GC_USB_DAINT_INEPINT10_MASK              0x400
-#define GC_USB_DAINT_INEPINT10_SIZE              0x1
-#define GC_USB_DAINT_INEPINT10_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT10_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT11_LSB               0xb
-#define GC_USB_DAINT_INEPINT11_MASK              0x800
-#define GC_USB_DAINT_INEPINT11_SIZE              0x1
-#define GC_USB_DAINT_INEPINT11_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT11_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT12_LSB               0xc
-#define GC_USB_DAINT_INEPINT12_MASK              0x1000
-#define GC_USB_DAINT_INEPINT12_SIZE              0x1
-#define GC_USB_DAINT_INEPINT12_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT12_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT13_LSB               0xd
-#define GC_USB_DAINT_INEPINT13_MASK              0x2000
-#define GC_USB_DAINT_INEPINT13_SIZE              0x1
-#define GC_USB_DAINT_INEPINT13_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT13_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT14_LSB               0xe
-#define GC_USB_DAINT_INEPINT14_MASK              0x4000
-#define GC_USB_DAINT_INEPINT14_SIZE              0x1
-#define GC_USB_DAINT_INEPINT14_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT14_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT15_LSB               0xf
-#define GC_USB_DAINT_INEPINT15_MASK              0x8000
-#define GC_USB_DAINT_INEPINT15_SIZE              0x1
-#define GC_USB_DAINT_INEPINT15_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT15_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT0_LSB               0x10
-#define GC_USB_DAINT_OUTEPINT0_MASK              0x10000
-#define GC_USB_DAINT_OUTEPINT0_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT0_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT0_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT1_LSB               0x11
-#define GC_USB_DAINT_OUTEPINT1_MASK              0x20000
-#define GC_USB_DAINT_OUTEPINT1_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT1_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT1_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT2_LSB               0x12
-#define GC_USB_DAINT_OUTEPINT2_MASK              0x40000
-#define GC_USB_DAINT_OUTEPINT2_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT2_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT2_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT3_LSB               0x13
-#define GC_USB_DAINT_OUTEPINT3_MASK              0x80000
-#define GC_USB_DAINT_OUTEPINT3_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT3_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT3_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT4_LSB               0x14
-#define GC_USB_DAINT_OUTEPINT4_MASK              0x100000
-#define GC_USB_DAINT_OUTEPINT4_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT4_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT4_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT5_LSB               0x15
-#define GC_USB_DAINT_OUTEPINT5_MASK              0x200000
-#define GC_USB_DAINT_OUTEPINT5_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT5_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT5_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT6_LSB               0x16
-#define GC_USB_DAINT_OUTEPINT6_MASK              0x400000
-#define GC_USB_DAINT_OUTEPINT6_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT6_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT6_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT7_LSB               0x17
-#define GC_USB_DAINT_OUTEPINT7_MASK              0x800000
-#define GC_USB_DAINT_OUTEPINT7_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT7_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT7_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT8_LSB               0x18
-#define GC_USB_DAINT_OUTEPINT8_MASK              0x1000000
-#define GC_USB_DAINT_OUTEPINT8_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT8_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT8_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT9_LSB               0x19
-#define GC_USB_DAINT_OUTEPINT9_MASK              0x2000000
-#define GC_USB_DAINT_OUTEPINT9_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT9_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT9_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT10_LSB              0x1a
-#define GC_USB_DAINT_OUTEPINT10_MASK             0x4000000
-#define GC_USB_DAINT_OUTEPINT10_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT10_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT10_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT11_LSB              0x1b
-#define GC_USB_DAINT_OUTEPINT11_MASK             0x8000000
-#define GC_USB_DAINT_OUTEPINT11_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT11_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT11_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT12_LSB              0x1c
-#define GC_USB_DAINT_OUTEPINT12_MASK             0x10000000
-#define GC_USB_DAINT_OUTEPINT12_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT12_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT12_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT13_LSB              0x1d
-#define GC_USB_DAINT_OUTEPINT13_MASK             0x20000000
-#define GC_USB_DAINT_OUTEPINT13_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT13_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT13_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT14_LSB              0x1e
-#define GC_USB_DAINT_OUTEPINT14_MASK             0x40000000
-#define GC_USB_DAINT_OUTEPINT14_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT14_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT14_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT15_LSB              0x1f
-#define GC_USB_DAINT_OUTEPINT15_MASK             0x80000000
-#define GC_USB_DAINT_OUTEPINT15_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT15_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT15_OFFSET           0x818
-#define GC_USB_DAINTMSK_INEPMSK0_LSB             0x0
-#define GC_USB_DAINTMSK_INEPMSK0_MASK            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK0_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK1_LSB             0x1
-#define GC_USB_DAINTMSK_INEPMSK1_MASK            0x2
-#define GC_USB_DAINTMSK_INEPMSK1_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK1_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK2_LSB             0x2
-#define GC_USB_DAINTMSK_INEPMSK2_MASK            0x4
-#define GC_USB_DAINTMSK_INEPMSK2_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK2_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK3_LSB             0x3
-#define GC_USB_DAINTMSK_INEPMSK3_MASK            0x8
-#define GC_USB_DAINTMSK_INEPMSK3_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK3_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK4_LSB             0x4
-#define GC_USB_DAINTMSK_INEPMSK4_MASK            0x10
-#define GC_USB_DAINTMSK_INEPMSK4_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK4_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK5_LSB             0x5
-#define GC_USB_DAINTMSK_INEPMSK5_MASK            0x20
-#define GC_USB_DAINTMSK_INEPMSK5_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK5_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK6_LSB             0x6
-#define GC_USB_DAINTMSK_INEPMSK6_MASK            0x40
-#define GC_USB_DAINTMSK_INEPMSK6_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK6_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK7_LSB             0x7
-#define GC_USB_DAINTMSK_INEPMSK7_MASK            0x80
-#define GC_USB_DAINTMSK_INEPMSK7_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK7_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK8_LSB             0x8
-#define GC_USB_DAINTMSK_INEPMSK8_MASK            0x100
-#define GC_USB_DAINTMSK_INEPMSK8_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK8_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK9_LSB             0x9
-#define GC_USB_DAINTMSK_INEPMSK9_MASK            0x200
-#define GC_USB_DAINTMSK_INEPMSK9_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK9_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK10_LSB            0xa
-#define GC_USB_DAINTMSK_INEPMSK10_MASK           0x400
-#define GC_USB_DAINTMSK_INEPMSK10_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK10_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK11_LSB            0xb
-#define GC_USB_DAINTMSK_INEPMSK11_MASK           0x800
-#define GC_USB_DAINTMSK_INEPMSK11_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK11_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK12_LSB            0xc
-#define GC_USB_DAINTMSK_INEPMSK12_MASK           0x1000
-#define GC_USB_DAINTMSK_INEPMSK12_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK12_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK13_LSB            0xd
-#define GC_USB_DAINTMSK_INEPMSK13_MASK           0x2000
-#define GC_USB_DAINTMSK_INEPMSK13_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK13_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK14_LSB            0xe
-#define GC_USB_DAINTMSK_INEPMSK14_MASK           0x4000
-#define GC_USB_DAINTMSK_INEPMSK14_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK14_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK15_LSB            0xf
-#define GC_USB_DAINTMSK_INEPMSK15_MASK           0x8000
-#define GC_USB_DAINTMSK_INEPMSK15_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK15_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK0_LSB            0x10
-#define GC_USB_DAINTMSK_OUTEPMSK0_MASK           0x10000
-#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK1_LSB            0x11
-#define GC_USB_DAINTMSK_OUTEPMSK1_MASK           0x20000
-#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK2_LSB            0x12
-#define GC_USB_DAINTMSK_OUTEPMSK2_MASK           0x40000
-#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK3_LSB            0x13
-#define GC_USB_DAINTMSK_OUTEPMSK3_MASK           0x80000
-#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK4_LSB            0x14
-#define GC_USB_DAINTMSK_OUTEPMSK4_MASK           0x100000
-#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK5_LSB            0x15
-#define GC_USB_DAINTMSK_OUTEPMSK5_MASK           0x200000
-#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK6_LSB            0x16
-#define GC_USB_DAINTMSK_OUTEPMSK6_MASK           0x400000
-#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK7_LSB            0x17
-#define GC_USB_DAINTMSK_OUTEPMSK7_MASK           0x800000
-#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK8_LSB            0x18
-#define GC_USB_DAINTMSK_OUTEPMSK8_MASK           0x1000000
-#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK9_LSB            0x19
-#define GC_USB_DAINTMSK_OUTEPMSK9_MASK           0x2000000
-#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK10_LSB           0x1a
-#define GC_USB_DAINTMSK_OUTEPMSK10_MASK          0x4000000
-#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK11_LSB           0x1b
-#define GC_USB_DAINTMSK_OUTEPMSK11_MASK          0x8000000
-#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK12_LSB           0x1c
-#define GC_USB_DAINTMSK_OUTEPMSK12_MASK          0x10000000
-#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK13_LSB           0x1d
-#define GC_USB_DAINTMSK_OUTEPMSK13_MASK          0x20000000
-#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK14_LSB           0x1e
-#define GC_USB_DAINTMSK_OUTEPMSK14_MASK          0x40000000
-#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK15_LSB           0x1f
-#define GC_USB_DAINTMSK_OUTEPMSK15_MASK          0x80000000
-#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET        0x81c
-#define GC_USB_DVBUSDIS_DVBUSDIS_LSB             0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_MASK            0xffff
-#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE            0x10
-#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT         0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET          0x828
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB         0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK        0xfff
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE        0xc
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT     0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET      0x82c
-#define GC_USB_DTHRCTL_NONISOTHREN_LSB           0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_MASK          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_SIZE          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT       0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET        0x830
-#define GC_USB_DTHRCTL_ISOTHREN_LSB              0x1
-#define GC_USB_DTHRCTL_ISOTHREN_MASK             0x2
-#define GC_USB_DTHRCTL_ISOTHREN_SIZE             0x1
-#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ISOTHREN_OFFSET           0x830
-#define GC_USB_DTHRCTL_TXTHRLEN_LSB              0x2
-#define GC_USB_DTHRCTL_TXTHRLEN_MASK             0x7fc
-#define GC_USB_DTHRCTL_TXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB           0xb
-#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK          0x1800
-#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE          0x2
-#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT       0x0
-#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET        0x830
-#define GC_USB_DTHRCTL_RXTHREN_LSB               0x10
-#define GC_USB_DTHRCTL_RXTHREN_MASK              0x10000
-#define GC_USB_DTHRCTL_RXTHREN_SIZE              0x1
-#define GC_USB_DTHRCTL_RXTHREN_DEFAULT           0x0
-#define GC_USB_DTHRCTL_RXTHREN_OFFSET            0x830
-#define GC_USB_DTHRCTL_RXTHRLEN_LSB              0x11
-#define GC_USB_DTHRCTL_RXTHRLEN_MASK             0x3fe0000
-#define GC_USB_DTHRCTL_RXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_ARBPRKEN_LSB              0x1b
-#define GC_USB_DTHRCTL_ARBPRKEN_MASK             0x8000000
-#define GC_USB_DTHRCTL_ARBPRKEN_SIZE             0x1
-#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET           0x830
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB      0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK     0xffff
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE     0x10
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT  0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET   0x834
-#define GC_USB_DIEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DIEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DIEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL0_MPS_OFFSET               0x900
-#define GC_USB_DIEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL0_USBACTEP_OFFSET          0x900
-#define GC_USB_DIEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_NAKSTS_OFFSET            0x900
-#define GC_USB_DIEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_EPTYPE_OFFSET            0x900
-#define GC_USB_DIEPCTL0_STALL_LSB                0x15
-#define GC_USB_DIEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_STALL_OFFSET             0x900
-#define GC_USB_DIEPCTL0_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL0_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL0_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_TXFNUM_OFFSET            0x900
-#define GC_USB_DIEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_CNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_SNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPDIS_OFFSET             0x900
-#define GC_USB_DIEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPENA_OFFSET             0x900
-#define GC_USB_DIEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET         0x908
-#define GC_USB_DIEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT0_EPDISBLD_OFFSET          0x908
-#define GC_USB_DIEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT0_AHBERR_OFFSET            0x908
-#define GC_USB_DIEPINT0_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT0_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT0_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT0_TIMEOUT_OFFSET           0x908
-#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET       0x908
-#define GC_USB_DIEPINT0_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT0_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET        0x908
-#define GC_USB_DIEPINT0_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT0_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET        0x908
-#define GC_USB_DIEPINT0_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT0_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT0_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT0_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT0_TXFEMP_OFFSET            0x908
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET       0x908
-#define GC_USB_DIEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BNAINTR_OFFSET           0x908
-#define GC_USB_DIEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET         0x908
-#define GC_USB_DIEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BBLEERR_OFFSET           0x908
-#define GC_USB_DIEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET         0x908
-#define GC_USB_DIEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET        0x908
-#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET         0x910
-#define GC_USB_DIEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ0_PKTCNT_MASK             0x180000
-#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE             0x2
-#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET           0x910
-#define GC_USB_DIEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA0_DMAADDR_OFFSET           0x914
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET   0x918
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET    0x91c
-#define GC_USB_DIEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL1_MPS_OFFSET               0x920
-#define GC_USB_DIEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_USBACTEP_OFFSET          0x920
-#define GC_USB_DIEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_DPID_OFFSET              0x920
-#define GC_USB_DIEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_NAKSTS_OFFSET            0x920
-#define GC_USB_DIEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_EPTYPE_OFFSET            0x920
-#define GC_USB_DIEPCTL1_STALL_LSB                0x15
-#define GC_USB_DIEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_STALL_OFFSET             0x920
-#define GC_USB_DIEPCTL1_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL1_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL1_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_TXFNUM_OFFSET            0x920
-#define GC_USB_DIEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_CNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_SNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD0PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD1PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPDIS_OFFSET             0x920
-#define GC_USB_DIEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPENA_OFFSET             0x920
-#define GC_USB_DIEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET         0x928
-#define GC_USB_DIEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT1_EPDISBLD_OFFSET          0x928
-#define GC_USB_DIEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT1_AHBERR_OFFSET            0x928
-#define GC_USB_DIEPINT1_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT1_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT1_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT1_TIMEOUT_OFFSET           0x928
-#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET       0x928
-#define GC_USB_DIEPINT1_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT1_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET        0x928
-#define GC_USB_DIEPINT1_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT1_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET        0x928
-#define GC_USB_DIEPINT1_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT1_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT1_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT1_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT1_TXFEMP_OFFSET            0x928
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET       0x928
-#define GC_USB_DIEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BNAINTR_OFFSET           0x928
-#define GC_USB_DIEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET         0x928
-#define GC_USB_DIEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BBLEERR_OFFSET           0x928
-#define GC_USB_DIEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET         0x928
-#define GC_USB_DIEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET        0x928
-#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET         0x930
-#define GC_USB_DIEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET           0x930
-#define GC_USB_DIEPTSIZ1_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ1_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ1_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ1_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ1_MC_OFFSET               0x930
-#define GC_USB_DIEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA1_DMAADDR_OFFSET           0x934
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET   0x938
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET    0x93c
-#define GC_USB_DIEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL2_MPS_OFFSET               0x940
-#define GC_USB_DIEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_USBACTEP_OFFSET          0x940
-#define GC_USB_DIEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_DPID_OFFSET              0x940
-#define GC_USB_DIEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_NAKSTS_OFFSET            0x940
-#define GC_USB_DIEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_EPTYPE_OFFSET            0x940
-#define GC_USB_DIEPCTL2_STALL_LSB                0x15
-#define GC_USB_DIEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_STALL_OFFSET             0x940
-#define GC_USB_DIEPCTL2_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL2_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL2_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_TXFNUM_OFFSET            0x940
-#define GC_USB_DIEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_CNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_SNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD0PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD1PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPDIS_OFFSET             0x940
-#define GC_USB_DIEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPENA_OFFSET             0x940
-#define GC_USB_DIEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET         0x948
-#define GC_USB_DIEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT2_EPDISBLD_OFFSET          0x948
-#define GC_USB_DIEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT2_AHBERR_OFFSET            0x948
-#define GC_USB_DIEPINT2_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT2_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT2_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT2_TIMEOUT_OFFSET           0x948
-#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET       0x948
-#define GC_USB_DIEPINT2_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT2_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET        0x948
-#define GC_USB_DIEPINT2_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT2_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET        0x948
-#define GC_USB_DIEPINT2_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT2_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT2_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT2_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT2_TXFEMP_OFFSET            0x948
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET       0x948
-#define GC_USB_DIEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BNAINTR_OFFSET           0x948
-#define GC_USB_DIEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET         0x948
-#define GC_USB_DIEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BBLEERR_OFFSET           0x948
-#define GC_USB_DIEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET         0x948
-#define GC_USB_DIEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET        0x948
-#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET         0x950
-#define GC_USB_DIEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET           0x950
-#define GC_USB_DIEPTSIZ2_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ2_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ2_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ2_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ2_MC_OFFSET               0x950
-#define GC_USB_DIEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA2_DMAADDR_OFFSET           0x954
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET   0x958
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET    0x95c
-#define GC_USB_DIEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL3_MPS_OFFSET               0x960
-#define GC_USB_DIEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_USBACTEP_OFFSET          0x960
-#define GC_USB_DIEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_DPID_OFFSET              0x960
-#define GC_USB_DIEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_NAKSTS_OFFSET            0x960
-#define GC_USB_DIEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_EPTYPE_OFFSET            0x960
-#define GC_USB_DIEPCTL3_STALL_LSB                0x15
-#define GC_USB_DIEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_STALL_OFFSET             0x960
-#define GC_USB_DIEPCTL3_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL3_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL3_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_TXFNUM_OFFSET            0x960
-#define GC_USB_DIEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_CNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_SNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD0PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD1PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPDIS_OFFSET             0x960
-#define GC_USB_DIEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPENA_OFFSET             0x960
-#define GC_USB_DIEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET         0x968
-#define GC_USB_DIEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT3_EPDISBLD_OFFSET          0x968
-#define GC_USB_DIEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT3_AHBERR_OFFSET            0x968
-#define GC_USB_DIEPINT3_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT3_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT3_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT3_TIMEOUT_OFFSET           0x968
-#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET       0x968
-#define GC_USB_DIEPINT3_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT3_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET        0x968
-#define GC_USB_DIEPINT3_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT3_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET        0x968
-#define GC_USB_DIEPINT3_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT3_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT3_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT3_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT3_TXFEMP_OFFSET            0x968
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET       0x968
-#define GC_USB_DIEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BNAINTR_OFFSET           0x968
-#define GC_USB_DIEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET         0x968
-#define GC_USB_DIEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BBLEERR_OFFSET           0x968
-#define GC_USB_DIEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET         0x968
-#define GC_USB_DIEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET        0x968
-#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET         0x970
-#define GC_USB_DIEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET           0x970
-#define GC_USB_DIEPTSIZ3_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ3_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ3_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ3_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ3_MC_OFFSET               0x970
-#define GC_USB_DIEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA3_DMAADDR_OFFSET           0x974
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET   0x978
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET    0x97c
-#define GC_USB_DIEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL4_MPS_OFFSET               0x980
-#define GC_USB_DIEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_USBACTEP_OFFSET          0x980
-#define GC_USB_DIEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_DPID_OFFSET              0x980
-#define GC_USB_DIEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_NAKSTS_OFFSET            0x980
-#define GC_USB_DIEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_EPTYPE_OFFSET            0x980
-#define GC_USB_DIEPCTL4_STALL_LSB                0x15
-#define GC_USB_DIEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_STALL_OFFSET             0x980
-#define GC_USB_DIEPCTL4_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL4_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL4_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_TXFNUM_OFFSET            0x980
-#define GC_USB_DIEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_CNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_SNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD0PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD1PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPDIS_OFFSET             0x980
-#define GC_USB_DIEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPENA_OFFSET             0x980
-#define GC_USB_DIEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET         0x988
-#define GC_USB_DIEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT4_EPDISBLD_OFFSET          0x988
-#define GC_USB_DIEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT4_AHBERR_OFFSET            0x988
-#define GC_USB_DIEPINT4_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT4_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT4_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT4_TIMEOUT_OFFSET           0x988
-#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET       0x988
-#define GC_USB_DIEPINT4_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT4_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET        0x988
-#define GC_USB_DIEPINT4_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT4_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET        0x988
-#define GC_USB_DIEPINT4_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT4_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT4_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT4_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT4_TXFEMP_OFFSET            0x988
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET       0x988
-#define GC_USB_DIEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BNAINTR_OFFSET           0x988
-#define GC_USB_DIEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET         0x988
-#define GC_USB_DIEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BBLEERR_OFFSET           0x988
-#define GC_USB_DIEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET         0x988
-#define GC_USB_DIEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET        0x988
-#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET         0x990
-#define GC_USB_DIEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET           0x990
-#define GC_USB_DIEPTSIZ4_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ4_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ4_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ4_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ4_MC_OFFSET               0x990
-#define GC_USB_DIEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA4_DMAADDR_OFFSET           0x994
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET   0x998
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET    0x99c
-#define GC_USB_DIEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL5_MPS_OFFSET               0x9a0
-#define GC_USB_DIEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_USBACTEP_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_DPID_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_NAKSTS_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_EPTYPE_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_STALL_LSB                0x15
-#define GC_USB_DIEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_STALL_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL5_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL5_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_TXFNUM_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_CNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_SNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD0PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD1PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPDIS_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPENA_OFFSET             0x9a0
-#define GC_USB_DIEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT5_EPDISBLD_OFFSET          0x9a8
-#define GC_USB_DIEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT5_AHBERR_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT5_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT5_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT5_TIMEOUT_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT5_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT5_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT5_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT5_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT5_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT5_TXFEMP_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BNAINTR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BBLEERR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET        0x9a8
-#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET         0x9b0
-#define GC_USB_DIEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET           0x9b0
-#define GC_USB_DIEPTSIZ5_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ5_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ5_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ5_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ5_MC_OFFSET               0x9b0
-#define GC_USB_DIEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA5_DMAADDR_OFFSET           0x9b4
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET   0x9b8
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET    0x9bc
-#define GC_USB_DIEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL6_MPS_OFFSET               0x9c0
-#define GC_USB_DIEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_USBACTEP_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_DPID_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_NAKSTS_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_EPTYPE_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_STALL_LSB                0x15
-#define GC_USB_DIEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_STALL_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL6_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL6_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_TXFNUM_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_CNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_SNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD0PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD1PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPDIS_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPENA_OFFSET             0x9c0
-#define GC_USB_DIEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT6_EPDISBLD_OFFSET          0x9c8
-#define GC_USB_DIEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT6_AHBERR_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT6_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT6_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT6_TIMEOUT_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT6_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT6_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT6_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT6_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT6_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT6_TXFEMP_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BNAINTR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BBLEERR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET        0x9c8
-#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET         0x9d0
-#define GC_USB_DIEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET           0x9d0
-#define GC_USB_DIEPTSIZ6_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ6_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ6_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ6_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ6_MC_OFFSET               0x9d0
-#define GC_USB_DIEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA6_DMAADDR_OFFSET           0x9d4
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET   0x9d8
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET    0x9dc
-#define GC_USB_DIEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL7_MPS_OFFSET               0x9e0
-#define GC_USB_DIEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_USBACTEP_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_DPID_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_NAKSTS_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_EPTYPE_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_STALL_LSB                0x15
-#define GC_USB_DIEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_STALL_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL7_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL7_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_TXFNUM_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_CNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_SNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD0PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD1PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPDIS_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPENA_OFFSET             0x9e0
-#define GC_USB_DIEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT7_EPDISBLD_OFFSET          0x9e8
-#define GC_USB_DIEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT7_AHBERR_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT7_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT7_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT7_TIMEOUT_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT7_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT7_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT7_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT7_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT7_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT7_TXFEMP_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BNAINTR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BBLEERR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET        0x9e8
-#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET         0x9f0
-#define GC_USB_DIEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET           0x9f0
-#define GC_USB_DIEPTSIZ7_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ7_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ7_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ7_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ7_MC_OFFSET               0x9f0
-#define GC_USB_DIEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA7_DMAADDR_OFFSET           0x9f4
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET   0x9f8
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET    0x9fc
-#define GC_USB_DIEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL8_MPS_OFFSET               0xa00
-#define GC_USB_DIEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_USBACTEP_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_DPID_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_NAKSTS_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_EPTYPE_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_STALL_LSB                0x15
-#define GC_USB_DIEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_STALL_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL8_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL8_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_TXFNUM_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_CNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_SNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD0PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD1PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPDIS_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPENA_OFFSET             0xa00
-#define GC_USB_DIEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET         0xa08
-#define GC_USB_DIEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT8_EPDISBLD_OFFSET          0xa08
-#define GC_USB_DIEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT8_AHBERR_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT8_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT8_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT8_TIMEOUT_OFFSET           0xa08
-#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET       0xa08
-#define GC_USB_DIEPINT8_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT8_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET        0xa08
-#define GC_USB_DIEPINT8_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT8_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET        0xa08
-#define GC_USB_DIEPINT8_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT8_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT8_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT8_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT8_TXFEMP_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET       0xa08
-#define GC_USB_DIEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BNAINTR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET         0xa08
-#define GC_USB_DIEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BBLEERR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET         0xa08
-#define GC_USB_DIEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET        0xa08
-#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET         0xa10
-#define GC_USB_DIEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET           0xa10
-#define GC_USB_DIEPTSIZ8_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ8_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ8_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ8_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ8_MC_OFFSET               0xa10
-#define GC_USB_DIEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA8_DMAADDR_OFFSET           0xa14
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET   0xa18
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET    0xa1c
-#define GC_USB_DIEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL9_MPS_OFFSET               0xa20
-#define GC_USB_DIEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_USBACTEP_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_DPID_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_NAKSTS_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_EPTYPE_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_STALL_LSB                0x15
-#define GC_USB_DIEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_STALL_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL9_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL9_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_TXFNUM_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_CNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_SNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD0PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD1PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPDIS_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPENA_OFFSET             0xa20
-#define GC_USB_DIEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET         0xa28
-#define GC_USB_DIEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT9_EPDISBLD_OFFSET          0xa28
-#define GC_USB_DIEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT9_AHBERR_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT9_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT9_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT9_TIMEOUT_OFFSET           0xa28
-#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET       0xa28
-#define GC_USB_DIEPINT9_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT9_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET        0xa28
-#define GC_USB_DIEPINT9_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT9_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET        0xa28
-#define GC_USB_DIEPINT9_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT9_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT9_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT9_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT9_TXFEMP_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET       0xa28
-#define GC_USB_DIEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BNAINTR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET         0xa28
-#define GC_USB_DIEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BBLEERR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET         0xa28
-#define GC_USB_DIEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET        0xa28
-#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET         0xa30
-#define GC_USB_DIEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET           0xa30
-#define GC_USB_DIEPTSIZ9_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ9_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ9_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ9_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ9_MC_OFFSET               0xa30
-#define GC_USB_DIEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA9_DMAADDR_OFFSET           0xa34
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET   0xa38
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET    0xa3c
-#define GC_USB_DIEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL10_MPS_OFFSET              0xa40
-#define GC_USB_DIEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_USBACTEP_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_DPID_LSB                0x10
-#define GC_USB_DIEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_DPID_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_NAKSTS_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_EPTYPE_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_STALL_LSB               0x15
-#define GC_USB_DIEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_STALL_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL10_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL10_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_TXFNUM_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_CNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_SNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD0PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD1PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPDIS_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPENA_OFFSET            0xa40
-#define GC_USB_DIEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET        0xa48
-#define GC_USB_DIEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT10_EPDISBLD_OFFSET         0xa48
-#define GC_USB_DIEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT10_AHBERR_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT10_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT10_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT10_TIMEOUT_OFFSET          0xa48
-#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET      0xa48
-#define GC_USB_DIEPINT10_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT10_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET       0xa48
-#define GC_USB_DIEPINT10_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT10_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET       0xa48
-#define GC_USB_DIEPINT10_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT10_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT10_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT10_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT10_TXFEMP_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET      0xa48
-#define GC_USB_DIEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BNAINTR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET        0xa48
-#define GC_USB_DIEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BBLEERR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET        0xa48
-#define GC_USB_DIEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET       0xa48
-#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET        0xa50
-#define GC_USB_DIEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET          0xa50
-#define GC_USB_DIEPTSIZ10_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ10_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ10_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ10_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ10_MC_OFFSET              0xa50
-#define GC_USB_DIEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA10_DMAADDR_OFFSET          0xa54
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET  0xa58
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET   0xa5c
-#define GC_USB_DIEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL11_MPS_OFFSET              0xa60
-#define GC_USB_DIEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_USBACTEP_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_DPID_LSB                0x10
-#define GC_USB_DIEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_DPID_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_NAKSTS_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_EPTYPE_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_STALL_LSB               0x15
-#define GC_USB_DIEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_STALL_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL11_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL11_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_TXFNUM_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_CNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_SNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD0PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD1PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPDIS_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPENA_OFFSET            0xa60
-#define GC_USB_DIEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET        0xa68
-#define GC_USB_DIEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT11_EPDISBLD_OFFSET         0xa68
-#define GC_USB_DIEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT11_AHBERR_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT11_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT11_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT11_TIMEOUT_OFFSET          0xa68
-#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET      0xa68
-#define GC_USB_DIEPINT11_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT11_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET       0xa68
-#define GC_USB_DIEPINT11_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT11_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET       0xa68
-#define GC_USB_DIEPINT11_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT11_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT11_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT11_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT11_TXFEMP_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET      0xa68
-#define GC_USB_DIEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BNAINTR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET        0xa68
-#define GC_USB_DIEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BBLEERR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET        0xa68
-#define GC_USB_DIEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET       0xa68
-#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET        0xa70
-#define GC_USB_DIEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET          0xa70
-#define GC_USB_DIEPTSIZ11_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ11_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ11_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ11_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ11_MC_OFFSET              0xa70
-#define GC_USB_DIEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA11_DMAADDR_OFFSET          0xa74
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET  0xa78
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET   0xa7c
-#define GC_USB_DIEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL12_MPS_OFFSET              0xa80
-#define GC_USB_DIEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_USBACTEP_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_DPID_LSB                0x10
-#define GC_USB_DIEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_DPID_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_NAKSTS_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_EPTYPE_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_STALL_LSB               0x15
-#define GC_USB_DIEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_STALL_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL12_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL12_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_TXFNUM_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_CNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_SNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD0PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD1PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPDIS_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPENA_OFFSET            0xa80
-#define GC_USB_DIEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET        0xa88
-#define GC_USB_DIEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT12_EPDISBLD_OFFSET         0xa88
-#define GC_USB_DIEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT12_AHBERR_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT12_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT12_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT12_TIMEOUT_OFFSET          0xa88
-#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET      0xa88
-#define GC_USB_DIEPINT12_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT12_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET       0xa88
-#define GC_USB_DIEPINT12_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT12_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET       0xa88
-#define GC_USB_DIEPINT12_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT12_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT12_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT12_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT12_TXFEMP_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET      0xa88
-#define GC_USB_DIEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BNAINTR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET        0xa88
-#define GC_USB_DIEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BBLEERR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET        0xa88
-#define GC_USB_DIEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET       0xa88
-#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET        0xa90
-#define GC_USB_DIEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET          0xa90
-#define GC_USB_DIEPTSIZ12_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ12_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ12_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ12_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ12_MC_OFFSET              0xa90
-#define GC_USB_DIEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA12_DMAADDR_OFFSET          0xa94
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET  0xa98
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET   0xa9c
-#define GC_USB_DIEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL13_MPS_OFFSET              0xaa0
-#define GC_USB_DIEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_USBACTEP_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_DPID_LSB                0x10
-#define GC_USB_DIEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_DPID_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_NAKSTS_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_EPTYPE_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_STALL_LSB               0x15
-#define GC_USB_DIEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_STALL_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL13_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL13_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_TXFNUM_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_CNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_SNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD0PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD1PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPDIS_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPENA_OFFSET            0xaa0
-#define GC_USB_DIEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT13_EPDISBLD_OFFSET         0xaa8
-#define GC_USB_DIEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT13_AHBERR_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT13_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT13_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT13_TIMEOUT_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT13_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT13_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT13_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT13_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT13_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT13_TXFEMP_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BNAINTR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BBLEERR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET       0xaa8
-#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET        0xab0
-#define GC_USB_DIEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET          0xab0
-#define GC_USB_DIEPTSIZ13_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ13_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ13_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ13_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ13_MC_OFFSET              0xab0
-#define GC_USB_DIEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA13_DMAADDR_OFFSET          0xab4
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET  0xab8
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET   0xabc
-#define GC_USB_DIEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL14_MPS_OFFSET              0xac0
-#define GC_USB_DIEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_USBACTEP_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_DPID_LSB                0x10
-#define GC_USB_DIEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_DPID_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_NAKSTS_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_EPTYPE_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_STALL_LSB               0x15
-#define GC_USB_DIEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_STALL_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL14_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL14_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_TXFNUM_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_CNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_SNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD0PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD1PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPDIS_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPENA_OFFSET            0xac0
-#define GC_USB_DIEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET        0xac8
-#define GC_USB_DIEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT14_EPDISBLD_OFFSET         0xac8
-#define GC_USB_DIEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT14_AHBERR_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT14_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT14_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT14_TIMEOUT_OFFSET          0xac8
-#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET      0xac8
-#define GC_USB_DIEPINT14_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT14_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET       0xac8
-#define GC_USB_DIEPINT14_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT14_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET       0xac8
-#define GC_USB_DIEPINT14_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT14_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT14_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT14_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT14_TXFEMP_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET      0xac8
-#define GC_USB_DIEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BNAINTR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET        0xac8
-#define GC_USB_DIEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BBLEERR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET        0xac8
-#define GC_USB_DIEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET       0xac8
-#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET        0xad0
-#define GC_USB_DIEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET          0xad0
-#define GC_USB_DIEPTSIZ14_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ14_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ14_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ14_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ14_MC_OFFSET              0xad0
-#define GC_USB_DIEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA14_DMAADDR_OFFSET          0xad4
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET  0xad8
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET   0xadc
-#define GC_USB_DIEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL15_MPS_OFFSET              0xae0
-#define GC_USB_DIEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_USBACTEP_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_DPID_LSB                0x10
-#define GC_USB_DIEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_DPID_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_NAKSTS_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_EPTYPE_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_STALL_LSB               0x15
-#define GC_USB_DIEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_STALL_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL15_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL15_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_TXFNUM_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_CNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_SNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD0PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD1PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPDIS_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPENA_OFFSET            0xae0
-#define GC_USB_DIEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET        0xae8
-#define GC_USB_DIEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT15_EPDISBLD_OFFSET         0xae8
-#define GC_USB_DIEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT15_AHBERR_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT15_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT15_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT15_TIMEOUT_OFFSET          0xae8
-#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET      0xae8
-#define GC_USB_DIEPINT15_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT15_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET       0xae8
-#define GC_USB_DIEPINT15_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT15_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET       0xae8
-#define GC_USB_DIEPINT15_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT15_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT15_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT15_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT15_TXFEMP_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET      0xae8
-#define GC_USB_DIEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BNAINTR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET        0xae8
-#define GC_USB_DIEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BBLEERR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET        0xae8
-#define GC_USB_DIEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET       0xae8
-#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET        0xaf0
-#define GC_USB_DIEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET          0xaf0
-#define GC_USB_DIEPTSIZ15_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ15_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ15_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ15_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ15_MC_OFFSET              0xaf0
-#define GC_USB_DIEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA15_DMAADDR_OFFSET          0xaf4
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET  0xaf8
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET   0xafc
-#define GC_USB_DOEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DOEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DOEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_MPS_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL0_USBACTEP_OFFSET          0xb00
-#define GC_USB_DOEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_NAKSTS_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_EPTYPE_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL0_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL0_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL0_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_SNP_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_STALL_LSB                0x15
-#define GC_USB_DOEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_STALL_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_CNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_SNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPDIS_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPENA_OFFSET             0xb00
-#define GC_USB_DOEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET         0xb08
-#define GC_USB_DOEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT0_EPDISBLD_OFFSET          0xb08
-#define GC_USB_DOEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT0_AHBERR_OFFSET            0xb08
-#define GC_USB_DOEPINT0_SETUP_LSB                0x3
-#define GC_USB_DOEPINT0_SETUP_MASK               0x8
-#define GC_USB_DOEPINT0_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT0_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT0_SETUP_OFFSET             0xb08
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET       0xb08
-#define GC_USB_DOEPINT0_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT0_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET       0xb08
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET    0xb08
-#define GC_USB_DOEPINT0_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT0_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT0_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BNAINTR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BBLEERR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET         0xb08
-#define GC_USB_DOEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET        0xb08
-#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET       0xb08
-#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET         0xb10
-#define GC_USB_DOEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ0_PKTCNT_MASK             0x80000
-#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE             0x1
-#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET           0xb10
-#define GC_USB_DOEPTSIZ0_SUPCNT_LSB              0x1d
-#define GC_USB_DOEPTSIZ0_SUPCNT_MASK             0x60000000
-#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE             0x2
-#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET           0xb10
-#define GC_USB_DOEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA0_DMAADDR_OFFSET           0xb14
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET    0xb1c
-#define GC_USB_DOEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_MPS_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_USBACTEP_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_DPID_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_NAKSTS_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_EPTYPE_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL1_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL1_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL1_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_SNP_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_STALL_LSB                0x15
-#define GC_USB_DOEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_STALL_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_CNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_SNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD0PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD1PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPDIS_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPENA_OFFSET             0xb20
-#define GC_USB_DOEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET         0xb28
-#define GC_USB_DOEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT1_EPDISBLD_OFFSET          0xb28
-#define GC_USB_DOEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT1_AHBERR_OFFSET            0xb28
-#define GC_USB_DOEPINT1_SETUP_LSB                0x3
-#define GC_USB_DOEPINT1_SETUP_MASK               0x8
-#define GC_USB_DOEPINT1_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT1_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT1_SETUP_OFFSET             0xb28
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET       0xb28
-#define GC_USB_DOEPINT1_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT1_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET       0xb28
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET    0xb28
-#define GC_USB_DOEPINT1_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT1_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT1_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BNAINTR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BBLEERR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET         0xb28
-#define GC_USB_DOEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET        0xb28
-#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET       0xb28
-#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET         0xb30
-#define GC_USB_DOEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET           0xb30
-#define GC_USB_DOEPTSIZ1_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ1_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ1_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET           0xb30
-#define GC_USB_DOEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA1_DMAADDR_OFFSET           0xb34
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET    0xb3c
-#define GC_USB_DOEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_MPS_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_USBACTEP_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_DPID_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_NAKSTS_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_EPTYPE_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL2_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL2_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL2_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_SNP_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_STALL_LSB                0x15
-#define GC_USB_DOEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_STALL_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_CNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_SNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD0PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD1PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPDIS_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPENA_OFFSET             0xb40
-#define GC_USB_DOEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET         0xb48
-#define GC_USB_DOEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT2_EPDISBLD_OFFSET          0xb48
-#define GC_USB_DOEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT2_AHBERR_OFFSET            0xb48
-#define GC_USB_DOEPINT2_SETUP_LSB                0x3
-#define GC_USB_DOEPINT2_SETUP_MASK               0x8
-#define GC_USB_DOEPINT2_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT2_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT2_SETUP_OFFSET             0xb48
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET       0xb48
-#define GC_USB_DOEPINT2_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT2_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET       0xb48
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET    0xb48
-#define GC_USB_DOEPINT2_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT2_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT2_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BNAINTR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BBLEERR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET         0xb48
-#define GC_USB_DOEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET        0xb48
-#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET       0xb48
-#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET         0xb50
-#define GC_USB_DOEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET           0xb50
-#define GC_USB_DOEPTSIZ2_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ2_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ2_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET           0xb50
-#define GC_USB_DOEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA2_DMAADDR_OFFSET           0xb54
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET    0xb5c
-#define GC_USB_DOEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_MPS_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_USBACTEP_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_DPID_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_NAKSTS_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_EPTYPE_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL3_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL3_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL3_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_SNP_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_STALL_LSB                0x15
-#define GC_USB_DOEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_STALL_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_CNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_SNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD0PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD1PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPDIS_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPENA_OFFSET             0xb60
-#define GC_USB_DOEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET         0xb68
-#define GC_USB_DOEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT3_EPDISBLD_OFFSET          0xb68
-#define GC_USB_DOEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT3_AHBERR_OFFSET            0xb68
-#define GC_USB_DOEPINT3_SETUP_LSB                0x3
-#define GC_USB_DOEPINT3_SETUP_MASK               0x8
-#define GC_USB_DOEPINT3_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT3_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT3_SETUP_OFFSET             0xb68
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET       0xb68
-#define GC_USB_DOEPINT3_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT3_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET       0xb68
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET    0xb68
-#define GC_USB_DOEPINT3_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT3_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT3_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BNAINTR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BBLEERR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET         0xb68
-#define GC_USB_DOEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET        0xb68
-#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET       0xb68
-#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET         0xb70
-#define GC_USB_DOEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET           0xb70
-#define GC_USB_DOEPTSIZ3_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ3_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ3_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET           0xb70
-#define GC_USB_DOEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA3_DMAADDR_OFFSET           0xb74
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET    0xb7c
-#define GC_USB_DOEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_MPS_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_USBACTEP_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_DPID_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_NAKSTS_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_EPTYPE_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL4_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL4_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL4_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_SNP_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_STALL_LSB                0x15
-#define GC_USB_DOEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_STALL_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_CNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_SNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD0PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD1PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPDIS_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPENA_OFFSET             0xb80
-#define GC_USB_DOEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET         0xb88
-#define GC_USB_DOEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT4_EPDISBLD_OFFSET          0xb88
-#define GC_USB_DOEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT4_AHBERR_OFFSET            0xb88
-#define GC_USB_DOEPINT4_SETUP_LSB                0x3
-#define GC_USB_DOEPINT4_SETUP_MASK               0x8
-#define GC_USB_DOEPINT4_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT4_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT4_SETUP_OFFSET             0xb88
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET       0xb88
-#define GC_USB_DOEPINT4_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT4_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET       0xb88
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET    0xb88
-#define GC_USB_DOEPINT4_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT4_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT4_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BNAINTR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BBLEERR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET         0xb88
-#define GC_USB_DOEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET        0xb88
-#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET       0xb88
-#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET         0xb90
-#define GC_USB_DOEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET           0xb90
-#define GC_USB_DOEPTSIZ4_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ4_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ4_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET           0xb90
-#define GC_USB_DOEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA4_DMAADDR_OFFSET           0xb94
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET    0xb9c
-#define GC_USB_DOEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_MPS_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_USBACTEP_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_DPID_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_NAKSTS_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_EPTYPE_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL5_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL5_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL5_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_SNP_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_STALL_LSB                0x15
-#define GC_USB_DOEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_STALL_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_CNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_SNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD0PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD1PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPDIS_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPENA_OFFSET             0xba0
-#define GC_USB_DOEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET         0xba8
-#define GC_USB_DOEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT5_EPDISBLD_OFFSET          0xba8
-#define GC_USB_DOEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT5_AHBERR_OFFSET            0xba8
-#define GC_USB_DOEPINT5_SETUP_LSB                0x3
-#define GC_USB_DOEPINT5_SETUP_MASK               0x8
-#define GC_USB_DOEPINT5_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT5_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT5_SETUP_OFFSET             0xba8
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET       0xba8
-#define GC_USB_DOEPINT5_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT5_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET       0xba8
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET    0xba8
-#define GC_USB_DOEPINT5_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT5_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT5_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BNAINTR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BBLEERR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET         0xba8
-#define GC_USB_DOEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET        0xba8
-#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET       0xba8
-#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET         0xbb0
-#define GC_USB_DOEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET           0xbb0
-#define GC_USB_DOEPTSIZ5_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ5_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ5_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET           0xbb0
-#define GC_USB_DOEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA5_DMAADDR_OFFSET           0xbb4
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET    0xbbc
-#define GC_USB_DOEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_MPS_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_USBACTEP_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_DPID_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_NAKSTS_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_EPTYPE_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL6_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL6_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL6_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_SNP_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_STALL_LSB                0x15
-#define GC_USB_DOEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_STALL_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_CNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_SNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD0PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD1PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPDIS_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPENA_OFFSET             0xbc0
-#define GC_USB_DOEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT6_EPDISBLD_OFFSET          0xbc8
-#define GC_USB_DOEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT6_AHBERR_OFFSET            0xbc8
-#define GC_USB_DOEPINT6_SETUP_LSB                0x3
-#define GC_USB_DOEPINT6_SETUP_MASK               0x8
-#define GC_USB_DOEPINT6_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT6_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT6_SETUP_OFFSET             0xbc8
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT6_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET    0xbc8
-#define GC_USB_DOEPINT6_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT6_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT6_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BNAINTR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BBLEERR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET        0xbc8
-#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET       0xbc8
-#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET         0xbd0
-#define GC_USB_DOEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET           0xbd0
-#define GC_USB_DOEPTSIZ6_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ6_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ6_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET           0xbd0
-#define GC_USB_DOEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA6_DMAADDR_OFFSET           0xbd4
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET    0xbdc
-#define GC_USB_DOEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_MPS_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_USBACTEP_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_DPID_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_NAKSTS_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_EPTYPE_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL7_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL7_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL7_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_SNP_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_STALL_LSB                0x15
-#define GC_USB_DOEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_STALL_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_CNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_SNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD0PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD1PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPDIS_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPENA_OFFSET             0xbe0
-#define GC_USB_DOEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT7_EPDISBLD_OFFSET          0xbe8
-#define GC_USB_DOEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT7_AHBERR_OFFSET            0xbe8
-#define GC_USB_DOEPINT7_SETUP_LSB                0x3
-#define GC_USB_DOEPINT7_SETUP_MASK               0x8
-#define GC_USB_DOEPINT7_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT7_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT7_SETUP_OFFSET             0xbe8
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT7_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET    0xbe8
-#define GC_USB_DOEPINT7_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT7_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT7_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BNAINTR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BBLEERR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET        0xbe8
-#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET       0xbe8
-#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET         0xbf0
-#define GC_USB_DOEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET           0xbf0
-#define GC_USB_DOEPTSIZ7_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ7_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ7_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET           0xbf0
-#define GC_USB_DOEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA7_DMAADDR_OFFSET           0xbf4
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET    0xbfc
-#define GC_USB_DOEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_MPS_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_USBACTEP_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_DPID_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_NAKSTS_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_EPTYPE_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL8_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL8_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL8_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_SNP_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_STALL_LSB                0x15
-#define GC_USB_DOEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_STALL_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_CNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_SNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD0PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD1PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPDIS_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPENA_OFFSET             0xc00
-#define GC_USB_DOEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET         0xc08
-#define GC_USB_DOEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT8_EPDISBLD_OFFSET          0xc08
-#define GC_USB_DOEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT8_AHBERR_OFFSET            0xc08
-#define GC_USB_DOEPINT8_SETUP_LSB                0x3
-#define GC_USB_DOEPINT8_SETUP_MASK               0x8
-#define GC_USB_DOEPINT8_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT8_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT8_SETUP_OFFSET             0xc08
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET       0xc08
-#define GC_USB_DOEPINT8_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT8_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET       0xc08
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET    0xc08
-#define GC_USB_DOEPINT8_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT8_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT8_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BNAINTR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BBLEERR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET         0xc08
-#define GC_USB_DOEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET        0xc08
-#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET       0xc08
-#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET         0xc10
-#define GC_USB_DOEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET           0xc10
-#define GC_USB_DOEPTSIZ8_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ8_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ8_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET           0xc10
-#define GC_USB_DOEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA8_DMAADDR_OFFSET           0xc14
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET    0xc1c
-#define GC_USB_DOEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_MPS_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_USBACTEP_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_DPID_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_NAKSTS_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_EPTYPE_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL9_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL9_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL9_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_SNP_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_STALL_LSB                0x15
-#define GC_USB_DOEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_STALL_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_CNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_SNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD0PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD1PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPDIS_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPENA_OFFSET             0xc20
-#define GC_USB_DOEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET         0xc28
-#define GC_USB_DOEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT9_EPDISBLD_OFFSET          0xc28
-#define GC_USB_DOEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT9_AHBERR_OFFSET            0xc28
-#define GC_USB_DOEPINT9_SETUP_LSB                0x3
-#define GC_USB_DOEPINT9_SETUP_MASK               0x8
-#define GC_USB_DOEPINT9_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT9_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT9_SETUP_OFFSET             0xc28
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET       0xc28
-#define GC_USB_DOEPINT9_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT9_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET       0xc28
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET    0xc28
-#define GC_USB_DOEPINT9_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT9_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT9_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BNAINTR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BBLEERR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET         0xc28
-#define GC_USB_DOEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET        0xc28
-#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET       0xc28
-#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET         0xc30
-#define GC_USB_DOEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET           0xc30
-#define GC_USB_DOEPTSIZ9_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ9_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ9_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET           0xc30
-#define GC_USB_DOEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA9_DMAADDR_OFFSET           0xc34
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET    0xc3c
-#define GC_USB_DOEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_MPS_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_USBACTEP_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_DPID_LSB                0x10
-#define GC_USB_DOEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_DPID_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_NAKSTS_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_EPTYPE_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL10_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL10_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL10_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_SNP_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_STALL_LSB               0x15
-#define GC_USB_DOEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_STALL_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_CNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_SNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD0PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD1PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPDIS_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPENA_OFFSET            0xc40
-#define GC_USB_DOEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET        0xc48
-#define GC_USB_DOEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT10_EPDISBLD_OFFSET         0xc48
-#define GC_USB_DOEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT10_AHBERR_OFFSET           0xc48
-#define GC_USB_DOEPINT10_SETUP_LSB               0x3
-#define GC_USB_DOEPINT10_SETUP_MASK              0x8
-#define GC_USB_DOEPINT10_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT10_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT10_SETUP_OFFSET            0xc48
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET      0xc48
-#define GC_USB_DOEPINT10_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT10_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET      0xc48
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET   0xc48
-#define GC_USB_DOEPINT10_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT10_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT10_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BNAINTR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BBLEERR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET        0xc48
-#define GC_USB_DOEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET       0xc48
-#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET      0xc48
-#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET        0xc50
-#define GC_USB_DOEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET          0xc50
-#define GC_USB_DOEPTSIZ10_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ10_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ10_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET          0xc50
-#define GC_USB_DOEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA10_DMAADDR_OFFSET          0xc54
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET   0xc5c
-#define GC_USB_DOEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_MPS_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_USBACTEP_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_DPID_LSB                0x10
-#define GC_USB_DOEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_DPID_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_NAKSTS_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_EPTYPE_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL11_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL11_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL11_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_SNP_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_STALL_LSB               0x15
-#define GC_USB_DOEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_STALL_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_CNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_SNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD0PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD1PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPDIS_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPENA_OFFSET            0xc60
-#define GC_USB_DOEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET        0xc68
-#define GC_USB_DOEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT11_EPDISBLD_OFFSET         0xc68
-#define GC_USB_DOEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT11_AHBERR_OFFSET           0xc68
-#define GC_USB_DOEPINT11_SETUP_LSB               0x3
-#define GC_USB_DOEPINT11_SETUP_MASK              0x8
-#define GC_USB_DOEPINT11_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT11_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT11_SETUP_OFFSET            0xc68
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET      0xc68
-#define GC_USB_DOEPINT11_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT11_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET      0xc68
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET   0xc68
-#define GC_USB_DOEPINT11_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT11_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT11_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BNAINTR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BBLEERR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET        0xc68
-#define GC_USB_DOEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET       0xc68
-#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET      0xc68
-#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET        0xc70
-#define GC_USB_DOEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET          0xc70
-#define GC_USB_DOEPTSIZ11_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ11_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ11_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET          0xc70
-#define GC_USB_DOEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA11_DMAADDR_OFFSET          0xc74
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET   0xc7c
-#define GC_USB_DOEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_MPS_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_USBACTEP_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_DPID_LSB                0x10
-#define GC_USB_DOEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_DPID_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_NAKSTS_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_EPTYPE_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL12_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL12_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL12_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_SNP_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_STALL_LSB               0x15
-#define GC_USB_DOEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_STALL_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_CNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_SNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD0PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD1PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPDIS_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPENA_OFFSET            0xc80
-#define GC_USB_DOEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET        0xc88
-#define GC_USB_DOEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT12_EPDISBLD_OFFSET         0xc88
-#define GC_USB_DOEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT12_AHBERR_OFFSET           0xc88
-#define GC_USB_DOEPINT12_SETUP_LSB               0x3
-#define GC_USB_DOEPINT12_SETUP_MASK              0x8
-#define GC_USB_DOEPINT12_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT12_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT12_SETUP_OFFSET            0xc88
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET      0xc88
-#define GC_USB_DOEPINT12_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT12_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET      0xc88
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET   0xc88
-#define GC_USB_DOEPINT12_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT12_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT12_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BNAINTR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BBLEERR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET        0xc88
-#define GC_USB_DOEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET       0xc88
-#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET      0xc88
-#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET        0xc90
-#define GC_USB_DOEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET          0xc90
-#define GC_USB_DOEPTSIZ12_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ12_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ12_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET          0xc90
-#define GC_USB_DOEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA12_DMAADDR_OFFSET          0xc94
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET   0xc9c
-#define GC_USB_DOEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_MPS_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_USBACTEP_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_DPID_LSB                0x10
-#define GC_USB_DOEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_DPID_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_NAKSTS_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_EPTYPE_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL13_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL13_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL13_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_SNP_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_STALL_LSB               0x15
-#define GC_USB_DOEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_STALL_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_CNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_SNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD0PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD1PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPDIS_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPENA_OFFSET            0xca0
-#define GC_USB_DOEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET        0xca8
-#define GC_USB_DOEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT13_EPDISBLD_OFFSET         0xca8
-#define GC_USB_DOEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT13_AHBERR_OFFSET           0xca8
-#define GC_USB_DOEPINT13_SETUP_LSB               0x3
-#define GC_USB_DOEPINT13_SETUP_MASK              0x8
-#define GC_USB_DOEPINT13_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT13_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT13_SETUP_OFFSET            0xca8
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET      0xca8
-#define GC_USB_DOEPINT13_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT13_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET      0xca8
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET   0xca8
-#define GC_USB_DOEPINT13_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT13_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT13_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BNAINTR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BBLEERR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET        0xca8
-#define GC_USB_DOEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET       0xca8
-#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET      0xca8
-#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET        0xcb0
-#define GC_USB_DOEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET          0xcb0
-#define GC_USB_DOEPTSIZ13_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ13_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ13_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET          0xcb0
-#define GC_USB_DOEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA13_DMAADDR_OFFSET          0xcb4
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET   0xcbc
-#define GC_USB_DOEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_MPS_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_USBACTEP_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_DPID_LSB                0x10
-#define GC_USB_DOEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_DPID_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_NAKSTS_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_EPTYPE_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL14_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL14_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL14_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_SNP_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_STALL_LSB               0x15
-#define GC_USB_DOEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_STALL_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_CNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_SNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD0PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD1PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPDIS_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPENA_OFFSET            0xcc0
-#define GC_USB_DOEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT14_EPDISBLD_OFFSET         0xcc8
-#define GC_USB_DOEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT14_AHBERR_OFFSET           0xcc8
-#define GC_USB_DOEPINT14_SETUP_LSB               0x3
-#define GC_USB_DOEPINT14_SETUP_MASK              0x8
-#define GC_USB_DOEPINT14_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT14_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT14_SETUP_OFFSET            0xcc8
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT14_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET   0xcc8
-#define GC_USB_DOEPINT14_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT14_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT14_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BNAINTR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BBLEERR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET       0xcc8
-#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET      0xcc8
-#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET        0xcd0
-#define GC_USB_DOEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET          0xcd0
-#define GC_USB_DOEPTSIZ14_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ14_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ14_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET          0xcd0
-#define GC_USB_DOEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA14_DMAADDR_OFFSET          0xcd4
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET   0xcdc
-#define GC_USB_DOEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_MPS_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_USBACTEP_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_DPID_LSB                0x10
-#define GC_USB_DOEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_DPID_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_NAKSTS_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_EPTYPE_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL15_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL15_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL15_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_SNP_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_STALL_LSB               0x15
-#define GC_USB_DOEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_STALL_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_CNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_SNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD0PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD1PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPDIS_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPENA_OFFSET            0xce0
-#define GC_USB_DOEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET        0xce8
-#define GC_USB_DOEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT15_EPDISBLD_OFFSET         0xce8
-#define GC_USB_DOEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT15_AHBERR_OFFSET           0xce8
-#define GC_USB_DOEPINT15_SETUP_LSB               0x3
-#define GC_USB_DOEPINT15_SETUP_MASK              0x8
-#define GC_USB_DOEPINT15_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT15_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT15_SETUP_OFFSET            0xce8
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET      0xce8
-#define GC_USB_DOEPINT15_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT15_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET      0xce8
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET   0xce8
-#define GC_USB_DOEPINT15_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT15_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT15_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BNAINTR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BBLEERR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET        0xce8
-#define GC_USB_DOEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET       0xce8
-#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET      0xce8
-#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET        0xcf0
-#define GC_USB_DOEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET          0xcf0
-#define GC_USB_DOEPTSIZ15_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ15_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ15_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET          0xcf0
-#define GC_USB_DOEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA15_DMAADDR_OFFSET          0xcf4
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET   0xcfc
-#define GC_USB_PCGCCTL_STOPPCLK_LSB              0x0
-#define GC_USB_PCGCCTL_STOPPCLK_MASK             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_STOPPCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_GATEHCLK_LSB              0x1
-#define GC_USB_PCGCCTL_GATEHCLK_MASK             0x2
-#define GC_USB_PCGCCTL_GATEHCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_GATEHCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_PWRCLMP_LSB               0x2
-#define GC_USB_PCGCCTL_PWRCLMP_MASK              0x4
-#define GC_USB_PCGCCTL_PWRCLMP_SIZE              0x1
-#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT           0x0
-#define GC_USB_PCGCCTL_PWRCLMP_OFFSET            0xe00
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB         0x3
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK        0x8
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE        0x1
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT     0x0
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET      0xe00
-#define GC_USB_PCGCCTL_PHYSLEEP_LSB              0x6
-#define GC_USB_PCGCCTL_PHYSLEEP_MASK             0x40
-#define GC_USB_PCGCCTL_PHYSLEEP_SIZE             0x1
-#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT          0x0
-#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET           0xe00
-#define GC_USB_PCGCCTL_L1SUSPENDED_LSB           0x7
-#define GC_USB_PCGCCTL_L1SUSPENDED_MASK          0x80
-#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE          0x1
-#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT       0x0
-#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET        0xe00
-#define GC_USB_DFIFO_SIZE                        0x1000
-
-
-#endif /* __CHIP_STM32_USB_DWC_REGISTERS_H */
diff --git a/chip/stm32/usb_dwc_stream.c b/chip/stm32/usb_dwc_stream.c
deleted file mode 100644
index 2f20d88dda..0000000000
--- a/chip/stm32/usb_dwc_stream.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "registers.h"
-#include "timer.h"
-#include "usb_dwc_stream.h"
-#include "util.h"
-
-#include "console.h"
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-/*
- * This function tries to shove new bytes from the USB host into the queue for
- * consumption elsewhere. It is invoked either by a HW interrupt (telling us we
- * have new bytes from the USB host), or by whoever is reading bytes out of the
- * other end of the queue (telling us that there's now more room in the queue
- * if we still have bytes to shove in there).
- */
-int rx_stream_handler(struct usb_stream_config const *config)
-{
-	int rx_count = rx_ep_pending(config->endpoint);
-
-	/* If we have some, try to shove them into the queue */
-	if (rx_count) {
-		size_t added = QUEUE_ADD_UNITS(
-			config->producer.queue, config->rx_ram,
-			rx_count);
-		if (added != rx_count) {
-			CPRINTF("rx_stream_handler: failed ep%d "
-				"queue %d bytes, accepted %d\n",
-				config->endpoint, rx_count, added);
-		}
-	}
-
-	if (!rx_ep_is_active(config->endpoint))
-		usb_read_ep(config->endpoint, config->rx_size, config->rx_ram);
-
-	return rx_count;
-}
-
-/* Try to send some bytes to the host */
-int tx_stream_handler(struct usb_stream_config const *config)
-{
-	size_t count;
-
-	if (!*(config->is_reset))
-		return 0;
-	if (!tx_ep_is_ready(config->endpoint))
-		return 0;
-
-	count = QUEUE_REMOVE_UNITS(config->consumer.queue, config->tx_ram,
-				   config->tx_size);
-	if (count)
-		usb_write_ep(config->endpoint, count, config->tx_ram);
-
-	return count;
-}
-
-/* Reset stream */
-void usb_stream_event(struct usb_stream_config const *config,
-		enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	epN_reset(config->endpoint);
-
-	*(config->is_reset) = 1;
-
-	/* Flush any queued data */
-	hook_call_deferred(config->deferred_tx, 0);
-	hook_call_deferred(config->deferred_rx, 0);
-}
-
-static void usb_read(struct producer const *producer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(producer, struct usb_stream_config, producer);
-
-	hook_call_deferred(config->deferred_rx, 0);
-}
-
-static void usb_written(struct consumer const *consumer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(consumer, struct usb_stream_config, consumer);
-
-	hook_call_deferred(config->deferred_tx, 0);
-}
-
-struct producer_ops const usb_stream_producer_ops = {
-	.read = usb_read,
-};
-
-struct consumer_ops const usb_stream_consumer_ops = {
-	.written = usb_written,
-};
diff --git a/chip/stm32/usb_dwc_stream.h b/chip/stm32/usb_dwc_stream.h
deleted file mode 100644
index e46e7a929c..0000000000
--- a/chip/stm32/usb_dwc_stream.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_DWC_STREAM_H
-#define __CROS_EC_USB_DWC_STREAM_H
-
-/* USB STREAM driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "consumer.h"
-#include "hooks.h"
-#include "registers.h"
-#include "producer.h"
-#include "queue.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/*
- * Compile time Per-USB stream configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB stream.  This structure binds
- * together all information required to operate a USB stream.
- */
-struct usb_stream_config {
-	/*
-	 * Endpoint index, and pointers to the USB packet RAM buffers.
-	 */
-	int endpoint;
-	struct dwc_usb_ep *ep;
-
-	int *is_reset;
-	int *overflow;
-
-	/*
-	 * Deferred function to call to handle USB and Queue request.
-	 */
-	const struct deferred_data *deferred_tx;
-	const struct deferred_data *deferred_rx;
-
-	int tx_size;
-	int rx_size;
-
-	uint8_t *tx_ram;
-	uint8_t *rx_ram;
-
-	struct consumer consumer;
-	struct producer producer;
-};
-
-/*
- * These function tables are defined by the USB Stream driver and are used to
- * initialize the consumer and producer in the usb_stream_config.
- */
-extern struct consumer_ops const usb_stream_consumer_ops;
-extern struct producer_ops const usb_stream_producer_ops;
-
-
-/*
- * Convenience macro for defining USB streams and their associated state and
- * buffers.
- *
- * NAME is used to construct the names of the packet RAM buffers, trampoline
- * functions, usb_stream_state struct, and usb_stream_config struct, the
- * latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * stream.
- *
- * INTERFACE_CLASS, INTERFACE_SUBCLASS, INTERFACE_PROTOCOL are the
- * .bInterfaceClass, .bInterfaceSubClass, and .bInterfaceProtocol fields
- * respectively in the USB interface descriptor.
- *
- * INTERFACE_NAME is the index of the USB string descriptor (iInterface).
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- *
- * RX_SIZE and TX_SIZE are the number of bytes of USB packet RAM to allocate
- * for the RX and TX packets respectively.  The valid values for these
- * parameters are dictated by the USB peripheral.
- *
- * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this driver
- * should write to and read from respectively.
- */
-
-/*
- * The following assertions can not be made because they require access to
- * non-const fields, but should be kept in mind.
- *
- * BUILD_ASSERT(RX_QUEUE.buffer_units >= RX_SIZE);
- * BUILD_ASSERT(TX_QUEUE.buffer_units >= TX_SIZE);
- * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
- * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
- */
-#define USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       INTERFACE_CLASS,				\
-			       INTERFACE_SUBCLASS,			\
-			       INTERFACE_PROTOCOL,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)				\
-									\
-	static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE];		\
-	static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE];		\
-	static int CONCAT2(NAME, _is_reset_);				\
-	static int CONCAT2(NAME, _overflow_);				\
-	static void CONCAT2(NAME, _deferred_tx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));			\
-	static void CONCAT2(NAME, _deferred_rx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));			\
-	struct usb_stream_config const NAME = {				\
-		.endpoint     = ENDPOINT,				\
-		.is_reset     = &CONCAT2(NAME, _is_reset_),		\
-		.overflow     = &CONCAT2(NAME, _overflow_),		\
-		.deferred_tx  = &CONCAT2(NAME, _deferred_tx__data),	\
-		.deferred_rx  = &CONCAT2(NAME, _deferred_rx__data),	\
-		.tx_size      = TX_SIZE,				\
-		.rx_size      = RX_SIZE,				\
-		.tx_ram       = CONCAT2(NAME, _buf_tx_),		\
-		.rx_ram       = CONCAT2(NAME, _buf_rx_),		\
-		.consumer  = {						\
-			.queue = &TX_QUEUE,				\
-			.ops   = &usb_stream_consumer_ops,		\
-		},							\
-		.producer  = {						\
-			.queue = &RX_QUEUE,				\
-			.ops   = &usb_stream_producer_ops,		\
-		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = RX_SIZE,				\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _deferred_tx_)(void)			\
-	{ tx_stream_handler(&NAME); }					\
-	static void CONCAT2(NAME, _deferred_rx_)(void)			\
-	{ rx_stream_handler(&NAME); }					\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_epN_tx(ENDPOINT);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_epN_rx(ENDPOINT);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_stream_event(&NAME, evt);				\
-	}								\
-	struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {			\
-		.max_packet = USB_MAX_PACKET_SIZE,			\
-		.tx_fifo = ENDPOINT,					\
-		.out_pending = 0,					\
-		.out_expected = 0,					\
-		.out_data = 0,						\
-		.out_databuffer = CONCAT2(NAME, _buf_rx_),		\
-		.out_databuffer_max = RX_SIZE,				\
-		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),	\
-		.in_packets = 0,					\
-		.in_pending = 0,					\
-		.in_data = 0,						\
-		.in_databuffer = CONCAT2(NAME, _buf_tx_),		\
-		.in_databuffer_max = TX_SIZE,				\
-		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),	\
-	};								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
-		       CONCAT2(NAME, _ep_event));
-
-/* This is a short version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG(NAME,						\
-			  INTERFACE,					\
-			  INTERFACE_NAME,				\
-			  ENDPOINT,					\
-			  RX_SIZE,					\
-			  TX_SIZE,					\
-			  RX_QUEUE,					\
-			  TX_QUEUE)					\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)
-
-/*
- * Handle USB and Queue request in a deferred callback.
- */
-int rx_stream_handler(struct usb_stream_config const *config);
-int tx_stream_handler(struct usb_stream_config const *config);
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB stream driver.
- */
-void usb_stream_tx(struct usb_stream_config const *config);
-void usb_stream_rx(struct usb_stream_config const *config);
-void usb_stream_event(struct usb_stream_config const *config,
-		enum usb_ep_event evt);
-
-#endif /* __CROS_EC_USB_STREAM_H */
diff --git a/chip/stm32/usb_dwc_update.h b/chip/stm32/usb_dwc_update.h
deleted file mode 100644
index 6d79f3aca9..0000000000
--- a/chip/stm32/usb_dwc_update.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_STM32_USB_DWC_UPDATE_H
-#define __CROS_EC_STM32_USB_DWC_UPDATE_H
-
-extern struct dwc_usb_ep usb_update_ep_ctl;
-
-#endif /* __CROS_EC_STM32_USB_DWC_UPDATE_H */
diff --git a/chip/stm32/usb_endpoints.c b/chip/stm32/usb_endpoints.c
deleted file mode 100644
index 85952a1387..0000000000
--- a/chip/stm32/usb_endpoints.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB endpoints/interfaces callbacks declaration
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include "config.h"
-#include "common.h"
-#include "usb_hw.h"
-
-typedef void (*xfer_func)(void);
-typedef void (*evt_func) (enum usb_ep_event evt);
-
-#if defined(CHIP_FAMILY_STM32F4)
-#define iface_arguments struct usb_setup_packet *req
-#else
-#define iface_arguments usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx
-#endif
-typedef int (*iface_func)(iface_arguments);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#if PASS == 1
-void ep_undefined(void)
-{
-	return;
-}
-
-void ep_evt_undefined(enum usb_ep_event evt)
-{
-	return;
-}
-
-/* Undefined interface callbacks fail by returning non-zero*/
-int iface_undefined(iface_arguments)
-{
-	return 1;
-}
-
-#define table(type, name, x) x
-
-#define endpoint_tx(number) \
-	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _tx(void);
-#define endpoint_rx(number) \
-	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _rx(void);
-#define endpoint_evt(number) \
-	extern void __attribute__((used, weak, alias("ep_evt_undefined"))) \
-		ep_ ## number ## _evt(enum usb_ep_event evt);
-#define interface(number) \
-	extern int __attribute__((used, weak, alias("iface_undefined"))) \
-		iface_ ## number ## _request(iface_arguments);
-
-#define null
-
-#endif /* PASS 1 */
-
-#if PASS == 2
-#undef table
-#undef endpoint_tx
-#undef endpoint_rx
-#undef endpoint_evt
-#undef interface
-#undef null
-
-/* align function pointers on a 32-bit boundary */
-#define table(type, name, x) type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name ",\"a\" @"))) = { x };
-#define null (void*)0
-
-#define ep_(num, suf) CONCAT3(ep_, num, suf)
-#define ep(num, suf) ep_(num, suf)
-
-#define endpoint_tx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _tx,
-#define endpoint_rx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rx,
-#define endpoint_evt(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _evt,
-#define interface(number) \
-	[number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = iface_ ## number ## _request,
-#endif /* PASS 2 */
-
-/*
- * The initializers are listed backwards, but that's so that the items beyond
- * the chip's limit are first assigned to the last field, then overwritten by
- * its actual value due to the designated initializers in the macros above.
- * It all sorts out nicely
- */
-table(xfer_func, usb_ep_tx,
-	endpoint_tx(15)
-	endpoint_tx(14)
-	endpoint_tx(13)
-	endpoint_tx(12)
-	endpoint_tx(11)
-	endpoint_tx(10)
-	endpoint_tx(9)
-	endpoint_tx(8)
-	endpoint_tx(7)
-	endpoint_tx(6)
-	endpoint_tx(5)
-	endpoint_tx(4)
-	endpoint_tx(3)
-	endpoint_tx(2)
-	endpoint_tx(1)
-	endpoint_tx(0)
-)
-
-table(xfer_func, usb_ep_rx,
-	endpoint_rx(15)
-	endpoint_rx(14)
-	endpoint_rx(13)
-	endpoint_rx(12)
-	endpoint_rx(11)
-	endpoint_rx(10)
-	endpoint_rx(9)
-	endpoint_rx(8)
-	endpoint_rx(7)
-	endpoint_rx(6)
-	endpoint_rx(5)
-	endpoint_rx(4)
-	endpoint_rx(3)
-	endpoint_rx(2)
-	endpoint_rx(1)
-	endpoint_rx(0)
-)
-
-table(evt_func, usb_ep_event,
-	endpoint_evt(15)
-	endpoint_evt(14)
-	endpoint_evt(13)
-	endpoint_evt(12)
-	endpoint_evt(11)
-	endpoint_evt(10)
-	endpoint_evt(9)
-	endpoint_evt(8)
-	endpoint_evt(7)
-	endpoint_evt(6)
-	endpoint_evt(5)
-	endpoint_evt(4)
-	endpoint_evt(3)
-	endpoint_evt(2)
-	endpoint_evt(1)
-	endpoint_evt(0)
-)
-
-#if USB_IFACE_COUNT > 0
-table(iface_func, usb_iface_request,
-	interface(7)
-	interface(6)
-	interface(5)
-	interface(4)
-	interface(3)
-	interface(2)
-	interface(1)
-	interface(0)
-)
-#endif
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "usb_endpoints.c"
-#endif
diff --git a/chip/stm32/usb_gpio.c b/chip/stm32/usb_gpio.c
deleted file mode 100644
index 64d46875b5..0000000000
--- a/chip/stm32/usb_gpio.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "usb_gpio.h"
-
-void usb_gpio_tx(struct usb_gpio_config const *config)
-{
-	size_t   i;
-	uint32_t mask  = 1;
-	uint32_t value = 0;
-
-	for (i = 0; i < config->num_gpios; ++i, mask <<= 1)
-		value |= (gpio_get_level(config->gpios[i])) ? mask : 0;
-
-	config->tx_ram[0] = value;
-	config->tx_ram[1] = value >> 16;
-
-	btable_ep[config->endpoint].tx_count = USB_GPIO_TX_PACKET_SIZE;
-
-	/*
-	 * TX packet updated, mark the packet as VALID.
-	 */
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0);
-}
-
-void usb_gpio_rx(struct usb_gpio_config const *config)
-{
-	size_t   i;
-	uint32_t mask        = 1;
-	uint32_t set_mask    = ((uint32_t)(config->rx_ram[0]) |
-			        (uint32_t)(config->rx_ram[1]) << 16);
-	uint32_t clear_mask  = ((uint32_t)(config->rx_ram[2]) |
-			        (uint32_t)(config->rx_ram[3]) << 16);
-	uint32_t ignore_mask = set_mask & clear_mask;
-
-	config->state->set_mask = set_mask;
-	config->state->clear_mask = clear_mask;
-
-	if ((btable_ep[config->endpoint].rx_count & RX_COUNT_MASK) ==
-	    USB_GPIO_RX_PACKET_SIZE) {
-		for (i = 0; i < config->num_gpios; ++i, mask <<= 1) {
-			if (ignore_mask & mask)
-				;
-			else if (set_mask & mask)
-				gpio_set_level(config->gpios[i], 1);
-			else if (clear_mask & mask)
-				gpio_set_level(config->gpios[i], 0);
-		}
-	}
-
-	/*
-	 * RX packet consumed, mark the packet as VALID.
-	 */
-	STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0);
-}
-
-void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt)
-{
-	int i;
-
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	i = config->endpoint;
-
-	btable_ep[i].tx_addr  = usb_sram_addr(config->tx_ram);
-	btable_ep[i].tx_count = USB_GPIO_TX_PACKET_SIZE;
-
-	btable_ep[i].rx_addr  = usb_sram_addr(config->rx_ram);
-	btable_ep[i].rx_count = ((USB_GPIO_RX_PACKET_SIZE / 2) << 10);
-
-	/*
-	 * Initialize TX buffer with zero, the first IN transaction will fill
-	 * this in with a valid value.
-	 */
-	config->tx_ram[0] = 0;
-	config->tx_ram[1] = 0;
-
-	STM32_USB_EP(i) = ((i <<  0) | /* Endpoint Addr*/
-			   (3 <<  4) | /* TX Valid */
-			   (0 <<  9) | /* Bulk EP */
-			   (3 << 12)); /* RX Valid */
-}
diff --git a/chip/stm32/usb_gpio.h b/chip/stm32/usb_gpio.h
deleted file mode 100644
index b27c7f9485..0000000000
--- a/chip/stm32/usb_gpio.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_GPIO_H
-#define __CROS_EC_USB_GPIO_H
-
-/* STM32 USB GPIO driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-struct usb_gpio_state {
-	uint32_t set_mask;
-	uint32_t clear_mask;
-};
-
-/*
- * Compile time Per-USB gpio configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB gpio.  This structure binds
- * together all information required to operate a USB gpio.
- */
-struct usb_gpio_config {
-	struct usb_gpio_state *state;
-
-	/*
-	 * Endpoint index, and pointers to the USB packet RAM buffers.
-	 */
-	int endpoint;
-
-	usb_uint *rx_ram;
-	usb_uint *tx_ram;
-
-	/*
-	 * GPIO list
-	 */
-	enum gpio_signal const *gpios;
-	size_t num_gpios;
-};
-
-#define USB_GPIO_RX_PACKET_SIZE 8
-#define USB_GPIO_TX_PACKET_SIZE 4
-
-/*
- * Convenience macro for defining a USB GPIO driver and its associated state.
- *
- * NAME is used to construct the names of the trampoline functions,
- * usb_gpio_state struct, and usb_gpio_config struct, the latter is just
- * called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * GPIO driver.
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- */
-#define USB_GPIO_CONFIG(NAME,						\
-			GPIO_LIST,					\
-			INTERFACE,					\
-			ENDPOINT)					\
-	BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32);			\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram;	\
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram;	\
-	struct usb_gpio_config const NAME = {				\
-		.state     = &((struct usb_gpio_state){}),		\
-		.endpoint  = ENDPOINT,					\
-		.rx_ram    = CONCAT2(NAME, _ep_rx_buffer),		\
-		.tx_ram    = CONCAT2(NAME, _ep_tx_buffer),		\
-		.gpios     = GPIO_LIST,					\
-		.num_gpios = ARRAY_SIZE(GPIO_LIST),			\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = 0,				\
-		.bInterfaceProtocol = 0,				\
-		.iInterface         = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_GPIO_TX_PACKET_SIZE,		\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_GPIO_RX_PACKET_SIZE,		\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_gpio_tx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_gpio_rx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_gpio_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
-		       CONCAT2(NAME, _ep_event))
-
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB GPIO driver.
- */
-void usb_gpio_tx(struct usb_gpio_config const *config);
-void usb_gpio_rx(struct usb_gpio_config const *config);
-void usb_gpio_event(struct usb_gpio_config const *config,
-		    enum usb_ep_event evt);
-
-#endif /* __CROS_EC_USB_GPIO_H */
diff --git a/chip/stm32/usb_hid.c b/chip/stm32/usb_hid.c
deleted file mode 100644
index b8336fa0a0..0000000000
--- a/chip/stm32/usb_hid.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "usb_hid.h"
-#include "usb_hid_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-void hid_tx(int ep)
-{
-	/* clear IT */
-	STM32_USB_EP(ep) = (STM32_USB_EP(ep) & EP_MASK);
-}
-
-void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len,
-	       usb_uint *hid_ep_rx_buf, int rx_len)
-{
-	int i;
-	uint16_t ep_reg;
-
-	btable_ep[ep].tx_addr = usb_sram_addr(hid_ep_tx_buf);
-	btable_ep[ep].tx_count = tx_len;
-
-	/* STM32 USB SRAM needs to be accessed one U16 at a time */
-	for (i = 0; i < DIV_ROUND_UP(tx_len, 2); i++)
-		hid_ep_tx_buf[i] = 0;
-
-	ep_reg = (ep << 0) /* Endpoint Address */ |
-		EP_TX_VALID |
-		(3 << 9) /* interrupt EP */ |
-		EP_RX_DISAB;
-
-	/* Enable RX for output reports */
-	if (hid_ep_rx_buf && rx_len > 0) {
-		btable_ep[ep].rx_addr = usb_sram_addr(hid_ep_rx_buf);
-		btable_ep[ep].rx_count = ((rx_len + 1) / 2) << 10;
-
-		ep_reg |= EP_RX_VALID;  /* RX Valid */
-	}
-
-	STM32_USB_EP(ep) = ep_reg;
-}
-
-/*
- * Keep track of state in case we need to be called multiple times,
- * if the report length is bigger than 64 bytes.
- */
-static int report_left;
-static const uint8_t *report_ptr;
-
-/*
- * Send report through ep0_buf_tx.
- *
- * If report size is greater than USB packet size (64 bytes), rest of the
- * reports will be saved in `report_ptr` and `report_left`, so we can call this
- * function again to send the remain parts.
- *
- * @return 0 if entire report is sent, 1 if there are remaining data.
- */
-static int send_report(usb_uint *ep0_buf_tx,
-		       const uint8_t *report,
-		       int report_size)
-{
-	int packet_size = MIN(report_size, USB_MAX_PACKET_SIZE);
-
-	memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-			 report, packet_size);
-	btable_ep[0].tx_count = packet_size;
-	/* report_left != 0 if report doesn't fit in 1 packet. */
-	report_left = report_size - packet_size;
-	report_ptr = report + packet_size;
-
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-			report_left ? 0 : EP_STATUS_OUT);
-
-	return report_left ? 1 : 0;
-}
-
-int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
-		      const struct usb_hid_config_t *config)
-{
-	const uint8_t *report_desc = config->report_desc;
-	int report_size = config->report_size;
-	const struct usb_hid_descriptor *hid_desc = config->hid_desc;
-
-	if (!ep0_buf_rx) {
-		/*
-		 * Continue previous transfer. We ignore report_desc/size here,
-		 * which is fine as only one GET_DESCRIPTOR command comes at a
-		 * time.
-		 */
-		if (report_left == 0)
-			return -1;
-		report_size = MIN(USB_MAX_PACKET_SIZE, report_left);
-		memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				 report_ptr, report_size);
-		btable_ep[0].tx_count = report_size;
-		report_left -= report_size;
-		report_ptr += report_size;
-		STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID,
-				report_left ? 0 : EP_STATUS_OUT);
-		return report_left ? 1 : 0;
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_RECIP_INTERFACE |
-					(USB_REQ_GET_DESCRIPTOR << 8))) {
-		if (ep0_buf_rx[1] == (USB_HID_DT_REPORT << 8)) {
-			/* Setup : HID specific : Get Report descriptor */
-			return send_report(ep0_buf_tx, report_desc,
-					   MIN(ep0_buf_rx[3], report_size));
-		} else if (ep0_buf_rx[1] == (USB_HID_DT_HID << 8)) {
-			/* Setup : HID specific : Get HID descriptor */
-			memcpy_to_usbram_ep0_patch(hid_desc, sizeof(*hid_desc));
-			btable_ep[0].tx_count = sizeof(*hid_desc);
-			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-					EP_STATUS_OUT);
-			return 0;
-		}
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN |
-				     USB_RECIP_INTERFACE |
-				     USB_TYPE_CLASS |
-				     (USB_HID_REQ_GET_REPORT << 8))) {
-		const uint8_t report_type = (ep0_buf_rx[1] >> 8) & 0xFF;
-		const uint8_t report_id = ep0_buf_rx[1] & 0xFF;
-		int retval;
-
-		report_left = ep0_buf_rx[3];
-		if (!config->get_report) /* not supported */
-			return -1;
-
-		retval = config->get_report(report_id,
-					    report_type,
-					    &report_ptr,
-					    &report_left);
-		if (retval)
-			return retval;
-
-		return send_report(ep0_buf_tx, report_ptr, report_left);
-	}
-
-	return -1;
-}
diff --git a/chip/stm32/usb_hid_hw.h b/chip/stm32/usb_hid_hw.h
deleted file mode 100644
index a36a66567e..0000000000
--- a/chip/stm32/usb_hid_hw.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB HID HW definitions, to be used by class drivers.
- */
-
-#ifndef __CROS_EC_USB_HID_HW_H
-#define __CROS_EC_USB_HID_HW_H
-
-#include <common.h>
-
-struct usb_hid_config_t {
-	const uint8_t *report_desc;
-	int report_size;
-	const struct usb_hid_descriptor *hid_desc;
-
-	/*
-	 * Handle USB HID Get_Report request, can be NULL if not supported.
-	 *
-	 * @param report_id: ID of the report being requested
-	 * @param report_type: 0x1 (INPUT) / 0x2 (OUTPUT) / 0x3 (FEATURE)
-	 * @param buffer_ptr: handler should set it to the pointer of buffer to
-	 *     return.
-	 * @param buffer_size: handler should set it to the size of returned
-	 *     buffer.
-	 */
-	int (*get_report)(uint8_t report_id,
-			  uint8_t report_type,
-			  const uint8_t **buffer_ptr,
-			  int *buffer_size);
-};
-
-/* internal callbacks for HID class drivers */
-void hid_tx(int ep);
-void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len,
-	       usb_uint *hid_ep_rx_buf, int rx_len);
-int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
-		      const struct usb_hid_config_t *hid_config);
-
-#endif
diff --git a/chip/stm32/usb_hid_keyboard.c b/chip/stm32/usb_hid_keyboard.c
deleted file mode 100644
index e2a8d675e9..0000000000
--- a/chip/stm32/usb_hid_keyboard.c
+++ /dev/null
@@ -1,841 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "keyboard_config.h"
-#include "keyboard_protocol.h"
-#include "link_defs.h"
-#include "pwm.h"
-#include "queue.h"
-#include "registers.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "usb_hid.h"
-#include "usb_hid_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-static const int keyboard_debug;
-
-struct key_event {
-	uint32_t time;
-	uint8_t keycode;
-	uint8_t pressed;
-};
-
-static struct queue const key_queue = QUEUE_NULL(16, struct key_event);
-static struct mutex key_queue_mutex;
-
-enum hid_protocol {
-	HID_BOOT_PROTOCOL = 0,
-	HID_REPORT_PROTOCOL = 1,
-	HID_PROTOCOL_COUNT = 2,
-};
-
-/* Current protocol, behaviour is identical in both modes. */
-static enum hid_protocol protocol = HID_REPORT_PROTOCOL;
-
-#if defined(CONFIG_KEYBOARD_ASSISTANT_KEY) || \
-    defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH)
-#define HID_KEYBOARD_EXTRA_FIELD
-#endif
-
-/*
- * Note: This first 8 bytes of this report format cannot be changed, as that
- * would break HID Boot protocol compatibility (see HID 1.11 "Appendix B: Boot
- * Interface Descriptors").
- */
-struct usb_hid_keyboard_report {
-	uint8_t modifiers; /* bitmap of modifiers 224-231 */
-	uint8_t reserved; /* 0x0 */
-	uint8_t keys[6];
-	/* Non-boot protocol fields below */
-#ifdef HID_KEYBOARD_EXTRA_FIELD
-	/* Assistant/tablet mode switch bitmask */
-	uint8_t extra;
-#endif
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	uint32_t top_row; /* bitmap of top row action keys */
-#endif
-} __packed;
-
-struct usb_hid_keyboard_output_report {
-	uint8_t brightness;
-} __packed;
-
-#define HID_KEYBOARD_BOOT_SIZE 8
-
-#define HID_KEYBOARD_REPORT_SIZE sizeof(struct usb_hid_keyboard_report)
-#define HID_KEYBOARD_OUTPUT_REPORT_SIZE \
-	sizeof(struct usb_hid_keyboard_output_report)
-
-#define HID_KEYBOARD_EP_INTERVAL_MS 16 /* ms */
-
-/*
- * Coalesce events happening within some interval. The value must be greater
- * than EP interval to ensure we cannot have a backlog of keys.
- * It must also be short enough to ensure that the intended order of key presses
- * is passed to AP, and that we do not coalesce press and release events (which
- * would result in lost keys).
- */
-#define COALESCE_INTERVAL (18 * MSEC)
-
-/*
- * Discard key events in the FIFO buffer that are older than this amount of
- * time. Note that we do not fully drop them, we still update the report,
- * but we do not send the events individually anymore (so an old key press
- * and release will be dropped altogether, but a single press/release will
- * still be reported correctly).
- */
-#define KEY_DISCARD_MAX_TIME (1 * SECOND)
-
-/* Modifiers keycode range */
-#define HID_KEYBOARD_MODIFIER_LOW 0xe0
-#define HID_KEYBOARD_MODIFIER_HIGH 0xe7
-
-/* Supported function key range */
-#define HID_F1 0x3a
-#define HID_F12 0x45
-#define HID_F13 0x68
-#define HID_F15 0x6a
-
-/* Special keys/switches */
-#define HID_KEYBOARD_EXTRA_LOW 0xf0
-#define HID_KEYBOARD_ASSISTANT_KEY 0xf0
-#define HID_KEYBOARD_TABLET_MODE_SWITCH 0xf1
-#define HID_KEYBOARD_EXTRA_HIGH 0xf1
-
-/* The standard Chrome OS keyboard matrix table. See HUT 1.12v2 Table 12 and
- * https://www.w3.org/TR/DOM-Level-3-Events-code .
- *
- * Assistant key is mapped as 0xf0, but this key code is never actually send.
- */
-const uint8_t keycodes[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, 0x00},
-	{0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14},
-	{0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08},
-	{0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15},
-	{0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a},
-	{0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c},
-	{0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18},
-	{0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5},
-	{0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13},
-	{0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12},
-	{0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00},
-	{0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52},
-	{0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50},
-};
-
-/* HID descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID_KEYBOARD) = {
-	.bLength = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType = USB_DT_INTERFACE,
-	.bInterfaceNumber = USB_IFACE_HID_KEYBOARD,
-	.bAlternateSetting = 0,
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-	.bNumEndpoints = 2,
-#else
-	.bNumEndpoints = 1,
-#endif
-	.bInterfaceClass = USB_CLASS_HID,
-	.bInterfaceSubClass = USB_HID_SUBCLASS_BOOT,
-	.bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD,
-	.iInterface = 0,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 81) = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = 0x80 | USB_EP_HID_KEYBOARD,
-	.bmAttributes = 0x03 /* Interrupt endpoint */,
-	.wMaxPacketSize = HID_KEYBOARD_REPORT_SIZE,
-	.bInterval = HID_KEYBOARD_EP_INTERVAL_MS /* ms polling interval */
-};
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = USB_EP_HID_KEYBOARD,
-	.bmAttributes = 0x03 /* Interrupt endpoint */,
-	.wMaxPacketSize = HID_KEYBOARD_OUTPUT_REPORT_SIZE,
-	.bInterval = HID_KEYBOARD_EP_INTERVAL_MS
-};
-#endif
-
-#define KEYBOARD_BASE_DESC						\
-	0x05, 0x01, /* Usage Page (Generic Desktop) */			\
-	0x09, 0x06, /* Usage (Keyboard) */				\
-	0xA1, 0x01, /* Collection (Application) */			\
-									\
-	/* Modifiers */							\
-	0x05, 0x07, /* Usage Page (Key Codes) */			\
-	0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */		\
-	0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */		\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x08, /* Report Count (8) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \
-									\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x08, /* Report Size (8) */				\
-	0x81, 0x01, /* Input (Constant), ;Reserved byte */		\
-									\
-	/* Normal keys */						\
-	0x95, 0x06, /* Report Count (6) */				\
-	0x75, 0x08, /* Report Size (8) */				\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0xa4, /* Logical Maximum (164) */				\
-	0x05, 0x07, /* Usage Page (Key Codes) */			\
-	0x19, 0x00, /* Usage Minimum (0) */				\
-	0x29, 0xa4, /* Usage Maximum (164) */				\
-	0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */
-
-#define KEYBOARD_TOP_ROW_DESC						\
-	/* Modifiers */							\
-	0x05, 0x0C, /* Consumer Page */					\
-	0x0A, 0x24, 0x02, /* AC Back (0x224) */				\
-	0x0A, 0x25, 0x02, /* AC Forward (0x225) */			\
-	0x0A, 0x27, 0x02, /* AC Refresh (0x227) */			\
-	0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */			\
-	0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */	\
-	0x09, 0x70,       /* Display Brightness Decrement (0x70) */	\
-	0x09, 0x6F,       /* Display Brightness Increment (0x6F) */	\
-	0x09, 0xE2,       /* Mute (0xE2) */				\
-	0x09, 0xEA,       /* Volume Decrement (0xEA) */			\
-	0x09, 0xE9,       /* Volume Increment (0xE9) */			\
-	0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage 0x46) */ \
-	0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */		\
-	0x09, 0x7A,       /* Keyboard Brightness Decrement (0x7A) */	\
-	0x09, 0x79,       /* Keyboard Brightness Increment (0x79)*/	\
-	0x09, 0xCD,       /* Play / Pause (0xCD) */			\
-	0x09, 0xB5,       /* Scan Next Track (0xB5) */			\
-	0x09, 0xB6,       /* Scan Previous Track (0xB6) */		\
-	0x09, 0x7C,       /* Keyboard Backlight OOC (0x7C) */ \
-	0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage 0x2F) */ \
-	0x09, 0x32,       /* Sleep (0x32) */				\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x14, /* Report Count (20) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \
-									\
-	/* 12-bit padding */						\
-	0x95, 0x0C, /* Report Count (12) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
-
-#define KEYBOARD_TOP_ROW_FEATURE_DESC					\
-	0x06, 0xd1, 0xff, /* Usage Page (Google) */			\
-	0x09, 0x01,       /* Usage (Top Row List) */			\
-	0xa1, 0x02,       /* Collection (Logical) */			\
-	0x05, 0x0a,       /*   Usage Page (Ordinal) */			\
-	0x19, 0x01,       /*   Usage Minimum (1) */			\
-	0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */	\
-	0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */	\
-	0x75, 0x20,       /*   Report Size (32) */			\
-	0xb1, 0x03,       /*   Feature (Cnst,Var,Abs) */		\
-	0xc0,             /* End Collection */
-
-/*
- * Vendor-defined Usage Page 0xffd1:
- *  - 0x18: Assistant key
- *  - 0x19: Tablet mode switch
- */
-#ifdef HID_KEYBOARD_EXTRA_FIELD
-#ifdef CONFIG_KEYBOARD_ASSISTANT_KEY
-#define KEYBOARD_ASSISTANT_KEY_DESC					\
-	0x19, 0x18, /* Usage Minimum */					\
-	0x29, 0x18, /* Usage Maximum */					\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */
-#else
-/* No assistant key: just pad 1 bit. */
-#define KEYBOARD_ASSISTANT_KEY_DESC					\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
-#endif /* !CONFIG_KEYBOARD_ASSISTANT_KEY */
-
-#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-#define KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-	0x19, 0x19, /* Usage Minimum */					\
-	0x29, 0x19, /* Usage Maximum */					\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */
-#else
-/* No tablet mode swtch: just pad 1 bit. */
-#define KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
-#endif /* CONFIG_KEYBOARD_TABLET_MODE_SWITCH */
-
-#define KEYBOARD_VENDOR_DESC						\
-	0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */	\
-									\
-	KEYBOARD_ASSISTANT_KEY_DESC					\
-	KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-									\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x06, /* Report Size (6) */				\
-	0x81, 0x01, /* Input (Constant), ;6-bit padding */
-#endif /* HID_KEYBOARD_EXTRA_FIELD */
-
-#define KEYBOARD_BACKLIGHT_DESC \
-	0xA1, 0x02, /* Collection (Logical) */				\
-	0x05, 0x14, /*   Usage Page (Alphanumeric Display) */		\
-	0x09, 0x46, /*   Usage (Display Brightness) */			\
-	0x95, 0x01, /*   Report Count (1) */				\
-	0x75, 0x08, /*   Report Size (8) */				\
-	0x15, 0x00, /*   Logical Minimum (0) */				\
-	0x25, 0x64, /*   Logical Maximum (100) */			\
-	0x91, 0x02, /*   Output (Data, Variable, Absolute) */		\
-	0xC0,       /* End Collection */
-
-/*
- * To allow dynamic detection of keyboard backlights, we define two descriptors.
- * One has keyboard backlight, and the other one does not.
- */
-
-/* HID : Report Descriptor */
-static const uint8_t report_desc[] = {
-
-	KEYBOARD_BASE_DESC
-
-#ifdef KEYBOARD_VENDOR_DESC
-	KEYBOARD_VENDOR_DESC
-#endif
-
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	KEYBOARD_TOP_ROW_DESC
-	KEYBOARD_TOP_ROW_FEATURE_DESC
-#endif
-	0xC0        /* End Collection */
-};
-
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-
-/* HID : Report Descriptor with keyboard backlight */
-static const uint8_t report_desc_with_backlight[] = {
-
-	KEYBOARD_BASE_DESC
-
-#ifdef KEYBOARD_VENDOR_DESC
-	KEYBOARD_VENDOR_DESC
-#endif
-
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	KEYBOARD_TOP_ROW_DESC
-	KEYBOARD_TOP_ROW_FEATURE_DESC
-#endif
-	KEYBOARD_BACKLIGHT_DESC
-
-	0xC0        /* End Collection */
-};
-
-#endif
-
-/* HID: HID Descriptor */
-const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD,
-						hid, hid_desc_kb) = {
-	.bLength = 9,
-	.bDescriptorType = USB_HID_DT_HID,
-	.bcdHID = 0x0100,
-	.bCountryCode = 0x00, /* Hardware target country */
-	.bNumDescriptors = 1,
-	.desc = {{
-		.bDescriptorType = USB_HID_DT_REPORT,
-		.wDescriptorLength = sizeof(report_desc)
-	}}
-};
-
-#define EP_TX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_REPORT_SIZE, 2)
-
-static usb_uint hid_ep_tx_buf[EP_TX_BUF_SIZE] __usb_ram;
-static volatile int hid_current_buf;
-
-static volatile int hid_ep_data_ready;
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-#define EP_RX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_OUTPUT_REPORT_SIZE, 2)
-static usb_uint hid_ep_rx_buf[EP_RX_BUF_SIZE] __usb_ram;
-#endif
-
-static struct usb_hid_keyboard_report report;
-
-static void keyboard_process_queue(void);
-DECLARE_DEFERRED(keyboard_process_queue);
-
-static void write_keyboard_report(void)
-{
-	/* Tell the interrupt handler to send the next buffer. */
-	hid_ep_data_ready = 1;
-	if ((STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) == EP_TX_VALID) {
-		/* Endpoint is busy */
-		return;
-	}
-
-	if (atomic_clear((int *)&hid_ep_data_ready)) {
-		/*
-		 * Endpoint is not busy, and interrupt handler did not just
-		 * send the buffer: enable TX.
-		 */
-
-		memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf),
-				&report, sizeof(report));
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
-	}
-
-	/*
-	 * Wake the host. This is required to prevent a race between EP getting
-	 * reloaded and host suspending the device, as, ideally, we never want
-	 * to have EP loaded during suspend, to avoid reporting stale data.
-	 */
-	usb_wake();
-}
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-
-static void hid_keyboard_rx(void)
-{
-	struct usb_hid_keyboard_output_report report;
-	memcpy_from_usbram(&report, (void *) usb_sram_addr(hid_ep_rx_buf),
-			   HID_KEYBOARD_OUTPUT_REPORT_SIZE);
-
-	CPRINTF("Keyboard backlight set to %d%%\n", report.brightness);
-
-	pwm_enable(PWM_CH_KBLIGHT, report.brightness > 0);
-	pwm_set_duty(PWM_CH_KBLIGHT, report.brightness);
-
-	STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-}
-
-#endif
-
-static void hid_keyboard_tx(void)
-{
-	hid_tx(USB_EP_HID_KEYBOARD);
-	if (hid_ep_data_ready) {
-		memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf),
-				&report, sizeof(report));
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
-		hid_ep_data_ready = 0;
-	}
-
-	if (queue_count(&key_queue) > 0)
-		hook_call_deferred(&keyboard_process_queue_data, 0);
-}
-
-static void hid_keyboard_event(enum usb_ep_event evt)
-{
-	if (evt == USB_EVENT_RESET) {
-		protocol = HID_REPORT_PROTOCOL;
-
-		hid_reset(USB_EP_HID_KEYBOARD,
-			  hid_ep_tx_buf,
-			  HID_KEYBOARD_REPORT_SIZE,
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-			  hid_ep_rx_buf,
-			  HID_KEYBOARD_OUTPUT_REPORT_SIZE
-#else
-			  NULL, 0
-#endif
-			  );
-
-		/*
-		 * Reload endpoint on reset, to make sure we report accurate
-		 * state to host (this is especially important for tablet mode
-		 * switch).
-		 */
-		write_keyboard_report();
-		return;
-	}
-
-	if (evt == USB_EVENT_DEVICE_RESUME && queue_count(&key_queue) > 0)
-		hook_call_deferred(&keyboard_process_queue_data, 0);
-}
-
-USB_DECLARE_EP(USB_EP_HID_KEYBOARD, hid_keyboard_tx,
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-	       hid_keyboard_rx,
-#else
-	       hid_keyboard_tx,
-#endif
-	       hid_keyboard_event);
-
-struct action_key_config {
-	uint32_t mask; /* bit position of usb_hid_keyboard_report.top_row */
-	uint32_t usage; /*usage ID */
-};
-
-static const struct action_key_config action_key[] = {
-	[TK_BACK] = { .mask = BIT(0), .usage = 0x000C0224 },
-	[TK_FORWARD] = { .mask = BIT(1), .usage = 0x000C0225 },
-	[TK_REFRESH] = { .mask = BIT(2), .usage = 0x000C0227 },
-	[TK_FULLSCREEN] = { .mask = BIT(3), .usage = 0x000C0232 },
-	[TK_OVERVIEW] = { .mask = BIT(4), .usage = 0x000C029F },
-	[TK_BRIGHTNESS_DOWN] = { .mask = BIT(5), .usage = 0x000C0070 },
-	[TK_BRIGHTNESS_UP] = { .mask = BIT(6), .usage = 0x000C006F },
-	[TK_VOL_MUTE] = { .mask = BIT(7), .usage = 0x000C00E2 },
-	[TK_VOL_DOWN] = { .mask = BIT(8), .usage = 0x000C00EA },
-	[TK_VOL_UP] = { .mask = BIT(9), .usage = 0x000C00E9 },
-	[TK_SNAPSHOT] = { .mask = BIT(10), .usage = 0x00070046 },
-	[TK_PRIVACY_SCRN_TOGGLE] = { .mask = BIT(11), .usage = 0x000C02D0 },
-	[TK_KBD_BKLIGHT_DOWN] = { .mask = BIT(12), .usage = 0x000C007A },
-	[TK_KBD_BKLIGHT_UP] = { .mask = BIT(13), .usage = 0x000C0079 },
-	[TK_PLAY_PAUSE] = { .mask = BIT(14), .usage = 0x000C00CD },
-	[TK_NEXT_TRACK] = { .mask = BIT(15), .usage = 0x000C00B5 },
-	[TK_PREV_TRACK] = { .mask = BIT(16), .usage = 0x000C00B6 },
-	[TK_KBD_BKLIGHT_TOGGLE] = { .mask = BIT(17), .usage = 0x000C007C },
-	[TK_MICMUTE] = { .mask = BIT(18), .usage = 0x000B002F },
-};
-
-/* TK_* is 1-indexed, so the next bit is at ARRAY_SIZE(action_key) - 1 */
-static const int SLEEP_KEY_MASK = BIT(ARRAY_SIZE(action_key) - 1);
-
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-static uint32_t feature_report[CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS];
-
-static void hid_keyboard_feature_init(void)
-{
-	const struct ec_response_keybd_config *config =
-		board_vivaldi_keybd_config();
-
-	for (int i = 0; i < CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS; i++) {
-		int key = config->action_keys[i];
-
-		if (IN_RANGE(key, 0, ARRAY_SIZE(action_key)))
-			feature_report[i] = action_key[key].usage;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, hid_keyboard_feature_init, HOOK_PRIO_DEFAULT - 1);
-#endif
-
-static int hid_keyboard_get_report(uint8_t report_id, uint8_t report_type,
-				   const uint8_t **buffer_ptr, int *buffer_size)
-{
-	if (report_type == REPORT_TYPE_INPUT) {
-		*buffer_ptr = (uint8_t *)&report;
-		*buffer_size = sizeof(report);
-		return 0;
-	}
-
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	if (report_type == REPORT_TYPE_FEATURE) {
-		*buffer_ptr = (uint8_t *)feature_report;
-		*buffer_size = (sizeof(uint32_t) *
-				CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS);
-		return 0;
-	}
-#endif
-
-	return -1;
-}
-
-static struct usb_hid_config_t hid_config_kb = {
-	.report_desc = report_desc,
-	.report_size = sizeof(report_desc),
-	.hid_desc = &hid_desc_kb,
-	.get_report = &hid_keyboard_get_report,
-};
-
-static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx,
-				      usb_uint *ep0_buf_tx)
-{
-	int ret;
-
-	ret = hid_iface_request(ep0_buf_rx, ep0_buf_tx, &hid_config_kb);
-	if (ret >= 0)
-		return ret;
-
-	if (ep0_buf_rx[0] == (USB_DIR_OUT | USB_TYPE_CLASS |
-		       USB_RECIP_INTERFACE | (USB_HID_REQ_SET_PROTOCOL << 8))) {
-		uint16_t value = ep0_buf_rx[1];
-
-		if (value >= HID_PROTOCOL_COUNT)
-			return -1;
-
-		protocol = value;
-
-		/* Reload endpoint with appropriate tx_count. */
-		btable_ep[USB_EP_HID_KEYBOARD].tx_count =
-			(protocol == HID_BOOT_PROTOCOL) ?
-			HID_KEYBOARD_BOOT_SIZE : HID_KEYBOARD_REPORT_SIZE;
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
-
-		btable_ep[0].tx_count = 0;
-		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-		return 0;
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_TYPE_CLASS |
-		       USB_RECIP_INTERFACE | (USB_HID_REQ_GET_PROTOCOL << 8))) {
-		uint8_t value = protocol;
-
-		memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				 &value, sizeof(value));
-		btable_ep[0].tx_count = 1;
-		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-		return 0;
-	}
-
-	return -1;
-}
-USB_DECLARE_IFACE(USB_IFACE_HID_KEYBOARD, hid_keyboard_iface_request)
-
-void keyboard_clear_buffer(void)
-{
-	mutex_lock(&key_queue_mutex);
-	queue_init(&key_queue);
-	mutex_unlock(&key_queue_mutex);
-
-	memset(&report, 0, sizeof(report));
-#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-	if (tablet_get_mode())
-		report.extra |= 0x01 <<	(HID_KEYBOARD_TABLET_MODE_SWITCH -
-					 HID_KEYBOARD_EXTRA_LOW);
-#endif
-	write_keyboard_report();
-}
-
-/*
- * Convert a function key to the bit mask of corresponding action key.
- *
- * Return 0 if no need to map (not a function key or vivaldi not enabled)
- */
-static uint32_t maybe_convert_function_key(int keycode)
-{
-	const struct ec_response_keybd_config *config =
-		board_vivaldi_keybd_config();
-	/* zero-based function key index (e.g. F1 -> 0) */
-	int index;
-
-	if (!IS_ENABLED(CONFIG_USB_HID_KEYBOARD_VIVALDI) || !config)
-		return 0;
-
-	if (IN_RANGE(keycode, HID_F1, HID_F12 + 1))
-		index = keycode - HID_F1;
-	else if (IN_RANGE(keycode, HID_F13, HID_F15 + 1))
-		index = keycode - HID_F13 + 12;
-	else
-		return 0; /* not a function key */
-
-	/* convert F13 to Sleep */
-	if (index == 12 && (config->capabilities & KEYBD_CAP_SCRNLOCK_KEY))
-		return SLEEP_KEY_MASK;
-
-	if (index >= config->num_top_row_keys ||
-			config->action_keys[index] == TK_ABSENT)
-		return 0; /* not mapped */
-	return action_key[config->action_keys[index]].mask;
-}
-
-static void keyboard_process_queue(void)
-{
-	int i;
-	uint8_t mask;
-	struct key_event ev;
-	int valid = 0;
-	int trimming = 0;
-	uint32_t now = __hw_clock_source_read();
-	uint32_t first_key_time;
-
-	if (keyboard_debug)
-		CPRINTF("Q%d (s%d ep%d hw%d)\n", queue_count(&key_queue),
-			usb_is_suspended(), hid_ep_data_ready,
-			(STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK)
-			== EP_TX_VALID);
-	mutex_lock(&key_queue_mutex);
-
-	if (queue_count(&key_queue) == 0) {
-		mutex_unlock(&key_queue_mutex);
-		return;
-	}
-
-	if (usb_is_suspended() || hid_ep_data_ready) {
-		usb_wake();
-
-		if (!queue_is_full(&key_queue)) {
-			/* Queue still has space, let's keep gathering keys. */
-			mutex_unlock(&key_queue_mutex);
-			return;
-		}
-
-		/*
-		 * Queue is full, so we continue, as the code below is
-		 * guaranteed to pop at least one key from the queue, but we do
-		 * not write the report at the end.
-		 */
-		CPRINTF("Trimming queue (%d %d %d)\n", queue_count(&key_queue),
-			usb_is_suspended(), hid_ep_data_ready);
-
-		trimming = 1;
-	}
-
-	/* There is at least one element in the queue. */
-	queue_peek_units(&key_queue, &ev, 0, 1);
-	first_key_time = ev.time;
-
-	/*
-	 * Pick key events from the queue, coalescing events older than events
-	 * within EP interval time to make sure the queue cannot grow, and
-	 * dropping keys that are too old.
-	 */
-	while (queue_count(&key_queue) > 0) {
-		uint32_t action_key_mask;
-
-		queue_peek_units(&key_queue, &ev, 0, 1);
-		if (keyboard_debug)
-			CPRINTF(" =%02x/%d %d %d\n", ev.keycode, ev.keycode,
-				ev.pressed, ev.time - now);
-
-		if ((now - ev.time) <= KEY_DISCARD_MAX_TIME &&
-		    (ev.time - first_key_time) >= COALESCE_INTERVAL)
-			break;
-
-		queue_advance_head(&key_queue, 1);
-
-		action_key_mask = maybe_convert_function_key(ev.keycode);
-		if (action_key_mask) {
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-			if (ev.pressed)
-				report.top_row |= action_key_mask;
-			else
-				report.top_row &= ~action_key_mask;
-			valid = 1;
-#endif
-		} else if (ev.keycode >= HID_KEYBOARD_EXTRA_LOW &&
-		    ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) {
-#ifdef HID_KEYBOARD_EXTRA_FIELD
-			mask = 0x01 << (ev.keycode - HID_KEYBOARD_EXTRA_LOW);
-			if (ev.pressed)
-				report.extra |= mask;
-			else
-				report.extra &= ~mask;
-			valid = 1;
-#endif
-		} else if (ev.keycode >= HID_KEYBOARD_MODIFIER_LOW &&
-		    ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) {
-			mask = 0x01 << (ev.keycode - HID_KEYBOARD_MODIFIER_LOW);
-			if (ev.pressed)
-				report.modifiers |= mask;
-			else
-				report.modifiers &= ~mask;
-			valid = 1;
-		} else if (ev.pressed) {
-			/*
-			 * Add keycode to the list of keys (does nothing if the
-			 * array is already full).
-			 */
-			for (i = 0; i < ARRAY_SIZE(report.keys); i++) {
-				/* Is key already pressed? */
-				if (report.keys[i] == ev.keycode)
-					break;
-				if (report.keys[i] == 0) {
-					report.keys[i] = ev.keycode;
-					valid = 1;
-					break;
-				}
-			}
-		} else {
-			/*
-			 * Remove keycode from the list of keys (does nothing
-			 * if the key is not in the array).
-			 */
-			for (i = 0; i < ARRAY_SIZE(report.keys); i++) {
-				if (report.keys[i] == ev.keycode) {
-					report.keys[i] = 0;
-					valid = 1;
-					break;
-				}
-			}
-		}
-	}
-
-	mutex_unlock(&key_queue_mutex);
-
-	if (valid && !trimming)
-		write_keyboard_report();
-}
-
-static void queue_keycode_event(uint8_t keycode, int is_pressed)
-{
-	struct key_event ev = {
-		.time = __hw_clock_source_read(),
-		.keycode = keycode,
-		.pressed = is_pressed,
-	};
-
-	mutex_lock(&key_queue_mutex);
-	queue_add_unit(&key_queue, &ev);
-	mutex_unlock(&key_queue_mutex);
-
-	keyboard_process_queue();
-}
-
-#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-#include "console.h"
-
-static void tablet_mode_change(void)
-{
-	queue_keycode_event(HID_KEYBOARD_TABLET_MODE_SWITCH, tablet_get_mode());
-}
-DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change, HOOK_PRIO_DEFAULT);
-/* Run after tablet_mode_init. */
-DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT+1);
-#endif
-
-void keyboard_state_changed(int row, int col, int is_pressed)
-{
-	uint8_t keycode = keycodes[col][row];
-
-	if (!keycode) {
-		CPRINTF("Unknown key at %d/%d\n", row, col);
-		return;
-	}
-
-	queue_keycode_event(keycode, is_pressed);
-}
-
-void clear_typematic_key(void)
-{ }
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-void usb_hid_keyboard_init(void)
-{
-	if (board_has_keyboard_backlight()) {
-		hid_config_kb.report_desc = report_desc_with_backlight;
-		hid_config_kb.report_size = sizeof(report_desc_with_backlight);
-
-		set_descriptor_patch(USB_DESC_KEYBOARD_BACKLIGHT,
-			&hid_desc_kb.desc[0].wDescriptorLength,
-			sizeof(report_desc_with_backlight));
-	}
-}
-/* This needs to happen before usb_init (HOOK_PRIO_DEFAULT) */
-DECLARE_HOOK(HOOK_INIT, usb_hid_keyboard_init, HOOK_PRIO_DEFAULT - 1);
-#endif
diff --git a/chip/stm32/usb_hid_touchpad.c b/chip/stm32/usb_hid_touchpad.c
deleted file mode 100644
index 0ead660432..0000000000
--- a/chip/stm32/usb_hid_touchpad.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "link_defs.h"
-#include "queue.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "usb_hid.h"
-#include "usb_hid_hw.h"
-#include "usb_hid_touchpad.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-static const int touchpad_debug;
-
-static struct queue const report_queue = QUEUE_NULL(8,
-						struct usb_hid_touchpad_report);
-static struct mutex report_queue_mutex;
-
-#define HID_TOUCHPAD_REPORT_SIZE  sizeof(struct usb_hid_touchpad_report)
-
-/*
- * Touchpad EP interval: Make sure this value is smaller than the typical
- * interrupt interval from the trackpad.
- */
-#define HID_TOUCHPAD_EP_INTERVAL_MS 2 /* ms */
-
-/* Discard TP events older than this time */
-#define EVENT_DISCARD_MAX_TIME (1 * SECOND)
-
-/* HID descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID_TOUCHPAD) = {
-	.bLength = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType = USB_DT_INTERFACE,
-	.bInterfaceNumber = USB_IFACE_HID_TOUCHPAD,
-	.bAlternateSetting = 0,
-	.bNumEndpoints = 1,
-	.bInterfaceClass = USB_CLASS_HID,
-	.bInterfaceSubClass = 0,
-	.bInterfaceProtocol = 0,
-	.iInterface = 0,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = 0x80 | USB_EP_HID_TOUCHPAD,
-	.bmAttributes = 0x03 /* Interrupt endpoint */,
-	.wMaxPacketSize = HID_TOUCHPAD_REPORT_SIZE,
-	.bInterval = HID_TOUCHPAD_EP_INTERVAL_MS /* polling interval */
-};
-
-#define FINGER_USAGE \
-	0x05, 0x0D,        /*   Usage Page (Digitizer) */ \
-	0x09, 0x22,        /*   Usage (Finger) */ \
-	0xA1, 0x02,        /*   Collection (Logical) */ \
-	0x09, 0x47,        /*     Usage (Confidence) */ \
-	0x09, 0x42,        /*     Usage (Tip Switch) */ \
-	0x09, 0x32,        /*     Usage (In Range) */ \
-	0x15, 0x00,        /*     Logical Minimum (0) */ \
-	0x25, 0x01,        /*     Logical Maximum (1) */ \
-	0x75, 0x01,        /*     Report Size (1) */ \
-	0x95, 0x03,        /*     Report Count (3) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x09, 0x51,        /*     Usage (0x51) Contact identifier */ \
-	0x75, 0x04,        /*     Report Size (4) */ \
-	0x95, 0x01,        /*     Report Count (1) */ \
-	0x25, 0x0F,        /*     Logical Maximum (15) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x05, 0x0D,        /*     Usage Page (Digitizer) */ \
-			   /*     Logical Maximum of Pressure */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), \
-	0x75, 0x09,        /*     Report Size (9) */ \
-	0x09, 0x30,        /*     Usage (Tip pressure) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x26, 0xFF, 0x0F,  /*     Logical Maximum (4095) */ \
-	0x75, 0x0C,        /*     Report Size (12) */ \
-	0x09, 0x48,        /*     Usage (WIDTH) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x09, 0x49,        /*     Usage (HEIGHT) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x05, 0x01,        /*     Usage Page (Generic Desktop Ctrls) */ \
-	0x75, 0x0C,        /*     Report Size (12) */ \
-	0x55, 0x0E,        /*     Unit Exponent (-2) */ \
-	0x65, 0x11,        /*     Unit (System: SI Linear, Length: cm) */ \
-	0x09, 0x30,        /*     Usage (X) */ \
-	0x35, 0x00,        /*     Physical Minimum (0) */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), \
-	                   /*     Logical Maximum */ \
-	0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), \
-	                   /*     Physical Maximum (tenth of mm) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), \
-	                   /*     Logical Maximum */ \
-	0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), \
-	                   /*     Physical Maximum (tenth of mm) */ \
-	0x09, 0x31,        /*     Usage (Y) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0xC0               /*   End Collection */
-
-/*
- * HID: Report Descriptor
- * TODO(b/35582031): There are ways to reduce flash usage, as the
- * Finger Usage is repeated 5 times.
- */
-static const uint8_t report_desc[] = {
-	/* Touchpad Collection */
-	0x05, 0x0D,                    /* Usage Page (Digitizer) */
-	0x09, 0x05,                    /* Usage (Touch Pad) */
-	0xA1, 0x01,                    /* Collection (Application) */
-	0x85, REPORT_ID_TOUCHPAD,      /*   Report ID (1, Touch) */
-	/* Finger 0 */
-	FINGER_USAGE,
-	/* Finger 1 */
-	FINGER_USAGE,
-	/* Finger 2 */
-	FINGER_USAGE,
-	/* Finger 3 */
-	FINGER_USAGE,
-	/* Finger 4 */
-	FINGER_USAGE,
-	/* Contact count */
-	0x05, 0x0D,                    /*   Usage Page (Digitizer) */
-	0x09, 0x54,                    /*   Usage (Contact count) */
-	0x25, MAX_FINGERS,             /*   Logical Maximum (MAX_FINGERS) */
-	0x75, 0x07,                    /*   Report Size (7) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
-	/* Button */
-	0x05, 0x01,                    /*   Usage Page(Generic Desktop Ctrls) */
-	0x05, 0x09,                    /*   Usage (Button) */
-	0x19, 0x01,                    /*   Usage Minimum (0x01) */
-	0x29, 0x01,                    /*   Usage Maximum (0x01) */
-	0x15, 0x00,                    /*   Logical Minimum (0) */
-	0x25, 0x01,                    /*   Logical Maximum (1) */
-	0x75, 0x01,                    /*   Report Size (1) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
-	/* Timestamp */
-	0x05, 0x0D,                    /*   Usage Page (Digitizer) */
-	0x55, 0x0C,                    /*   Unit Exponent (-4) */
-	0x66, 0x01, 0x10,              /*   Unit (Seconds) */
-	0x47, 0xFF, 0xFF, 0x00, 0x00,  /*   Physical Maximum (65535) */
-	0x27, 0xFF, 0xFF, 0x00, 0x00,  /*   Logical Maximum (65535) */
-	0x75, 0x10,                    /*   Report Size (16) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x09, 0x56,                    /*   Usage (0x56, Relative Scan Time) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
-
-	0x85, REPORT_ID_DEVICE_CAPS,   /*   Report ID (Device Capabilities) */
-	0x09, 0x55,                    /*   Usage (Contact Count Maximum) */
-	0x09, 0x59,                    /*   Usage (Pad Type) */
-	0x25, 0x0F,                    /*   Logical Maximum (15) */
-	0x75, 0x08,                    /*   Report Size (8) */
-	0x95, 0x02,                    /*   Report Count (2) */
-	0xB1, 0x02,                    /*   Feature (Data,Var,Abs) */
-
-	/* Page 0xFF, usage 0xC5 is device certificate. */
-	0x06, 0x00, 0xFF,              /*   Usage Page (Vendor Defined) */
-	0x85, REPORT_ID_DEVICE_CERT,   /*   Report ID (Device Certification) */
-	0x09, 0xC5,                    /*   Usage (Vendor Usage 0xC5) */
-	0x15, 0x00,                    /*   Logical Minimum (0) */
-	0x26, 0xFF, 0x00,              /*   Logical Maximum (255) */
-	0x75, 0x08,                    /*   Report Size (8) */
-	0x96, 0x00, 0x01,              /*   Report Count (256) */
-	0xB1, 0x02,                    /*   Feature (Data,Var,Abs) */
-
-	0xC0,                          /* End Collection */
-};
-
-/* A 256-byte default blob for the 'device certification status' feature report.
- *
- * TODO(b/113248108): do we need a real certification?
- */
-static const uint8_t device_cert_response[] = {
-	REPORT_ID_DEVICE_CERT,
-
-	0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87,
-	0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88,
-	0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6,
-	0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2,
-	0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43,
-	0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC,
-	0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4,
-	0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71,
-	0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5,
-	0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19,
-	0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9,
-	0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C,
-	0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26,
-	0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B,
-	0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A,
-	0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8,
-	0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1,
-	0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7,
-	0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B,
-	0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35,
-	0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC,
-	0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73,
-	0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF,
-	0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60,
-	0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC,
-	0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13,
-	0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7,
-	0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48,
-	0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89,
-	0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4,
-	0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08,
-	0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2,
-};
-
-/* Device capabilities feature report. */
-static const uint8_t device_caps_response[] = {
-	REPORT_ID_DEVICE_CAPS,
-
-	MAX_FINGERS,            /* Contact Count Maximum */
-	0x00,                   /* Pad Type: Depressible click-pad */
-};
-
-const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD,
-						hid, hid_desc_tp) = {
-	.bLength = 9,
-	.bDescriptorType = USB_HID_DT_HID,
-	.bcdHID = 0x0100,
-	.bCountryCode = 0x00, /* Hardware target country */
-	.bNumDescriptors = 1,
-	.desc = {{
-		.bDescriptorType = USB_HID_DT_REPORT,
-		.wDescriptorLength = sizeof(report_desc)
-	}}
-};
-
-static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram;
-
-/*
- * Write a report to EP, must be called with queue mutex held, and caller
- * must first check that EP is not busy.
- */
-static void write_touchpad_report(struct usb_hid_touchpad_report *report)
-{
-	memcpy_to_usbram((void *) usb_sram_addr(hid_ep_buf),
-			 report, sizeof(*report));
-	/* enable TX */
-	STM32_TOGGLE_EP(USB_EP_HID_TOUCHPAD, EP_TX_MASK, EP_TX_VALID, 0);
-
-	/*
-	 * Wake the host. This is required to prevent a race between EP getting
-	 * reloaded and host suspending the device, as, ideally, we never want
-	 * to have EP loaded during suspend, to avoid reporting stale data.
-	 */
-	usb_wake();
-}
-
-static void hid_touchpad_process_queue(void);
-DECLARE_DEFERRED(hid_touchpad_process_queue);
-
-static void hid_touchpad_process_queue(void)
-{
-	struct usb_hid_touchpad_report report;
-	uint16_t now;
-	int trimming = 0;
-
-	mutex_lock(&report_queue_mutex);
-
-	/* EP is busy, or nothing in queue: do nothing. */
-	if (queue_count(&report_queue) == 0)
-		goto unlock;
-
-	now = __hw_clock_source_read() / USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
-
-	if (usb_is_suspended() ||
-			(STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK)
-				== EP_TX_VALID) {
-		usb_wake();
-
-		/* Let's trim old events from the queue, if any. */
-		trimming = 1;
-	} else {
-		hook_call_deferred(&hid_touchpad_process_queue_data, -1);
-	}
-
-	if (touchpad_debug)
-		CPRINTS("TPQ t=%d (%d)", trimming, queue_count(&report_queue));
-
-	while (queue_count(&report_queue) > 0) {
-		int delta;
-
-		queue_peek_units(&report_queue, &report, 0, 1);
-
-		delta = (int)((uint16_t)(now - report.timestamp))
-				* USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
-
-		if (touchpad_debug)
-			CPRINTS("evt t=%d d=%d", report.timestamp, delta);
-
-		/* Drop old events */
-		if (delta > EVENT_DISCARD_MAX_TIME) {
-			queue_advance_head(&report_queue, 1);
-			continue;
-		}
-
-		if (trimming) {
-			/*
-			 * If we stil fail to resume, this will discard the
-			 * event after the timeout expires.
-			 */
-			hook_call_deferred(&hid_touchpad_process_queue_data,
-					   EVENT_DISCARD_MAX_TIME - delta);
-		} else {
-			queue_advance_head(&report_queue, 1);
-			write_touchpad_report(&report);
-		}
-		break;
-	}
-
-unlock:
-	mutex_unlock(&report_queue_mutex);
-}
-
-void set_touchpad_report(struct usb_hid_touchpad_report *report)
-{
-	static int print_full = 1;
-
-	mutex_lock(&report_queue_mutex);
-
-	/* USB/EP ready and nothing in queue, just write the report. */
-	if (!usb_is_suspended() &&
-	    (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID
-	    && queue_count(&report_queue) == 0) {
-		write_touchpad_report(report);
-		mutex_unlock(&report_queue_mutex);
-		return;
-	}
-
-	/* Else add to queue, dropping oldest event if needed. */
-	if (touchpad_debug)
-		CPRINTS("sTP t=%d", report->timestamp);
-	if (queue_is_full(&report_queue)) {
-		if (print_full)
-			CPRINTF("TP queue full\n");
-		print_full = 0;
-
-		queue_advance_head(&report_queue, 1);
-	} else {
-		print_full = 1;
-	}
-	queue_add_unit(&report_queue, report);
-
-	mutex_unlock(&report_queue_mutex);
-
-	hid_touchpad_process_queue();
-}
-
-static void hid_touchpad_tx(void)
-{
-	hid_tx(USB_EP_HID_TOUCHPAD);
-
-	if (queue_count(&report_queue) > 0)
-		hook_call_deferred(&hid_touchpad_process_queue_data, 0);
-}
-
-static void hid_touchpad_event(enum usb_ep_event evt)
-{
-	if (evt == USB_EVENT_RESET)
-		hid_reset(USB_EP_HID_TOUCHPAD, hid_ep_buf,
-			  HID_TOUCHPAD_REPORT_SIZE, NULL, 0);
-	else if (evt == USB_EVENT_DEVICE_RESUME &&
-			queue_count(&report_queue) > 0)
-		hook_call_deferred(&hid_touchpad_process_queue_data, 0);
-}
-
-USB_DECLARE_EP(USB_EP_HID_TOUCHPAD, hid_touchpad_tx, hid_touchpad_tx,
-	       hid_touchpad_event);
-
-static int get_report(uint8_t report_id, uint8_t report_type,
-		      const uint8_t **buffer_ptr,
-		      int *buffer_size)
-{
-	switch (report_id) {
-	case REPORT_ID_DEVICE_CAPS:
-		*buffer_ptr = device_caps_response;
-		*buffer_size = MIN(sizeof(device_caps_response), *buffer_size);
-		return 0;
-	case REPORT_ID_DEVICE_CERT:
-		*buffer_ptr = device_cert_response;
-		*buffer_size = MIN(sizeof(device_cert_response), *buffer_size);
-		return 0;
-	}
-	return -1;
-}
-
-static const struct usb_hid_config_t hid_config_tp = {
-	.report_desc = report_desc,
-	.report_size = sizeof(report_desc),
-	.hid_desc = &hid_desc_tp,
-	.get_report = get_report,
-};
-
-static int hid_touchpad_iface_request(usb_uint *ep0_buf_rx,
-				      usb_uint *ep0_buf_tx)
-{
-	return hid_iface_request(ep0_buf_rx, ep0_buf_tx, &hid_config_tp);
-}
-USB_DECLARE_IFACE(USB_IFACE_HID_TOUCHPAD, hid_touchpad_iface_request)
diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h
deleted file mode 100644
index 0c75322a7d..0000000000
--- a/chip/stm32/usb_hw.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_HW_H
-#define __CROS_EC_USB_HW_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* Event types for the endpoint event handler. */
-enum usb_ep_event {
-	USB_EVENT_RESET,
-	USB_EVENT_DEVICE_RESUME, /* Device-initiated wake completed. */
-};
-
-#if defined(CHIP_FAMILY_STM32F4)
-#include "usb_dwc_hw.h"
-#else
-
-
-/*
- * The STM32 has dedicated USB RAM visible on the APB1 bus (so all reads &
- * writes are 16-bits wide). The endpoint tables and the data buffers live in
- * this RAM.
-*/
-
-/* Primitive to access the words in USB RAM */
-typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint;
-/* Linker symbol for start of USB RAM */
-extern usb_uint __usb_ram_start[];
-
-/* Attribute to define a buffer variable in USB RAM */
-#define __usb_ram __attribute__((section(".usb_ram.99_data")))
-
-/* Mask for the rx_count to identify the number of bytes in the buffer. */
-#define RX_COUNT_MASK (0x3ff)
-
-struct stm32_endpoint {
-	volatile usb_uint tx_addr;
-	volatile usb_uint tx_count;
-	volatile usb_uint rx_addr;
-	volatile usb_uint rx_count;
-};
-
-extern struct stm32_endpoint btable_ep[];
-
-/* Attribute to put the endpoint table in USB RAM */
-#define __usb_btable __attribute__((section(".usb_ram.00_btable")))
-
-/* Read from USB RAM into a usb_setup_packet struct */
-struct usb_setup_packet;
-void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet);
-
-/*
- * Copy data to and from the USB dedicated RAM and take care of the weird
- * addressing.  These functions correctly handle unaligned accesses to the USB
- * memory.  They have the same prototype as memcpy, allowing them to be used
- * in places that expect memcpy.  The void pointer used to represent a location
- * in the USB dedicated RAM should be the offset in that address space, not the
- * AHB address space.
- *
- * The USB packet RAM is attached to the processor via the AHB2APB bridge.  This
- * bridge performs manipulations of read and write accesses as per the note in
- * section 2.1 of RM0091.  The upshot is that custom memcpy-like routines need
- * to be employed.
- */
-void *memcpy_to_usbram(void *dest, const void *src, size_t n);
-void *memcpy_from_usbram(void *dest, const void *src, size_t n);
-
-/*
- * Descriptor patching support, useful to change a few values in the descriptor
- * (typically, length or bitfields) without having to move descriptors to RAM.
- */
-
-enum usb_desc_patch_type {
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-	USB_DESC_KEYBOARD_BACKLIGHT,
-#endif
-	USB_DESC_PATCH_COUNT,
-};
-
-/*
- * Set patch in table: replace uint16_t at address (STM32 flash) with data.
- *
- * The patches need to be setup before _before_ usb_init is executed (or, at
- * least, before the first call to memcpy_to_usbram_ep0_patch).
- */
-void set_descriptor_patch(enum usb_desc_patch_type type,
-			  const void *address, uint16_t data);
-
-/* Copy to USB ram, applying patches to src as required. */
-void *memcpy_to_usbram_ep0_patch(const void *src, size_t n);
-
-/* Compute the address inside dedicate SRAM for the USB controller */
-#define usb_sram_addr(x) ((x - __usb_ram_start) * sizeof(uint16_t))
-
-/* Helpers for endpoint declaration */
-#define _EP_HANDLER2(num, suffix) CONCAT3(ep_, num, suffix)
-#define _EP_TX_HANDLER(num) _EP_HANDLER2(num, _tx)
-#define _EP_RX_HANDLER(num) _EP_HANDLER2(num, _rx)
-#define _EP_EVENT_HANDLER(num) _EP_HANDLER2(num, _evt)
-/* Used to check function types are correct (attribute alias does not do it) */
-#define _EP_TX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _tx_typecheck)
-#define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck)
-#define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck)
-
-#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)  \
-	void _EP_TX_HANDLER(num)(void)				  \
-		__attribute__ ((alias(STRINGIFY(tx_handler))));	  \
-	void _EP_RX_HANDLER(num)(void)                            \
-		__attribute__ ((alias(STRINGIFY(rx_handler))));	  \
-	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)        \
-		__attribute__ ((alias(STRINGIFY(evt_handler))));  \
-	static __unused void					  \
-	(*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler;	  \
-	static __unused void					  \
-	(*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler;	  \
-	static __unused void					  \
-	(*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\
-			= evt_handler
-
-/* arrays with all endpoint callbacks */
-extern void (*usb_ep_tx[]) (void);
-extern void (*usb_ep_rx[]) (void);
-extern void (*usb_ep_event[]) (enum usb_ep_event evt);
-/* array with interface-specific control request callbacks */
-extern int (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
-
-/*
- * Interface handler returns -1 on error, 0 if it wrote the last chunk of data,
- * or 1 if more data needs to be transferred on the next control request.
- */
-#define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request)
-#define USB_DECLARE_IFACE(num, handler)					\
-	int _IFACE_HANDLER(num)(usb_uint *ep0_buf_rx,			\
-			       usb_uint *epo_buf_tx)			\
-	__attribute__ ((alias(STRINGIFY(handler))));
-
-#endif
-#endif	/* __CROS_EC_USB_HW_H */
diff --git a/chip/stm32/usb_isochronous.c b/chip/stm32/usb_isochronous.c
deleted file mode 100644
index 792507aa75..0000000000
--- a/chip/stm32/usb_isochronous.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "stddef.h"
-#include "common.h"
-#include "config.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_hw.h"
-#include "usb_isochronous.h"
-
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-/*
- * Currently, we only support TX direction for USB isochronous transfer.
- *
- * According to RM0091, isochronous transfer is always double buffered.
- * Addresses of buffers are pointed by `btable_ep[<endpoint>].tx_addr` and
- * `btable_ep[<endpoint>].rx_addr`.
- *
- * DTOG | USB Buffer | App Buffer
- * -----+------------+-----------
- *   0  | tx_addr    | rx_addr
- *   1  | rx_addr    | tx_addr
- *
- * That is, when DTOG bit is 0 (see `get_tx_dtog()`), USB hardware will read
- * from `tx_addr`, and our application can write new data to `rx_addr` at the
- * same time.
- *
- * Number of bytes in each buffer shall be tracked by `tx_count` and `rx_count`
- * respectively.
- *
- * `get_app_addr()`, `set_app_count()` help you to to select the correct
- * variable to use by given DTOG value, which is available by `get_tx_dtog()`.
- */
-
-/*
- * Gets current DTOG value of given `config`.
- */
-static int get_tx_dtog(struct usb_isochronous_config const *config)
-{
-	return !!(STM32_USB_EP(config->endpoint) & EP_TX_DTOG);
-}
-
-/*
- * Gets buffer address that can be used by software (application).
- *
- * The mapping between application buffer address and current TX DTOG value is
- * shown in table above.
- */
-static usb_uint *get_app_addr(struct usb_isochronous_config const *config,
-			      int dtog_value)
-{
-	return config->tx_ram[dtog_value];
-}
-
-/*
- * Sets number of bytes written to application buffer.
- */
-static void set_app_count(struct usb_isochronous_config const *config,
-			  int dtog_value,
-			  usb_uint count)
-{
-	if (dtog_value)
-		btable_ep[config->endpoint].tx_count = count;
-	else
-		btable_ep[config->endpoint].rx_count = count;
-}
-
-int usb_isochronous_write_buffer(
-		struct usb_isochronous_config const *config,
-		const uint8_t *src,
-		size_t n,
-		size_t dst_offset,
-		int *buffer_id,
-		int commit)
-{
-	int dtog_value = get_tx_dtog(config);
-	usb_uint *buffer = get_app_addr(config, dtog_value);
-	uintptr_t ptr = usb_sram_addr(buffer);
-
-	if (*buffer_id == -1)
-		*buffer_id = dtog_value;
-	else if (dtog_value != *buffer_id)
-		return -EC_ERROR_TIMEOUT;
-
-	if (dst_offset > config->tx_size)
-		return -EC_ERROR_INVAL;
-
-	n = MIN(n, config->tx_size - dst_offset);
-	memcpy_to_usbram((void *)(ptr + dst_offset), src, n);
-
-	if (commit)
-		set_app_count(config, dtog_value, dst_offset + n);
-
-	return n;
-}
-
-void usb_isochronous_init(struct usb_isochronous_config const *config)
-{
-	int ep = config->endpoint;
-
-	btable_ep[ep].tx_addr = usb_sram_addr(get_app_addr(config, 1));
-	btable_ep[ep].rx_addr = usb_sram_addr(get_app_addr(config, 0));
-	set_app_count(config, 0, 0);
-	set_app_count(config, 1, 0);
-
-	STM32_USB_EP(ep) = ((ep << 0) | /* Endpoint Addr */
-			    EP_TX_VALID | /* start transmit */
-			    (2 << 9) | /* ISO EP */
-			    EP_RX_DISAB);
-}
-
-void usb_isochronous_event(struct usb_isochronous_config const *config,
-			   enum usb_ep_event evt)
-{
-	if (evt == USB_EVENT_RESET)
-		usb_isochronous_init(config);
-}
-
-void usb_isochronous_tx(struct usb_isochronous_config const *config)
-{
-	/*
-	 * Clear CTR_TX, note that EP_TX_VALID will *NOT* be cleared by
-	 * hardware, so we don't need to toggle it.
-	 */
-	STM32_TOGGLE_EP(config->endpoint, 0, 0, 0);
-	/*
-	 * Clear buffer count for buffer we just transmitted, so we do not
-	 * transmit the data twice.
-	 */
-	set_app_count(config, get_tx_dtog(config), 0);
-
-	config->tx_callback(config);
-}
-
-int usb_isochronous_iface_handler(struct usb_isochronous_config const *config,
-				  usb_uint *ep0_buf_rx,
-				  usb_uint *ep0_buf_tx)
-{
-	int ret = -1;
-
-	if (ep0_buf_rx[0] == (USB_DIR_OUT |
-			      USB_TYPE_STANDARD |
-			      USB_RECIP_INTERFACE |
-			      USB_REQ_SET_INTERFACE << 8)) {
-		ret = config->set_interface(ep0_buf_rx[1], ep0_buf_rx[2]);
-
-		if (ret == 0) {
-			/* ACK */
-			btable_ep[0].tx_count = 0;
-			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-		}
-	}
-	return ret;
-}
diff --git a/chip/stm32/usb_isochronous.h b/chip/stm32/usb_isochronous.h
deleted file mode 100644
index efa4d94ab4..0000000000
--- a/chip/stm32/usb_isochronous.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_ISOCHRONOUS_H
-#define __CROS_EC_USB_ISOCHRONOUS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-struct usb_isochronous_config;
-
-/*
- * Currently, we only support TX direction for USB isochronous transfer.
- */
-
-/*
- * Copy `n` bytes from `src` to USB buffer.
- *
- * We are using double buffering, therefore, we need to write to the buffer that
- * hardware is not currently using.  This function will handle this for you.
- *
- * Sample usage:
- *
- *	int buffer_id = -1;  // initialize to unknown
- *	int ret;
- *	size_t dst_offset = 0, src_offset = 0;
- *	const uint8_t* buf;
- *	size_t buf_size;
- *
- *	while (1) {
- *		buf = ...;
- *		buf_size = ...;
- *		if (no more data) {
- *			buf = NULL;
- *			break;
- *		} else {
- *			ret = usb_isochronous_write_buffer(
- *				config, buf, buf_size, dst_offset,
- *				&buffer_id,
- *				0);
- *			if (ret < 0)
- *				goto FAILED;
- *			dst_offset += ret;
- *			if (ret != buf_size) {
- *				// no more space in TX buffer
- *				src_offset = ret;
- *				break;
- *			}
- *		}
- *	}
- *	// commit
- *	ret = usb_isochronous_write_buffer(
- *		config, NULL, 0, dst_offset,
- *		&buffer_id, 1);
- *	if (ret < 0)
- *		goto FAILED;
- *	if (buf)
- *		// buf[src_offset ... buf_size] haven't been sent yet, send them
- *		// later.
- *
- * On the first invocation, on success, `ret` will be number of bytes that have
- * been written, and `buffer_id` will be 0 or 1, depending on which buffer we
- * are writing.  And commit=0 means there are pending data, so buffer count
- * won't be set yet.
- *
- * On the second invocation, since buffer_id is not -1, we will return an error
- * if hardware has switched to this buffer (it means we spent too much time
- * filling buffer).  And commit=1 means we are done, and buffer count will be
- * set to `dst_offset + num_bytes_written` on success.
- *
- * @return  -EC_ERROR_CODE on failure, or number of bytes written on success.
- */
-int usb_isochronous_write_buffer(
-		struct usb_isochronous_config const *config,
-		const uint8_t *src,
-		size_t n,
-		size_t dst_offset,
-		int *buffer_id,
-		int commit);
-
-struct usb_isochronous_config {
-	int endpoint;
-
-	/*
-	 * On TX complete, this function will be called in **interrupt
-	 * context**.
-	 *
-	 * @param config	the usb_isochronous_config of the USB interface.
-	 */
-	void (*tx_callback)(struct usb_isochronous_config const *config);
-
-	/*
-	 * Received SET_INTERFACE request.
-	 *
-	 * @param  alternate_setting	new bAlternateSetting value.
-	 * @param  interface		interface number.
-	 * @return int			0 for success, -1 for unknown setting.
-	 */
-	int (*set_interface)(usb_uint alternate_setting, usb_uint interface);
-
-	/* USB packet RAM buffer size. */
-	size_t tx_size;
-	/* USB packet RAM buffers. */
-	usb_uint *tx_ram[2];
-};
-
-/* Define an USB isochronous interface */
-#define USB_ISOCHRONOUS_CONFIG_FULL(NAME,				\
-				    INTERFACE,				\
-				    INTERFACE_CLASS,			\
-				    INTERFACE_SUBCLASS,			\
-				    INTERFACE_PROTOCOL,			\
-				    INTERFACE_NAME,			\
-				    ENDPOINT,				\
-				    TX_SIZE,				\
-				    TX_CALLBACK,			\
-				    SET_INTERFACE,			\
-				    NUM_EXTRA_ENDPOINTS)		\
-	BUILD_ASSERT(TX_SIZE > 0);					\
-	BUILD_ASSERT((TX_SIZE <   64 && (TX_SIZE & 0x01) == 0) ||	\
-		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));	\
-	/* Declare buffer */						\
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer_0)[TX_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer_1)[TX_SIZE / 2] __usb_ram; \
-	struct usb_isochronous_config const NAME = {			\
-		.endpoint  = ENDPOINT,					\
-		.tx_callback = TX_CALLBACK,				\
-		.set_interface = SET_INTERFACE,				\
-		.tx_size   = TX_SIZE,					\
-		.tx_ram    = {						\
-			CONCAT2(NAME, _ep_tx_buffer_0),			\
-			CONCAT2(NAME, _ep_tx_buffer_1),			\
-		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 0,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_CONF_DESC(CONCAT3(iface, INTERFACE, _1iface)) = {		\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 1,				\
-		.bNumEndpoints      = 1 + NUM_EXTRA_ENDPOINTS,		\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x01 /* Isochronous IN */,		\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 1,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_isochronous_tx(&NAME);				\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_isochronous_event(&NAME, evt);			\
-	}								\
-	static int CONCAT2(NAME, _handler)(usb_uint *rx, usb_uint *tx)	\
-	{								\
-		return usb_isochronous_iface_handler(&NAME, rx, tx);	\
-	}								\
-	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler));		\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_event));			\
-
-void usb_isochronous_tx(struct usb_isochronous_config const *config);
-void usb_isochronous_event(struct usb_isochronous_config const *config,
-			   enum usb_ep_event event);
-int usb_isochronous_iface_handler(struct usb_isochronous_config const *config,
-				  usb_uint *ep0_buf_rx,
-				  usb_uint *ep0_buf_tx);
-#endif /* __CROS_EC_USB_ISOCHRONOUS_H */
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c
deleted file mode 100644
index 90506d8975..0000000000
--- a/chip/stm32/usb_pd_phy.c
+++ /dev/null
@@ -1,680 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "crc.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-#define PD_DATARATE 300000 /* Hz */
-
-/*
- * Maximum size of a Power Delivery packet (in bits on the wire) :
- *    16-bit header + 0..7 32-bit data objects  (+ 4b5b encoding)
- * 64-bit preamble + SOP (4x 5b) + message in 4b5b + 32-bit CRC + EOP (1x 5b)
- * = 64 + 4*5 + 16 * 5/4 + 7 * 32 * 5/4 + 32 * 5/4 + 5
- */
-#define PD_BIT_LEN 429
-
-#define PD_MAX_RAW_SIZE (PD_BIT_LEN*2)
-
-/* maximum number of consecutive similar bits with Biphase Mark Coding */
-#define MAX_BITS 2
-
-/* alternating bit sequence used for packet preamble : 00 10 11 01 00 ..  */
-#define PD_PREAMBLE 0xB4B4B4B4 /* starts with 0, ends with 1 */
-
-#define TX_CLOCK_DIV ((clock_get_freq() / (2*PD_DATARATE)))
-
-/* threshold for 1 300-khz period */
-#define PERIOD 4
-#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD/2)) & 0xFF) / PERIOD)
-#define PERIOD_THRESHOLD ((PERIOD + 2*PERIOD) / 2)
-
-static struct pd_physical {
-	/* samples for the PD messages */
-	uint32_t raw_samples[DIV_ROUND_UP(PD_MAX_RAW_SIZE, sizeof(uint32_t))];
-
-	/* state of the bit decoder */
-	int d_toggle;
-	int d_lastlen;
-	uint32_t d_last;
-	int b_toggle;
-
-	/* DMA structures for each PD port */
-	struct dma_option dma_tx_option;
-	struct dma_option dma_tim_option;
-
-	/* Pointers to timer register for each port */
-	timer_ctlr_t *tim_tx;
-	timer_ctlr_t *tim_rx;
-} pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* keep track of RX edge timing in order to trigger receive */
-static timestamp_t
-	rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT][PD_RX_TRANSITION_COUNT];
-static int rx_edge_ts_idx[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* keep track of transmit polarity for DMA interrupt */
-static int tx_dma_polarities[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void pd_init_dequeue(int port)
-{
-	/* preamble ends with 1 */
-	pd_phy[port].d_toggle = 0;
-	pd_phy[port].d_last = 0;
-	pd_phy[port].d_lastlen = 0;
-}
-
-static int wait_bits(int port, int nb)
-{
-	int avail;
-	stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX(port));
-
-	avail = dma_bytes_done(rx, PD_MAX_RAW_SIZE);
-	if (avail < nb) { /* no received yet ... */
-		while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb)
-			&& !(pd_phy[port].tim_rx->sr & 4))
-			; /* optimized for latency, not CPU usage ... */
-		if (dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) {
-			CPRINTS("PD TMOUT RX %d/%d",
-				dma_bytes_done(rx, PD_MAX_RAW_SIZE), nb);
-			return -1;
-		}
-	}
-	return nb;
-}
-
-int pd_dequeue_bits(int port, int off, int len, uint32_t *val)
-{
-	int w;
-	uint8_t cnt = 0xff;
-	uint8_t *samples = (uint8_t *)pd_phy[port].raw_samples;
-
-	while ((pd_phy[port].d_lastlen < len) && (off < PD_MAX_RAW_SIZE - 1)) {
-		w = wait_bits(port, off + 2);
-		if (w < 0)
-			goto stream_err;
-		cnt = samples[off] - samples[off-1];
-		if (!cnt || (cnt > 3*PERIOD))
-			goto stream_err;
-		off++;
-		if (cnt <= PERIOD_THRESHOLD) {
-			/*
-			w = wait_bits(port, off + 1);
-			if (w < 0)
-				goto stream_err;
-			*/
-			cnt = samples[off] - samples[off-1];
-			if (cnt >  PERIOD_THRESHOLD)
-				goto stream_err;
-			off++;
-		}
-
-		/* enqueue the bit of the last period */
-		pd_phy[port].d_last = (pd_phy[port].d_last >> 1)
-		       | (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0);
-		pd_phy[port].d_lastlen++;
-	}
-	if (off < PD_MAX_RAW_SIZE) {
-		*val = (pd_phy[port].d_last << (pd_phy[port].d_lastlen - len))
-				>> (32 - len);
-		pd_phy[port].d_lastlen -= len;
-		return off;
-	} else {
-		return -1;
-	}
-stream_err:
-	/* CPRINTS("PD Invalid %d @%d", cnt, off); */
-	return -1;
-}
-
-int pd_find_preamble(int port)
-{
-	int bit;
-	uint8_t *vals = (uint8_t *)pd_phy[port].raw_samples;
-
-	/*
-	 * Detect preamble
-	 * Alternate 1-period 1-period & 2-period.
-	 */
-	uint32_t all = 0;
-	stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX(port));
-
-	for (bit = 1; bit < PD_MAX_RAW_SIZE - 1; bit++) {
-		uint8_t cnt;
-		/* wait if the bit is not received yet ... */
-		if (PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) {
-			while ((PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) &&
-				!(pd_phy[port].tim_rx->sr & 4))
-				;
-			if (pd_phy[port].tim_rx->sr & 4) {
-				CPRINTS("PD TMOUT RX %d/%d",
-					PD_MAX_RAW_SIZE - rx->cndtr, bit);
-				return -1;
-			}
-		}
-		cnt = vals[bit] - vals[bit-1];
-		all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0);
-		if (all == 0x36db6db6)
-			return bit - 1; /* should be SYNC-1 */
-		if (all == 0xF33F3F3F)
-			return PD_RX_ERR_HARD_RESET; /* got HARD-RESET */
-		if (all == 0x3c7fe0ff)
-			return PD_RX_ERR_CABLE_RESET; /* got CABLE-RESET */
-	}
-	return -1;
-}
-
-int pd_write_preamble(int port)
-{
-	uint32_t *msg = pd_phy[port].raw_samples;
-
-	/* 64-bit x2 preamble */
-	msg[0] = PD_PREAMBLE;
-	msg[1] = PD_PREAMBLE;
-	msg[2] = PD_PREAMBLE;
-	msg[3] = PD_PREAMBLE;
-	pd_phy[port].b_toggle = 0x3FF; /* preamble ends with 1 */
-	return 2*64;
-}
-
-int pd_write_sym(int port, int bit_off, uint32_t val10)
-{
-	uint32_t *msg = pd_phy[port].raw_samples;
-	int word_idx = bit_off / 32;
-	int bit_idx = bit_off % 32;
-	uint32_t val = pd_phy[port].b_toggle ^ val10;
-	pd_phy[port].b_toggle = val & 0x200 ? 0x3FF : 0;
-	if (bit_idx <= 22) {
-		if (bit_idx == 0)
-			msg[word_idx] = 0;
-		msg[word_idx] |= val << bit_idx;
-	} else {
-		msg[word_idx] |= val << bit_idx;
-		msg[word_idx+1] = val >> (32 - bit_idx);
-		/* side effect: clear the new word when starting it */
-	}
-	return bit_off + 5*2;
-}
-
-int pd_write_last_edge(int port, int bit_off)
-{
-	uint32_t *msg = pd_phy[port].raw_samples;
-	int word_idx = bit_off / 32;
-	int bit_idx = bit_off % 32;
-
-	if (bit_idx == 0)
-		msg[word_idx] = 0;
-
-	if (!pd_phy[port].b_toggle /* last bit was 0 */) {
-		/* transition to 1, another 1, then 0 */
-		if (bit_idx == 31) {
-			msg[word_idx++] |= 1 << bit_idx;
-			msg[word_idx] = 1;
-		} else {
-			msg[word_idx] |= 3 << bit_idx;
-		}
-	}
-	/* ensure that the trailer is 0 */
-	msg[word_idx+1] = 0;
-
-	return bit_off + 3;
-}
-
-#ifdef CONFIG_COMMON_RUNTIME
-void pd_dump_packet(int port, const char *msg)
-{
-	uint8_t *vals = (uint8_t *)pd_phy[port].raw_samples;
-	int bit;
-
-	CPRINTF("ERR %s:\n000:- ", msg);
-	/* Packet debug output */
-	for (bit = 1; bit <  PD_MAX_RAW_SIZE; bit++) {
-		int cnt = NB_PERIOD(vals[bit-1], vals[bit]);
-		if ((bit & 31) == 0)
-			CPRINTF("\n%03d:", bit);
-		CPRINTF("%1d ", cnt);
-	}
-	CPRINTF("><\n");
-	cflush();
-	for (bit = 0; bit <  PD_MAX_RAW_SIZE; bit++) {
-		if ((bit & 31) == 0)
-			CPRINTF("\n%03d:", bit);
-		CPRINTF("%02x ", vals[bit]);
-	}
-	CPRINTF("||\n");
-	cflush();
-}
-#endif /* CONFIG_COMMON_RUNTIME */
-
-/* --- SPI TX operation --- */
-
-void pd_tx_spi_init(int port)
-{
-	stm32_spi_regs_t *spi = SPI_REGS(port);
-
-	/* Enable Tx DMA for our first transaction */
-	spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_DATASIZE(8);
-
-	/* Enable the slave SPI: LSB first, force NSS, TX only, CPHA */
-	spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST
-		 | STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE
-		 | STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA;
-}
-
-static void tx_dma_done(void *data)
-{
-	int port = (int)data;
-	int polarity = tx_dma_polarities[port];
-	stm32_spi_regs_t *spi = SPI_REGS(port);
-
-	while (spi->sr & STM32_SPI_SR_FTLVL)
-		; /* wait for TX FIFO empty */
-	while (spi->sr & STM32_SPI_SR_BSY)
-		; /* wait for BSY == 0 */
-
-	/* Stop counting */
-	pd_phy[port].tim_tx->cr1 &= ~1;
-
-	/* put TX pins and reference in Hi-Z */
-	pd_tx_disable(port, polarity);
-
-#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS)
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_DMA_TC);
-#endif
-}
-
-int pd_start_tx(int port, int polarity, int bit_len)
-{
-	stm32_dma_chan_t *tx = dma_get_channel(DMAC_SPI_TX(port));
-
-#ifndef CONFIG_USB_PD_TX_PHY_ONLY
-	/* disable RX detection interrupt */
-	pd_rx_disable_monitoring(port);
-
-	/* Check that we are not receiving a frame to avoid collisions */
-	if (pd_rx_started(port))
-		return -5;
-#endif /* !CONFIG_USB_PD_TX_PHY_ONLY */
-
-	/* Initialize spi peripheral to prepare for transmission. */
-	pd_tx_spi_init(port);
-
-	/*
-	 * Set timer to one tick before reset so that the first tick causes
-	 * a rising edge on the output.
-	 */
-	pd_phy[port].tim_tx->cnt = TX_CLOCK_DIV - 1;
-
-	/* update DMA configuration */
-	dma_prepare_tx(&(pd_phy[port].dma_tx_option),
-			DIV_ROUND_UP(bit_len, 8),
-			pd_phy[port].raw_samples);
-	/* Flush data in write buffer so that DMA can get the latest data */
-	asm volatile("dmb;");
-
-	/* Kick off the DMA to send the data */
-	dma_clear_isr(DMAC_SPI_TX(port));
-#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS)
-	tx_dma_polarities[port] = polarity;
-	if (!(pd_phy[port].dma_tx_option.flags & STM32_DMA_CCR_CIRC)) {
-		/* Only enable interrupt if not in circular mode */
-		dma_enable_tc_interrupt_callback(DMAC_SPI_TX(port),
-						 &tx_dma_done,
-						 (void *)port);
-	}
-#endif
-	dma_go(tx);
-
-	/*
-	 * Drive the CC line from the TX block :
-	 * - put SPI function on TX pin.
-	 * - set the low level reference.
-	 * Call this last before enabling timer in order to meet spec on
-	 * timing between enabling TX and clocking out bits.
-	 */
-	pd_tx_enable(port, polarity);
-
-	/* Start counting at 300Khz*/
-	pd_phy[port].tim_tx->cr1 |= 1;
-
-	return bit_len;
-}
-
-void pd_tx_done(int port, int polarity)
-{
-#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS)
-	/* wait for DMA, DMA interrupt will stop the SPI clock */
-	task_wait_event_mask(TASK_EVENT_DMA_TC, DMA_TRANSFER_TIMEOUT_US);
-	dma_disable_tc_interrupt(DMAC_SPI_TX(port));
-#else
-	tx_dma_polarities[port] = polarity;
-	tx_dma_done((void *)port);
-#endif
-
-	/* Reset SPI to clear remaining data in buffer */
-	pd_tx_spi_reset(port);
-}
-
-void pd_tx_set_circular_mode(int port)
-{
-	pd_phy[port].dma_tx_option.flags |= STM32_DMA_CCR_CIRC;
-}
-
-void pd_tx_clear_circular_mode(int port)
-{
-	/* clear the circular mode bit in flag variable */
-	pd_phy[port].dma_tx_option.flags &= ~STM32_DMA_CCR_CIRC;
-	/* disable dma transaction underway */
-	dma_disable(DMAC_SPI_TX(port));
-#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS)
-	tx_dma_done((void *)port);
-#endif
-}
-
-/* --- RX operation using comparator linked to timer --- */
-
-void pd_rx_start(int port)
-{
-	/* start sampling the edges on the CC line using the RX timer */
-	dma_start_rx(&(pd_phy[port].dma_tim_option), PD_MAX_RAW_SIZE,
-			pd_phy[port].raw_samples);
-	/* enable TIM2 DMA requests */
-	pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */;
-	pd_phy[port].tim_rx->sr = 0; /* clear overflows */
-	pd_phy[port].tim_rx->cr1 |= 1;
-}
-
-void pd_rx_complete(int port)
-{
-	/* stop stampling TIM2 */
-	pd_phy[port].tim_rx->cr1 &= ~1;
-	/* stop DMA */
-	dma_disable(DMAC_TIM_RX(port));
-}
-
-int pd_rx_started(int port)
-{
-	/* is the sampling timer running ? */
-	return pd_phy[port].tim_rx->cr1 & 1;
-}
-
-void pd_rx_enable_monitoring(int port)
-{
-	/* clear comparator external interrupt */
-	STM32_EXTI_PR = EXTI_COMP_MASK(port);
-	/* enable comparator external interrupt */
-	STM32_EXTI_IMR |= EXTI_COMP_MASK(port);
-}
-
-void pd_rx_disable_monitoring(int port)
-{
-	/* disable comparator external interrupt */
-	STM32_EXTI_IMR &= ~EXTI_COMP_MASK(port);
-	/* clear comparator external interrupt */
-	STM32_EXTI_PR = EXTI_COMP_MASK(port);
-}
-
-uint64_t get_time_since_last_edge(int port)
-{
-	int prev_idx = (rx_edge_ts_idx[port] == 0) ?
-			PD_RX_TRANSITION_COUNT - 1 :
-			rx_edge_ts_idx[port] - 1;
-	return get_time().val - rx_edge_ts[port][prev_idx].val;
-}
-
-/* detect an edge on the PD RX pin */
-void pd_rx_handler(void)
-{
-	int pending, i;
-	int next_idx;
-	pending = STM32_EXTI_PR;
-
-#ifdef CONFIG_USB_CTVPD
-	/* Charge-Through Side detach event */
-	if (pending & EXTI_COMP2_MASK) {
-		task_wake(PD_PORT_TO_TASK_ID(0));
-		/* Clear interrupt */
-		STM32_EXTI_PR = EXTI_COMP2_MASK;
-		pending &= ~EXTI_COMP2_MASK;
-	}
-#endif
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (pending & EXTI_COMP_MASK(i)) {
-			rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val;
-			next_idx = (rx_edge_ts_idx[i] ==
-					PD_RX_TRANSITION_COUNT - 1) ?
-						0 : rx_edge_ts_idx[i] + 1;
-
-#if defined(CONFIG_LOW_POWER_IDLE) &&                        \
-defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED)
-			/*
-			 * Do not deep sleep while waiting for more edges. For
-			 * most boards, sleep is already disabled due to being
-			 * in PD connected state, but boards which define
-			 * CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED can
-			 * sleep while connected.
-			 */
-			disable_sleep(SLEEP_MASK_USB_PD);
-#endif
-
-			/*
-			 * If we have seen enough edges in a certain amount of
-			 * time, then trigger RX start.
-			 */
-			if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val -
-			     rx_edge_ts[i][next_idx].val)
-			     < PD_RX_TRANSITION_WINDOW) {
-				/* start sampling */
-				pd_rx_start(i);
-				/*
-				 * ignore the comparator IRQ until we are done
-				 * with current message
-				 */
-				pd_rx_disable_monitoring(i);
-				/* trigger the analysis in the task */
-				pd_rx_event(i);
-			} else {
-				/* do not trigger RX start, just clear int */
-				STM32_EXTI_PR = EXTI_COMP_MASK(i);
-			}
-			rx_edge_ts_idx[i] = next_idx;
-		}
-	}
-}
-#ifdef CONFIG_USB_PD_RX_COMP_IRQ
-DECLARE_IRQ(STM32_IRQ_COMP, pd_rx_handler, 1);
-#endif
-
-/* --- release hardware --- */
-void pd_hw_release(int port)
-{
-	__hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 0);
-	__hw_timer_enable_clock(TIM_CLOCK_PD_TX(port), 0);
-	dma_disable(DMAC_SPI_TX(port));
-}
-
-/* --- Startup initialization --- */
-
-void pd_hw_init_rx(int port)
-{
-	struct pd_physical *phy = &pd_phy[port];
-
-	/* configure registers used for timers */
-	phy->tim_rx = (void *)TIM_REG_RX(port);
-
-	/* configure RX DMA */
-	phy->dma_tim_option.channel = DMAC_TIM_RX(port);
-	phy->dma_tim_option.periph = (void *)(TIM_RX_CCR_REG(port));
-	phy->dma_tim_option.flags = STM32_DMA_CCR_MSIZE_8_BIT |
-				     STM32_DMA_CCR_PSIZE_16_BIT;
-
-	/* --- set counter for RX timing : 2.4Mhz rate, free-running --- */
-	__hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 1);
-	/* Timer configuration */
-	phy->tim_rx->cr1 = 0x0000;
-	phy->tim_rx->cr2 = 0x0000;
-	phy->tim_rx->dier = 0x0000;
-	/* Auto-reload value : 16-bit free running counter */
-	phy->tim_rx->arr = 0xFFFF;
-
-	/* Timeout for message receive */
-	phy->tim_rx->ccr[2] = (2400000 / 1000) * USB_PD_RX_TMOUT_US / 1000;
-	/* Timer ICx input configuration */
-	if (TIM_RX_CCR_IDX(port) == 1)
-		phy->tim_rx->ccmr1 |= TIM_CCR_CS << 0;
-	else if (TIM_RX_CCR_IDX(port) == 2)
-		phy->tim_rx->ccmr1 |= TIM_CCR_CS << 8;
-	else if (TIM_RX_CCR_IDX(port) == 4)
-		phy->tim_rx->ccmr2 |= TIM_CCR_CS << 8;
-	else
-		/*  Unsupported RX timer capture input */
-		ASSERT(0);
-
-	phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4);
-	/* configure DMA request on CCRx update */
-	phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */;
-	/* set prescaler to /26 (F=1.2Mhz, T=0.8us) */
-	phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1;
-	/* Reload the pre-scaler and reset the counter (clear CCRx) */
-	phy->tim_rx->egr = 0x0001 | (1 << TIM_RX_CCR_IDX(port));
-	/* clear update event from reloading */
-	phy->tim_rx->sr = 0;
-
-	/* --- DAC configuration for comparator at 850mV --- */
-#ifdef CONFIG_PD_USE_DAC_AS_REF
-	/* Enable DAC interface clock. */
-	STM32_RCC_APB1ENR |= BIT(29);
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-	/* set voltage Vout=0.850V (Vref = 3.0V) */
-	STM32_DAC_DHR12RD = 850 * 4096 / 3000;
-	/* Start DAC channel 1 */
-	STM32_DAC_CR = STM32_DAC_CR_EN1;
-#endif
-
-	/* --- COMP2 as comparator for RX vs Vmid = 850mV --- */
-#ifdef CONFIG_USB_PD_INTERNAL_COMP
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-	/* turn on COMP/SYSCFG */
-	STM32_RCC_APB2ENR |= BIT(0);
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-	/* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */
-	STM32_COMP_CSR = STM32_COMP_CMP1MODE_LSPEED |
-			 STM32_COMP_CMP1INSEL_INM6 |
-			 CMP1OUTSEL |
-			 STM32_COMP_CMP1HYST_HI |
-			 STM32_COMP_CMP2MODE_LSPEED |
-			 STM32_COMP_CMP2INSEL_INM6 |
-			 CMP2OUTSEL |
-			 STM32_COMP_CMP2HYST_HI;
-#elif defined(CHIP_FAMILY_STM32L)
-	STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */
-
-	STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1
-			| STM32_COMP_SPEED_FAST;
-	/* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */
-	STM32_RI_ASCR2 |= BIT(4);
-#else
-#error Unsupported chip family
-#endif
-#endif /* CONFIG_USB_PD_INTERNAL_COMP */
-
-	/* comparator interrupt setup */
-	EXTI_XTSR |= EXTI_COMP_MASK(port);
-	STM32_EXTI_IMR |= EXTI_COMP_MASK(port);
-	task_enable_irq(IRQ_COMP);
-}
-
-void pd_hw_init(int port, enum pd_power_role role)
-{
-	struct pd_physical *phy = &pd_phy[port];
-	uint32_t val;
-
-	/* Initialize all PD pins to default state based on desired role */
-	pd_config_init(port, role);
-
-	/* set 40 MHz pin speed on communication pins */
-	pd_set_pins_speed(port);
-
-	/* --- SPI init --- */
-
-	/* Enable clocks to SPI module */
-	spi_enable_clock(port);
-
-	/* Initialize SPI peripheral registers */
-	pd_tx_spi_init(port);
-
-	/* configure TX DMA */
-	phy->dma_tx_option.channel = DMAC_SPI_TX(port);
-	phy->dma_tx_option.periph = (void *)&SPI_REGS(port)->dr;
-	phy->dma_tx_option.flags = STM32_DMA_CCR_MSIZE_8_BIT |
-				    STM32_DMA_CCR_PSIZE_8_BIT;
-	dma_prepare_tx(&(phy->dma_tx_option), PD_MAX_RAW_SIZE,
-			phy->raw_samples);
-
-	/* configure registers used for timers */
-	phy->tim_tx = (void *)TIM_REG_TX(port);
-
-	/* --- set the TX timer with updates at 600KHz (BMC frequency) --- */
-	__hw_timer_enable_clock(TIM_CLOCK_PD_TX(port), 1);
-	/* Timer configuration */
-	phy->tim_tx->cr1 = 0x0000;
-	phy->tim_tx->cr2 = 0x0000;
-	phy->tim_tx->dier = 0x0000;
-	/* Auto-reload value : 600000 Khz overflow */
-	phy->tim_tx->arr = TX_CLOCK_DIV;
-	/* 50% duty cycle on the output */
-	phy->tim_tx->ccr[TIM_TX_CCR_IDX(port)] = phy->tim_tx->arr / 2;
-	/* Timer channel output configuration */
-	val = (6 << 4) | BIT(3);
-	if ((TIM_TX_CCR_IDX(port) & 1) == 0) /* CH2 or CH4 */
-		val <<= 8;
-	if (TIM_TX_CCR_IDX(port) <= 2)
-		phy->tim_tx->ccmr1 = val;
-	else
-		phy->tim_tx->ccmr2 = val;
-
-	phy->tim_tx->ccer = 1 << ((TIM_TX_CCR_IDX(port) - 1) * 4);
-	phy->tim_tx->bdtr = 0x8000;
-	/* set prescaler to /1 */
-	phy->tim_tx->psc = 0;
-	/* Reload the pre-scaler and reset the counter */
-	phy->tim_tx->egr = 0x0001;
-#ifndef CONFIG_USB_PD_TX_PHY_ONLY
-	/* Configure the reception side : comparators + edge timer + DMA */
-	pd_hw_init_rx(port);
-#endif /* CONFIG_USB_PD_TX_PHY_ONLY */
-
-	CPRINTS("USB PD initialized");
-}
-
-void pd_set_clock(int port, int freq)
-{
-	pd_phy[port].tim_tx->arr = clock_get_freq() / (2*freq);
-}
diff --git a/chip/stm32/usb_power.c b/chip/stm32/usb_power.c
deleted file mode 100644
index 24dbff06cd..0000000000
--- a/chip/stm32/usb_power.c
+++ /dev/null
@@ -1,733 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "dma.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "timer.h"
-#include "usb_descriptor.h"
-#include "usb_power.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-static int usb_power_init_inas(struct usb_power_config const *config);
-static int usb_power_read(struct usb_power_config const *config);
-static int usb_power_write_line(struct usb_power_config const *config);
-
-void usb_power_deferred_rx(struct usb_power_config const *config)
-{
-	int rx_count = rx_ep_pending(config->endpoint);
-
-	/* Handle an incoming command if available */
-	if (rx_count)
-		usb_power_read(config);
-}
-
-void usb_power_deferred_tx(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-
-	if (!tx_ep_is_ready(config->endpoint))
-		return;
-
-	/* We've replied, set up the next read. */
-	if (!rx_ep_is_active(config->endpoint)) {
-		/* Remove any active dma region from output buffer */
-		state->reports_xmit_active = state->reports_tail;
-
-		/* Wait for the next command */
-		usb_read_ep(config->endpoint,
-			config->ep->out_databuffer_max,
-			config->ep->out_databuffer);
-		return;
-	}
-}
-
-/* Reset stream */
-void usb_power_event(struct usb_power_config const *config,
-		enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	config->ep->out_databuffer = config->state->rx_buf;
-	config->ep->out_databuffer_max = sizeof(config->state->rx_buf);
-	config->ep->in_databuffer = config->state->tx_buf;
-	config->ep->in_databuffer_max = sizeof(config->state->tx_buf);
-
-	epN_reset(config->endpoint);
-
-	/* Flush any queued data */
-	hook_call_deferred(config->ep->rx_deferred, 0);
-	hook_call_deferred(config->ep->tx_deferred, 0);
-}
-
-
-/* Write one or more power records to USB */
-static int usb_power_write_line(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-	struct usb_power_report *r = (struct usb_power_report *)(
-		state->reports_data_area +
-		(USB_POWER_RECORD_SIZE(state->ina_count)
-		* state->reports_tail));
-	/* status + size + timestamps + power list */
-	size_t bytes = USB_POWER_RECORD_SIZE(state->ina_count);
-
-	/* Check if queue has active data. */
-	if (config->state->reports_head != config->state->reports_tail) {
-		int recordcount = 1;
-
-		/* We'll concatenate all the upcoming recrds. */
-		if (config->state->reports_tail < config->state->reports_head)
-			recordcount = config->state->reports_head -
-				      config->state->reports_tail;
-		else
-			recordcount = state->max_cached -
-				      config->state->reports_tail;
-
-		state->reports_xmit_active = state->reports_tail;
-		state->reports_tail = (state->reports_tail + recordcount) %
-			state->max_cached;
-
-		usb_write_ep(config->endpoint, bytes * recordcount, r);
-		return bytes;
-	}
-
-	return 0;
-}
-
-
-static int usb_power_state_reset(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-
-	state->state = USB_POWER_STATE_OFF;
-	state->reports_head = 0;
-	state->reports_tail = 0;
-	state->reports_xmit_active = 0;
-
-	CPRINTS("[RESET] STATE -> OFF");
-	return USB_POWER_SUCCESS;
-}
-
-
-static int usb_power_state_stop(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-
-	/* Only a valid transition from CAPTURING */
-	if (state->state != USB_POWER_STATE_CAPTURING) {
-		CPRINTS("[STOP] Error not capturing.");
-		return USB_POWER_ERROR_NOT_CAPTURING;
-	}
-
-	state->state = USB_POWER_STATE_OFF;
-	state->reports_head = 0;
-	state->reports_tail = 0;
-	state->reports_xmit_active = 0;
-	state->stride_bytes = 0;
-	CPRINTS("[STOP] STATE: CAPTURING -> OFF");
-	return USB_POWER_SUCCESS;
-}
-
-
-
-static int usb_power_state_start(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
-{
-	struct usb_power_state *state = config->state;
-	int integration_us = cmd->start.integration_us;
-	int ret;
-
-	if (state->state != USB_POWER_STATE_SETUP) {
-		CPRINTS("[START] Error not setup.");
-		return USB_POWER_ERROR_NOT_SETUP;
-	}
-
-	if (count != sizeof(struct usb_power_command_start)) {
-		CPRINTS("[START] Error count %d is not %d", (int)count,
-			sizeof(struct usb_power_command_start));
-		return USB_POWER_ERROR_READ_SIZE;
-	}
-
-	if (integration_us == 0) {
-		CPRINTS("[START] integration_us cannot be 0");
-		return USB_POWER_ERROR_UNKNOWN;
-	}
-
-	/* Calculate the reports array */
-	state->stride_bytes = USB_POWER_RECORD_SIZE(state->ina_count);
-	state->max_cached = USB_POWER_MAX_CACHED(state->ina_count);
-
-	state->integration_us = integration_us;
-	ret = usb_power_init_inas(config);
-
-	if (ret)
-		return USB_POWER_ERROR_INVAL;
-
-	state->state = USB_POWER_STATE_CAPTURING;
-	CPRINTS("[START] STATE: SETUP -> CAPTURING %dus", integration_us);
-
-	/* Find our starting time. */
-	config->state->base_time = get_time().val;
-
-	hook_call_deferred(config->deferred_cap, state->integration_us);
-	return USB_POWER_SUCCESS;
-}
-
-
-static int usb_power_state_settime(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
-{
-	if (count != sizeof(struct usb_power_command_settime)) {
-		CPRINTS("[SETTIME] Error: count %d is not %d",
-			(int)count, sizeof(struct usb_power_command_settime));
-		return USB_POWER_ERROR_READ_SIZE;
-	}
-
-	/* Find the offset between microcontroller clock and host clock. */
-	if (cmd->settime.time)
-		config->state->wall_offset = cmd->settime.time - get_time().val;
-	else
-		config->state->wall_offset = 0;
-
-	return USB_POWER_SUCCESS;
-}
-
-
-static int usb_power_state_addina(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
-{
-	struct usb_power_state *state = config->state;
-	struct usb_power_ina_cfg *ina;
-	int i;
-
-	/* Only valid from OFF or SETUP */
-	if ((state->state != USB_POWER_STATE_OFF) &&
-	    (state->state != USB_POWER_STATE_SETUP)) {
-		CPRINTS("[ADDINA] Error incorrect state.");
-		return USB_POWER_ERROR_NOT_SETUP;
-	}
-
-	if (count != sizeof(struct usb_power_command_addina)) {
-		CPRINTS("[ADDINA] Error count %d is not %d",
-			(int)count, sizeof(struct usb_power_command_addina));
-		return USB_POWER_ERROR_READ_SIZE;
-	}
-
-	if (state->ina_count >= USB_POWER_MAX_READ_COUNT) {
-		CPRINTS("[ADDINA] Error INA list full");
-		return USB_POWER_ERROR_FULL;
-	}
-
-	/* Transition to SETUP state if necessary and clear INA data */
-	if (state->state == USB_POWER_STATE_OFF) {
-		state->state = USB_POWER_STATE_SETUP;
-		state->ina_count = 0;
-	}
-
-	if ((cmd->addina.type < USBP_INA231_POWER) ||
-	    (cmd->addina.type > USBP_INA231_SHUNTV)) {
-		CPRINTS("[ADDINA] Error INA type 0x%x invalid",
-			(int)(cmd->addina.type));
-		return USB_POWER_ERROR_INVAL;
-	}
-
-	if (cmd->addina.rs == 0) {
-		CPRINTS("[ADDINA] Error INA resistance cannot be zero!");
-		return USB_POWER_ERROR_INVAL;
-	}
-
-	/* Select INA to configure */
-	ina = state->ina_cfg + state->ina_count;
-
-	ina->port = cmd->addina.port;
-	ina->addr_flags = cmd->addina.addr_flags;
-	ina->rs = cmd->addina.rs;
-	ina->type = cmd->addina.type;
-
-	/*
-	 * INAs can be shared, in that they will have various values
-	 * (and therefore registers) read from them each cycle, including
-	 * power, voltage, current. If only a single value is read,
-	 * we an use i2c_readagain for faster transactions as we don't
-	 * have to respecify the address.
-	 */
-	ina->shared = 0;
-#ifdef USB_POWER_VERBOSE
-	ina->shared = 1;
-#endif
-
-	/* Check if shared with previously configured INAs. */
-	for (i = 0; i < state->ina_count; i++) {
-		struct usb_power_ina_cfg *tmp = state->ina_cfg + i;
-
-		if ((tmp->port == ina->port) &&
-		    (tmp->addr_flags == ina->addr_flags)) {
-			ina->shared = 1;
-			tmp->shared = 1;
-		}
-	}
-
-	state->ina_count += 1;
-	return USB_POWER_SUCCESS;
-}
-
-static int usb_power_read(struct usb_power_config const *config)
-{
-	/*
-	 * If there is a USB packet waiting we process it and generate a
-	 * response.
-	 */
-	uint8_t count		= rx_ep_pending(config->endpoint);
-	uint8_t result		= USB_POWER_SUCCESS;
-	union usb_power_command_data *cmd =
-		(union usb_power_command_data *)config->ep->out_databuffer;
-
-	struct usb_power_state *state = config->state;
-	struct dwc_usb_ep *ep = config->ep;
-
-	/* Bytes to return */
-	int in_msgsize = 1;
-
-	if (count < 2)
-		return EC_ERROR_INVAL;
-
-	/* State machine. */
-	switch (cmd->command) {
-	case USB_POWER_CMD_RESET:
-		result = usb_power_state_reset(config);
-		break;
-
-	case USB_POWER_CMD_STOP:
-		result = usb_power_state_stop(config);
-		break;
-
-	case USB_POWER_CMD_START:
-		result = usb_power_state_start(config, cmd, count);
-		if (result == USB_POWER_SUCCESS) {
-			/* Send back actual integration time. */
-			ep->in_databuffer[1] =
-				(state->integration_us >> 0) & 0xff;
-			ep->in_databuffer[2] =
-				(state->integration_us >> 8) & 0xff;
-			ep->in_databuffer[3] =
-				(state->integration_us >> 16) & 0xff;
-			ep->in_databuffer[4] =
-				(state->integration_us >> 24) & 0xff;
-			in_msgsize += 4;
-		}
-		break;
-
-	case USB_POWER_CMD_ADDINA:
-		result = usb_power_state_addina(config, cmd, count);
-		break;
-
-	case USB_POWER_CMD_SETTIME:
-		result = usb_power_state_settime(config, cmd, count);
-		break;
-
-	case USB_POWER_CMD_NEXT:
-		if (state->state == USB_POWER_STATE_CAPTURING) {
-			int ret;
-
-			ret = usb_power_write_line(config);
-			if (ret)
-				return EC_SUCCESS;
-
-			result = USB_POWER_ERROR_BUSY;
-		} else {
-			CPRINTS("[STOP] Error not capturing.");
-			result = USB_POWER_ERROR_NOT_CAPTURING;
-		}
-		break;
-
-	default:
-		CPRINTS("[ERROR] Unknown command 0x%04x", (int)cmd->command);
-		result = USB_POWER_ERROR_UNKNOWN;
-		break;
-	}
-
-	/* Return result code if applicable. */
-	ep->in_databuffer[0] = result;
-
-	usb_write_ep(config->endpoint, in_msgsize, ep->in_databuffer);
-
-	return EC_SUCCESS;
-}
-
-
-
-/******************************************************************************
- * INA231 interface.
- * List the registers and fields here.
- * TODO(nsanders): combine with the currently incompatible common INA drivers.
- */
-
-#define INA231_REG_CONF 0
-#define INA231_REG_RSHV 1
-#define INA231_REG_BUSV 2
-#define INA231_REG_PWR  3
-#define INA231_REG_CURR 4
-#define INA231_REG_CAL  5
-#define INA231_REG_EN   6
-
-
-#define INA231_CONF_AVG(val)		(((int)(val & 0x7)) << 9)
-#define INA231_CONF_BUS_TIME(val)	(((int)(val & 0x7)) << 6)
-#define INA231_CONF_SHUNT_TIME(val)	(((int)(val & 0x7)) << 3)
-#define INA231_CONF_MODE(val)		(((int)(val & 0x7)) << 0)
-#define INA231_MODE_OFF			0x0
-#define INA231_MODE_SHUNT		0x5
-#define INA231_MODE_BUS			0x6
-#define INA231_MODE_BOTH		0x7
-
-int reg_type_mapping(enum usb_power_ina_type ina_type)
-{
-	switch (ina_type) {
-	case USBP_INA231_POWER:
-		return INA231_REG_PWR;
-	case USBP_INA231_BUSV:
-		return INA231_REG_BUSV;
-	case USBP_INA231_CURRENT:
-		return INA231_REG_CURR;
-	case USBP_INA231_SHUNTV:
-		return INA231_REG_RSHV;
-
-	default:
-		return INA231_REG_CONF;
-	}
-}
-
-uint16_t ina2xx_readagain(uint8_t port, uint16_t slave_addr_flags)
-{
-	int res;
-	uint16_t val;
-
-	res = i2c_xfer(port, slave_addr_flags,
-		       NULL, 0, (uint8_t *)&val, sizeof(uint16_t));
-
-	if (res) {
-		CPRINTS("INA2XX I2C readagain failed p:%d a:%02x",
-			(int)port, (int)I2C_STRIP_FLAGS(slave_addr_flags));
-		return 0x0bad;
-	}
-	return (val >> 8) | ((val & 0xff) << 8);
-}
-
-
-uint16_t ina2xx_read(uint8_t port, uint16_t slave_addr_flags,
-		     uint8_t reg)
-{
-	int res;
-	int val;
-
-	res = i2c_read16(port, slave_addr_flags, reg, &val);
-	if (res) {
-		CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x",
-			(int)port, (int)I2C_STRIP_FLAGS(slave_addr_flags),
-			(int)reg);
-		return 0x0bad;
-	}
-	return (val >> 8) | ((val & 0xff) << 8);
-}
-
-int ina2xx_write(uint8_t port, uint16_t slave_addr_flags,
-		 uint8_t reg, uint16_t val)
-{
-	int res;
-	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
-
-	res = i2c_write16(port, slave_addr_flags, reg, be_val);
-	if (res)
-		CPRINTS("INA2XX I2C write failed");
-	return res;
-}
-
-
-
-/******************************************************************************
- * Background tasks
- *
- * Here we setup the INAs and read them at the specified interval.
- * INA samples are stored in a ringbuffer that can be fetched using the
- * USB commands.
- */
-
-/* INA231 integration and averaging time presets, indexed by register value */
-#define NELEMS(x)  (sizeof(x) / sizeof((x)[0]))
-static const int average_settings[] = {
-	1, 4, 16, 64, 128, 256, 512, 1024};
-static const int conversion_time_us[] =	{
-	140, 204, 332, 588, 1100, 2116, 4156, 8244};
-
-static int usb_power_init_inas(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-	int i;
-	int shunt_time = 0;
-	int avg = 0;
-	int target_us = state->integration_us;
-
-	if (state->state != USB_POWER_STATE_SETUP) {
-		CPRINTS("[ERROR] usb_power_init_inas while not SETUP");
-		return -1;
-	}
-
-	/* Find an INA preset integration time less than specified */
-	while (shunt_time < (NELEMS(conversion_time_us) - 1)) {
-		if (conversion_time_us[shunt_time + 1] > target_us)
-			break;
-		shunt_time++;
-	}
-
-	/* Find an averaging setting from the INA presets that fits. */
-	while (avg < (NELEMS(average_settings) - 1)) {
-		if ((conversion_time_us[shunt_time] *
-		     average_settings[avg + 1])
-		    > target_us)
-			break;
-		avg++;
-	}
-
-	state->integration_us =
-		conversion_time_us[shunt_time] * average_settings[avg];
-
-	for (i = 0; i < state->ina_count; i++) {
-		int value;
-		int ret;
-		struct usb_power_ina_cfg *ina = state->ina_cfg + i;
-
-#ifdef USB_POWER_VERBOSE
-		{
-		int conf, cal;
-
-		conf = ina2xx_read(ina->port, ina->addr_flags,
-				   INA231_REG_CONF);
-		cal = ina2xx_read(ina->port, ina->addr_flags,
-				  INA231_REG_CAL);
-		CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			conf, cal);
-		}
-#endif
-		/*
-		 * Calculate INA231 Calibration register
-		 * CurrentLSB = uA per div = 80mV / (Rsh * 2^15)
-		 * CurrentLSB 100x uA = 100x 80000000nV / (Rsh mOhm * 0x8000)
-		 */
-		/* TODO: allow voltage readings if no sense resistor. */
-		if (ina->rs == 0)
-			return -1;
-
-		ina->scale = (100 * (80000000 / 0x8000)) / ina->rs;
-
-		/*
-		 * CAL = .00512 / (CurrentLSB * Rsh)
-		 * CAL = 5120000 / (uA * mOhm)
-		 */
-		if (ina->scale == 0)
-			return -1;
-		value = (5120000 * 100) / (ina->scale * ina->rs);
-		ret = ina2xx_write(ina->port, ina->addr_flags,
-				   INA231_REG_CAL, value);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("[CAP] usb_power_init_inas CAL FAIL: %d", ret);
-			return ret;
-		}
-#ifdef USB_POWER_VERBOSE
-		{
-		int actual;
-
-		actual = ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_CAL);
-		CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x",
-			ina->scale / 100, ina->scale*25/100, value, actual);
-		}
-#endif
-		/* Conversion time, shunt + bus, set average. */
-		value = INA231_CONF_MODE(INA231_MODE_BOTH) |
-			INA231_CONF_SHUNT_TIME(shunt_time) |
-			INA231_CONF_BUS_TIME(shunt_time) |
-			INA231_CONF_AVG(avg);
-		ret = ina2xx_write(ina->port, ina->addr_flags,
-				   INA231_REG_CONF, value);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("[CAP] usb_power_init_inas CONF FAIL: %d", ret);
-			return ret;
-		}
-#ifdef USB_POWER_VERBOSE
-		{
-		int actual;
-
-		actual = ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_CONF);
-		CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			value, actual);
-		}
-#endif
-#ifdef USB_POWER_VERBOSE
-		{
-		int busv_mv =
-			(ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_BUSV)
-			 * 125) / 100;
-
-		CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			busv_mv);
-		}
-#endif
-		/* Initialize read from power register. This register address
-		 * will be cached and all ina2xx_readagain() calls will read
-		 * from the same address.
-		 */
-		ina2xx_read(ina->port, ina->addr_flags,
-			    reg_type_mapping(ina->type));
-#ifdef USB_POWER_VERBOSE
-		CPRINTS("[CAP] %d (%d,0x%02x): type:%d", (int)(ina->type));
-#endif
-	}
-
-	return EC_SUCCESS;
-}
-
-
-/*
- * Read each INA's power integration measurement.
- *
- * INAs recall the most recent address, so no register access write is
- * necessary, simply read 16 bits from each INA and fill the result into
- * the power record.
- *
- * If the power record ringbuffer is full, fail with USB_POWER_ERROR_OVERFLOW.
- */
-static int usb_power_get_samples(struct usb_power_config const *config)
-{
-	uint64_t time = get_time().val;
-	struct usb_power_state *state = config->state;
-	struct usb_power_report *r = (struct usb_power_report *)(
-		state->reports_data_area +
-		(USB_POWER_RECORD_SIZE(state->ina_count)
-		* state->reports_head));
-	struct usb_power_ina_cfg *inas = state->ina_cfg;
-	int i;
-
-	/* TODO(nsanders): Would we prefer to evict oldest? */
-	if (((state->reports_head + 1) % USB_POWER_MAX_CACHED(state->ina_count))
-	    == state->reports_xmit_active) {
-		CPRINTS("Overflow! h:%d a:%d t:%d (%d)",
-			state->reports_head, state->reports_xmit_active,
-			state->reports_tail,
-			USB_POWER_MAX_CACHED(state->ina_count));
-		return USB_POWER_ERROR_OVERFLOW;
-	}
-
-	r->status = USB_POWER_SUCCESS;
-	r->size = state->ina_count;
-	if (config->state->wall_offset)
-		time = time + config->state->wall_offset;
-	else
-		time -= config->state->base_time;
-	r->timestamp = time;
-
-	for (i = 0; i < state->ina_count; i++) {
-		int regval;
-		struct usb_power_ina_cfg *ina = inas + i;
-
-		/* Read INA231.
-		 * ina2xx_read(ina->port, ina->addr, INA231_REG_PWR);
-		 * Readagain cached this address so we'll save an I2C
-		 * transaction.
-		 */
-		if (ina->shared)
-			regval = ina2xx_read(ina->port, ina->addr_flags,
-					reg_type_mapping(ina->type));
-		else
-			regval = ina2xx_readagain(ina->port,
-						  ina->addr_flags);
-		r->power[i] = regval;
-#ifdef USB_POWER_VERBOSE
-		{
-		int current;
-		int power;
-		int voltage;
-		int bvoltage;
-
-		voltage = ina2xx_read(ina->port, ina->addr_flags,
-				      INA231_REG_RSHV);
-		bvoltage = ina2xx_read(ina->port, ina->addr_flags,
-				       INA231_REG_BUSV);
-		current = ina2xx_read(ina->port, ina->addr_flags,
-				      INA231_REG_CURR);
-		power = ina2xx_read(ina->port, ina->addr_flags,
-				    INA231_REG_PWR);
-		{
-		int uV = ((int)voltage * 25) / 10;
-		int mV = ((int)bvoltage * 125) / 100;
-		int uA = (uV * 1000) / ina->rs;
-		int CuA = (((int)current * ina->scale) / 100);
-		int uW = (((int)power * ina->scale*25)/100);
-
-		CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			uV/1000, ina->rs, uA/1000);
-		CPRINTS("[CAP] %duV %dmV %duA %dCuA "
-			"%duW v:%04x, b:%04x, p:%04x",
-			uV, mV, uA, CuA, uW, voltage, bvoltage, power);
-		}
-		}
-#endif
-	}
-
-	/* Mark this slot as used. */
-	state->reports_head = (state->reports_head + 1) %
-		USB_POWER_MAX_CACHED(state->ina_count);
-
-	return EC_SUCCESS;
-}
-
-/*
- * This function is called every [interval] uS, and reads the accumulated
- * values of the INAs, and reschedules itself for the next interval.
- *
- * It will stop collecting frames if a ringbuffer overflow is
- * detected, or a stop request is seen..
- */
-void usb_power_deferred_cap(struct usb_power_config const *config)
-{
-	int ret;
-	uint64_t timeout = get_time().val + config->state->integration_us;
-	uint64_t timein;
-
-	/* Exit if we have stopped capturing in the meantime. */
-	if (config->state->state != USB_POWER_STATE_CAPTURING)
-		return;
-
-	/* Get samples for this timeslice */
-	ret = usb_power_get_samples(config);
-	if (ret == USB_POWER_ERROR_OVERFLOW) {
-		CPRINTS("[CAP] usb_power_deferred_cap: OVERFLOW");
-		return;
-	}
-
-	/* Calculate time remaining until next slice. */
-	timein = get_time().val;
-	if (timeout > timein)
-		timeout = timeout - timein;
-	else
-		timeout = 0;
-
-	/* Double check if we are still capturing. */
-	if (config->state->state == USB_POWER_STATE_CAPTURING)
-		hook_call_deferred(config->deferred_cap, timeout);
-}
-
diff --git a/chip/stm32/usb_power.h b/chip/stm32/usb_power.h
deleted file mode 100644
index 68b7f75ca2..0000000000
--- a/chip/stm32/usb_power.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_POWER_H
-#define __CROS_EC_USB_POWER_H
-
-/* Power monitoring USB interface for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/*
- * Command:
- *
- *     Commands are a 16 bit value, with optional command dependent data.
- *     +--------------+-----------------------------------+
- *     | command : 2B |					  |
- *     +--------------+-----------------------------------+
- *
- *     Responses are an 8 bit status value, with optional data.
- *     +----------+-----------------------------------+
- *     | res : 1B |				      |
- *     +----------+-----------------------------------+
- *
- *     reset:	0x0000
- *     +--------+
- *     | 0x0000 |
- *     +--------+
- *
- *     stop:	0x0001
- *     +--------+
- *     | 0x0001 |
- *     +--------+
- *
- *     addina:	0x0002
- *     +--------+--------------------------+-------------+--------------+-----------+--------+
- *     | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: extra | 4B: Rs |
- *     +--------+--------------------------+-------------+--------------+-----------+--------+
- *
- *     start:	0x0003
- *     +--------+----------------------+
- *     | 0x0003 | 4B: integration time |
- *     +--------+----------------------+
- *
- *     start response:
- *     +-------------+-----------------------------+
- *     | status : 1B | Actual integration time: 4B |
- *     +-------------+-----------------------------+
- *
- *     next:	0x0004
- *     +--------+
- *     | 0x0004 |
- *     +--------+
- *
- *     next response:
- *     +-------------+----------+----------------+----------------------------+
- *     | status : 1B | size: 1B | timestamp : 8B | payload : may span packets |
- *     +-------------+----------+----------------+----------------------------+
- *
- *     settime:	0x0005
- *     +--------+---------------------+
- *     | 0x0005 | 8B: Wall clock time |
- *     +--------+---------------------+
- *
- *
- *     Status: 1 byte status
- *
- *	 0x00: Success
- *	 0x01: I2C Error
- *	 0x02: Overflow
- *	     This can happen if data acquisition is faster than USB reads.
- *	 0x03: No configuration set.
- *	 0x04: No active capture.
- *	 0x05: Timeout.
- *	 0x06: Busy, outgoing queue is empty.
- *	 0x07: Size, command length is incorrect for command type..
- *	 0x08: More INAs specified than board limit.
- *	 0x09: Invalid input, eg. invalid INA type.
- *	 0x80: Unknown error
- *
- *     size: 1 byte incoming INA reads count
- *
- *     timestamp: 4 byte timestamp associated with these samples
- *
- */
-
-/* 8b status field. */
-enum usb_power_error {
-	USB_POWER_SUCCESS		= 0x00,
-	USB_POWER_ERROR_I2C		= 0x01,
-	USB_POWER_ERROR_OVERFLOW	= 0x02,
-	USB_POWER_ERROR_NOT_SETUP	= 0x03,
-	USB_POWER_ERROR_NOT_CAPTURING	= 0x04,
-	USB_POWER_ERROR_TIMEOUT		= 0x05,
-	USB_POWER_ERROR_BUSY		= 0x06,
-	USB_POWER_ERROR_READ_SIZE	= 0x07,
-	USB_POWER_ERROR_FULL		= 0x08,
-	USB_POWER_ERROR_INVAL		= 0x09,
-	USB_POWER_ERROR_UNKNOWN		= 0x80,
-};
-
-/* 16b command field. */
-enum usb_power_command {
-	USB_POWER_CMD_RESET	= 0x0000,
-	USB_POWER_CMD_STOP	= 0x0001,
-	USB_POWER_CMD_ADDINA	= 0x0002,
-	USB_POWER_CMD_START	= 0x0003,
-	USB_POWER_CMD_NEXT	= 0x0004,
-	USB_POWER_CMD_SETTIME	= 0x0005,
-};
-
-/* Addina "INA Type" field. */
-enum usb_power_ina_type {
-	USBP_INA231_POWER	= 0x01,
-	USBP_INA231_BUSV	= 0x02,
-	USBP_INA231_CURRENT	= 0x03,
-	USBP_INA231_SHUNTV	= 0x04,
-};
-
-/* Internal state machine values */
-enum usb_power_states {
-	USB_POWER_STATE_OFF	= 0,
-	USB_POWER_STATE_SETUP,
-	USB_POWER_STATE_CAPTURING,
-};
-
-#define USB_POWER_MAX_READ_COUNT 64
-#define USB_POWER_MIN_CACHED 10
-
-struct usb_power_ina_cfg {
-	/*
-	 * Relevant config for INA usage.
-	 */
-	/* i2c bus. TODO(nsanders): specify what kind of index. */
-	int port;
-	/* 7-bit i2c addr */
-	uint16_t addr_flags;
-
-	/* Base voltage. mV */
-	int mv;
-
-	/* Shunt resistor. mOhm */
-	int rs;
-	/* uA per div as reported from INA */
-	int scale;
-
-	/* Is this power, shunt voltage, bus voltage, or current? */
-	int type;
-	/* Is this INA returning the one value only and can use readagain? */
-	int shared;
-};
-
-
-struct __attribute__ ((__packed__)) usb_power_report {
-	uint8_t status;
-	uint8_t size;
-	uint64_t timestamp;
-	uint16_t power[USB_POWER_MAX_READ_COUNT];
-};
-
-/* Must be 4 byte aligned */
-#define USB_POWER_RECORD_SIZE(ina_count)				\
-	((((sizeof(struct usb_power_report)				\
-	- (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT)			\
-	+ (sizeof(uint16_t) * (ina_count))) + 3) / 4) * 4)
-
-#define USB_POWER_DATA_SIZE						\
-	(sizeof(struct usb_power_report) * (USB_POWER_MIN_CACHED + 1))
-#define USB_POWER_MAX_CACHED(ina_count)					\
-	(USB_POWER_DATA_SIZE / USB_POWER_RECORD_SIZE(ina_count))
-
-
-struct usb_power_state {
-	/*
-	 * The power data acquisition must be setup, then started, in order to
-	 * return data.
-	 * States are OFF, SETUP, and CAPTURING.
-	 */
-	int state;
-
-	struct usb_power_ina_cfg ina_cfg[USB_POWER_MAX_READ_COUNT];
-	int ina_count;
-	int integration_us;
-	/* Start of sampling. */
-	uint64_t base_time;
-	/* Offset between microcontroller timestamp and host wall clock. */
-	uint64_t wall_offset;
-
-	/* Cached power reports for sending on USB. */
-	/* Actual backing data for variable sized record queue. */
-	uint8_t reports_data_area[USB_POWER_DATA_SIZE];
-	/* Size of power report struct for this config. */
-	int stride_bytes;
-	/* Max power records storeable in this config */
-	int max_cached;
-	struct usb_power_report *reports;
-
-	/* Head and tail pointers for output ringbuffer */
-	/* Head adds newly probed power data. */
-	int reports_head;
-	/* Tail contains oldest records not yet sent to USB */
-	int reports_tail;
-	/* Xmit_active -> tail is active usb DMA */
-	int reports_xmit_active;
-
-	/* Pointers to RAM. */
-	uint8_t rx_buf[USB_MAX_PACKET_SIZE];
-	uint8_t tx_buf[USB_MAX_PACKET_SIZE * 4];
-};
-
-
-/*
- * Compile time Per-USB gpio configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB gpio.  This structure binds
- * together all information required to operate a USB gpio.
- */
-struct usb_power_config {
-	/* In RAM state of the USB power interface. */
-	struct usb_power_state *state;
-
-	/* USB endpoint state.*/
-	struct dwc_usb_ep *ep;
-
-	/* Interface and endpoint indicies. */
-	int interface;
-	int endpoint;
-
-	/* Deferred function to call to handle power request. */
-	const struct deferred_data *deferred;
-	const struct deferred_data *deferred_cap;
-};
-
-struct __attribute__ ((__packed__)) usb_power_command_start {
-	uint16_t command;
-	uint32_t integration_us;
-};
-
-struct __attribute__ ((__packed__)) usb_power_command_addina {
-	uint16_t command;
-	uint8_t port;
-	uint8_t type;
-	uint8_t addr_flags;
-	uint8_t extra;
-	uint32_t rs;
-};
-
-struct __attribute__ ((__packed__)) usb_power_command_settime {
-	uint16_t command;
-	uint64_t time;
-};
-
-union usb_power_command_data {
-	uint16_t command;
-	struct usb_power_command_start start;
-	struct usb_power_command_addina addina;
-	struct usb_power_command_settime settime;
-};
-
-
-/*
- * Convenience macro for defining a USB INA Power driver.
- *
- * NAME is used to construct the names of the trampoline functions and the
- * usb_power_config struct, the latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * driver.
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- */
-#define USB_POWER_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       ENDPOINT)					\
-	static void CONCAT2(NAME, _deferred_tx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));			\
-	static void CONCAT2(NAME, _deferred_rx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));			\
-	static void CONCAT2(NAME, _deferred_cap_)(void);		\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_));		\
-	struct usb_power_state CONCAT2(NAME, _state_) = {		\
-		.state = USB_POWER_STATE_OFF,				\
-		.ina_count = 0,						\
-		.integration_us = 0,					\
-		.reports_head = 0,					\
-		.reports_tail = 0,					\
-		.wall_offset = 0,					\
-	};								\
-	static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {		\
-		.max_packet = USB_MAX_PACKET_SIZE,			\
-		.tx_fifo = ENDPOINT,					\
-		.out_pending = 0,					\
-		.out_data = 0,						\
-		.out_databuffer = 0,					\
-		.out_databuffer_max = 0,				\
-		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),	\
-		.in_packets = 0,					\
-		.in_pending = 0,					\
-		.in_data = 0,						\
-		.in_databuffer = 0,					\
-		.in_databuffer_max = 0,					\
-		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),	\
-	};								\
-	struct usb_power_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state_),			\
-		.ep	= &CONCAT2(NAME, _ep_ctl),			\
-		.interface = INTERFACE,					\
-		.endpoint  = ENDPOINT,					\
-		.deferred_cap  = &CONCAT2(NAME, _deferred_cap__data),	\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength	    = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER,	\
-		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER,	\
-		.iInterface	 = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength	  = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval	= 1,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength	  = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval	= 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx_)   (void) { usb_epN_tx(ENDPOINT); } \
-	static void CONCAT2(NAME, _ep_rx_)   (void) { usb_epN_rx(ENDPOINT); } \
-	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)	\
-	{								\
-			usb_power_event(&NAME, evt);			\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx_),				\
-		       CONCAT2(NAME, _ep_rx_),				\
-		       CONCAT2(NAME, _ep_event_));			\
-	static void CONCAT2(NAME, _deferred_tx_)(void)			\
-	{ usb_power_deferred_tx(&NAME); }				\
-	static void CONCAT2(NAME, _deferred_rx_)(void)			\
-	{ usb_power_deferred_rx(&NAME); }				\
-	static void CONCAT2(NAME, _deferred_cap_)(void)			\
-	{ usb_power_deferred_cap(&NAME); }
-
-
-/*
- * Handle power request in a deferred callback.
- */
-void usb_power_deferred_rx(struct usb_power_config const *config);
-void usb_power_deferred_tx(struct usb_power_config const *config);
-void usb_power_deferred_cap(struct usb_power_config const *config);
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB GPIO driver.
- */
-void usb_power_tx(struct usb_power_config const *config);
-void usb_power_rx(struct usb_power_config const *config);
-void usb_power_event(struct usb_power_config const *config,
-		enum usb_ep_event evt);
-
-
-
-
-#endif /* __CROS_EC_USB_DWC_POWER_H */
-
diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c
deleted file mode 100644
index 54caae015e..0000000000
--- a/chip/stm32/usb_spi.c
+++ /dev/null
@@ -1,627 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "spi.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "usb_spi.h"
-#include "util.h"
-
-/* Forward declare platform specific functions. */
-static bool usb_spi_received_packet(struct usb_spi_config const *config);
-static bool usb_spi_transmitted_packet(struct usb_spi_config const *config);
-static void usb_spi_read_packet(struct usb_spi_config const *config,
-			struct usb_spi_packet_ctx *packet);
-static void usb_spi_write_packet(struct usb_spi_config const *config,
-			struct usb_spi_packet_ctx *packet);
-
-/*
- * Map EC error codes to USB_SPI error codes.
- *
- * @param error     EC error code
- *
- * @returns         USB SPI error code based on the mapping.
- */
-static int16_t usb_spi_map_error(int error)
-{
-	switch (error) {
-	case EC_SUCCESS:       return USB_SPI_SUCCESS;
-	case EC_ERROR_TIMEOUT: return USB_SPI_TIMEOUT;
-	case EC_ERROR_BUSY:    return USB_SPI_BUSY;
-	default:               return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff);
-	}
-}
-
-/*
- * Read data into the receive buffer.
- *
- * @param dst       Destination receive context we are writing data to.
- * @param src       Source packet context we are reading data from.
- *
- * @returns         USB_SPI_RX_DATA_OVERFLOW if the source packet is too large
- */
-static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst,
-				const struct usb_spi_packet_ctx *src)
-{
-	size_t max_read_length = dst->transfer_size - dst->transfer_index;
-	size_t bytes_in_buffer = src->packet_size - src->header_size;
-	const uint8_t *packet_buffer = src->bytes + src->header_size;
-
-	if (bytes_in_buffer > max_read_length) {
-		/*
-		 * An error occurred, we should not receive more data than
-		 * the buffer can support.
-		 */
-		return USB_SPI_RX_DATA_OVERFLOW;
-	}
-	memcpy(dst->buffer + dst->transfer_index, packet_buffer,
-		bytes_in_buffer);
-
-	dst->transfer_index += bytes_in_buffer;
-	return USB_SPI_SUCCESS;
-}
-
-/*
- * Fill the USB packet with data from the transmit buffer.
- *
- * @param dst       Destination packet context we are writing data to.
- * @param src       Source transmit context we are reading data from.
- */
-static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst,
-				struct usb_spi_transfer_ctx *src)
-{
-	size_t transfer_size = src->transfer_size - src->transfer_index;
-	size_t max_buffer_size = USB_MAX_PACKET_SIZE - dst->header_size;
-	uint8_t *packet_buffer = dst->bytes + dst->header_size;
-
-	if (transfer_size > max_buffer_size)
-		transfer_size = max_buffer_size;
-
-	memcpy(packet_buffer, src->buffer + src->transfer_index, transfer_size);
-
-	dst->packet_size = dst->header_size + transfer_size;
-	src->transfer_index += transfer_size;
-}
-
-/*
- * Setup the USB SPI state to start a new SPI transfer.
- *
- * @param config        USB SPI config
- * @param write_count   Number of bytes to write in the SPI transfer
- * @param read_count    Number of bytes to read in the SPI transfer
- */
-static void usb_spi_setup_transfer(struct usb_spi_config const *config,
-				size_t write_count, size_t read_count)
-{
-	/* Reset any status code. */
-	config->state->status_code = USB_SPI_SUCCESS;
-
-	/* Reset the write and read counts. */
-	config->state->spi_write_ctx.transfer_size = write_count;
-	config->state->spi_write_ctx.transfer_index = 0;
-	config->state->spi_read_ctx.transfer_size = read_count;
-	config->state->spi_read_ctx.transfer_index = 0;
-}
-
-/*
- * Handle USB events that will reset the USB SPI state.
- *
- * @param config        USB SPI config
- */
-static void usb_spi_reset_interface(struct usb_spi_config const *config)
-{
-	/* Setup a 0 byte transfer to clear the contexts. */
-	usb_spi_setup_transfer(config, 0, 0);
-}
-
-/*
- * Returns if the response transfer is in progress.
- *
- * @param config        USB SPI config
- *
- * @returns         	True if a response transfer is in progress.
- */
-static bool usb_spi_response_in_progress(struct usb_spi_config const *config)
-{
-	if ((config->state->mode == USB_SPI_MODE_START_RESPONSE) ||
-	    (config->state->mode == USB_SPI_MODE_CONTINUE_RESPONSE)) {
-		return true;
-	}
-	return false;
-}
-
-/*
- * Prep the state to construct a new response. This sets the transfer
- * contexts, the mode, and status code. If a non-zero status code is
- * returned, then no payload will be transmitted.
- *
- * @param config        USB SPI config
- * @param status_code	status code to set for the response.
- */
-static void setup_transfer_response(struct usb_spi_config const *config,
-				uint16_t status_code)
-{
-	config->state->status_code = status_code;
-	config->state->spi_read_ctx.transfer_index = 0;
-	config->state->mode = USB_SPI_MODE_START_RESPONSE;
-
-	/* If an error occurred, transmit an empty start packet. */
-	if (status_code != USB_SPI_SUCCESS)
-		config->state->spi_read_ctx.transfer_size = 0;
-}
-
-/*
- * Constructs the response packet containing the SPI configuration.
- *
- * @param config        USB SPI config
- * @param packet        Packet buffer we will be transmitting.
- */
-static void create_spi_config_response(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
-{
-	/* Construct the response packet. */
-	packet->rsp_config.packet_id = USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG;
-	packet->rsp_config.max_write_count = USB_SPI_MAX_WRITE_COUNT;
-	packet->rsp_config.max_read_count = USB_SPI_MAX_READ_COUNT;
-	/* Set the feature flags. */
-	packet->rsp_config.feature_bitmap = 0;
-#ifndef CONFIG_SPI_HALFDUPLEX
-	packet->rsp_config.feature_bitmap |=
-		USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED;
-#endif
-	packet->packet_size =
-		sizeof(struct usb_spi_response_configuration_v2);
-}
-
-/*
- * If we have a transfer response in progress, this will construct the
- * next entry. If no transfer is in progress or if we are unable to
- * create the next packet, it will not modify tx_packet.
- *
- * @param config        USB SPI config
- * @param packet        Packet buffer we will be transmitting.
- */
-static void usb_spi_create_spi_transfer_response(
-				struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *transmit_packet)
-{
-
-	if (!usb_spi_response_in_progress(config))
-		return;
-
-	if (config->state->spi_read_ctx.transfer_index == 0) {
-
-		/* Transmit the first packet with the status code. */
-		transmit_packet->header_size =
-			offsetof(struct usb_spi_response_v2, data);
-		transmit_packet->rsp_start.packet_id =
-			USB_SPI_PKT_ID_RSP_TRANSFER_START;
-		transmit_packet->rsp_start.status_code =
-			config->state->status_code;
-
-		usb_spi_fill_usb_packet(transmit_packet,
-			&config->state->spi_read_ctx);
-	} else if (config->state->spi_read_ctx.transfer_index <
-		config->state->spi_read_ctx.transfer_size) {
-
-		/* Transmit the continue packets. */
-		transmit_packet->header_size =
-			offsetof(struct usb_spi_continue_v2, data);
-		transmit_packet->rsp_continue.packet_id =
-			USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE;
-		transmit_packet->rsp_continue.data_index =
-			config->state->spi_read_ctx.transfer_index;
-
-		usb_spi_fill_usb_packet(transmit_packet,
-			&config->state->spi_read_ctx);
-	}
-	if (config->state->spi_read_ctx.transfer_index <
-		config->state->spi_read_ctx.transfer_size) {
-		config->state->mode = USB_SPI_MODE_CONTINUE_RESPONSE;
-	} else {
-		config->state->mode = USB_SPI_MODE_IDLE;
-	}
-}
-
-/*
- * Process the rx packet.
- *
- * @param config        USB SPI config
- * @param packet        Received packet to process.
- */
-static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
-{
-	if (packet->packet_size < USB_SPI_MIN_PACKET_SIZE) {
-		/* No valid packet exists smaller than the packet id. */
-		setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET);
-		return;
-	}
-	/* Reset the mode until we've processed the packet. */
-	config->state->mode = USB_SPI_MODE_IDLE;
-
-	switch (packet->packet_id) {
-	case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG:
-	{
-		/* The host requires the SPI configuration. */
-		config->state->mode = USB_SPI_MODE_SEND_CONFIGURATION;
-		break;
-	}
-	case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE:
-	{
-		/*
-		 * The host has requested the device restart the last response.
-		 * This is used to recover from lost USB packets without
-		 * duplicating SPI transfers.
-		 */
-		setup_transfer_response(config, config->state->status_code);
-		break;
-	}
-	case USB_SPI_PKT_ID_CMD_TRANSFER_START:
-	{
-		/* The host started a new USB SPI transfer */
-		size_t write_count = packet->cmd_start.write_count;
-		size_t read_count = packet->cmd_start.read_count;
-
-		if (!config->state->enabled) {
-			setup_transfer_response(config, USB_SPI_DISABLED);
-		} else if (write_count > USB_SPI_MAX_WRITE_COUNT) {
-			setup_transfer_response(config,
-				USB_SPI_WRITE_COUNT_INVALID);
-		} else if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) {
-#ifndef CONFIG_SPI_HALFDUPLEX
-			/* Full duplex mode is not supported on this device. */
-			setup_transfer_response(config,
-				USB_SPI_UNSUPPORTED_FULL_DUPLEX);
-#endif
-		} else if (read_count > USB_SPI_MAX_READ_COUNT &&
-				read_count != USB_SPI_FULL_DUPLEX_ENABLED) {
-			setup_transfer_response(config,
-				USB_SPI_READ_COUNT_INVALID);
-		} else {
-		        usb_spi_setup_transfer(config, write_count, read_count);
-		        packet->header_size =
-		        	offsetof(struct usb_spi_command_v2, data);
-		        config->state->status_code = usb_spi_read_usb_packet(
-		        	&config->state->spi_write_ctx, packet);
-		}
-
-		/* Send responses if we encountered an error. */
-		if (config->state->status_code != USB_SPI_SUCCESS) {
-			setup_transfer_response(config,
-				config->state->status_code);
-			break;
-		}
-
-		/* Start the SPI transfer when we've read all data. */
-		if (config->state->spi_write_ctx.transfer_index ==
-				config->state->spi_write_ctx.transfer_size) {
-			config->state->mode = USB_SPI_MODE_START_SPI;
-		}
-
-		break;
-	}
-	case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE:
-	{
-		/*
-		 * The host has sent a continue packet for the SPI transfer
-		 * which contains additional data payload.
-		 */
-		packet->header_size =
-			offsetof(struct usb_spi_continue_v2, data);
-		if (config->state->status_code == USB_SPI_SUCCESS) {
-			config->state->status_code = usb_spi_read_usb_packet(
-					&config->state->spi_write_ctx, packet);
-		}
-
-		/* Send responses if we encountered an error. */
-		if (config->state->status_code != USB_SPI_SUCCESS) {
-			setup_transfer_response(config,
-				config->state->status_code);
-			break;
-		}
-
-		/* Start the SPI transfer when we've read all data. */
-		if (config->state->spi_write_ctx.transfer_index ==
-				config->state->spi_write_ctx.transfer_size) {
-			config->state->mode = USB_SPI_MODE_START_SPI;
-		}
-
-		break;
-	}
-	default:
-	{
-		/* An unknown USB packet was delivered. */
-		setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET);
-		break;
-	}
-	}
-}
-
-/* Deferred function to handle state changes, process USB SPI packets,
- * and construct responses.
- *
- * @param config        USB SPI config
- */
-void usb_spi_deferred(struct usb_spi_config const *config)
-{
-	int enabled;
-	struct usb_spi_packet_ctx *receive_packet =
-		&config->state->receive_packet;
-	struct usb_spi_packet_ctx *transmit_packet =
-		&config->state->transmit_packet;
-	transmit_packet->packet_size = 0;
-
-	if (config->flags & USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE)
-		enabled = config->state->enabled_device;
-	else
-		enabled = config->state->enabled_device &&
-			  config->state->enabled_host;
-
-	/*
-	 * If our overall enabled state has changed we call the board specific
-	 * enable or disable routines and save our new state.
-	 */
-	if (enabled != config->state->enabled) {
-		if (enabled) usb_spi_board_enable(config);
-		else         usb_spi_board_disable(config);
-
-		config->state->enabled = enabled;
-	}
-
-	/* Read any packets from the endpoint. */
-
-	usb_spi_read_packet(config, receive_packet);
-	if (receive_packet->packet_size) {
-		usb_spi_process_rx_packet(config, receive_packet);
-	}
-
-	/* Need to send the USB SPI configuration */
-	if (config->state->mode == USB_SPI_MODE_SEND_CONFIGURATION) {
-		create_spi_config_response(config, transmit_packet);
-		usb_spi_write_packet(config, transmit_packet);
-		config->state->mode = USB_SPI_MODE_IDLE;
-		return;
-	}
-
-	/* Start a new SPI transfer. */
-	if (config->state->mode == USB_SPI_MODE_START_SPI) {
-		uint16_t status_code;
-		int read_count = config->state->spi_read_ctx.transfer_size;
-#ifndef CONFIG_SPI_HALFDUPLEX
-		/*
-		 * Handle the full duplex mode on supported platforms.
-		 * The read count is equal to the write count.
-		 */
-		if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) {
-			config->state->spi_read_ctx.transfer_size =
-				config->state->spi_write_ctx.transfer_size;
-			read_count = SPI_READBACK_ALL;
-		}
-#endif
-		status_code = spi_transaction(SPI_FLASH_DEVICE,
-			config->state->spi_write_ctx.buffer,
-			config->state->spi_write_ctx.transfer_size,
-			config->state->spi_read_ctx.buffer,
-			read_count);
-
-		/* Cast the EC status code to USB SPI and start the response. */
-		status_code = usb_spi_map_error(status_code);
-		setup_transfer_response(config, status_code);
-	}
-
-	if (usb_spi_response_in_progress(config) &&
-			usb_spi_transmitted_packet(config)) {
-		usb_spi_create_spi_transfer_response(config, transmit_packet);
-		usb_spi_write_packet(config, transmit_packet);
-	}
-}
-
-/*
- * Sets which SPI modes will be enabled
- *
- * @param config        USB SPI config
- * @param enabled       usb_spi_request indicating which SPI mode is enabled.
- */
-void usb_spi_enable(struct usb_spi_config const *config, int enabled)
-{
-	config->state->enabled_device = enabled;
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-/*
- * STM32 Platform: Receive the data from the endpoint into the packet and
- *  mark the endpoint as ready to accept more data.
- *
- * @param config        USB SPI config
- * @param packet        Destination packet used to store the endpoint data.
- */
-static void usb_spi_read_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
-{
-	size_t packet_size;
-
-	if (!usb_spi_received_packet(config)) {
-		/* No data is present on the endpoint. */
-		packet->packet_size = 0;
-		return;
-	}
-
-	/* Copy bytes from endpoint memory. */
-	packet_size = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK;
-	memcpy_from_usbram(packet->bytes,
-		(void *)usb_sram_addr(config->ep_rx_ram), packet_size);
-	packet->packet_size = packet_size;
-	/* Set endpoint as valid for accepting new packet. */
-	STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0);
-}
-
-/*
- * STM32 Platform: Transmit data from the packet to the endpoint buffer.
- *  If a packet is written, the endpoint will be marked valid for transmitting.
- *
- * @param config        USB SPI config
- * @param packet        Source packet we will write to the endpoint data.
- */
-static void usb_spi_write_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
-{
-	if (packet->packet_size == 0)
-		return;
-
-	/* Copy bytes to endpoint memory. */
-	memcpy_to_usbram((void *)usb_sram_addr(config->ep_tx_ram),
-		packet->bytes, packet->packet_size);
-	btable_ep[config->endpoint].tx_count = packet->packet_size;
-
-	/* Mark the packet as having no data. */
-	packet->packet_size = 0;
-
-	/* Set endpoint as valid for transmitting new packet. */
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0);
-}
-
-/*
- * STM32 Platform: Returns the RX endpoint status
- *
- * @param config        USB SPI config
- *
- * @returns             Returns true when the RX endpoint has a packet.
- */
-static bool usb_spi_received_packet(struct usb_spi_config const *config)
-{
-	return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) != EP_RX_VALID;
-}
-
-/* STM32 Platform: Returns the TX endpoint status
- *
- * @param config        USB SPI config
- *
- * @returns             Returns true when the TX endpoint transmitted
- *                      the packet written.
- */
-static bool usb_spi_transmitted_packet(struct usb_spi_config const *config)
-{
-	return (STM32_USB_EP(config->endpoint) & EP_TX_MASK) != EP_TX_VALID;
-}
-
-/* STM32 Platform: Handle interrupt for USB data received.
- *
- * @param config        USB SPI config
- */
-void usb_spi_rx(struct usb_spi_config const *config)
-{
-	/*
-	 * We need to set both the TX and RX endpoints to NAK to prevent
-	 * transfers. The protocol requires responses to follow a command, but
-	 * the USB host will request the next packet from the TX endpoint
-	 * before the USB SPI has updated the memory in the buffer. By setting
-	 * it to NAK in the ISR, it will not perform a transfer until the
-	 * next packet is ready.
-	 *
-	 * This has a side effect of disabling the endpoint interrupts until
-	 * they are set to valid or a USB reset events occurs.
-	 */
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_RX_MASK, EP_TX_RX_NAK, 0);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-/*
- * STM32 Platform: Handle interrupt for USB data transmitted.
- *
- * @param config        USB SPI config
- */
-void usb_spi_tx(struct usb_spi_config const *config)
-{
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_NAK, 0);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-/*
- * STM32 Platform: Handle interrupt for USB events
- *
- * @param config        USB SPI config
- * @param evt           USB event
- */
-void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt)
-{
-	int endpoint;
-
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	endpoint = config->endpoint;
-
-	usb_spi_reset_interface(config);
-
-	btable_ep[endpoint].tx_addr  = usb_sram_addr(config->ep_tx_ram);
-	btable_ep[endpoint].tx_count = 0;
-
-	btable_ep[endpoint].rx_addr  = usb_sram_addr(config->ep_rx_ram);
-	btable_ep[endpoint].rx_count =
-		0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
-
-	STM32_USB_EP(endpoint) = ((endpoint <<  0) | /* Endpoint Addr*/
-				  (2        <<  4) | /* TX NAK */
-				  (0        <<  9) | /* Bulk EP */
-				  (3        << 12)); /* RX Valid */
-}
-
-/*
- * STM32 Platform: Handle control transfers.
- *
- * @param config        USB SPI config
- * @param rx_buf        Contains setup packet
- * @param tx_buf        unused
- */
-int usb_spi_interface(struct usb_spi_config const *config,
-		      usb_uint *rx_buf,
-		      usb_uint *tx_buf)
-{
-	struct usb_setup_packet setup;
-
-	usb_read_setup_packet(rx_buf, &setup);
-
-	if (setup.bmRequestType != (USB_DIR_OUT |
-				    USB_TYPE_VENDOR |
-				    USB_RECIP_INTERFACE))
-		return 1;
-
-	if (setup.wValue  != 0 ||
-	    setup.wIndex  != config->interface ||
-	    setup.wLength != 0)
-		return 1;
-
-	switch (setup.bRequest) {
-	case USB_SPI_REQ_ENABLE:
-		config->state->enabled_host = 1;
-		break;
-
-	case USB_SPI_REQ_DISABLE:
-		config->state->enabled_host = 0;
-		break;
-
-	default: return 1;
-	}
-
-	/*
-	 * Our state has changed, call the deferred function to handle the
-	 * state change.
-	 */
-	if (!(config->flags & USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE))
-		hook_call_deferred(config->deferred, 0);
-
-	usb_spi_reset_interface(config);
-
-	btable_ep[0].tx_count = 0;
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, EP_STATUS_OUT);
-	return 0;
-}
diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h
deleted file mode 100644
index 591975234d..0000000000
--- a/chip/stm32/usb_spi.h
+++ /dev/null
@@ -1,594 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_SPI_H
-#define __CROS_EC_USB_SPI_H
-
-/* STM32 USB SPI driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/*
- * This SPI flash programming interface is designed to talk to a Chromium OS
- * device over a Raiden USB connection.
- *
- * USB SPI Version 2:
- *
- *     USB SPI version 2 adds support for larger SPI transfers and reduces the
- *     number of USB packets transferred. This improves performance when
- *     writing or reading large chunks of memory from a device. A packet ID
- *     field is used to distinguish the different packet types. Additional
- *     packets have been included to query the device for its configuration
- *     allowing the interface to be used on platforms with different SPI
- *     limitations. It includes validation and a packet to recover from the
- *     situations where USB packets are lost.
- *
- *     The USB SPI hosts which support packet version 2 are backwards compatible
- *     and use the bInterfaceProtocol field to identify which type of target
- *     they are connected to.
- *
- *
- * Example: USB SPI request with 128 byte write and 0 byte read.
- *
- *      Packet #1 Host to Device:
- *           packet id   = USB_SPI_PKT_ID_CMD_TRANSFER_START
- *           write count = 128
- *           read count  = 0
- *           payload     = First 58 bytes from the write buffer,
- *                            starting at byte 0 in the buffer
- *           packet size = 64 bytes
- *
- *      Packet #2 Host to Device:
- *           packet id   = USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE
- *           data index  = 58
- *           payload     = Next 60 bytes from the write buffer,
- *                           starting at byte 58 in the buffer
- *           packet size = 64 bytes
- *
- *      Packet #3 Host to Device:
- *           packet id   = USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE
- *           data index  = 118
- *           payload     = Next 10 bytes from the write buffer,
- *                           starting at byte 118 in the buffer
- *           packet size = 14 bytes
- *
- *      Packet #4 Device to Host:
- *           packet id   = USB_SPI_PKT_ID_RSP_TRANSFER_START
- *           status code = status code from device
- *           payload     = 0 bytes
- *           packet size = 4 bytes
- *
- * Example: USB SPI request with 2 byte write and 100 byte read.
- *
- *      Packet #1 Host to Device:
- *           packet id   = USB_SPI_PKT_ID_CMD_TRANSFER_START
- *           write count = 2
- *           read count  = 100
- *           payload     = The 2 byte write buffer
- *           packet size = 8 bytes
- *
- *      Packet #2 Device to Host:
- *           packet id   = USB_SPI_PKT_ID_RSP_TRANSFER_START
- *           status code = status code from device
- *           payload     = First 60 bytes from the read buffer,
- *                            starting at byte 0 in the buffer
- *           packet size = 64 bytes
- *
- *      Packet #3 Device to Host:
- *           packet id   = USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE
- *           data index  = 60
- *           payload     = Next 40 bytes from the read buffer,
- *                           starting at byte 60 in the buffer
- *           packet size = 44 bytes
- *
- *
- * Message Packets:
- *
- * Command Start Packet (Host to Device):
- *
- *      Start of the USB SPI command, contains the number of bytes to write
- *      and read on SPI and up to the first 58 bytes of write payload.
- *      Longer writes will use the continue packets with packet id
- *      USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE to transmit the remaining data.
- *
- *     +----------------+------------------+-----------------+---------------+
- *     | packet id : 2B | write count : 2B | read count : 2B | w.p. : <= 58B |
- *     +----------------+------------------+-----------------+---------------+
- *
- *     packet id:     2 byte enum defined by packet_id_type
- *                    Valid values packet id = USB_SPI_PKT_ID_CMD_TRANSFER_START
- *
- *     write count:   2 byte, zero based count of bytes to write
- *
- *     read count:    2 byte, zero based count of bytes to read
- *                    UINT16_MAX indicates full duplex mode with a read count
- *                    equal to the write count.
- *
- *     write payload: Up to 58 bytes of data to write to SPI, the total
- *                    length of all TX packets must match write count.
- *                    Due to data alignment constraints, this must be an
- *                    even number of bytes unless this is the final packet.
- *
- *
- * Response Start Packet (Device to Host):
- *
- *      Start of the USB SPI response, contains the status code and up to
- *      the first 60 bytes of read payload. Longer reads will use the
- *      continue packets with packet id USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE
- *      to transmit the remaining data.
- *
- *     +----------------+------------------+-----------------------+
- *     | packet id : 2B | status code : 2B | read payload : <= 60B |
- *     +----------------+------------------+-----------------------+
- *
- *     packet id:     2 byte enum defined by packet_id_type
- *                    Valid values packet id = USB_SPI_PKT_ID_RSP_TRANSFER_START
- *
- *     status code: 2 byte status code
- *         0x0000: Success
- *         0x0001: SPI timeout
- *         0x0002: Busy, try again
- *             This can happen if someone else has acquired the shared memory
- *             buffer that the SPI driver uses as /dev/null
- *         0x0003: Write count invalid. The byte limit is platform specific
- *             and is set during the configure USB SPI response.
- *         0x0004: Read count invalid. The byte limit is platform specific
- *             and is set during the configure USB SPI response.
- *         0x0005: The SPI bridge is disabled.
- *         0x0006: The RX continue packet's data index is invalid. This
- *             can indicate a USB transfer failure to the device.
- *         0x0007: The RX endpoint has received more data than write count.
- *             This can indicate a USB transfer failure to the device.
- *         0x0008: An unexpected packet arrived that the device could not
- *             process.
- *         0x0009: The device does not support full duplex mode.
- *         0x8000: Unknown error mask
- *             The bottom 15 bits will contain the bottom 15 bits from the EC
- *             error code.
- *
- *     read payload: Up to 60 bytes of data read from SPI, the total
- *                   length of all RX packets must match read count
- *                   unless an error status was returned. Due to data
- *                   alignment constraints, this must be a even number
- *                   of bytes unless this is the final packet.
- *
- *
- * Continue Packet (Bidirectional):
- *
- *      Continuation packet for the writes and read buffers. Both packets
- *      follow the same format, a data index counts the number of bytes
- *      previously transferred in the USB SPI transfer and a payload of bytes.
- *
- *     +----------------+-----------------+-------------------------------+
- *     | packet id : 2B | data index : 2B | write / read payload : <= 60B |
- *     +----------------+-----------------+-------------------------------+
- *
- *     packet id:     2 byte enum defined by packet_id_type
- *                    The packet id has 2 values depending on direction:
- *                    packet id = USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE
- *                    indicates the packet is being transmitted from the host
- *                    to the device and contains SPI write payload.
- *                    packet id = USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE
- *                    indicates the packet is being transmitted from the device
- *                    to the host and contains SPI read payload.
- *
- *     data index:    The data index indicates the number of bytes in the
- *                    read or write buffers that have already been transmitted.
- *                    It is used to validate that no packets have been dropped
- *                    and that the prior packets have been correctly decoded.
- *                    This value corresponds to the offset bytes in the buffer
- *                    to start copying the payload into.
- *
- *     read and write payload:
- *                    Contains up to 60 bytes of payload data to transfer to
- *                    the SPI write buffer or from the SPI read buffer.
- *
- *
- * Command Get Configuration Packet (Host to Device):
- *
- *      Query the device to request it's USB SPI configuration indicating
- *      the number of bytes it can write and read.
- *
- *     +----------------+
- *     | packet id : 2B |
- *     +----------------+
- *
- *     packet id:     2 byte enum USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG
- *
- * Response Configuration Packet (Device to Host):
- *
- *      Response packet form the device to report the maximum write and
- *      read size supported by the device.
- *
- *     +----------------+----------------+---------------+----------------+
- *     | packet id : 2B | max write : 2B | max read : 2B | feature bitmap |
- *     +----------------+----------------+---------------+----------------+
- *
- *     packet id:         2 byte enum USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG
- *
- *     max write count:   2 byte count of the maximum number of bytes
- *                        the device can write to SPI in one transaction.
- *
- *     max read count:    2 byte count of the maximum number of bytes
- *                        the device can read from SPI in one transaction.
- *
- *     feature bitmap:    Bitmap of supported features.
- *                        BIT(0): Full duplex SPI mode is supported
- *                        BIT(1:15): Reserved for future use
- *
- * Command Restart Response Packet (Host to Device):
- *
- *      Command to restart the response transfer from the device. This enables
- *      the host to recover from a lost packet when reading the response
- *      without restarting the SPI transfer.
- *
- *     +----------------+
- *     | packet id : 2B |
- *     +----------------+
- *
- *     packet id:         2 byte enum USB_SPI_PKT_ID_CMD_RESTART_RESPONSE
- *
- * USB Error Codes:
- *
- * send_command return codes have the following format:
- *
- *     0x00000:         Status code success.
- *     0x00001-0x0FFFF: Error code returned by the USB SPI device.
- *     0x10001-0x1FFFF: USB SPI Host error codes
- *     0x20001-0x20063  Lower bits store the positive value representation
- *                      of the libusb_error enum. See the libusb documentation:
- *                      http://libusb.sourceforge.net/api-1.0/group__misc.html
- */
-
-#define USB_SPI_FULL_DUPLEX_ENABLED         (UINT16_MAX)
-
-#define USB_SPI_PAYLOAD_SIZE_V2_START       (58)
-
-#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE    (60)
-
-#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE    (60)
-
-#define USB_SPI_PAYLOAD_SIZE_V2_ERROR       (60)
-
-#define USB_SPI_MIN_PACKET_SIZE             (2)
-
-enum packet_id_type {
-	/* Request USB SPI configuration data from device. */
-	USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG = 0,
-	/* USB SPI configuration data from device. */
-	USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG     = 1,
-	/*
-	 * Start a USB SPI transfer specifying number of bytes to write,
-	 * read and deliver first packet of data to write.
-	 */
-	USB_SPI_PKT_ID_CMD_TRANSFER_START     = 2,
-	/* Additional packets containing write payload. */
-	USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE  = 3,
-	/*
-	 * Request the device restart the response enabling us to recover
-	 * from packet loss without another SPI transfer.
-	 */
-	USB_SPI_PKT_ID_CMD_RESTART_RESPONSE   = 4,
-	/*
-	 * First packet of USB SPI response with the status code
-	 * and read payload if it was successful.
-	 */
-	USB_SPI_PKT_ID_RSP_TRANSFER_START     = 5,
-	/* Additional packets containing read payload. */
-	USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE  = 6,
-};
-
-enum feature_bitmap {
-	/* Indicates the platform supports full duplex mode. */
-	USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED = BIT(0)
-};
-
-struct usb_spi_response_configuration_v2 {
-	uint16_t packet_id;
-	uint16_t max_write_count;
-	uint16_t max_read_count;
-	uint16_t feature_bitmap;
-} __packed;
-
-struct usb_spi_command_v2 {
-	uint16_t packet_id;
-	uint16_t write_count;
-	/* UINT16_MAX Indicates readback all on halfduplex compliant devices. */
-	uint16_t read_count;
-	uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_START];
-} __packed;
-
-struct usb_spi_response_v2 {
-	uint16_t packet_id;
-	uint16_t status_code;
-	uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_RESPONSE];
-} __packed;
-
-struct usb_spi_continue_v2 {
-	uint16_t packet_id;
-	uint16_t data_index;
-	uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_CONTINUE];
-} __packed;
-
-struct usb_spi_packet_ctx {
-	union {
-		uint8_t bytes[USB_MAX_PACKET_SIZE];
-		uint16_t packet_id;
-		struct usb_spi_command_v2 cmd_start;
-		struct usb_spi_continue_v2 cmd_continue;
-		struct usb_spi_response_configuration_v2 rsp_config;
-		struct usb_spi_response_v2 rsp_start;
-		struct usb_spi_continue_v2 rsp_continue;
-	} __packed;
-	/*
-	 * By storing the number of bytes in the header and knowing that the
-	 * USB data packets are all 64B long, we are able to use the header
-	 * size to store the offset of the buffer and it's size without
-	 * duplicating variables that can go out of sync.
-	 */
-	size_t header_size;
-	/* Number of bytes in the packet. */
-	size_t packet_size;
-};
-
-enum usb_spi_error {
-	USB_SPI_SUCCESS                 = 0x0000,
-	USB_SPI_TIMEOUT                 = 0x0001,
-	USB_SPI_BUSY                    = 0x0002,
-	USB_SPI_WRITE_COUNT_INVALID     = 0x0003,
-	USB_SPI_READ_COUNT_INVALID      = 0x0004,
-	USB_SPI_DISABLED                = 0x0005,
-	/* The RX continue packet's data index is invalid. */
-	USB_SPI_RX_BAD_DATA_INDEX       = 0x0006,
-	/* The RX endpoint has received more data than write count. */
-	USB_SPI_RX_DATA_OVERFLOW        = 0x0007,
-	/* An unexpected packet arrived on the device. */
-	USB_SPI_RX_UNEXPECTED_PACKET    = 0x0008,
-	/* The device does not support full duplex mode. */
-	USB_SPI_UNSUPPORTED_FULL_DUPLEX = 0x0009,
-	USB_SPI_UNKNOWN_ERROR           = 0x8000,
-};
-
-enum usb_spi_request {
-	USB_SPI_REQ_ENABLE  = 0x0000,
-	USB_SPI_REQ_DISABLE = 0x0001,
-};
-
-/*
- * To optimize for speed, we want to fill whole packets for each transfer
- * This is done by setting the read and write counts to the payload sizes
- * of the smaller start packet + N * continue packets.
- *
- * If a platform has a small maximum SPI transfer size, it can be optimized
- * by setting these limits to the maximum transfer size.
- */
-#define USB_SPI_BUFFER_SIZE	(USB_SPI_PAYLOAD_SIZE_V2_START + \
-				(4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE))
-#define USB_SPI_MAX_WRITE_COUNT	USB_SPI_BUFFER_SIZE
-#define USB_SPI_MAX_READ_COUNT	USB_SPI_BUFFER_SIZE
-
-struct usb_spi_transfer_ctx {
-	/* Address of transfer buffer. */
-	uint8_t *buffer;
-	/* Number of bytes in the transfer. */
-	size_t transfer_size;
-	/* Number of bytes transferred. */
-	size_t transfer_index;
-};
-
-enum usb_spi_mode {
-	/* No tasks are required. */
-	USB_SPI_MODE_IDLE = 0,
-	/* Indicates the device needs to send it's USB SPI configuration.*/
-	USB_SPI_MODE_SEND_CONFIGURATION,
-	/* Indicates we device needs start the SPI transfer. */
-	USB_SPI_MODE_START_SPI,
-	/* Indicates we should start a transfer response. */
-	USB_SPI_MODE_START_RESPONSE,
-	/* Indicates we need to continue a transfer response. */
-	USB_SPI_MODE_CONTINUE_RESPONSE,
-};
-
-struct usb_spi_state {
-	/*
-	 * The SPI bridge must be enabled both locally and by the host to allow
-	 * access to the SPI device.  The enabled_host flag is set and cleared
-	 * by sending USB_SPI_REQ_ENABLE and USB_SPI_REQ_DISABLE to the device
-	 * control endpoint.  The enabled_device flag is set by calling
-	 * usb_spi_enable.
-	 */
-	int enabled_host;
-	int enabled_device;
-
-	/*
-	 * The current enabled state.  This is only updated in the deferred
-	 * callback.  Whenever either of the host or device specific enable
-	 * flags is changed the deferred callback is queued, and it will check
-	 * their combined state against this flag.  If the combined state is
-	 * different, then one of usb_spi_board_enable or usb_spi_board_disable
-	 * is called and this flag is updated.  This ensures that the board
-	 * specific state update routines are only called from the deferred
-	 * callback.
-	 */
-	int enabled;
-
-	/* Mark the current operating mode. */
-	enum usb_spi_mode mode;
-
-	/*
-	 * Stores the status code response for the transfer, delivered in the
-	 * header for the first response packet. Error code is cleared during
-	 * first RX packet and set if a failure occurs.
-	 */
-	uint16_t status_code;
-
-	/* Stores the content from the USB packets */
-	struct usb_spi_packet_ctx receive_packet;
-	struct usb_spi_packet_ctx transmit_packet;
-
-	/*
-	 * Context structures representing the progress receiving the SPI
-	 * write data and transmitting the SPI read data.
-	 */
-	struct usb_spi_transfer_ctx spi_write_ctx;
-	struct usb_spi_transfer_ctx spi_read_ctx;
-};
-
-/*
- * Compile time Per-USB gpio configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB gpio.  This structure binds
- * together all information required to operate a USB gpio.
- */
-struct usb_spi_config {
-	/* In RAM state of the USB SPI bridge. */
-	struct usb_spi_state *state;
-
-	/* Interface and endpoint indices. */
-	int interface;
-	int endpoint;
-
-	/* Deferred function to call to handle SPI request. */
-	const struct deferred_data *deferred;
-
-	/* Pointers to USB endpoint buffers. */
-	usb_uint *ep_rx_ram;
-	usb_uint *ep_tx_ram;
-
-	/* Flags. See USB_SPI_CONFIG_FLAGS_* for definitions */
-	uint32_t flags;
-};
-
-/*
- * Use when you want the SPI subsystem to be enabled even when the USB SPI
- * endpoint is not enabled by the host. This means that when this firmware
- * enables SPI, then the HW SPI module is enabled (i.e. SPE bit is set) until
- * this firmware disables the SPI module; it ignores the host's enables state.
- */
-#define USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE BIT(0)
-
-/*
- * Convenience macro for defining a USB SPI bridge driver.
- *
- * NAME is used to construct the names of the trampoline functions and the
- * usb_spi_config struct, the latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * SPI driver.
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- *
- * FLAGS encodes different run-time control parameters. See
- * USB_SPI_CONFIG_FLAGS_* for definitions.
- */
-#define USB_SPI_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       ENDPOINT,					\
-		       FLAGS)						\
-	static uint16_t CONCAT2(NAME, _buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2];\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	struct usb_spi_state CONCAT2(NAME, _state_) = {			\
-		.enabled_host   = 0,					\
-		.enabled_device = 0,					\
-		.enabled        = 0,					\
-		.spi_write_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \
-		.spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \
-	};								\
-	struct usb_spi_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state_),			\
-		.interface = INTERFACE,					\
-		.endpoint  = ENDPOINT,					\
-		.deferred  = &CONCAT2(NAME, _deferred__data),		\
-		.ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_),		\
-		.ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_),		\
-		.flags     = FLAGS,		\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI,		\
-		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI,		\
-		.iInterface         = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx_)   (void) { usb_spi_tx   (&NAME); } \
-	static void CONCAT2(NAME, _ep_rx_)   (void) { usb_spi_rx   (&NAME); } \
-	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)	\
-	{								\
-		usb_spi_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx_),				\
-		       CONCAT2(NAME, _ep_rx_),				\
-		       CONCAT2(NAME, _ep_event_));			\
-	static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf,		\
-					      usb_uint *tx_buf)		\
-	{ return usb_spi_interface(&NAME, rx_buf, tx_buf); }		\
-	USB_DECLARE_IFACE(INTERFACE,					\
-			  CONCAT2(NAME, _interface_));			\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_spi_deferred(&NAME); }
-
-/*
- * Handle SPI request in a deferred callback.
- */
-void usb_spi_deferred(struct usb_spi_config const *config);
-
-/*
- * Set the enable state for the USB-SPI bridge.
- *
- * The bridge must be enabled from both the host and device side
- * before the SPI bus is usable.  This allows the bridge to be
- * available for host tools to use without forcing the device to
- * disconnect or disable whatever else might be using the SPI bus.
- */
-void usb_spi_enable(struct usb_spi_config const *config, int enabled);
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB GPIO driver.
- */
-void usb_spi_tx(struct usb_spi_config const *config);
-void usb_spi_rx(struct usb_spi_config const *config);
-void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt);
-int  usb_spi_interface(struct usb_spi_config const *config,
-		       usb_uint *rx_buf,
-		       usb_uint *tx_buf);
-
-/*
- * These functions should be implemented by the board to provide any board
- * specific operations required to enable or disable access to the SPI device.
- */
-void usb_spi_board_enable(struct usb_spi_config const *config);
-void usb_spi_board_disable(struct usb_spi_config const *config);
-
-#endif /* __CROS_EC_USB_SPI_H */
diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c
deleted file mode 100644
index 40dfc72059..0000000000
--- a/chip/stm32/watchdog.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * LSI oscillator frequency is typically 38 kHz, but it may be between 28-56
- * kHz and we don't calibrate it to know.  Use 56 kHz so that we pick a counter
- * value large enough that we reload before the worst-case watchdog delay
- * (fastest LSI clock).
- */
-#ifdef CHIP_FAMILY_STM32L4
-#define LSI_CLOCK 34000
-#else
-#define LSI_CLOCK 56000
-#endif
-
-/* The timeout value is multiplied by 1000 to be converted into ms */
-#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_CLOCK)
-
-/*
- * Use largest prescaler divider = /256.  This gives a worst-case watchdog
- * clock of 56000/256 = 218 Hz, and a maximum timeout period of (4095/218 Hz) =
- * 18.7 sec.
- *
- * For STM32L4, Max LSI is 34000. Watchdog clock is 34000 / 256 = 132Hz,
- * Max timeout = 4095 / 132 = 31 sec.
- */
-#define IWDG_PRESCALER 6
-#define IWDG_PRESCALER_DIV (4 << IWDG_PRESCALER)
-
-void watchdog_reload(void)
-{
-	/* Reload the watchdog */
-	STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
-
-#ifdef CONFIG_WATCHDOG_HELP
-	hwtimer_reset_watchdog();
-#endif
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-#ifdef CHIP_FAMILY_STM32L4
-	timestamp_t tickstart, ticknow;
-
-	/* Enable watchdog registers */
-	STM32_IWDG_KR = STM32_IWDG_KR_START;
-#endif
-	/* Unlock watchdog registers */
-	STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK;
-
-	/* Set the prescaler between the LSI clock and the watchdog counter */
-	STM32_IWDG_PR = IWDG_PRESCALER & 7;
-
-	/* Set the reload value of the watchdog counter */
-	STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS *
-			     (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000);
-#ifdef CHIP_FAMILY_STM32L4
-	tickstart = get_time();
-	/* Wait for SR */
-	while (STM32_IWDG_SR != 0x00u) {
-		ticknow = get_time();
-		if ((ticknow.val - tickstart.val) >
-		    HAL_IWDG_DEFAULT_TIMEOUT * 1000) {
-			return EC_ERROR_TIMEOUT;
-		}
-	}
-
-	/* Reload the watchdog */
-	STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
-#else
-	/* Start the watchdog (and re-lock registers) */
-	STM32_IWDG_KR = STM32_IWDG_KR_START;
-
-	/*
-	 * We should really wait for IWDG_PR and IWDG_RLR value to be updated
-	 * but updating those registers can take about 48ms (found
-	 * empirically, it's 6 LSI cycles at 32kHz). Such a big delay is not
-	 * desired during system init.
-	 *
-	 * However documentation allows us to continue code execution, but
-	 * we should wait for RVU bit to be clear before updating IWDG_RLR
-	 * once again (hard reboot for STM32H7 and STM32F4).
-	 *
-	 * RM0433 Rev 7
-	 * Section 45.4.4 Page 1920
-	 * https://www.st.com/resource/en/reference_manual/dm00314099.pdf
-	 * If several reload, prescaler, or window values are used by the
-	 * application, it is mandatory to wait until RVU bit is reset before
-	 * changing the reload value, to wait until PVU bit is reset before
-	 * changing the prescaler value, and to wait until WVU bit is reset
-	 * before changing the window value. However, after updating the
-	 * prescaler and/or the reload/window value it is not necessary to wait
-	 * until RVU or PVU or WVU is reset before continuing code execution
-	 * except in case of low-power mode entry.
-	 */
-
-#endif
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Use a harder timer to warn about an impending watchdog reset */
-	hwtimer_setup_watchdog();
-#endif
-
-	return EC_SUCCESS;
-}