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-rw-r--r--chip/mt_scp/mt818x/uart.c1
-rw-r--r--chip/mt_scp/mt8192/uart.c4
-rw-r--r--chip/mt_scp/mt8195/uart.c4
3 files changed, 0 insertions, 9 deletions
diff --git a/chip/mt_scp/mt818x/uart.c b/chip/mt_scp/mt818x/uart.c
index 4b3b45d8ea..e6bd361d8d 100644
--- a/chip/mt_scp/mt818x/uart.c
+++ b/chip/mt_scp/mt818x/uart.c
@@ -174,6 +174,5 @@ void uart_init(void)
/* UART RX IRQ needs an extra enable */
SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
#endif
- gpio_config_module(MODULE_UART, 1);
uart_done = 1;
}
diff --git a/chip/mt_scp/mt8192/uart.c b/chip/mt_scp/mt8192/uart.c
index 0ebb93cbb4..9e2c097414 100644
--- a/chip/mt_scp/mt8192/uart.c
+++ b/chip/mt_scp/mt8192/uart.c
@@ -19,10 +19,6 @@ void uart_init_pinmux(void)
#if UARTN == 0
SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
- /* set AP GPIO164 and GPIO165 to alt func 3 */
- AP_GPIO_MODE20_CLR = 0x00770000;
- AP_GPIO_MODE20_SET = 0x00330000;
#elif UARTN == 1
SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST;
diff --git a/chip/mt_scp/mt8195/uart.c b/chip/mt_scp/mt8195/uart.c
index 76674fa7d3..dab25e7d19 100644
--- a/chip/mt_scp/mt8195/uart.c
+++ b/chip/mt_scp/mt8195/uart.c
@@ -19,9 +19,5 @@ void uart_init_pinmux(void)
#if UARTN == 0
SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
- /* set AP GPIO102 and GPIO103 to alt func 5 */
- AP_GPIO_MODE12_CLR = 0x77000000;
- AP_GPIO_MODE12_SET = 0x55000000;
#endif
}