diff options
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/it83xx/config_chip_it8xxx2.h | 1 | ||||
| -rw-r--r-- | chip/it83xx/flash.c | 37 | ||||
| -rw-r--r-- | chip/it83xx/flash_chip.h | 3 | ||||
| -rw-r--r-- | chip/it83xx/registers.h | 4 |
4 files changed, 45 insertions, 0 deletions
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index a3113907fd..0bd8963e6e 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -133,6 +133,7 @@ #error "Unsupported chip variant!" #endif +#define CHIP_RAMCODE_ILM0 (CONFIG_RAM_BASE + 0) /* base+0000h~base+0FFF */ #define CHIP_H2RAM_BASE (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */ #define CHIP_RAMCODE_BASE (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF */ diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c index 6d3b9d8074..c0f46552fd 100644 --- a/chip/it83xx/flash.c +++ b/chip/it83xx/flash.c @@ -19,6 +19,7 @@ #define FLASH_DMA_START ((uint32_t) &__flash_dma_start) #define FLASH_DMA_CODE __attribute__((section(".flash_direct_map"))) +#define FLASH_ILM0_ADDR ((uint32_t) &__ilm0_ram_code) /* erase size of sector is 1KB or 4KB */ #define FLASH_SECTOR_ERASE_SIZE CONFIG_FLASH_ERASE_SIZE @@ -640,6 +641,37 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) return ret; } +static void flash_enable_second_ilm(void) +{ +#ifdef CHIP_CORE_RISCV + /* Make sure no interrupt while enable static cache */ + interrupt_disable(); + + /* Invalid ILM0 */ + IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM0_ENABLE; + IT83XX_SMFI_SCAR0H = BIT(3); + /* copy code to ram */ + memcpy((void *)CHIP_RAMCODE_ILM0, + (const void *)FLASH_ILM0_ADDR, + IT83XX_ILM_BLOCK_SIZE); + /* + * Set the logic memory address(flash code of RO/RW) in flash + * by programming the register SCAR0x bit19-bit0. + */ + IT83XX_SMFI_SCAR0L = FLASH_ILM0_ADDR & GENMASK(7, 0); + IT83XX_SMFI_SCAR0M = (FLASH_ILM0_ADDR >> 8) & GENMASK(7, 0); + IT83XX_SMFI_SCAR0H = (FLASH_ILM0_ADDR >> 16) & GENMASK(2, 0); + if (FLASH_ILM0_ADDR & BIT(19)) + IT83XX_SMFI_SCAR0H |= BIT(7); + else + IT83XX_SMFI_SCAR0H &= ~BIT(7); + /* Enable ILM 0 */ + IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM0_ENABLE; + + interrupt_enable(); +#endif +} + static void flash_code_static_dma(void) { @@ -703,6 +735,11 @@ int flash_pre_init(void) if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD)) IT83XX_SMFI_FLHCTRL6R |= IT83XX_SMFI_MASK_ECINDPP; flash_code_static_dma(); + /* + * Enable second ilm (ILM0 of it8xxx2 series), so we can pull more code + * (4kB) into static cache to save latency of fetching code from flash. + */ + flash_enable_second_ilm(); reset_flags = system_get_reset_flags(); prot_flags = flash_get_protect(); diff --git a/chip/it83xx/flash_chip.h b/chip/it83xx/flash_chip.h index 4a604ed7f7..c1262da116 100644 --- a/chip/it83xx/flash_chip.h +++ b/chip/it83xx/flash_chip.h @@ -13,6 +13,9 @@ */ extern const char __flash_dma_start; +/* This symbol is the begin address of the __ilm0_ram_code section. */ +extern const char __ilm0_ram_code; + /* This symbol is the begin address of the text section. */ extern const char __flash_text_start; diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 166b690404..83a0fb4014 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -999,6 +999,7 @@ enum clock_gate_offsets { /* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */ #define ETWD_HW_RST_EN BIT(0) #define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE+0x5D) +#define ILMCR_ILM0_ENABLE BIT(0) #define ILMCR_ILM2_ENABLE BIT(2) #define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE+0x60+i) #define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE+0xA0+i) @@ -1284,6 +1285,9 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) #define IT83XX_SMFI_ECINDAR3 REG8(IT83XX_SMFI_BASE+0x3E) #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) #define IT83XX_SMFI_ECINDDR REG8(IT83XX_SMFI_BASE+0x3F) +#define IT83XX_SMFI_SCAR0L REG8(IT83XX_SMFI_BASE+0x40) +#define IT83XX_SMFI_SCAR0M REG8(IT83XX_SMFI_BASE+0x41) +#define IT83XX_SMFI_SCAR0H REG8(IT83XX_SMFI_BASE+0x42) #define IT83XX_SMFI_SCAR2L REG8(IT83XX_SMFI_BASE+0x46) #define IT83XX_SMFI_SCAR2M REG8(IT83XX_SMFI_BASE+0x47) #define IT83XX_SMFI_SCAR2H REG8(IT83XX_SMFI_BASE+0x48) |