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-rw-r--r--core/cortex-m0/__builtin.c2
-rw-r--r--core/cortex-m0/atomic.h40
-rw-r--r--core/cortex-m0/build.mk14
-rw-r--r--core/cortex-m0/config_core.h2
-rw-r--r--core/cortex-m0/cpu.c2
-rw-r--r--core/cortex-m0/cpu.h61
-rw-r--r--core/cortex-m0/ec.lds.S12
-rw-r--r--core/cortex-m0/include/fpu.h4
-rw-r--r--core/cortex-m0/init.S2
-rw-r--r--core/cortex-m0/irq_handler.h41
-rw-r--r--core/cortex-m0/mula.S2
-rw-r--r--core/cortex-m0/panic-internal.h4
-rw-r--r--core/cortex-m0/panic.c57
-rw-r--r--core/cortex-m0/switch.S2
-rw-r--r--core/cortex-m0/task.c97
-rw-r--r--core/cortex-m0/thumb_case.S2
-rw-r--r--core/cortex-m0/toolchain.mk15
-rw-r--r--core/cortex-m0/vecttable.c89
-rw-r--r--core/cortex-m0/watchdog.c2
19 files changed, 207 insertions, 243 deletions
diff --git a/core/cortex-m0/__builtin.c b/core/cortex-m0/__builtin.c
index 4bf495a011..8e2bf984ff 100644
--- a/core/cortex-m0/__builtin.c
+++ b/core/cortex-m0/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h
index 7ec856ed62..9fd3ab849b 100644
--- a/core/cortex-m0/atomic.h
+++ b/core/cortex-m0/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -16,22 +16,22 @@
*
* There is no load/store exclusive on ARMv6-M, just disable interrupts
*/
-#define ATOMIC_OP(asm_op, a, v) \
-({ \
- uint32_t reg0, reg1; \
- \
- __asm__ __volatile__(".syntax unified\n" \
- " cpsid i\n" \
- " ldr %0, [%2]\n" \
- " mov %1, %0\n" \
- #asm_op" %0, %0, %3\n" \
- " str %0, [%2]\n" \
- " cpsie i\n" \
- : "=&l"(reg0), "=&l"(reg1) \
- : "l"(a), "r"(v) \
- : "cc", "memory"); \
- reg1; \
-})
+#define ATOMIC_OP(asm_op, a, v) \
+ ({ \
+ uint32_t reg0, reg1; \
+ \
+ __asm__ __volatile__(".syntax unified\n" \
+ " cpsid i\n" \
+ " ldr %0, [%2]\n" \
+ " mov %1, %0\n" #asm_op \
+ " %0, %0, %3\n" \
+ " str %0, [%2]\n" \
+ " cpsie i\n" \
+ : "=&l"(reg0), "=&l"(reg1) \
+ : "l"(a), "r"(v) \
+ : "cc", "memory"); \
+ reg1; \
+ })
static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
{
@@ -62,8 +62,8 @@ static inline atomic_val_t atomic_clear(atomic_t *addr)
" ldr %0, [%1]\n"
" str %2, [%1]\n"
" cpsie i\n"
- : "=&l" (ret)
- : "l" (addr), "r" (0)
+ : "=&l"(ret)
+ : "l"(addr), "r"(0)
: "cc", "memory");
return ret;
@@ -74,4 +74,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
return ATOMIC_OP(ands, addr, bits);
}
-#endif /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk
index eab2a1eb1c..0bea9d09ab 100644
--- a/core/cortex-m0/build.mk
+++ b/core/cortex-m0/build.mk
@@ -1,23 +1,11 @@
# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Cortex-M0 core OS files build
#
-ifeq ($(cc-name),gcc)
-# coreboot sdk
-CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
-else
-# llvm sdk
-CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi-
-endif
-
-$(call set-option,CROSS_COMPILE,\
- $(CROSS_COMPILE_arm),\
- $(CROSS_COMPILE_ARM_DEFAULT))
-
# CPU specific compilation flags
CFLAGS_CPU+=-mthumb
ifeq ($(cc-name),clang)
diff --git a/core/cortex-m0/config_core.h b/core/cortex-m0/config_core.h
index a40756fb49..e954e5e0af 100644
--- a/core/cortex-m0/config_core.h
+++ b/core/cortex-m0/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
diff --git a/core/cortex-m0/cpu.c b/core/cortex-m0/cpu.c
index b354cc03e2..e180570863 100644
--- a/core/cortex-m0/cpu.c
+++ b/core/cortex-m0/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h
index c30095fd65..568b16eedb 100644
--- a/core/cortex-m0/cpu.h
+++ b/core/cortex-m0/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
@@ -10,41 +10,42 @@
#include <stdint.h>
#include "compile_time_macros.h"
+#include "debug.h"
/* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
+#define CPUREG(addr) (*(volatile uint32_t *)(addr))
/* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x) CPUREG(0xe000e100)
-#define CPU_NVIC_DIS(x) CPUREG(0xe000e180)
-#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280)
-#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200)
-#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
+#define CPU_NVIC_EN(x) CPUREG(0xe000e100)
+#define CPU_NVIC_DIS(x) CPUREG(0xe000e180)
+#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280)
+#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200)
+#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
/* System Control Block */
-#define CPU_SCB_ICSR CPUREG(0xe000ed04)
+#define CPU_SCB_ICSR CPUREG(0xe000ed04)
/* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
-#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */
-#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */
-#define CPU_NVIC_APINT_KEY_RD (0U)
-#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16)
+#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
+#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */
+#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */
+#define CPU_NVIC_APINT_KEY_RD (0U)
+#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16)
/* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
-#define CPU_NVIC_CCR CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c)
-#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20)
+#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
+#define CPU_NVIC_CCR CPUREG(0xe000ed14)
+#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c)
+#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20)
#define CPU_NVIC_CCR_UNALIGN_TRAP BIT(3)
/* Bitfield values for EXC_RETURN. */
-#define EXC_RETURN_SPSEL_MASK BIT(2)
-#define EXC_RETURN_SPSEL_MSP 0
-#define EXC_RETURN_SPSEL_PSP BIT(2)
-#define EXC_RETURN_MODE_MASK BIT(3)
-#define EXC_RETURN_MODE_HANDLER 0
-#define EXC_RETURN_MODE_THREAD BIT(3)
+#define EXC_RETURN_SPSEL_MASK BIT(2)
+#define EXC_RETURN_SPSEL_MSP 0
+#define EXC_RETURN_SPSEL_PSP BIT(2)
+#define EXC_RETURN_MODE_MASK BIT(3)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD BIT(3)
/* Set up the cpu to detect faults */
void cpu_init(void);
@@ -57,10 +58,16 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
if (priority > 3)
priority = 3;
- CPU_NVIC_PRI(irq / 4) =
- (CPU_NVIC_PRI(irq / 4) &
- ~(3 << prio_shift)) |
- (priority << prio_shift);
+ CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(3 << prio_shift)) |
+ (priority << prio_shift);
+}
+
+static inline void cpu_enter_suspend_mode(void)
+{
+ /* Preserve debug sessions by not suspending when connected */
+ if (!debugger_is_connected()) {
+ asm("wfi");
+ }
}
#endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
index ce67760cf2..3c2076b9e4 100644
--- a/core/cortex-m0/ec.lds.S
+++ b/core/cortex-m0/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -189,6 +189,10 @@ SECTIONS
KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
__hooks_usb_pd_connect_end = .;
+ __hooks_power_supply_change = .;
+ KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+ __hooks_power_supply_change_end = .;
+
__deferred_funcs = .;
KEEP(*(.rodata.deferred))
__deferred_funcs_end = .;
@@ -291,6 +295,12 @@ SECTIONS
__data_end = .;
/*
+ * _sbrk in newlib expects "end" symbol to point to start of
+ * free memory.
+ */
+ end = .;
+
+ /*
* Shared memory buffer must be at the end of preallocated
* RAM, so it can expand to use all the remaining RAM.
*/
diff --git a/core/cortex-m0/include/fpu.h b/core/cortex-m0/include/fpu.h
index 3acec557a7..1054f388b0 100644
--- a/core/cortex-m0/include/fpu.h
+++ b/core/cortex-m0/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -8,4 +8,4 @@
#ifndef __CROS_EC_FPU_H
#define __CROS_EC_FPU_H
-#endif /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/cortex-m0/init.S b/core/cortex-m0/init.S
index 6ccb75bbe8..58316e92d6 100644
--- a/core/cortex-m0/init.S
+++ b/core/cortex-m0/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/cortex-m0/irq_handler.h b/core/cortex-m0/irq_handler.h
index 302befe7a6..f2f6a220e4 100644
--- a/core/cortex-m0/irq_handler.h
+++ b/core/cortex-m0/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -20,25 +20,26 @@
*/
#define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
#ifdef CONFIG_TASK_PROFILING
-#define DECLARE_IRQ_(irq, routine, priority) \
- static void routine(void); \
- void IRQ_HANDLER(irq)(void) \
- { \
- void *ret = __builtin_return_address(0); \
- task_start_irq_handler(ret); \
- routine(); \
- task_end_irq_handler(ret); \
- } \
- const struct irq_priority __keep IRQ_PRIORITY(irq) \
- __attribute__((section(".rodata.irqprio"))) \
- = {irq, priority}
+#define DECLARE_IRQ_(irq, routine, priority) \
+ static void routine(void); \
+ void IRQ_HANDLER(irq)(void) \
+ { \
+ void *ret = __builtin_return_address(0); \
+ task_start_irq_handler(ret); \
+ routine(); \
+ task_end_irq_handler(ret); \
+ } \
+ const struct irq_priority __keep IRQ_PRIORITY(irq) \
+ __attribute__((section(".rodata.irqprio"))) = { irq, \
+ priority }
#else /* CONFIG_TASK_PROFILING */
/* No Profiling : connect directly the IRQ vector */
-#define DECLARE_IRQ_(irq, routine, priority) \
- static void __keep routine(void); \
- void IRQ_HANDLER(irq)(void) __attribute__((alias(STRINGIFY(routine))));\
- const struct irq_priority __keep IRQ_PRIORITY(irq) \
- __attribute__((section(".rodata.irqprio"))) \
- = {irq, priority}
+#define DECLARE_IRQ_(irq, routine, priority) \
+ static void __keep routine(void); \
+ void IRQ_HANDLER(irq)(void) \
+ __attribute__((alias(STRINGIFY(routine)))); \
+ const struct irq_priority __keep IRQ_PRIORITY(irq) \
+ __attribute__((section(".rodata.irqprio"))) = { irq, \
+ priority }
#endif /* CONFIG_TASK_PROFILING */
-#endif /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/cortex-m0/mula.S b/core/cortex-m0/mula.S
index 02e617c328..7bb54263b4 100644
--- a/core/cortex-m0/mula.S
+++ b/core/cortex-m0/mula.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/cortex-m0/panic-internal.h b/core/cortex-m0/panic-internal.h
index 51c12f65b2..9f831495ff 100644
--- a/core/cortex-m0/panic-internal.h
+++ b/core/cortex-m0/panic-internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -10,4 +10,4 @@
noreturn void exception_panic(void) __attribute__((naked));
-#endif /* __CROS_EC_PANIC_INTERNAL_H */
+#endif /* __CROS_EC_PANIC_INTERNAL_H */
diff --git a/core/cortex-m0/panic.c b/core/cortex-m0/panic.c
index f1ee816c60..f20908eb7c 100644
--- a/core/cortex-m0/panic.c
+++ b/core/cortex-m0/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -19,9 +19,8 @@
/* Whether bus fault is ignored */
static int bus_fault_ignored;
-
/* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
+static struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
/* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
static const uint32_t pstack_addr = ((uint32_t)pdata_ptr) & ~7;
@@ -101,7 +100,7 @@ void panic_data_print(const struct panic_data *pdata)
print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12);
print_reg(13, lregs,
in_handler ? CORTEX_PANIC_REGISTER_MSP :
- CORTEX_PANIC_REGISTER_PSP);
+ CORTEX_PANIC_REGISTER_PSP);
print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR);
print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC);
}
@@ -126,10 +125,9 @@ void __keep report_panic(void)
sp = is_frame_in_handler_stack(
pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ?
pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] :
- pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
+ pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
/* If stack is valid, copy exception frame to pdata */
- if ((sp & 3) == 0 &&
- sp >= CONFIG_RAM_BASE &&
+ if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE &&
sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
const uint32_t *sregs = (const uint32_t *)sp;
int i;
@@ -162,38 +160,41 @@ void exception_panic(void)
"mov r5, lr\n"
"stmia %[pregs]!, {r1-r5}\n"
"mov sp, %[pstack]\n"
- "bl report_panic\n" : :
- [pregs] "r" (pdata_ptr->cm.regs),
- [pstack] "r" (pstack_addr) :
- /* Constraints protecting these from being clobbered.
- * Gcc should be using r0 & r12 for pregs and pstack. */
- "r1", "r2", "r3", "r4", "r5", "r6",
- /* clang warns that we're clobbering a reserved register:
- * inline asm clobber list contains reserved registers: R7
- * [-Werror,-Winline-asm]. The intent of the clobber list is
- * to force pregs and pstack to be in R0 and R12, which
- * still holds.
- */
+ "bl report_panic\n"
+ :
+ : [pregs] "r"(pdata_ptr->cm.regs), [pstack] "r"(pstack_addr)
+ :
+ /* Constraints protecting these from being clobbered.
+ * Gcc should be using r0 & r12 for pregs and pstack. */
+ "r1", "r2", "r3", "r4", "r5", "r6",
+ /* clang warns that we're clobbering a reserved register:
+ * inline asm clobber list contains reserved registers: R7
+ * [-Werror,-Winline-asm]. The intent of the clobber list is
+ * to force pregs and pstack to be in R0 and R12, which
+ * still holds.
+ */
#ifndef __clang__
- "r7",
+ "r7",
#endif
- "r8", "r9", "r10", "r11", "cc", "memory"
- );
+ "r8", "r9", "r10", "r11", "cc", "memory");
}
#ifdef CONFIG_SOFTWARE_PANIC
void software_panic(uint32_t reason, uint32_t info)
{
- __asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
- "mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
- "bl exception_panic\n"
- : : "r"(info), "r"(reason));
+ __asm__("mov " STRINGIFY(
+ SOFTWARE_PANIC_INFO_REG) ", %0\n"
+ "mov " STRINGIFY(
+ SOFTWARE_PANIC_REASON_REG) ", %1\n"
+ "bl exception_panic\n"
+ :
+ : "r"(info), "r"(reason));
__builtin_unreachable();
}
void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
{
- struct panic_data * const pdata = get_panic_data_write();
+ struct panic_data *const pdata = get_panic_data_write();
uint32_t *lregs;
lregs = pdata->cm.regs;
@@ -213,7 +214,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
{
- struct panic_data * const pdata = panic_get_data();
+ struct panic_data *const pdata = panic_get_data();
uint32_t *lregs;
if (pdata && pdata->struct_version == 2) {
diff --git a/core/cortex-m0/switch.S b/core/cortex-m0/switch.S
index a75daad939..4914788460 100644
--- a/core/cortex-m0/switch.S
+++ b/core/cortex-m0/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c
index 52a6921ae6..b34e920e09 100644
--- a/core/cortex-m0/task.c
+++ b/core/cortex-m0/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -6,6 +6,7 @@
/* Task scheduling / events module for Chrome EC operating system */
#include "atomic.h"
+#include "builtin/assert.h"
#include "common.h"
#include "console.h"
#include "cpu.h"
@@ -21,10 +22,10 @@ typedef union {
* Note that sp must be the first element in the task struct
* for __switchto() to work.
*/
- uint32_t sp; /* Saved stack pointer for context switch */
- atomic_t events; /* Bitmaps of received events */
- uint64_t runtime; /* Time spent in task */
- uint32_t *stack; /* Start of stack */
+ uint32_t sp; /* Saved stack pointer for context switch */
+ atomic_t events; /* Bitmaps of received events */
+ uint64_t runtime; /* Time spent in task */
+ uint32_t *stack; /* Start of stack */
};
} task_;
@@ -40,12 +41,10 @@ CONFIG_CTS_TASK_LIST
#undef TASK
/* Task names for easier debugging */
-#define TASK(n, r, d, s) #n,
-static const char * const task_names[] = {
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
"<< idle >>",
- CONFIG_TASK_LIST
- CONFIG_TEST_TASK_LIST
- CONFIG_CTS_TASK_LIST
+ CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
};
#undef TASK
@@ -55,12 +54,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
* We only keep 32-bit values for exception start/end time, to avoid
* accounting errors when we service interrupt when the timer wraps around.
*/
-static uint32_t exc_start_time; /* Time of task->exception transition */
-static uint32_t exc_end_time; /* Time of exception->task transition */
-static uint64_t exc_total_time; /* Total time in exceptions */
-static uint32_t svc_calls; /* Number of service calls */
-static uint32_t task_switches; /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
#endif
extern int __task_start(int *task_stack_ready);
@@ -74,7 +73,7 @@ void __idle(void)
* Wait for the next irq event. This stops the CPU clock
* (sleep / deep sleep, depending on chip config).
*/
- asm("wfi");
+ cpu_enter_suspend_mode();
}
}
#endif /* !CONFIG_LOW_POWER_IDLE */
@@ -89,20 +88,19 @@ static void task_exit_trap(void)
}
/* Startup parameters for all tasks. */
-#define TASK(n, r, d, s) { \
- .r0 = (uint32_t)d, \
- .pc = (uint32_t)r, \
- .stack_size = s, \
-},
+#define TASK(n, r, d, s) \
+ { \
+ .r0 = (uint32_t)d, \
+ .pc = (uint32_t)r, \
+ .stack_size = s, \
+ },
static const struct {
uint32_t r0;
uint32_t pc;
uint16_t stack_size;
} tasks_init[] = {
TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
- CONFIG_TASK_LIST
- CONFIG_TEST_TASK_LIST
- CONFIG_CTS_TASK_LIST
+ CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
};
#undef TASK
@@ -112,15 +110,11 @@ static task_ tasks[TASK_ID_COUNT];
BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
-
/* Stacks for all tasks */
-#define TASK(n, r, d, s) + s
-uint8_t task_stacks[0
- TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
- CONFIG_TASK_LIST
- CONFIG_TEST_TASK_LIST
- CONFIG_CTS_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+ CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
+ CONFIG_CTS_TASK_LIST] __aligned(8);
#undef TASK
@@ -144,7 +138,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
*/
static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
-static int start_called; /* Has task swapping started */
+static int start_called; /* Has task swapping started */
static inline task_ *__task_id_to_ptr(task_id_t id)
{
@@ -166,7 +160,7 @@ inline bool is_interrupt_enabled(void)
int primask;
/* Interrupts are enabled when PRIMASK bit is 0 */
- asm("mrs %0, primask":"=r"(primask));
+ asm("mrs %0, primask" : "=r"(primask));
return !(primask & 0x1);
}
@@ -184,7 +178,7 @@ static inline int get_interrupt_context(void)
{
int ret;
asm("mrs %0, ipsr\n" : "=r"(ret)); /* read exception number */
- return ret & 0x1ff; /* exception bits are the 9 LSB */
+ return ret & 0x1ff; /* exception bits are the 9 LSB */
}
#endif
@@ -211,7 +205,7 @@ int task_start_called(void)
/**
* Scheduling system call
*/
-task_ __attribute__((noinline)) *__svc_handler(int desched, task_id_t resched)
+task_ __attribute__((noinline)) * __svc_handler(int desched, task_id_t resched)
{
task_ *current, *next;
#ifdef CONFIG_TASK_PROFILING
@@ -304,9 +298,8 @@ void task_start_irq_handler(void *excep_return)
* Continue iff the tasks are ready and we are not called from another
* exception (as the time accouting is done in the outer irq).
*/
- if (!start_called
- || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
- == EXC_RETURN_MODE_HANDLER))
+ if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+ EXC_RETURN_MODE_HANDLER))
return;
exc_start_time = t;
@@ -324,9 +317,8 @@ void task_end_irq_handler(void *excep_return)
* Continue iff the tasks are ready and we are not called from another
* exception (as the time accouting is done in the outer irq).
*/
- if (!start_called
- || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
- == EXC_RETURN_MODE_HANDLER))
+ if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+ EXC_RETURN_MODE_HANDLER))
return;
/* Track time in interrupts */
@@ -584,7 +576,7 @@ void task_print_list(void)
}
}
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
{
#ifdef CONFIG_TASK_PROFILING
int total = 0;
@@ -613,12 +605,10 @@ static int command_task_info(int argc, char **argv)
return EC_SUCCESS;
}
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
- NULL,
- "Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
#ifdef CONFIG_CMD_TASKREADY
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
{
if (argc < 2) {
ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -630,8 +620,7 @@ static int command_task_ready(int argc, char **argv)
return EC_SUCCESS;
}
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
- "[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
"Print/set ready tasks");
#endif
@@ -657,10 +646,10 @@ void task_pre_init(void)
tasks[i].sp = (uint32_t)sp;
/* Initial context on stack (see __switchto()) */
- sp[8] = tasks_init[i].r0; /* r0 */
- sp[13] = (uint32_t)task_exit_trap; /* lr */
- sp[14] = tasks_init[i].pc; /* pc */
- sp[15] = 0x01000000; /* psr */
+ sp[8] = tasks_init[i].r0; /* r0 */
+ sp[13] = (uint32_t)task_exit_trap; /* lr */
+ sp[14] = tasks_init[i].pc; /* pc */
+ sp[15] = 0x01000000; /* psr */
/* Fill unused stack; also used to detect stack overflow. */
for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/cortex-m0/thumb_case.S b/core/cortex-m0/thumb_case.S
index 5628361a94..9148a33427 100644
--- a/core/cortex-m0/thumb_case.S
+++ b/core/cortex-m0/thumb_case.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/cortex-m0/toolchain.mk b/core/cortex-m0/toolchain.mk
new file mode 100644
index 0000000000..6b5f07ccf6
--- /dev/null
+++ b/core/cortex-m0/toolchain.mk
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+ifeq ($(cc-name),gcc)
+# coreboot sdk
+CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
+else
+# llvm sdk
+CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi-
+endif
+
+$(call set-option,CROSS_COMPILE,\
+ $(CROSS_COMPILE_arm),\
+ $(CROSS_COMPILE_ARM_DEFAULT))
diff --git a/core/cortex-m0/vecttable.c b/core/cortex-m0/vecttable.c
index 5c69f6d6c8..3871a30055 100644
--- a/core/cortex-m0/vecttable.c
+++ b/core/cortex-m0/vecttable.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
@@ -13,7 +13,7 @@
#include "config.h"
#include "panic-internal.h"
#include "task.h"
-#endif /* __INIT */
+#endif /* __INIT */
typedef void (*func)(void);
@@ -30,7 +30,7 @@ void __attribute__((naked)) default_handler(void)
* restricting the relative placement of default_handler and
* exception_panic.
*/
- asm volatile("bx %0\n" : : "r" (exception_panic));
+ asm volatile("bx %0\n" : : "r"(exception_panic));
}
#define table(x) x
@@ -38,8 +38,8 @@ void __attribute__((naked)) default_handler(void)
/* Note: the alias target must be defined in this translation unit */
#define weak_with_default __attribute__((used, weak, alias("default_handler")))
-#define vec(name) extern void weak_with_default name ## _handler(void);
-#define irq(num) vec(irq_ ## num)
+#define vec(name) extern void weak_with_default name##_handler(void);
+#define irq(num) vec(irq_##num)
#define item(name) extern void name(void);
#define null
@@ -47,12 +47,6 @@ void __attribute__((naked)) default_handler(void)
extern void stack_end(void); /* not technically correct, it's just a pointer */
extern void reset(void);
-#pragma GCC diagnostic push
-#if __GNUC__ >= 8
-#pragma GCC diagnostic ignored "-Wattribute-alias"
-#endif
-#pragma GCC diagnostic pop
-
#endif /* PASS 1 */
#if PASS == 2
@@ -77,69 +71,28 @@ extern void reset(void);
#pragma clang diagnostic ignored "-Winitializer-overrides"
#endif /* __clang__ */
-#define table(x) \
- const func vectors[] __attribute__((section(".text.vecttable"))) = { \
- x \
- [IRQ_UNUSED_OFFSET] = null \
- }
+#define table(x) \
+ const func vectors[] __attribute__(( \
+ section(".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null }
-#define vec(name) name ## _handler,
-#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num)
+#define vec(name) name##_handler,
+#define irq(num) \
+ [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \
+ vec(irq_##num)
#define item(name) name,
#define null (void *)0,
#endif /* PASS 2 */
-table(
- item(stack_end)
- item(reset)
- vec(nmi)
- vec(hard_fault)
- vec(mpu_fault)
- vec(bus_fault)
- vec(usage_fault)
- null
- null
- null
- null
- vec(svc)
- vec(debug)
- null
- vec(pendsv)
- vec(sys_tick)
- irq(0)
- irq(1)
- irq(2)
- irq(3)
- irq(4)
- irq(5)
- irq(6)
- irq(7)
- irq(8)
- irq(9)
- irq(10)
- irq(11)
- irq(12)
- irq(13)
- irq(14)
- irq(15)
- irq(16)
- irq(17)
- irq(18)
- irq(19)
- irq(20)
- irq(21)
- irq(22)
- irq(23)
- irq(24)
- irq(25)
- irq(26)
- irq(27)
- irq(28)
- irq(29)
- irq(30)
- irq(31)
-);
+table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec(
+ bus_fault) vec(usage_fault) null null null null vec(svc) vec(debug)
+ null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4)
+ irq(5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12)
+ irq(13) irq(14) irq(15) irq(16) irq(17) irq(18)
+ irq(19) irq(20) irq(21) irq(22) irq(23)
+ irq(24) irq(25) irq(26) irq(27)
+ irq(28) irq(29) irq(30)
+ irq(31));
#if PASS == 2
#ifdef __clang__
diff --git a/core/cortex-m0/watchdog.c b/core/cortex-m0/watchdog.c
index 9961922ee5..b4d5c086f0 100644
--- a/core/cortex-m0/watchdog.c
+++ b/core/cortex-m0/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
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