diff options
Diffstat (limited to 'core/cortex-m')
| -rw-r--r-- | core/cortex-m/atomic.h | 4 | ||||
| -rw-r--r-- | core/cortex-m/build.mk | 15 | ||||
| -rw-r--r-- | core/cortex-m/cache.S | 2 | ||||
| -rw-r--r-- | core/cortex-m/config_core.h | 2 | ||||
| -rw-r--r-- | core/cortex-m/cpu.c | 5 | ||||
| -rw-r--r-- | core/cortex-m/cpu.h | 142 | ||||
| -rw-r--r-- | core/cortex-m/debug.c | 2 | ||||
| -rw-r--r-- | core/cortex-m/debug.h | 2 | ||||
| -rw-r--r-- | core/cortex-m/ec.lds.S | 12 | ||||
| -rw-r--r-- | core/cortex-m/fpu.c | 9 | ||||
| -rw-r--r-- | core/cortex-m/include/fpu.h | 18 | ||||
| -rw-r--r-- | core/cortex-m/include/mpu.h | 66 | ||||
| -rw-r--r-- | core/cortex-m/include/mpu_private.h | 2 | ||||
| -rw-r--r-- | core/cortex-m/init.S | 2 | ||||
| -rw-r--r-- | core/cortex-m/irq_handler.h | 36 | ||||
| -rw-r--r-- | core/cortex-m/llsr.c | 23 | ||||
| -rw-r--r-- | core/cortex-m/mpu.c | 64 | ||||
| -rw-r--r-- | core/cortex-m/panic-internal.h | 4 | ||||
| -rw-r--r-- | core/cortex-m/panic.c | 71 | ||||
| -rw-r--r-- | core/cortex-m/switch.S | 2 | ||||
| -rw-r--r-- | core/cortex-m/task.c | 164 | ||||
| -rw-r--r-- | core/cortex-m/toolchain.mk | 15 | ||||
| -rw-r--r-- | core/cortex-m/vecttable.c | 361 | ||||
| -rw-r--r-- | core/cortex-m/watchdog.c | 2 |
24 files changed, 399 insertions, 626 deletions
diff --git a/core/cortex-m/atomic.h b/core/cortex-m/atomic.h index a09f5cc8be..92ecdd96e5 100644 --- a/core/cortex-m/atomic.h +++ b/core/cortex-m/atomic.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -41,4 +41,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits) return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST); } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk index bcffe16e8d..1e2c47297b 100644 --- a/core/cortex-m/build.mk +++ b/core/cortex-m/build.mk @@ -1,24 +1,11 @@ # -*- makefile -*- -# Copyright 2012 The Chromium OS Authors. All rights reserved. +# Copyright 2012 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # # Cortex-M4 core OS files build # - -ifeq ($(cc-name),gcc) -# coreboot sdk -CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi- -else -# llvm sdk -CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi- -endif - -$(call set-option,CROSS_COMPILE,\ - $(CROSS_COMPILE_arm),\ - $(CROSS_COMPILE_ARM_DEFAULT)) - # FPU compilation flags CFLAGS_FPU-$(CONFIG_FPU)=-mfloat-abi=hard ifeq ($(cc-name),gcc) diff --git a/core/cortex-m/cache.S b/core/cortex-m/cache.S index 0a3d3bb67d..d5089a920e 100644 --- a/core/cortex-m/cache.S +++ b/core/cortex-m/cache.S @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/core/cortex-m/config_core.h b/core/cortex-m/config_core.h index 0665b28852..949df7ee21 100644 --- a/core/cortex-m/config_core.h +++ b/core/cortex-m/config_core.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c index 7c31892c18..ffb6b7780c 100644 --- a/core/cortex-m/cpu.c +++ b/core/cortex-m/cpu.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -16,7 +16,8 @@ void cpu_init(void) /* Enable reporting of memory faults, bus faults and usage faults */ CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA | - CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA; + CPU_NVIC_SHCSR_BUSFAULTENA | + CPU_NVIC_SHCSR_USGFAULTENA; } #ifdef CONFIG_ARMV7M_CACHE diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index e3137cd864..8c284d6132 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,68 +10,69 @@ #include <stdint.h> #include "compile_time_macros.h" +#include "debug.h" /* Macro to access 32-bit registers */ -#define CPUREG(addr) (*(volatile uint32_t*)(addr)) +#define CPUREG(addr) (*(volatile uint32_t *)(addr)) -#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010) -#define ST_ENABLE BIT(0) -#define ST_TICKINT BIT(1) -#define ST_CLKSOURCE BIT(2) -#define ST_COUNTFLAG BIT(16) +#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010) +#define ST_ENABLE BIT(0) +#define ST_TICKINT BIT(1) +#define ST_CLKSOURCE BIT(2) +#define ST_COUNTFLAG BIT(16) /* Nested Vectored Interrupt Controller */ -#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x)) -#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x)) -#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x)) -#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) +#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x)) +#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x)) +#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x)) +#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) /* SCB AIRCR : Application interrupt and reset control register */ -#define CPU_NVIC_APINT CPUREG(0xe000ed0c) -#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ -#define CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10)) -#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ -#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16) -#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) +#define CPU_NVIC_APINT CPUREG(0xe000ed0c) +#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ +#define CPU_NVIC_APINT_PRIOGRP (BIT(8) | BIT(9) | BIT(10)) +#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ +#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16) +#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) /* NVIC STIR : Software Trigger Interrupt Register */ -#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00) +#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00) /* SCB SCR : System Control Register */ -#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) +#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) -#define CPU_NVIC_CCR CPUREG(0xe000ed14) -#define CPU_NVIC_SHCSR CPUREG(0xe000ed24) -#define CPU_NVIC_CFSR CPUREG(0xe000ed28) -#define CPU_NVIC_HFSR CPUREG(0xe000ed2c) -#define CPU_NVIC_DFSR CPUREG(0xe000ed30) -#define CPU_NVIC_MFAR CPUREG(0xe000ed34) -#define CPU_NVIC_BFAR CPUREG(0xe000ed38) +#define CPU_NVIC_CCR CPUREG(0xe000ed14) +#define CPU_NVIC_SHCSR CPUREG(0xe000ed24) +#define CPU_NVIC_CFSR CPUREG(0xe000ed28) +#define CPU_NVIC_HFSR CPUREG(0xe000ed2c) +#define CPU_NVIC_DFSR CPUREG(0xe000ed30) +#define CPU_NVIC_MFAR CPUREG(0xe000ed34) +#define CPU_NVIC_BFAR CPUREG(0xe000ed38) enum { - CPU_NVIC_CFSR_BFARVALID = BIT(15), - CPU_NVIC_CFSR_MFARVALID = BIT(7), + CPU_NVIC_CFSR_BFARVALID = BIT(15), + CPU_NVIC_CFSR_MFARVALID = BIT(7), - CPU_NVIC_CCR_ICACHE = BIT(17), - CPU_NVIC_CCR_DCACHE = BIT(16), - CPU_NVIC_CCR_DIV_0_TRAP = BIT(4), - CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3), + CPU_NVIC_CCR_ICACHE = BIT(17), + CPU_NVIC_CCR_DCACHE = BIT(16), + CPU_NVIC_CCR_DIV_0_TRAP = BIT(4), + CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3), - CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31, - CPU_NVIC_HFSR_FORCED = BIT(30), - CPU_NVIC_HFSR_VECTTBL = BIT(1), + CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31, + CPU_NVIC_HFSR_FORCED = BIT(30), + CPU_NVIC_HFSR_VECTTBL = BIT(1), - CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16), - CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17), - CPU_NVIC_SHCSR_USGFAULTENA = BIT(18), + CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16), + CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17), + CPU_NVIC_SHCSR_USGFAULTENA = BIT(18), }; /* System Control Block: cache registers */ -#define CPU_SCB_CCSIDR CPUREG(0xe000ed80) -#define CPU_SCB_CCSELR CPUREG(0xe000ed84) -#define CPU_SCB_ICIALLU CPUREG(0xe000ef50) -#define CPU_SCB_DCISW CPUREG(0xe000ef60) -#define CPU_SCB_DCCISW CPUREG(0xe000ef74) +#define CPU_SCB_CCSIDR CPUREG(0xe000ed80) +#define CPU_SCB_CCSELR CPUREG(0xe000ed84) +#define CPU_SCB_ICIALLU CPUREG(0xe000ef50) +#define CPU_SCB_DCISW CPUREG(0xe000ef60) +#define CPU_SCB_DCCISW CPUREG(0xe000ef74) /* Floating Point Context Address Register */ -#define CPU_FPU_FPCAR CPUREG(0xe000ef38) +#define CPU_FPU_FPCAR CPUREG(0xe000ef38) /* * As defined by Armv7-M Reference Manual B1.5.7 "Context state stacking on @@ -85,28 +86,29 @@ enum { #define FPU_FPSCR_UFC BIT(3) /* Underflow */ #define FPU_FPSCR_IXC BIT(4) /* Inexact */ #define FPU_FPSCR_IDC BIT(7) /* Input denormal */ -#define FPU_FPSCR_EXC_FLAGS (FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | \ - FPU_FPSCR_UFC | FPU_FPSCR_IXC | FPU_FPSCR_IDC) +#define FPU_FPSCR_EXC_FLAGS \ + (FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | FPU_FPSCR_UFC | \ + FPU_FPSCR_IXC | FPU_FPSCR_IDC) /* Bitfield values for EXC_RETURN. */ -#define EXC_RETURN_ES_MASK BIT(0) +#define EXC_RETURN_ES_MASK BIT(0) #define EXC_RETURN_ES_NON_SECURE 0 -#define EXC_RETURN_ES_SECURE BIT(0) -#define EXC_RETURN_SPSEL_MASK BIT(2) -#define EXC_RETURN_SPSEL_MSP 0 -#define EXC_RETURN_SPSEL_PSP BIT(2) -#define EXC_RETURN_MODE_MASK BIT(3) -#define EXC_RETURN_MODE_HANDLER 0 -#define EXC_RETURN_MODE_THREAD BIT(3) -#define EXC_RETURN_FTYPE_MASK BIT(4) -#define EXC_RETURN_FTYPE_ON 0 -#define EXC_RETURN_FTYPE_OFF BIT(4) -#define EXC_RETURN_DCRS_MASK BIT(5) -#define EXC_RETURN_DCRS_OFF 0 -#define EXC_RETURN_DCRS_ON BIT(5) -#define EXC_RETURN_S_MASK BIT(6) -#define EXC_RETURN_S_NON_SECURE 0 -#define EXC_RETURN_S_SECURE BIT(6) +#define EXC_RETURN_ES_SECURE BIT(0) +#define EXC_RETURN_SPSEL_MASK BIT(2) +#define EXC_RETURN_SPSEL_MSP 0 +#define EXC_RETURN_SPSEL_PSP BIT(2) +#define EXC_RETURN_MODE_MASK BIT(3) +#define EXC_RETURN_MODE_HANDLER 0 +#define EXC_RETURN_MODE_THREAD BIT(3) +#define EXC_RETURN_FTYPE_MASK BIT(4) +#define EXC_RETURN_FTYPE_ON 0 +#define EXC_RETURN_FTYPE_OFF BIT(4) +#define EXC_RETURN_DCRS_MASK BIT(5) +#define EXC_RETURN_DCRS_OFF 0 +#define EXC_RETURN_DCRS_ON BIT(5) +#define EXC_RETURN_S_MASK BIT(6) +#define EXC_RETURN_S_NON_SECURE 0 +#define EXC_RETURN_S_SECURE BIT(6) /* Set up the cpu to detect faults */ void cpu_init(void); @@ -132,10 +134,16 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority) if (priority > 7) priority = 7; - CPU_NVIC_PRI(irq / 4) = - (CPU_NVIC_PRI(irq / 4) & - ~(7 << prio_shift)) | - (priority << prio_shift); + CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(7 << prio_shift)) | + (priority << prio_shift); +} + +static inline void cpu_enter_suspend_mode(void) +{ + /* Preserve debug sessions by not suspending when connected */ + if (!debugger_is_connected()) { + asm("wfi"); + } } #endif /* __CROS_EC_CPU_H */ diff --git a/core/cortex-m/debug.c b/core/cortex-m/debug.c index db8891b5d8..214e8dd177 100644 --- a/core/cortex-m/debug.c +++ b/core/cortex-m/debug.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/core/cortex-m/debug.h b/core/cortex-m/debug.h index ae5ef08d06..30643268cb 100644 --- a/core/cortex-m/debug.h +++ b/core/cortex-m/debug.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index f85b262c18..8580e366b7 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -309,6 +309,10 @@ SECTIONS KEEP(*(.rodata.HOOK_USB_PD_CONNECT)) __hooks_usb_pd_connect_end = .; + __hooks_power_supply_change = .; + KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE)) + __hooks_power_supply_change_end = .; + __deferred_funcs = .; KEEP(*(.rodata.deferred)) __deferred_funcs_end = .; @@ -457,6 +461,12 @@ SECTIONS __data_end = .; /* + * _sbrk in newlib expects "end" symbol to point to start of + * free memory. + */ + end = .; + + /* * Shared memory buffer must be at the end of preallocated * RAM, so it can expand to use all the remaining RAM. */ diff --git a/core/cortex-m/fpu.c b/core/cortex-m/fpu.c index 29fa568fd8..6e897a5266 100644 --- a/core/cortex-m/fpu.c +++ b/core/cortex-m/fpu.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,8 +9,8 @@ #include "hooks.h" #include "task.h" -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPUTS(format, args...) cputs(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPUTS(format, args...) cputs(CC_SYSTEM, format, ##args) /* Floating point unit common code */ @@ -65,8 +65,7 @@ static void fpu_warn(void) DECLARE_DEFERRED(fpu_warn); -test_mockable -void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp) +test_mockable void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp) { /* * Get address of exception FPU exception frame. FPCAR register points diff --git a/core/cortex-m/include/fpu.h b/core/cortex-m/include/fpu.h index 0949d336e2..74862d00ab 100644 --- a/core/cortex-m/include/fpu.h +++ b/core/cortex-m/include/fpu.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,24 +12,16 @@ static inline float sqrtf(float v) { float root; - asm volatile( - "fsqrts %0, %1" - : "=w" (root) - : "w" (v) - ); + asm volatile("fsqrts %0, %1" : "=w"(root) : "w"(v)); return root; } static inline float fabsf(float v) { float root; - asm volatile( - "fabss %0, %1" - : "=w" (root) - : "w" (v) - ); + asm volatile("fabss %0, %1" : "=w"(root) : "w"(v)); return root; } -#endif /* CONFIG_FPU */ +#endif /* CONFIG_FPU */ -#endif /* __CROS_EC_FPU_H */ +#endif /* __CROS_EC_FPU_H */ diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h index 610728b501..75f95e7000 100644 --- a/core/cortex-m/include/mpu.h +++ b/core/cortex-m/include/mpu.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,7 +14,7 @@ /* * ARMv7-M SRAM region */ -#define CORTEX_M_SRAM_BASE 0x20000000 +#define CORTEX_M_SRAM_BASE 0x20000000 /* * Region assignment. 7 as the highest, a higher index has a higher priority. @@ -26,64 +26,64 @@ * made mutually exclusive. */ enum mpu_region { - REGION_DATA_RAM = 0, /* For internal data RAM */ - REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ - REGION_CODE_RAM = 2, /* For internal code RAM */ - REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ - REGION_STORAGE = 4, /* For mapped internal storage */ - REGION_STORAGE2 = 5, /* Second region for unaligned size */ - REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ - REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ + REGION_DATA_RAM = 0, /* For internal data RAM */ + REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ + REGION_CODE_RAM = 2, /* For internal code RAM */ + REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ + REGION_STORAGE = 4, /* For mapped internal storage */ + REGION_STORAGE2 = 5, /* Second region for unaligned size */ + REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ + REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ /* only for chips with MPU supporting 16 regions */ - REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ - REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ - REGION_ROLLBACK = 10, /* For rollback */ + REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ + REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ + REGION_ROLLBACK = 10, /* For rollback */ }; -#define MPU_TYPE REG32(0xe000ed90) -#define MPU_CTRL REG32(0xe000ed94) -#define MPU_NUMBER REG32(0xe000ed98) -#define MPU_BASE REG32(0xe000ed9c) -#define MPU_SIZE REG16(0xe000eda0) -#define MPU_ATTR REG16(0xe000eda2) +#define MPU_TYPE REG32(0xe000ed90) +#define MPU_CTRL REG32(0xe000ed94) +#define MPU_NUMBER REG32(0xe000ed98) +#define MPU_BASE REG32(0xe000ed9c) +#define MPU_SIZE REG16(0xe000eda0) +#define MPU_ATTR REG16(0xe000eda2) /* * See ARM v7-M Architecture Reference Manual * Section B3.5.5 MPU Type Register, MPU_TYPE */ -#define MPU_TYPE_UNIFIED_MASK 0x00FF0001 -#define MPU_TYPE_REG_COUNT(t) (((t) >> 8) & 0xFF) +#define MPU_TYPE_UNIFIED_MASK 0x00FF0001 +#define MPU_TYPE_REG_COUNT(t) (((t) >> 8) & 0xFF) -#define MPU_CTRL_PRIVDEFEN BIT(2) -#define MPU_CTRL_HFNMIENA BIT(1) -#define MPU_CTRL_ENABLE BIT(0) +#define MPU_CTRL_PRIVDEFEN BIT(2) +#define MPU_CTRL_HFNMIENA BIT(1) +#define MPU_CTRL_ENABLE BIT(0) /* * Minimum region size is 32 bytes, 5 bits of address space */ -#define MPU_SIZE_BITS_MIN 5 +#define MPU_SIZE_BITS_MIN 5 /* * XN (execute never) bit. It's bit 12 if accessed by halfword. * 0: XN off * 1: XN on */ -#define MPU_ATTR_XN BIT(12) +#define MPU_ATTR_XN BIT(12) /* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */ -#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */ -#define MPU_ATTR_RW_NO (1 << 8) /* previleged ReadWrite, unprev no access */ -#define MPU_ATTR_RW_RO (2 << 8) /* previleged ReadWrite, unprev Read-only */ -#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */ -#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */ +#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */ +#define MPU_ATTR_RW_NO (1 << 8) /* previleged ReadWrite, unprev no access */ +#define MPU_ATTR_RW_RO (2 << 8) /* previleged ReadWrite, unprev Read-only */ +#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */ +#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */ /* Suggested value for TEX S/C/B bit. See table 3-6 of Stellaris LM4F232H5QC * datasheet and table 38 of STM32F10xxx Cortex-M3 programming manual. */ #ifndef MPU_ATTR_INTERNAL_SRAM -#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */ +#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */ #endif #ifndef MPU_ATTR_FLASH_MEMORY -#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */ +#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */ #endif /* Represent RW with at most 2 MPU regions. */ diff --git a/core/cortex-m/include/mpu_private.h b/core/cortex-m/include/mpu_private.h index e6030114c2..eca474e14d 100644 --- a/core/cortex-m/include/mpu_private.h +++ b/core/cortex-m/include/mpu_private.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/core/cortex-m/init.S b/core/cortex-m/init.S index 9d4815ac79..5cde406a58 100644 --- a/core/cortex-m/init.S +++ b/core/cortex-m/init.S @@ -1,4 +1,4 @@ -/* Copyright 2011 The Chromium OS Authors. All rights reserved. +/* Copyright 2011 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/core/cortex-m/irq_handler.h b/core/cortex-m/irq_handler.h index dceda73958..eb23de7049 100644 --- a/core/cortex-m/irq_handler.h +++ b/core/cortex-m/irq_handler.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,20 +23,20 @@ * ensure it is enabled in the interrupt controller with the right priority. */ #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority) -#define DECLARE_IRQ_(irq, routine, priority) \ - void IRQ_HANDLER(irq)(void); \ - typedef struct { \ - int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1]; \ - } irq_num_check_##irq; \ - static void __keep routine(void); \ - void IRQ_HANDLER(irq)(void) \ - { \ - void *ret = __builtin_return_address(0); \ - TASK_START_IRQ_HANDLER(ret); \ - routine(); \ - task_resched_if_needed(ret); \ - } \ - const struct irq_priority __keep IRQ_PRIORITY(irq) \ - __attribute__((section(".rodata.irqprio"))) \ - = {irq, priority} -#endif /* __CROS_EC_IRQ_HANDLER_H */ +#define DECLARE_IRQ_(irq, routine, priority) \ + void IRQ_HANDLER(irq)(void); \ + typedef struct { \ + int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1]; \ + } irq_num_check_##irq; \ + static void __keep routine(void); \ + void IRQ_HANDLER(irq)(void) \ + { \ + void *ret = __builtin_return_address(0); \ + TASK_START_IRQ_HANDLER(ret); \ + routine(); \ + task_resched_if_needed(ret); \ + } \ + const struct irq_priority __keep IRQ_PRIORITY(irq) \ + __attribute__((section(".rodata.irqprio"))) = { irq, \ + priority } +#endif /* __CROS_EC_IRQ_HANDLER_H */ diff --git a/core/cortex-m/llsr.c b/core/cortex-m/llsr.c index 616b8653db..0ab920f628 100644 --- a/core/cortex-m/llsr.c +++ b/core/cortex-m/llsr.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -29,7 +29,7 @@ uint64_t __keep __aeabi_llsr(uint64_t v, uint32_t shift) #ifdef CONFIG_LLSR_TEST -static int command_llsr(int argc, char **argv) +static int command_llsr(int argc, const char **argv) { /* Volatile to prevent compilier optimization from interfering. */ volatile uint64_t start = 0x123456789ABCDEF0ull; @@ -38,13 +38,11 @@ static int command_llsr(int argc, char **argv) const struct { uint32_t shift_by; uint64_t result; - } cases[] = { - {0, start}, - {16, 0x123456789ABCull}, - {32, 0x12345678u}, - {48, 0x1234u}, - {64, 0u} - }; + } cases[] = { { 0, start }, + { 16, 0x123456789ABCull }, + { 32, 0x12345678u }, + { 48, 0x1234u }, + { 64, 0u } }; for (x = 0; x < ARRAY_SIZE(cases); ++x) { if ((start >> cases[x].shift_by) != cases[x].result) { @@ -58,8 +56,7 @@ static int command_llsr(int argc, char **argv) } DECLARE_CONSOLE_COMMAND( - llsrtest, command_llsr, - "", - "Run tests against the LLSR ABI. Prints SUCCESS or FAILURE."); + llsrtest, command_llsr, "", + "Run tests against the LLSR ABI. Prints SUCCESS or FAILURE."); -#endif /* CONFIG_LLSR_TEST */ +#endif /* CONFIG_LLSR_TEST */ diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c index 29da931a28..c0793180dc 100644 --- a/core/cortex-m/mpu.c +++ b/core/cortex-m/mpu.c @@ -1,10 +1,11 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* MPU module for Chrome EC */ +#include "builtin/assert.h" #include "mpu.h" #include "console.h" #include "cpu.h" @@ -37,7 +38,6 @@ bool mpu_is_unified(void) return (mpu_get_type() & MPU_TYPE_UNIFIED_MASK) == 0; } - /** * Update a memory region. * @@ -74,7 +74,7 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit, asm volatile("isb; dsb;"); MPU_NUMBER = region; - MPU_SIZE &= ~1; /* Disable */ + MPU_SIZE &= ~1; /* Disable */ if (enable) { MPU_BASE = addr; /* @@ -85,8 +85,8 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit, * according to the doc, but they don't ..., do a single 32-bit * one. */ - REG32(&MPU_SIZE) = ((uint32_t)attr << 16) - | (srd << 8) | ((size_bit - 1) << 1) | 1; + REG32(&MPU_SIZE) = ((uint32_t)attr << 16) | (srd << 8) | + ((size_bit - 1) << 1) | 1; } asm volatile("isb; dsb;"); @@ -117,7 +117,7 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr, * regions must be naturally aligned to their size. */ uint8_t natural_alignment = MIN(addr == 0 ? 32 : alignment_log2(addr), - alignment_log2(size)); + alignment_log2(size)); uint8_t subregion_disable = 0; if (natural_alignment >= 5) { @@ -159,10 +159,9 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr, *consumed = 1 << natural_alignment; } - return mpu_update_region(region, - addr & ~((1 << natural_alignment) - 1), - natural_alignment, - attr, enable, subregion_disable); + return mpu_update_region(region, addr & ~((1 << natural_alignment) - 1), + natural_alignment, attr, enable, + subregion_disable); } /** @@ -188,8 +187,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size, if (size == 0) return EC_SUCCESS; - rv = mpu_config_region_greedy(region, addr, size, - attr, enable, &consumed); + rv = mpu_config_region_greedy(region, addr, size, attr, enable, + &consumed); if (rv != EC_SUCCESS) return rv; ASSERT(consumed <= size); @@ -198,8 +197,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size, /* Regions other than DATA_RAM_TEXT may use two MPU regions */ if (size > 0 && region != REGION_DATA_RAM_TEXT) { - rv = mpu_config_region_greedy(region + 1, addr, size, - attr, enable, &consumed); + rv = mpu_config_region_greedy(region + 1, addr, size, attr, + enable, &consumed); if (rv != EC_SUCCESS) return rv; ASSERT(consumed <= size); @@ -223,8 +222,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size, static int mpu_unlock_region(uint8_t region, uint32_t addr, uint32_t size, uint8_t texscb) { - return mpu_config_region(region, addr, size, - MPU_ATTR_RW_RW | texscb, 1); + return mpu_config_region(region, addr, size, MPU_ATTR_RW_RW | texscb, + 1); } void mpu_enable(void) @@ -247,13 +246,9 @@ int mpu_protect_data_ram(void) int ret; /* Prevent code execution from data RAM */ - ret = mpu_config_region(REGION_DATA_RAM, - CONFIG_RAM_BASE, - CONFIG_DATA_RAM_SIZE, - MPU_ATTR_XN | - MPU_ATTR_RW_RW | - MPU_ATTR_INTERNAL_SRAM, - 1); + ret = mpu_config_region( + REGION_DATA_RAM, CONFIG_RAM_BASE, CONFIG_DATA_RAM_SIZE, + MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_INTERNAL_SRAM, 1); if (ret != EC_SUCCESS) return ret; @@ -271,18 +266,16 @@ int mpu_protect_code_ram(void) return mpu_config_region(REGION_STORAGE, CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF, CONFIG_CODE_RAM_SIZE, - MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, - 1); + MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, 1); } #else int mpu_lock_ro_flash(void) { /* Prevent execution from internal mapped RO flash */ - return mpu_config_region(REGION_STORAGE, - CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF, - CONFIG_RO_SIZE, - MPU_ATTR_XN | MPU_ATTR_RW_RW | - MPU_ATTR_FLASH_MEMORY, 1); + return mpu_config_region( + REGION_STORAGE, CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF, + CONFIG_RO_SIZE, + MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_FLASH_MEMORY, 1); } /* Represent RW with at most 2 MPU regions. */ @@ -298,8 +291,7 @@ struct mpu_rw_regions mpu_get_rw_regions(void) * the region because on the Cortex-M3, Cortex-M4 and Cortex-M7, the * address used for an MPU region must be aligned to the size. */ - aligned_size_bit = - __fls(regions.addr[0] & -regions.addr[0]); + aligned_size_bit = __fls(regions.addr[0] & -regions.addr[0]); regions.size[0] = MIN(BIT(aligned_size_bit), CONFIG_RW_SIZE); regions.addr[1] = regions.addr[0] + regions.size[0]; regions.size[1] = CONFIG_RW_SIZE - regions.size[0]; @@ -386,10 +378,10 @@ int mpu_lock_rollback(int lock) #ifdef CONFIG_CHIP_UNCACHED_REGION /* Store temporarily the regions ranges to use them for the MPU configuration */ -#define REGION(_name, _flag, _start, _size) \ - static const uint32_t CONCAT2(_region_start_, _name) \ +#define REGION(_name, _flag, _start, _size) \ + static const uint32_t CONCAT2(_region_start_, _name) \ __attribute__((unused, section(".unused"))) = _start; \ - static const uint32_t CONCAT2(_region_size_, _name) \ + static const uint32_t CONCAT2(_region_size_, _name) \ __attribute__((unused, section(".unused"))) = _size; #include "memory_regions.inc" #undef REGION @@ -424,7 +416,7 @@ int mpu_pre_init(void) * to the region size. */ rv = mpu_update_region(i, CORTEX_M_SRAM_BASE, MPU_SIZE_BITS_MIN, - 0, 0, 0); + 0, 0, 0); if (rv != EC_SUCCESS) return rv; } diff --git a/core/cortex-m/panic-internal.h b/core/cortex-m/panic-internal.h index 1a58afa8a2..6fa6440006 100644 --- a/core/cortex-m/panic-internal.h +++ b/core/cortex-m/panic-internal.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,4 +8,4 @@ void exception_panic(void) __attribute__((naked)); -#endif /* __CROS_EC_PANIC_INTERNAL_H */ +#endif /* __CROS_EC_PANIC_INTERNAL_H */ diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c index 2f71080392..3a59fcf201 100644 --- a/core/cortex-m/panic.c +++ b/core/cortex-m/panic.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,9 +20,8 @@ /* Whether bus fault is ignored */ static int bus_fault_ignored; - /* Panic data goes at the end of RAM. */ -static struct panic_data * const pdata_ptr = PANIC_DATA_PTR; +static struct panic_data *const pdata_ptr = PANIC_DATA_PTR; /* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */ static const uint32_t pstack_addr = ((uint32_t)pdata_ptr) & ~7; @@ -77,7 +76,7 @@ static int32_t is_frame_in_handler_stack(const uint32_t exc_return) #ifdef CONFIG_DEBUG_EXCEPTIONS /* Names for each of the bits in the cfs register, starting at bit 0 */ -static const char * const cfsr_name[32] = { +static const char *const cfsr_name[32] = { /* MMFSR */ [0] = "Instruction access violation", [1] = "Data access violation", @@ -101,11 +100,9 @@ static const char * const cfsr_name[32] = { }; /* Names for the first 5 bits in the DFSR */ -static const char * const dfsr_name[] = { - "Halt request", - "Breakpoint", - "Data watchpoint/trace", - "Vector catch", +static const char *const dfsr_name[] = { + "Halt request", "Breakpoint", + "Data watchpoint/trace", "Vector catch", "External debug request", }; @@ -281,7 +278,7 @@ void panic_data_print(const struct panic_data *pdata) print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12); print_reg(13, lregs, in_handler ? CORTEX_PANIC_REGISTER_MSP : - CORTEX_PANIC_REGISTER_PSP); + CORTEX_PANIC_REGISTER_PSP); print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR); print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC); @@ -310,24 +307,23 @@ void __keep report_panic(void) sp = is_frame_in_handler_stack( pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ? pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] : - pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP]; + pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP]; /* If stack is valid, copy exception frame to pdata */ - if ((sp & 3) == 0 && - sp >= CONFIG_RAM_BASE && + if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE && sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) { const uint32_t *sregs = (const uint32_t *)sp; int i; /* Skip r0-r3 and r12 registers if necessary */ for (i = CORTEX_PANIC_FRAME_REGISTER_R0; - i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++) + i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++) if (IS_ENABLED(CONFIG_PANIC_STRIP_GPR)) pdata->cm.frame[i] = 0; else pdata->cm.frame[i] = sregs[i]; for (i = CORTEX_PANIC_FRAME_REGISTER_LR; - i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++) + i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++) pdata->cm.frame[i] = sregs[i]; pdata->flags |= PANIC_DATA_FLAG_FRAME_VALID; @@ -401,38 +397,41 @@ void exception_panic(void) #endif "stmia %[pregs], {r1-r11, lr}\n" "mov sp, %[pstack]\n" - "bl report_panic\n" : : - [pregs] "r" (pdata_ptr->cm.regs), - [pstack] "r" (pstack_addr) : - /* Constraints protecting these from being clobbered. - * Gcc should be using r0 & r12 for pregs and pstack. */ - "r1", "r2", "r3", "r4", "r5", "r6", - /* clang warns that we're clobbering a reserved register: - * inline asm clobber list contains reserved registers: R7 - * [-Werror,-Winline-asm]. The intent of the clobber list is - * to force pregs and pstack to be in R0 and R12, which - * still holds. - */ + "bl report_panic\n" + : + : [pregs] "r"(pdata_ptr->cm.regs), [pstack] "r"(pstack_addr) + : + /* Constraints protecting these from being clobbered. + * Gcc should be using r0 & r12 for pregs and pstack. */ + "r1", "r2", "r3", "r4", "r5", "r6", + /* clang warns that we're clobbering a reserved register: + * inline asm clobber list contains reserved registers: R7 + * [-Werror,-Winline-asm]. The intent of the clobber list is + * to force pregs and pstack to be in R0 and R12, which + * still holds. + */ #ifndef __clang__ - "r7", + "r7", #endif - "r8", "r9", "r10", "r11", "cc", "memory" - ); + "r8", "r9", "r10", "r11", "cc", "memory"); } #ifdef CONFIG_SOFTWARE_PANIC void software_panic(uint32_t reason, uint32_t info) { - __asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n" - "mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n" - "bl exception_panic\n" - : : "r"(info), "r"(reason)); + __asm__("mov " STRINGIFY( + SOFTWARE_PANIC_INFO_REG) ", %0\n" + "mov " STRINGIFY( + SOFTWARE_PANIC_REASON_REG) ", %1\n" + "bl exception_panic\n" + : + : "r"(info), "r"(reason)); __builtin_unreachable(); } void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) { - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); uint32_t *lregs; lregs = pdata->cm.regs; @@ -452,7 +451,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) { - struct panic_data * const pdata = panic_get_data(); + struct panic_data *const pdata = panic_get_data(); uint32_t *lregs; if (pdata && pdata->struct_version == 2) { diff --git a/core/cortex-m/switch.S b/core/cortex-m/switch.S index 6573e0ecaa..512b48036f 100644 --- a/core/cortex-m/switch.S +++ b/core/cortex-m/switch.S @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 2ec1ec1dc2..ce6c8c9615 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,9 +6,11 @@ /* Task scheduling / events module for Chrome EC operating system */ #include "atomic.h" +#include "builtin/assert.h" #include "common.h" #include "console.h" #include "cpu.h" +#include "debug.h" #include "link_defs.h" #include "panic.h" #include "task.h" @@ -21,10 +23,10 @@ typedef union { * Note that sp must be the first element in the task struct * for __switchto() to work. */ - uint32_t sp; /* Saved stack pointer for context switch */ - atomic_t events; /* Bitmaps of received events */ - uint64_t runtime; /* Time spent in task */ - uint32_t *stack; /* Start of stack */ + uint32_t sp; /* Saved stack pointer for context switch */ + atomic_t events; /* Bitmaps of received events */ + uint64_t runtime; /* Time spent in task */ + uint32_t *stack; /* Start of stack */ }; } task_; @@ -40,12 +42,10 @@ CONFIG_CTS_TASK_LIST #undef TASK /* Task names for easier debugging */ -#define TASK(n, r, d, s) #n, -static const char * const task_names[] = { +#define TASK(n, r, d, s) #n, +static const char *const task_names[] = { "<< idle >>", - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST }; #undef TASK @@ -55,12 +55,12 @@ static uint64_t task_start_time; /* Time task scheduling started */ * We only keep 32-bit values for exception start/end time, to avoid * accounting errors when we service interrupt when the timer wraps around. */ -static uint32_t exc_start_time; /* Time of task->exception transition */ -static uint32_t exc_end_time; /* Time of exception->task transition */ -static uint64_t exc_total_time; /* Total time in exceptions */ -static uint32_t svc_calls; /* Number of service calls */ -static uint32_t task_switches; /* Number of times active task changed */ -static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ +static uint32_t exc_start_time; /* Time of task->exception transition */ +static uint32_t exc_end_time; /* Time of exception->task transition */ +static uint64_t exc_total_time; /* Total time in exceptions */ +static uint32_t svc_calls; /* Number of service calls */ +static uint32_t task_switches; /* Number of times active task changed */ +static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif extern void __switchto(task_ *from, task_ *to); @@ -91,21 +91,20 @@ void __idle(void) * shortly therefore, resumes execution on exiting idle mode. * Workaround: Replace the idle function with the followings */ - asm ( - "cpsid i\n" /* Disable interrupt */ - "push {r0-r5}\n" /* Save needed registers */ - "wfi\n" /* Wait for int to enter idle */ - "ldm %0, {r0-r5}\n" /* Add a delay after WFI */ - "pop {r0-r5}\n" /* Restore regs before enabling ints */ - "isb\n" /* Flush the cpu pipeline */ - "cpsie i\n" :: "r" (0x100A8000) /* Enable interrupts */ + asm("cpsid i\n" /* Disable interrupt */ + "push {r0-r5}\n" /* Save needed registers */ + "wfi\n" /* Wait for int to enter idle */ + "ldm %0, {r0-r5}\n" /* Add a delay after WFI */ + "pop {r0-r5}\n" /* Restore regs before enabling ints */ + "isb\n" /* Flush the cpu pipeline */ + "cpsie i\n" ::"r"(0x100A8000) /* Enable interrupts */ ); #else /* * Wait for the next irq event. This stops the CPU clock * (sleep / deep sleep, depending on chip config). */ - asm("wfi"); + cpu_enter_suspend_mode(); #endif } } @@ -121,20 +120,19 @@ static void task_exit_trap(void) } /* Startup parameters for all tasks. */ -#define TASK(n, r, d, s) { \ - .r0 = (uint32_t)d, \ - .pc = (uint32_t)r, \ - .stack_size = s, \ -}, +#define TASK(n, r, d, s) \ + { \ + .r0 = (uint32_t)d, \ + .pc = (uint32_t)r, \ + .stack_size = s, \ + }, static const struct { uint32_t r0; uint32_t pc; uint16_t stack_size; } tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST }; #undef TASK @@ -142,17 +140,16 @@ static const struct { static task_ tasks[TASK_ID_COUNT]; /* Reset constants and state for all tasks */ -#define TASK_RESET_SUPPORTED BIT(31) -#define TASK_RESET_LOCK BIT(30) -#define TASK_RESET_STATE_MASK (TASK_RESET_SUPPORTED | TASK_RESET_LOCK) -#define TASK_RESET_WAITERS_MASK ~TASK_RESET_STATE_MASK -#define TASK_RESET_UNSUPPORTED 0 -#define TASK_RESET_STATE_LOCKED (TASK_RESET_SUPPORTED | TASK_RESET_LOCK) -#define TASK_RESET_STATE_UNLOCKED TASK_RESET_SUPPORTED +#define TASK_RESET_SUPPORTED BIT(31) +#define TASK_RESET_LOCK BIT(30) +#define TASK_RESET_STATE_MASK (TASK_RESET_SUPPORTED | TASK_RESET_LOCK) +#define TASK_RESET_WAITERS_MASK ~TASK_RESET_STATE_MASK +#define TASK_RESET_UNSUPPORTED 0 +#define TASK_RESET_STATE_LOCKED (TASK_RESET_SUPPORTED | TASK_RESET_LOCK) +#define TASK_RESET_STATE_UNLOCKED TASK_RESET_SUPPORTED #ifdef CONFIG_TASK_RESET_LIST -#define ENABLE_RESET(n) \ - [TASK_ID_##n] = TASK_RESET_SUPPORTED, +#define ENABLE_RESET(n) [TASK_ID_##n] = TASK_RESET_SUPPORTED, static uint32_t task_reset_state[TASK_ID_COUNT] = { #ifdef CONFIG_TASK_RESET_LIST CONFIG_TASK_RESET_LIST @@ -167,13 +164,10 @@ BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8))); BUILD_ASSERT(BIT(TASK_ID_COUNT) < TASK_RESET_LOCK); /* Stacks for all tasks */ -#define TASK(n, r, d, s) + s -uint8_t task_stacks[0 - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST -] __aligned(8); +#define TASK(n, r, d, s) +s +uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST + CONFIG_CTS_TASK_LIST] __aligned(8); #undef TASK @@ -210,7 +204,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS); */ static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE); -static int start_called; /* Has task swapping started */ +static int start_called; /* Has task swapping started */ static inline task_ *__task_id_to_ptr(task_id_t id) { @@ -232,7 +226,7 @@ inline bool is_interrupt_enabled(void) int primask; /* Interrupts are enabled when PRIMASK bit is 0 */ - asm("mrs %0, primask":"=r"(primask)); + asm("mrs %0, primask" : "=r"(primask)); return !(primask & 0x1); } @@ -240,8 +234,9 @@ inline bool is_interrupt_enabled(void) inline bool in_interrupt_context(void) { int ret; - asm("mrs %0, ipsr \n" /* read exception number */ - "lsl %0, #23 \n":"=r"(ret)); /* exception bits are the 9 LSB */ + asm("mrs %0, ipsr \n" /* read exception number */ + "lsl %0, #23 \n" + : "=r"(ret)); /* exception bits are the 9 LSB */ return ret; } @@ -249,8 +244,8 @@ inline bool in_interrupt_context(void) static inline int get_interrupt_context(void) { int ret; - asm("mrs %0, ipsr \n":"=r"(ret)); /* read exception number */ - return ret & 0x1ff; /* exception bits are the 9 LSB */ + asm("mrs %0, ipsr \n" : "=r"(ret)); /* read exception number */ + return ret & 0x1ff; /* exception bits are the 9 LSB */ } #endif @@ -351,7 +346,7 @@ void svc_handler(int desched, task_id_t resched) if (next == current) return; - /* Switch to new task */ + /* Switch to new task */ #ifdef CONFIG_TASK_PROFILING task_switches++; #endif @@ -364,7 +359,7 @@ void __schedule(int desched, int resched) register int p0 asm("r0") = desched; register int p1 asm("r1") = resched; - asm("svc 0"::"r"(p0),"r"(p1)); + asm("svc 0" ::"r"(p0), "r"(p1)); } #ifdef CONFIG_TASK_PROFILING @@ -389,9 +384,9 @@ void __keep task_start_irq_handler(void *excep_return) * and we are not called from another exception (this must match the * logic for when we chain to svc_handler() below). */ - if (!need_resched_or_profiling - || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) - == EXC_RETURN_MODE_HANDLER)) + if (!need_resched_or_profiling || + (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) == + EXC_RETURN_MODE_HANDLER)) return; exc_start_time = t; @@ -404,9 +399,9 @@ void __keep task_resched_if_needed(void *excep_return) * Continue iff a rescheduling event happened or profiling is active, * and we are not called from another exception. */ - if (!need_resched_or_profiling - || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) - == EXC_RETURN_MODE_HANDLER)) + if (!need_resched_or_profiling || + (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) == + EXC_RETURN_MODE_HANDLER)) return; svc_handler(0, 0); @@ -570,10 +565,10 @@ static uint32_t init_task_context(task_id_t id) tasks[id].sp = (uint32_t)sp; /* Initial context on stack (see __switchto()) */ - sp[8] = tasks_init[id].r0; /* r0 */ - sp[13] = (uint32_t)task_exit_trap; /* lr */ - sp[14] = tasks_init[id].pc; /* pc */ - sp[15] = 0x01000000; /* psr */ + sp[8] = tasks_init[id].r0; /* r0 */ + sp[13] = (uint32_t)task_exit_trap; /* lr */ + sp[14] = tasks_init[id].pc; /* pc */ + sp[15] = 0x01000000; /* psr */ /* Fill unused stack; also used to detect stack overflow. */ for (sp = tasks[id].stack; sp < (uint32_t *)tasks[id].sp; sp++) @@ -618,8 +613,7 @@ DECLARE_DEFERRED(deferred_task_reset); * and if it matches if_value, updates the state to new_value, and returns * TRUE. */ -static int update_reset_state(uint32_t *state, - uint32_t if_value, +static int update_reset_state(uint32_t *state, uint32_t if_value, uint32_t to_value) { int update; @@ -675,8 +669,7 @@ void task_enable_resets(void) uint32_t *state = &task_reset_state[id]; if (*state == TASK_RESET_UNSUPPORTED) { - cprints(CC_TASK, - "%s called from non-resettable task, id: %d", + cprints(CC_TASK, "%s called from non-resettable task, id: %d", __func__, id); return; } @@ -719,8 +712,7 @@ void task_disable_resets(void) uint32_t *state = &task_reset_state[id]; if (*state == TASK_RESET_UNSUPPORTED) { - cprints(CC_TASK, - "%s called from non-resettable task, id %d", + cprints(CC_TASK, "%s called from non-resettable task, id %d", __func__, id); return; } @@ -775,8 +767,8 @@ int task_reset_cleanup(void) if (cleanup_req) { while (!try_release_reset_lock(state)) { /* Find the first waiter to notify. */ - task_id_t notify_id = __fls( - *state & TASK_RESET_WAITERS_MASK); + task_id_t notify_id = + __fls(*state & TASK_RESET_WAITERS_MASK); /* * Remove the task from waiters first, so that * when it wakes after being notified, it is in @@ -912,8 +904,9 @@ void mutex_lock(struct mutex *mtx) " teq %0, #0\n" " it eq\n" " strexeq %0, %2, [%1]\n" - : "=&r" (value) - : "r" (&mtx->lock), "r" (2) : "cc"); + : "=&r"(value) + : "r"(&mtx->lock), "r"(2) + : "cc"); /* * "value" is equals to 1 if the store conditional failed, * 2 if somebody else owns the mutex, 0 else. @@ -976,7 +969,7 @@ void task_print_list(void) } } -static int command_task_info(int argc, char **argv) +static int command_task_info(int argc, const char **argv) { #ifdef CONFIG_TASK_PROFILING int total = 0; @@ -1005,12 +998,11 @@ static int command_task_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info"); #ifdef CONFIG_CMD_TASKREADY -static int command_task_ready(int argc, char **argv) +static int command_task_ready(int argc, const char **argv) { if (argc < 2) { ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready); @@ -1022,8 +1014,7 @@ static int command_task_ready(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, - "[setmask]", +DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]", "Print/set ready tasks"); #endif @@ -1078,7 +1069,7 @@ int task_start(void) } #ifdef CONFIG_CMD_TASK_RESET -static int command_task_reset(int argc, char **argv) +static int command_task_reset(int argc, const char **argv) { task_id_t id; char *e; @@ -1093,7 +1084,6 @@ static int command_task_reset(int argc, char **argv) return EC_ERROR_PARAM_COUNT; } -DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset, - "task_id", +DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset, "task_id", "Reset a task"); -#endif /* CONFIG_CMD_TASK_RESET */ +#endif /* CONFIG_CMD_TASK_RESET */ diff --git a/core/cortex-m/toolchain.mk b/core/cortex-m/toolchain.mk new file mode 100644 index 0000000000..55ca2d74cd --- /dev/null +++ b/core/cortex-m/toolchain.mk @@ -0,0 +1,15 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +ifeq ($(cc-name),gcc) +# coreboot sdk +CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi- +else +# llvm sdk +CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi- +endif + +$(call set-option,CROSS_COMPILE,\ + $(CROSS_COMPILE_arm),\ + $(CROSS_COMPILE_ARM_DEFAULT)) diff --git a/core/cortex-m/vecttable.c b/core/cortex-m/vecttable.c index 4897376c1b..433898c00a 100644 --- a/core/cortex-m/vecttable.c +++ b/core/cortex-m/vecttable.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -20,20 +20,18 @@ typedef void (*func)(void); #if PASS == 1 /* Default exception handler */ void __attribute__((used, naked)) default_handler(void); -void default_handler() +void default_handler(void) { - asm( - ".thumb_func\n" - " b exception_panic" - ); + asm(".thumb_func\n" + " b exception_panic"); } #define table(x) x -#define weak_with_default __attribute__((used,weak,alias("default_handler"))) +#define weak_with_default __attribute__((used, weak, alias("default_handler"))) -#define vec(name) extern void weak_with_default name ## _handler(void); -#define irq(num) vec(irq_ ## num) +#define vec(name) extern void weak_with_default name##_handler(void); +#define irq(num) vec(irq_##num) #define item(name) extern void name(void); #define null @@ -59,21 +57,19 @@ void weak_with_default svc_handler(int desched, task_id_t resched); * This approach differs slightly from the one in the document, * it only loads r0 (desched) and r1 (resched) for svc_handler. */ -void __attribute__((used,naked)) svc_helper_handler(void); -void svc_helper_handler() +void __attribute__((used, naked)) svc_helper_handler(void); +void svc_helper_handler(void) { - asm( - ".thumb_func\n" - " tst lr, #4 /* see if called from supervisor mode */\n" - " mrs r2, msp /* get the correct stack pointer into r2 */\n" - " it ne\n" - " mrsne r2, psp\n" - " ldr r1, [r2, #4] /* get regs from stack frame */\n" - " ldr r0, [r2]\n" - " b %0 /* call svc_handler */\n" - : - : "i"(svc_handler) - ); + asm(".thumb_func\n" + " tst lr, #4 /* see if called from supervisor mode */\n" + " mrs r2, msp /* get the correct stack pointer into r2 */\n" + " it ne\n" + " mrsne r2, psp\n" + " ldr r1, [r2, #4] /* get regs from stack frame */\n" + " ldr r0, [r2]\n" + " b %0 /* call svc_handler */\n" + : + : "i"(svc_handler)); } #endif /* PASS 1 */ @@ -100,277 +96,64 @@ void svc_helper_handler() #pragma clang diagnostic ignored "-Winitializer-overrides" #endif /* __clang__ */ -#define table(x) \ - const func vectors[] __attribute__((section(".text.vecttable"))) = { \ - x \ - [IRQ_UNUSED_OFFSET] = null \ - }; +#define table(x) \ + const func vectors[] __attribute__((section( \ + ".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null }; -#define vec(name) name ## _handler, -#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num) +#define vec(name) name##_handler, +#define irq(num) \ + [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \ + vec(irq_##num) #define item(name) name, -#define null (void*)0, +#define null (void *)0, #endif /* PASS 2 */ -table( - item(stack_end) - item(reset) - vec(nmi) - vec(hard_fault) - vec(mpu_fault) - vec(bus_fault) - vec(usage_fault) - null - null - null - null - item(svc_helper_handler) - vec(debug) - null - vec(pendsv) - vec(sys_tick) - irq(0) - irq(1) - irq(2) - irq(3) - irq(4) - irq(5) - irq(6) - irq(7) - irq(8) - irq(9) - irq(10) - irq(11) - irq(12) - irq(13) - irq(14) - irq(15) - irq(16) - irq(17) - irq(18) - irq(19) - irq(20) - irq(21) - irq(22) - irq(23) - irq(24) - irq(25) - irq(26) - irq(27) - irq(28) - irq(29) - irq(30) - irq(31) - irq(32) - irq(33) - irq(34) - irq(35) - irq(36) - irq(37) - irq(38) - irq(39) - irq(40) - irq(41) - irq(42) - irq(43) - irq(44) - irq(45) - irq(46) - irq(47) - irq(48) - irq(49) - irq(50) - irq(51) - irq(52) - irq(53) - irq(54) - irq(55) - irq(56) - irq(57) - irq(58) - irq(59) - irq(60) - irq(61) - irq(62) - irq(63) - irq(64) - irq(65) - irq(66) - irq(67) - irq(68) - irq(69) - irq(70) - irq(71) - irq(72) - irq(73) - irq(74) - irq(75) - irq(76) - irq(77) - irq(78) - irq(79) - irq(80) - irq(81) - irq(82) - irq(83) - irq(84) - irq(85) - irq(86) - irq(87) - irq(88) - irq(89) - irq(90) - irq(91) - irq(92) - irq(93) - irq(94) - irq(95) - irq(96) - irq(97) - irq(98) - irq(99) - irq(100) - irq(101) - irq(102) - irq(103) - irq(104) - irq(105) - irq(106) - irq(107) - irq(108) - irq(109) - irq(110) - irq(111) - irq(112) - irq(113) - irq(114) - irq(115) - irq(116) - irq(117) - irq(118) - irq(119) - irq(120) - irq(121) - irq(122) - irq(123) - irq(124) - irq(125) - irq(126) - irq(127) - irq(128) - irq(129) - irq(130) - irq(131) - irq(132) - irq(133) - irq(134) - irq(135) - irq(136) - irq(137) - irq(138) - irq(139) - irq(140) - irq(141) - irq(142) - irq(143) - irq(144) - irq(145) - irq(146) - irq(147) - irq(148) - irq(149) - irq(150) - irq(151) - irq(152) - irq(153) - irq(154) - irq(155) - irq(156) - irq(157) - irq(158) - irq(159) - irq(160) - irq(161) - irq(162) - irq(163) - irq(164) - irq(165) - irq(166) - irq(167) - irq(168) - irq(169) - irq(170) - irq(171) - irq(172) - irq(173) - irq(174) - irq(175) - irq(176) - irq(177) - irq(178) - irq(179) - irq(180) - irq(181) - irq(182) - irq(183) - irq(184) - irq(185) - irq(186) - irq(187) - irq(188) - irq(189) - irq(190) - irq(191) - irq(192) - irq(193) - irq(194) - irq(195) - irq(196) - irq(197) - irq(198) - irq(199) - irq(200) - irq(201) - irq(202) - irq(203) - irq(204) - irq(205) - irq(206) - irq(207) - irq(208) - irq(209) - irq(210) - irq(211) - irq(212) - irq(213) - irq(214) - irq(215) - irq(216) - irq(217) - irq(218) - irq(219) - irq(220) - irq(221) - irq(222) - irq(223) - irq(224) - irq(225) - irq(226) - irq(227) - irq(228) - irq(229) - irq(230) - irq(231) - irq(232) - irq(233) - irq(234) - irq(235) - irq(236) - irq(237) - irq(238) - irq(239) -) +table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec( + bus_fault) vec(usage_fault) null null null null item(svc_helper_handler) vec(debug) + null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4) irq( + 5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12) irq(13) + irq(14) irq(15) irq(16) irq(17) irq(18) irq(19) irq(20) irq( + 21) irq(22) irq(23) irq(24) irq(25) irq(26) irq(27) + irq(28) irq(29) irq(30) irq(31) irq(32) irq(33) irq( + 34) irq(35) irq(36) irq(37) irq(38) irq(39) + irq(40) irq(41) irq(42) irq(43) irq(44) irq( + 45) irq(46) irq(47) irq(48) irq(49) + irq(50) irq(51) irq(52) irq(53) irq( + 54) irq(55) irq(56) irq(57) + irq(58) irq(59) irq(60) irq( + 61) irq(62) irq(63) + irq(64) irq(65) irq( + 66) irq(67) + irq(68) irq( + 69) irq(70) + irq(71) irq(72) irq(73) irq(74) irq(75) irq(76) irq(77) irq(78) irq(79) irq(80) irq(81) irq(82) irq(83) irq(84) irq(85) irq(86) irq(87) irq(88) irq(89) irq(90) irq(91) irq(92) irq(93) irq(94) irq(95) irq(96) irq(97) irq( + 98) irq(99) + irq(100) irq(101) irq(102) irq(103) irq(104) irq(105) irq(106) irq( + 107) irq(108) irq(109) irq(110) irq(111) irq(112) irq(113) irq(114) irq(115) + irq(116) irq(117) irq(118) irq(119) irq(120) irq(121) irq(122) irq( + 123) irq(124) irq(125) irq(126) irq(127) irq(128) irq(129) irq(130) irq(131) + irq(132) irq(133) irq(134) irq(135) irq(136) irq(137) irq(138) irq( + 139) irq(140) irq(141) irq(142) irq(143) irq(144) irq(145) irq(146) irq(147) + irq(148) irq(149) irq(150) irq(151) irq(152) irq(153) irq(154) irq( + 155) irq(156) irq(157) irq(158) irq(159) irq(160) irq(161) irq(162) irq(163) + irq(164) irq(165) irq(166) irq(167) irq(168) irq(169) irq(170) irq( + 171) irq(172) irq(173) irq(174) irq(175) irq(176) irq(177) irq(178) + irq(179) irq(180) irq(181) irq(182) irq(183) irq(184) irq(185) irq( + 186) irq(187) irq(188) irq(189) irq(190) irq(191) irq(192) + irq(193) irq(194) irq(195) irq(196) irq(197) irq(198) irq( + 199) irq(200) irq(201) irq(202) irq(203) irq(204) + irq(205) irq(206) irq(207) irq(208) irq(209) irq( + 210) irq(211) irq(212) irq(213) irq(214) + irq(215) irq(216) irq(217) irq(218) irq( + 219) irq(220) irq(221) irq(222) + irq(223) irq(224) irq(225) irq( + 226) irq(227) irq(228) + irq(229) irq(230) irq(231) irq( + 232) irq(233) irq(234) + irq(235) irq(236) irq( + 237) irq(238) + irq(239)) #if PASS == 2 #ifdef __clang__ diff --git a/core/cortex-m/watchdog.c b/core/cortex-m/watchdog.c index c9faf54b2b..a94c6a9c25 100644 --- a/core/cortex-m/watchdog.c +++ b/core/cortex-m/watchdog.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ |