diff options
Diffstat (limited to 'core/nds32/cpu.h')
| -rw-r--r-- | core/nds32/cpu.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h index 3bd5a93efc..54d1a243ba 100644 --- a/core/nds32/cpu.h +++ b/core/nds32/cpu.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -15,9 +15,9 @@ #define TASK_SCRATCHPAD_SIZE (18) /* Process Status Word bits */ -#define PSW_GIE BIT(0) /* Global Interrupt Enable */ -#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */ -#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT) +#define PSW_GIE BIT(0) /* Global Interrupt Enable */ +#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */ +#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT) #ifndef __ASSEMBLER__ @@ -26,28 +26,28 @@ /* write Process Status Word privileged register */ static inline void set_psw(uint32_t val) { - asm volatile ("mtsr %0, $PSW" : : "r"(val)); + asm volatile("mtsr %0, $PSW" : : "r"(val)); } /* read Process Status Word privileged register */ static inline uint32_t get_psw(void) { uint32_t ret; - asm volatile ("mfsr %0, $PSW" : "=r"(ret)); + asm volatile("mfsr %0, $PSW" : "=r"(ret)); return ret; } /* write Interruption Program Counter privileged register */ static inline void set_ipc(uint32_t val) { - asm volatile ("mtsr %0, $IPC" : : "r"(val)); + asm volatile("mtsr %0, $IPC" : : "r"(val)); } /* read Interruption Program Counter privileged register */ static inline uint32_t get_ipc(void) { uint32_t ret; - asm volatile ("mfsr %0, $IPC" : "=r"(ret)); + asm volatile("mfsr %0, $IPC" : "=r"(ret)); return ret; } @@ -55,7 +55,7 @@ static inline uint32_t get_ipc(void) static inline uint32_t get_itype(void) { uint32_t ret; - asm volatile ("mfsr %0, $ITYPE" : "=r"(ret)); + asm volatile("mfsr %0, $ITYPE" : "=r"(ret)); return ret; } |