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-rw-r--r--core/nds32/__builtin.c2
-rw-r--r--core/nds32/__divdi3.S2
-rw-r--r--core/nds32/__libsoftfpu.S2
-rw-r--r--core/nds32/__muldi3.S2
-rw-r--r--core/nds32/__udivdi3.S2
-rw-r--r--core/nds32/atomic.h4
-rw-r--r--core/nds32/build.mk8
-rw-r--r--core/nds32/config_core.h2
-rw-r--r--core/nds32/cpu.c4
-rw-r--r--core/nds32/cpu.h18
-rw-r--r--core/nds32/ec.lds.S12
-rw-r--r--core/nds32/include/fpu.h4
-rw-r--r--core/nds32/init.S2
-rw-r--r--core/nds32/irq_chip.h2
-rw-r--r--core/nds32/irq_handler.h18
-rw-r--r--core/nds32/math.c18
-rw-r--r--core/nds32/panic.c46
-rw-r--r--core/nds32/switch.S2
-rw-r--r--core/nds32/task.c130
-rw-r--r--core/nds32/toolchain.mk9
20 files changed, 146 insertions, 143 deletions
diff --git a/core/nds32/__builtin.c b/core/nds32/__builtin.c
index 7b1d5eea62..ae8aa4b053 100644
--- a/core/nds32/__builtin.c
+++ b/core/nds32/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
diff --git a/core/nds32/__divdi3.S b/core/nds32/__divdi3.S
index d86e8f6273..36fe00a917 100644
--- a/core/nds32/__divdi3.S
+++ b/core/nds32/__divdi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/nds32/__libsoftfpu.S b/core/nds32/__libsoftfpu.S
index 672e6bbb3d..3f2e60767f 100644
--- a/core/nds32/__libsoftfpu.S
+++ b/core/nds32/__libsoftfpu.S
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
diff --git a/core/nds32/__muldi3.S b/core/nds32/__muldi3.S
index ef4a491183..0e766de3cb 100644
--- a/core/nds32/__muldi3.S
+++ b/core/nds32/__muldi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/nds32/__udivdi3.S b/core/nds32/__udivdi3.S
index 4cb3b058fe..624faff2c5 100644
--- a/core/nds32/__udivdi3.S
+++ b/core/nds32/__udivdi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/nds32/atomic.h b/core/nds32/atomic.h
index 592834faae..746093c919 100644
--- a/core/nds32/atomic.h
+++ b/core/nds32/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -85,4 +85,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
return ret;
}
-#endif /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/nds32/build.mk b/core/nds32/build.mk
index ddd65c680b..7790b96009 100644
--- a/core/nds32/build.mk
+++ b/core/nds32/build.mk
@@ -1,17 +1,11 @@
# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Andestar v3m architecture core OS files build
#
-# Set coreboot-sdk as the default toolchain for nds32
-NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf-
-
-# Select Andes bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
-
# CPU specific compilation flags
CFLAGS_CPU+=-march=v3m -Os
LDFLAGS_EXTRA+=-mrelax
diff --git a/core/nds32/config_core.h b/core/nds32/config_core.h
index 7670e5cfad..096b244643 100644
--- a/core/nds32/config_core.h
+++ b/core/nds32/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c
index 6a3f3b5bc4..cfdddb334e 100644
--- a/core/nds32/cpu.c
+++ b/core/nds32/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
@@ -12,5 +12,5 @@ void cpu_init(void)
{
/* DLM initialization is done in init.S */
/* Global interrupt enable */
- asm volatile ("setgie.e");
+ asm volatile("setgie.e");
}
diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h
index 3bd5a93efc..54d1a243ba 100644
--- a/core/nds32/cpu.h
+++ b/core/nds32/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
@@ -15,9 +15,9 @@
#define TASK_SCRATCHPAD_SIZE (18)
/* Process Status Word bits */
-#define PSW_GIE BIT(0) /* Global Interrupt Enable */
-#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */
-#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT)
+#define PSW_GIE BIT(0) /* Global Interrupt Enable */
+#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */
+#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT)
#ifndef __ASSEMBLER__
@@ -26,28 +26,28 @@
/* write Process Status Word privileged register */
static inline void set_psw(uint32_t val)
{
- asm volatile ("mtsr %0, $PSW" : : "r"(val));
+ asm volatile("mtsr %0, $PSW" : : "r"(val));
}
/* read Process Status Word privileged register */
static inline uint32_t get_psw(void)
{
uint32_t ret;
- asm volatile ("mfsr %0, $PSW" : "=r"(ret));
+ asm volatile("mfsr %0, $PSW" : "=r"(ret));
return ret;
}
/* write Interruption Program Counter privileged register */
static inline void set_ipc(uint32_t val)
{
- asm volatile ("mtsr %0, $IPC" : : "r"(val));
+ asm volatile("mtsr %0, $IPC" : : "r"(val));
}
/* read Interruption Program Counter privileged register */
static inline uint32_t get_ipc(void)
{
uint32_t ret;
- asm volatile ("mfsr %0, $IPC" : "=r"(ret));
+ asm volatile("mfsr %0, $IPC" : "=r"(ret));
return ret;
}
@@ -55,7 +55,7 @@ static inline uint32_t get_ipc(void)
static inline uint32_t get_itype(void)
{
uint32_t ret;
- asm volatile ("mfsr %0, $ITYPE" : "=r"(ret));
+ asm volatile("mfsr %0, $ITYPE" : "=r"(ret));
return ret;
}
diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S
index fbc5ceaafd..87f6d2041a 100644
--- a/core/nds32/ec.lds.S
+++ b/core/nds32/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -185,6 +185,10 @@ SECTIONS
KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
__hooks_usb_pd_connect_end = .;
+ __hooks_power_supply_change = .;
+ KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+ __hooks_power_supply_change_end = .;
+
__deferred_funcs = .;
KEEP(*(.rodata.deferred))
__deferred_funcs_end = .;
@@ -263,6 +267,12 @@ SECTIONS
__bss_end = .;
/*
+ * _sbrk in newlib expects "end" symbol to point to start of
+ * free memory.
+ */
+ end = .;
+
+ /*
* Shared memory buffer must be at the end of preallocated RAM,
* so it can expand to use all the remaining RAM.
*/
diff --git a/core/nds32/include/fpu.h b/core/nds32/include/fpu.h
index 4f3efc2e5a..80c3395d14 100644
--- a/core/nds32/include/fpu.h
+++ b/core/nds32/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -11,4 +11,4 @@
float sqrtf(float x);
float fabsf(float x);
-#endif /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/nds32/init.S b/core/nds32/init.S
index 159f3709d3..648e3d8183 100644
--- a/core/nds32/init.S
+++ b/core/nds32/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/nds32/irq_chip.h b/core/nds32/irq_chip.h
index ca517558b3..a339bb516c 100644
--- a/core/nds32/irq_chip.h
+++ b/core/nds32/irq_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/nds32/irq_handler.h b/core/nds32/irq_handler.h
index 7e404b5d0c..b1feaa44c3 100644
--- a/core/nds32/irq_handler.h
+++ b/core/nds32/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -15,12 +15,12 @@
* Macro to connect the interrupt handler "routine" to the irq number "irq" and
* ensure it is enabled in the interrupt controller with the right priority.
*/
-#define DECLARE_IRQ(irq, routine, priority) \
- static void __keep routine(void); \
- void IRQ_HANDLER(CPU_INT(irq))(void) \
- __attribute__ ((alias(STRINGIFY(routine)))); \
- const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq)) \
- __attribute__((section(".rodata.irqprio"))) \
- = {CPU_INT(irq), priority}
+#define DECLARE_IRQ(irq, routine, priority) \
+ static void __keep routine(void); \
+ void IRQ_HANDLER(CPU_INT(irq))(void) \
+ __attribute__((alias(STRINGIFY(routine)))); \
+ const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq)) \
+ __attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \
+ priority }
-#endif /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/nds32/math.c b/core/nds32/math.c
index 496fcc0e5d..d0c8fc5c33 100644
--- a/core/nds32/math.c
+++ b/core/nds32/math.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -12,19 +12,19 @@ union ieee_float_shape_type {
};
/* Get a 32 bit int from a float. */
-#define GET_FLOAT_WORD(i, d) \
- do { \
+#define GET_FLOAT_WORD(i, d) \
+ do { \
union ieee_float_shape_type gf_u; \
- gf_u.value = (d); \
- (i) = gf_u.word; \
+ gf_u.value = (d); \
+ (i) = gf_u.word; \
} while (0)
/* Set a float from a 32 bit int. */
-#define SET_FLOAT_WORD(d, i) \
- do { \
+#define SET_FLOAT_WORD(d, i) \
+ do { \
union ieee_float_shape_type sf_u; \
- sf_u.word = (i); \
- (d) = sf_u.value; \
+ sf_u.word = (i); \
+ (d) = sf_u.value; \
} while (0)
float fabsf(float x)
diff --git a/core/nds32/panic.c b/core/nds32/panic.c
index 70e2cae3e0..a1eca1574f 100644
--- a/core/nds32/panic.c
+++ b/core/nds32/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -17,7 +17,7 @@
/* General purpose register (r6) for saving software panic reason */
#define SOFT_PANIC_GPR_REASON 6
/* General purpose register (r7) for saving software panic information */
-#define SOFT_PANIC_GPR_INFO 7
+#define SOFT_PANIC_GPR_INFO 7
#ifdef CONFIG_DEBUG_EXCEPTIONS
/**
@@ -46,7 +46,7 @@
* All other exceptions not in the abovetable should have the INST field of
* the ITYPE register set to 0.
*/
-static const char * const itype_inst[2] = {
+static const char *const itype_inst[2] = {
"a data memory access",
"an instruction fetch access",
};
@@ -54,7 +54,7 @@ static const char * const itype_inst[2] = {
/**
* bit[3-0] @ ITYPE, general exception type information.
*/
-static const char * const itype_exc_type[16] = {
+static const char *const itype_exc_type[16] = {
"Alignment check",
"Reserved instruction",
"Trap",
@@ -78,8 +78,8 @@ static const char * const itype_exc_type[16] = {
#ifdef CONFIG_SOFTWARE_PANIC
void software_panic(uint32_t reason, uint32_t info)
{
- asm volatile ("mov55 $r6, %0" : : "r"(reason));
- asm volatile ("mov55 $r7, %0" : : "r"(info));
+ asm volatile("mov55 $r6, %0" : : "r"(reason));
+ asm volatile("mov55 $r7, %0" : : "r"(info));
if (in_interrupt_context())
asm("j excep_handler");
else
@@ -94,7 +94,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
* If it was called earlier (eg. when saving nds_n8.ipc) calling it
* once again won't remove any data
*/
- struct panic_data * const pdata = get_panic_data_write();
+ struct panic_data *const pdata = get_panic_data_write();
uint32_t warning_ipc;
uint32_t *regs;
@@ -121,7 +121,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
{
- struct panic_data * const pdata = panic_get_data();
+ struct panic_data *const pdata = panic_get_data();
uint32_t *regs;
if (pdata && pdata->struct_version == 2) {
@@ -136,17 +136,17 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
#endif /* CONFIG_SOFTWARE_PANIC */
static void print_panic_information(uint32_t *regs, uint32_t itype,
- uint32_t ipc, uint32_t ipsw)
+ uint32_t ipc, uint32_t ipsw)
{
panic_printf("=== EXCEP: ITYPE=%x ===\n", itype);
- panic_printf("R0 %08x R1 %08x R2 %08x R3 %08x\n",
- regs[0], regs[1], regs[2], regs[3]);
- panic_printf("R4 %08x R5 %08x R6 %08x R7 %08x\n",
- regs[4], regs[5], regs[6], regs[7]);
- panic_printf("R8 %08x R9 %08x R10 %08x R15 %08x\n",
- regs[8], regs[9], regs[10], regs[11]);
- panic_printf("FP %08x GP %08x LP %08x SP %08x\n",
- regs[12], regs[13], regs[14], regs[15]);
+ panic_printf("R0 %08x R1 %08x R2 %08x R3 %08x\n", regs[0], regs[1],
+ regs[2], regs[3]);
+ panic_printf("R4 %08x R5 %08x R6 %08x R7 %08x\n", regs[4], regs[5],
+ regs[6], regs[7]);
+ panic_printf("R8 %08x R9 %08x R10 %08x R15 %08x\n", regs[8], regs[9],
+ regs[10], regs[11]);
+ panic_printf("FP %08x GP %08x LP %08x SP %08x\n", regs[12],
+ regs[13], regs[14], regs[15]);
panic_printf("IPC %08x IPSW %05x\n", ipc, ipsw);
if ((ipsw & PSW_INTL_MASK) == (2 << PSW_INTL_SHIFT)) {
/* 2nd level exception */
@@ -161,16 +161,16 @@ static void print_panic_information(uint32_t *regs, uint32_t itype,
if (panic_sw_reason_is_valid(regs[SOFT_PANIC_GPR_REASON])) {
#ifdef CONFIG_SOFTWARE_PANIC
panic_printf("Software panic reason %s\n",
- panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
- PANIC_SW_BASE)]);
+ panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+ PANIC_SW_BASE)]);
panic_printf("Software panic info 0x%x\n",
- regs[SOFT_PANIC_GPR_INFO]);
+ regs[SOFT_PANIC_GPR_INFO]);
#endif
} else {
panic_printf("Exception type: General exception [%s]\n",
- itype_exc_type[(itype & 0xf)]);
+ itype_exc_type[(itype & 0xf)]);
panic_printf("Exception is caused by %s\n",
- itype_inst[(itype & BIT(4))]);
+ itype_inst[(itype & BIT(4))]);
}
#endif
}
@@ -178,7 +178,7 @@ static void print_panic_information(uint32_t *regs, uint32_t itype,
void report_panic(uint32_t *regs, uint32_t itype)
{
int i;
- struct panic_data * const pdata = get_panic_data_write();
+ struct panic_data *const pdata = get_panic_data_write();
pdata->magic = PANIC_DATA_MAGIC;
pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
diff --git a/core/nds32/switch.S b/core/nds32/switch.S
index 13d1b14345..e7a8584ce5 100644
--- a/core/nds32/switch.S
+++ b/core/nds32/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
diff --git a/core/nds32/task.c b/core/nds32/task.c
index 5fc86d6050..d9ea6f191f 100644
--- a/core/nds32/task.c
+++ b/core/nds32/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -6,6 +6,7 @@
/* Task scheduling / events module for Chrome EC operating system */
#include "atomic.h"
+#include "builtin/assert.h"
#include "common.h"
#include "console.h"
#include "cpu.h"
@@ -13,6 +14,7 @@
#include "intc.h"
#include "irq_chip.h"
#include "link_defs.h"
+#include "panic.h"
#include "registers.h"
#include "task.h"
#include "timer.h"
@@ -24,10 +26,10 @@ typedef union {
* Note that sp must be the first element in the task struct
* for __switchto() to work.
*/
- uint32_t sp; /* Saved stack pointer for context switch */
- atomic_t events; /* Bitmaps of received events */
- uint64_t runtime; /* Time spent in task */
- uint32_t *stack; /* Start of stack */
+ uint32_t sp; /* Saved stack pointer for context switch */
+ atomic_t events; /* Bitmaps of received events */
+ uint64_t runtime; /* Time spent in task */
+ uint32_t *stack; /* Start of stack */
};
} task_;
@@ -42,11 +44,9 @@ CONFIG_TEST_TASK_LIST
#undef TASK
/* Task names for easier debugging */
-#define TASK(n, r, d, s) #n,
-static const char * const task_names[] = {
- "<< idle >>",
- CONFIG_TASK_LIST
- CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
+ "<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
};
#undef TASK
@@ -54,12 +54,12 @@ static const char * const task_names[] = {
static int task_will_switch;
static uint32_t exc_sub_time;
static uint64_t task_start_time; /* Time task scheduling started */
-static uint32_t exc_start_time; /* Time of task->exception transition */
-static uint32_t exc_end_time; /* Time of exception->task transition */
-static uint64_t exc_total_time; /* Total time in exceptions */
-static uint32_t svc_calls; /* Number of service calls */
-static uint32_t task_switches; /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
#endif
extern int __task_start(void);
@@ -80,7 +80,7 @@ void __idle(void)
/* doze mode */
IT83XX_ECPM_PLLCTRL = EC_PLL_DOZE;
#endif
- asm volatile ("dsb");
+ asm volatile("dsb");
/*
* Wait for the next irq event. This stops the CPU clock
* (sleep / deep sleep, depending on chip config).
@@ -100,20 +100,18 @@ static void task_exit_trap(void)
}
/* Startup parameters for all tasks. */
-#define TASK(n, r, d, s) { \
- .r0 = (uint32_t)d, \
- .pc = (uint32_t)r, \
- .stack_size = s, \
-},
+#define TASK(n, r, d, s) \
+ { \
+ .r0 = (uint32_t)d, \
+ .pc = (uint32_t)r, \
+ .stack_size = s, \
+ },
static const struct {
uint32_t r0;
uint32_t pc;
uint16_t stack_size;
-} tasks_init[] = {
- TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
- CONFIG_TASK_LIST
- CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+ CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
#undef TASK
/* Contexts for all tasks */
@@ -122,20 +120,16 @@ static task_ tasks[TASK_ID_COUNT];
BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
-
/* Stacks for all tasks */
-#define TASK(n, r, d, s) + s
-uint8_t task_stacks[0
- TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
- CONFIG_TASK_LIST
- CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+ CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
#undef TASK
/* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__
- ((section(".bss.task_scratchpad")));
+uint32_t scratchpad[TASK_SCRATCHPAD_SIZE]
+ __attribute__((section(".bss.task_scratchpad")));
task_ *current_task = (task_ *)scratchpad;
@@ -167,7 +161,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
*/
static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
-int start_called; /* Has task swapping started */
+int start_called; /* Has task swapping started */
/* interrupt number of sw interrupt */
static int sw_int_num;
@@ -213,22 +207,22 @@ void __ram_code interrupt_disable(void)
{
/* Mask all interrupts, only keep division by zero exception */
uint32_t val = BIT(30);
- asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
- asm volatile ("dsb");
+ asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
+ asm volatile("dsb");
}
void __ram_code interrupt_enable(void)
{
/* Enable HW2 ~ HW15 and division by zero exception interrupts */
uint32_t val = (BIT(30) | 0xFFFC);
- asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
+ asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
}
inline bool is_interrupt_enabled(void)
{
uint32_t val = 0;
- asm volatile ("mfsr %0, $INT_MASK" : "=r"(val));
+ asm volatile("mfsr %0, $INT_MASK" : "=r"(val));
/* Interrupts are enabled if any of HW2 ~ HW15 is enabled */
return val & 0xFFFC;
@@ -267,7 +261,7 @@ int task_start_called(void)
* Also includes emulation of software triggering interrupt vector
*/
void __ram_code __keep syscall_handler(int desched, task_id_t resched,
- int swirq)
+ int swirq)
{
/* are we emulating an interrupt ? */
if (swirq) {
@@ -307,7 +301,7 @@ task_ *next_sched_task(void)
#ifdef CONFIG_TASK_PROFILING
if (current_task != new_task) {
current_task->runtime +=
- (exc_start_time - exc_end_time - exc_sub_time);
+ (exc_start_time - exc_end_time - exc_sub_time);
task_will_switch = 1;
}
#endif
@@ -348,7 +342,7 @@ volatile int ec_int;
void __ram_code start_irq_handler(void)
{
/* save r0, r1, and r2 for syscall */
- asm volatile ("smw.adm $r0, [$sp], $r2, 0");
+ asm volatile("smw.adm $r0, [$sp], $r2, 0");
/* If this is a SW interrupt */
if (get_itype() & 8)
ec_int = sw_int_num;
@@ -369,7 +363,7 @@ void __ram_code start_irq_handler(void)
irq_dist[ec_int]++;
#endif
/* restore r0, r1, and r2 */
- asm volatile ("lmw.bim $r0, [$sp], $r2, 0");
+ asm volatile("lmw.bim $r0, [$sp], $r2, 0");
}
void end_irq_handler(void)
@@ -380,7 +374,7 @@ void end_irq_handler(void)
* save r0 and fp (fp for restore r0-r5, r15, fp, lp and sp
* while interrupt exit.
*/
- asm volatile ("smw.adm $r0, [$sp], $r0, 8");
+ asm volatile("smw.adm $r0, [$sp], $r0, 8");
t = get_time().le.lo;
p = t - exc_start_time;
@@ -395,7 +389,7 @@ void end_irq_handler(void)
}
/* restore r0 and fp */
- asm volatile ("lmw.bim $r0, [$sp], $r0, 8");
+ asm volatile("lmw.bim $r0, [$sp], $r0, 8");
#endif
}
@@ -483,37 +477,36 @@ uint32_t __ram_code read_clear_int_mask(void)
{
uint32_t int_mask, int_dis = BIT(30);
- asm volatile(
- "mfsr %0, $INT_MASK\n\t"
- "mtsr %1, $INT_MASK\n\t"
- "dsb\n\t"
- : "=&r"(int_mask)
- : "r"(int_dis));
+ asm volatile("mfsr %0, $INT_MASK\n\t"
+ "mtsr %1, $INT_MASK\n\t"
+ "dsb\n\t"
+ : "=&r"(int_mask)
+ : "r"(int_dis));
return int_mask;
}
void __ram_code set_int_mask(uint32_t val)
{
- asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
+ asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
}
static void set_int_priority(uint32_t val)
{
- asm volatile ("mtsr %0, $INT_PRI" : : "r"(val));
+ asm volatile("mtsr %0, $INT_PRI" : : "r"(val));
}
uint32_t get_int_ctrl(void)
{
uint32_t ret;
- asm volatile ("mfsr %0, $INT_CTRL" : "=r"(ret));
+ asm volatile("mfsr %0, $INT_CTRL" : "=r"(ret));
return ret;
}
void set_int_ctrl(uint32_t val)
{
- asm volatile ("mtsr %0, $INT_CTRL" : : "r"(val));
+ asm volatile("mtsr %0, $INT_CTRL" : : "r"(val));
}
void task_enable_all_tasks(void)
@@ -599,7 +592,7 @@ static void ivic_init_irqs(void)
for (i = 0; i < exc_calls; i++) {
uint8_t irq = __irqprio[i].irq;
uint8_t prio = __irqprio[i].priority;
- all_priorities |= (prio & 0x3) << (irq * 2);
+ all_priorities |= (prio & 0x3) << (irq * 2);
}
set_int_priority(all_priorities);
}
@@ -685,7 +678,7 @@ void task_print_list(void)
}
}
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
{
#ifdef CONFIG_TASK_PROFILING
int total = 0;
@@ -715,11 +708,9 @@ static int command_task_info(int argc, char **argv)
return EC_SUCCESS;
}
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
- NULL,
- "Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
{
if (argc < 2) {
ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -731,8 +722,7 @@ static int command_task_ready(int argc, char **argv)
return EC_SUCCESS;
}
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
- "[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
"Print/set ready tasks");
void task_pre_init(void)
@@ -755,11 +745,11 @@ void task_pre_init(void)
tasks[i].sp = (uint32_t)sp;
/* Initial context on stack (see __switchto()) */
- sp[7] = tasks_init[i].r0; /* r0 */
- sp[15] = (uint32_t)task_exit_trap; /* lr */
- sp[1] = tasks_init[i].pc; /* pc */
- sp[0] = 0x70009; /* psw */
- sp[16] = (uint32_t)(sp + 17); /* sp */
+ sp[7] = tasks_init[i].r0; /* r0 */
+ sp[15] = (uint32_t)task_exit_trap; /* lr */
+ sp[1] = tasks_init[i].pc; /* pc */
+ sp[0] = 0x70009; /* psw */
+ sp[16] = (uint32_t)(sp + 17); /* sp */
/* Fill unused stack; also used to detect stack overflow. */
for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/nds32/toolchain.mk b/core/nds32/toolchain.mk
new file mode 100644
index 0000000000..e2405d3054
--- /dev/null
+++ b/core/nds32/toolchain.mk
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Set coreboot-sdk as the default toolchain for nds32
+NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf-
+
+# Select Andes bare-metal toolchain
+$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
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