1 files changed, 19 insertions, 20 deletions

diff --git a/driver/ioexpander/ccgxxf.c b/driver/ioexpander/ccgxxf.c
index 08dd17c863..a95d17ada3 100644
--- a/driver/ioexpander/ccgxxf.c
+++ b/driver/ioexpander/ccgxxf.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,25 +12,25 @@
 /* Add after all include files */
 #include "ccgxxf.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 static inline int ccgxxf_read8(int ioex, int reg, int *data)
 {
 	return i2c_read8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, data);
+			 ioex_config[ioex].i2c_addr_flags, reg, data);
 }
 
 static inline int ccgxxf_update8(int ioex, int reg, uint8_t mask,
-				enum mask_update_action action)
+				 enum mask_update_action action)
 {
 	return i2c_update8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, mask, action);
+			   ioex_config[ioex].i2c_addr_flags, reg, mask, action);
 }
 
 static inline int ccgxxf_write16(int ioex, uint16_t reg, uint16_t data)
 {
 	return i2c_write16(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, data);
+			   ioex_config[ioex].i2c_addr_flags, reg, data);
 }
 
 static int ccgxxf_get_level(int ioex, int port, int mask, int *val)
@@ -64,9 +64,9 @@ static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags)
 
 	/* Push-pull output can't be configured for 1.8V level */
 	if ((flags & GPIO_OUTPUT) && (flags & GPIO_SEL_1P8V) &&
-		!(flags & GPIO_OPEN_DRAIN)) {
+	    !(flags & GPIO_OPEN_DRAIN)) {
 		CPRINTS("Invalid flags: ioex=%d, port=%d, mask=%d, flags=0x%x",
-				ioex, port, mask, flags);
+			ioex, port, mask, flags);
 
 		return EC_ERROR_INVAL;
 	}
@@ -99,7 +99,7 @@ static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags)
 	}
 
 	pin_mode = port | (pin_mode << CCGXXF_GPIO_PIN_MODE_SHIFT) |
-			(mask << CCGXXF_GPIO_PIN_MASK_SHIFT);
+		   (mask << CCGXXF_GPIO_PIN_MASK_SHIFT);
 
 	/* Note: once set the 1.8V level affect whole GPIO port */
 	if (flags & GPIO_SEL_1P8V)
@@ -111,17 +111,17 @@ static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags)
 	 */
 	if (flags & (GPIO_HIGH | GPIO_LOW)) {
 		rv = ccgxxf_set_level(ioex, port, mask,
-					flags & GPIO_HIGH ? 1 : 0);
+				      flags & GPIO_HIGH ? 1 : 0);
 		if (rv)
 			return rv;
 	}
 
-	return	ccgxxf_write16(ioex, CCGXXF_REG_GPIO_MODE, pin_mode);
+	return ccgxxf_write16(ioex, CCGXXF_REG_GPIO_MODE, pin_mode);
 }
 
 static int ccgxxf_get_flags_by_mask(int ioex, int port, int mask, int *flags)
 {
-	 /* TODO: Add it after implementing in the CCGXXF firmware. */
+	/* TODO: Add it after implementing in the CCGXXF firmware. */
 	return EC_SUCCESS;
 }
 
@@ -131,7 +131,6 @@ static int ccgxxf_enable_interrupt(int ioex, int port, int mask, int enable)
 	return EC_ERROR_UNIMPLEMENTED;
 }
 
-
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
 static int ccgxxf_get_port(int ioex, int port, int *val)
 {
@@ -146,13 +145,13 @@ int ccgxxf_init(int ioex)
 }
 
 const struct ioexpander_drv ccgxxf_ioexpander_drv = {
-	.init			= &ccgxxf_init,
-	.get_level		= &ccgxxf_get_level,
-	.set_level		= &ccgxxf_set_level,
-	.get_flags_by_mask	= &ccgxxf_get_flags_by_mask,
-	.set_flags_by_mask	= &ccgxxf_set_flags_by_mask,
-	.enable_interrupt	= &ccgxxf_enable_interrupt,
+	.init = &ccgxxf_init,
+	.get_level = &ccgxxf_get_level,
+	.set_level = &ccgxxf_set_level,
+	.get_flags_by_mask = &ccgxxf_get_flags_by_mask,
+	.set_flags_by_mask = &ccgxxf_set_flags_by_mask,
+	.enable_interrupt = &ccgxxf_enable_interrupt,
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-	.get_port		= &ccgxxf_get_port,
+	.get_port = &ccgxxf_get_port,
 #endif
 };