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Diffstat (limited to 'driver/pmic_bd99992gw.h')
-rw-r--r--driver/pmic_bd99992gw.h31
1 files changed, 0 insertions, 31 deletions
diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h
deleted file mode 100644
index e00ea1d252..0000000000
--- a/driver/pmic_bd99992gw.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ROHM BD99992GW PMIC register map.
- */
-
-#ifndef __CROS_EC_PMIC_BD99992GW_H
-#define __CROS_EC_PMIC_BD99992GW_H
-
-#include "temp_sensor/bd99992gw.h"
-
-#define BD99992GW_REG_PWRSRCINT 0x04
-#define BD99992GW_REG_RESETIRQ1 0x08
-#define BD99992GW_REG_PBCONFIG 0x14
-#define BD99992GW_REG_PWRSTAT1 0x16
-#define BD99992GW_REG_PWRSTAT2 0x17
-#define BD99992GW_REG_VCCIOCNT 0x30
-#define BD99992GW_REG_V5ADS3CNT 0x31
-#define BD99992GW_REG_V18ACNT 0x34
-#define BD99992GW_REG_V100ACNT 0x37
-#define BD99992GW_REG_V085ACNT 0x38
-#define BD99992GW_REG_VRMODECTRL 0x3b
-#define BD99992GW_REG_DISCHGCNT1 0x3c
-#define BD99992GW_REG_DISCHGCNT2 0x3d
-#define BD99992GW_REG_DISCHGCNT3 0x3e
-#define BD99992GW_REG_DISCHGCNT4 0x3f
-#define BD99992GW_REG_SDWNCTRL 0x49
-#define BD99992GW_SDWNCTRL_SWDN BIT(0) /* SWDN mask */
-
-#endif /* __CROS_EC_PMIC_BD99992GW_H */