diff options
Diffstat (limited to 'driver/retimer/anx7483.c')
| -rw-r--r-- | driver/retimer/anx7483.c | 300 |
1 files changed, 151 insertions, 149 deletions
diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c index 6804fd3de8..2194483e44 100644 --- a/driver/retimer/anx7483.c +++ b/driver/retimer/anx7483.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -19,11 +19,11 @@ * Programming guide specifies it may be as much as 30ms after chip power on * before it's ready for i2c */ -#define ANX7483_I2C_WAKE_TIMEOUT_MS 30 +#define ANX7483_I2C_WAKE_TIMEOUT_MS 30 #define ANX7483_I2C_WAKE_RETRY_DELAY_US 5000 -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Tuning defaults */ struct anx7483_tuning_set { @@ -32,163 +32,162 @@ struct anx7483_tuning_set { }; static struct anx7483_tuning_set anx7483_usb_enabled[] = { - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dp_enabled[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dock_noflip[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dock_flip[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, }; -static inline int anx7483_read(const struct usb_mux *me, - uint8_t reg, int *val) +static inline int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val) { return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val); } -static inline int anx7483_write(const struct usb_mux *me, - uint8_t reg, uint8_t val) +static inline int anx7483_write(const struct usb_mux *me, uint8_t reg, + uint8_t val) { return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val); } @@ -231,6 +230,10 @@ static int anx7483_set(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; + /* This driver treats safe mode as none */ + if (mux_state == USB_PD_MUX_SAFE_MODE) + mux_state = USB_PD_MUX_NONE; + /* * Mux is not powered in Z1 */ @@ -287,8 +290,7 @@ static enum ec_error_list anx7483_apply_tuning(const struct usb_mux *me, return EC_SUCCESS; } -enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state) +int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state) { bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; @@ -324,7 +326,7 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me, if (pin == ANX7483_PIN_UTX1) reg = ANX7483_UTX1_PORT_CFG0_REG; - else if (pin == ANX7483_PIN_UTX2) + else if (pin == ANX7483_PIN_UTX2) reg = ANX7483_UTX2_PORT_CFG0_REG; else if (pin == ANX7483_PIN_URX1) reg = ANX7483_URX1_PORT_CFG0_REG; |