diff options
Diffstat (limited to 'driver/retimer')
| -rw-r--r-- | driver/retimer/anx7483.c | 300 | ||||
| -rw-r--r-- | driver/retimer/anx7483.h | 110 | ||||
| -rw-r--r-- | driver/retimer/anx7491.h | 10 | ||||
| -rw-r--r-- | driver/retimer/bb_retimer.c | 208 | ||||
| -rw-r--r-- | driver/retimer/kb800x.c | 43 | ||||
| -rw-r--r-- | driver/retimer/kb800x.h | 70 | ||||
| -rw-r--r-- | driver/retimer/nb7v904m.c | 37 | ||||
| -rw-r--r-- | driver/retimer/nb7v904m.h | 149 | ||||
| -rw-r--r-- | driver/retimer/pi3dpx1207.c | 35 | ||||
| -rw-r--r-- | driver/retimer/pi3dpx1207.h | 38 | ||||
| -rw-r--r-- | driver/retimer/pi3hdx1204.c | 8 | ||||
| -rw-r--r-- | driver/retimer/pi3hdx1204.h | 71 | ||||
| -rw-r--r-- | driver/retimer/ps8802.c | 157 | ||||
| -rw-r--r-- | driver/retimer/ps8802.h | 132 | ||||
| -rw-r--r-- | driver/retimer/ps8811.c | 19 | ||||
| -rw-r--r-- | driver/retimer/ps8811.h | 302 | ||||
| -rw-r--r-- | driver/retimer/ps8818.c | 102 | ||||
| -rw-r--r-- | driver/retimer/ps8818.h | 99 | ||||
| -rw-r--r-- | driver/retimer/tdp142.c | 12 | ||||
| -rw-r--r-- | driver/retimer/tdp142.h | 12 | ||||
| -rw-r--r-- | driver/retimer/tusb544.c | 23 | ||||
| -rw-r--r-- | driver/retimer/tusb544.h | 115 |
22 files changed, 969 insertions, 1083 deletions
diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c index 6804fd3de8..2194483e44 100644 --- a/driver/retimer/anx7483.c +++ b/driver/retimer/anx7483.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -19,11 +19,11 @@ * Programming guide specifies it may be as much as 30ms after chip power on * before it's ready for i2c */ -#define ANX7483_I2C_WAKE_TIMEOUT_MS 30 +#define ANX7483_I2C_WAKE_TIMEOUT_MS 30 #define ANX7483_I2C_WAKE_RETRY_DELAY_US 5000 -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Tuning defaults */ struct anx7483_tuning_set { @@ -32,163 +32,162 @@ struct anx7483_tuning_set { }; static struct anx7483_tuning_set anx7483_usb_enabled[] = { - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dp_enabled[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dock_noflip[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dock_flip[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, }; -static inline int anx7483_read(const struct usb_mux *me, - uint8_t reg, int *val) +static inline int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val) { return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val); } -static inline int anx7483_write(const struct usb_mux *me, - uint8_t reg, uint8_t val) +static inline int anx7483_write(const struct usb_mux *me, uint8_t reg, + uint8_t val) { return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val); } @@ -231,6 +230,10 @@ static int anx7483_set(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; + /* This driver treats safe mode as none */ + if (mux_state == USB_PD_MUX_SAFE_MODE) + mux_state = USB_PD_MUX_NONE; + /* * Mux is not powered in Z1 */ @@ -287,8 +290,7 @@ static enum ec_error_list anx7483_apply_tuning(const struct usb_mux *me, return EC_SUCCESS; } -enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state) +int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state) { bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; @@ -324,7 +326,7 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me, if (pin == ANX7483_PIN_UTX1) reg = ANX7483_UTX1_PORT_CFG0_REG; - else if (pin == ANX7483_PIN_UTX2) + else if (pin == ANX7483_PIN_UTX2) reg = ANX7483_UTX2_PORT_CFG0_REG; else if (pin == ANX7483_PIN_URX1) reg = ANX7483_URX1_PORT_CFG0_REG; diff --git a/driver/retimer/anx7483.h b/driver/retimer/anx7483.h index d5f6723818..d489b3d8e6 100644 --- a/driver/retimer/anx7483.h +++ b/driver/retimer/anx7483.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -20,12 +20,12 @@ * 1 DP_EN (0: disable DP mode; 1: Enable DP mode.) * 0 USB_EN (1: disable USB mode; 1: enable USB mode.) */ -#define ANX7483_ANALOG_STATUS_CTRL_REG 0x07 -#define ANX7483_CTRL_REG_BYPASS_EN BIT(5) -#define ANX7483_CTRL_REG_EN BIT(4) -#define ANX7483_CTRL_FLIP_EN BIT(2) -#define ANX7483_CTRL_DP_EN BIT(1) -#define ANX7483_CTRL_USB_EN BIT(0) +#define ANX7483_ANALOG_STATUS_CTRL_REG 0x07 +#define ANX7483_CTRL_REG_BYPASS_EN BIT(5) +#define ANX7483_CTRL_REG_EN BIT(4) +#define ANX7483_CTRL_FLIP_EN BIT(2) +#define ANX7483_CTRL_DP_EN BIT(1) +#define ANX7483_CTRL_USB_EN BIT(0) /* * Register_EQ/FG/SW_EN register @@ -34,8 +34,8 @@ * 7:1 Reserved * 0 Reg_EQ/FG/SW_EN (0: from pin control; 1: from register control) */ -#define ANX7483_ENABLE_EQ_FLAT_SWING_REG 0x15 -#define ANX7483_ENABLE_EQ_FLAT_SWING_EN BIT(0) +#define ANX7483_ENABLE_EQ_FLAT_SWING_REG 0x15 +#define ANX7483_ENABLE_EQ_FLAT_SWING_EN BIT(0) /* * EQ Settings Registers @@ -43,20 +43,20 @@ * 7:4 Equilation settings when pin is input * 3:0 Fine tuning EQ step */ -#define ANX7483_UTX1_PORT_CFG0_REG 0x52 -#define ANX7483_UTX2_PORT_CFG0_REG 0x16 -#define ANX7483_URX1_PORT_CFG0_REG 0x3E -#define ANX7483_URX2_PORT_CFG0_REG 0x2A -#define ANX7483_DRX1_PORT_CFG0_REG 0x5C -#define ANX7483_DRX2_PORT_CFG0_REG 0x20 +#define ANX7483_UTX1_PORT_CFG0_REG 0x52 +#define ANX7483_UTX2_PORT_CFG0_REG 0x16 +#define ANX7483_URX1_PORT_CFG0_REG 0x3E +#define ANX7483_URX2_PORT_CFG0_REG 0x2A +#define ANX7483_DRX1_PORT_CFG0_REG 0x5C +#define ANX7483_DRX2_PORT_CFG0_REG 0x20 -#define ANX7483_CFG0_EQ_SHIFT 4 -#define ANX7483_CFG0_EQ_MASK GENMASK(7, 4) +#define ANX7483_CFG0_EQ_SHIFT 4 +#define ANX7483_CFG0_EQ_MASK GENMASK(7, 4) /* * Default CFG0 value to apply: 9.2 dB with optimized tuning step */ -#define ANX7483_CFG0_DEF 0x53 +#define ANX7483_CFG0_DEF 0x53 /* * Flat Gain Settings Registers @@ -65,17 +65,17 @@ * 5:4 Flat gain settings when pin is input * 3:0 Fine tuning EQ */ -#define ANX7483_UTX1_PORT_CFG2_REG 0x54 -#define ANX7483_UTX2_PORT_CFG2_REG 0x18 -#define ANX7483_URX1_PORT_CFG2_REG 0x40 -#define ANX7483_URX2_PORT_CFG2_REG 0x2C -#define ANX7483_DRX1_PORT_CFG2_REG 0x5E -#define ANX7483_DRX2_PORT_CFG2_REG 0x22 +#define ANX7483_UTX1_PORT_CFG2_REG 0x54 +#define ANX7483_UTX2_PORT_CFG2_REG 0x18 +#define ANX7483_URX1_PORT_CFG2_REG 0x40 +#define ANX7483_URX2_PORT_CFG2_REG 0x2C +#define ANX7483_DRX1_PORT_CFG2_REG 0x5E +#define ANX7483_DRX2_PORT_CFG2_REG 0x22 /* * Default CFG2 value to apply: 0.3 dB with optimized fine tuning */ -#define ANX7483_CFG2_DEF 0xEE +#define ANX7483_CFG2_DEF 0xEE /* * Swing and 60K Input Termination Registers @@ -85,20 +85,20 @@ * 3:2 Vendor internal use * 1:0 Swing setting when configured as input port */ -#define ANX7483_UTX1_PORT_CFG4_REG 0x56 -#define ANX7483_UTX2_PORT_CFG4_REG 0x1A -#define ANX7483_URX1_PORT_CFG4_REG 0x42 -#define ANX7483_URX2_PORT_CFG4_REG 0x2E -#define ANX7483_DRX1_PORT_CFG4_REG 0x60 -#define ANX7483_DRX2_PORT_CFG4_REG 0x24 -#define ANX7483_DTX1_PORT_CFG4_REG 0x4C -#define ANX7483_DTX2_PORT_CFG4_REG 0x38 +#define ANX7483_UTX1_PORT_CFG4_REG 0x56 +#define ANX7483_UTX2_PORT_CFG4_REG 0x1A +#define ANX7483_URX1_PORT_CFG4_REG 0x42 +#define ANX7483_URX2_PORT_CFG4_REG 0x2E +#define ANX7483_DRX1_PORT_CFG4_REG 0x60 +#define ANX7483_DRX2_PORT_CFG4_REG 0x24 +#define ANX7483_DTX1_PORT_CFG4_REG 0x4C +#define ANX7483_DTX2_PORT_CFG4_REG 0x38 /* * Default values: 1300 mV gain with 60k termination either enabled or disabled */ -#define ANX7483_CFG4_TERM_DISABLE 0x63 -#define ANX7483_CFG4_TERM_ENABLE 0x73 +#define ANX7483_CFG4_TERM_DISABLE 0x63 +#define ANX7483_CFG4_TERM_ENABLE 0x73 /* * Termination Resistance Registers @@ -108,21 +108,21 @@ * 1 Enable termination res for UTX2 path. (0:disable 1: enable.) * 0 Tune Flat Gain. */ -#define ANX7483_UTX1_PORT_CFG3_REG 0x55 -#define ANX7483_UTX2_PORT_CFG3_REG 0x19 -#define ANX7483_URX1_PORT_CFG3_REG 0x41 -#define ANX7483_URX2_PORT_CFG3_REG 0x2D -#define ANX7483_DTX1_PORT_CFG3_REG 0x4B -#define ANX7483_DTX2_PORT_CFG3_REG 0x37 -#define ANX7483_DRX1_PORT_CFG3_REG 0x5F -#define ANX7483_DRX2_PORT_CFG3_REG 0x23 +#define ANX7483_UTX1_PORT_CFG3_REG 0x55 +#define ANX7483_UTX2_PORT_CFG3_REG 0x19 +#define ANX7483_URX1_PORT_CFG3_REG 0x41 +#define ANX7483_URX2_PORT_CFG3_REG 0x2D +#define ANX7483_DTX1_PORT_CFG3_REG 0x4B +#define ANX7483_DTX2_PORT_CFG3_REG 0x37 +#define ANX7483_DRX1_PORT_CFG3_REG 0x5F +#define ANX7483_DRX2_PORT_CFG3_REG 0x23 /* * Default values: Either 100Ohm or 90Ohm, input or output */ -#define ANX7483_CFG3_100Ohm_IN 0x3A -#define ANX7483_CFG3_90Ohm_IN 0x7A -#define ANX7483_CFG3_90Ohm_OUT 0x7E +#define ANX7483_CFG3_100Ohm_IN 0x3A +#define ANX7483_CFG3_90Ohm_IN 0x7A +#define ANX7483_CFG3_90Ohm_OUT 0x7E /* * AUX_Snooping_CTRL register @@ -131,13 +131,13 @@ * 2:1 AUX_VTH (00:60mVppd, 01:90mVppd, 10:120mVppd, 11:140mVppd) * 0 AUX_Snooping_EN (0: disable; 1: enable.) */ -#define ANX7483_AUX_SNOOPING_CTRL_REG 0x13 +#define ANX7483_AUX_SNOOPING_CTRL_REG 0x13 /* * Default value: Enable snooping with 90mVppd * (register ignored outside DP mode and does not need to be cleared) */ -#define ANX7483_AUX_SNOOPING_DEF 0x13 +#define ANX7483_AUX_SNOOPING_DEF 0x13 /* * Middle Frequency Compensation @@ -146,17 +146,17 @@ * 5:3 UTX1_EQ_MFR CTLE middle-freq resistance when input * 2:0 UTX1_EQ_MFC CTLE middle-freq Capacitance */ -#define ANX7483_UTX1_PORT_CFG1_REG 0x53 -#define ANX7483_UTX2_PORT_CFG1_REG 0x17 -#define ANX7483_URX1_PORT_CFG1_REG 0x3F -#define ANX7483_URX2_PORT_CFG1_REG 0x2B -#define ANX7483_DRX1_PORT_CFG1_REG 0x5D -#define ANX7483_DRX2_PORT_CFG1_REG 0x21 +#define ANX7483_UTX1_PORT_CFG1_REG 0x53 +#define ANX7483_UTX2_PORT_CFG1_REG 0x17 +#define ANX7483_URX1_PORT_CFG1_REG 0x3F +#define ANX7483_URX2_PORT_CFG1_REG 0x2B +#define ANX7483_DRX1_PORT_CFG1_REG 0x5D +#define ANX7483_DRX2_PORT_CFG1_REG 0x21 /* * Default CFG1 setting: current bias max, Middle frequency resistance of 0x5, * Middle frequency capacitance of 0x6 */ -#define ANX7483_CFG1_DEF 0xEE +#define ANX7483_CFG1_DEF 0xEE #endif /* __CROS_EC_USB_RETIMER_ANX7483_H */ diff --git a/driver/retimer/anx7491.h b/driver/retimer/anx7491.h index 045cf9f411..9bf9594ea7 100644 --- a/driver/retimer/anx7491.h +++ b/driver/retimer/anx7491.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -9,9 +9,9 @@ #define __CROS_EC_USB_RETIMER_ANX7491_H /* I2C interface addresses */ -#define ANX7491_I2C_ADDR0_FLAGS 0x10 -#define ANX7491_I2C_ADDR1_FLAGS 0x14 -#define ANX7491_I2C_ADDR2_FLAGS 0x16 -#define ANX7491_I2C_ADDR3_FLAGS 0x11 +#define ANX7491_I2C_ADDR0_FLAGS 0x10 +#define ANX7491_I2C_ADDR1_FLAGS 0x14 +#define ANX7491_I2C_ADDR2_FLAGS 0x16 +#define ANX7491_I2C_ADDR3_FLAGS 0x11 #endif /* __CROS_EC_USB_RETIMER_ANX7491_H */ diff --git a/driver/retimer/bb_retimer.c b/driver/retimer/bb_retimer.c index c515505900..897541bfc2 100644 --- a/driver/retimer/bb_retimer.c +++ b/driver/retimer/bb_retimer.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,40 +10,45 @@ #include "common.h" #include "console.h" #include "gpio.h" +#include "hooks.h" #include "i2c.h" #include "task.h" #include "timer.h" #include "usb_pd.h" #include "util.h" -#define BB_RETIMER_REG_SIZE 4 -#define BB_RETIMER_READ_SIZE (BB_RETIMER_REG_SIZE + 1) -#define BB_RETIMER_WRITE_SIZE (BB_RETIMER_REG_SIZE + 2) -#define BB_RETIMER_MUX_DATA_PRESENT (USB_PD_MUX_USB_ENABLED \ - | USB_PD_MUX_DP_ENABLED \ - | USB_PD_MUX_SAFE_MODE \ - | USB_PD_MUX_TBT_COMPAT_ENABLED \ - | USB_PD_MUX_USB4_ENABLED) +#define BB_RETIMER_REG_SIZE 4 +#define BB_RETIMER_READ_SIZE (BB_RETIMER_REG_SIZE + 1) +#define BB_RETIMER_WRITE_SIZE (BB_RETIMER_REG_SIZE + 2) +#define BB_RETIMER_MUX_DATA_PRESENT \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \ + USB_PD_MUX_USB4_ENABLED) -#define BB_RETIMER_MUX_USB_ALT_MODE (USB_PD_MUX_USB_ENABLED\ - | USB_PD_MUX_DP_ENABLED \ - | USB_PD_MUX_TBT_COMPAT_ENABLED \ - | USB_PD_MUX_USB4_ENABLED) +#define BB_RETIMER_MUX_USB_ALT_MODE \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_TBT_COMPAT_ENABLED | USB_PD_MUX_USB4_ENABLED) -#define BB_RETIMER_MUX_USB_DP_MODE (USB_PD_MUX_USB_ENABLED \ - | USB_PD_MUX_DP_ENABLED \ - | USB_PD_MUX_USB4_ENABLED) +#define BB_RETIMER_MUX_USB_DP_MODE \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_USB4_ENABLED) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define BB_RETIMER_I2C_RETRY 5 +#define BB_RETIMER_I2C_RETRY 5 + +/* + * Mutex for BB_RETIMER_REG_CONNECTION_STATE register, which can be + * accessed from multiple tasks. + */ +static mutex_t bb_retimer_lock[CONFIG_USB_PD_PORT_MAX_COUNT]; /** * Utility functions */ -static int bb_retimer_read(const struct usb_mux *me, - const uint8_t offset, uint32_t *data) +static int bb_retimer_read(const struct usb_mux *me, const uint8_t offset, + uint32_t *data) { int rv, retry = 0; uint8_t buf[BB_RETIMER_READ_SIZE]; @@ -60,15 +65,15 @@ static int bb_retimer_read(const struct usb_mux *me, * byte[1:4] : Data [LSB -> MSB] * Stop */ - rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, - &offset, 1, buf, BB_RETIMER_READ_SIZE); + rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, &offset, 1, buf, + BB_RETIMER_READ_SIZE); if (rv == EC_SUCCESS) break; if (++retry >= BB_RETIMER_I2C_RETRY) { - CPRINTS("C%d: Retimer I2C read err=%d", - me->usb_port, rv); + CPRINTS("C%d: Retimer I2C read err=%d", me->usb_port, + rv); return rv; } msleep(10); @@ -82,8 +87,8 @@ static int bb_retimer_read(const struct usb_mux *me, return EC_SUCCESS; } -static int bb_retimer_write(const struct usb_mux *me, - const uint8_t offset, uint32_t data) +static int bb_retimer_write(const struct usb_mux *me, const uint8_t offset, + uint32_t data) { int rv, retry = 0; uint8_t buf[BB_RETIMER_WRITE_SIZE]; @@ -109,14 +114,14 @@ static int bb_retimer_write(const struct usb_mux *me, */ while (1) { rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, buf, - BB_RETIMER_WRITE_SIZE, NULL, 0); + BB_RETIMER_WRITE_SIZE, NULL, 0); if (rv == EC_SUCCESS) break; if (++retry >= BB_RETIMER_I2C_RETRY) { - CPRINTS("C%d: Retimer I2C write err=%d", - me->usb_port, rv); + CPRINTS("C%d: Retimer I2C write err=%d", me->usb_port, + rv); break; } msleep(10); @@ -157,7 +162,8 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, uint32_t *set_retimer_con) { union tbt_mode_resp_cable cable_resp = { - .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) }; + .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) + }; union tbt_mode_resp_device dev_resp; enum idh_ptype cable_type = get_usb_pd_cable_type(port); @@ -171,7 +177,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, * */ if (is_active_cable_element_retimer(port) && - (mux_state & BB_RETIMER_MUX_USB_DP_MODE)) + (mux_state & BB_RETIMER_MUX_USB_DP_MODE)) *set_retimer_con |= BB_RETIMER_RE_TIMER_DRIVER; /* @@ -184,7 +190,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, */ if ((mux_state & BB_RETIMER_MUX_USB_ALT_MODE) && ((cable_type == IDH_PTYPE_ACABLE) || - cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE)) + cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE)) *set_retimer_con |= BB_RETIMER_ACTIVE_PASSIVE; if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED || @@ -239,7 +245,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, */ if ((cable_type == IDH_PTYPE_ACABLE || cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) && - cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) + cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) *set_retimer_con |= BB_RETIMER_TBT_ACTIVE_LINK_TRAINING; /* @@ -251,9 +257,9 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, * 10..11b - Reserved */ *set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT( - mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ? - get_tbt_cable_speed(port) : - get_usb4_cable_speed(port)); + mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ? + get_tbt_cable_speed(port) : + get_usb4_cable_speed(port)); /* * Bits 29-28: TBT_GEN_SUPPORT @@ -262,8 +268,8 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, * 20.0625Gb/s, 20.000Gb/s) * 10..11b - Reserved */ - *set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION( - cable_resp.tbt_rounded); + *set_retimer_con |= + BB_RETIMER_TBT_CABLE_GENERATION(cable_resp.tbt_rounded); } } @@ -284,7 +290,8 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state, /* TODO:b/168890624: Set USB4 retimer config for UFP */ if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED) { union tbt_dev_mode_enter_cmd ufp_tbt_enter_mode = { - .raw_value = pd_ufp_get_enter_mode(port)}; + .raw_value = pd_ufp_get_enter_mode(port) + }; /* * Bit 2: RE_TIMER_DRIVER * 0 - Re-driver @@ -316,9 +323,9 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state, */ if ((IS_ENABLED(CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE) && ufp_tbt_enter_mode.intel_spec_b0 == - VENDOR_SPECIFIC_SUPPORTED) || + VENDOR_SPECIFIC_SUPPORTED) || ufp_tbt_enter_mode.vendor_spec_b1 == - VENDOR_SPECIFIC_SUPPORTED) + VENDOR_SPECIFIC_SUPPORTED) *set_retimer_con |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE; /* @@ -352,7 +359,7 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state, * Set according to TBT3 Enter Mode bit 18:16 */ *set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT( - ufp_tbt_enter_mode.tbt_cable_speed); + ufp_tbt_enter_mode.tbt_cable_speed); /* * Bits 29-28: TBT_GEN_SUPPORT * 00b - 3rd generation TBT (10.3125 and 20.625Gb/s) @@ -363,7 +370,7 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state, * Set according to TBT3 Enter Mode bit 20:19 */ *set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION( - ufp_tbt_enter_mode.tbt_rounded); + ufp_tbt_enter_mode.tbt_rounded); } } @@ -376,10 +383,13 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, uint32_t set_retimer_con = 0; uint8_t dp_pin_mode; int port = me->usb_port; + int rv = 0; /* This driver does not use host command ACKs */ *ack_required = false; + mutex_lock(&bb_retimer_lock[port]); + /* * Bit 0: DATA_CONNECTION_PRESENT * 0 - No connection present @@ -413,14 +423,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, set_retimer_con |= BB_RETIMER_USB_3_SPEED; } - /* - * Bit 8: DP_CONNECTION - * 0 – No DP connection - * 1 – DP connected - */ if (mux_state & USB_PD_MUX_DP_ENABLED) { - set_retimer_con |= BB_RETIMER_DP_CONNECTION; - /* * Bit 11-10: DP_PIN_ASSIGNMENT (ignored if BIT8 = 0) * 00 – Pin assignments E/E’ @@ -429,7 +432,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, */ dp_pin_mode = get_dp_pin_mode(port); if (dp_pin_mode == MODE_DP_PIN_C || - dp_pin_mode == MODE_DP_PIN_D) + dp_pin_mode == MODE_DP_PIN_D) set_retimer_con |= BB_RETIMER_DP_PIN_ASSIGNMENT; /* @@ -471,22 +474,28 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, retimer_set_state_ufp(port, mux_state, &set_retimer_con); /* Writing the register4 */ - return bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, - set_retimer_con); + rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, + set_retimer_con); + mutex_unlock(&bb_retimer_lock[port]); + return rv; } void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { uint32_t retimer_con_reg = 0; + int port = me->usb_port; /* This driver does not use host command ACKs */ *ack_required = false; + mutex_lock(&bb_retimer_lock[port]); + if (bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE, - &retimer_con_reg) != EC_SUCCESS) + &retimer_con_reg) != EC_SUCCESS) { + mutex_unlock(&bb_retimer_lock[port]); return; - + } /* * Bit 14: IRQ_HPD (ignored if BIT8 = 0) * 0 - No IRQ_HPD @@ -498,19 +507,69 @@ void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, retimer_con_reg &= ~BB_RETIMER_IRQ_HPD; /* + * Bit 8: DP_CONNECTION + * 0 - No DP connection + * 1 - DP connected + * * Bit 15: HPD_LVL (ignored if BIT8 = 0) * 0 - HPD_State Low * 1 - HPD_State High + * + * HDMI card connect to chromebook the DP_CONNECTION bit + * would be enable. + * It will increase BBR power consumption, so enable the DP bit + * only when the HPD bit is set so that the retimer stays in + * low power mode until the external monitor is connected. */ if (mux_state & USB_PD_MUX_HPD_LVL) - retimer_con_reg |= BB_RETIMER_HPD_LVL; + retimer_con_reg |= + (BB_RETIMER_HPD_LVL | BB_RETIMER_DP_CONNECTION); else - retimer_con_reg &= ~BB_RETIMER_HPD_LVL; + retimer_con_reg &= + ~(BB_RETIMER_HPD_LVL | BB_RETIMER_DP_CONNECTION); /* Writing the register4 */ bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, retimer_con_reg); + + mutex_unlock(&bb_retimer_lock[port]); +} + +void bb_retimer_set_usb3(const struct usb_mux *me, bool enable) +{ + int rv; + uint32_t reg_val = 0; + int port = me->usb_port; + + mutex_lock(&bb_retimer_lock[port]); + + rv = bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE, ®_val); + if (rv != EC_SUCCESS) { + mutex_unlock(&bb_retimer_lock[port]); + return; + } + /* Bit 5: USB_3_CONNECTION */ + WRITE_BIT(reg_val, 5, enable); + rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, reg_val); + if (rv != EC_SUCCESS) { + mutex_unlock(&bb_retimer_lock[port]); + return; + } + + mutex_unlock(&bb_retimer_lock[port]); } +#ifdef CONFIG_ZEPHYR +static void init_retimer_mutexes(void) +{ + int port; + + for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) { + k_mutex_init(&bb_retimer_lock[port]); + } +} +DECLARE_HOOK(HOOK_INIT, init_retimer_mutexes, HOOK_PRIO_FIRST); +#endif + static int retimer_low_power_mode(const struct usb_mux *me) { return bb_retimer_power_enable(me, false); @@ -538,14 +597,21 @@ static int retimer_init(const struct usb_mux *me) return rv; rv = bb_retimer_read(me, BB_RETIMER_REG_VENDOR_ID, &data); + /* + * After reset, i2c controller may not be ready, if this fails, + * retry one more time. + * TODO: revisit the delay time after retimer reset. + */ + if (rv != EC_SUCCESS) + rv = bb_retimer_read(me, BB_RETIMER_REG_VENDOR_ID, &data); if (rv != EC_SUCCESS) return rv; + CPRINTS("C%d: retimer power enable success", me->usb_port); #ifdef CONFIG_USBC_RETIMER_INTEL_HB if (data != BB_RETIMER_DEVICE_ID) return EC_ERROR_INVAL; #else - if ((data != BB_RETIMER_VENDOR_ID_1) && - data != BB_RETIMER_VENDOR_ID_2) + if ((data != BB_RETIMER_VENDOR_ID_1) && data != BB_RETIMER_VENDOR_ID_2) return EC_ERROR_INVAL; rv = bb_retimer_read(me, BB_RETIMER_REG_DEVICE_ID, &data); @@ -566,12 +632,13 @@ const struct usb_mux_driver bb_usb_retimer = { }; #ifdef CONFIG_CMD_RETIMER -static int console_command_bb_retimer(int argc, char **argv) +static int console_command_bb_retimer(int argc, const char **argv) { char rw, *e; int port, reg, data, val = 0; int rv = EC_SUCCESS; const struct usb_mux *mux; + const struct usb_mux_chain *mux_chain; if (argc < 4) return EC_ERROR_PARAM_COUNT; @@ -581,14 +648,15 @@ static int console_command_bb_retimer(int argc, char **argv) if (*e || !board_is_usb_pd_port_present(port)) return EC_ERROR_PARAM1; - mux = &usb_muxes[port]; - while (mux) { + mux_chain = &usb_muxes[port]; + while (mux_chain) { + mux = mux_chain->mux; if (mux->driver == &bb_usb_retimer) break; - mux = mux->next_mux; + mux_chain = mux_chain->next; } - if (!mux) + if (!mux_chain) return EC_ERROR_PARAM1; /* Validate r/w selection */ @@ -608,17 +676,17 @@ static int console_command_bb_retimer(int argc, char **argv) return EC_ERROR_PARAM4; } - for (; mux != NULL; mux = mux->next_mux) { + for (; mux_chain != NULL; mux_chain = mux_chain->next) { + mux = mux_chain->mux; if (mux->driver == &bb_usb_retimer) { if (rw == 'r') rv = bb_retimer_read(mux, reg, &data); else { rv = bb_retimer_write(mux, reg, val); if (rv == EC_SUCCESS) { - rv = bb_retimer_read( - mux, reg, &data); - if (rv == EC_SUCCESS && data != val) - rv = EC_ERROR_UNKNOWN; + rv = bb_retimer_read(mux, reg, &data); + if (rv == EC_SUCCESS && data != val) + rv = EC_ERROR_UNKNOWN; } } if (rv == EC_SUCCESS) diff --git a/driver/retimer/kb800x.c b/driver/retimer/kb800x.c index 44bd166c14..35ab5b183d 100644 --- a/driver/retimer/kb800x.c +++ b/driver/retimer/kb800x.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -79,14 +79,15 @@ static const uint8_t usb_ss_lane_to_eb[] = { [KB800X_TX0] = KB800X_EB4, /* Assign a phy TX to an elastic buffer */ static int kb800x_assign_tx_to_eb(const struct usb_mux *me, - enum kb800x_phy_lane phy_lane, enum kb800x_eb eb) + enum kb800x_phy_lane phy_lane, + enum kb800x_eb eb) { uint8_t field_value = 0; uint8_t regval; int rv; field_value = KB800X_PHY_IS_AB(phy_lane) ? tx_eb_to_field_ab[eb] : - tx_eb_to_field_cd[eb]; + tx_eb_to_field_cd[eb]; /* For lane1 of each PHY, shift by 3 bits */ field_value <<= 3 * KB800X_LANE_NUMBER_FROM_PHY(phy_lane); @@ -95,20 +96,19 @@ static int kb800x_assign_tx_to_eb(const struct usb_mux *me, if (rv) return rv; return kb800x_write(me, KB800X_REG_TXSEL_FROM_PHY(phy_lane), - regval | field_value); + regval | field_value); } - /* Assign a phy RX to an elastic buffer */ static int kb800x_assign_rx_to_eb(const struct usb_mux *me, - enum kb800x_phy_lane phy_lane, enum kb800x_eb eb) + enum kb800x_phy_lane phy_lane, + enum kb800x_eb eb) { uint16_t address = 0; uint8_t field_value = 0; uint8_t regval = 0; int rv; - field_value = rx_phy_lane_to_field[phy_lane]; address = rx_eb_to_address[eb]; @@ -246,13 +246,11 @@ static int kb800x_xbar_override(const struct usb_mux *me) for (i = KB800X_A0; i < KB800X_PHY_LANE_COUNT; ++i) { rv = kb800x_assign_lane( - me, i, - kb800x_control[me->usb_port].ss_lanes[i]); + me, i, kb800x_control[me->usb_port].ss_lanes[i]); if (rv) return rv; } - return kb800x_write(me, KB800X_REG_XBAR_OVR, - KB800X_XBAR_OVR_EN); + return kb800x_write(me, KB800X_REG_XBAR_OVR, KB800X_XBAR_OVR_EN); } #endif /* CONFIG_KB800X_CUSTOM_XBAR */ @@ -314,8 +312,8 @@ static int kb800x_dp_init(const struct usb_mux *me, mux_state_t mux_state) me, KB800X_REG_ORIENTATION, KB800X_ORIENTATION_DP_DFP | ((mux_state & USB_PD_MUX_POLARITY_INVERTED) ? - KB800X_ORIENTATION_POLARITY : - 0x0)); + KB800X_ORIENTATION_POLARITY : + 0x0)); } static int kb800x_usb3_init(const struct usb_mux *me, mux_state_t mux_state) @@ -356,7 +354,7 @@ static int kb800x_cio_init(const struct usb_mux *me, mux_state_t mux_state) if (!(mux_state & USB_PD_MUX_USB4_ENABLED)) { /* Special configuration only for legacy mode */ if (cable_type == IDH_PTYPE_ACABLE || - cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) { + cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) { /* Active cable */ if (cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) { orientation |= @@ -391,7 +389,7 @@ static int kb800x_set_state(const struct usb_mux *me, mux_state_t mux_state, return rv; /* Release memory map reset */ rv = kb800x_write(me, KB800X_REG_RESET, - KB800X_RESET_MASK & ~KB800X_RESET_MM); + KB800X_RESET_MASK & ~KB800X_RESET_MM); if (rv) return rv; @@ -476,11 +474,12 @@ static int kb800x_enter_low_power_mode(const struct usb_mux *me) #ifdef CONFIG_CMD_RETIMER -static int console_command_kb800x_xfer(int argc, char **argv) +static int console_command_kb800x_xfer(int argc, const char **argv) { char rw, *e; int rv, port, reg, val; uint8_t data; + const struct usb_mux_chain *mux_chain; const struct usb_mux *mux; if (argc < 4) @@ -491,16 +490,18 @@ static int console_command_kb800x_xfer(int argc, char **argv) if (*e || !board_is_usb_pd_port_present(port)) return EC_ERROR_PARAM1; - mux = &usb_muxes[port]; - while (mux) { - if (mux->driver == &kb800x_usb_mux_driver) + mux_chain = &usb_muxes[port]; + while (mux_chain) { + if (mux_chain->mux->driver == &kb800x_usb_mux_driver) break; - mux = mux->next_mux; + mux_chain = mux_chain->next; } - if (!mux) + if (!mux_chain) return EC_ERROR_PARAM1; + mux = mux_chain->mux; + /* Validate r/w selection */ rw = argv[2][0]; if (rw != 'w' && rw != 'r') diff --git a/driver/retimer/kb800x.h b/driver/retimer/kb800x.h index 5f8cf2810d..1d041f3e29 100644 --- a/driver/retimer/kb800x.h +++ b/driver/retimer/kb800x.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,54 +12,49 @@ #include "gpio_signal.h" #include "usb_mux.h" -#define KB800X_I2C_ADDR0_FLAGS 0x08 -#define KB800X_I2C_ADDR1_FLAGS 0x0C +#define KB800X_I2C_ADDR0_FLAGS 0x08 +#define KB800X_I2C_ADDR1_FLAGS 0x0C extern const struct usb_mux_driver kb800x_usb_mux_driver; /* Set the protocol */ -#define KB800X_REG_PROTOCOL 0x0001 -#define KB800X_PROTOCOL_USB3 0x0 -#define KB800X_PROTOCOL_DPMF 0x1 -#define KB800X_PROTOCOL_DP 0x2 -#define KB800X_PROTOCOL_CIO 0x3 +#define KB800X_REG_PROTOCOL 0x0001 +#define KB800X_PROTOCOL_USB3 0x0 +#define KB800X_PROTOCOL_DPMF 0x1 +#define KB800X_PROTOCOL_DP 0x2 +#define KB800X_PROTOCOL_CIO 0x3 /* Configure the lane orientaitons */ -#define KB800X_REG_ORIENTATION 0x0002 -#define KB800X_ORIENTATION_POLARITY 0x1 -#define KB800X_ORIENTATION_DP_UFP 0x4 -#define KB800X_ORIENTATION_DP_DFP 0x6 -#define KB800X_ORIENTATION_CIO_LANE_SWAP 0x8 +#define KB800X_REG_ORIENTATION 0x0002 +#define KB800X_ORIENTATION_POLARITY 0x1 +#define KB800X_ORIENTATION_DP_UFP 0x4 +#define KB800X_ORIENTATION_DP_DFP 0x6 +#define KB800X_ORIENTATION_CIO_LANE_SWAP 0x8 /* Select one, 0x0 for non-legacy */ -#define KB800X_ORIENTATION_CIO_LEGACY_PASSIVE (0x1 << 4) -#define KB800X_ORIENTATION_CIO_LEGACY_UNIDIR (0x2 << 4) -#define KB800X_ORIENTATION_CIO_LEGACY_BIDIR (0x3 << 4) +#define KB800X_ORIENTATION_CIO_LEGACY_PASSIVE (0x1 << 4) +#define KB800X_ORIENTATION_CIO_LEGACY_UNIDIR (0x2 << 4) +#define KB800X_ORIENTATION_CIO_LEGACY_BIDIR (0x3 << 4) -#define KB800X_REG_RESET 0x0006 -#define KB800X_RESET_FSM BIT(0) -#define KB800X_RESET_MM BIT(1) -#define KB800X_RESET_SERDES BIT(2) -#define KB800X_RESET_COM BIT(3) -#define KB800X_RESET_MASK GENMASK(3, 0) +#define KB800X_REG_RESET 0x0006 +#define KB800X_RESET_FSM BIT(0) +#define KB800X_RESET_MM BIT(1) +#define KB800X_RESET_SERDES BIT(2) +#define KB800X_RESET_COM BIT(3) +#define KB800X_RESET_MASK GENMASK(3, 0) -#define KB800X_REG_XBAR_OVR 0x5040 -#define KB800X_XBAR_OVR_EN BIT(6) +#define KB800X_REG_XBAR_OVR 0x5040 +#define KB800X_XBAR_OVR_EN BIT(6) /* Registers to configure the elastic buffer input connection */ -#define KB800X_REG_XBAR_EB1SEL 0x5044 -#define KB800X_REG_XBAR_EB23SEL 0x5045 -#define KB800X_REG_XBAR_EB4SEL 0x5046 -#define KB800X_REG_XBAR_EB56SEL 0x5047 +#define KB800X_REG_XBAR_EB1SEL 0x5044 +#define KB800X_REG_XBAR_EB23SEL 0x5045 +#define KB800X_REG_XBAR_EB4SEL 0x5046 +#define KB800X_REG_XBAR_EB56SEL 0x5047 /* Registers to configure the elastic buffer output connection (x=0-7) */ -#define KB800X_REG_TXSEL_FROM_PHY(x) (0x5048+((x)/2)) +#define KB800X_REG_TXSEL_FROM_PHY(x) (0x5048 + ((x) / 2)) -enum kb800x_ss_lane { - KB800X_TX0 = 0, - KB800X_TX1, - KB800X_RX0, - KB800X_RX1 -}; +enum kb800x_ss_lane { KB800X_TX0 = 0, KB800X_TX1, KB800X_RX0, KB800X_RX1 }; enum kb800x_phy_lane { KB800X_A0 = 0, @@ -82,8 +77,8 @@ enum kb800x_eb { KB800X_EB6 }; -#define KB800X_FLIP_SS_LANE(x) ((x) + 1 - 2*((x) & 0x1)) -#define KB800X_LANE_NUMBER_FROM_PHY(x) ((x) & 0x1) +#define KB800X_FLIP_SS_LANE(x) ((x) + 1 - 2 * ((x)&0x1)) +#define KB800X_LANE_NUMBER_FROM_PHY(x) ((x)&0x1) #define KB800X_PHY_IS_AB(x) ((x) <= KB800X_B1) struct kb800x_control_t { @@ -106,5 +101,4 @@ struct kb800x_control_t { extern struct kb800x_control_t kb800x_control[]; - #endif /* __CROS_EC_KB800X_H */ diff --git a/driver/retimer/nb7v904m.c b/driver/retimer/nb7v904m.c index 94e96230b2..58c57e5c95 100644 --- a/driver/retimer/nb7v904m.c +++ b/driver/retimer/nb7v904m.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,8 +12,8 @@ #include "nb7v904m.h" #include "usb_mux.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #ifdef CONFIG_NB7V904M_LPM_OVERRIDE int nb7v904m_lpm_disable = 0; @@ -21,18 +21,12 @@ int nb7v904m_lpm_disable = 0; static int nb7v904m_write(const struct usb_mux *me, int offset, int data) { - return i2c_write8(me->i2c_port, - me->i2c_addr_flags, - offset, data); - + return i2c_write8(me->i2c_port, me->i2c_addr_flags, offset, data); } static int nb7v904m_read(const struct usb_mux *me, int offset, int *regval) { - return i2c_read8(me->i2c_port, - me->i2c_addr_flags, - offset, regval); - + return i2c_read8(me->i2c_port, me->i2c_addr_flags, offset, regval); } static int set_low_power_mode(const struct usb_mux *me, bool enable) @@ -68,7 +62,7 @@ static int nb7v904m_enter_low_power_mode(const struct usb_mux *me) /* Tune USB Eq All: This must be called on board_init context */ int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a, - uint8_t eq_b, uint8_t eq_c, uint8_t eq_d) + uint8_t eq_b, uint8_t eq_c, uint8_t eq_d) { int rv = EC_SUCCESS; @@ -89,7 +83,7 @@ int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a, /* Tune USB Flat Gain: This must be called on board_init context */ int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a, - uint8_t gain_b, uint8_t gain_c, uint8_t gain_d) + uint8_t gain_b, uint8_t gain_c, uint8_t gain_d) { int rv = EC_SUCCESS; @@ -110,7 +104,8 @@ int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a, /* Set Loss Profile Matching : This must be called on board_init context */ int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a, - uint8_t loss_b, uint8_t loss_c, uint8_t loss_d) + uint8_t loss_b, uint8_t loss_c, + uint8_t loss_d) { int rv = EC_SUCCESS; @@ -157,6 +152,10 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; + /* This driver treats safe mode as none */ + if (mux_state == USB_PD_MUX_SAFE_MODE) + mux_state = USB_PD_MUX_NONE; + /* Turn off redriver if it's not needed at all. */ if (mux_state == USB_PD_MUX_NONE) return nb7v904m_enter_low_power_mode(me); @@ -168,8 +167,8 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* Clear operation mode field */ rv = nb7v904m_read(me, NB7V904M_REG_GEN_DEV_SETTINGS, ®val); if (rv) { - CPRINTS("C%d %s: Failed to obtain dev settings!", - me->usb_port, __func__); + CPRINTS("C%d %s: Failed to obtain dev settings!", me->usb_port, + __func__); return rv; } regval &= ~NB7V904M_OP_MODE_MASK; @@ -193,9 +192,9 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Connect AUX */ - rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL, flipped ? - NB7V904M_AUX_CH_FLIPPED : - NB7V904M_AUX_CH_NORMAL); + rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL, + flipped ? NB7V904M_AUX_CH_FLIPPED : + NB7V904M_AUX_CH_NORMAL); /* Enable all channels for DP */ regval |= NB7V904M_CH_EN_MASK; } else { diff --git a/driver/retimer/nb7v904m.h b/driver/retimer/nb7v904m.h index d19602153c..07c3b4d51f 100644 --- a/driver/retimer/nb7v904m.h +++ b/driver/retimer/nb7v904m.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -16,99 +16,99 @@ #define NB7V904M_I2C_ADDR2 0x1C /* Registers */ -#define NB7V904M_REG_GEN_DEV_SETTINGS 0x00 -#define NB7V904M_REG_CH_A_EQ_SETTINGS 0x01 -#define NB7V904M_REG_CH_B_EQ_SETTINGS 0x03 -#define NB7V904M_REG_CH_C_EQ_SETTINGS 0x05 -#define NB7V904M_REG_CH_D_EQ_SETTINGS 0x07 -#define NB7V904M_REG_AUX_CH_CTRL 0x09 -#define NB7V904M_REG_CH_A_FLAT_GAIN 0x18 -#define NB7V904M_REG_CH_A_LOSS_CTRL 0x19 -#define NB7V904M_REG_CH_B_FLAT_GAIN 0x1a -#define NB7V904M_REG_CH_B_LOSS_CTRL 0x1b -#define NB7V904M_REG_CH_C_FLAT_GAIN 0x1c -#define NB7V904M_REG_CH_C_LOSS_CTRL 0x1d -#define NB7V904M_REG_CH_D_FLAT_GAIN 0x1e -#define NB7V904M_REG_CH_D_LOSS_CTRL 0x1f +#define NB7V904M_REG_GEN_DEV_SETTINGS 0x00 +#define NB7V904M_REG_CH_A_EQ_SETTINGS 0x01 +#define NB7V904M_REG_CH_B_EQ_SETTINGS 0x03 +#define NB7V904M_REG_CH_C_EQ_SETTINGS 0x05 +#define NB7V904M_REG_CH_D_EQ_SETTINGS 0x07 +#define NB7V904M_REG_AUX_CH_CTRL 0x09 +#define NB7V904M_REG_CH_A_FLAT_GAIN 0x18 +#define NB7V904M_REG_CH_A_LOSS_CTRL 0x19 +#define NB7V904M_REG_CH_B_FLAT_GAIN 0x1a +#define NB7V904M_REG_CH_B_LOSS_CTRL 0x1b +#define NB7V904M_REG_CH_C_FLAT_GAIN 0x1c +#define NB7V904M_REG_CH_C_LOSS_CTRL 0x1d +#define NB7V904M_REG_CH_D_FLAT_GAIN 0x1e +#define NB7V904M_REG_CH_D_LOSS_CTRL 0x1f /* 0x00 - General Device Settings */ -#define NB7V904M_CHIP_EN BIT(0) -#define NB7V904M_USB_DP_NORMAL BIT(1) +#define NB7V904M_CHIP_EN BIT(0) +#define NB7V904M_USB_DP_NORMAL BIT(1) #define NB7V904M_USB_DP_FLIPPED 0 -#define NB7V904M_DP_ONLY BIT(2) -#define NB7V904M_USB_ONLY (BIT(3) | BIT(1)) -#define NB7V904M_OP_MODE_MASK GENMASK(3, 1) -#define NB7V904M_CH_A_EN BIT(4) -#define NB7V904M_CH_B_EN BIT(5) -#define NB7V904M_CH_C_EN BIT(6) -#define NB7V904M_CH_D_EN BIT(7) -#define NB7V904M_CH_EN_MASK GENMASK(7, 4) +#define NB7V904M_DP_ONLY BIT(2) +#define NB7V904M_USB_ONLY (BIT(3) | BIT(1)) +#define NB7V904M_OP_MODE_MASK GENMASK(3, 1) +#define NB7V904M_CH_A_EN BIT(4) +#define NB7V904M_CH_B_EN BIT(5) +#define NB7V904M_CH_C_EN BIT(6) +#define NB7V904M_CH_D_EN BIT(7) +#define NB7V904M_CH_EN_MASK GENMASK(7, 4) /* 0x01 - Channel A Equalization Settings */ -#define NB7V904M_CH_A_EQ_0_DB 0x0a -#define NB7V904M_CH_A_EQ_2_DB 0x08 -#define NB7V904M_CH_A_EQ_4_DB 0x0e -#define NB7V904M_CH_A_EQ_6_DB 0x0c -#define NB7V904M_CH_A_EQ_8_DB 0x02 -#define NB7V904M_CH_A_EQ_10_DB 0x00 +#define NB7V904M_CH_A_EQ_0_DB 0x0a +#define NB7V904M_CH_A_EQ_2_DB 0x08 +#define NB7V904M_CH_A_EQ_4_DB 0x0e +#define NB7V904M_CH_A_EQ_6_DB 0x0c +#define NB7V904M_CH_A_EQ_8_DB 0x02 +#define NB7V904M_CH_A_EQ_10_DB 0x00 /* 0x03 - Channel B Equalization Settings */ -#define NB7V904M_CH_B_EQ_0_DB 0x0e -#define NB7V904M_CH_B_EQ_2_DB 0x0c -#define NB7V904M_CH_B_EQ_4_DB 0x0a -#define NB7V904M_CH_B_EQ_6_DB 0x08 -#define NB7V904M_CH_B_EQ_8_DB 0x06 -#define NB7V904M_CH_B_EQ_10_DB 0x00 +#define NB7V904M_CH_B_EQ_0_DB 0x0e +#define NB7V904M_CH_B_EQ_2_DB 0x0c +#define NB7V904M_CH_B_EQ_4_DB 0x0a +#define NB7V904M_CH_B_EQ_6_DB 0x08 +#define NB7V904M_CH_B_EQ_8_DB 0x06 +#define NB7V904M_CH_B_EQ_10_DB 0x00 /* 0x05 - Channel C Equalization Settings */ -#define NB7V904M_CH_C_EQ_0_DB 0x0e -#define NB7V904M_CH_C_EQ_2_DB 0x0c -#define NB7V904M_CH_C_EQ_4_DB 0x0a -#define NB7V904M_CH_C_EQ_6_DB 0x08 -#define NB7V904M_CH_C_EQ_8_DB 0x06 -#define NB7V904M_CH_C_EQ_10_DB 0x00 +#define NB7V904M_CH_C_EQ_0_DB 0x0e +#define NB7V904M_CH_C_EQ_2_DB 0x0c +#define NB7V904M_CH_C_EQ_4_DB 0x0a +#define NB7V904M_CH_C_EQ_6_DB 0x08 +#define NB7V904M_CH_C_EQ_8_DB 0x06 +#define NB7V904M_CH_C_EQ_10_DB 0x00 /* 0x07 - Channel D Equalization Settings */ -#define NB7V904M_CH_D_EQ_0_DB 0x0a -#define NB7V904M_CH_D_EQ_2_DB 0x08 -#define NB7V904M_CH_D_EQ_4_DB 0x0e -#define NB7V904M_CH_D_EQ_6_DB 0x0c -#define NB7V904M_CH_D_EQ_8_DB 0x02 -#define NB7V904M_CH_D_EQ_10_DB 0x00 +#define NB7V904M_CH_D_EQ_0_DB 0x0a +#define NB7V904M_CH_D_EQ_2_DB 0x08 +#define NB7V904M_CH_D_EQ_4_DB 0x0e +#define NB7V904M_CH_D_EQ_6_DB 0x0c +#define NB7V904M_CH_D_EQ_8_DB 0x02 +#define NB7V904M_CH_D_EQ_10_DB 0x00 /* 0x09 - Auxiliary Channel Control */ -#define NB7V904M_AUX_CH_NORMAL 0 -#define NB7V904M_AUX_CH_FLIPPED BIT(0) -#define NB7V904M_AUX_CH_HI_Z BIT(1) +#define NB7V904M_AUX_CH_NORMAL 0 +#define NB7V904M_AUX_CH_FLIPPED BIT(0) +#define NB7V904M_AUX_CH_HI_Z BIT(1) /* 0x18 - Channel A Flag Gain */ -#define NB7V904M_CH_A_GAIN_0_DB 0x00 -#define NB7V904M_CH_A_GAIN_1P5_DB 0x02 -#define NB7V904M_CH_A_GAIN_3P5_DB 0x03 +#define NB7V904M_CH_A_GAIN_0_DB 0x00 +#define NB7V904M_CH_A_GAIN_1P5_DB 0x02 +#define NB7V904M_CH_A_GAIN_3P5_DB 0x03 /* 0x1a - Channel B Flag Gain */ -#define NB7V904M_CH_B_GAIN_0_DB 0x03 -#define NB7V904M_CH_B_GAIN_1P5_DB 0x01 -#define NB7V904M_CH_B_GAIN_3P5_DB 0x00 +#define NB7V904M_CH_B_GAIN_0_DB 0x03 +#define NB7V904M_CH_B_GAIN_1P5_DB 0x01 +#define NB7V904M_CH_B_GAIN_3P5_DB 0x00 /* 0x1c - Channel C Flag Gain */ -#define NB7V904M_CH_C_GAIN_0_DB 0x03 -#define NB7V904M_CH_C_GAIN_1P5_DB 0x01 -#define NB7V904M_CH_C_GAIN_3P5_DB 0x00 +#define NB7V904M_CH_C_GAIN_0_DB 0x03 +#define NB7V904M_CH_C_GAIN_1P5_DB 0x01 +#define NB7V904M_CH_C_GAIN_3P5_DB 0x00 /* 0x1e - Channel D Flag Gain */ -#define NB7V904M_CH_D_GAIN_0_DB 0x00 -#define NB7V904M_CH_D_GAIN_1P5_DB 0x02 -#define NB7V904M_CH_D_GAIN_3P5_DB 0x03 +#define NB7V904M_CH_D_GAIN_0_DB 0x00 +#define NB7V904M_CH_D_GAIN_1P5_DB 0x02 +#define NB7V904M_CH_D_GAIN_3P5_DB 0x03 /* 0x19 - Channel A Loss Profile Matching Control */ /* 0x1b - Channel B Loss Profile Matching Control */ /* 0x1d - Channel C Loss Profile Matching Control */ /* 0x1f - Channel D Loss Profile Matching Control */ -#define NB7V904M_LOSS_PROFILE_A 0x00 -#define NB7V904M_LOSS_PROFILE_B 0x01 -#define NB7V904M_LOSS_PROFILE_C 0x02 -#define NB7V904M_LOSS_PROFILE_D 0x03 +#define NB7V904M_LOSS_PROFILE_A 0x00 +#define NB7V904M_LOSS_PROFILE_B 0x01 +#define NB7V904M_LOSS_PROFILE_C 0x02 +#define NB7V904M_LOSS_PROFILE_D 0x03 extern const struct usb_mux_driver nb7v904m_usb_redriver_drv; #ifdef CONFIG_NB7V904M_LPM_OVERRIDE @@ -116,18 +116,19 @@ extern int nb7v904m_lpm_disable; #endif /* Use this value if tuning eq wants to be skipped */ -#define NB7V904M_CH_ALL_SKIP_EQ 0xff +#define NB7V904M_CH_ALL_SKIP_EQ 0xff int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a, - uint8_t eq_b, uint8_t eq_c, uint8_t eq_d); + uint8_t eq_b, uint8_t eq_c, uint8_t eq_d); /* Use this value if tuning gain wants to be skipped */ -#define NB7V904M_CH_ALL_SKIP_GAIN 0xff +#define NB7V904M_CH_ALL_SKIP_GAIN 0xff int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a, - uint8_t gain_b, uint8_t gain_c, uint8_t gain_d); + uint8_t gain_b, uint8_t gain_c, uint8_t gain_d); /* Use this value if loss profile control wants to be skipped */ -#define NB7V904M_CH_ALL_SKIP_LOSS 0xff +#define NB7V904M_CH_ALL_SKIP_LOSS 0xff /* Control channel Loss Profile Matching */ int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a, - uint8_t loss_b, uint8_t loss_c, uint8_t loss_d); + uint8_t loss_b, uint8_t loss_c, + uint8_t loss_d); /* Control mapping between AUX and SBU */ int nb7v904m_set_aux_ch_switch(const struct usb_mux *me, uint8_t aux_ch); #endif /* __CROS_EC_USB_REDRIVER_NB7V904M_H */ diff --git a/driver/retimer/pi3dpx1207.c b/driver/retimer/pi3dpx1207.c index 8829c508a1..27ea474832 100644 --- a/driver/retimer/pi3dpx1207.c +++ b/driver/retimer/pi3dpx1207.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -21,8 +21,7 @@ static uint8_t buf[PI3DPX1207_NUM_REGISTERS]; /** * Local utility functions */ -static int pi3dpx1207_i2c_write(const struct usb_mux *me, - uint8_t offset, +static int pi3dpx1207_i2c_write(const struct usb_mux *me, uint8_t offset, uint8_t val) { int rv = EC_SUCCESS; @@ -44,8 +43,8 @@ static int pi3dpx1207_i2c_write(const struct usb_mux *me, attempt = 0; do { attempt++; - rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, - NULL, 0, buf, offset); + rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, NULL, 0, + buf, offset); } while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES)); } @@ -55,8 +54,8 @@ static int pi3dpx1207_i2c_write(const struct usb_mux *me, attempt = 0; do { attempt++; - rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, - buf, offset + 1, NULL, 0); + rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, buf, + offset + 1, NULL, 0); } while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES)); } return rv; @@ -102,31 +101,35 @@ static int pi3dpx1207_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; + /* This driver treats safe mode as none */ + if (mux_state == USB_PD_MUX_SAFE_MODE) + mux_state = USB_PD_MUX_NONE; + /* USB */ if (mux_state & USB_PD_MUX_USB_ENABLED) { gpio_or_ioex_set_level(gpio_enable, 1); /* USB with DP */ if (mux_state & USB_PD_MUX_DP_ENABLED) { gpio_or_ioex_set_level(gpio_dp_enable, 1); - mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? PI3DPX1207_MODE_CONF_USB_DP_FLIP - : PI3DPX1207_MODE_CONF_USB_DP; + mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + PI3DPX1207_MODE_CONF_USB_DP_FLIP : + PI3DPX1207_MODE_CONF_USB_DP; } /* USB without DP */ else { gpio_or_ioex_set_level(gpio_dp_enable, 0); - mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? PI3DPX1207_MODE_CONF_USB_FLIP - : PI3DPX1207_MODE_CONF_USB; + mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + PI3DPX1207_MODE_CONF_USB_FLIP : + PI3DPX1207_MODE_CONF_USB; } } /* DP without USB */ else if (mux_state & USB_PD_MUX_DP_ENABLED) { gpio_or_ioex_set_level(gpio_enable, 1); gpio_or_ioex_set_level(gpio_dp_enable, 1); - mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? PI3DPX1207_MODE_CONF_DP_FLIP - : PI3DPX1207_MODE_CONF_DP; + mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + PI3DPX1207_MODE_CONF_DP_FLIP : + PI3DPX1207_MODE_CONF_DP; } /* Nothing enabled, power down the retimer */ else { diff --git a/driver/retimer/pi3dpx1207.h b/driver/retimer/pi3dpx1207.h index ec3c9b42bc..b246052f2c 100644 --- a/driver/retimer/pi3dpx1207.h +++ b/driver/retimer/pi3dpx1207.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -9,35 +9,35 @@ #ifndef __CROS_EC_USB_RETIMER_PI3PDX1207_H #define __CROS_EC_USB_RETIMER_PI3PDX1207_H -#define PI3DPX1207_I2C_ADDR_FLAGS 0x57 -#define PI3DPX1207_NUM_REGISTERS 32 +#define PI3DPX1207_I2C_ADDR_FLAGS 0x57 +#define PI3DPX1207_NUM_REGISTERS 32 /* Register Offset 0 - Revision and Vendor ID */ -#define PI3DPX1207_VID_OFFSET 0 +#define PI3DPX1207_VID_OFFSET 0 -#define PI3DPX1207B_VID 0x03 -#define PI3DPX1207C_VID 0x13 +#define PI3DPX1207B_VID 0x03 +#define PI3DPX1207C_VID 0x13 /* Register Offset 1 - Device Type/ID */ -#define PI3DPX1207_DID_OFFSET 1 +#define PI3DPX1207_DID_OFFSET 1 -#define PI3DPX1207_DID_ACTIVE_MUX 0x11 +#define PI3DPX1207_DID_ACTIVE_MUX 0x11 /* Register Offset 3 - Mode Control */ -#define PI3DPX1207_MODE_OFFSET 3 +#define PI3DPX1207_MODE_OFFSET 3 -#define PI3DPX1207_MODE_WATCHDOG_EN 0x02 +#define PI3DPX1207_MODE_WATCHDOG_EN 0x02 -#define PI3DPX1207B_MODE_GEN_APP_EN 0x08 +#define PI3DPX1207B_MODE_GEN_APP_EN 0x08 -#define PI3DPX1207_MODE_CONF_SAFE 0x00 -#define PI3DPX1207_MODE_CONF_DP 0x20 -#define PI3DPX1207_MODE_CONF_DP_FLIP 0x30 -#define PI3DPX1207_MODE_CONF_USB 0x40 -#define PI3DPX1207_MODE_CONF_USB_FLIP 0x50 -#define PI3DPX1207_MODE_CONF_USB_DP 0x60 -#define PI3DPX1207_MODE_CONF_USB_DP_FLIP 0x70 -#define PI3DPX1207_MODE_CONF_USB_SUPER 0xC0 +#define PI3DPX1207_MODE_CONF_SAFE 0x00 +#define PI3DPX1207_MODE_CONF_DP 0x20 +#define PI3DPX1207_MODE_CONF_DP_FLIP 0x30 +#define PI3DPX1207_MODE_CONF_USB 0x40 +#define PI3DPX1207_MODE_CONF_USB_FLIP 0x50 +#define PI3DPX1207_MODE_CONF_USB_DP 0x60 +#define PI3DPX1207_MODE_CONF_USB_DP_FLIP 0x70 +#define PI3DPX1207_MODE_CONF_USB_SUPER 0xC0 /* Supported USB retimer drivers */ extern const struct usb_mux_driver pi3dpx1207_usb_retimer; diff --git a/driver/retimer/pi3hdx1204.c b/driver/retimer/pi3hdx1204.c index 0431610059..7cf963c7f9 100644 --- a/driver/retimer/pi3hdx1204.c +++ b/driver/retimer/pi3hdx1204.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -9,8 +9,7 @@ #include "i2c.h" #include "pi3hdx1204.h" -int pi3hdx1204_enable(const int i2c_port, - const uint16_t i2c_addr_flags, +int pi3hdx1204_enable(const int i2c_port, const uint16_t i2c_addr_flags, const int enable) { const uint8_t buf[PI3HDX1204_DE_OFFSET + 1] = { @@ -27,8 +26,7 @@ int pi3hdx1204_enable(const int i2c_port, }; int rv; - rv = i2c_xfer(i2c_port, i2c_addr_flags, - buf, PI3HDX1204_DE_OFFSET + 1, + rv = i2c_xfer(i2c_port, i2c_addr_flags, buf, PI3HDX1204_DE_OFFSET + 1, NULL, 0); if (rv) diff --git a/driver/retimer/pi3hdx1204.h b/driver/retimer/pi3hdx1204.h index f758149c10..637accaf56 100644 --- a/driver/retimer/pi3hdx1204.h +++ b/driver/retimer/pi3hdx1204.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -8,62 +8,61 @@ #ifndef __CROS_EC_USB_RETIMER_PI3HDX1204_H #define __CROS_EC_USB_RETIMER_PI3HDX1204_H -#define PI3HDX1204_I2C_ADDR_FLAGS 0x60 +#define PI3HDX1204_I2C_ADDR_FLAGS 0x60 /* Register Offset 0 - Activity */ -#define PI3HDX1204_ACTIVITY_OFFSET 0 +#define PI3HDX1204_ACTIVITY_OFFSET 0 /* Register Offset 1 - Not Used */ -#define PI3HDX1204_NOT_USED_OFFSET 1 +#define PI3HDX1204_NOT_USED_OFFSET 1 /* Register Offset 2 - Enable */ -#define PI3HDX1204_ENABLE_OFFSET 2 -#define PI3HDX1204_ENABLE_ALL_CHANNELS 0xF0 +#define PI3HDX1204_ENABLE_OFFSET 2 +#define PI3HDX1204_ENABLE_ALL_CHANNELS 0xF0 /* Register Offset 3 - EQ setting BIT7-4:CH1, BIT3-0:CH0 */ -#define PI3HDX1204_EQ_CH0_CH1_OFFSET 3 +#define PI3HDX1204_EQ_CH0_CH1_OFFSET 3 /* Register Offset 4 - EQ setting BIT7-4:CH3, BIT3-0:CH2 */ -#define PI3HDX1204_EQ_CH2_CH3_OFFSET 4 +#define PI3HDX1204_EQ_CH2_CH3_OFFSET 4 /* EQ setting for two channel */ -#define PI3HDX1204_EQ_DB25 0x00 -#define PI3HDX1204_EQ_DB80 0x11 -#define PI3HDX1204_EQ_DB110 0x22 -#define PI3HDX1204_EQ_DB220 0x33 -#define PI3HDX1204_EQ_DB410 0x44 -#define PI3HDX1204_EQ_DB710 0x55 -#define PI3HDX1204_EQ_DB900 0x66 -#define PI3HDX1204_EQ_DB1030 0x77 -#define PI3HDX1204_EQ_DB1180 0x88 -#define PI3HDX1204_EQ_DB1390 0x99 -#define PI3HDX1204_EQ_DB1530 0xAA -#define PI3HDX1204_EQ_DB1690 0xBB -#define PI3HDX1204_EQ_DB1790 0xCC -#define PI3HDX1204_EQ_DB1920 0xDD -#define PI3HDX1204_EQ_DB2050 0xEE -#define PI3HDX1204_EQ_DB2220 0xFF +#define PI3HDX1204_EQ_DB25 0x00 +#define PI3HDX1204_EQ_DB80 0x11 +#define PI3HDX1204_EQ_DB110 0x22 +#define PI3HDX1204_EQ_DB220 0x33 +#define PI3HDX1204_EQ_DB410 0x44 +#define PI3HDX1204_EQ_DB710 0x55 +#define PI3HDX1204_EQ_DB900 0x66 +#define PI3HDX1204_EQ_DB1030 0x77 +#define PI3HDX1204_EQ_DB1180 0x88 +#define PI3HDX1204_EQ_DB1390 0x99 +#define PI3HDX1204_EQ_DB1530 0xAA +#define PI3HDX1204_EQ_DB1690 0xBB +#define PI3HDX1204_EQ_DB1790 0xCC +#define PI3HDX1204_EQ_DB1920 0xDD +#define PI3HDX1204_EQ_DB2050 0xEE +#define PI3HDX1204_EQ_DB2220 0xFF /* Register Offset 5 - Output Voltage Swing Setting */ -#define PI3HDX1204_VOD_OFFSET 5 -#define PI3HDX1204_VOD_80_ALL_CHANNELS 0x00 -#define PI3HDX1204_VOD_95_ALL_CHANNELS 0x55 -#define PI3HDX1204_VOD_115_ALL_CHANNELS 0xAA -#define PI3HDX1204_VOD_130_ALL_CHANNELS 0xFF +#define PI3HDX1204_VOD_OFFSET 5 +#define PI3HDX1204_VOD_80_ALL_CHANNELS 0x00 +#define PI3HDX1204_VOD_95_ALL_CHANNELS 0x55 +#define PI3HDX1204_VOD_115_ALL_CHANNELS 0xAA +#define PI3HDX1204_VOD_130_ALL_CHANNELS 0xFF /* Register Offset 6 - Output De-emphasis Setting */ -#define PI3HDX1204_DE_OFFSET 6 -#define PI3HDX1204_DE_DB_0 0x00 -#define PI3HDX1204_DE_DB_MINUS5 0x55 -#define PI3HDX1204_DE_DB_MINUS7 0xAA -#define PI3HDX1204_DE_DB_MINUS10 0xFF +#define PI3HDX1204_DE_OFFSET 6 +#define PI3HDX1204_DE_DB_0 0x00 +#define PI3HDX1204_DE_DB_MINUS5 0x55 +#define PI3HDX1204_DE_DB_MINUS7 0xAA +#define PI3HDX1204_DE_DB_MINUS10 0xFF /* Delay for I2C to be ready after power on. */ #define PI3HDX1204_POWER_ON_DELAY_MS 13 /* Enable or disable the PI3HDX1204. */ -int pi3hdx1204_enable(const int i2c_port, - const uint16_t i2c_addr_flags, +int pi3hdx1204_enable(const int i2c_port, const uint16_t i2c_addr_flags, const int enable); struct pi3hdx1204_tuning { diff --git a/driver/retimer/ps8802.c b/driver/retimer/ps8802.c index 9738123ace..e2d93a25b4 100644 --- a/driver/retimer/ps8802.c +++ b/driver/retimer/ps8802.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -16,22 +16,19 @@ #define PS8802_DEBUG 0 #define PS8802_I2C_WAKE_DELAY 500 -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data) { int rv; - rv = i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8802_DEBUG) ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, *data); + me->i2c_port, me->i2c_addr_flags + page, offset, + *data); return rv; } @@ -42,58 +39,43 @@ int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data) int pre_val, post_val; if (PS8802_DEBUG) - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_write8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8802_DEBUG) { - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) " - "0x%02X=>0x%02X\n", - __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, data, - pre_val, post_val); + "0x%02X=>0x%02X\n", + __func__, me->i2c_port, me->i2c_addr_flags + page, + offset, data, pre_val, post_val); } return rv; } -int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset, - int data) +int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset, int data) { int rv; int pre_val, post_val; if (PS8802_DEBUG) - i2c_read16(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_write16(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_write16(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8802_DEBUG) { - i2c_read16(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%04X) " "0x%04X=>0x%04X\n", - __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, data, - pre_val, post_val); + __func__, me->i2c_port, me->i2c_addr_flags + page, + offset, data, pre_val, post_val); } return rv; @@ -106,62 +88,46 @@ int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset, int pre_val, post_val; if (PS8802_DEBUG) - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_field_update8(me->i2c_port, - me->i2c_addr_flags + page, - offset, - field_mask, - set_value); + rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset, + field_mask, set_value); if (PS8802_DEBUG) { - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) " "0x%02X=>0x%02X\n", - __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, field_mask, set_value, - pre_val, post_val); + __func__, me->i2c_port, me->i2c_addr_flags + page, + offset, field_mask, set_value, pre_val, post_val); } return rv; } int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset, - uint16_t field_mask, uint16_t set_value) + uint16_t field_mask, uint16_t set_value) { int rv; int pre_val, post_val; if (PS8802_DEBUG) - i2c_read16(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_field_update16(me->i2c_port, - me->i2c_addr_flags + page, - offset, - field_mask, - set_value); + rv = i2c_field_update16(me->i2c_port, me->i2c_addr_flags + page, offset, + field_mask, set_value); if (PS8802_DEBUG) { - i2c_read16(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%04X) " "0x%04X=>0x%04X\n", - __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, field_mask, set_value, - pre_val, post_val); + __func__, me->i2c_port, me->i2c_addr_flags + page, + offset, field_mask, set_value, pre_val, post_val); } return rv; @@ -179,9 +145,7 @@ int ps8802_i2c_wake(const struct usb_mux *me) /* If in standby, first read will fail, second should succeed. */ for (int i = 0; i < 2; i++) { - rv = ps8802_i2c_read(me, - PS8802_REG_PAGE2, - PS8802_REG2_MODE, + rv = ps8802_i2c_read(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, &data); if (rv == EC_SUCCESS) return rv; @@ -200,7 +164,7 @@ static int ps8802_enter_low_power_mode(const struct usb_mux *me) int rv; rv = ps8802_i2c_write(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, - PS8802_MODE_STANDBY_MODE); + PS8802_MODE_STANDBY_MODE); if (rv) CPRINTS("C%d: PS8802: Failed to enter low power mode!", @@ -224,9 +188,13 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; + /* This driver treats safe mode as none */ + if (mux_state == USB_PD_MUX_SAFE_MODE) + mux_state = USB_PD_MUX_NONE; + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) - return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS - : EC_ERROR_NOT_POWERED; + return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS : + EC_ERROR_NOT_POWERED; /* Make sure the PS8802 is awake */ rv = ps8802_i2c_wake(me); @@ -234,18 +202,16 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state, return rv; if (PS8802_DEBUG) - ccprintf("%s(%d, 0x%02X) %s %s %s\n", - __func__, me->usb_port, mux_state, - (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "", - (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "", - (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? "FLIP" : ""); + ccprintf("%s(%d, 0x%02X) %s %s %s\n", __func__, me->usb_port, + mux_state, + (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "", + (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "", + (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? "FLIP" : + ""); /* Set the mode and flip */ - val = (PS8802_MODE_DP_REG_CONTROL | - PS8802_MODE_USB_REG_CONTROL | - PS8802_MODE_FLIP_REG_CONTROL | - PS8802_MODE_IN_HPD_REG_CONTROL); + val = (PS8802_MODE_DP_REG_CONTROL | PS8802_MODE_USB_REG_CONTROL | + PS8802_MODE_FLIP_REG_CONTROL | PS8802_MODE_IN_HPD_REG_CONTROL); if (mux_state & USB_PD_MUX_USB_ENABLED) val |= PS8802_MODE_USB_ENABLE; @@ -254,10 +220,7 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_POLARITY_INVERTED) val |= PS8802_MODE_FLIP_ENABLE; - rv = ps8802_i2c_write(me, - PS8802_REG_PAGE2, - PS8802_REG2_MODE, - val); + rv = ps8802_i2c_write(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, val); return rv; } @@ -276,10 +239,7 @@ static int ps8802_get_mux(const struct usb_mux *me, mux_state_t *mux_state) if (rv) return rv; - rv = ps8802_i2c_read(me, - PS8802_REG_PAGE2, - PS8802_REG2_MODE, - &val); + rv = ps8802_i2c_read(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, &val); if (rv) return rv; @@ -309,8 +269,7 @@ int ps8802_chg_i2c_addr(int i2c_port) { int rv; - rv = i2c_write8(i2c_port, - PS8802_P1_ADDR, PS8802_ADDR_CFG, + rv = i2c_write8(i2c_port, PS8802_P1_ADDR, PS8802_ADDR_CFG, PS8802_I2C_ADDR_FLAGS_ALT); return rv; diff --git a/driver/retimer/ps8802.h b/driver/retimer/ps8802.h index 5f4b9e4e9c..b8a51de62d 100644 --- a/driver/retimer/ps8802.h +++ b/driver/retimer/ps8802.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -13,70 +13,70 @@ * PS8802 uses 7-bit I2C addresses 0x08 to 0x17 (ADDR=L). * Page 0 = 0x08, Page 1 = 0x09, Page 2 = 0x0A. */ -#define PS8802_I2C_ADDR_FLAGS 0x08 +#define PS8802_I2C_ADDR_FLAGS 0x08 /* * PS8802 uses 7-bit I2C addresses 0x28 to 0x37. * Page 0 = 0x028, Page 1 = 0x29, Page 2 = 0x2A. */ -#define PS8802_I2C_ADDR_FLAGS_CUSTOM 0x28 +#define PS8802_I2C_ADDR_FLAGS_CUSTOM 0x28 /* * PAGE 0 Register Definitions */ -#define PS8802_REG_PAGE0 0x00 +#define PS8802_REG_PAGE0 0x00 -#define PS8802_REG0_TX_STATUS 0x72 -#define PS8802_REG0_RX_STATUS 0x76 -#define PS8802_STATUS_NORMAL_OPERATION BIT(7) -#define PS8802_STATUS_10_GBPS BIT(5) +#define PS8802_REG0_TX_STATUS 0x72 +#define PS8802_REG0_RX_STATUS 0x76 +#define PS8802_STATUS_NORMAL_OPERATION BIT(7) +#define PS8802_STATUS_10_GBPS BIT(5) /* * PAGE 1 Register Definitions */ -#define PS8802_REG_PAGE1 0x01 - -#define PS8802_800MV_LEVEL_TUNING 0x8A -#define PS8802_EXTRA_SWING_LEVEL_P0_DEFAULT 0X00 -#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_1 0X01 -#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_2 0X02 -#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_3 0X03 -#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_4 0X04 -#define PS8802_EXTRA_SWING_LEVEL_P0_UP_1 0X05 -#define PS8802_EXTRA_SWING_LEVEL_P0_UP_2 0X06 -#define PS8802_EXTRA_SWING_LEVEL_P0_UP_3 0X07 -#define PS8802_EXTRA_SWING_LEVEL_P0_MASK 0X07 - -#define PS8802_REG_DCIRX 0x4B -#define PS8802_AUTO_DCI_MODE_DISABLE BIT(7) -#define PS8802_FORCE_DCI_MODE BIT(6) +#define PS8802_REG_PAGE1 0x01 + +#define PS8802_800MV_LEVEL_TUNING 0x8A +#define PS8802_EXTRA_SWING_LEVEL_P0_DEFAULT 0X00 +#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_1 0X01 +#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_2 0X02 +#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_3 0X03 +#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_4 0X04 +#define PS8802_EXTRA_SWING_LEVEL_P0_UP_1 0X05 +#define PS8802_EXTRA_SWING_LEVEL_P0_UP_2 0X06 +#define PS8802_EXTRA_SWING_LEVEL_P0_UP_3 0X07 +#define PS8802_EXTRA_SWING_LEVEL_P0_MASK 0X07 + +#define PS8802_REG_DCIRX 0x4B +#define PS8802_AUTO_DCI_MODE_DISABLE BIT(7) +#define PS8802_FORCE_DCI_MODE BIT(6) /* * PAGE 2 Register Definitions */ -#define PS8802_REG_PAGE2 0x02 - -#define PS8802_REG2_USB_SSEQ_LEVEL 0x02 -#define PS8802_REG2_USB_CEQ_LEVEL 0x04 -#define PS8802_USBEQ_LEVEL_UP_12DB (0x0000 | 0x0003) -#define PS8802_USBEQ_LEVEL_UP_13DB (0x0400 | 0x0007) -#define PS8802_USBEQ_LEVEL_UP_16DB (0x0C00 | 0x000F) -#define PS8802_USBEQ_LEVEL_UP_17DB (0x1C00 | 0x001F) -#define PS8802_USBEQ_LEVEL_UP_18DB (0x3C00 | 0x003F) -#define PS8802_USBEQ_LEVEL_UP_19DB (0x7C00 | 0x007F) -#define PS8802_USBEQ_LEVEL_UP_20DB (0xFC00 | 0x00FF) -#define PS8802_USBEQ_LEVEL_UP_23DB (0xFD00 | 0x01FF) -#define PS8802_USBEQ_LEVEL_UP_MASK 0xFDFF - -#define PS8802_REG2_MODE 0x06 -#define PS8802_MODE_DP_REG_CONTROL BIT(7) -#define PS8802_MODE_DP_ENABLE BIT(6) -#define PS8802_MODE_USB_REG_CONTROL BIT(5) -#define PS8802_MODE_USB_ENABLE BIT(4) -#define PS8802_MODE_FLIP_REG_CONTROL BIT(3) -#define PS8802_MODE_FLIP_ENABLE BIT(2) -#define PS8802_MODE_IN_HPD_REG_CONTROL BIT(1) -#define PS8802_MODE_IN_HPD_ENABLE BIT(0) +#define PS8802_REG_PAGE2 0x02 + +#define PS8802_REG2_USB_SSEQ_LEVEL 0x02 +#define PS8802_REG2_USB_CEQ_LEVEL 0x04 +#define PS8802_USBEQ_LEVEL_UP_12DB (0x0000 | 0x0003) +#define PS8802_USBEQ_LEVEL_UP_13DB (0x0400 | 0x0007) +#define PS8802_USBEQ_LEVEL_UP_16DB (0x0C00 | 0x000F) +#define PS8802_USBEQ_LEVEL_UP_17DB (0x1C00 | 0x001F) +#define PS8802_USBEQ_LEVEL_UP_18DB (0x3C00 | 0x003F) +#define PS8802_USBEQ_LEVEL_UP_19DB (0x7C00 | 0x007F) +#define PS8802_USBEQ_LEVEL_UP_20DB (0xFC00 | 0x00FF) +#define PS8802_USBEQ_LEVEL_UP_23DB (0xFD00 | 0x01FF) +#define PS8802_USBEQ_LEVEL_UP_MASK 0xFDFF + +#define PS8802_REG2_MODE 0x06 +#define PS8802_MODE_DP_REG_CONTROL BIT(7) +#define PS8802_MODE_DP_ENABLE BIT(6) +#define PS8802_MODE_USB_REG_CONTROL BIT(5) +#define PS8802_MODE_USB_ENABLE BIT(4) +#define PS8802_MODE_FLIP_REG_CONTROL BIT(3) +#define PS8802_MODE_FLIP_ENABLE BIT(2) +#define PS8802_MODE_IN_HPD_REG_CONTROL BIT(1) +#define PS8802_MODE_IN_HPD_ENABLE BIT(0) /* * Support power saving mode, Bit7 Disable @@ -84,23 +84,23 @@ * FLIP pin, Bit1 Display IN_HPD pin, [Bit6 Bit4] * 00: I2C standy by mode. */ -#define PS8802_MODE_STANDBY_MODE 0xAA - -#define PS8802_REG2_DPEQ_LEVEL 0x07 -#define PS8802_DPEQ_LEVEL_UP_9DB 0x00 -#define PS8802_DPEQ_LEVEL_UP_11DB 0x01 -#define PS8802_DPEQ_LEVEL_UP_12DB 0x02 -#define PS8802_DPEQ_LEVEL_UP_14DB 0x03 -#define PS8802_DPEQ_LEVEL_UP_17DB 0x04 -#define PS8802_DPEQ_LEVEL_UP_18DB 0x05 -#define PS8802_DPEQ_LEVEL_UP_19DB 0x06 -#define PS8802_DPEQ_LEVEL_UP_20DB 0x07 -#define PS8802_DPEQ_LEVEL_UP_21DB 0x08 -#define PS8802_DPEQ_LEVEL_UP_MASK 0x0F - -#define PS8802_P1_ADDR 0x0A -#define PS8802_ADDR_CFG 0xB0 -#define PS8802_I2C_ADDR_FLAGS_ALT 0x50 +#define PS8802_MODE_STANDBY_MODE 0xAA + +#define PS8802_REG2_DPEQ_LEVEL 0x07 +#define PS8802_DPEQ_LEVEL_UP_9DB 0x00 +#define PS8802_DPEQ_LEVEL_UP_11DB 0x01 +#define PS8802_DPEQ_LEVEL_UP_12DB 0x02 +#define PS8802_DPEQ_LEVEL_UP_14DB 0x03 +#define PS8802_DPEQ_LEVEL_UP_17DB 0x04 +#define PS8802_DPEQ_LEVEL_UP_18DB 0x05 +#define PS8802_DPEQ_LEVEL_UP_19DB 0x06 +#define PS8802_DPEQ_LEVEL_UP_20DB 0x07 +#define PS8802_DPEQ_LEVEL_UP_21DB 0x08 +#define PS8802_DPEQ_LEVEL_UP_MASK 0x0F + +#define PS8802_P1_ADDR 0x0A +#define PS8802_ADDR_CFG 0xB0 +#define PS8802_I2C_ADDR_FLAGS_ALT 0x50 extern const struct usb_mux_driver ps8802_usb_mux_driver; @@ -108,11 +108,11 @@ int ps8802_i2c_wake(const struct usb_mux *me); int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data); int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data); int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset, - int data); + int data); int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset, uint8_t field_mask, uint8_t set_value); int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset, - uint16_t field_mask, uint16_t set_value); + uint16_t field_mask, uint16_t set_value); int ps8802_chg_i2c_addr(int i2c_port); #endif /* __CROS_EC_USB_RETIMER_PS8802_H */ diff --git a/driver/retimer/ps8811.c b/driver/retimer/ps8811.c index 6a66248d38..aadcbc9f6c 100644 --- a/driver/retimer/ps8811.c +++ b/driver/retimer/ps8811.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -15,9 +15,7 @@ int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data) { int rv; - rv = i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data); return rv; } @@ -26,23 +24,18 @@ int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data) { int rv; - rv = i2c_write8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data); return rv; } int ps8811_i2c_field_update(const struct usb_mux *me, int page, int offset, - uint8_t field_mask, uint8_t set_value) + uint8_t field_mask, uint8_t set_value) { int rv; - rv = i2c_field_update8(me->i2c_port, - me->i2c_addr_flags + page, - offset, - field_mask, - set_value); + rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset, + field_mask, set_value); return rv; } diff --git a/driver/retimer/ps8811.h b/driver/retimer/ps8811.h index 5721f31eae..b834635215 100644 --- a/driver/retimer/ps8811.h +++ b/driver/retimer/ps8811.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -20,172 +20,172 @@ * PS8811 uses 7-bit I2C addresses 0x72 to 0x73 (ADDR=HH). * Page 0 = 0x72, Page 1 = 0x73. */ -#define PS8811_I2C_ADDR_FLAGS0 0x28 -#define PS8811_I2C_ADDR_FLAGS1 0x2A -#define PS8811_I2C_ADDR_FLAGS2 0x70 -#define PS8811_I2C_ADDR_FLAGS3 0x72 +#define PS8811_I2C_ADDR_FLAGS0 0x28 +#define PS8811_I2C_ADDR_FLAGS1 0x2A +#define PS8811_I2C_ADDR_FLAGS2 0x70 +#define PS8811_I2C_ADDR_FLAGS3 0x72 /* * PAGE 1 Register Definitions */ -#define PS8811_REG_PAGE1 0x01 - -#define PS8811_REG1_USB_AEQ_LEVEL 0x01 -#define PS8811_AEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0) -#define PS8811_AEQ_PIN_LEVEL_UP_SHIFT 0 -#define PS8811_AEQ_PIN_LEVEL_UP_9DB 0x00 -#define PS8811_AEQ_PIN_LEVEL_UP_10P5DB 0x01 -#define PS8811_AEQ_PIN_LEVEL_UP_12DB 0x02 -#define PS8811_AEQ_PIN_LEVEL_UP_13DB 0x03 -#define PS8811_AEQ_PIN_LEVEL_UP_16DB 0x04 -#define PS8811_AEQ_PIN_LEVEL_UP_17DB 0x05 -#define PS8811_AEQ_PIN_LEVEL_UP_18DB 0x06 -#define PS8811_AEQ_PIN_LEVEL_UP_19DB 0x07 -#define PS8811_AEQ_PIN_LEVEL_UP_20DB 0x08 -#define PS8811_AEQ_PIN_LEVEL_UP_21DB 0x09 -#define PS8811_AEQ_PIN_LEVEL_UP_23DB 0x0A -#define PS8811_AEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4) -#define PS8811_AEQ_I2C_LEVEL_UP_SHIFT 4 -#define PS8811_AEQ_I2C_LEVEL_UP_9DB 0x00 -#define PS8811_AEQ_I2C_LEVEL_UP_10P5DB 0x01 -#define PS8811_AEQ_I2C_LEVEL_UP_12DB 0x02 -#define PS8811_AEQ_I2C_LEVEL_UP_13DB 0x03 -#define PS8811_AEQ_I2C_LEVEL_UP_16DB 0x04 -#define PS8811_AEQ_I2C_LEVEL_UP_17DB 0x05 -#define PS8811_AEQ_I2C_LEVEL_UP_18DB 0x06 -#define PS8811_AEQ_I2C_LEVEL_UP_19DB 0x07 -#define PS8811_AEQ_I2C_LEVEL_UP_20DB 0x08 -#define PS8811_AEQ_I2C_LEVEL_UP_21DB 0x09 -#define PS8811_AEQ_I2C_LEVEL_UP_23DB 0x0A - -#define PS8811_REG1_USB_ADE_CONFIG 0x02 -#define PS8811_AEQ_CONFIG_REG_ENABLE BIT(0) -#define PS8811_AEQ_ADAPTIVE_REG_ENABLE BIT(1) -#define PS8811_ADE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5) -#define PS8811_ADE_PIN_MID_LEVEL_SHIFT 5 -#define PS8811_ADE_PIN_MID_LEVEL_0P5DB 0x00 -#define PS8811_ADE_PIN_MID_LEVEL_1P5DB 0x01 -#define PS8811_ADE_PIN_MID_LEVEL_2DB 0x02 -#define PS8811_ADE_PIN_MID_LEVEL_3DB 0x03 -#define PS8811_ADE_PIN_MID_LEVEL_3P5DB 0x04 -#define PS8811_ADE_PIN_MID_LEVEL_4P5DB 0x05 -#define PS8811_ADE_PIN_MID_LEVEL_6DB 0x06 -#define PS8811_ADE_PIN_MID_LEVEL_7P5DB 0x07 -#define PS8811_ADE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2) -#define PS8811_ADE_PIN_LOW_LEVEL_SHIFT 2 -#define PS8811_ADE_PIN_LOW_LEVEL_0P5DB 0x00 -#define PS8811_ADE_PIN_LOW_LEVEL_1P5DB 0x01 -#define PS8811_ADE_PIN_LOW_LEVEL_2DB 0x02 -#define PS8811_ADE_PIN_LOW_LEVEL_3DB 0x03 -#define PS8811_ADE_PIN_LOW_LEVEL_3P5DB 0x04 -#define PS8811_ADE_PIN_LOW_LEVEL_4P5DB 0x05 -#define PS8811_ADE_PIN_LOW_LEVEL_6DB 0x06 -#define PS8811_ADE_PIN_LOW_LEVEL_7P5DB 0x07 - -#define PS8811_REG1_USB_BEQ_LEVEL 0x05 -#define PS8811_BEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0) -#define PS8811_BEQ_PIN_LEVEL_UP_SHIFT 0 -#define PS8811_BEQ_PIN_LEVEL_UP_9DB 0x00 -#define PS8811_BEQ_PIN_LEVEL_UP_10P5DB 0x01 -#define PS8811_BEQ_PIN_LEVEL_UP_12DB 0x02 -#define PS8811_BEQ_PIN_LEVEL_UP_13DB 0x03 -#define PS8811_BEQ_PIN_LEVEL_UP_16DB 0x04 -#define PS8811_BEQ_PIN_LEVEL_UP_17DB 0x05 -#define PS8811_BEQ_PIN_LEVEL_UP_18DB 0x06 -#define PS8811_BEQ_PIN_LEVEL_UP_19DB 0x07 -#define PS8811_BEQ_PIN_LEVEL_UP_20DB 0x08 -#define PS8811_BEQ_PIN_LEVEL_UP_21DB 0x09 -#define PS8811_BEQ_PIN_LEVEL_UP_23DB 0x0A -#define PS8811_BEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4) -#define PS8811_BEQ_I2C_LEVEL_UP_SHIFT 4 -#define PS8811_BEQ_I2C_LEVEL_UP_9DB 0x00 -#define PS8811_BEQ_I2C_LEVEL_UP_10P5DB 0x01 -#define PS8811_BEQ_I2C_LEVEL_UP_12DB 0x02 -#define PS8811_BEQ_I2C_LEVEL_UP_13DB 0x03 -#define PS8811_BEQ_I2C_LEVEL_UP_16DB 0x04 -#define PS8811_BEQ_I2C_LEVEL_UP_17DB 0x05 -#define PS8811_BEQ_I2C_LEVEL_UP_18DB 0x06 -#define PS8811_BEQ_I2C_LEVEL_UP_19DB 0x07 -#define PS8811_BEQ_I2C_LEVEL_UP_20DB 0x08 -#define PS8811_BEQ_I2C_LEVEL_UP_21DB 0x09 -#define PS8811_BEQ_I2C_LEVEL_UP_23DB 0x0A - -#define PS8811_REG1_USB_BDE_CONFIG 0x06 -#define PS8811_BEQ_CONFIG_REG_ENABLE BIT(0) -#define PS8811_BEQ_ADAPTIVE_REG_ENABLE BIT(1) -#define PS8811_BDE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5) -#define PS8811_BDE_PIN_MID_LEVEL_SHIFT 5 -#define PS8811_BDE_PIN_MID_LEVEL_0P5DB 0x00 -#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01 -#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02 -#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03 -#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04 -#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05 -#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06 -#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07 -#define PS8811_BDE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2) -#define PS8811_BDE_PIN_LOW_LEVEL_SHIFT 2 -#define PS8811_BDE_PIN_LOW_LEVEL_0P5DB 0x00 -#define PS8811_BDE_PIN_LOW_LEVEL_1P5DB 0x01 -#define PS8811_BDE_PIN_LOW_LEVEL_2DB 0x02 -#define PS8811_BDE_PIN_LOW_LEVEL_3DB 0x03 -#define PS8811_BDE_PIN_LOW_LEVEL_3P5DB 0x04 -#define PS8811_BDE_PIN_LOW_LEVEL_4P5DB 0x05 -#define PS8811_BDE_PIN_LOW_LEVEL_6DB 0x06 -#define PS8811_BDE_PIN_LOW_LEVEL_7P5DB 0x07 - -#define PS8811_REG1_USB_CHAN_A_SWING 0x66 -#define PS8811_CHAN_A_SWING_MASK GENMASK(6, 4) -#define PS8811_CHAN_A_SWING_SHIFT 4 - -#define PS8811_REG1_50OHM_ADJUST_CHAN_B 0x73 -#define PS8811_50OHM_ADJUST_CHAN_B_CONFIG_MASK GENMASK(3, 1) -#define PS8811_50OHM_ADJUST_CHAN_B_SHIFT 1 -#define PS8811_50OHM_ADJUST_CHAN_B_DEFAULT 0x00 -#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_6PCT 0x01 -#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT 0x02 -#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_14PCT 0x03 -#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_7PCT 0x04 -#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_11PCT 0x05 -#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_20PCT 0x06 - -#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01 -#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02 -#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03 -#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04 -#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05 -#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06 -#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07 - -#define PS8811_REG1_USB_CHAN_B_SWING 0xA4 -#define PS8811_CHAN_B_SWING_MASK GENMASK(2, 0) -#define PS8811_CHAN_B_SWING_SHIFT 0 +#define PS8811_REG_PAGE1 0x01 + +#define PS8811_REG1_USB_AEQ_LEVEL 0x01 +#define PS8811_AEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0) +#define PS8811_AEQ_PIN_LEVEL_UP_SHIFT 0 +#define PS8811_AEQ_PIN_LEVEL_UP_9DB 0x00 +#define PS8811_AEQ_PIN_LEVEL_UP_10P5DB 0x01 +#define PS8811_AEQ_PIN_LEVEL_UP_12DB 0x02 +#define PS8811_AEQ_PIN_LEVEL_UP_13DB 0x03 +#define PS8811_AEQ_PIN_LEVEL_UP_16DB 0x04 +#define PS8811_AEQ_PIN_LEVEL_UP_17DB 0x05 +#define PS8811_AEQ_PIN_LEVEL_UP_18DB 0x06 +#define PS8811_AEQ_PIN_LEVEL_UP_19DB 0x07 +#define PS8811_AEQ_PIN_LEVEL_UP_20DB 0x08 +#define PS8811_AEQ_PIN_LEVEL_UP_21DB 0x09 +#define PS8811_AEQ_PIN_LEVEL_UP_23DB 0x0A +#define PS8811_AEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4) +#define PS8811_AEQ_I2C_LEVEL_UP_SHIFT 4 +#define PS8811_AEQ_I2C_LEVEL_UP_9DB 0x00 +#define PS8811_AEQ_I2C_LEVEL_UP_10P5DB 0x01 +#define PS8811_AEQ_I2C_LEVEL_UP_12DB 0x02 +#define PS8811_AEQ_I2C_LEVEL_UP_13DB 0x03 +#define PS8811_AEQ_I2C_LEVEL_UP_16DB 0x04 +#define PS8811_AEQ_I2C_LEVEL_UP_17DB 0x05 +#define PS8811_AEQ_I2C_LEVEL_UP_18DB 0x06 +#define PS8811_AEQ_I2C_LEVEL_UP_19DB 0x07 +#define PS8811_AEQ_I2C_LEVEL_UP_20DB 0x08 +#define PS8811_AEQ_I2C_LEVEL_UP_21DB 0x09 +#define PS8811_AEQ_I2C_LEVEL_UP_23DB 0x0A + +#define PS8811_REG1_USB_ADE_CONFIG 0x02 +#define PS8811_AEQ_CONFIG_REG_ENABLE BIT(0) +#define PS8811_AEQ_ADAPTIVE_REG_ENABLE BIT(1) +#define PS8811_ADE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5) +#define PS8811_ADE_PIN_MID_LEVEL_SHIFT 5 +#define PS8811_ADE_PIN_MID_LEVEL_0P5DB 0x00 +#define PS8811_ADE_PIN_MID_LEVEL_1P5DB 0x01 +#define PS8811_ADE_PIN_MID_LEVEL_2DB 0x02 +#define PS8811_ADE_PIN_MID_LEVEL_3DB 0x03 +#define PS8811_ADE_PIN_MID_LEVEL_3P5DB 0x04 +#define PS8811_ADE_PIN_MID_LEVEL_4P5DB 0x05 +#define PS8811_ADE_PIN_MID_LEVEL_6DB 0x06 +#define PS8811_ADE_PIN_MID_LEVEL_7P5DB 0x07 +#define PS8811_ADE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2) +#define PS8811_ADE_PIN_LOW_LEVEL_SHIFT 2 +#define PS8811_ADE_PIN_LOW_LEVEL_0P5DB 0x00 +#define PS8811_ADE_PIN_LOW_LEVEL_1P5DB 0x01 +#define PS8811_ADE_PIN_LOW_LEVEL_2DB 0x02 +#define PS8811_ADE_PIN_LOW_LEVEL_3DB 0x03 +#define PS8811_ADE_PIN_LOW_LEVEL_3P5DB 0x04 +#define PS8811_ADE_PIN_LOW_LEVEL_4P5DB 0x05 +#define PS8811_ADE_PIN_LOW_LEVEL_6DB 0x06 +#define PS8811_ADE_PIN_LOW_LEVEL_7P5DB 0x07 + +#define PS8811_REG1_USB_BEQ_LEVEL 0x05 +#define PS8811_BEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0) +#define PS8811_BEQ_PIN_LEVEL_UP_SHIFT 0 +#define PS8811_BEQ_PIN_LEVEL_UP_9DB 0x00 +#define PS8811_BEQ_PIN_LEVEL_UP_10P5DB 0x01 +#define PS8811_BEQ_PIN_LEVEL_UP_12DB 0x02 +#define PS8811_BEQ_PIN_LEVEL_UP_13DB 0x03 +#define PS8811_BEQ_PIN_LEVEL_UP_16DB 0x04 +#define PS8811_BEQ_PIN_LEVEL_UP_17DB 0x05 +#define PS8811_BEQ_PIN_LEVEL_UP_18DB 0x06 +#define PS8811_BEQ_PIN_LEVEL_UP_19DB 0x07 +#define PS8811_BEQ_PIN_LEVEL_UP_20DB 0x08 +#define PS8811_BEQ_PIN_LEVEL_UP_21DB 0x09 +#define PS8811_BEQ_PIN_LEVEL_UP_23DB 0x0A +#define PS8811_BEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4) +#define PS8811_BEQ_I2C_LEVEL_UP_SHIFT 4 +#define PS8811_BEQ_I2C_LEVEL_UP_9DB 0x00 +#define PS8811_BEQ_I2C_LEVEL_UP_10P5DB 0x01 +#define PS8811_BEQ_I2C_LEVEL_UP_12DB 0x02 +#define PS8811_BEQ_I2C_LEVEL_UP_13DB 0x03 +#define PS8811_BEQ_I2C_LEVEL_UP_16DB 0x04 +#define PS8811_BEQ_I2C_LEVEL_UP_17DB 0x05 +#define PS8811_BEQ_I2C_LEVEL_UP_18DB 0x06 +#define PS8811_BEQ_I2C_LEVEL_UP_19DB 0x07 +#define PS8811_BEQ_I2C_LEVEL_UP_20DB 0x08 +#define PS8811_BEQ_I2C_LEVEL_UP_21DB 0x09 +#define PS8811_BEQ_I2C_LEVEL_UP_23DB 0x0A + +#define PS8811_REG1_USB_BDE_CONFIG 0x06 +#define PS8811_BEQ_CONFIG_REG_ENABLE BIT(0) +#define PS8811_BEQ_ADAPTIVE_REG_ENABLE BIT(1) +#define PS8811_BDE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5) +#define PS8811_BDE_PIN_MID_LEVEL_SHIFT 5 +#define PS8811_BDE_PIN_MID_LEVEL_0P5DB 0x00 +#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01 +#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02 +#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03 +#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04 +#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05 +#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06 +#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07 +#define PS8811_BDE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2) +#define PS8811_BDE_PIN_LOW_LEVEL_SHIFT 2 +#define PS8811_BDE_PIN_LOW_LEVEL_0P5DB 0x00 +#define PS8811_BDE_PIN_LOW_LEVEL_1P5DB 0x01 +#define PS8811_BDE_PIN_LOW_LEVEL_2DB 0x02 +#define PS8811_BDE_PIN_LOW_LEVEL_3DB 0x03 +#define PS8811_BDE_PIN_LOW_LEVEL_3P5DB 0x04 +#define PS8811_BDE_PIN_LOW_LEVEL_4P5DB 0x05 +#define PS8811_BDE_PIN_LOW_LEVEL_6DB 0x06 +#define PS8811_BDE_PIN_LOW_LEVEL_7P5DB 0x07 + +#define PS8811_REG1_USB_CHAN_A_SWING 0x66 +#define PS8811_CHAN_A_SWING_MASK GENMASK(6, 4) +#define PS8811_CHAN_A_SWING_SHIFT 4 + +#define PS8811_REG1_50OHM_ADJUST_CHAN_B 0x73 +#define PS8811_50OHM_ADJUST_CHAN_B_CONFIG_MASK GENMASK(3, 1) +#define PS8811_50OHM_ADJUST_CHAN_B_SHIFT 1 +#define PS8811_50OHM_ADJUST_CHAN_B_DEFAULT 0x00 +#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_6PCT 0x01 +#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT 0x02 +#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_14PCT 0x03 +#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_7PCT 0x04 +#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_11PCT 0x05 +#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_20PCT 0x06 + +#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01 +#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02 +#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03 +#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04 +#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05 +#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06 +#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07 + +#define PS8811_REG1_USB_CHAN_B_SWING 0xA4 +#define PS8811_CHAN_B_SWING_MASK GENMASK(2, 0) +#define PS8811_CHAN_B_SWING_SHIFT 0 /* De-emphasis -2.2 dB, Pre-shoot 1.2 dB */ -#define PS8811_CHAN_B_DE_2_2_PS_1_2_LSB 0x1 -#define PS8811_CHAN_B_DE_2_2_PS_1_2_MSB 0x13 +#define PS8811_CHAN_B_DE_2_2_PS_1_2_LSB 0x1 +#define PS8811_CHAN_B_DE_2_2_PS_1_2_MSB 0x13 /* De-emphasis -3.5 dB, Pre-shoot 0 dB */ -#define PS8811_CHAN_B_DE_3_5_PS_0_LSB 0x0 -#define PS8811_CHAN_B_DE_3_5_PS_0_MSB 0x5 +#define PS8811_CHAN_B_DE_3_5_PS_0_LSB 0x0 +#define PS8811_CHAN_B_DE_3_5_PS_0_MSB 0x5 /* De-emphasis -4.5 dB, Pre-shoot 0 dB */ -#define PS8811_CHAN_B_DE_4_5_PS_0_LSB 0x0 -#define PS8811_CHAN_B_DE_4_5_PS_0_MSB 0x6 +#define PS8811_CHAN_B_DE_4_5_PS_0_LSB 0x0 +#define PS8811_CHAN_B_DE_4_5_PS_0_MSB 0x6 /* De-emphasis -6 dB, Pre-shoot 1.5 dB */ -#define PS8811_CHAN_B_DE_6_PS_1_5_LSB 0x2 -#define PS8811_CHAN_B_DE_6_PS_1_5_MSB 0x16 +#define PS8811_CHAN_B_DE_6_PS_1_5_LSB 0x2 +#define PS8811_CHAN_B_DE_6_PS_1_5_MSB 0x16 /* De-emphasis -6 dB, Pre-shoot 3 dB */ -#define PS8811_CHAN_B_DE_6_PS_3_LSB 0x4 -#define PS8811_CHAN_B_DE_6_PS_3_MSB 0x16 +#define PS8811_CHAN_B_DE_6_PS_3_LSB 0x4 +#define PS8811_CHAN_B_DE_6_PS_3_MSB 0x16 -#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB 0xA5 -#define PS8811_CHAN_B_DE_PS_LSB_MASK GENMASK(2, 0) +#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB 0xA5 +#define PS8811_CHAN_B_DE_PS_LSB_MASK GENMASK(2, 0) -#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB 0xA6 -#define PS8811_CHAN_B_DE_PS_MSB_MASK GENMASK(5, 0) +#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB 0xA6 +#define PS8811_CHAN_B_DE_PS_MSB_MASK GENMASK(5, 0) int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data); int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data); diff --git a/driver/retimer/ps8818.c b/driver/retimer/ps8818.c index 2f8e353099..dff1b33a64 100644 --- a/driver/retimer/ps8818.c +++ b/driver/retimer/ps8818.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -8,10 +8,10 @@ #include "chipset.h" #include "common.h" #include "console.h" +#include "driver/retimer/ps8818_public.h" #include "gpio.h" #include "i2c.h" #include "ioexpander.h" -#include "ps8818.h" #include "usb_mux.h" #define PS8818_DEBUG 0 @@ -20,15 +20,12 @@ int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data) { int rv; - rv = i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8818_DEBUG) ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__, - me->usb_port, - me->i2c_addr_flags + page, - offset, *data); + me->usb_port, me->i2c_addr_flags + page, offset, + *data); return rv; } @@ -39,26 +36,19 @@ int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data) int pre_val, post_val; if (PS8818_DEBUG) - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_write8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8818_DEBUG) { - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) " - "0x%02X=>0x%02X\n", - __func__, - me->usb_port, - me->i2c_addr_flags + page, - offset, data, - pre_val, post_val); + "0x%02X=>0x%02X\n", + __func__, me->usb_port, me->i2c_addr_flags + page, + offset, data, pre_val, post_val); } return rv; @@ -71,28 +61,20 @@ int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset, int pre_val, post_val; if (PS8818_DEBUG) - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_field_update8(me->i2c_port, - me->i2c_addr_flags + page, - offset, - field_mask, - set_value); + rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset, + field_mask, set_value); if (PS8818_DEBUG) { - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) " "0x%02X=>0x%02X\n", - __func__, - me->usb_port, - me->i2c_addr_flags + page, - offset, field_mask, set_value, - pre_val, post_val); + __func__, me->usb_port, me->i2c_addr_flags + page, + offset, field_mask, set_value, pre_val, post_val); } return rv; @@ -107,17 +89,21 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; + /* This driver treats safe mode as none */ + if (mux_state == USB_PD_MUX_SAFE_MODE) + mux_state = USB_PD_MUX_NONE; + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) - return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS - : EC_ERROR_NOT_POWERED; + return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS : + EC_ERROR_NOT_POWERED; if (PS8818_DEBUG) - ccprintf("%s(%d, 0x%02X) %s %s %s\n", - __func__, me->usb_port, mux_state, - (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "", - (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "", - (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? "FLIP" : ""); + ccprintf("%s(%d, 0x%02X) %s %s %s\n", __func__, me->usb_port, + mux_state, + (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "", + (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "", + (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? "FLIP" : + ""); /* Set the mode */ if (mux_state & USB_PD_MUX_USB_ENABLED) @@ -125,11 +111,8 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_DP_ENABLED) val |= PS8818_MODE_DP_ENABLE; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE0, - PS8818_REG0_MODE, - PS8818_MODE_NON_RESERVED_MASK, - val); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, PS8818_REG0_MODE, + PS8818_MODE_NON_RESERVED_MASK, val); if (rv) return rv; @@ -138,11 +121,8 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_POLARITY_INVERTED) val |= PS8818_FLIP_CONFIG; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE0, - PS8818_REG0_FLIP, - PS8818_FLIP_NON_RESERVED_MASK, - val); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, PS8818_REG0_FLIP, + PS8818_FLIP_NON_RESERVED_MASK, val); if (rv) return rv; @@ -151,11 +131,9 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_DP_ENABLED) val |= PS8818_DPHPD_PLUGGED; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE0, - PS8818_REG0_DPHPD_CONFIG, - PS8818_DPHPD_NON_RESERVED_MASK, - val); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, + PS8818_REG0_DPHPD_CONFIG, + PS8818_DPHPD_NON_RESERVED_MASK, val); return rv; } diff --git a/driver/retimer/ps8818.h b/driver/retimer/ps8818.h deleted file mode 100644 index b56df4b411..0000000000 --- a/driver/retimer/ps8818.h +++ /dev/null @@ -1,99 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * PS8818 retimer. - */ -#include "usb_mux.h" - -#ifndef __CROS_EC_USB_RETIMER_PS8818_H -#define __CROS_EC_USB_RETIMER_PS8818_H - -#define PS8818_I2C_ADDR_FLAGS 0x28 - -/* - * PAGE 0 Register Definitions - */ -#define PS8818_REG_PAGE0 0x00 - -#define PS8818_REG0_FLIP 0x00 -#define PS8818_FLIP_CONFIG BIT(7) -#define PS8818_FLIP_NON_RESERVED_MASK 0xE0 - -#define PS8818_REG0_MODE 0x01 -#define PS8818_MODE_DP_ENABLE BIT(7) -#define PS8818_MODE_USB_ENABLE BIT(6) -#define PS8818_MODE_NON_RESERVED_MASK 0xC0 - -#define PS8818_REG0_DPHPD_CONFIG 0x02 -#define PS8818_DPHPD_CONFIG_INHPD_DISABLE BIT(7) -#define PS8818_DPHPD_PLUGGED BIT(6) -#define PS8818_DPHPD_NON_RESERVED_MASK 0xFC - -/* - * PAGE 1 Register Definitions - */ -#define PS8818_REG_PAGE1 0x01 - -#define PS8818_REG1_APTX1EQ_10G_LEVEL 0x00 -#define PS8818_REG1_APTX2EQ_10G_LEVEL 0x02 -#define PS8818_REG1_CRX1EQ_10G_LEVEL 0x08 -#define PS8818_REG1_CRX2EQ_10G_LEVEL 0x0A -#define PS8818_REG1_APRX1_DE_LEVEL 0x0C -#define PS8818_REG1_APTX1EQ_5G_LEVEL 0x70 -#define PS8818_REG1_APTX2EQ_5G_LEVEL 0x72 -#define PS8818_REG1_CRX1EQ_5G_LEVEL 0x78 -#define PS8818_REG1_CRX2EQ_5G_LEVEL 0x7A -#define PS8818_EQ_LEVEL_UP_9DB (0) -#define PS8818_EQ_LEVEL_UP_10DB (1) -#define PS8818_EQ_LEVEL_UP_12DB (2) -#define PS8818_EQ_LEVEL_UP_13DB (3) -#define PS8818_EQ_LEVEL_UP_16DB (4) -#define PS8818_EQ_LEVEL_UP_17DB (5) -#define PS8818_EQ_LEVEL_UP_18DB (6) -#define PS8818_EQ_LEVEL_UP_19DB (7) -#define PS8818_EQ_LEVEL_UP_20DB (8) -#define PS8818_EQ_LEVEL_UP_21DB (9) -#define PS8818_EQ_LEVEL_UP_MASK (0x0F) - -#define PS8818_REG1_RX_PHY 0x6D -#define PS8818_RX_INPUT_TERM_112_OHM (0 << 6) -#define PS8818_RX_INPUT_TERM_104_OHM (1 << 6) -#define PS8818_RX_INPUT_TERM_96_OHM (2 << 6) -#define PS8818_RX_INPUT_TERM_85_OHM (3 << 6) -#define PS8818_RX_INPUT_TERM_MASK (3 << 6) - -#define PS8818_REG1_DPEQ_LEVEL 0xB6 -#define PS8818_DPEQ_LEVEL_UP_9DB (0 << 3) -#define PS8818_DPEQ_LEVEL_UP_10DB (1 << 3) -#define PS8818_DPEQ_LEVEL_UP_12DB (2 << 3) -#define PS8818_DPEQ_LEVEL_UP_13DB (3 << 3) -#define PS8818_DPEQ_LEVEL_UP_16DB (4 << 3) -#define PS8818_DPEQ_LEVEL_UP_17DB (5 << 3) -#define PS8818_DPEQ_LEVEL_UP_18DB (6 << 3) -#define PS8818_DPEQ_LEVEL_UP_19DB (7 << 3) -#define PS8818_DPEQ_LEVEL_UP_20DB (8 << 3) -#define PS8818_DPEQ_LEVEL_UP_21DB (9 << 3) -#define PS8818_DPEQ_LEVEL_UP_MASK (0x0F << 3) - -/* - * PAGE 2 Register Definitions - */ -#define PS8818_REG_PAGE2 0x02 - -#define PS8818_REG2_TX_STATUS 0x42 -#define PS8818_REG2_RX_STATUS 0x46 -#define PS8818_STATUS_NORMAL_OPERATION BIT(7) -#define PS8818_STATUS_10_GBPS BIT(5) - -extern const struct usb_mux_driver ps8818_usb_retimer_driver; - -int ps8818_i2c_read(const struct usb_mux *me, - int page, int offset, int *data); -int ps8818_i2c_write(const struct usb_mux *me, - int page, int offset, int data); -int ps8818_i2c_field_update8(const struct usb_mux *me, - int page, int offset, - uint8_t field_mask, uint8_t set_value); - -#endif /* __CROS_EC_USB_RETIMER_PS8818_H */ diff --git a/driver/retimer/tdp142.c b/driver/retimer/tdp142.c index e1632150d0..fb5149da63 100644 --- a/driver/retimer/tdp142.c +++ b/driver/retimer/tdp142.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,18 +12,12 @@ static enum ec_error_list tdp142_write(int offset, int data) { - return i2c_write8(TDP142_I2C_PORT, - TDP142_I2C_ADDR, - offset, data); - + return i2c_write8(TDP142_I2C_PORT, TDP142_I2C_ADDR, offset, data); } static enum ec_error_list tdp142_read(int offset, int *regval) { - return i2c_read8(TDP142_I2C_PORT, - TDP142_I2C_ADDR, - offset, regval); - + return i2c_read8(TDP142_I2C_PORT, TDP142_I2C_ADDR, offset, regval); } enum ec_error_list tdp142_set_ctlsel(enum tdp142_ctlsel selection) diff --git a/driver/retimer/tdp142.h b/driver/retimer/tdp142.h index 8346a233a5..abf0e3588c 100644 --- a/driver/retimer/tdp142.h +++ b/driver/retimer/tdp142.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -20,11 +20,11 @@ #define TDP142_I2C_ADDR3 0x0F /* Registers */ -#define TDP142_REG_GENERAL 0x0A -#define TDP142_GENERAL_CTLSEL GENMASK(1, 0) -#define TDP142_GENERAL_HPDIN_OVRRIDE BIT(3) -#define TDP142_GENERAL_EQ_OVERRIDE BIT(4) -#define TDP142_GENERAL_SWAP_HPDIN BIT(5) +#define TDP142_REG_GENERAL 0x0A +#define TDP142_GENERAL_CTLSEL GENMASK(1, 0) +#define TDP142_GENERAL_HPDIN_OVRRIDE BIT(3) +#define TDP142_GENERAL_EQ_OVERRIDE BIT(4) +#define TDP142_GENERAL_SWAP_HPDIN BIT(5) enum tdp142_ctlsel { TDP142_CTLSEL_SHUTDOWN, diff --git a/driver/retimer/tusb544.c b/driver/retimer/tusb544.c index 9de543fd42..c2d617c3be 100644 --- a/driver/retimer/tusb544.c +++ b/driver/retimer/tusb544.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,28 +10,21 @@ static int tusb544_write(const struct usb_mux *me, int offset, int data) { - return i2c_write8(me->i2c_port, - me->i2c_addr_flags, - offset, data); + return i2c_write8(me->i2c_port, me->i2c_addr_flags, offset, data); } static int tusb544_read(const struct usb_mux *me, int offset, int *data) { - return i2c_read8(me->i2c_port, - me->i2c_addr_flags, - offset, data); + return i2c_read8(me->i2c_port, me->i2c_addr_flags, offset, data); } int tusb544_i2c_field_update8(const struct usb_mux *me, int offset, - uint8_t field_mask, uint8_t set_value) + uint8_t field_mask, uint8_t set_value) { int rv; - rv = i2c_field_update8(me->i2c_port, - me->i2c_addr_flags, - offset, - field_mask, - set_value); + rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags, offset, + field_mask, set_value); return rv; } @@ -67,6 +60,10 @@ static int tusb544_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; + /* This driver treats safe mode as none */ + if (mux_state == USB_PD_MUX_SAFE_MODE) + mux_state = USB_PD_MUX_NONE; + if (mux_state == USB_PD_MUX_NONE) return tusb544_enter_low_power_mode(me); diff --git a/driver/retimer/tusb544.h b/driver/retimer/tusb544.h index e1599c78ca..9fe74c5299 100644 --- a/driver/retimer/tusb544.h +++ b/driver/retimer/tusb544.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -9,55 +9,54 @@ #ifndef __CROS_EC_USB_REDRIVER_TUSB544_H #define __CROS_EC_USB_REDRIVER_TUSB544_H - #define TUSB544_I2C_ADDR_FLAGS0 0x44 -#define TUSB544_REG_GENERAL4 0x0A -#define TUSB544_GEN4_CTL_SEL GENMASK(1, 0) -#define TUSB544_GEN4_FLIP_SEL BIT(2) -#define TUSB544_GEN4_HPDIN BIT(3) -#define TUSB544_GEN4_EQ_OVRD BIT(4) -#define TUSB544_GEN4_SWAP_SEL BIT(5) +#define TUSB544_REG_GENERAL4 0x0A +#define TUSB544_GEN4_CTL_SEL GENMASK(1, 0) +#define TUSB544_GEN4_FLIP_SEL BIT(2) +#define TUSB544_GEN4_HPDIN BIT(3) +#define TUSB544_GEN4_EQ_OVRD BIT(4) +#define TUSB544_GEN4_SWAP_SEL BIT(5) -#define TUSB544_REG_DISPLAYPORT_1 0x10 -#define TUSB544_REG_DISPLAYPORT_2 0x11 -#define TUSB544_REG_USB3_1_1 0x20 -#define TUSB544_REG_USB3_1_2 0x21 -#define TUSB544_EQ_RX_DFP_MINUS14_UFP_MINUS33 (0) -#define TUSB544_EQ_RX_DFP_04_UFP_MINUS15 (1) -#define TUSB544_EQ_RX_DFP_17_UFP_0 (2) -#define TUSB544_EQ_RX_DFP_32_UFP_14 (3) -#define TUSB544_EQ_RX_DFP_41_UFP_24 (4) -#define TUSB544_EQ_RX_DFP_52_UFP_35 (5) -#define TUSB544_EQ_RX_DFP_61_UFP_43 (6) -#define TUSB544_EQ_RX_DFP_69_UFP_52 (7) -#define TUSB544_EQ_RX_DFP_77_UFP_60 (8) -#define TUSB544_EQ_RX_DFP_83_UFP_66 (9) -#define TUSB544_EQ_RX_DFP_88_UFP_72 (10) -#define TUSB544_EQ_RX_DFP_94_UFP_77 (11) -#define TUSB544_EQ_RX_DFP_98_UFP_81 (12) -#define TUSB544_EQ_RX_DFP_103_UFP_86 (13) -#define TUSB544_EQ_RX_DFP_106_UFP_90 (14) -#define TUSB544_EQ_RX_DFP_110_UFP_94 (15) -#define TUSB544_EQ_RX_MASK (0x0F) +#define TUSB544_REG_DISPLAYPORT_1 0x10 +#define TUSB544_REG_DISPLAYPORT_2 0x11 +#define TUSB544_REG_USB3_1_1 0x20 +#define TUSB544_REG_USB3_1_2 0x21 +#define TUSB544_EQ_RX_DFP_MINUS14_UFP_MINUS33 (0) +#define TUSB544_EQ_RX_DFP_04_UFP_MINUS15 (1) +#define TUSB544_EQ_RX_DFP_17_UFP_0 (2) +#define TUSB544_EQ_RX_DFP_32_UFP_14 (3) +#define TUSB544_EQ_RX_DFP_41_UFP_24 (4) +#define TUSB544_EQ_RX_DFP_52_UFP_35 (5) +#define TUSB544_EQ_RX_DFP_61_UFP_43 (6) +#define TUSB544_EQ_RX_DFP_69_UFP_52 (7) +#define TUSB544_EQ_RX_DFP_77_UFP_60 (8) +#define TUSB544_EQ_RX_DFP_83_UFP_66 (9) +#define TUSB544_EQ_RX_DFP_88_UFP_72 (10) +#define TUSB544_EQ_RX_DFP_94_UFP_77 (11) +#define TUSB544_EQ_RX_DFP_98_UFP_81 (12) +#define TUSB544_EQ_RX_DFP_103_UFP_86 (13) +#define TUSB544_EQ_RX_DFP_106_UFP_90 (14) +#define TUSB544_EQ_RX_DFP_110_UFP_94 (15) +#define TUSB544_EQ_RX_MASK (0x0F) -#define TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33 (0 << 4) -#define TUSB544_EQ_TX_DFP_04_UFP_MINUS15 (1 << 4) -#define TUSB544_EQ_TX_DFP_17_UFP_0 (2 << 4) -#define TUSB544_EQ_TX_DFP_32_UFP_14 (3 << 4) -#define TUSB544_EQ_TX_DFP_41_UFP_24 (4 << 4) -#define TUSB544_EQ_TX_DFP_52_UFP_35 (5 << 4) -#define TUSB544_EQ_TX_DFP_61_UFP_43 (6 << 4) -#define TUSB544_EQ_TX_DFP_69_UFP_52 (7 << 4) -#define TUSB544_EQ_TX_DFP_77_UFP_60 (8 << 4) -#define TUSB544_EQ_TX_DFP_83_UFP_66 (9 << 4) -#define TUSB544_EQ_TX_DFP_88_UFP_72 (10 << 4) -#define TUSB544_EQ_TX_DFP_94_UFP_77 (11 << 4) -#define TUSB544_EQ_TX_DFP_98_UFP_81 (12 << 4) -#define TUSB544_EQ_TX_DFP_103_UFP_86 (13 << 4) -#define TUSB544_EQ_TX_DFP_106_UFP_90 (14 << 4) -#define TUSB544_EQ_TX_DFP_110_UFP_94 (15 << 4) -#define TUSB544_EQ_TX_MASK (0xF0) +#define TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33 (0 << 4) +#define TUSB544_EQ_TX_DFP_04_UFP_MINUS15 (1 << 4) +#define TUSB544_EQ_TX_DFP_17_UFP_0 (2 << 4) +#define TUSB544_EQ_TX_DFP_32_UFP_14 (3 << 4) +#define TUSB544_EQ_TX_DFP_41_UFP_24 (4 << 4) +#define TUSB544_EQ_TX_DFP_52_UFP_35 (5 << 4) +#define TUSB544_EQ_TX_DFP_61_UFP_43 (6 << 4) +#define TUSB544_EQ_TX_DFP_69_UFP_52 (7 << 4) +#define TUSB544_EQ_TX_DFP_77_UFP_60 (8 << 4) +#define TUSB544_EQ_TX_DFP_83_UFP_66 (9 << 4) +#define TUSB544_EQ_TX_DFP_88_UFP_72 (10 << 4) +#define TUSB544_EQ_TX_DFP_94_UFP_77 (11 << 4) +#define TUSB544_EQ_TX_DFP_98_UFP_81 (12 << 4) +#define TUSB544_EQ_TX_DFP_103_UFP_86 (13 << 4) +#define TUSB544_EQ_TX_DFP_106_UFP_90 (14 << 4) +#define TUSB544_EQ_TX_DFP_110_UFP_94 (15 << 4) +#define TUSB544_EQ_TX_MASK (0xF0) enum tusb544_ct_sel { TUSB544_CTL_SEL_DISABLED, @@ -66,10 +65,10 @@ enum tusb544_ct_sel { TUSB544_CTL_SEL_DP_USB, }; -#define TUSB544_REG_GENERAL6 0x0C -#define TUSB544_GEN6_DIR_SEL GENMASK(1, 0) -#define TUSB544_VOD_DCGAIN_SEL GENMASK(5, 2) -#define TUSB544_VOD_DCGAIN_OVERRIDE BIT(6) +#define TUSB544_REG_GENERAL6 0x0C +#define TUSB544_GEN6_DIR_SEL GENMASK(1, 0) +#define TUSB544_VOD_DCGAIN_SEL GENMASK(5, 2) +#define TUSB544_VOD_DCGAIN_OVERRIDE BIT(6) enum tusb544_dir_sel { TUSB544_DIR_SEL_USB_DP_SRC, @@ -93,17 +92,17 @@ enum tusb544_vod_dcgain_sel { * Note: TUSB544 automatically snoops DP lanes to enable, but may be manually * directed which lanes to turn on when snoop is disabled */ -#define TUSB544_REG_DP4 0x13 -#define TUSB544_DP4_DP0_DISABLE BIT(0) -#define TUSB544_DP4_DP1_DISABLE BIT(1) -#define TUSB544_DP4_DP2_DISABLE BIT(2) -#define TUSB544_DP4_DP3_DISABLE BIT(3) -#define TUSB544_DP4_AUX_SBU_OVR GENMASK(5, 4) -#define TUSB544_DP4_AUX_SNOOP_DISABLE BIT(7) +#define TUSB544_REG_DP4 0x13 +#define TUSB544_DP4_DP0_DISABLE BIT(0) +#define TUSB544_DP4_DP1_DISABLE BIT(1) +#define TUSB544_DP4_DP2_DISABLE BIT(2) +#define TUSB544_DP4_DP3_DISABLE BIT(3) +#define TUSB544_DP4_AUX_SBU_OVR GENMASK(5, 4) +#define TUSB544_DP4_AUX_SNOOP_DISABLE BIT(7) extern const struct usb_mux_driver tusb544_drv; int tusb544_i2c_field_update8(const struct usb_mux *me, int offset, - uint8_t field_mask, uint8_t set_value); + uint8_t field_mask, uint8_t set_value); #endif |