diff options
Diffstat (limited to 'include/driver/tcpm')
| -rw-r--r-- | include/driver/tcpm/anx7447_public.h | 28 | ||||
| -rw-r--r-- | include/driver/tcpm/it8xxx2_pd_public.h | 2 | ||||
| -rw-r--r-- | include/driver/tcpm/ps8xxx_public.h | 19 | ||||
| -rw-r--r-- | include/driver/tcpm/rt1715_public.h | 2 | ||||
| -rw-r--r-- | include/driver/tcpm/rt1718s_public.h | 24 | ||||
| -rw-r--r-- | include/driver/tcpm/tcpci.h | 452 | ||||
| -rw-r--r-- | include/driver/tcpm/tcpm.h | 121 | ||||
| -rw-r--r-- | include/driver/tcpm/tusb422_public.h | 2 |
8 files changed, 354 insertions, 296 deletions
diff --git a/include/driver/tcpm/anx7447_public.h b/include/driver/tcpm/anx7447_public.h new file mode 100644 index 0000000000..5ea1eebd35 --- /dev/null +++ b/include/driver/tcpm/anx7447_public.h @@ -0,0 +1,28 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Analogix Type-C port controller */ + +#ifndef __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H +#define __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H + +#include "usb_mux.h" + +#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C +#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B +#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A +#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29 + +#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F +#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37 +#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32 +#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31 + +extern const struct tcpm_drv anx7447_tcpm_drv; +extern const struct usb_mux_driver anx7447_usb_mux_driver; + +void anx7447_tcpc_update_hpd_status(const struct usb_mux *me, + mux_state_t mux_state, bool *ack_required); +#endif /* __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H */ diff --git a/include/driver/tcpm/it8xxx2_pd_public.h b/include/driver/tcpm/it8xxx2_pd_public.h index 6ad11a9555..0c28127cdb 100644 --- a/include/driver/tcpm/it8xxx2_pd_public.h +++ b/include/driver/tcpm/it8xxx2_pd_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/tcpm/ps8xxx_public.h b/include/driver/tcpm/ps8xxx_public.h index ad84f93ced..d327dee2a3 100644 --- a/include/driver/tcpm/ps8xxx_public.h +++ b/include/driver/tcpm/ps8xxx_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,12 +15,12 @@ struct usb_mux; /* I2C interface */ #define PS8XXX_I2C_ADDR1_P1_FLAGS 0x09 #define PS8XXX_I2C_ADDR1_P2_FLAGS 0x0A -#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */ -#define PS8XXX_I2C_ADDR2_FLAGS 0x1B -#define PS8XXX_I2C_ADDR3_FLAGS 0x2B -#define PS8XXX_I2C_ADDR4_FLAGS 0x4B +#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */ +#define PS8XXX_I2C_ADDR2_FLAGS 0x1B +#define PS8XXX_I2C_ADDR3_FLAGS 0x2B +#define PS8XXX_I2C_ADDR4_FLAGS 0x4B -#define PS8XXX_VENDOR_ID 0x1DA0 +#define PS8XXX_VENDOR_ID 0x1DA0 /* Minimum Delay for reset assertion */ #define PS8XXX_RESET_DELAY_MS 1 @@ -56,6 +56,7 @@ struct usb_mux; * 8705, 8755 and 8805. */ #define PS8705_PRODUCT_ID 0x8705 +#define PS8745_PRODUCT_ID 0x8745 #define PS8751_PRODUCT_ID 0x8751 #define PS8755_PRODUCT_ID 0x8755 #define PS8805_PRODUCT_ID 0x8805 @@ -75,12 +76,10 @@ extern const struct tcpm_drv ps8xxx_tcpm_drv; * * @param port TCPC port number. */ -__override_proto -uint16_t board_get_ps8xxx_product_id(int port); +__override_proto uint16_t board_get_ps8xxx_product_id(int port); void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required); + mux_state_t mux_state, bool *ack_required); #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC extern struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev; diff --git a/include/driver/tcpm/rt1715_public.h b/include/driver/tcpm/rt1715_public.h index 14fa9495e8..2f3af95443 100644 --- a/include/driver/tcpm/rt1715_public.h +++ b/include/driver/tcpm/rt1715_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/tcpm/rt1718s_public.h b/include/driver/tcpm/rt1718s_public.h new file mode 100644 index 0000000000..62bade6ab9 --- /dev/null +++ b/include/driver/tcpm/rt1718s_public.h @@ -0,0 +1,24 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Richtek Type-C port controller */ + +#ifndef __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H +#define __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H + +#define RT1718S_I2C_ADDR1_FLAGS 0x43 +#define RT1718S_I2C_ADDR2_FLAGS 0x40 + +#define RT1718S_VID 0x29CF +#define RT1718S_PID 0x1718 + +#define RT1718S_DEVICE_ID 0x04 +#define RT1718S_DEVICE_ID_ES1 0x4511 +#define RT1718S_DEVICE_ID_ES2 0x4513 + +extern const struct tcpm_drv rt1718s_tcpm_drv; +extern const struct bc12_drv rt1718s_bc12_drv; + +#endif /* __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H */ diff --git a/include/driver/tcpm/tcpci.h b/include/driver/tcpm/tcpci.h index 559b75a14f..4879f7dad1 100644 --- a/include/driver/tcpm/tcpci.h +++ b/include/driver/tcpm/tcpci.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,259 +14,250 @@ #include "usb_mux.h" #include "usb_pd_tcpm.h" -#define TCPC_REG_VENDOR_ID 0x0 -#define TCPC_REG_PRODUCT_ID 0x2 -#define TCPC_REG_BCD_DEV 0x4 -#define TCPC_REG_TC_REV 0x6 -#define TCPC_REG_PD_REV 0x8 -#define TCPC_REG_PD_INT_REV 0xa - -#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00 -#define TCPC_REG_PD_INT_REV_REV_1_0 0x10 -#define TCPC_REG_PD_INT_REV_REV_2_0 0x20 -#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff -#define TCPC_REG_PD_INT_REV_VER_1_0 0x10 -#define TCPC_REG_PD_INT_REV_VER_1_1 0x11 -#define TCPC_REG_PD_INT_REV_REV(reg) \ - ((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8) -#define TCPC_REG_PD_INT_REV_VER(reg) \ - (reg & TCOC_REG_PD_INT_REV_VER_MASK) - -#define TCPC_REG_ALERT 0x10 -#define TCPC_REG_ALERT_NONE 0x0000 -#define TCPC_REG_ALERT_MASK_ALL 0xffff -#define TCPC_REG_ALERT_VENDOR_DEF BIT(15) -#define TCPC_REG_ALERT_ALERT_EXT BIT(14) -#define TCPC_REG_ALERT_EXT_STATUS BIT(13) +#define TCPC_REG_VENDOR_ID 0x0 +#define TCPC_REG_PRODUCT_ID 0x2 +#define TCPC_REG_BCD_DEV 0x4 +#define TCPC_REG_TC_REV 0x6 +#define TCPC_REG_PD_REV 0x8 +#define TCPC_REG_PD_INT_REV 0xa + +#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00 +#define TCPC_REG_PD_INT_REV_REV_1_0 0x10 +#define TCPC_REG_PD_INT_REV_REV_2_0 0x20 +#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff +#define TCPC_REG_PD_INT_REV_VER_1_0 0x10 +#define TCPC_REG_PD_INT_REV_VER_1_1 0x11 +#define TCPC_REG_PD_INT_REV_REV(reg) ((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8) +#define TCPC_REG_PD_INT_REV_VER(reg) (reg & TCOC_REG_PD_INT_REV_VER_MASK) + +#define TCPC_REG_ALERT 0x10 +#define TCPC_REG_ALERT_NONE 0x0000 +#define TCPC_REG_ALERT_MASK_ALL 0xffff +#define TCPC_REG_ALERT_VENDOR_DEF BIT(15) +#define TCPC_REG_ALERT_ALERT_EXT BIT(14) +#define TCPC_REG_ALERT_EXT_STATUS BIT(13) #define TCPC_REG_ALERT_RX_BEGINNING BIT(12) #define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11) -#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10) -#define TCPC_REG_ALERT_FAULT BIT(9) -#define TCPC_REG_ALERT_V_ALARM_LO BIT(8) -#define TCPC_REG_ALERT_V_ALARM_HI BIT(7) -#define TCPC_REG_ALERT_TX_SUCCESS BIT(6) +#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10) +#define TCPC_REG_ALERT_FAULT BIT(9) +#define TCPC_REG_ALERT_V_ALARM_LO BIT(8) +#define TCPC_REG_ALERT_V_ALARM_HI BIT(7) +#define TCPC_REG_ALERT_TX_SUCCESS BIT(6) #define TCPC_REG_ALERT_TX_DISCARDED BIT(5) -#define TCPC_REG_ALERT_TX_FAILED BIT(4) -#define TCPC_REG_ALERT_RX_HARD_RST BIT(3) -#define TCPC_REG_ALERT_RX_STATUS BIT(2) +#define TCPC_REG_ALERT_TX_FAILED BIT(4) +#define TCPC_REG_ALERT_RX_HARD_RST BIT(3) +#define TCPC_REG_ALERT_RX_STATUS BIT(2) #define TCPC_REG_ALERT_POWER_STATUS BIT(1) -#define TCPC_REG_ALERT_CC_STATUS BIT(0) -#define TCPC_REG_ALERT_TX_COMPLETE (TCPC_REG_ALERT_TX_SUCCESS | \ - TCPC_REG_ALERT_TX_DISCARDED | \ - TCPC_REG_ALERT_TX_FAILED) +#define TCPC_REG_ALERT_CC_STATUS BIT(0) +#define TCPC_REG_ALERT_TX_COMPLETE \ + (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | \ + TCPC_REG_ALERT_TX_FAILED) -#define TCPC_REG_ALERT_MASK 0x12 -#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15) +#define TCPC_REG_ALERT_MASK 0x12 +#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15) #define TCPC_REG_POWER_STATUS_MASK 0x14 #define TCPC_REG_FAULT_STATUS_MASK 0x15 -#define TCPC_REG_EXT_STATUS_MASK 0x16 +#define TCPC_REG_EXT_STATUS_MASK 0x16 #define TCPC_REG_ALERT_EXTENDED_MASK 0x17 #define TCPC_REG_CONFIG_STD_OUTPUT 0x18 -#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) -#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) +#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) #define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0) -#define TCPC_REG_TCPC_CTRL 0x19 +#define TCPC_REG_TCPC_CTRL 0x19 #define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity) -#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg) & 0x1) +#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg)&0x1) /* * In TCPCI Rev 2.0, this bit must be set this to generate CC status alerts when * a connection is found. */ -#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6) -#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4) -#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1) - -#define TCPC_REG_ROLE_CTRL 0x1a -#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6) -#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5)|BIT(4)) -#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3)|BIT(2)) -#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1)|BIT(0)) -#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \ - ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \ - (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \ - (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \ - ((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK)) -#define TCPC_REG_ROLE_CTRL_DRP(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6) -#define TCPC_REG_ROLE_CTRL_RP(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4) -#define TCPC_REG_ROLE_CTRL_CC2(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2) -#define TCPC_REG_ROLE_CTRL_CC1(reg) \ - ((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK) - -#define TCPC_REG_FAULT_CTRL 0x1b -#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1) -#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(0) - -#define TCPC_REG_POWER_CTRL 0x1c -#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) -#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) -#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) -#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) -#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) +#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6) +#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4) +#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1) + +#define TCPC_REG_ROLE_CTRL 0x1a +#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6) +#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5) | BIT(4)) +#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3) | BIT(2)) +#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1) | BIT(0)) +#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \ + ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \ + (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \ + (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \ + ((cc1)&TCPC_REG_ROLE_CTRL_CC1_MASK)) +#define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg)&TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6) +#define TCPC_REG_ROLE_CTRL_RP(reg) (((reg)&TCPC_REG_ROLE_CTRL_RP_MASK) >> 4) +#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg)&TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2) +#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg)&TCPC_REG_ROLE_CTRL_CC1_MASK) + +#define TCPC_REG_FAULT_CTRL 0x1b +#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1) +#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(0) + +#define TCPC_REG_POWER_CTRL 0x1c +#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) +#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) +#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) +#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) +#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) #define TCPC_REG_POWER_CTRL_SET(vconn) (vconn) -#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg) & 0x1) +#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg)&0x1) -#define TCPC_REG_CC_STATUS 0x1d -#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5) -#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4) -#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3)|BIT(2)) -#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1)|BIT(0)) +#define TCPC_REG_CC_STATUS 0x1d +#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5) +#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4) +#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3) | BIT(2)) +#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1) | BIT(0)) #define TCPC_REG_CC_STATUS_SET(term, cc1, cc2) \ - ((term) << 4 | ((cc2) & 0x3) << 2 | ((cc1) & 0x3)) + ((term) << 4 | ((cc2)&0x3) << 2 | ((cc1)&0x3)) #define TCPC_REG_CC_STATUS_LOOK4CONNECTION(reg) \ - ((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5) + ((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5) #define TCPC_REG_CC_STATUS_TERM(reg) \ - (((reg) & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4) + (((reg)&TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4) #define TCPC_REG_CC_STATUS_CC2(reg) \ - (((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2) -#define TCPC_REG_CC_STATUS_CC1(reg) \ - ((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK) + (((reg)&TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2) +#define TCPC_REG_CC_STATUS_CC1(reg) ((reg)&TCPC_REG_CC_STATUS_CC1_STATE_MASK) -#define TCPC_REG_POWER_STATUS 0x1e -#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff +#define TCPC_REG_POWER_STATUS 0x1e +#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff #define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7) -#define TCPC_REG_POWER_STATUS_UNINIT BIT(6) +#define TCPC_REG_POWER_STATUS_UNINIT BIT(6) #define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4) -#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3) +#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3) #define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2) #define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0) -#define TCPC_REG_FAULT_STATUS 0x1f -#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7) -#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6) -#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5) -#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4) -#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3) -#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2) -#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1) -#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0) - -#define TCPC_REG_EXT_STATUS 0x20 -#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0) - -#define TCPC_REG_ALERT_EXT 0x21 -#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2) -#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1) -#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0) - -#define TCPC_REG_COMMAND 0x23 -#define TCPC_REG_COMMAND_WAKE_I2C 0x11 -#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33 -#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44 -#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55 -#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66 -#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77 -#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99 -#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD -#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE -#define TCPC_REG_COMMAND_I2CIDLE 0xFF - -#define TCPC_REG_DEV_CAP_1 0x24 -#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) -#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) -#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) -#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) -#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) -#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8)|BIT(9)) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8) -#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5) -#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) -#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) -#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) -#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1) -#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) - -#define TCPC_REG_DEV_CAP_2 0x26 -#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12) -#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9) - -#define TCPC_REG_STD_INPUT_CAP 0x28 -#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4)|BIT(3)) -#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2) -#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1) -#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0) - -#define TCPC_REG_STD_OUTPUT_CAP 0x29 -#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7) -#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6) -#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5) -#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4) -#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3) -#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2) -#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1) -#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0) - -#define TCPC_REG_CONFIG_EXT_1 0x2A -#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1) - -#define TCPC_REG_GENERIC_TIMER 0x2c - -#define TCPC_REG_MSG_HDR_INFO 0x2e +#define TCPC_REG_FAULT_STATUS 0x1f +#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7) +#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6) +#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5) +#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4) +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3) +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2) +#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1) +#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0) + +#define TCPC_REG_EXT_STATUS 0x20 +#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0) + +#define TCPC_REG_ALERT_EXT 0x21 +#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2) +#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1) +#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0) + +#define TCPC_REG_COMMAND 0x23 +#define TCPC_REG_COMMAND_WAKE_I2C 0x11 +#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33 +#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44 +#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55 +#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66 +#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77 +#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99 +#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD +#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE +#define TCPC_REG_COMMAND_I2CIDLE 0xFF + +#define TCPC_REG_DEV_CAP_1 0x24 +#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) +#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) +#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) +#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) +#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) +#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8) | BIT(9)) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8) +#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5) | BIT(6) | BIT(7)) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5) +#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) +#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) +#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) +#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1) +#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) + +#define TCPC_REG_DEV_CAP_2 0x26 +#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12) +#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9) + +#define TCPC_REG_STD_INPUT_CAP 0x28 +#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4) | BIT(3)) +#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2) +#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1) +#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0) + +#define TCPC_REG_STD_OUTPUT_CAP 0x29 +#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7) +#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6) +#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5) +#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4) +#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3) +#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2) +#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1) +#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0) + +#define TCPC_REG_CONFIG_EXT_1 0x2A +#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1) + +#define TCPC_REG_GENERIC_TIMER 0x2c + +#define TCPC_REG_MSG_HDR_INFO 0x2e #define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \ - ((drole) << 3 | (PD_REV20 << 1) | (prole)) -#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3) -#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1) - -#define TCPC_REG_RX_DETECT 0x2f -#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7) -#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6) -#define TCPC_REG_RX_DETECT_HRST BIT(5) -#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4) -#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3) -#define TCPC_REG_RX_DETECT_SOPPP BIT(2) -#define TCPC_REG_RX_DETECT_SOPP BIT(1) -#define TCPC_REG_RX_DETECT_SOP BIT(0) -#define TCPC_REG_RX_DETECT_SOP_HRST_MASK (TCPC_REG_RX_DETECT_SOP | \ - TCPC_REG_RX_DETECT_HRST) -#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \ - (TCPC_REG_RX_DETECT_SOP | \ - TCPC_REG_RX_DETECT_SOPP | \ - TCPC_REG_RX_DETECT_SOPPP | \ - TCPC_REG_RX_DETECT_HRST) + ((drole) << 3 | (PD_REV20 << 1) | (prole)) +#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg)&0x8) >> 3) +#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg)&0x1) + +#define TCPC_REG_RX_DETECT 0x2f +#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7) +#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6) +#define TCPC_REG_RX_DETECT_HRST BIT(5) +#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4) +#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3) +#define TCPC_REG_RX_DETECT_SOPPP BIT(2) +#define TCPC_REG_RX_DETECT_SOPP BIT(1) +#define TCPC_REG_RX_DETECT_SOP BIT(0) +#define TCPC_REG_RX_DETECT_SOP_HRST_MASK \ + (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST) +#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \ + (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | \ + TCPC_REG_RX_DETECT_SOPPP | TCPC_REG_RX_DETECT_HRST) /* TCPCI Rev 1.0 receive registers */ -#define TCPC_REG_RX_BYTE_CNT 0x30 +#define TCPC_REG_RX_BYTE_CNT 0x30 #define TCPC_REG_RX_BUF_FRAME_TYPE 0x31 -#define TCPC_REG_RX_HDR 0x32 -#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */ +#define TCPC_REG_RX_HDR 0x32 +#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */ /* * In TCPCI Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers: * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can * only be accessed by reading at a common register address 30h. */ -#define TCPC_REG_RX_BUFFER 0x30 +#define TCPC_REG_RX_BUFFER 0x30 -#define TCPC_REG_TRANSMIT 0x50 +#define TCPC_REG_TRANSMIT 0x50 #define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) \ - ((retries) << 4 | (type)) + ((retries) << 4 | (type)) #define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type) -#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4) -#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg) & 0x7) +#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg)&0x30) >> 4) +#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg)&0x7) /* TCPCI Rev 1.0 transmit registers */ -#define TCPC_REG_TX_BYTE_CNT 0x51 -#define TCPC_REG_TX_HDR 0x52 -#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */ +#define TCPC_REG_TX_BYTE_CNT 0x51 +#define TCPC_REG_TX_HDR 0x52 +#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */ /* * In TCPCI Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the @@ -274,12 +265,12 @@ * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x * is “hidden” and can only be accessed by writing to register address 51h */ -#define TCPC_REG_TX_BUFFER 0x51 +#define TCPC_REG_TX_BUFFER 0x51 -#define TCPC_REG_VBUS_VOLTAGE 0x70 -#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0) -#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10) -#define TCPC_REG_VBUS_VOLTAGE_LSB 25 +#define TCPC_REG_VBUS_VOLTAGE 0x70 +#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0) +#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10) +#define TCPC_REG_VBUS_VOLTAGE_LSB 25 /* * 00: the measurement is not scaled @@ -287,22 +278,21 @@ * 10: the measurement is divided by 4 * 11: reserved */ -#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \ - (1 << (((x) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9)) -#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) \ - ((x) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT) -#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \ - (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \ +#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \ + (1 << (((x)&TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9)) +#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) ((x)&TCPC_REG_VBUS_VOLTAGE_MEASUREMENT) +#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \ + (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \ TCPC_REG_VBUS_VOLTAGE_LSB) #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72 #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */ -#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74 -#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 -#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 +#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74 +#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 +#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 -#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a +#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a extern const struct tcpm_drv tcpci_tcpm_drv; extern const struct usb_mux_driver tcpci_tcpm_usb_mux_driver; @@ -315,7 +305,7 @@ enum tcpc_cc_pull tcpci_get_cached_pull(int port); void tcpci_tcpc_alert(int port); int tcpci_tcpm_init(int port); int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); bool tcpci_tcpm_check_vbus_level(int port, enum vbus_level level); int tcpci_tcpm_select_rp_value(int port, int rp); int tcpci_tcpm_set_cc(int port, int pull); @@ -325,20 +315,22 @@ int tcpci_tcpm_set_vconn(int port, int enable); int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role); int tcpci_tcpm_set_rx_enable(int port, int enable); int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head); -int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, - uint16_t header, const uint32_t *data); +int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header, + const uint32_t *data); int tcpci_tcpm_release(int port); #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp, - enum tcpc_cc_pull pull); + enum tcpc_cc_pull pull); int tcpci_tcpc_drp_toggle(int port); #endif #ifdef CONFIG_USB_PD_TCPC_LOW_POWER int tcpci_enter_low_power_mode(int port); void tcpci_wake_low_power_mode(int port); #endif -enum ec_error_list tcpci_set_bist_test_mode(const int port, - const bool enable); +int tcpci_hard_reset_reinit(int port); + +enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable); +enum ec_error_list tcpci_get_bist_test_mode(const int port, bool *enable); void tcpci_tcpc_discharge_vbus(int port, int enable); void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable); int tcpci_tcpc_debug_accessory(int port, bool enable); diff --git a/include/driver/tcpm/tcpm.h b/include/driver/tcpm/tcpm.h index ef47a3b1e2..8352423d9d 100644 --- a/include/driver/tcpm/tcpm.h +++ b/include/driver/tcpm/tcpm.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,26 +26,22 @@ #ifndef CONFIG_USB_PD_TCPC_LOW_POWER static inline int tcpc_addr_write(int port, int i2c_addr, int reg, int val) { - return i2c_write8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_write8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_write16(int port, int i2c_addr, int reg, int val) { - return i2c_write16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_write16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_read(int port, int i2c_addr, int reg, int *val) { - return i2c_read8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_read8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val) { - return i2c_read16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_read16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } /* @@ -65,8 +61,8 @@ static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val) * need an explicit by the caller. */ -static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, - int reg, int *val) +static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, + int *val) { return tcpc_addr_read16(port, i2c_addr, reg, val); } @@ -75,49 +71,47 @@ static inline int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in, int in_size) { return i2c_xfer(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - out, out_size, in, in_size); + tcpc_config[port].i2c_info.addr_flags, out, out_size, + in, in_size); } static inline int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) + uint8_t *in, int in_size, int flags) { return i2c_xfer_unlocked(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - out, out_size, in, in_size, flags); + tcpc_config[port].i2c_info.addr_flags, out, + out_size, in, in_size, flags); } static inline int tcpc_read_block(int port, int reg, uint8_t *in, int size) { return i2c_read_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, in, size); + tcpc_config[port].i2c_info.addr_flags, reg, in, + size); } -static inline int tcpc_write_block(int port, int reg, - const uint8_t *out, int size) +static inline int tcpc_write_block(int port, int reg, const uint8_t *out, + int size) { return i2c_write_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, out, size); + tcpc_config[port].i2c_info.addr_flags, reg, out, + size); } -static inline int tcpc_update8(int port, int reg, - uint8_t mask, +static inline int tcpc_update8(int port, int reg, uint8_t mask, enum mask_update_action action) { return i2c_update8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, mask, action); + tcpc_config[port].i2c_info.addr_flags, reg, mask, + action); } -static inline int tcpc_update16(int port, int reg, - uint16_t mask, +static inline int tcpc_update16(int port, int reg, uint16_t mask, enum mask_update_action action) { return i2c_update16(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, mask, action); + tcpc_config[port].i2c_info.addr_flags, reg, mask, + action); } #else /* !CONFIG_USB_PD_TCPC_LOW_POWER */ @@ -128,40 +122,40 @@ int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val); int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val); int tcpc_read_block(int port, int reg, uint8_t *in, int size); int tcpc_write_block(int port, int reg, const uint8_t *out, int size); -int tcpc_xfer(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size); -int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); +int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size); +int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags); -int tcpc_update8(int port, int reg, - uint8_t mask, enum mask_update_action action); -int tcpc_update16(int port, int reg, - uint16_t mask, enum mask_update_action action); +int tcpc_update8(int port, int reg, uint8_t mask, + enum mask_update_action action); +int tcpc_update16(int port, int reg, uint16_t mask, + enum mask_update_action action); #endif /* CONFIG_USB_PD_TCPC_LOW_POWER */ static inline int tcpc_write(int port, int reg, int val) { - return tcpc_addr_write(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_write(port, tcpc_config[port].i2c_info.addr_flags, reg, + val); } static inline int tcpc_write16(int port, int reg, int val) { - return tcpc_addr_write16(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_write16(port, tcpc_config[port].i2c_info.addr_flags, + reg, val); } static inline int tcpc_read(int port, int reg, int *val) { - return tcpc_addr_read(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_read(port, tcpc_config[port].i2c_info.addr_flags, reg, + val); } static inline int tcpc_read16(int port, int reg, int *val) { - return tcpc_addr_read16(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_read16(port, tcpc_config[port].i2c_info.addr_flags, + reg, val); } static inline void tcpc_lock(int port, int lock) @@ -191,7 +185,7 @@ static inline int tcpm_release(int port) } static inline int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { return tcpc_config[port].drv->get_cc(port, cc1, cc2); } @@ -281,7 +275,8 @@ static inline int tcpm_transmit(int port, enum tcpci_msg_type type, static inline bool tcpm_get_snk_ctrl(int port) { return tcpc_config[port].drv->get_snk_ctrl ? - tcpc_config[port].drv->get_snk_ctrl(port) : false; + tcpc_config[port].drv->get_snk_ctrl(port) : + false; } static inline int tcpm_set_snk_ctrl(int port, int enable) { @@ -293,9 +288,9 @@ static inline int tcpm_set_snk_ctrl(int port, int enable) static inline bool tcpm_get_src_ctrl(int port) { - return tcpc_config[port].drv->get_src_ctrl ? - tcpc_config[port].drv->get_src_ctrl(port) : false; + tcpc_config[port].drv->get_src_ctrl(port) : + false; } static inline int tcpm_set_src_ctrl(int port, int enable) { @@ -387,6 +382,13 @@ static inline int tcpm_get_chip_info(int port, int live, return EC_ERROR_UNIMPLEMENTED; } +static inline int tcpm_hard_reset_reinit(int port) +{ + if (tcpc_config[port].drv->hard_reset_reinit) + return tcpc_config[port].drv->hard_reset_reinit(port); + return EC_ERROR_UNIMPLEMENTED; +} + static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable) { const struct tcpm_drv *tcpc; @@ -398,6 +400,19 @@ static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable) return rv; } +static inline enum ec_error_list tcpc_get_bist_test_mode(int port, bool *enable) +{ + const struct tcpm_drv *tcpc; + + tcpc = tcpc_config[port].drv; + if (tcpc->get_bist_test_mode) + return tcpc->get_bist_test_mode(port, enable); + + *enable = false; + + return EC_ERROR_UNIMPLEMENTED; +} + /* * Returns true if the port controls FRS using the TCPC. */ @@ -444,8 +459,8 @@ static inline int tcpm_set_frs_enable(int port, int enable) static inline int tcpc_set_sbu(int port, bool enable) { return tcpc_config[port].drv->set_sbu ? - tcpc_config[port].drv->set_sbu(port, enable) : - EC_SUCCESS; + tcpc_config[port].drv->set_sbu(port, enable) : + EC_SUCCESS; } #endif /* CONFIG_USB_PD_TCPM_SBU */ @@ -470,7 +485,7 @@ int tcpm_init(int port); * @return EC_SUCCESS or error */ int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); /** * Check VBUS level diff --git a/include/driver/tcpm/tusb422_public.h b/include/driver/tcpm/tusb422_public.h index 8756d9b362..004abdd5c9 100644 --- a/include/driver/tcpm/tusb422_public.h +++ b/include/driver/tcpm/tusb422_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ |