diff options
Diffstat (limited to 'include/driver')
42 files changed, 1867 insertions, 1637 deletions
diff --git a/include/driver/accel_bma2x2.h b/include/driver/accel_bma2x2.h index 3a46c7c050..c6be3b0c87 100644 --- a/include/driver/accel_bma2x2.h +++ b/include/driver/accel_bma2x2.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,144 +12,143 @@ /*** Chip-specific registers ***/ /* REGISTER ADDRESS DEFINITIONS */ -#define BMA2x2_EEP_OFFSET 0x16 -#define BMA2x2_IMAGE_BASE 0x38 -#define BMA2x2_IMAGE_LEN 22 -#define BMA2x2_CHIP_ID_ADDR 0x00 -#define BMA255_CHIP_ID_MAJOR 0xfa +#define BMA2x2_EEP_OFFSET 0x16 +#define BMA2x2_IMAGE_BASE 0x38 +#define BMA2x2_IMAGE_LEN 22 +#define BMA2x2_CHIP_ID_ADDR 0x00 +#define BMA255_CHIP_ID_MAJOR 0xfa /* DATA ADDRESS DEFINITIONS */ -#define BMA2x2_X_AXIS_LSB_ADDR 0x02 -#define BMA2x2_X_AXIS_MSB_ADDR 0x03 -#define BMA2x2_Y_AXIS_LSB_ADDR 0x04 -#define BMA2x2_Y_AXIS_MSB_ADDR 0x05 -#define BMA2x2_Z_AXIS_LSB_ADDR 0x06 -#define BMA2x2_Z_AXIS_MSB_ADDR 0x07 -#define BMA2x2_TEMP_ADDR 0x08 +#define BMA2x2_X_AXIS_LSB_ADDR 0x02 +#define BMA2x2_X_AXIS_MSB_ADDR 0x03 +#define BMA2x2_Y_AXIS_LSB_ADDR 0x04 +#define BMA2x2_Y_AXIS_MSB_ADDR 0x05 +#define BMA2x2_Z_AXIS_LSB_ADDR 0x06 +#define BMA2x2_Z_AXIS_MSB_ADDR 0x07 +#define BMA2x2_TEMP_ADDR 0x08 -#define BMA2x2_AXIS_LSB_NEW_DATA 0x01 +#define BMA2x2_AXIS_LSB_NEW_DATA 0x01 /* STATUS ADDRESS DEFINITIONS */ -#define BMA2x2_STAT1_ADDR 0x09 -#define BMA2x2_STAT2_ADDR 0x0A -#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B -#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C -#define BMA2x2_STAT_FIFO_ADDR 0x0E -#define BMA2x2_RANGE_SELECT_ADDR 0x0F -#define BMA2x2_RANGE_SELECT_MSK 0x0F -#define BMA2x2_RANGE_2G 3 -#define BMA2x2_RANGE_4G 5 -#define BMA2x2_RANGE_8G 8 -#define BMA2x2_RANGE_16G 12 - -#define BMA2x2_RANGE_TO_REG(_range) \ +#define BMA2x2_STAT1_ADDR 0x09 +#define BMA2x2_STAT2_ADDR 0x0A +#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B +#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C +#define BMA2x2_STAT_FIFO_ADDR 0x0E +#define BMA2x2_RANGE_SELECT_ADDR 0x0F +#define BMA2x2_RANGE_SELECT_MSK 0x0F +#define BMA2x2_RANGE_2G 3 +#define BMA2x2_RANGE_4G 5 +#define BMA2x2_RANGE_8G 8 +#define BMA2x2_RANGE_16G 12 + +#define BMA2x2_RANGE_TO_REG(_range) \ ((_range) < 8 ? BMA2x2_RANGE_2G + ((_range) / 4) * 2 : \ BMA2x2_RANGE_8G + ((_range) / 16) * 4) -#define BMA2x2_REG_TO_RANGE(_reg) \ - ((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg) - BMA2x2_RANGE_2G : \ - 8 + ((_reg) - BMA2x2_RANGE_8G) * 2) - -#define BMA2x2_BW_SELECT_ADDR 0x10 -#define BMA2x2_BW_MSK 0x1F -#define BMA2x2_BW_7_81HZ 0x08 /* LowPass 7.8125HZ */ -#define BMA2x2_BW_15_63HZ 0x09 /* LowPass 15.625HZ */ -#define BMA2x2_BW_31_25HZ 0x0A /* LowPass 31.25HZ */ -#define BMA2x2_BW_62_50HZ 0x0B /* LowPass 62.50HZ */ -#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */ -#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */ -#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */ -#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */ +#define BMA2x2_REG_TO_RANGE(_reg) \ + ((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg)-BMA2x2_RANGE_2G : \ + 8 + ((_reg)-BMA2x2_RANGE_8G) * 2) + +#define BMA2x2_BW_SELECT_ADDR 0x10 +#define BMA2x2_BW_MSK 0x1F +#define BMA2x2_BW_7_81HZ 0x08 /* LowPass 7.8125HZ */ +#define BMA2x2_BW_15_63HZ 0x09 /* LowPass 15.625HZ */ +#define BMA2x2_BW_31_25HZ 0x0A /* LowPass 31.25HZ */ +#define BMA2x2_BW_62_50HZ 0x0B /* LowPass 62.50HZ */ +#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */ +#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */ +#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */ +#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */ /* Do not use BW lower than 7813, because __fls cannot be call for 0 */ -#define BMA2x2_BW_TO_REG(_bw) \ - ((_bw) < 125000 ? \ - BMA2x2_BW_7_81HZ + __fls(((_bw) * 10) / 78125) : \ - BMA2x2_BW_125HZ + __fls((_bw) / 125000)) - -#define BMA2x2_REG_TO_BW(_reg) \ - ((_reg) < BMA2x2_BW_125HZ ? \ - (78125 << ((_reg) - BMA2x2_BW_7_81HZ)) / 10 : \ - 125000 << ((_reg) - BMA2x2_BW_125HZ)) - -#define BMA2x2_MODE_CTRL_ADDR 0x11 -#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12 -#define BMA2x2_DATA_CTRL_ADDR 0x13 -#define BMA2x2_DATA_HIGH_BW 0x80 -#define BMA2x2_DATA_SHADOW_DIS 0x40 -#define BMA2x2_RST_ADDR 0x14 -#define BMA2x2_CMD_SOFT_RESET 0xb6 +#define BMA2x2_BW_TO_REG(_bw) \ + ((_bw) < 125000 ? BMA2x2_BW_7_81HZ + __fls(((_bw)*10) / 78125) : \ + BMA2x2_BW_125HZ + __fls((_bw) / 125000)) + +#define BMA2x2_REG_TO_BW(_reg) \ + ((_reg) < BMA2x2_BW_125HZ ? \ + (78125 << ((_reg)-BMA2x2_BW_7_81HZ)) / 10 : \ + 125000 << ((_reg)-BMA2x2_BW_125HZ)) + +#define BMA2x2_MODE_CTRL_ADDR 0x11 +#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12 +#define BMA2x2_DATA_CTRL_ADDR 0x13 +#define BMA2x2_DATA_HIGH_BW 0x80 +#define BMA2x2_DATA_SHADOW_DIS 0x40 +#define BMA2x2_RST_ADDR 0x14 +#define BMA2x2_CMD_SOFT_RESET 0xb6 /* INTERRUPT ADDRESS DEFINITIONS */ -#define BMA2x2_INTR_ENABLE1_ADDR 0x16 -#define BMA2x2_INTR_ENABLE2_ADDR 0x17 -#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18 -#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19 -#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A -#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B -#define BMA2x2_INTR_SOURCE_ADDR 0x1E -#define BMA2x2_INTR_SET_ADDR 0x20 -#define BMA2x2_INTR_CTRL_ADDR 0x21 -#define BMA2x2_INTR_CTRL_RST_INT 0x80 +#define BMA2x2_INTR_ENABLE1_ADDR 0x16 +#define BMA2x2_INTR_ENABLE2_ADDR 0x17 +#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18 +#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19 +#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A +#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B +#define BMA2x2_INTR_SOURCE_ADDR 0x1E +#define BMA2x2_INTR_SET_ADDR 0x20 +#define BMA2x2_INTR_CTRL_ADDR 0x21 +#define BMA2x2_INTR_CTRL_RST_INT 0x80 /* FEATURE ADDRESS DEFINITIONS */ -#define BMA2x2_LOW_DURN_ADDR 0x22 -#define BMA2x2_LOW_THRES_ADDR 0x23 -#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24 -#define BMA2x2_HIGH_DURN_ADDR 0x25 -#define BMA2x2_HIGH_THRES_ADDR 0x26 -#define BMA2x2_SLOPE_DURN_ADDR 0x27 -#define BMA2x2_SLOPE_THRES_ADDR 0x28 -#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29 -#define BMA2x2_TAP_PARAM_ADDR 0x2A -#define BMA2x2_TAP_THRES_ADDR 0x2B -#define BMA2x2_ORIENT_PARAM_ADDR 0x2C -#define BMA2x2_THETA_BLOCK_ADDR 0x2D -#define BMA2x2_THETA_FLAT_ADDR 0x2E -#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F -#define BMA2x2_SELFTEST_ADDR 0x32 -#define BMA2x2_EEPROM_CTRL_ADDR 0x33 -#define BMA2x2_EEPROM_REMAIN_OFF 4 -#define BMA2x2_EEPROM_REMAIN_MSK 0xF0 -#define BMA2x2_EEPROM_LOAD 0x08 -#define BMA2x2_EEPROM_RDY 0x04 -#define BMA2x2_EEPROM_PROG 0x02 -#define BMA2x2_EEPROM_PROG_EN 0x01 -#define BMA2x2_SERIAL_CTRL_ADDR 0x34 +#define BMA2x2_LOW_DURN_ADDR 0x22 +#define BMA2x2_LOW_THRES_ADDR 0x23 +#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24 +#define BMA2x2_HIGH_DURN_ADDR 0x25 +#define BMA2x2_HIGH_THRES_ADDR 0x26 +#define BMA2x2_SLOPE_DURN_ADDR 0x27 +#define BMA2x2_SLOPE_THRES_ADDR 0x28 +#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29 +#define BMA2x2_TAP_PARAM_ADDR 0x2A +#define BMA2x2_TAP_THRES_ADDR 0x2B +#define BMA2x2_ORIENT_PARAM_ADDR 0x2C +#define BMA2x2_THETA_BLOCK_ADDR 0x2D +#define BMA2x2_THETA_FLAT_ADDR 0x2E +#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F +#define BMA2x2_SELFTEST_ADDR 0x32 +#define BMA2x2_EEPROM_CTRL_ADDR 0x33 +#define BMA2x2_EEPROM_REMAIN_OFF 4 +#define BMA2x2_EEPROM_REMAIN_MSK 0xF0 +#define BMA2x2_EEPROM_LOAD 0x08 +#define BMA2x2_EEPROM_RDY 0x04 +#define BMA2x2_EEPROM_PROG 0x02 +#define BMA2x2_EEPROM_PROG_EN 0x01 +#define BMA2x2_SERIAL_CTRL_ADDR 0x34 /* OFFSET ADDRESS DEFINITIONS */ -#define BMA2x2_OFFSET_CTRL_ADDR 0x36 -#define BMA2x2_OFFSET_RESET 0x80 -#define BMA2x2_OFFSET_TRIGGER_OFF 5 -#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF) -#define BMA2x2_OFFSET_CAL_READY 0x10 -#define BMA2x2_OFFSET_CAL_SLOW_X 0x04 -#define BMA2x2_OFFSET_CAL_SLOW_Y 0x02 -#define BMA2x2_OFFSET_CAL_SLOW_Z 0x01 - -#define BMA2x2_OFC_SETTING_ADDR 0x37 -#define BMA2x2_OFC_TARGET_AXIS_OFF 1 -#define BMA2x2_OFC_TARGET_AXIS_LEN 2 +#define BMA2x2_OFFSET_CTRL_ADDR 0x36 +#define BMA2x2_OFFSET_RESET 0x80 +#define BMA2x2_OFFSET_TRIGGER_OFF 5 +#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF) +#define BMA2x2_OFFSET_CAL_READY 0x10 +#define BMA2x2_OFFSET_CAL_SLOW_X 0x04 +#define BMA2x2_OFFSET_CAL_SLOW_Y 0x02 +#define BMA2x2_OFFSET_CAL_SLOW_Z 0x01 + +#define BMA2x2_OFC_SETTING_ADDR 0x37 +#define BMA2x2_OFC_TARGET_AXIS_OFF 1 +#define BMA2x2_OFC_TARGET_AXIS_LEN 2 #define BMA2x2_OFC_TARGET_AXIS(_axis) \ (BMA2x2_OFC_TARGET_AXIS_LEN * (_axis) + BMA2x2_OFC_TARGET_AXIS_OFF) -#define BMA2x2_OFC_TARGET_0G 0 -#define BMA2x2_OFC_TARGET_PLUS_1G 1 -#define BMA2x2_OFC_TARGET_MINUS_1G 2 +#define BMA2x2_OFC_TARGET_0G 0 +#define BMA2x2_OFC_TARGET_PLUS_1G 1 +#define BMA2x2_OFC_TARGET_MINUS_1G 2 -#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38 -#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39 -#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A +#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38 +#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39 +#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A /* GP ADDRESS DEFINITIONS */ -#define BMA2x2_GP0_ADDR 0x3B -#define BMA2x2_GP1_ADDR 0x3C +#define BMA2x2_GP0_ADDR 0x3B +#define BMA2x2_GP1_ADDR 0x3C /* FIFO ADDRESS DEFINITIONS */ -#define BMA2x2_FIFO_MODE_ADDR 0x3E -#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F -#define BMA2x2_FIFO_WML_TRIG 0x30 +#define BMA2x2_FIFO_MODE_ADDR 0x3E +#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F +#define BMA2x2_FIFO_WML_TRIG 0x30 /* Sensor resolution in number of bits. This sensor has fixed resolution. */ -#define BMA2x2_RESOLUTION 12 +#define BMA2x2_RESOLUTION 12 #endif /* __CROS_EC_ACCEL_BMA2x2_H */ diff --git a/include/driver/accel_bma2x2_public.h b/include/driver/accel_bma2x2_public.h index 731fcebbc9..04d7a33e4c 100644 --- a/include/driver/accel_bma2x2_public.h +++ b/include/driver/accel_bma2x2_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,27 +14,27 @@ extern const struct accelgyro_drv bma2x2_accel_drv; /* I2C ADDRESS DEFINITIONS */ /* The following definition of I2C address is used for the following sensors -* BMA253 -* BMA255 -* BMA355 -* BMA280 -* BMA282 -* BMA223 -* BMA254 -* BMA284 -* BMA250E -* BMA222E -*/ -#define BMA2x2_I2C_ADDR1_FLAGS 0x18 -#define BMA2x2_I2C_ADDR2_FLAGS 0x19 + * BMA253 + * BMA255 + * BMA355 + * BMA280 + * BMA282 + * BMA223 + * BMA254 + * BMA284 + * BMA250E + * BMA222E + */ +#define BMA2x2_I2C_ADDR1_FLAGS 0x18 +#define BMA2x2_I2C_ADDR2_FLAGS 0x19 /* The following definition of I2C address is used for the following sensors -* BMC150 -* BMC056 -* BMC156 -*/ -#define BMA2x2_I2C_ADDR3_FLAGS 0x10 -#define BMA2x2_I2C_ADDR4_FLAGS 0x11 + * BMC150 + * BMC056 + * BMC156 + */ +#define BMA2x2_I2C_ADDR3_FLAGS 0x10 +#define BMA2x2_I2C_ADDR4_FLAGS 0x11 /* * Min and Max sampling frequency in mHz. @@ -43,8 +43,7 @@ extern const struct accelgyro_drv bma2x2_accel_drv; * (see CONFIG_MOTION_MIN_SENSE_WAIT_TIME), we may read too early when * other sensors are active. */ -#define BMA255_ACCEL_MIN_FREQ 7810 -#define BMA255_ACCEL_MAX_FREQ \ - MOTION_MAX_SENSOR_FREQUENCY(125000, 15625) +#define BMA255_ACCEL_MIN_FREQ 7810 +#define BMA255_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(125000, 15625) #endif /* CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H */ diff --git a/include/driver/accel_lis2dw12_public.h b/include/driver/accel_lis2dw12_public.h index 751df15f86..5596e6ba6a 100644 --- a/include/driver/accel_lis2dw12_public.h +++ b/include/driver/accel_lis2dw12_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,18 +17,18 @@ extern const struct accelgyro_drv lis2dw12_drv; * 7-bit address is 011000Xb. Where 'X' is determined * by the voltage on the ADDR pin. */ -#define LIS2DW12_ADDR0 0x18 -#define LIS2DW12_ADDR1 0x19 +#define LIS2DW12_ADDR0 0x18 +#define LIS2DW12_ADDR1 0x19 -#define LIS2DWL_ADDR0_FLAGS 0x18 -#define LIS2DWL_ADDR1_FLAGS 0x19 +#define LIS2DWL_ADDR0_FLAGS 0x18 +#define LIS2DWL_ADDR1_FLAGS 0x19 -#define LIS2DW12_EN_BIT 0x01 -#define LIS2DW12_DIS_BIT 0x00 +#define LIS2DW12_EN_BIT 0x01 +#define LIS2DW12_DIS_BIT 0x00 /* Absolute Acc rate. */ -#define LIS2DW12_ODR_MIN_VAL 12500 -#define LIS2DW12_ODR_MAX_VAL \ +#define LIS2DW12_ODR_MIN_VAL 12500 +#define LIS2DW12_ODR_MAX_VAL \ MOTION_MAX_SENSOR_FREQUENCY(1600000, LIS2DW12_ODR_MIN_VAL) void lis2dw12_interrupt(enum gpio_signal signal); diff --git a/include/driver/accelgyro_bmi160.h b/include/driver/accelgyro_bmi160.h index bd5637c2ba..8c6310e65b 100644 --- a/include/driver/accelgyro_bmi160.h +++ b/include/driver/accelgyro_bmi160.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,253 +12,251 @@ #include "driver/accelgyro_bmi160_public.h" #include "mag_bmm150.h" -#define BMI160_CHIP_ID 0x00 -#define BMI160_CHIP_ID_MAJOR 0xd1 -#define BMI168_CHIP_ID_MAJOR 0xd2 +#define BMI160_CHIP_ID 0x00 +#define BMI160_CHIP_ID_MAJOR 0xd1 +#define BMI168_CHIP_ID_MAJOR 0xd2 -#define BMI160_SPEC_ACC_STARTUP_TIME_MS 10 -#define BMI160_SPEC_GYR_STARTUP_TIME_MS 80 -#define BMI160_SPEC_MAG_STARTUP_TIME_MS 60 +#define BMI160_SPEC_ACC_STARTUP_TIME_MS 10 +#define BMI160_SPEC_GYR_STARTUP_TIME_MS 80 +#define BMI160_SPEC_MAG_STARTUP_TIME_MS 60 - -#define BMI160_ERR_REG 0x02 -#define BMI160_PMU_STATUS 0x03 -#define BMI160_PMU_MAG_OFFSET 0 -#define BMI160_PMU_GYR_OFFSET 2 -#define BMI160_PMU_ACC_OFFSET 4 +#define BMI160_ERR_REG 0x02 +#define BMI160_PMU_STATUS 0x03 +#define BMI160_PMU_MAG_OFFSET 0 +#define BMI160_PMU_GYR_OFFSET 2 +#define BMI160_PMU_ACC_OFFSET 4 #define BMI160_PMU_SENSOR_STATUS(_sensor_type, _val) \ (((_val) >> (4 - 2 * (_sensor_type))) & 0x3) -#define BMI160_PMU_SUSPEND 0 -#define BMI160_PMU_NORMAL 1 -#define BMI160_PMU_LOW_POWER 2 -#define BMI160_PMU_FAST_STARTUP 3 - -#define BMI160_MAG_X_L_G 0x04 -#define BMI160_MAG_X_H_G 0x05 -#define BMI160_MAG_Y_L_G 0x06 -#define BMI160_MAG_Y_H_G 0x07 -#define BMI160_MAG_Z_L_G 0x08 -#define BMI160_MAG_Z_H_G 0x09 -#define BMI160_RHALL_L_G 0x0a -#define BMI160_RHALL_H_G 0x0b -#define BMI160_GYR_X_L_G 0x0c -#define BMI160_GYR_X_H_G 0x0d -#define BMI160_GYR_Y_L_G 0x0e -#define BMI160_GYR_Y_H_G 0x0f -#define BMI160_GYR_Z_L_G 0x10 -#define BMI160_GYR_Z_H_G 0x11 -#define BMI160_ACC_X_L_G 0x12 -#define BMI160_ACC_X_H_G 0x13 -#define BMI160_ACC_Y_L_G 0x14 -#define BMI160_ACC_Y_H_G 0x15 -#define BMI160_ACC_Z_L_G 0x16 -#define BMI160_ACC_Z_H_G 0x17 - -#define BMI160_SENSORTIME_0 0x18 -#define BMI160_SENSORTIME_1 0x19 -#define BMI160_SENSORTIME_2 0x1a - -#define BMI160_STATUS 0x1b -#define BMI160_POR_DETECTED BIT(0) -#define BMI160_GYR_SLF_TST BIT(1) -#define BMI160_MAG_MAN_OP BIT(2) -#define BMI160_FOC_RDY BIT(3) -#define BMI160_NVM_RDY BIT(4) -#define BMI160_DRDY_MAG BIT(5) -#define BMI160_DRDY_GYR BIT(6) -#define BMI160_DRDY_ACC BIT(7) -#define BMI160_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) +#define BMI160_PMU_SUSPEND 0 +#define BMI160_PMU_NORMAL 1 +#define BMI160_PMU_LOW_POWER 2 +#define BMI160_PMU_FAST_STARTUP 3 + +#define BMI160_MAG_X_L_G 0x04 +#define BMI160_MAG_X_H_G 0x05 +#define BMI160_MAG_Y_L_G 0x06 +#define BMI160_MAG_Y_H_G 0x07 +#define BMI160_MAG_Z_L_G 0x08 +#define BMI160_MAG_Z_H_G 0x09 +#define BMI160_RHALL_L_G 0x0a +#define BMI160_RHALL_H_G 0x0b +#define BMI160_GYR_X_L_G 0x0c +#define BMI160_GYR_X_H_G 0x0d +#define BMI160_GYR_Y_L_G 0x0e +#define BMI160_GYR_Y_H_G 0x0f +#define BMI160_GYR_Z_L_G 0x10 +#define BMI160_GYR_Z_H_G 0x11 +#define BMI160_ACC_X_L_G 0x12 +#define BMI160_ACC_X_H_G 0x13 +#define BMI160_ACC_Y_L_G 0x14 +#define BMI160_ACC_Y_H_G 0x15 +#define BMI160_ACC_Z_L_G 0x16 +#define BMI160_ACC_Z_H_G 0x17 + +#define BMI160_SENSORTIME_0 0x18 +#define BMI160_SENSORTIME_1 0x19 +#define BMI160_SENSORTIME_2 0x1a + +#define BMI160_STATUS 0x1b +#define BMI160_POR_DETECTED BIT(0) +#define BMI160_GYR_SLF_TST BIT(1) +#define BMI160_MAG_MAN_OP BIT(2) +#define BMI160_FOC_RDY BIT(3) +#define BMI160_NVM_RDY BIT(4) +#define BMI160_DRDY_MAG BIT(5) +#define BMI160_DRDY_GYR BIT(6) +#define BMI160_DRDY_ACC BIT(7) +#define BMI160_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) /* first 2 bytes are the interrupt reasons, next 2 some qualifier */ -#define BMI160_INT_STATUS_0 0x1c -#define BMI160_STEP_INT BIT(0) -#define BMI160_SIGMOT_INT BIT(1) -#define BMI160_ANYM_INT BIT(2) -#define BMI160_PMU_TRIGGER_INT BIT(3) -#define BMI160_D_TAP_INT BIT(4) -#define BMI160_S_TAP_INT BIT(5) -#define BMI160_ORIENT_INT BIT(6) -#define BMI160_FLAT_INT BIT(7) -#define BMI160_ORIENT_XY_MASK 0x30 -#define BMI160_ORIENT_PORTRAIT (0 << 4) -#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4) -#define BMI160_ORIENT_LANDSCAPE (2 << 4) -#define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4) - - -#define BMI160_INT_STATUS_1 0x1d -#define BMI160_HIGHG_INT (1 << (2 + 8)) -#define BMI160_LOWG_INT (1 << (3 + 8)) -#define BMI160_DRDY_INT (1 << (4 + 8)) -#define BMI160_FFULL_INT (1 << (5 + 8)) -#define BMI160_FWM_INT (1 << (6 + 8)) -#define BMI160_NOMO_INT (1 << (7 + 8)) - -#define BMI160_INT_MASK 0xFFFF - -#define BMI160_INT_STATUS_2 0x1e -#define BMI160_INT_STATUS_3 0x1f -#define BMI160_FIRST_X (1 << (0 + 16)) -#define BMI160_FIRST_Y (1 << (1 + 16)) -#define BMI160_FIRST_Z (1 << (2 + 16)) -#define BMI160_SIGN (1 << (3 + 16)) -#define BMI160_ANYM_OFFSET 0 -#define BMI160_TAP_OFFSET 4 -#define BMI160_HIGH_OFFSET 8 +#define BMI160_INT_STATUS_0 0x1c +#define BMI160_STEP_INT BIT(0) +#define BMI160_SIGMOT_INT BIT(1) +#define BMI160_ANYM_INT BIT(2) +#define BMI160_PMU_TRIGGER_INT BIT(3) +#define BMI160_D_TAP_INT BIT(4) +#define BMI160_S_TAP_INT BIT(5) +#define BMI160_ORIENT_INT BIT(6) +#define BMI160_FLAT_INT BIT(7) +#define BMI160_ORIENT_XY_MASK 0x30 +#define BMI160_ORIENT_PORTRAIT (0 << 4) +#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4) +#define BMI160_ORIENT_LANDSCAPE (2 << 4) +#define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4) + +#define BMI160_INT_STATUS_1 0x1d +#define BMI160_HIGHG_INT (1 << (2 + 8)) +#define BMI160_LOWG_INT (1 << (3 + 8)) +#define BMI160_DRDY_INT (1 << (4 + 8)) +#define BMI160_FFULL_INT (1 << (5 + 8)) +#define BMI160_FWM_INT (1 << (6 + 8)) +#define BMI160_NOMO_INT (1 << (7 + 8)) + +#define BMI160_INT_MASK 0xFFFF + +#define BMI160_INT_STATUS_2 0x1e +#define BMI160_INT_STATUS_3 0x1f +#define BMI160_FIRST_X (1 << (0 + 16)) +#define BMI160_FIRST_Y (1 << (1 + 16)) +#define BMI160_FIRST_Z (1 << (2 + 16)) +#define BMI160_SIGN (1 << (3 + 16)) +#define BMI160_ANYM_OFFSET 0 +#define BMI160_TAP_OFFSET 4 +#define BMI160_HIGH_OFFSET 8 #define BMI160_INT_INFO(_type, _data) \ -(CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET)) - -#define BMI160_ORIENT_Z (1 << (6 + 24)) -#define BMI160_FLAT (1 << (7 + 24)) - -#define BMI160_TEMPERATURE_0 0x20 -#define BMI160_TEMPERATURE_1 0x21 - - -#define BMI160_FIFO_LENGTH_0 0x22 -#define BMI160_FIFO_LENGTH_1 0x23 -#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1) -#define BMI160_FIFO_DATA 0x24 - -#define BMI160_ACC_CONF 0x40 -#define BMI160_ACC_BW_OFFSET 4 -#define BMI160_ACC_BW_MASK (0x7 << BMI160_ACC_BW_OFFSET) - -#define BMI160_ACC_RANGE 0x41 -#define BMI160_GSEL_2G 0x03 -#define BMI160_GSEL_4G 0x05 -#define BMI160_GSEL_8G 0x08 -#define BMI160_GSEL_16G 0x0c - -#define BMI160_GYR_CONF 0x42 -#define BMI160_GYR_BW_OFFSET 4 -#define BMI160_GYR_BW_MASK (0x3 << BMI160_GYR_BW_OFFSET) - -#define BMI160_GYR_RANGE 0x43 -#define BMI160_DPS_SEL_2000 0x00 -#define BMI160_DPS_SEL_1000 0x01 -#define BMI160_DPS_SEL_500 0x02 -#define BMI160_DPS_SEL_250 0x03 -#define BMI160_DPS_SEL_125 0x04 - -#define BMI160_MAG_CONF 0x44 - -#define BMI160_FIFO_DOWNS 0x45 -#define BMI160_FIFO_CONFIG_0 0x46 -#define BMI160_FIFO_CONFIG_1 0x47 -#define BMI160_FIFO_TAG_TIME_EN BIT(1) -#define BMI160_FIFO_TAG_INT2_EN BIT(2) -#define BMI160_FIFO_TAG_INT1_EN BIT(3) -#define BMI160_FIFO_HEADER_EN BIT(4) -#define BMI160_FIFO_MAG_EN BIT(5) -#define BMI160_FIFO_ACC_EN BIT(6) -#define BMI160_FIFO_GYR_EN BIT(7) -#define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN) -#define BMI160_FIFO_SENSOR_EN(_sensor) \ - ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI160_FIFO_ACC_EN : \ - ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \ - BMI160_FIFO_MAG_EN)) - -#define BMI160_MAG_IF_0 0x4b + (CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET)) + +#define BMI160_ORIENT_Z (1 << (6 + 24)) +#define BMI160_FLAT (1 << (7 + 24)) + +#define BMI160_TEMPERATURE_0 0x20 +#define BMI160_TEMPERATURE_1 0x21 + +#define BMI160_FIFO_LENGTH_0 0x22 +#define BMI160_FIFO_LENGTH_1 0x23 +#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1) +#define BMI160_FIFO_DATA 0x24 + +#define BMI160_ACC_CONF 0x40 +#define BMI160_ACC_BW_OFFSET 4 +#define BMI160_ACC_BW_MASK (0x7 << BMI160_ACC_BW_OFFSET) + +#define BMI160_ACC_RANGE 0x41 +#define BMI160_GSEL_2G 0x03 +#define BMI160_GSEL_4G 0x05 +#define BMI160_GSEL_8G 0x08 +#define BMI160_GSEL_16G 0x0c + +#define BMI160_GYR_CONF 0x42 +#define BMI160_GYR_BW_OFFSET 4 +#define BMI160_GYR_BW_MASK (0x3 << BMI160_GYR_BW_OFFSET) + +#define BMI160_GYR_RANGE 0x43 +#define BMI160_DPS_SEL_2000 0x00 +#define BMI160_DPS_SEL_1000 0x01 +#define BMI160_DPS_SEL_500 0x02 +#define BMI160_DPS_SEL_250 0x03 +#define BMI160_DPS_SEL_125 0x04 + +#define BMI160_MAG_CONF 0x44 + +#define BMI160_FIFO_DOWNS 0x45 +#define BMI160_FIFO_CONFIG_0 0x46 +#define BMI160_FIFO_CONFIG_1 0x47 +#define BMI160_FIFO_TAG_TIME_EN BIT(1) +#define BMI160_FIFO_TAG_INT2_EN BIT(2) +#define BMI160_FIFO_TAG_INT1_EN BIT(3) +#define BMI160_FIFO_HEADER_EN BIT(4) +#define BMI160_FIFO_MAG_EN BIT(5) +#define BMI160_FIFO_ACC_EN BIT(6) +#define BMI160_FIFO_GYR_EN BIT(7) +#define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN) +#define BMI160_FIFO_SENSOR_EN(_sensor) \ + ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? \ + BMI160_FIFO_ACC_EN : \ + ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \ + BMI160_FIFO_MAG_EN)) + +#define BMI160_MAG_IF_0 0x4b #define BMI160_MAG_I2C_ADDRESS BMI160_MAG_IF_0 -#define BMI160_MAG_IF_1 0x4c +#define BMI160_MAG_IF_1 0x4c #define BMI160_MAG_I2C_CONTROL BMI160_MAG_IF_1 #define BMI160_MAG_READ_BURST_MASK 3 -#define BMI160_MAG_READ_BURST_1 0 -#define BMI160_MAG_READ_BURST_2 1 -#define BMI160_MAG_READ_BURST_6 2 -#define BMI160_MAG_READ_BURST_8 3 -#define BMI160_MAG_OFFSET_OFF 3 -#define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF) -#define BMI160_MAG_MANUAL_EN BIT(7) - -#define BMI160_MAG_IF_2 0x4d -#define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2 -#define BMI160_MAG_IF_3 0x4e -#define BMI160_MAG_I2C_WRITE_ADDR BMI160_MAG_IF_3 -#define BMI160_MAG_IF_4 0x4f -#define BMI160_MAG_I2C_WRITE_DATA BMI160_MAG_IF_4 -#define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G - -#define BMI160_INT_EN_0 0x50 -#define BMI160_INT_ANYMO_X_EN BIT(0) -#define BMI160_INT_ANYMO_Y_EN BIT(1) -#define BMI160_INT_ANYMO_Z_EN BIT(2) -#define BMI160_INT_D_TAP_EN BIT(4) -#define BMI160_INT_S_TAP_EN BIT(5) -#define BMI160_INT_ORIENT_EN BIT(6) -#define BMI160_INT_FLAT_EN BIT(7) -#define BMI160_INT_EN_1 0x51 -#define BMI160_INT_HIGHG_X_EN BIT(0) -#define BMI160_INT_HIGHG_Y_EN BIT(1) -#define BMI160_INT_HIGHG_Z_EN BIT(2) -#define BMI160_INT_LOW_EN BIT(3) -#define BMI160_INT_DRDY_EN BIT(4) -#define BMI160_INT_FFUL_EN BIT(5) -#define BMI160_INT_FWM_EN BIT(6) -#define BMI160_INT_EN_2 0x52 -#define BMI160_INT_NOMOX_EN BIT(0) -#define BMI160_INT_NOMOY_EN BIT(1) -#define BMI160_INT_NOMOZ_EN BIT(2) -#define BMI160_INT_STEP_DET_EN BIT(3) - -#define BMI160_INT_OUT_CTRL 0x53 -#define BMI160_INT_EDGE_CTRL BIT(0) -#define BMI160_INT_LVL_CTRL BIT(1) -#define BMI160_INT_OD BIT(2) -#define BMI160_INT_OUTPUT_EN BIT(3) -#define BMI160_INT1_CTRL_OFFSET 0 -#define BMI160_INT2_CTRL_OFFSET 4 +#define BMI160_MAG_READ_BURST_1 0 +#define BMI160_MAG_READ_BURST_2 1 +#define BMI160_MAG_READ_BURST_6 2 +#define BMI160_MAG_READ_BURST_8 3 +#define BMI160_MAG_OFFSET_OFF 3 +#define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF) +#define BMI160_MAG_MANUAL_EN BIT(7) + +#define BMI160_MAG_IF_2 0x4d +#define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2 +#define BMI160_MAG_IF_3 0x4e +#define BMI160_MAG_I2C_WRITE_ADDR BMI160_MAG_IF_3 +#define BMI160_MAG_IF_4 0x4f +#define BMI160_MAG_I2C_WRITE_DATA BMI160_MAG_IF_4 +#define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G + +#define BMI160_INT_EN_0 0x50 +#define BMI160_INT_ANYMO_X_EN BIT(0) +#define BMI160_INT_ANYMO_Y_EN BIT(1) +#define BMI160_INT_ANYMO_Z_EN BIT(2) +#define BMI160_INT_D_TAP_EN BIT(4) +#define BMI160_INT_S_TAP_EN BIT(5) +#define BMI160_INT_ORIENT_EN BIT(6) +#define BMI160_INT_FLAT_EN BIT(7) +#define BMI160_INT_EN_1 0x51 +#define BMI160_INT_HIGHG_X_EN BIT(0) +#define BMI160_INT_HIGHG_Y_EN BIT(1) +#define BMI160_INT_HIGHG_Z_EN BIT(2) +#define BMI160_INT_LOW_EN BIT(3) +#define BMI160_INT_DRDY_EN BIT(4) +#define BMI160_INT_FFUL_EN BIT(5) +#define BMI160_INT_FWM_EN BIT(6) +#define BMI160_INT_EN_2 0x52 +#define BMI160_INT_NOMOX_EN BIT(0) +#define BMI160_INT_NOMOY_EN BIT(1) +#define BMI160_INT_NOMOZ_EN BIT(2) +#define BMI160_INT_STEP_DET_EN BIT(3) + +#define BMI160_INT_OUT_CTRL 0x53 +#define BMI160_INT_EDGE_CTRL BIT(0) +#define BMI160_INT_LVL_CTRL BIT(1) +#define BMI160_INT_OD BIT(2) +#define BMI160_INT_OUTPUT_EN BIT(3) +#define BMI160_INT1_CTRL_OFFSET 0 +#define BMI160_INT2_CTRL_OFFSET 4 #define BMI160_INT_CTRL(_i, _bit) \ -(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET)) - -#define BMI160_INT_LATCH 0x54 -#define BMI160_INT1_INPUT_EN BIT(4) -#define BMI160_INT2_INPUT_EN BIT(5) -#define BMI160_LATCH_MASK 0xf -#define BMI160_LATCH_NONE 0 -#define BMI160_LATCH_5MS 5 -#define BMI160_LATCH_FOREVER 0xf - -#define BMI160_INT_MAP_0 0x55 -#define BMI160_INT_LOWG_STEP BIT(0) -#define BMI160_INT_HIGHG BIT(1) -#define BMI160_INT_ANYMOTION BIT(2) -#define BMI160_INT_NOMOTION BIT(3) -#define BMI160_INT_D_TAP BIT(4) -#define BMI160_INT_S_TAP BIT(5) -#define BMI160_INT_ORIENT BIT(6) -#define BMI160_INT_FLAT BIT(7) - -#define BMI160_INT_MAP_1 0x56 -#define BMI160_INT_PMU_TRIG BIT(0) -#define BMI160_INT_FFULL BIT(1) -#define BMI160_INT_FWM BIT(2) -#define BMI160_INT_DRDY BIT(3) -#define BMI160_INT1_MAP_OFFSET 4 -#define BMI160_INT2_MAP_OFFSET 0 + (CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET)) + +#define BMI160_INT_LATCH 0x54 +#define BMI160_INT1_INPUT_EN BIT(4) +#define BMI160_INT2_INPUT_EN BIT(5) +#define BMI160_LATCH_MASK 0xf +#define BMI160_LATCH_NONE 0 +#define BMI160_LATCH_5MS 5 +#define BMI160_LATCH_FOREVER 0xf + +#define BMI160_INT_MAP_0 0x55 +#define BMI160_INT_LOWG_STEP BIT(0) +#define BMI160_INT_HIGHG BIT(1) +#define BMI160_INT_ANYMOTION BIT(2) +#define BMI160_INT_NOMOTION BIT(3) +#define BMI160_INT_D_TAP BIT(4) +#define BMI160_INT_S_TAP BIT(5) +#define BMI160_INT_ORIENT BIT(6) +#define BMI160_INT_FLAT BIT(7) + +#define BMI160_INT_MAP_1 0x56 +#define BMI160_INT_PMU_TRIG BIT(0) +#define BMI160_INT_FFULL BIT(1) +#define BMI160_INT_FWM BIT(2) +#define BMI160_INT_DRDY BIT(3) +#define BMI160_INT1_MAP_OFFSET 4 +#define BMI160_INT2_MAP_OFFSET 0 #define BMI160_INT_MAP(_i, _bit) \ -(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET)) -#define BMI160_INT_FIFO_MAP BMI160_INT_MAP_1 + (CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET)) +#define BMI160_INT_FIFO_MAP BMI160_INT_MAP_1 -#define BMI160_INT_MAP_2 0x57 +#define BMI160_INT_MAP_2 0x57 -#define BMI160_INT_MAP_INT_1 BMI160_INT_MAP_0 -#define BMI160_INT_MAP_INT_2 BMI160_INT_MAP_2 -#define BMI160_INT_MAP_REG(_i) CONCAT2(BMI160_INT_MAP_INT_, _i) +#define BMI160_INT_MAP_INT_1 BMI160_INT_MAP_0 +#define BMI160_INT_MAP_INT_2 BMI160_INT_MAP_2 +#define BMI160_INT_MAP_REG(_i) CONCAT2(BMI160_INT_MAP_INT_, _i) -#define BMI160_INT_DATA_0 0x58 -#define BMI160_INT_DATA_1 0x59 +#define BMI160_INT_DATA_0 0x58 +#define BMI160_INT_DATA_1 0x59 -#define BMI160_INT_LOW_HIGH_0 0x5a -#define BMI160_INT_LOW_HIGH_1 0x5b -#define BMI160_INT_LOW_HIGH_2 0x5c -#define BMI160_INT_LOW_HIGH_3 0x5d -#define BMI160_INT_LOW_HIGH_4 0x5e +#define BMI160_INT_LOW_HIGH_0 0x5a +#define BMI160_INT_LOW_HIGH_1 0x5b +#define BMI160_INT_LOW_HIGH_2 0x5c +#define BMI160_INT_LOW_HIGH_3 0x5d +#define BMI160_INT_LOW_HIGH_4 0x5e -#define BMI160_INT_MOTION_0 0x5f -#define BMI160_INT_MOTION_1 0x60 +#define BMI160_INT_MOTION_0 0x5f +#define BMI160_INT_MOTION_1 0x60 /* * The formula is defined in 2.11.25 (any motion interrupt [1]). * @@ -268,11 +266,11 @@ * x = a * 1000 / range * 1953 */ #define BMI160_MOTION_TH(_s, _mg) \ - (MIN(((_mg) * 1000) / ((_s)->current_range * 1953), 0xff)) -#define BMI160_INT_MOTION_2 0x61 -#define BMI160_INT_MOTION_3 0x62 -#define BMI160_MOTION_NO_MOT_SEL BIT(0) -#define BMI160_MOTION_SIG_MOT_SEL BIT(1) + (MIN(((_mg)*1000) / ((_s)->current_range * 1953), 0xff)) +#define BMI160_INT_MOTION_2 0x61 +#define BMI160_INT_MOTION_3 0x62 +#define BMI160_MOTION_NO_MOT_SEL BIT(0) +#define BMI160_MOTION_SIG_MOT_SEL BIT(1) #define BMI160_MOTION_SKIP_OFF 2 #define BMI160_MOTION_SKIP_MASK 0x3 #define BMI160_MOTION_SKIP_TIME(_ms) \ @@ -282,74 +280,75 @@ #define BMI160_MOTION_PROOF_TIME(_ms) \ (MIN(__fls((_ms) / 250), BMI160_MOTION_PROOF_MASK)) -#define BMI160_INT_TAP_0 0x63 -#define BMI160_TAP_DUR(_s, _ms) \ +#define BMI160_INT_TAP_0 0x63 +#define BMI160_TAP_DUR(_s, _ms) \ ((_ms) <= 250 ? MAX((_ms), 50) / 50 - 1 : \ - (_ms) <= 500 ? 4 + ((_ms) - 250) / 125 : \ - (_ms) < 700 ? 6 : 7) + (_ms) <= 500 ? 4 + ((_ms)-250) / 125 : \ + (_ms) < 700 ? 6 : \ + 7) -#define BMI160_INT_TAP_1 0x64 +#define BMI160_INT_TAP_1 0x64 #define BMI160_TAP_TH(_s, _mg) \ - (MIN(((_mg) * 1000) / ((_s)->current_range * 31250), 0x1f)) + (MIN(((_mg)*1000) / ((_s)->current_range * 31250), 0x1f)) -#define BMI160_INT_ORIENT_0 0x65 +#define BMI160_INT_ORIENT_0 0x65 /* No hysterisis, theta block, int on slope > 0.2 or axis > 1.5, symmetrical */ -#define BMI160_INT_ORIENT_0_INIT_VAL 0x48 +#define BMI160_INT_ORIENT_0_INIT_VAL 0x48 -#define BMI160_INT_ORIENT_1 0x66 +#define BMI160_INT_ORIENT_1 0x66 /* no axes remap, no int on up/down, no blocking angle */ -#define BMI160_INT_ORIENT_1_INIT_VAL 0x00 - -#define BMI160_INT_FLAT_0 0x67 -#define BMI160_INT_FLAT_1 0x68 - -#define BMI160_FOC_CONF 0x69 -#define BMI160_FOC_GYRO_EN BIT(6) -#define BMI160_FOC_ACC_PLUS_1G 1 -#define BMI160_FOC_ACC_MINUS_1G 2 -#define BMI160_FOC_ACC_0G 3 -#define BMI160_FOC_ACC_Z_OFFSET 0 -#define BMI160_FOC_ACC_Y_OFFSET 2 -#define BMI160_FOC_ACC_X_OFFSET 4 - -#define BMI160_CONF 0x6a -#define BMI160_IF_CONF 0x6b -#define BMI160_IF_MODE_OFF 4 -#define BMI160_IF_MODE_MASK 3 +#define BMI160_INT_ORIENT_1_INIT_VAL 0x00 + +#define BMI160_INT_FLAT_0 0x67 +#define BMI160_INT_FLAT_1 0x68 + +#define BMI160_FOC_CONF 0x69 +#define BMI160_FOC_GYRO_EN BIT(6) +#define BMI160_FOC_ACC_PLUS_1G 1 +#define BMI160_FOC_ACC_MINUS_1G 2 +#define BMI160_FOC_ACC_0G 3 +#define BMI160_FOC_ACC_Z_OFFSET 0 +#define BMI160_FOC_ACC_Y_OFFSET 2 +#define BMI160_FOC_ACC_X_OFFSET 4 + +#define BMI160_CONF 0x6a +#define BMI160_IF_CONF 0x6b +#define BMI160_IF_MODE_OFF 4 +#define BMI160_IF_MODE_MASK 3 #define BMI160_IF_MODE_AUTO_OFF 0 -#define BMI160_IF_MODE_I2C_IOS 1 +#define BMI160_IF_MODE_I2C_IOS 1 #define BMI160_IF_MODE_AUTO_I2C 2 -#define BMI160_PMU_TRIGGER 0x6c -#define BMI160_SELF_TEST 0x6d +#define BMI160_PMU_TRIGGER 0x6c +#define BMI160_SELF_TEST 0x6d -#define BMI160_NV_CONF 0x70 +#define BMI160_NV_CONF 0x70 -#define BMI160_OFFSET_ACC70 0x71 -#define BMI160_OFFSET_GYR70 0x74 -#define BMI160_OFFSET_EN_GYR98 0x77 -#define BMI160_OFFSET_ACC_EN BIT(6) -#define BMI160_OFFSET_GYRO_EN BIT(7) +#define BMI160_OFFSET_ACC70 0x71 +#define BMI160_OFFSET_GYR70 0x74 +#define BMI160_OFFSET_EN_GYR98 0x77 +#define BMI160_OFFSET_ACC_EN BIT(6) +#define BMI160_OFFSET_GYRO_EN BIT(7) -#define BMI160_STEP_CNT_0 0x78 -#define BMI160_STEP_CNT_1 0x79 -#define BMI160_STEP_CONF_0 0x7a -#define BMI160_STEP_CONF_1 0x7b +#define BMI160_STEP_CNT_0 0x78 +#define BMI160_STEP_CNT_1 0x79 +#define BMI160_STEP_CONF_0 0x7a +#define BMI160_STEP_CONF_1 0x7b -#define BMI160_CMD_REG 0x7e -#define BMI160_CMD_SOFT_RESET 0xb6 -#define BMI160_CMD_NOOP 0x00 -#define BMI160_CMD_START_FOC 0x03 +#define BMI160_CMD_REG 0x7e +#define BMI160_CMD_SOFT_RESET 0xb6 +#define BMI160_CMD_NOOP 0x00 +#define BMI160_CMD_START_FOC 0x03 #define BMI160_CMD_ACC_MODE_OFFSET 0x10 -#define BMI160_CMD_ACC_MODE_SUSP 0x10 +#define BMI160_CMD_ACC_MODE_SUSP 0x10 #define BMI160_CMD_ACC_MODE_NORMAL 0x11 #define BMI160_CMD_ACC_MODE_LOWPOWER 0x12 -#define BMI160_CMD_GYR_MODE_SUSP 0x14 +#define BMI160_CMD_GYR_MODE_SUSP 0x14 #define BMI160_CMD_GYR_MODE_NORMAL 0x15 #define BMI160_CMD_GYR_MODE_FAST_STARTUP 0x17 -#define BMI160_CMD_MAG_MODE_SUSP 0x18 +#define BMI160_CMD_MAG_MODE_SUSP 0x18 #define BMI160_CMD_MAG_MODE_NORMAL 0x19 #define BMI160_CMD_MAG_MODE_LOWPOWER 0x1a #define BMI160_CMD_MODE_SUSPEND(_sensor_type) \ @@ -357,31 +356,31 @@ #define BMI160_CMD_MODE_NORMAL(_sensor_type) \ (BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_NORMAL) -#define BMI160_CMD_FIFO_FLUSH 0xb0 -#define BMI160_CMD_INT_RESET 0xb1 -#define BMI160_CMD_SOFT_RESET 0xb6 -#define BMI160_CMD_EXT_MODE_EN_B0 0x37 -#define BMI160_CMD_EXT_MODE_EN_B1 0x9a -#define BMI160_CMD_EXT_MODE_EN_B2 0xc0 +#define BMI160_CMD_FIFO_FLUSH 0xb0 +#define BMI160_CMD_INT_RESET 0xb1 +#define BMI160_CMD_SOFT_RESET 0xb6 +#define BMI160_CMD_EXT_MODE_EN_B0 0x37 +#define BMI160_CMD_EXT_MODE_EN_B1 0x9a +#define BMI160_CMD_EXT_MODE_EN_B2 0xc0 -#define BMI160_CMD_EXT_MODE_ADDR 0x7f -#define BMI160_CMD_PAGING_EN BIT(7) -#define BMI160_CMD_TARGET_PAGE BIT(4) +#define BMI160_CMD_EXT_MODE_ADDR 0x7f +#define BMI160_CMD_PAGING_EN BIT(7) +#define BMI160_CMD_TARGET_PAGE BIT(4) #define BMI160_COM_C_TRIM_ADDR 0x85 -#define BMI160_COM_C_TRIM (3 << 4) +#define BMI160_COM_C_TRIM (3 << 4) -#define BMI160_CMD_TGT_PAGE 0 -#define BMI160_CMD_TGT_PAGE_COM 1 -#define BMI160_CMD_TGT_PAGE_ACC 2 -#define BMI160_CMD_TGT_PAGE_GYR 3 +#define BMI160_CMD_TGT_PAGE 0 +#define BMI160_CMD_TGT_PAGE_COM 1 +#define BMI160_CMD_TGT_PAGE_ACC 2 +#define BMI160_CMD_TGT_PAGE_GYR 3 -#define BMI160_FF_FRAME_LEN_TS 4 -#define BMI160_FF_DATA_LEN_ACC 6 -#define BMI160_FF_DATA_LEN_GYR 6 -#define BMI160_FF_DATA_LEN_MAG 8 +#define BMI160_FF_FRAME_LEN_TS 4 +#define BMI160_FF_DATA_LEN_ACC 6 +#define BMI160_FF_DATA_LEN_GYR 6 +#define BMI160_FF_DATA_LEN_MAG 8 /* Root mean square noise of 100 Hz accelerometer, units: ug */ -#define BMI160_ACCEL_RMS_NOISE_100HZ 1300 +#define BMI160_ACCEL_RMS_NOISE_100HZ 1300 /* Functions to access the secondary device through the accel/gyro. */ int bmi160_sec_raw_read8(const int port, const uint16_t addr_flags, @@ -404,6 +403,6 @@ int bmi160_sec_raw_write8(const int port, const uint16_t addr_flags, #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ACCELGYRO_BMI160_H */ diff --git a/include/driver/accelgyro_bmi160_public.h b/include/driver/accelgyro_bmi160_public.h index 6a6890eb84..551e351fea 100644 --- a/include/driver/accelgyro_bmi160_public.h +++ b/include/driver/accelgyro_bmi160_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,7 +18,7 @@ */ /* I2C addresses */ -#define BMI160_ADDR0_FLAGS 0x68 +#define BMI160_ADDR0_FLAGS 0x68 extern const struct accelgyro_drv bmi160_drv; diff --git a/include/driver/accelgyro_bmi260.h b/include/driver/accelgyro_bmi260.h index fb5db82afb..5d55a85acc 100644 --- a/include/driver/accelgyro_bmi260.h +++ b/include/driver/accelgyro_bmi260.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,320 +13,320 @@ #include "mag_bmm150.h" #include "driver/accelgyro_bmi260_public.h" -#define BMI260_CHIP_ID 0x00 +#define BMI260_CHIP_ID 0x00 /* BMI260 chip identifier */ -#define BMI260_CHIP_ID_MAJOR 0x27 +#define BMI260_CHIP_ID_MAJOR 0x27 /* BMI220 chip identifier */ -#define BMI220_CHIP_ID_MAJOR 0x26 - -#define BMI260_ERR_REG 0x02 - -#define BMI260_STATUS 0x03 -#define BMI260_AUX_BUSY BIT(2) -#define BMI260_CMD_RDY BIT(4) -#define BMI260_DRDY_AUX BIT(5) -#define BMI260_DRDY_GYR BIT(6) -#define BMI260_DRDY_ACC BIT(7) -#define BMI260_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI260_DRDY_MASK(_sensor) (1 << BMI260_DRDY_OFF(_sensor)) - -#define BMI260_AUX_X_L_G 0x04 -#define BMI260_AUX_X_H_G 0x05 -#define BMI260_AUX_Y_L_G 0x06 -#define BMI260_AUX_Y_H_G 0x07 -#define BMI260_AUX_Z_L_G 0x08 -#define BMI260_AUX_Z_H_G 0x09 -#define BMI260_AUX_R_L_G 0x0a -#define BMI260_AUX_R_H_G 0x0b -#define BMI260_ACC_X_L_G 0x0c -#define BMI260_ACC_X_H_G 0x0d -#define BMI260_ACC_Y_L_G 0x0e -#define BMI260_ACC_Y_H_G 0x0f -#define BMI260_ACC_Z_L_G 0x10 -#define BMI260_ACC_Z_H_G 0x11 -#define BMI260_GYR_X_L_G 0x12 -#define BMI260_GYR_X_H_G 0x13 -#define BMI260_GYR_Y_L_G 0x14 -#define BMI260_GYR_Y_H_G 0x15 -#define BMI260_GYR_Z_L_G 0x16 -#define BMI260_GYR_Z_H_G 0x17 - -#define BMI260_SENSORTIME_0 0x18 -#define BMI260_SENSORTIME_1 0x19 -#define BMI260_SENSORTIME_2 0x1a - -#define BMI260_EVENT 0x1b +#define BMI220_CHIP_ID_MAJOR 0x26 + +#define BMI260_ERR_REG 0x02 + +#define BMI260_STATUS 0x03 +#define BMI260_AUX_BUSY BIT(2) +#define BMI260_CMD_RDY BIT(4) +#define BMI260_DRDY_AUX BIT(5) +#define BMI260_DRDY_GYR BIT(6) +#define BMI260_DRDY_ACC BIT(7) +#define BMI260_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI260_DRDY_MASK(_sensor) (1 << BMI260_DRDY_OFF(_sensor)) + +#define BMI260_AUX_X_L_G 0x04 +#define BMI260_AUX_X_H_G 0x05 +#define BMI260_AUX_Y_L_G 0x06 +#define BMI260_AUX_Y_H_G 0x07 +#define BMI260_AUX_Z_L_G 0x08 +#define BMI260_AUX_Z_H_G 0x09 +#define BMI260_AUX_R_L_G 0x0a +#define BMI260_AUX_R_H_G 0x0b +#define BMI260_ACC_X_L_G 0x0c +#define BMI260_ACC_X_H_G 0x0d +#define BMI260_ACC_Y_L_G 0x0e +#define BMI260_ACC_Y_H_G 0x0f +#define BMI260_ACC_Z_L_G 0x10 +#define BMI260_ACC_Z_H_G 0x11 +#define BMI260_GYR_X_L_G 0x12 +#define BMI260_GYR_X_H_G 0x13 +#define BMI260_GYR_Y_L_G 0x14 +#define BMI260_GYR_Y_H_G 0x15 +#define BMI260_GYR_Z_L_G 0x16 +#define BMI260_GYR_Z_H_G 0x17 + +#define BMI260_SENSORTIME_0 0x18 +#define BMI260_SENSORTIME_1 0x19 +#define BMI260_SENSORTIME_2 0x1a + +#define BMI260_EVENT 0x1b /* 2 bytes interrupt reasons*/ -#define BMI260_INT_STATUS_0 0x1c -#define BMI260_SIG_MOTION_OUT BIT(0) -#define BMI260_STEP_COUNTER_OUT BIT(1) -#define BMI260_HIGH_LOW_G_OUT BIT(2) -#define BMI260_TAP_OUT BIT(3) -#define BMI260_FLAT_OUT BIT(4) -#define BMI260_NO_MOTION_OUT BIT(5) -#define BMI260_ANY_MOTION_OUT BIT(6) -#define BMI260_ORIENTATION_OUT BIT(7) - -#define BMI260_INT_STATUS_1 0x1d -#define BMI260_FFULL_INT BIT(0 + 8) -#define BMI260_FWM_INT BIT(1 + 8) -#define BMI260_ERR_INT BIT(2 + 8) -#define BMI260_AUX_DRDY_INT BIT(5 + 8) -#define BMI260_GYR_DRDY_INT BIT(6 + 8) -#define BMI260_ACC_DRDY_INT BIT(7 + 8) - -#define BMI260_INT_MASK 0xFFFF - -#define BMI260_SC_OUT_0 0x1e -#define BMI260_SC_OUT_1 0x1f - -#define BMI260_ORIENT_ACT 0x20 - -#define BMI260_INTERNAL_STATUS 0X21 -#define BMI260_MESSAGE_MASK 0xf -#define BMI260_NOT_INIT 0x00 -#define BMI260_INIT_OK 0x01 -#define BMI260_INIT_ERR 0x02 -#define BMI260_DRV_ERR 0x03 -#define BMI260_SNS_STOP 0x04 -#define BMI260_NVM_ERROR 0x05 -#define BMI260_START_UP_ERROR 0x06 -#define BMI260_COMPAT_ERROR 0x07 - -#define BMI260_TEMPERATURE_0 0x22 -#define BMI260_TEMPERATURE_1 0x23 - -#define BMI260_FIFO_LENGTH_0 0x24 -#define BMI260_FIFO_LENGTH_1 0x25 -#define BMI260_FIFO_LENGTH_MASK (BIT(14) - 1) -#define BMI260_FIFO_DATA 0x26 - -#define BMI260_FEAT_PAGE 0x2f +#define BMI260_INT_STATUS_0 0x1c +#define BMI260_SIG_MOTION_OUT BIT(0) +#define BMI260_STEP_COUNTER_OUT BIT(1) +#define BMI260_HIGH_LOW_G_OUT BIT(2) +#define BMI260_TAP_OUT BIT(3) +#define BMI260_FLAT_OUT BIT(4) +#define BMI260_NO_MOTION_OUT BIT(5) +#define BMI260_ANY_MOTION_OUT BIT(6) +#define BMI260_ORIENTATION_OUT BIT(7) + +#define BMI260_INT_STATUS_1 0x1d +#define BMI260_FFULL_INT BIT(0 + 8) +#define BMI260_FWM_INT BIT(1 + 8) +#define BMI260_ERR_INT BIT(2 + 8) +#define BMI260_AUX_DRDY_INT BIT(5 + 8) +#define BMI260_GYR_DRDY_INT BIT(6 + 8) +#define BMI260_ACC_DRDY_INT BIT(7 + 8) + +#define BMI260_INT_MASK 0xFFFF + +#define BMI260_SC_OUT_0 0x1e +#define BMI260_SC_OUT_1 0x1f + +#define BMI260_ORIENT_ACT 0x20 + +#define BMI260_INTERNAL_STATUS 0X21 +#define BMI260_MESSAGE_MASK 0xf +#define BMI260_NOT_INIT 0x00 +#define BMI260_INIT_OK 0x01 +#define BMI260_INIT_ERR 0x02 +#define BMI260_DRV_ERR 0x03 +#define BMI260_SNS_STOP 0x04 +#define BMI260_NVM_ERROR 0x05 +#define BMI260_START_UP_ERROR 0x06 +#define BMI260_COMPAT_ERROR 0x07 + +#define BMI260_TEMPERATURE_0 0x22 +#define BMI260_TEMPERATURE_1 0x23 + +#define BMI260_FIFO_LENGTH_0 0x24 +#define BMI260_FIFO_LENGTH_1 0x25 +#define BMI260_FIFO_LENGTH_MASK (BIT(14) - 1) +#define BMI260_FIFO_DATA 0x26 + +#define BMI260_FEAT_PAGE 0x2f /* * The register of feature page should be read/write as 16-bit register * Otherwise, there can be invalid data */ /* Features page 0 */ -#define BMI260_ORIENT_OUT 0x36 -#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK 3 -#define BMI260_ORIENT_PORTRAIT 0x0 -#define BMI260_ORIENT_LANDSCAPE 0x1 -#define BMI260_ORIENT_PORTRAIT_INVERT 0x2 -#define BMI260_ORIENT_LANDSCAPE_INVERT 0x3 +#define BMI260_ORIENT_OUT 0x36 +#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK 3 +#define BMI260_ORIENT_PORTRAIT 0x0 +#define BMI260_ORIENT_LANDSCAPE 0x1 +#define BMI260_ORIENT_PORTRAIT_INVERT 0x2 +#define BMI260_ORIENT_LANDSCAPE_INVERT 0x3 /* Features page 1 */ -#define BMI260_GEN_SET_1 0x34 -#define BMI260_GYR_SELF_OFF BIT(9) +#define BMI260_GEN_SET_1 0x34 +#define BMI260_GYR_SELF_OFF BIT(9) -#define BMI260_TAP_1 0x3e -#define BMI260_TAP_1_EN BIT(0) -#define BMI260_TAP_1_SENSITIVITY_OFFSET 1 -#define BMI260_TAP_1_SENSITIVITY_MASK \ - (0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET) +#define BMI260_TAP_1 0x3e +#define BMI260_TAP_1_EN BIT(0) +#define BMI260_TAP_1_SENSITIVITY_OFFSET 1 +#define BMI260_TAP_1_SENSITIVITY_MASK (0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET) /* Features page 2 */ -#define BMI260_ORIENT_1 0x30 -#define BMI260_ORIENT_1_EN BIT(0) -#define BMI260_ORIENT_1_UD_EN BIT(1) +#define BMI260_ORIENT_1 0x30 +#define BMI260_ORIENT_1_EN BIT(0) +#define BMI260_ORIENT_1_UD_EN BIT(1) #define BMI260_ORIENT_1_MODE_OFFSET 2 -#define BMI260_ORIENT_1_MODE_MASK (0x3 << BMI260_ORIENT_1_MODE_OFFSET) -#define BMI260_ORIENT_1_BLOCK_OFFSET 4 -#define BMI260_ORIENT_1_BLOCK_MASK (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET) -#define BMI260_ORIENT_1_THETA_OFFSET 6 -#define BMI260_ORIENT_1_THETA_MASK \ +#define BMI260_ORIENT_1_MODE_MASK (0x3 << BMI260_ORIENT_1_MODE_OFFSET) +#define BMI260_ORIENT_1_BLOCK_OFFSET 4 +#define BMI260_ORIENT_1_BLOCK_MASK (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET) +#define BMI260_ORIENT_1_THETA_OFFSET 6 +#define BMI260_ORIENT_1_THETA_MASK \ ((BIT(6) - 1) << BMI260_ORIENT_1_THETA_OFFSET) -#define BMI260_ORIENT_2 0x32 +#define BMI260_ORIENT_2 0x32 /* hysteresis(10...0) range is 0~1g, default is 128 (0.0625g) */ -#define BMI260_ORIENT_2_HYSTERESIS_MASK (BIT(11) - 1) +#define BMI260_ORIENT_2_HYSTERESIS_MASK (BIT(11) - 1) -#define BMI260_ACC_CONF 0x40 -#define BMI260_ACC_BW_OFFSET 4 -#define BMI260_ACC_BW_MASK (0x7 << BMI260_ACC_BW_OFFSET) -#define BMI260_FILTER_PERF BIT(7) -#define BMI260_ULP 0x0 -#define BMI260_HP 0x1 +#define BMI260_ACC_CONF 0x40 +#define BMI260_ACC_BW_OFFSET 4 +#define BMI260_ACC_BW_MASK (0x7 << BMI260_ACC_BW_OFFSET) +#define BMI260_FILTER_PERF BIT(7) +#define BMI260_ULP 0x0 +#define BMI260_HP 0x1 -#define BMI260_ACC_RANGE 0x41 -#define BMI260_GSEL_2G 0x00 -#define BMI260_GSEL_4G 0x01 -#define BMI260_GSEL_8G 0x02 -#define BMI260_GSEL_16G 0x03 +#define BMI260_ACC_RANGE 0x41 +#define BMI260_GSEL_2G 0x00 +#define BMI260_GSEL_4G 0x01 +#define BMI260_GSEL_8G 0x02 +#define BMI260_GSEL_16G 0x03 /* The max positvie value of accel data is 0x7FFF, equal to range(g) */ /* So, in order to get +1g, divide the 0x7FFF by range */ #define BMI260_ACC_DATA_PLUS_1G(range) (0x7FFF / (range)) #define BMI260_ACC_DATA_MINUS_1G(range) (-BMI260_ACC_DATA_PLUS_1G(range)) -#define BMI260_GYR_CONF 0x42 -#define BMI260_GYR_BW_OFFSET 4 -#define BMI260_GYR_BW_MASK (0x3 << BMI260_GYR_BW_OFFSET) -#define BMI260_GYR_NOISE_PERF BIT(6) - -#define BMI260_GYR_RANGE 0x43 -#define BMI260_DPS_SEL_2000 0x00 -#define BMI260_DPS_SEL_1000 0x01 -#define BMI260_DPS_SEL_500 0x02 -#define BMI260_DPS_SEL_250 0x03 -#define BMI260_DPS_SEL_125 0x04 - -#define BMI260_AUX_CONF 0x44 - -#define BMI260_FIFO_DOWNS 0x45 - -#define BMI260_FIFO_WTM_0 0x46 -#define BMI260_FIFO_WTM_1 0x47 - -#define BMI260_FIFO_CONFIG_0 0x48 -#define BMI260_FIFO_STOP_ON_FULL BIT(0) -#define BMI260_FIFO_TIME_EN BIT(1) - -#define BMI260_FIFO_CONFIG_1 0x49 -#define BMI260_FIFO_TAG_INT1_EN_OFFSET 0 -#define BMI260_FIFO_TAG_INT1_EN_MASK (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET) -#define BMI260_FIFO_TAG_INT2_EN_OFFSET 2 -#define BMI260_FIFO_TAG_INT2_EN_MASK (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET) -#define BMI260_FIFO_TAG_INT_EDGE 0x0 -#define BMI260_FIFO_TAG_INT_LEVEL 0x1 -#define BMI260_FIFO_TAG_ACC_SAT 0x2 -#define BMI260_FIFO_TAG_GYR_SAT 0x3 -#define BMI260_FIFO_HEADER_EN BIT(4) -#define BMI260_FIFO_AUX_EN BIT(5) -#define BMI260_FIFO_ACC_EN BIT(6) -#define BMI260_FIFO_GYR_EN BIT(7) -#define BMI260_FIFO_SENSOR_EN(_sensor) \ - ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI260_FIFO_ACC_EN : \ - ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \ - BMI260_FIFO_AUX_EN)) - -#define BMI260_SATURATION 0x4a - -#define BMI260_AUX_DEV_ID 0x4b -#define BMI260_AUX_I2C_ADDRESS BMI260_AUX_DEV_ID - -#define BMI260_AUX_IF_CONF 0x4c -#define BMI260_AUX_I2C_CONTROL BMI260_AUX_IF_CONF -#define BMI260_AUX_READ_BURST_MASK 3 -#define BMI260_AUX_MAN_READ_BURST_OFF 2 -#define BMI260_AUX_MAN_READ_BURST_MASK (0x3 << BMI280_AUX_MAN_READ_BURST_OFF) -#define BMI260_AUX_READ_BURST_1 0 -#define BMI260_AUX_READ_BURST_2 1 -#define BMI260_AUX_READ_BURST_6 2 -#define BMI260_AUX_READ_BURST_8 3 -#define BMI260_AUX_FCU_WRITE_EN BIT(6) -#define BMI260_AUX_MANUAL_EN BIT(7) - -#define BMI260_AUX_RD_ADDR 0x4d -#define BMI260_AUX_I2C_READ_ADDR BMI260_AUX_RD_ADDR -#define BMI260_AUX_WR_ADDR 0x4e -#define BMI260_AUX_I2C_WRITE_ADDR BMI260_AUX_WR_ADDR -#define BMI260_AUX_WR_DATA 0x4f -#define BMI260_AUX_I2C_WRITE_DATA BMI260_AUX_WR_DATA -#define BMI260_AUX_I2C_READ_DATA BMI260_AUX_X_L_G - -#define BMI260_ERR_REG_MSK 0x52 -#define BMI260_FATAL_ERR BIT(0) -#define BMI260_INTERNAL_ERR_OFF 1 -#define BMI260_INTERNAL_ERR_MASK (0xf << BMI260_INTERNAL_ERR_OFF) -#define BMI260_FIFO_ERR BIT(6) -#define BMI260_AUX_ERR BIT(7) - -#define BMI260_INT1_IO_CTRL 0x53 -#define BMI260_INT1_LVL BIT(1) -#define BMI260_INT1_OD BIT(2) -#define BMI260_INT1_OUTPUT_EN BIT(3) -#define BMI260_INT1_INPUT_EN BIT(4) - -#define BMI260_INT2_IO_CTRL 0x54 -#define BMI260_INT2_LVL BIT(1) -#define BMI260_INT2_OD BIT(2) -#define BMI260_INT2_OUTPUT_EN BIT(3) -#define BMI260_INT2_INPUT_EN BIT(4) - -#define BMI260_INT_LATCH 0x55 -#define BMI260_INT_LATCH_EN BIT(0) - -#define BMI260_INT1_MAP_FEAT 0x56 -#define BMI260_INT2_MAP_FEAT 0x57 -#define BMI260_MAP_SIG_MOTION_OUT BIT(0) +#define BMI260_GYR_CONF 0x42 +#define BMI260_GYR_BW_OFFSET 4 +#define BMI260_GYR_BW_MASK (0x3 << BMI260_GYR_BW_OFFSET) +#define BMI260_GYR_NOISE_PERF BIT(6) + +#define BMI260_GYR_RANGE 0x43 +#define BMI260_DPS_SEL_2000 0x00 +#define BMI260_DPS_SEL_1000 0x01 +#define BMI260_DPS_SEL_500 0x02 +#define BMI260_DPS_SEL_250 0x03 +#define BMI260_DPS_SEL_125 0x04 + +#define BMI260_AUX_CONF 0x44 + +#define BMI260_FIFO_DOWNS 0x45 + +#define BMI260_FIFO_WTM_0 0x46 +#define BMI260_FIFO_WTM_1 0x47 + +#define BMI260_FIFO_CONFIG_0 0x48 +#define BMI260_FIFO_STOP_ON_FULL BIT(0) +#define BMI260_FIFO_TIME_EN BIT(1) + +#define BMI260_FIFO_CONFIG_1 0x49 +#define BMI260_FIFO_TAG_INT1_EN_OFFSET 0 +#define BMI260_FIFO_TAG_INT1_EN_MASK (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET) +#define BMI260_FIFO_TAG_INT2_EN_OFFSET 2 +#define BMI260_FIFO_TAG_INT2_EN_MASK (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET) +#define BMI260_FIFO_TAG_INT_EDGE 0x0 +#define BMI260_FIFO_TAG_INT_LEVEL 0x1 +#define BMI260_FIFO_TAG_ACC_SAT 0x2 +#define BMI260_FIFO_TAG_GYR_SAT 0x3 +#define BMI260_FIFO_HEADER_EN BIT(4) +#define BMI260_FIFO_AUX_EN BIT(5) +#define BMI260_FIFO_ACC_EN BIT(6) +#define BMI260_FIFO_GYR_EN BIT(7) +#define BMI260_FIFO_SENSOR_EN(_sensor) \ + ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? \ + BMI260_FIFO_ACC_EN : \ + ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \ + BMI260_FIFO_AUX_EN)) + +#define BMI260_SATURATION 0x4a + +#define BMI260_AUX_DEV_ID 0x4b +#define BMI260_AUX_I2C_ADDRESS BMI260_AUX_DEV_ID + +#define BMI260_AUX_IF_CONF 0x4c +#define BMI260_AUX_I2C_CONTROL BMI260_AUX_IF_CONF +#define BMI260_AUX_READ_BURST_MASK 3 +#define BMI260_AUX_MAN_READ_BURST_OFF 2 +#define BMI260_AUX_MAN_READ_BURST_MASK (0x3 << BMI280_AUX_MAN_READ_BURST_OFF) +#define BMI260_AUX_READ_BURST_1 0 +#define BMI260_AUX_READ_BURST_2 1 +#define BMI260_AUX_READ_BURST_6 2 +#define BMI260_AUX_READ_BURST_8 3 +#define BMI260_AUX_FCU_WRITE_EN BIT(6) +#define BMI260_AUX_MANUAL_EN BIT(7) + +#define BMI260_AUX_RD_ADDR 0x4d +#define BMI260_AUX_I2C_READ_ADDR BMI260_AUX_RD_ADDR +#define BMI260_AUX_WR_ADDR 0x4e +#define BMI260_AUX_I2C_WRITE_ADDR BMI260_AUX_WR_ADDR +#define BMI260_AUX_WR_DATA 0x4f +#define BMI260_AUX_I2C_WRITE_DATA BMI260_AUX_WR_DATA +#define BMI260_AUX_I2C_READ_DATA BMI260_AUX_X_L_G + +#define BMI260_ERR_REG_MSK 0x52 +#define BMI260_FATAL_ERR BIT(0) +#define BMI260_INTERNAL_ERR_OFF 1 +#define BMI260_INTERNAL_ERR_MASK (0xf << BMI260_INTERNAL_ERR_OFF) +#define BMI260_FIFO_ERR BIT(6) +#define BMI260_AUX_ERR BIT(7) + +#define BMI260_INT1_IO_CTRL 0x53 +#define BMI260_INT1_LVL BIT(1) +#define BMI260_INT1_OD BIT(2) +#define BMI260_INT1_OUTPUT_EN BIT(3) +#define BMI260_INT1_INPUT_EN BIT(4) + +#define BMI260_INT2_IO_CTRL 0x54 +#define BMI260_INT2_LVL BIT(1) +#define BMI260_INT2_OD BIT(2) +#define BMI260_INT2_OUTPUT_EN BIT(3) +#define BMI260_INT2_INPUT_EN BIT(4) + +#define BMI260_INT_LATCH 0x55 +#define BMI260_INT_LATCH_EN BIT(0) + +#define BMI260_INT1_MAP_FEAT 0x56 +#define BMI260_INT2_MAP_FEAT 0x57 +#define BMI260_MAP_SIG_MOTION_OUT BIT(0) #define BMI260_MAP_STEP_COUNTER_OUT BIT(1) -#define BMI260_MAP_HIGH_LOW_G_OUT BIT(2) -#define BMI260_MAP_TAP_OUT BIT(3) -#define BMI260_MAP_FLAT_OUT BIT(4) -#define BMI260_MAP_NO_MOTION_OUT BIT(5) -#define BMI260_MAP_ANY_MOTION_OUT BIT(6) -#define BMI260_MAP_ORIENTAION_OUT BIT(7) - -#define BMI260_INT_MAP_DATA 0x58 -#define BMI260_MAP_FFULL_INT BIT(0) -#define BMI260_MAP_FWM_INT BIT(1) -#define BMI260_MAP_DRDY_INT BIT(2) -#define BMI260_MAP_ERR_INT BIT(3) -#define BMI260_INT_MAP_DATA_INT1_OFFSET 0 -#define BMI260_INT_MAP_DATA_INT2_OFFSET 4 +#define BMI260_MAP_HIGH_LOW_G_OUT BIT(2) +#define BMI260_MAP_TAP_OUT BIT(3) +#define BMI260_MAP_FLAT_OUT BIT(4) +#define BMI260_MAP_NO_MOTION_OUT BIT(5) +#define BMI260_MAP_ANY_MOTION_OUT BIT(6) +#define BMI260_MAP_ORIENTAION_OUT BIT(7) + +#define BMI260_INT_MAP_DATA 0x58 +#define BMI260_MAP_FFULL_INT BIT(0) +#define BMI260_MAP_FWM_INT BIT(1) +#define BMI260_MAP_DRDY_INT BIT(2) +#define BMI260_MAP_ERR_INT BIT(3) +#define BMI260_INT_MAP_DATA_INT1_OFFSET 0 +#define BMI260_INT_MAP_DATA_INT2_OFFSET 4 #define BMI260_INT_MAP_DATA_REG(_i, _bit) \ - (CONCAT3(BMI260_MAP_, _bit, _INT) << \ - CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET)) + (CONCAT3(BMI260_MAP_, _bit, _INT) \ + << CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET)) -#define BMI260_INIT_CTRL 0x59 -#define BMI260_INIT_ADDR_0 0x5b -#define BMI260_INIT_ADDR_1 0x5c -#define BMI260_INIT_DATA 0x5e -#define BMI260_INTERNAL_ERROR 0x5f -#define BMI260_INT_ERR_1 BIT(1) -#define BMI260_INT_ERR_2 BIT(2) -#define BMI260_FEAT_ENG_DISABLED BIT(4) +#define BMI260_INIT_CTRL 0x59 +#define BMI260_INIT_ADDR_0 0x5b +#define BMI260_INIT_ADDR_1 0x5c +#define BMI260_INIT_DATA 0x5e +#define BMI260_INTERNAL_ERROR 0x5f +#define BMI260_INT_ERR_1 BIT(1) +#define BMI260_INT_ERR_2 BIT(2) +#define BMI260_FEAT_ENG_DISABLED BIT(4) -#define BMI260_AUX_IF_TRIM 0x68 -#define BMI260_GYR_CRT_CONF 0x69 +#define BMI260_AUX_IF_TRIM 0x68 +#define BMI260_GYR_CRT_CONF 0x69 -#define BMI260_NVM_CONF 0x6a -#define BMI260_NVM_PROG_EN BIT(1) +#define BMI260_NVM_CONF 0x6a +#define BMI260_NVM_PROG_EN BIT(1) -#define BMI260_IF_CONF 0x6b -#define BMI260_IF_SPI3 BIT(0) -#define BMI260_IF_SPI3_OIS BIT(1) -#define BMI260_IF_OIS_EN BIT(4) -#define BMI260_IF_AUX_EN BIT(5) +#define BMI260_IF_CONF 0x6b +#define BMI260_IF_SPI3 BIT(0) +#define BMI260_IF_SPI3_OIS BIT(1) +#define BMI260_IF_OIS_EN BIT(4) +#define BMI260_IF_AUX_EN BIT(5) -#define BMI260_DRV 0x6c -#define BMI260_ACC_SELF_TEST 0x6d +#define BMI260_DRV 0x6c +#define BMI260_ACC_SELF_TEST 0x6d #define BMI260_GYR_SELF_TEST_AXES 0x6e -#define BMI260_NV_CONF 0x70 -#define BMI260_ACC_OFFSET_EN BIT(3) +#define BMI260_NV_CONF 0x70 +#define BMI260_ACC_OFFSET_EN BIT(3) -#define BMI260_OFFSET_ACC70 0x71 -#define BMI260_OFFSET_GYR70 0x74 -#define BMI260_OFFSET_EN_GYR98 0x77 -#define BMI260_OFFSET_GYRO_EN BIT(6) -#define BMI260_GYR_GAIN_EN BIT(7) +#define BMI260_OFFSET_ACC70 0x71 +#define BMI260_OFFSET_GYR70 0x74 +#define BMI260_OFFSET_EN_GYR98 0x77 +#define BMI260_OFFSET_GYRO_EN BIT(6) +#define BMI260_GYR_GAIN_EN BIT(7) -#define BMI260_PWR_CONF 0x7c -#define BMI260_ADV_POWER_SAVE BIT(0) -#define BMI260_FIFO_SELF_WAKE_UP BIT(1) -#define BMI260_FUP_EN BIT(2) +#define BMI260_PWR_CONF 0x7c +#define BMI260_ADV_POWER_SAVE BIT(0) +#define BMI260_FIFO_SELF_WAKE_UP BIT(1) +#define BMI260_FUP_EN BIT(2) -#define BMI260_PWR_CTRL 0x7d -#define BMI260_AUX_EN BIT(0) -#define BMI260_GYR_EN BIT(1) -#define BMI260_ACC_EN BIT(2) +#define BMI260_PWR_CTRL 0x7d +#define BMI260_AUX_EN BIT(0) +#define BMI260_GYR_EN BIT(1) +#define BMI260_ACC_EN BIT(2) #define BMI260_PWR_EN(_sensor_type) BIT(2 - _sensor_type) -#define BMI260_TEMP_EN BIT(3) +#define BMI260_TEMP_EN BIT(3) -#define BMI260_CMD_REG 0x7e -#define BMI260_CMD_FIFO_FLUSH 0xb0 -#define BMI260_CMD_SOFT_RESET 0xb6 +#define BMI260_CMD_REG 0x7e +#define BMI260_CMD_FIFO_FLUSH 0xb0 +#define BMI260_CMD_SOFT_RESET 0xb6 -#define BMI260_FF_FRAME_LEN_TS 4 -#define BMI260_FF_DATA_LEN_ACC 6 -#define BMI260_FF_DATA_LEN_GYR 6 -#define BMI260_FF_DATA_LEN_MAG 8 +#define BMI260_FF_FRAME_LEN_TS 4 +#define BMI260_FF_DATA_LEN_ACC 6 +#define BMI260_FF_DATA_LEN_GYR 6 +#define BMI260_FF_DATA_LEN_MAG 8 /* Root mean square noise of 100Hz accelerometer, units: ug */ -#define BMI260_ACCEL_RMS_NOISE_100HZ 1060 +#define BMI260_ACCEL_RMS_NOISE_100HZ 1060 #if defined(CONFIG_ZEPHYR) #if DT_NODE_EXISTS(DT_ALIAS(bmi260_int)) @@ -343,9 +343,9 @@ * bmi260-int = &base_accel; * }; */ -#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \ +#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ACCELGYRO_BMI260_H */ diff --git a/include/driver/accelgyro_bmi260_public.h b/include/driver/accelgyro_bmi260_public.h index 9b93ef65ae..33fc55300d 100644 --- a/include/driver/accelgyro_bmi260_public.h +++ b/include/driver/accelgyro_bmi260_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,7 +18,7 @@ */ /* I2C addresses */ -#define BMI260_ADDR0_FLAGS 0x68 +#define BMI260_ADDR0_FLAGS 0x68 extern const struct accelgyro_drv bmi260_drv; diff --git a/include/driver/accelgyro_bmi_common.h b/include/driver/accelgyro_bmi_common.h index 6e1ed122b3..371d3d97ce 100644 --- a/include/driver/accelgyro_bmi_common.h +++ b/include/driver/accelgyro_bmi_common.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,18 +18,18 @@ #error "BMI must use either SPI or I2C communication" #endif -#define BMI_CONF_REG(_sensor) (0x40 + 2 * (_sensor)) -#define BMI_RANGE_REG(_sensor) (0x41 + 2 * (_sensor)) +#define BMI_CONF_REG(_sensor) (0x40 + 2 * (_sensor)) +#define BMI_RANGE_REG(_sensor) (0x41 + 2 * (_sensor)) -#define BMI_ODR_MASK 0x0F +#define BMI_ODR_MASK 0x0F /* odr = 100 / (1 << (8 - reg)) , within limit */ -#define BMI_ODR_0_78HZ 0x01 -#define BMI_ODR_100HZ 0x08 +#define BMI_ODR_0_78HZ 0x01 +#define BMI_ODR_100HZ 0x08 -#define BMI_REG_TO_ODR(_regval) \ +#define BMI_REG_TO_ODR(_regval) \ ((_regval) < BMI_ODR_100HZ ? 100000 / (1 << (8 - (_regval))) : \ - 100000 * (1 << ((_regval) - 8))) -#define BMI_ODR_TO_REG(_odr) \ + 100000 * (1 << ((_regval)-8))) +#define BMI_ODR_TO_REG(_odr) \ ((_odr) < 100000 ? (__builtin_clz(100000 / ((_odr) + 1)) - 24) : \ (39 - __builtin_clz((_odr) / 100000))) @@ -40,92 +40,97 @@ enum fifo_header { BMI_FH_CONFIG = 0x48 }; -#define BMI_FH_MODE_MASK 0xc0 -#define BMI_FH_PARM_OFFSET 2 -#define BMI_FH_PARM_MASK (0x7 << BMI_FH_PARM_OFFSET) -#define BMI_FH_EXT_MASK 0x03 +#define BMI_FH_MODE_MASK 0xc0 +#define BMI_FH_PARM_OFFSET 2 +#define BMI_FH_PARM_MASK (0x7 << BMI_FH_PARM_OFFSET) +#define BMI_FH_EXT_MASK 0x03 /* Sensor resolution in number of bits. This sensor has fixed resolution. */ -#define BMI_RESOLUTION 16 +#define BMI_RESOLUTION 16 /* Min and Max sampling frequency in mHz */ #define BMI_ACCEL_MIN_FREQ 12500 #define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000) -#define BMI_GYRO_MIN_FREQ 25000 +#define BMI_GYRO_MIN_FREQ 25000 #define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000) enum bmi_running_mode { - STANDARD_UI_9DOF_FIFO = 0, - STANDARD_UI_IMU_FIFO = 1, - STANDARD_UI_IMU = 2, - STANDARD_UI_ADVANCEPOWERSAVE = 3, - ACCEL_PEDOMETER = 4, - APPLICATION_HEAD_TRACKING = 5, - APPLICATION_NAVIGATION = 6, - APPLICATION_REMOTE_CONTROL = 7, - APPLICATION_INDOOR_NAVIGATION = 8, + STANDARD_UI_9DOF_FIFO = 0, + STANDARD_UI_IMU_FIFO = 1, + STANDARD_UI_IMU = 2, + STANDARD_UI_ADVANCEPOWERSAVE = 3, + ACCEL_PEDOMETER = 4, + APPLICATION_HEAD_TRACKING = 5, + APPLICATION_NAVIGATION = 6, + APPLICATION_REMOTE_CONTROL = 7, + APPLICATION_INDOOR_NAVIGATION = 8, }; -#define BMI_FLAG_SEC_I2C_ENABLED BIT(0) -#define BMI_FIFO_FLAG_OFFSET 4 -#define BMI_FIFO_ALL_MASK 7 - -#define BMI_GET_DATA(_s) \ - ((struct bmi_drv_data_t *)(_s)->drv_data) -#define BMI_GET_SAVED_DATA(_s) \ - (&BMI_GET_DATA(_s)->saved_data[(_s)->type]) - -#define BMI_ACC_DATA(v) (BMI160_ACC_X_L_G + \ - (v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G)) -#define BMI_GYR_DATA(v) (BMI160_GYR_X_L_G + \ - (v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G)) -#define BMI_AUX_DATA(v) (BMI160_MAG_X_L_G + \ - (v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G)) - -#define BMI_FIFO_CONFIG_0(v) (BMI160_FIFO_CONFIG_0 + \ - (v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0)) -#define BMI_FIFO_CONFIG_1(v) (BMI160_FIFO_CONFIG_1 + \ - (v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1)) -#define BMI_FIFO_SENSOR_EN(v, _sensor) (BMI160_FIFO_SENSOR_EN(_sensor) + \ - (v) * (BMI260_FIFO_SENSOR_EN(_sensor) - BMI160_FIFO_SENSOR_EN(_sensor))) - -#define BMI_TEMPERATURE_0(v) (BMI160_TEMPERATURE_0 + \ - (v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0)) -#define BMI_INVALID_TEMP 0x8000 - -#define BMI_STATUS(v) (BMI160_STATUS + \ - (v) * (BMI260_STATUS - BMI160_STATUS)) -#define BMI_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) - -#define BMI_OFFSET_ACC70(v) (BMI160_OFFSET_ACC70 + \ - (v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70)) -#define BMI_OFFSET_GYR70(v) (BMI160_OFFSET_GYR70 + \ - (v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70)) +#define BMI_FLAG_SEC_I2C_ENABLED BIT(0) +#define BMI_FIFO_FLAG_OFFSET 4 +#define BMI_FIFO_ALL_MASK 7 + +#define BMI_GET_DATA(_s) ((struct bmi_drv_data_t *)(_s)->drv_data) +#define BMI_GET_SAVED_DATA(_s) (&BMI_GET_DATA(_s)->saved_data[(_s)->type]) + +#define BMI_ACC_DATA(v) \ + (BMI160_ACC_X_L_G + (v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G)) +#define BMI_GYR_DATA(v) \ + (BMI160_GYR_X_L_G + (v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G)) +#define BMI_AUX_DATA(v) \ + (BMI160_MAG_X_L_G + (v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G)) + +#define BMI_FIFO_CONFIG_0(v) \ + (BMI160_FIFO_CONFIG_0 + \ + (v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0)) +#define BMI_FIFO_CONFIG_1(v) \ + (BMI160_FIFO_CONFIG_1 + \ + (v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1)) +#define BMI_FIFO_SENSOR_EN(v, _sensor) \ + (BMI160_FIFO_SENSOR_EN(_sensor) + \ + (v) * (BMI260_FIFO_SENSOR_EN(_sensor) - \ + BMI160_FIFO_SENSOR_EN(_sensor))) + +#define BMI_TEMPERATURE_0(v) \ + (BMI160_TEMPERATURE_0 + \ + (v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0)) +#define BMI_INVALID_TEMP 0x8000 + +#define BMI_STATUS(v) (BMI160_STATUS + (v) * (BMI260_STATUS - BMI160_STATUS)) +#define BMI_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) + +#define BMI_OFFSET_ACC70(v) \ + (BMI160_OFFSET_ACC70 + \ + (v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70)) +#define BMI_OFFSET_GYR70(v) \ + (BMI160_OFFSET_GYR70 + \ + (v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70)) /* * There is some bits in this register that differ between BMI160 and BMI260 * Only use this macro for gyro offset 9:8 (BMI_OFFSET_EN_GYR98 5:0). */ -#define BMI_OFFSET_EN_GYR98(v) (BMI160_OFFSET_EN_GYR98 + \ - (v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98)) -#define BMI_OFFSET_GYR98_MASK (BIT(6) - 1) -#define BMI_OFFSET_ACC_MULTI_MG (3900 * 1024) -#define BMI_OFFSET_ACC_DIV_MG 1000000 +#define BMI_OFFSET_EN_GYR98(v) \ + (BMI160_OFFSET_EN_GYR98 + \ + (v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98)) +#define BMI_OFFSET_GYR98_MASK (BIT(6) - 1) +#define BMI_OFFSET_ACC_MULTI_MG (3900 * 1024) +#define BMI_OFFSET_ACC_DIV_MG 1000000 #define BMI_OFFSET_GYRO_MULTI_MDS (61 * 1024) -#define BMI_OFFSET_GYRO_DIV_MDS 1000 - -#define BMI_FIFO_LENGTH_0(v) (BMI160_FIFO_LENGTH_0 + \ - (v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0)) -#define BMI_FIFO_LENGTH_MASK(v) (BMI160_FIFO_LENGTH_MASK + \ - (v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK)) -#define BMI_FIFO_DATA(v) (BMI160_FIFO_DATA + \ - (v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA)) - -#define BMI_CMD_REG(v) (BMI160_CMD_REG + \ - (v) * (BMI260_CMD_REG - BMI160_CMD_REG)) +#define BMI_OFFSET_GYRO_DIV_MDS 1000 + +#define BMI_FIFO_LENGTH_0(v) \ + (BMI160_FIFO_LENGTH_0 + \ + (v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0)) +#define BMI_FIFO_LENGTH_MASK(v) \ + (BMI160_FIFO_LENGTH_MASK + \ + (v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK)) +#define BMI_FIFO_DATA(v) \ + (BMI160_FIFO_DATA + (v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA)) + +#define BMI_CMD_REG(v) \ + (BMI160_CMD_REG + (v) * (BMI260_CMD_REG - BMI160_CMD_REG)) #define BMI_CMD_FIFO_FLUSH 0xb0 -#define BMI_ACCEL_RMS_NOISE_100HZ(v) (BMI160_ACCEL_RMS_NOISE_100HZ + \ - (v) * (BMI260_ACCEL_RMS_NOISE_100HZ - BMI160_ACCEL_RMS_NOISE_100HZ)) #define BMI_ACCEL_100HZ 100 /* @@ -145,8 +150,8 @@ int bmi_get_xyz_reg(const struct motion_sensor_t *s); * * @return Range table of the type. */ -const struct bmi_accel_param_pair *bmi_get_range_table( - const struct motion_sensor_t *s, int *psize); +const struct bmi_accel_param_pair * +bmi_get_range_table(const struct motion_sensor_t *s, int *psize); /** * @return reg value that matches the given engineering value passed in. @@ -155,8 +160,7 @@ const struct bmi_accel_param_pair *bmi_get_range_table( * outside the range of values, it returns the closest valid reg value. */ int bmi_get_reg_val(const int eng_val, const int round_up, - const struct bmi_accel_param_pair *pairs, - const int size); + const struct bmi_accel_param_pair *pairs, const int size); /** * @return engineering value that matches the given reg val @@ -168,14 +172,14 @@ int bmi_get_engineering_val(const int reg_val, /** * Read 8bit register from accelerometer. */ -int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, - const int reg, int *data_ptr); +int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, + int *data_ptr); /** * Write 8bit register from accelerometer. */ -int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, - const int reg, int data); +int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, + int data); /** * Read 16bit register from accelerometer. @@ -210,14 +214,14 @@ int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags, /* * Enable/Disable specific bit set of a 8-bit reg. */ -int bmi_enable_reg8(const struct motion_sensor_t *s, - int reg, uint8_t bits, int enable); +int bmi_enable_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits, + int enable); /* * Set specific bit set to certain value of a 8-bit reg. */ -int bmi_set_reg8(const struct motion_sensor_t *s, int reg, - uint8_t bits, int mask); +int bmi_set_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits, + int mask); /* * @s: base sensor. @@ -237,9 +241,8 @@ void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input); * @bp: current pointer in the buffer, updated when processing the header. * @ep: pointer to the end of the valid data in the buffer. */ -int bmi_decode_header(struct motion_sensor_t *accel, - enum fifo_header hdr, uint32_t last_ts, - uint8_t **bp, uint8_t *ep); +int bmi_decode_header(struct motion_sensor_t *accel, enum fifo_header hdr, + uint32_t last_ts, uint8_t **bp, uint8_t *ep); /** * Retrieve hardware FIFO from sensor, * - put data in Sensor Hub fifo. @@ -261,21 +264,19 @@ int bmi_set_range(struct motion_sensor_t *s, int range, int rnd); int bmi_get_data_rate(const struct motion_sensor_t *s); - -int bmi_get_offset(const struct motion_sensor_t *s, - int16_t *offset, int16_t *temp); +int bmi_get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp); int bmi_get_resolution(const struct motion_sensor_t *s); -#ifdef CONFIG_BODY_DETECTION -int bmi_get_rms_noise(const struct motion_sensor_t *s); -#endif +int bmi_get_rms_noise(const struct motion_sensor_t *accel, + int rms_noise_100hz_mg); -int bmi_set_scale(const struct motion_sensor_t *s, - const uint16_t *scale, int16_t temp); +int bmi_set_scale(const struct motion_sensor_t *s, const uint16_t *scale, + int16_t temp); -int bmi_get_scale(const struct motion_sensor_t *s, - uint16_t *scale, int16_t *temp); +int bmi_get_scale(const struct motion_sensor_t *s, uint16_t *scale, + int16_t *temp); /* Start/Stop the FIFO collecting events */ int bmi_enable_fifo(const struct motion_sensor_t *s, int enable); @@ -311,9 +312,8 @@ int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v); /* Set the gyroscope offset */ int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v, - int *val98_ptr); + int *val98_ptr); -int bmi_list_activities(const struct motion_sensor_t *s, - uint32_t *enabled, +int bmi_list_activities(const struct motion_sensor_t *s, uint32_t *enabled, uint32_t *disabled); #endif /* __CROS_EC_ACCELGYRO_BMI_COMMON_H */ diff --git a/include/driver/accelgyro_bmi_common_public.h b/include/driver/accelgyro_bmi_common_public.h index 52814c71bf..b3965d4dc5 100644 --- a/include/driver/accelgyro_bmi_common_public.h +++ b/include/driver/accelgyro_bmi_common_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,14 +10,14 @@ /* Min and Max sampling frequency in mHz */ #define BMI_ACCEL_MIN_FREQ 12500 #define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000) -#define BMI_GYRO_MIN_FREQ 25000 +#define BMI_GYRO_MIN_FREQ 25000 #define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000) struct bmi_drv_data_t { struct accelgyro_saved_data_t saved_data[3]; - uint8_t flags; - uint8_t enabled_activities; - uint8_t disabled_activities; + uint8_t flags; + uint8_t enabled_activities; + uint8_t disabled_activities; #ifdef CONFIG_MAG_BMI_BMM150 struct bmm150_private_data compass; #endif @@ -26,7 +26,6 @@ struct bmi_drv_data_t { enum motionsensor_orientation orientation; enum motionsensor_orientation last_orientation; #endif - }; #endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H */ diff --git a/include/driver/accelgyro_lsm6dso_public.h b/include/driver/accelgyro_lsm6dso_public.h index 65e98bccec..f2c1b2bc4e 100644 --- a/include/driver/accelgyro_lsm6dso_public.h +++ b/include/driver/accelgyro_lsm6dso_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,12 +14,11 @@ * 7-bit address is 110101xb. Where 'x' is determined * by the voltage on the ADDR pin */ -#define LSM6DSO_ADDR0_FLAGS 0x6a -#define LSM6DSO_ADDR1_FLAGS 0x6b +#define LSM6DSO_ADDR0_FLAGS 0x6a +#define LSM6DSO_ADDR1_FLAGS 0x6b /* Absolute maximum rate for Acc and Gyro sensors */ -#define LSM6DSO_ODR_MIN_VAL 13000 -#define LSM6DSO_ODR_MAX_VAL \ - MOTION_MAX_SENSOR_FREQUENCY(416000, 13000) +#define LSM6DSO_ODR_MIN_VAL 13000 +#define LSM6DSO_ODR_MAX_VAL MOTION_MAX_SENSOR_FREQUENCY(416000, 13000) #endif /* __CROS_EC_ACCELGYRO_LSM6DSO_PUBLIC_H */ diff --git a/include/driver/als_tcs3400.h b/include/driver/als_tcs3400.h index 0748befa71..ab28d7e7d5 100644 --- a/include/driver/als_tcs3400.h +++ b/include/driver/als_tcs3400.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -11,70 +11,69 @@ #include "driver/als_tcs3400_public.h" /* ID for TCS34001 and TCS34005 */ -#define TCS340015_DEVICE_ID 0x90 +#define TCS340015_DEVICE_ID 0x90 /* ID for TCS34003 and TCS34007 */ -#define TCS340037_DEVICE_ID 0x93 +#define TCS340037_DEVICE_ID 0x93 /* Register Map */ -#define TCS_I2C_ENABLE 0x80 /* R/W Enables states and interrupts */ -#define TCS_I2C_ATIME 0x81 /* R/W RGBC integration time */ -#define TCS_I2C_WTIME 0x83 /* R/W Wait time */ -#define TCS_I2C_AILTL 0x84 /* R/W Clear irq low threshold low byte */ -#define TCS_I2C_AILTH 0x85 /* R/W Clear irq low threshold high byte */ -#define TCS_I2C_AIHTL 0x86 /* R/W Clear irq high threshold low byte */ -#define TCS_I2C_AIHTH 0x87 /* R/W Clear irq high threshold high byte */ -#define TCS_I2C_PERS 0x8C /* R/W Interrupt persistence filter */ -#define TCS_I2C_CONFIG 0x8D /* R/W Configuration */ -#define TCS_I2C_CONTROL 0x8F /* R/W Gain control register */ -#define TCS_I2C_AUX 0x90 /* R/W Auxiliary control register */ -#define TCS_I2C_REVID 0x91 /* R Revision ID */ -#define TCS_I2C_ID 0x92 /* R Device ID */ -#define TCS_I2C_STATUS 0x93 /* R Device status */ -#define TCS_I2C_CDATAL 0x94 /* R Clear / IR channel low data register */ -#define TCS_I2C_CDATAH 0x95 /* R Clear / IR channel high data register */ -#define TCS_I2C_RDATAL 0x96 /* R Red ADC low data register */ -#define TCS_I2C_RDATAH 0x97 /* R Red ADC high data register */ -#define TCS_I2C_GDATAL 0x98 /* R Green ADC low data register */ -#define TCS_I2C_GDATAH 0x99 /* R Green ADC high data register */ -#define TCS_I2C_BDATAL 0x9A /* R Blue ADC low data register */ -#define TCS_I2C_BDATAH 0x9B /* R Blue ADC high data register */ -#define TCS_I2C_IR 0xC0 /* R/W Access IR Channel */ -#define TCS_I2C_IFORCE 0xE4 /* W Force Interrupt */ -#define TCS_I2C_CICLEAR 0xE6 /* W Clear channel interrupt clear */ -#define TCS_I2C_AICLEAR 0xE7 /* W Clear all interrupts */ - -#define TCS_I2C_ENABLE_POWER_ON BIT(0) -#define TCS_I2C_ENABLE_ADC_ENABLE BIT(1) -#define TCS_I2C_ENABLE_WAIT_ENABLE BIT(3) -#define TCS_I2C_ENABLE_INT_ENABLE BIT(4) -#define TCS_I2C_ENABLE_SLEEP_AFTER_INT BIT(6) -#define TCS_I2C_ENABLE_MASK (TCS_I2C_ENABLE_POWER_ON | \ - TCS_I2C_ENABLE_ADC_ENABLE | \ - TCS_I2C_ENABLE_WAIT_ENABLE | \ - TCS_I2C_ENABLE_INT_ENABLE | \ - TCS_I2C_ENABLE_SLEEP_AFTER_INT) +#define TCS_I2C_ENABLE 0x80 /* R/W Enables states and interrupts */ +#define TCS_I2C_ATIME 0x81 /* R/W RGBC integration time */ +#define TCS_I2C_WTIME 0x83 /* R/W Wait time */ +#define TCS_I2C_AILTL 0x84 /* R/W Clear irq low threshold low byte */ +#define TCS_I2C_AILTH 0x85 /* R/W Clear irq low threshold high byte */ +#define TCS_I2C_AIHTL 0x86 /* R/W Clear irq high threshold low byte */ +#define TCS_I2C_AIHTH 0x87 /* R/W Clear irq high threshold high byte */ +#define TCS_I2C_PERS 0x8C /* R/W Interrupt persistence filter */ +#define TCS_I2C_CONFIG 0x8D /* R/W Configuration */ +#define TCS_I2C_CONTROL 0x8F /* R/W Gain control register */ +#define TCS_I2C_AUX 0x90 /* R/W Auxiliary control register */ +#define TCS_I2C_REVID 0x91 /* R Revision ID */ +#define TCS_I2C_ID 0x92 /* R Device ID */ +#define TCS_I2C_STATUS 0x93 /* R Device status */ +#define TCS_I2C_CDATAL 0x94 /* R Clear / IR channel low data register */ +#define TCS_I2C_CDATAH 0x95 /* R Clear / IR channel high data register */ +#define TCS_I2C_RDATAL 0x96 /* R Red ADC low data register */ +#define TCS_I2C_RDATAH 0x97 /* R Red ADC high data register */ +#define TCS_I2C_GDATAL 0x98 /* R Green ADC low data register */ +#define TCS_I2C_GDATAH 0x99 /* R Green ADC high data register */ +#define TCS_I2C_BDATAL 0x9A /* R Blue ADC low data register */ +#define TCS_I2C_BDATAH 0x9B /* R Blue ADC high data register */ +#define TCS_I2C_IR 0xC0 /* R/W Access IR Channel */ +#define TCS_I2C_IFORCE 0xE4 /* W Force Interrupt */ +#define TCS_I2C_CICLEAR 0xE6 /* W Clear channel interrupt clear */ +#define TCS_I2C_AICLEAR 0xE7 /* W Clear all interrupts */ + +#define TCS_I2C_ENABLE_POWER_ON BIT(0) +#define TCS_I2C_ENABLE_ADC_ENABLE BIT(1) +#define TCS_I2C_ENABLE_WAIT_ENABLE BIT(3) +#define TCS_I2C_ENABLE_INT_ENABLE BIT(4) +#define TCS_I2C_ENABLE_SLEEP_AFTER_INT BIT(6) +#define TCS_I2C_ENABLE_MASK \ + (TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE | \ + TCS_I2C_ENABLE_WAIT_ENABLE | TCS_I2C_ENABLE_INT_ENABLE | \ + TCS_I2C_ENABLE_SLEEP_AFTER_INT) enum tcs3400_mode { TCS3400_MODE_SUSPEND = 0, - TCS3400_MODE_IDLE = (TCS_I2C_ENABLE_POWER_ON | - TCS_I2C_ENABLE_ADC_ENABLE), - TCS3400_MODE_COLLECTING = (TCS_I2C_ENABLE_POWER_ON | - TCS_I2C_ENABLE_ADC_ENABLE | - TCS_I2C_ENABLE_INT_ENABLE), + TCS3400_MODE_IDLE = + (TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE), + TCS3400_MODE_COLLECTING = + (TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE | + TCS_I2C_ENABLE_INT_ENABLE), }; -#define TCS_I2C_CONTROL_MASK 0x03 -#define TCS_I2C_STATUS_RGBC_VALID BIT(0) -#define TCS_I2C_STATUS_ALS_IRQ BIT(4) -#define TCS_I2C_STATUS_ALS_SATURATED BIT(7) +#define TCS_I2C_CONTROL_MASK 0x03 +#define TCS_I2C_STATUS_RGBC_VALID BIT(0) +#define TCS_I2C_STATUS_ALS_IRQ BIT(4) +#define TCS_I2C_STATUS_ALS_SATURATED BIT(7) -#define TCS_I2C_AUX_ASL_INT_ENABLE BIT(5) +#define TCS_I2C_AUX_ASL_INT_ENABLE BIT(5) /* Light data resides at 0x94 thru 0x98 */ -#define TCS_DATA_START_LOCATION TCS_I2C_CDATAL -#define TCS_CLEAR_DATA_SIZE 2 -#define TCS_RGBC_DATA_SIZE 8 +#define TCS_DATA_START_LOCATION TCS_I2C_CDATAL +#define TCS_CLEAR_DATA_SIZE 2 +#define TCS_RGBC_DATA_SIZE 8 #define TCS3400_DRV_DATA(_s) ((struct als_drv_data_t *)(_s)->drv_data) #define TCS3400_RGB_DRV_DATA(_s) \ @@ -96,20 +95,20 @@ enum tcs3400_mode { * To avoid this, we require value to be <= 20% of saturation level * (TCS_GAIN_SAT_LEVEL) before allowing gain to be increased. */ -#define TCS_GAIN_ADJUST_FACTOR 5 -#define TCS_GAIN_SAT_LEVEL (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR) -#define TCS_UPSHIFT_FACTOR_N 25 /* upshift factor = 2.5 */ -#define TCS_UPSHIFT_FACTOR_D 10 -#define TCS_GAIN_UPSHIFT_LEVEL (TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D \ - / TCS_UPSHIFT_FACTOR_N) +#define TCS_GAIN_ADJUST_FACTOR 5 +#define TCS_GAIN_SAT_LEVEL (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR) +#define TCS_UPSHIFT_FACTOR_N 25 /* upshift factor = 2.5 */ +#define TCS_UPSHIFT_FACTOR_D 10 +#define TCS_GAIN_UPSHIFT_LEVEL \ + (TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D / TCS_UPSHIFT_FACTOR_N) /* * Percentage of saturation level that the auto-adjusting anti-saturation * method will drive towards. */ #define TSC_SATURATION_LOW_BAND_PERCENT 90 -#define TSC_SATURATION_LOW_BAND_LEVEL (TCS_SATURATION_LEVEL * \ - TSC_SATURATION_LOW_BAND_PERCENT / 100) +#define TSC_SATURATION_LOW_BAND_LEVEL \ + (TCS_SATURATION_LEVEL * TSC_SATURATION_LOW_BAND_PERCENT / 100) enum crbg_index { CLEAR_CRGB_IDX = 0, @@ -134,9 +133,9 @@ enum crbg_index { * tcs3400-int = &als_clear; * }; */ -#define CONFIG_ALS_TCS3400_INT_EVENT \ +#define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ALS_TCS3400_H */ diff --git a/include/driver/als_tcs3400_public.h b/include/driver/als_tcs3400_public.h index 812aeda8d3..2cf9aed45f 100644 --- a/include/driver/als_tcs3400_public.h +++ b/include/driver/als_tcs3400_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -11,34 +11,34 @@ #include "accelgyro.h" /* I2C Interface */ -#define TCS3400_I2C_ADDR_FLAGS 0x39 +#define TCS3400_I2C_ADDR_FLAGS 0x39 /* NOTE: The higher the ATIME value in reg, the shorter the accumulation time */ -#define TCS_MIN_ATIME 0x00 /* 712 ms */ -#define TCS_MAX_ATIME 0x70 /* 400 ms */ -#define TCS_ATIME_GRANULARITY 256 /* 256 atime settings */ -#define TCS_SATURATION_LEVEL 0xffff /* for 0 < atime < 0x70 */ -#define TCS_DEFAULT_ATIME TCS_MIN_ATIME /* 712 ms */ -#define TCS_CALIBRATION_ATIME TCS_MIN_ATIME -#define TCS_GAIN_UPSHIFT_ATIME TCS_MAX_ATIME +#define TCS_MIN_ATIME 0x00 /* 712 ms */ +#define TCS_MAX_ATIME 0x70 /* 400 ms */ +#define TCS_ATIME_GRANULARITY 256 /* 256 atime settings */ +#define TCS_SATURATION_LEVEL 0xffff /* for 0 < atime < 0x70 */ +#define TCS_DEFAULT_ATIME TCS_MIN_ATIME /* 712 ms */ +#define TCS_CALIBRATION_ATIME TCS_MIN_ATIME +#define TCS_GAIN_UPSHIFT_ATIME TCS_MAX_ATIME /* Number of different ranges supported for atime adjustment support */ -#define TCS_MAX_ATIME_RANGES 13 -#define TCS_GAIN_TABLE_MAX_LUX 12999 -#define TCS_ATIME_GAIN_FACTOR 100 /* table values are 100x actual value */ +#define TCS_MAX_ATIME_RANGES 13 +#define TCS_GAIN_TABLE_MAX_LUX 12999 +#define TCS_ATIME_GAIN_FACTOR 100 /* table values are 100x actual value */ -#define TCS_MIN_AGAIN 0x00 /* 1x gain */ -#define TCS_MAX_AGAIN 0x03 /* 64x gain */ -#define TCS_CALIBRATION_AGAIN 0x02 /* 16x gain */ -#define TCS_DEFAULT_AGAIN TCS_CALIBRATION_AGAIN +#define TCS_MIN_AGAIN 0x00 /* 1x gain */ +#define TCS_MAX_AGAIN 0x03 /* 64x gain */ +#define TCS_CALIBRATION_AGAIN 0x02 /* 16x gain */ +#define TCS_DEFAULT_AGAIN TCS_CALIBRATION_AGAIN #define TCS_MAX_INTEGRATION_TIME 2780 /* 2780us */ -#define TCS_ATIME_DEC_STEP 5 -#define TCS_ATIME_INC_STEP TCS_GAIN_UPSHIFT_ATIME +#define TCS_ATIME_DEC_STEP 5 +#define TCS_ATIME_INC_STEP TCS_GAIN_UPSHIFT_ATIME /* Min and Max sampling frequency in mHz */ -#define TCS3400_LIGHT_MIN_FREQ 149 -#define TCS3400_LIGHT_MAX_FREQ 1000 +#define TCS3400_LIGHT_MIN_FREQ 149 +#define TCS3400_LIGHT_MAX_FREQ 1000 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= TCS3400_LIGHT_MAX_FREQ) #error "EC too slow for light sensor" #endif @@ -55,15 +55,16 @@ struct tcs_saturation_t { uint8_t again; /* Acquisition Time, controlled by the ATIME register */ - uint8_t atime; /* ATIME register setting */ + uint8_t atime; /* ATIME register setting */ }; /* tcs3400 rgb als driver data */ struct tcs3400_rgb_drv_data_t { - uint8_t calibration_mode;/* 0 = normal run mode, 1 = calibration mode */ + uint8_t calibration_mode; /* 0 = normal run mode, 1 = calibration mode + */ struct rgb_calibration_t calibration; - struct tcs_saturation_t saturation; /* saturation adjustment */ + struct tcs_saturation_t saturation; /* saturation adjustment */ }; extern const struct accelgyro_drv tcs3400_drv; diff --git a/include/driver/amd_stt.h b/include/driver/amd_stt.h index 3d382a6c0a..124b13fb00 100644 --- a/include/driver/amd_stt.h +++ b/include/driver/amd_stt.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/bc12/mt6360_public.h b/include/driver/bc12/mt6360_public.h index d2b8499e1f..fbceb74dd6 100644 --- a/include/driver/bc12/mt6360_public.h +++ b/include/driver/bc12/mt6360_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/bc12/pi3usb9201_public.h b/include/driver/bc12/pi3usb9201_public.h index 643952ab4a..20788aa5e3 100644 --- a/include/driver/bc12/pi3usb9201_public.h +++ b/include/driver/bc12/pi3usb9201_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/charger/isl923x_public.h b/include/driver/charger/isl923x_public.h index 2ee5f62cdb..c5d38f75c7 100644 --- a/include/driver/charger/isl923x_public.h +++ b/include/driver/charger/isl923x_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -11,7 +11,7 @@ #include "common.h" #include "stdbool.h" -#define ISL923X_ADDR_FLAGS (0x09) +#define ISL923X_ADDR_FLAGS (0x09) extern const struct charger_drv isl923x_drv; diff --git a/include/driver/charger/isl9241_public.h b/include/driver/charger/isl9241_public.h index 342f627bd3..be586f39c3 100644 --- a/include/driver/charger/isl9241_public.h +++ b/include/driver/charger/isl9241_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -8,10 +8,10 @@ #ifndef __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H #define __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H -#define ISL9241_ADDR_FLAGS 0x09 +#define ISL9241_ADDR_FLAGS 0x09 /* Default minimum VIN voltage controlled by ISL9241_REG_VIN_VOLTAGE */ -#define ISL9241_BC12_MIN_VOLTAGE 4096 +#define ISL9241_BC12_MIN_VOLTAGE 4096 extern const struct charger_drv isl9241_drv; @@ -33,9 +33,9 @@ int isl9241_set_ac_prochot(int chgnum, int ma); */ int isl9241_set_dc_prochot(int chgnum, int ma); -#define ISL9241_AC_PROCHOT_CURRENT_MIN 128 /* mA */ -#define ISL9241_AC_PROCHOT_CURRENT_MAX 6400 /* mA */ -#define ISL9241_DC_PROCHOT_CURRENT_MIN 256 /* mA */ -#define ISL9241_DC_PROCHOT_CURRENT_MAX 12800 /* mA */ +#define ISL9241_AC_PROCHOT_CURRENT_MIN 128 /* mA */ +#define ISL9241_AC_PROCHOT_CURRENT_MAX 6400 /* mA */ +#define ISL9241_DC_PROCHOT_CURRENT_MIN 256 /* mA */ +#define ISL9241_DC_PROCHOT_CURRENT_MAX 12800 /* mA */ #endif /* __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H */ diff --git a/include/driver/ln9310.h b/include/driver/ln9310.h index a5d3cf8922..dacdf95a91 100644 --- a/include/driver/ln9310.h +++ b/include/driver/ln9310.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,192 +12,192 @@ #include "gpio_signal.h" /* I2C address */ -#define LN9310_I2C_ADDR_0_FLAGS 0x72 -#define LN9310_I2C_ADDR_1_FLAGS 0x73 -#define LN9310_I2C_ADDR_2_FLAGS 0x53 -#define LN9310_I2C_ADDR_3_FLAGS 0x54 +#define LN9310_I2C_ADDR_0_FLAGS 0x72 +#define LN9310_I2C_ADDR_1_FLAGS 0x73 +#define LN9310_I2C_ADDR_2_FLAGS 0x53 +#define LN9310_I2C_ADDR_3_FLAGS 0x54 /* Registers */ -#define LN9310_REG_CHIP_ID 0x00 -#define LN9310_CHIP_ID 0x44 -#define LN9310_REG_INT1 0x01 -#define LN9310_REG_INT1_MSK 0x02 -#define LN9310_INT1_TIMER BIT(0) -#define LN9310_INT1_INFET BIT(1) -#define LN9310_INT1_TEMP BIT(2) -#define LN9310_INT1_REV_CURR BIT(3) -#define LN9310_INT1_MODE BIT(4) -#define LN9310_INT1_ALARM BIT(5) -#define LN9310_INT1_OK BIT(6) -#define LN9310_INT1_FAULT BIT(7) - -#define LN9310_REG_SYSGPIO_MSK 0x03 - -#define LN9310_REG_SYS_STS 0x04 -#define LN9310_SYS_STANDBY BIT(0) -#define LN9310_SYS_SWITCHING21_ACTIVE BIT(1) -#define LN9310_SYS_SWITCHING31_ACTIVE BIT(2) -#define LN9310_SYS_BYPASS_ACTIVE BIT(3) -#define LN9310_SYS_INFET_OK BIT(4) -#define LN9310_SYS_SC_OUT_SWITCH_OK BIT(5) -#define LN9310_SYS_INFET_OUT_SWITCH_OK BIT(6) - -#define LN9310_REG_SAFETY_STS 0x05 -#define LN9310_REG_FAULT1_STS 0x06 -#define LN9310_REG_FAULT2_STS 0x07 - -#define LN9310_REG_PWR_CTRL 0x1d -#define LN9310_PWR_OP_MODE0 BIT(0) -#define LN9310_PWR_OP_MODE1 BIT(1) -#define LN9310_PWR_INFET_EN BIT(2) -#define LN9310_PWR_INFET_AUTO_MODE BIT(3) -#define LN9310_PWR_REVERSE_MODE BIT(4) -#define LN9310_PWR_VIN_OV_IGNORE BIT(5) -#define LN9310_PWR_OP_MANUAL_UPDATE BIT(6) -#define LN9310_PWR_FORCE_INSNS_EN BIT(7) -#define LN9310_PWR_OP_MODE_MASK 0x03 -#define LN9310_PWR_OP_MODE_DISABLED 0x00 -#define LN9310_PWR_OP_MODE_BYPASS 0x01 -#define LN9310_PWR_OP_MODE_SWITCH21 0x02 -#define LN9310_PWR_OP_MODE_SWITCH31 0x03 -#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK 0x40 -#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF 0x00 -#define LN9310_PWR_INFET_AUTO_MODE_MASK 0x08 -#define LN9310_PWR_INFET_AUTO_MODE_ON 0x08 -#define LN9310_PWR_INFET_AUTO_MODE_OFF 0x00 - -#define LN9310_REG_SYS_CTRL 0x1e - -#define LN9310_REG_STARTUP_CTRL 0x1f -#define LN9310_STARTUP_STANDBY_EN BIT(0) -#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR BIT(3) - -#define LN9310_REG_IIN_CTRL 0x20 -#define LN9310_REG_VIN_CTRL 0x21 - -#define LN9310_REG_TRACK_CTRL 0x22 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN BIT(7) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2 BIT(6) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1 BIT(5) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0 BIT(4) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK 0x80 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON 0x80 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF 0x00 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK 0x70 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V 0x10 - -#define LN9310_REG_OCP_CTRL 0x23 - -#define LN9310_REG_TIMER_CTRL 0x24 -#define LN9310_TIMER_OP_SELF_SYNC_EN BIT(3) -#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK 0x08 -#define LN9310_TIMER_OP_SELF_SYNC_EN_ON 0x08 - -#define LN9310_REG_RECOVERY_CTRL 0x25 - -#define LN9310_REG_LB_CTRL 0x26 -#define LN9310_LB_MIN_FREQ_EN BIT(2) -#define LN9310_LB_DELTA_MASK 0x38 -#define LN9310_LB_DELTA_2S 0x20 -#define LN9310_LB_DELTA_3S 0x20 - -#define LN9310_REG_SC_OUT_OV_CTRL 0x29 -#define LN9310_REG_STS_CTRL 0x2d - -#define LN9310_REG_MODE_CHANGE_CFG 0x2e -#define LN9310_MODE_TM_VIN_OV_CFG0 BIT(0) -#define LN9310_MODE_TM_VIN_OV_CFG1 BIT(1) -#define LN9310_MODE_TM_VIN_OV_CFG2 BIT(2) -#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0 BIT(3) -#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1 BIT(4) -#define LN9310_MODE_TM_TRACK_CFG0 BIT(5) -#define LN9310_MODE_TM_TRACK_CFG1 BIT(6) -#define LN9310_MODE_FORCE_MODE_CFG BIT(7) -#define LN9310_MODE_TM_TRACK_MASK 0x60 -#define LN9310_MODE_TM_TRACK_BYPASS 0x00 -#define LN9310_MODE_TM_TRACK_SWITCH21 0x20 -#define LN9310_MODE_TM_TRACK_SWITCH31 0x60 -#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK 0x18 -#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS 0x0 -#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21 0x08 -#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 0x18 -#define LN9310_MODE_TM_VIN_OV_CFG_MASK 0x07 -#define LN9310_MODE_TM_VIN_OV_CFG_2S 0x0 /* 14V */ -#define LN9310_MODE_TM_VIN_OV_CFG_3S 0x2 /* 20V */ - -#define LN9310_REG_SPARE_0 0x2A -#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK 0x40 -#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON 0x40 -#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK 0x10 -#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON 0x10 - -#define LN9310_REG_SC_DITHER_CTRL 0x2f - -#define LN9310_REG_LION_CTRL 0x30 -#define LN9310_LION_CTRL_MASK 0xFF -#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM 0xAA -#define LN9310_LION_CTRL_UNLOCK 0x5B +#define LN9310_REG_CHIP_ID 0x00 +#define LN9310_CHIP_ID 0x44 +#define LN9310_REG_INT1 0x01 +#define LN9310_REG_INT1_MSK 0x02 +#define LN9310_INT1_TIMER BIT(0) +#define LN9310_INT1_INFET BIT(1) +#define LN9310_INT1_TEMP BIT(2) +#define LN9310_INT1_REV_CURR BIT(3) +#define LN9310_INT1_MODE BIT(4) +#define LN9310_INT1_ALARM BIT(5) +#define LN9310_INT1_OK BIT(6) +#define LN9310_INT1_FAULT BIT(7) + +#define LN9310_REG_SYSGPIO_MSK 0x03 + +#define LN9310_REG_SYS_STS 0x04 +#define LN9310_SYS_STANDBY BIT(0) +#define LN9310_SYS_SWITCHING21_ACTIVE BIT(1) +#define LN9310_SYS_SWITCHING31_ACTIVE BIT(2) +#define LN9310_SYS_BYPASS_ACTIVE BIT(3) +#define LN9310_SYS_INFET_OK BIT(4) +#define LN9310_SYS_SC_OUT_SWITCH_OK BIT(5) +#define LN9310_SYS_INFET_OUT_SWITCH_OK BIT(6) + +#define LN9310_REG_SAFETY_STS 0x05 +#define LN9310_REG_FAULT1_STS 0x06 +#define LN9310_REG_FAULT2_STS 0x07 + +#define LN9310_REG_PWR_CTRL 0x1d +#define LN9310_PWR_OP_MODE0 BIT(0) +#define LN9310_PWR_OP_MODE1 BIT(1) +#define LN9310_PWR_INFET_EN BIT(2) +#define LN9310_PWR_INFET_AUTO_MODE BIT(3) +#define LN9310_PWR_REVERSE_MODE BIT(4) +#define LN9310_PWR_VIN_OV_IGNORE BIT(5) +#define LN9310_PWR_OP_MANUAL_UPDATE BIT(6) +#define LN9310_PWR_FORCE_INSNS_EN BIT(7) +#define LN9310_PWR_OP_MODE_MASK 0x03 +#define LN9310_PWR_OP_MODE_DISABLED 0x00 +#define LN9310_PWR_OP_MODE_BYPASS 0x01 +#define LN9310_PWR_OP_MODE_SWITCH21 0x02 +#define LN9310_PWR_OP_MODE_SWITCH31 0x03 +#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK 0x40 +#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF 0x00 +#define LN9310_PWR_INFET_AUTO_MODE_MASK 0x08 +#define LN9310_PWR_INFET_AUTO_MODE_ON 0x08 +#define LN9310_PWR_INFET_AUTO_MODE_OFF 0x00 + +#define LN9310_REG_SYS_CTRL 0x1e + +#define LN9310_REG_STARTUP_CTRL 0x1f +#define LN9310_STARTUP_STANDBY_EN BIT(0) +#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR BIT(3) + +#define LN9310_REG_IIN_CTRL 0x20 +#define LN9310_REG_VIN_CTRL 0x21 + +#define LN9310_REG_TRACK_CTRL 0x22 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN BIT(7) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2 BIT(6) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1 BIT(5) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0 BIT(4) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK 0x80 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON 0x80 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF 0x00 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK 0x70 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V 0x10 + +#define LN9310_REG_OCP_CTRL 0x23 + +#define LN9310_REG_TIMER_CTRL 0x24 +#define LN9310_TIMER_OP_SELF_SYNC_EN BIT(3) +#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK 0x08 +#define LN9310_TIMER_OP_SELF_SYNC_EN_ON 0x08 + +#define LN9310_REG_RECOVERY_CTRL 0x25 + +#define LN9310_REG_LB_CTRL 0x26 +#define LN9310_LB_MIN_FREQ_EN BIT(2) +#define LN9310_LB_DELTA_MASK 0x38 +#define LN9310_LB_DELTA_2S 0x20 +#define LN9310_LB_DELTA_3S 0x20 + +#define LN9310_REG_SC_OUT_OV_CTRL 0x29 +#define LN9310_REG_STS_CTRL 0x2d + +#define LN9310_REG_MODE_CHANGE_CFG 0x2e +#define LN9310_MODE_TM_VIN_OV_CFG0 BIT(0) +#define LN9310_MODE_TM_VIN_OV_CFG1 BIT(1) +#define LN9310_MODE_TM_VIN_OV_CFG2 BIT(2) +#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0 BIT(3) +#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1 BIT(4) +#define LN9310_MODE_TM_TRACK_CFG0 BIT(5) +#define LN9310_MODE_TM_TRACK_CFG1 BIT(6) +#define LN9310_MODE_FORCE_MODE_CFG BIT(7) +#define LN9310_MODE_TM_TRACK_MASK 0x60 +#define LN9310_MODE_TM_TRACK_BYPASS 0x00 +#define LN9310_MODE_TM_TRACK_SWITCH21 0x20 +#define LN9310_MODE_TM_TRACK_SWITCH31 0x60 +#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK 0x18 +#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS 0x0 +#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21 0x08 +#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 0x18 +#define LN9310_MODE_TM_VIN_OV_CFG_MASK 0x07 +#define LN9310_MODE_TM_VIN_OV_CFG_2S 0x0 /* 14V */ +#define LN9310_MODE_TM_VIN_OV_CFG_3S 0x2 /* 20V */ + +#define LN9310_REG_SPARE_0 0x2A +#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK 0x40 +#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON 0x40 +#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK 0x10 +#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON 0x10 + +#define LN9310_REG_SC_DITHER_CTRL 0x2f + +#define LN9310_REG_LION_CTRL 0x30 +#define LN9310_LION_CTRL_MASK 0xFF +#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM 0xAA +#define LN9310_LION_CTRL_UNLOCK 0x5B /* * value changed to 0x22 to distinguish from reset value of 0x00 * 0x22 and 0x00 are functionally equivalent within LN9310 */ -#define LN9310_LION_CTRL_LOCK 0x22 - -#define LN9310_REG_CFG_0 0x3C -#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK 0x20 -#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON 0x20 - -#define LN9310_REG_CFG_4 0x40 -#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG BIT(2) -#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK BIT(3) -#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 0x04 -#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK 0x08 -#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK 0xC0 -#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 0x04 -#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF 0x00 -#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST 0x00 - -#define LN9310_REG_CFG_5 0x41 -#define LN9310_CFG_5_INGATE_PD_EN_MASK 0xC0 -#define LN9310_CFG_5_INGATE_PD_EN_OFF 0x00 -#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK 0x30 -#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST 0x00 - -#define LN9310_REG_TEST_MODE_CTRL 0x46 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK 0x40 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON 0x40 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF 0x00 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK 0x20 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON 0x20 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF 0x00 - -#define LN9310_REG_FORCE_SC21_CTRL_1 0x49 -#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK 0xFF -#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON 0x59 -#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF 0x40 - -#define LN9310_REG_FORCE_SC21_CTRL_2 0x4A -#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK 0x80 -#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON 0x80 -#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF 0x00 - -#define LN9310_REG_SWAP_CTRL_0 0x58 -#define LN9310_REG_SWAP_CTRL_1 0x59 -#define LN9310_REG_SWAP_CTRL_2 0x5A -#define LN9310_REG_SWAP_CTRL_3 0x5B - -#define LN9310_REG_BC_STS_B 0x51 -#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK BIT(5) -#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK 0x20 - -#define LN9310_REG_BC_STS_C 0x52 -#define LN9310_BC_STS_C_CHIP_REV_MASK 0xF0 -#define LN9310_BC_STS_C_CHIP_REV_FIXED 0x40 +#define LN9310_LION_CTRL_LOCK 0x22 + +#define LN9310_REG_CFG_0 0x3C +#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK 0x20 +#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON 0x20 + +#define LN9310_REG_CFG_4 0x40 +#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG BIT(2) +#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK BIT(3) +#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 0x04 +#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK 0x08 +#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK 0xC0 +#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 0x04 +#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF 0x00 +#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST 0x00 + +#define LN9310_REG_CFG_5 0x41 +#define LN9310_CFG_5_INGATE_PD_EN_MASK 0xC0 +#define LN9310_CFG_5_INGATE_PD_EN_OFF 0x00 +#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK 0x30 +#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST 0x00 + +#define LN9310_REG_TEST_MODE_CTRL 0x46 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK 0x40 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON 0x40 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF 0x00 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK 0x20 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON 0x20 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF 0x00 + +#define LN9310_REG_FORCE_SC21_CTRL_1 0x49 +#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK 0xFF +#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON 0x59 +#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF 0x40 + +#define LN9310_REG_FORCE_SC21_CTRL_2 0x4A +#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK 0x80 +#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON 0x80 +#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF 0x00 + +#define LN9310_REG_SWAP_CTRL_0 0x58 +#define LN9310_REG_SWAP_CTRL_1 0x59 +#define LN9310_REG_SWAP_CTRL_2 0x5A +#define LN9310_REG_SWAP_CTRL_3 0x5B + +#define LN9310_REG_BC_STS_B 0x51 +#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK BIT(5) +#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK 0x20 + +#define LN9310_REG_BC_STS_C 0x52 +#define LN9310_BC_STS_C_CHIP_REV_MASK 0xF0 +#define LN9310_BC_STS_C_CHIP_REV_FIXED 0x40 /* LN9310 Timing definition */ -#define LN9310_CDC_DELAY 120 /* 120us */ -#define LN9310_CFLY_PRECHARGE_DELAY (12*MSEC) -#define LN9310_CFLY_PRECHARGE_TIMEOUT (100*MSEC) +#define LN9310_CDC_DELAY 120 /* 120us */ +#define LN9310_CFLY_PRECHARGE_DELAY (12 * MSEC) +#define LN9310_CFLY_PRECHARGE_TIMEOUT (100 * MSEC) /* LN9310 Driver Configuration */ #define LN9310_INIT_RETRY_COUNT 3 diff --git a/include/driver/mag_bmm150.h b/include/driver/mag_bmm150.h index 9f517f8097..0325e6c5fc 100644 --- a/include/driver/mag_bmm150.h +++ b/include/driver/mag_bmm150.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,68 +11,68 @@ #include "accelgyro.h" #include "mag_cal.h" -#define BMM150_ADDR0_FLAGS 0x10 -#define BMM150_ADDR1_FLAGS 0x11 -#define BMM150_ADDR2_FLAGS 0x12 -#define BMM150_ADDR3_FLAGS 0x13 - -#define BMM150_CHIP_ID 0x40 -#define BMM150_CHIP_ID_MAJOR 0x32 - -#define BMM150_BASE_DATA 0x42 - -#define BMM150_INT_STATUS 0x4a -#define BMM150_PWR_CTRL 0x4b -#define BMM150_SRST (BIT(7) | BIT(1)) -#define BMM150_PWR_ON BIT(0) - -#define BMM150_OP_CTRL 0x4c -#define BMM150_OP_MODE_OFFSET 1 -#define BMM150_OP_MODE_MASK 3 -#define BMM150_OP_MODE_NORMAL 0x00 -#define BMM150_OP_MODE_FORCED 0x01 -#define BMM150_OP_MODE_SLEEP 0x03 - -#define BMM150_INT_CTRL 0x4d - -#define BMM150_REPXY 0x51 -#define BMM150_LOW_POWER_nXY 3 -#define BMM150_REGULAR_nXY 9 -#define BMM150_ENHANCED_nXY 15 -#define BMM150_HIGH_ACCURACY_nXY 47 -#define BMM150_SPECIAL_nXY 75 -#define BMM150_REPZ 0x52 -#define BMM150_LOW_POWER_nZ 3 -#define BMM150_REGULAR_nZ 15 -#define BMM150_ENHANCED_nZ 27 -#define BMM150_HIGH_ACCURACY_nZ 83 -#define BMM150_SPECIAL_nZ 27 +#define BMM150_ADDR0_FLAGS 0x10 +#define BMM150_ADDR1_FLAGS 0x11 +#define BMM150_ADDR2_FLAGS 0x12 +#define BMM150_ADDR3_FLAGS 0x13 + +#define BMM150_CHIP_ID 0x40 +#define BMM150_CHIP_ID_MAJOR 0x32 + +#define BMM150_BASE_DATA 0x42 + +#define BMM150_INT_STATUS 0x4a +#define BMM150_PWR_CTRL 0x4b +#define BMM150_SRST (BIT(7) | BIT(1)) +#define BMM150_PWR_ON BIT(0) + +#define BMM150_OP_CTRL 0x4c +#define BMM150_OP_MODE_OFFSET 1 +#define BMM150_OP_MODE_MASK 3 +#define BMM150_OP_MODE_NORMAL 0x00 +#define BMM150_OP_MODE_FORCED 0x01 +#define BMM150_OP_MODE_SLEEP 0x03 + +#define BMM150_INT_CTRL 0x4d + +#define BMM150_REPXY 0x51 +#define BMM150_LOW_POWER_nXY 3 +#define BMM150_REGULAR_nXY 9 +#define BMM150_ENHANCED_nXY 15 +#define BMM150_HIGH_ACCURACY_nXY 47 +#define BMM150_SPECIAL_nXY 75 +#define BMM150_REPZ 0x52 +#define BMM150_LOW_POWER_nZ 3 +#define BMM150_REGULAR_nZ 15 +#define BMM150_ENHANCED_nZ 27 +#define BMM150_HIGH_ACCURACY_nZ 83 +#define BMM150_SPECIAL_nZ 27 #define BMM150_REP(_preset, _axis) CONCAT4(BMM150_, _preset, _n, _axis) /* Hidden registers for RHALL calculation */ -#define BMM150_REGA_DIG_X1 0x5d -#define BMM150_REGA_DIG_Y1 0x5e -#define BMM150_REGA_DIG_Z4_LSB 0x62 -#define BMM150_REGA_DIG_Z4_MSB 0x63 -#define BMM150_REGA_DIG_X2 0x64 -#define BMM150_REGA_DIG_Y2 0x65 -#define BMM150_REGA_DIG_Z2_LSB 0x68 -#define BMM150_REGA_DIG_Z2_MSB 0x69 -#define BMM150_REGA_DIG_Z1_LSB 0x6a -#define BMM150_REGA_DIG_Z1_MSB 0x6b +#define BMM150_REGA_DIG_X1 0x5d +#define BMM150_REGA_DIG_Y1 0x5e +#define BMM150_REGA_DIG_Z4_LSB 0x62 +#define BMM150_REGA_DIG_Z4_MSB 0x63 +#define BMM150_REGA_DIG_X2 0x64 +#define BMM150_REGA_DIG_Y2 0x65 +#define BMM150_REGA_DIG_Z2_LSB 0x68 +#define BMM150_REGA_DIG_Z2_MSB 0x69 +#define BMM150_REGA_DIG_Z1_LSB 0x6a +#define BMM150_REGA_DIG_Z1_MSB 0x6b #define BMM150_REGA_DIG_XYZ1_LSB 0x6c #define BMM150_REGA_DIG_XYZ1_MSB 0x6d -#define BMM150_REGA_DIG_Z3_LSB 0x6e -#define BMM150_REGA_DIG_Z3_MSB 0x6f -#define BMM150_REGA_DIG_XY2 0x70 -#define BMM150_REGA_DIG_XY1 0x71 +#define BMM150_REGA_DIG_Z3_LSB 0x6e +#define BMM150_REGA_DIG_Z3_MSB 0x6f +#define BMM150_REGA_DIG_XY2 0x70 +#define BMM150_REGA_DIG_XY1 0x71 /* Overflow */ -#define BMM150_FLIP_OVERFLOW_ADCVAL (-4096) -#define BMM150_HALL_OVERFLOW_ADCVAL (-16384) -#define BMM150_OVERFLOW_OUTPUT (0x8000) +#define BMM150_FLIP_OVERFLOW_ADCVAL (-4096) +#define BMM150_HALL_OVERFLOW_ADCVAL (-16384) +#define BMM150_OVERFLOW_OUTPUT (0x8000) /* Min and Max sampling frequency in mHz */ #define BMM150_MAG_MIN_FREQ 781 @@ -84,8 +84,9 @@ * * To be safe, declare only 75% of the value. */ -#define __BMM150_MAG_MAX_FREQ(_preset) (750000000 / \ - (145 * BMM150_REP(_preset, XY) + 500 * BMM150_REP(_preset, Z) + 980)) +#define __BMM150_MAG_MAX_FREQ(_preset) \ + (750000000 / \ + (145 * BMM150_REP(_preset, XY) + 500 * BMM150_REP(_preset, Z) + 980)) #if (__BMM150_MAG_MAX_FREQ(SPECIAL) > CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ) #error "EC too slow for magnetometer" @@ -93,34 +94,32 @@ struct bmm150_comp_registers { /* Local copy of the compensation registers. */ - int8_t dig1[2]; - int8_t dig2[2]; + int8_t dig1[2]; + int8_t dig2[2]; - uint16_t dig_z1; - int16_t dig_z2; - int16_t dig_z3; - int16_t dig_z4; + uint16_t dig_z1; + int16_t dig_z2; + int16_t dig_z3; + int16_t dig_z4; - uint8_t dig_xy1; - int8_t dig_xy2; + uint8_t dig_xy1; + int8_t dig_xy2; - uint16_t dig_xyz1; + uint16_t dig_xyz1; }; struct bmm150_private_data { /* lsm6dsm_data union requires cal be first element */ - struct mag_cal_t cal; + struct mag_cal_t cal; struct bmm150_comp_registers comp; }; #ifdef CONFIG_MAG_BMI_BMM150 #include "accelgyro_bmi_common.h" -#define BMM150_COMP_REG(_s) \ - (&BMI_GET_DATA(_s)->compass.comp) +#define BMM150_COMP_REG(_s) (&BMI_GET_DATA(_s)->compass.comp) -#define BMM150_CAL(_s) \ - (&BMI_GET_DATA(_s)->compass.cal) +#define BMM150_CAL(_s) (&BMI_GET_DATA(_s)->compass.cal) /* * Behind a BMI, the BMM150 is in forced mode. Be sure to choose a frequency * compatible with BMI. @@ -137,14 +136,11 @@ struct bmm150_private_data { int bmm150_init(struct motion_sensor_t *s); /* Command to normalize and apply temperature compensation */ -void bmm150_normalize(const struct motion_sensor_t *s, - intv3_t v, +void bmm150_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data); -int bmm150_set_offset(const struct motion_sensor_t *s, - const intv3_t offset); +int bmm150_set_offset(const struct motion_sensor_t *s, const intv3_t offset); -int bmm150_get_offset(const struct motion_sensor_t *s, - intv3_t offset); +int bmm150_get_offset(const struct motion_sensor_t *s, intv3_t offset); #endif /* __CROS_EC_MAG_BMM150_H */ diff --git a/include/driver/ppc/aoz1380_public.h b/include/driver/ppc/aoz1380_public.h new file mode 100644 index 0000000000..aa617054fe --- /dev/null +++ b/include/driver/ppc/aoz1380_public.h @@ -0,0 +1,43 @@ +/* Copyright 2019 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * AOZ1380 USB-C Power Path Controller + * + * This is a basic TCPM controlled PPC driver. It could easily be + * renamed and repurposed to be generic, if there are other TCPM + * controlled PPC chips that are similar to the AOZ1380 + */ + +#ifndef __CROS_EC_AOZ1380_PUBLIC_H +#define __CROS_EC_AOZ1380_PUBLIC_H + +#include "usb_pd_tcpm.h" + +struct ppc_drv; +extern const struct ppc_drv aoz1380_drv; + +/** + * AOZ1380 Set VBus Source Current Limit. + * + * Using this driver requires a board_aoz1380_set_vbus_source_limit + * function due to the lack of programability of this device and + * requirement for hardware specific code to handle setting this limit. + * + * @param port The Type-C port + * @param rp The Type-C RP value + * @return EC_SUCCESS for success, otherwise error + */ +int board_aoz1380_set_vbus_source_current_limit(int port, + enum tcpc_rp_value rp); + +/** + * Interrupt Handler for the AOZ1380. + * + * @param port: The Type-C port which triggered the interrupt. + */ +void aoz1380_interrupt(int port); + +#endif /* defined(__CROS_EC_AOZ1380_H) */ diff --git a/include/driver/ppc/ktu1125_public.h b/include/driver/ppc/ktu1125_public.h index 276f8c9a99..28ecfc7c23 100644 --- a/include/driver/ppc/ktu1125_public.h +++ b/include/driver/ppc/ktu1125_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/ppc/nx20p348x_public.h b/include/driver/ppc/nx20p348x_public.h new file mode 100644 index 0000000000..145896aca1 --- /dev/null +++ b/include/driver/ppc/nx20p348x_public.h @@ -0,0 +1,32 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* TI NX20P348X USB-C Power Path Controller */ + +#ifndef __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H +#define __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H + +#include "usbc_ppc.h" + +#define NX20P3483_ADDR0_FLAGS 0x70 +#define NX20P3483_ADDR1_FLAGS 0x71 +#define NX20P3483_ADDR2_FLAGS 0x72 +#define NX20P3483_ADDR3_FLAGS 0x73 + +#define NX20P3481_ADDR0_FLAGS 0x74 +#define NX20P3481_ADDR1_FLAGS 0x75 +#define NX20P3481_ADDR2_FLAGS 0x76 +#define NX20P3481_ADDR3_FLAGS 0x77 + +extern const struct ppc_drv nx20p348x_drv; + +/** + * Interrupt Handler for the NX20P348x. + * + * @param port: The Type-C port which triggered the interrupt. + */ +void nx20p348x_interrupt(int port); + +#endif /* __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H */ diff --git a/include/driver/ppc/sn5s330_public.h b/include/driver/ppc/sn5s330_public.h index fdd60e54cb..62652d99b2 100644 --- a/include/driver/ppc/sn5s330_public.h +++ b/include/driver/ppc/sn5s330_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/ppc/syv682x_public.h b/include/driver/ppc/syv682x_public.h index 92c841f811..a97d412478 100644 --- a/include/driver/ppc/syv682x_public.h +++ b/include/driver/ppc/syv682x_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,10 +9,10 @@ #define __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H /* I2C addresses */ -#define SYV682X_ADDR0_FLAGS 0x40 -#define SYV682X_ADDR1_FLAGS 0x41 -#define SYV682X_ADDR2_FLAGS 0x42 -#define SYV682X_ADDR3_FLAGS 0x43 +#define SYV682X_ADDR0_FLAGS 0x40 +#define SYV682X_ADDR1_FLAGS 0x41 +#define SYV682X_ADDR2_FLAGS 0x42 +#define SYV682X_ADDR3_FLAGS 0x43 extern const struct ppc_drv syv682x_drv; diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h index 8c3b9eaf60..83ad32508e 100644 --- a/include/driver/retimer/anx7483_public.h +++ b/include/driver/retimer/anx7483_public.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -13,10 +13,10 @@ #include "usb_mux.h" /* I2C interface addresses */ -#define ANX7483_I2C_ADDR0_FLAGS 0x3E -#define ANX7483_I2C_ADDR1_FLAGS 0x38 -#define ANX7483_I2C_ADDR2_FLAGS 0x40 -#define ANX7483_I2C_ADDR3_FLAGS 0x44 +#define ANX7483_I2C_ADDR0_FLAGS 0x3E +#define ANX7483_I2C_ADDR1_FLAGS 0x38 +#define ANX7483_I2C_ADDR2_FLAGS 0x40 +#define ANX7483_I2C_ADDR3_FLAGS 0x44 /* Equalization tuning */ enum anx7483_eq_setting { @@ -52,9 +52,11 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me, enum anx7483_tune_pin pin, enum anx7483_eq_setting eq); -/* Configure datasheet defaults for tuning registers at this mux setting */ -enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state); +/* + * Configure datasheet defaults for tuning registers at this mux setting. + * Return int so function can be used directly for board_set. + */ +int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state); extern const struct usb_mux_driver anx7483_usb_retimer_driver; #endif /* __CROS_EC_USB_RETIMER_ANX7483_PUBLIC_H */ diff --git a/include/driver/retimer/bb_retimer.h b/include/driver/retimer/bb_retimer.h index 6a311bd2ca..460156803e 100644 --- a/include/driver/retimer/bb_retimer.h +++ b/include/driver/retimer/bb_retimer.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,44 +12,44 @@ #include "driver/retimer/bb_retimer_public.h" /* Burnside Bridge I2C Configuration Space */ -#define BB_RETIMER_REG_VENDOR_ID 0 -#define BB_RETIMER_VENDOR_ID_1 0x8086 -#define BB_RETIMER_VENDOR_ID_2 0x8087 +#define BB_RETIMER_REG_VENDOR_ID 0 +#define BB_RETIMER_VENDOR_ID_1 0x8086 +#define BB_RETIMER_VENDOR_ID_2 0x8087 -#define BB_RETIMER_REG_DEVICE_ID 1 -#ifdef CONFIG_USBC_RETIMER_INTEL_HB +#define BB_RETIMER_REG_DEVICE_ID 1 +#ifdef CONFIG_USBC_RETIMER_INTEL_HB /* HB has no Device ID field instead it is combined with Vendor ID */ -#define BB_RETIMER_DEVICE_ID 0x0D9C8087 +#define BB_RETIMER_DEVICE_ID 0x0D9C8087 #else -#define BB_RETIMER_DEVICE_ID 0x15EE +#define BB_RETIMER_DEVICE_ID 0x15EE #endif /* Connection State Register Attributes */ -#define BB_RETIMER_REG_CONNECTION_STATE 4 -#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0) -#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1) -#define BB_RETIMER_RE_TIMER_DRIVER BIT(2) -#define BB_RETIMER_USB_2_CONNECTION BIT(4) -#define BB_RETIMER_USB_3_CONNECTION BIT(5) -#define BB_RETIMER_USB_3_SPEED BIT(6) -#define BB_RETIMER_USB_DATA_ROLE BIT(7) -#define BB_RETIMER_DP_CONNECTION BIT(8) -#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10) -#define BB_RETIMER_IRQ_HPD BIT(14) -#define BB_RETIMER_HPD_LVL BIT(15) -#define BB_RETIMER_TBT_CONNECTION BIT(16) -#define BB_RETIMER_TBT_TYPE BIT(17) -#define BB_RETIMER_TBT_CABLE_TYPE BIT(18) -#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19) -#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20) -#define BB_RETIMER_ACTIVE_PASSIVE BIT(22) -#define BB_RETIMER_USB4_ENABLED BIT(23) -#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x) & 0x7) << 25) -#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x) & 0x3) << 28) - -#define BB_RETIMER_REG_TBT_CONTROL 5 -#define BB_RETIMER_REG_EXT_CONNECTION_MODE 6 - -#define BB_RETIMER_REG_COUNT 7 +#define BB_RETIMER_REG_CONNECTION_STATE 4 +#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0) +#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1) +#define BB_RETIMER_RE_TIMER_DRIVER BIT(2) +#define BB_RETIMER_USB_2_CONNECTION BIT(4) +#define BB_RETIMER_USB_3_CONNECTION BIT(5) +#define BB_RETIMER_USB_3_SPEED BIT(6) +#define BB_RETIMER_USB_DATA_ROLE BIT(7) +#define BB_RETIMER_DP_CONNECTION BIT(8) +#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10) +#define BB_RETIMER_IRQ_HPD BIT(14) +#define BB_RETIMER_HPD_LVL BIT(15) +#define BB_RETIMER_TBT_CONNECTION BIT(16) +#define BB_RETIMER_TBT_TYPE BIT(17) +#define BB_RETIMER_TBT_CABLE_TYPE BIT(18) +#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19) +#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20) +#define BB_RETIMER_ACTIVE_PASSIVE BIT(22) +#define BB_RETIMER_USB4_ENABLED BIT(23) +#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x)&0x7) << 25) +#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x)&0x3) << 28) + +#define BB_RETIMER_REG_TBT_CONTROL 5 +#define BB_RETIMER_REG_EXT_CONNECTION_MODE 7 + +#define BB_RETIMER_REG_COUNT 8 #endif /* __CROS_EC_BB_RETIMER_H */ diff --git a/include/driver/retimer/bb_retimer_public.h b/include/driver/retimer/bb_retimer_public.h index d79b051504..2d2893fb49 100644 --- a/include/driver/retimer/bb_retimer_public.h +++ b/include/driver/retimer/bb_retimer_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -56,4 +56,12 @@ __override_proto int bb_retimer_power_enable(const struct usb_mux *me, void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required); +/** + * Enable/disable the USB3 state of BB retimer + * + * @param me Pointer to USB mux + * @param enable BB retimer USB3 state to be changed + */ +void bb_retimer_set_usb3(const struct usb_mux *me, bool enable); + #endif /* __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H */ diff --git a/include/driver/retimer/ps8818_public.h b/include/driver/retimer/ps8818_public.h new file mode 100644 index 0000000000..3f0aba963b --- /dev/null +++ b/include/driver/retimer/ps8818_public.h @@ -0,0 +1,96 @@ +/* Copyright 2019 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * PS8818 retimer. + */ +#include "usb_mux.h" + +#ifndef __CROS_EC_USB_RETIMER_PS8818_H +#define __CROS_EC_USB_RETIMER_PS8818_H + +#define PS8818_I2C_ADDR_FLAGS 0x28 + +/* + * PAGE 0 Register Definitions + */ +#define PS8818_REG_PAGE0 0x00 + +#define PS8818_REG0_FLIP 0x00 +#define PS8818_FLIP_CONFIG BIT(7) +#define PS8818_FLIP_NON_RESERVED_MASK 0xE0 + +#define PS8818_REG0_MODE 0x01 +#define PS8818_MODE_DP_ENABLE BIT(7) +#define PS8818_MODE_USB_ENABLE BIT(6) +#define PS8818_MODE_NON_RESERVED_MASK 0xC0 + +#define PS8818_REG0_DPHPD_CONFIG 0x02 +#define PS8818_DPHPD_CONFIG_INHPD_DISABLE BIT(7) +#define PS8818_DPHPD_PLUGGED BIT(6) +#define PS8818_DPHPD_NON_RESERVED_MASK 0xFC + +/* + * PAGE 1 Register Definitions + */ +#define PS8818_REG_PAGE1 0x01 + +#define PS8818_REG1_APTX1EQ_10G_LEVEL 0x00 +#define PS8818_REG1_APTX2EQ_10G_LEVEL 0x02 +#define PS8818_REG1_CRX1EQ_10G_LEVEL 0x08 +#define PS8818_REG1_CRX2EQ_10G_LEVEL 0x0A +#define PS8818_REG1_APRX1_DE_LEVEL 0x0C +#define PS8818_REG1_APTX1EQ_5G_LEVEL 0x70 +#define PS8818_REG1_APTX2EQ_5G_LEVEL 0x72 +#define PS8818_REG1_CRX1EQ_5G_LEVEL 0x78 +#define PS8818_REG1_CRX2EQ_5G_LEVEL 0x7A +#define PS8818_EQ_LEVEL_UP_9DB (0) +#define PS8818_EQ_LEVEL_UP_10DB (1) +#define PS8818_EQ_LEVEL_UP_12DB (2) +#define PS8818_EQ_LEVEL_UP_13DB (3) +#define PS8818_EQ_LEVEL_UP_16DB (4) +#define PS8818_EQ_LEVEL_UP_17DB (5) +#define PS8818_EQ_LEVEL_UP_18DB (6) +#define PS8818_EQ_LEVEL_UP_19DB (7) +#define PS8818_EQ_LEVEL_UP_20DB (8) +#define PS8818_EQ_LEVEL_UP_21DB (9) +#define PS8818_EQ_LEVEL_UP_MASK (0x0F) + +#define PS8818_REG1_RX_PHY 0x6D +#define PS8818_RX_INPUT_TERM_112_OHM (0 << 6) +#define PS8818_RX_INPUT_TERM_104_OHM (1 << 6) +#define PS8818_RX_INPUT_TERM_96_OHM (2 << 6) +#define PS8818_RX_INPUT_TERM_85_OHM (3 << 6) +#define PS8818_RX_INPUT_TERM_MASK (3 << 6) + +#define PS8818_REG1_DPEQ_LEVEL 0xB6 +#define PS8818_DPEQ_LEVEL_UP_9DB (0 << 3) +#define PS8818_DPEQ_LEVEL_UP_10DB (1 << 3) +#define PS8818_DPEQ_LEVEL_UP_12DB (2 << 3) +#define PS8818_DPEQ_LEVEL_UP_13DB (3 << 3) +#define PS8818_DPEQ_LEVEL_UP_16DB (4 << 3) +#define PS8818_DPEQ_LEVEL_UP_17DB (5 << 3) +#define PS8818_DPEQ_LEVEL_UP_18DB (6 << 3) +#define PS8818_DPEQ_LEVEL_UP_19DB (7 << 3) +#define PS8818_DPEQ_LEVEL_UP_20DB (8 << 3) +#define PS8818_DPEQ_LEVEL_UP_21DB (9 << 3) +#define PS8818_DPEQ_LEVEL_UP_MASK (0x0F << 3) + +/* + * PAGE 2 Register Definitions + */ +#define PS8818_REG_PAGE2 0x02 + +#define PS8818_REG2_TX_STATUS 0x42 +#define PS8818_REG2_RX_STATUS 0x46 +#define PS8818_STATUS_NORMAL_OPERATION BIT(7) +#define PS8818_STATUS_10_GBPS BIT(5) + +extern const struct usb_mux_driver ps8818_usb_retimer_driver; + +int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data); +int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data); +int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset, + uint8_t field_mask, uint8_t set_value); + +#endif /* __CROS_EC_USB_RETIMER_PS8818_H */ diff --git a/include/driver/tcpm/anx7447_public.h b/include/driver/tcpm/anx7447_public.h new file mode 100644 index 0000000000..5ea1eebd35 --- /dev/null +++ b/include/driver/tcpm/anx7447_public.h @@ -0,0 +1,28 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Analogix Type-C port controller */ + +#ifndef __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H +#define __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H + +#include "usb_mux.h" + +#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C +#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B +#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A +#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29 + +#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F +#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37 +#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32 +#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31 + +extern const struct tcpm_drv anx7447_tcpm_drv; +extern const struct usb_mux_driver anx7447_usb_mux_driver; + +void anx7447_tcpc_update_hpd_status(const struct usb_mux *me, + mux_state_t mux_state, bool *ack_required); +#endif /* __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H */ diff --git a/include/driver/tcpm/it8xxx2_pd_public.h b/include/driver/tcpm/it8xxx2_pd_public.h index 6ad11a9555..0c28127cdb 100644 --- a/include/driver/tcpm/it8xxx2_pd_public.h +++ b/include/driver/tcpm/it8xxx2_pd_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/tcpm/ps8xxx_public.h b/include/driver/tcpm/ps8xxx_public.h index ad84f93ced..d327dee2a3 100644 --- a/include/driver/tcpm/ps8xxx_public.h +++ b/include/driver/tcpm/ps8xxx_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,12 +15,12 @@ struct usb_mux; /* I2C interface */ #define PS8XXX_I2C_ADDR1_P1_FLAGS 0x09 #define PS8XXX_I2C_ADDR1_P2_FLAGS 0x0A -#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */ -#define PS8XXX_I2C_ADDR2_FLAGS 0x1B -#define PS8XXX_I2C_ADDR3_FLAGS 0x2B -#define PS8XXX_I2C_ADDR4_FLAGS 0x4B +#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */ +#define PS8XXX_I2C_ADDR2_FLAGS 0x1B +#define PS8XXX_I2C_ADDR3_FLAGS 0x2B +#define PS8XXX_I2C_ADDR4_FLAGS 0x4B -#define PS8XXX_VENDOR_ID 0x1DA0 +#define PS8XXX_VENDOR_ID 0x1DA0 /* Minimum Delay for reset assertion */ #define PS8XXX_RESET_DELAY_MS 1 @@ -56,6 +56,7 @@ struct usb_mux; * 8705, 8755 and 8805. */ #define PS8705_PRODUCT_ID 0x8705 +#define PS8745_PRODUCT_ID 0x8745 #define PS8751_PRODUCT_ID 0x8751 #define PS8755_PRODUCT_ID 0x8755 #define PS8805_PRODUCT_ID 0x8805 @@ -75,12 +76,10 @@ extern const struct tcpm_drv ps8xxx_tcpm_drv; * * @param port TCPC port number. */ -__override_proto -uint16_t board_get_ps8xxx_product_id(int port); +__override_proto uint16_t board_get_ps8xxx_product_id(int port); void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required); + mux_state_t mux_state, bool *ack_required); #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC extern struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev; diff --git a/include/driver/tcpm/rt1715_public.h b/include/driver/tcpm/rt1715_public.h index 14fa9495e8..2f3af95443 100644 --- a/include/driver/tcpm/rt1715_public.h +++ b/include/driver/tcpm/rt1715_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/tcpm/rt1718s_public.h b/include/driver/tcpm/rt1718s_public.h new file mode 100644 index 0000000000..62bade6ab9 --- /dev/null +++ b/include/driver/tcpm/rt1718s_public.h @@ -0,0 +1,24 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Richtek Type-C port controller */ + +#ifndef __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H +#define __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H + +#define RT1718S_I2C_ADDR1_FLAGS 0x43 +#define RT1718S_I2C_ADDR2_FLAGS 0x40 + +#define RT1718S_VID 0x29CF +#define RT1718S_PID 0x1718 + +#define RT1718S_DEVICE_ID 0x04 +#define RT1718S_DEVICE_ID_ES1 0x4511 +#define RT1718S_DEVICE_ID_ES2 0x4513 + +extern const struct tcpm_drv rt1718s_tcpm_drv; +extern const struct bc12_drv rt1718s_bc12_drv; + +#endif /* __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H */ diff --git a/include/driver/tcpm/tcpci.h b/include/driver/tcpm/tcpci.h index 559b75a14f..4879f7dad1 100644 --- a/include/driver/tcpm/tcpci.h +++ b/include/driver/tcpm/tcpci.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,259 +14,250 @@ #include "usb_mux.h" #include "usb_pd_tcpm.h" -#define TCPC_REG_VENDOR_ID 0x0 -#define TCPC_REG_PRODUCT_ID 0x2 -#define TCPC_REG_BCD_DEV 0x4 -#define TCPC_REG_TC_REV 0x6 -#define TCPC_REG_PD_REV 0x8 -#define TCPC_REG_PD_INT_REV 0xa - -#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00 -#define TCPC_REG_PD_INT_REV_REV_1_0 0x10 -#define TCPC_REG_PD_INT_REV_REV_2_0 0x20 -#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff -#define TCPC_REG_PD_INT_REV_VER_1_0 0x10 -#define TCPC_REG_PD_INT_REV_VER_1_1 0x11 -#define TCPC_REG_PD_INT_REV_REV(reg) \ - ((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8) -#define TCPC_REG_PD_INT_REV_VER(reg) \ - (reg & TCOC_REG_PD_INT_REV_VER_MASK) - -#define TCPC_REG_ALERT 0x10 -#define TCPC_REG_ALERT_NONE 0x0000 -#define TCPC_REG_ALERT_MASK_ALL 0xffff -#define TCPC_REG_ALERT_VENDOR_DEF BIT(15) -#define TCPC_REG_ALERT_ALERT_EXT BIT(14) -#define TCPC_REG_ALERT_EXT_STATUS BIT(13) +#define TCPC_REG_VENDOR_ID 0x0 +#define TCPC_REG_PRODUCT_ID 0x2 +#define TCPC_REG_BCD_DEV 0x4 +#define TCPC_REG_TC_REV 0x6 +#define TCPC_REG_PD_REV 0x8 +#define TCPC_REG_PD_INT_REV 0xa + +#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00 +#define TCPC_REG_PD_INT_REV_REV_1_0 0x10 +#define TCPC_REG_PD_INT_REV_REV_2_0 0x20 +#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff +#define TCPC_REG_PD_INT_REV_VER_1_0 0x10 +#define TCPC_REG_PD_INT_REV_VER_1_1 0x11 +#define TCPC_REG_PD_INT_REV_REV(reg) ((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8) +#define TCPC_REG_PD_INT_REV_VER(reg) (reg & TCOC_REG_PD_INT_REV_VER_MASK) + +#define TCPC_REG_ALERT 0x10 +#define TCPC_REG_ALERT_NONE 0x0000 +#define TCPC_REG_ALERT_MASK_ALL 0xffff +#define TCPC_REG_ALERT_VENDOR_DEF BIT(15) +#define TCPC_REG_ALERT_ALERT_EXT BIT(14) +#define TCPC_REG_ALERT_EXT_STATUS BIT(13) #define TCPC_REG_ALERT_RX_BEGINNING BIT(12) #define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11) -#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10) -#define TCPC_REG_ALERT_FAULT BIT(9) -#define TCPC_REG_ALERT_V_ALARM_LO BIT(8) -#define TCPC_REG_ALERT_V_ALARM_HI BIT(7) -#define TCPC_REG_ALERT_TX_SUCCESS BIT(6) +#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10) +#define TCPC_REG_ALERT_FAULT BIT(9) +#define TCPC_REG_ALERT_V_ALARM_LO BIT(8) +#define TCPC_REG_ALERT_V_ALARM_HI BIT(7) +#define TCPC_REG_ALERT_TX_SUCCESS BIT(6) #define TCPC_REG_ALERT_TX_DISCARDED BIT(5) -#define TCPC_REG_ALERT_TX_FAILED BIT(4) -#define TCPC_REG_ALERT_RX_HARD_RST BIT(3) -#define TCPC_REG_ALERT_RX_STATUS BIT(2) +#define TCPC_REG_ALERT_TX_FAILED BIT(4) +#define TCPC_REG_ALERT_RX_HARD_RST BIT(3) +#define TCPC_REG_ALERT_RX_STATUS BIT(2) #define TCPC_REG_ALERT_POWER_STATUS BIT(1) -#define TCPC_REG_ALERT_CC_STATUS BIT(0) -#define TCPC_REG_ALERT_TX_COMPLETE (TCPC_REG_ALERT_TX_SUCCESS | \ - TCPC_REG_ALERT_TX_DISCARDED | \ - TCPC_REG_ALERT_TX_FAILED) +#define TCPC_REG_ALERT_CC_STATUS BIT(0) +#define TCPC_REG_ALERT_TX_COMPLETE \ + (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | \ + TCPC_REG_ALERT_TX_FAILED) -#define TCPC_REG_ALERT_MASK 0x12 -#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15) +#define TCPC_REG_ALERT_MASK 0x12 +#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15) #define TCPC_REG_POWER_STATUS_MASK 0x14 #define TCPC_REG_FAULT_STATUS_MASK 0x15 -#define TCPC_REG_EXT_STATUS_MASK 0x16 +#define TCPC_REG_EXT_STATUS_MASK 0x16 #define TCPC_REG_ALERT_EXTENDED_MASK 0x17 #define TCPC_REG_CONFIG_STD_OUTPUT 0x18 -#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) -#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) +#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) #define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0) -#define TCPC_REG_TCPC_CTRL 0x19 +#define TCPC_REG_TCPC_CTRL 0x19 #define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity) -#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg) & 0x1) +#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg)&0x1) /* * In TCPCI Rev 2.0, this bit must be set this to generate CC status alerts when * a connection is found. */ -#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6) -#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4) -#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1) - -#define TCPC_REG_ROLE_CTRL 0x1a -#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6) -#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5)|BIT(4)) -#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3)|BIT(2)) -#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1)|BIT(0)) -#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \ - ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \ - (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \ - (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \ - ((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK)) -#define TCPC_REG_ROLE_CTRL_DRP(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6) -#define TCPC_REG_ROLE_CTRL_RP(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4) -#define TCPC_REG_ROLE_CTRL_CC2(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2) -#define TCPC_REG_ROLE_CTRL_CC1(reg) \ - ((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK) - -#define TCPC_REG_FAULT_CTRL 0x1b -#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1) -#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(0) - -#define TCPC_REG_POWER_CTRL 0x1c -#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) -#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) -#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) -#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) -#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) +#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6) +#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4) +#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1) + +#define TCPC_REG_ROLE_CTRL 0x1a +#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6) +#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5) | BIT(4)) +#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3) | BIT(2)) +#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1) | BIT(0)) +#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \ + ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \ + (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \ + (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \ + ((cc1)&TCPC_REG_ROLE_CTRL_CC1_MASK)) +#define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg)&TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6) +#define TCPC_REG_ROLE_CTRL_RP(reg) (((reg)&TCPC_REG_ROLE_CTRL_RP_MASK) >> 4) +#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg)&TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2) +#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg)&TCPC_REG_ROLE_CTRL_CC1_MASK) + +#define TCPC_REG_FAULT_CTRL 0x1b +#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1) +#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(0) + +#define TCPC_REG_POWER_CTRL 0x1c +#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) +#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) +#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) +#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) +#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) #define TCPC_REG_POWER_CTRL_SET(vconn) (vconn) -#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg) & 0x1) +#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg)&0x1) -#define TCPC_REG_CC_STATUS 0x1d -#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5) -#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4) -#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3)|BIT(2)) -#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1)|BIT(0)) +#define TCPC_REG_CC_STATUS 0x1d +#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5) +#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4) +#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3) | BIT(2)) +#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1) | BIT(0)) #define TCPC_REG_CC_STATUS_SET(term, cc1, cc2) \ - ((term) << 4 | ((cc2) & 0x3) << 2 | ((cc1) & 0x3)) + ((term) << 4 | ((cc2)&0x3) << 2 | ((cc1)&0x3)) #define TCPC_REG_CC_STATUS_LOOK4CONNECTION(reg) \ - ((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5) + ((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5) #define TCPC_REG_CC_STATUS_TERM(reg) \ - (((reg) & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4) + (((reg)&TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4) #define TCPC_REG_CC_STATUS_CC2(reg) \ - (((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2) -#define TCPC_REG_CC_STATUS_CC1(reg) \ - ((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK) + (((reg)&TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2) +#define TCPC_REG_CC_STATUS_CC1(reg) ((reg)&TCPC_REG_CC_STATUS_CC1_STATE_MASK) -#define TCPC_REG_POWER_STATUS 0x1e -#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff +#define TCPC_REG_POWER_STATUS 0x1e +#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff #define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7) -#define TCPC_REG_POWER_STATUS_UNINIT BIT(6) +#define TCPC_REG_POWER_STATUS_UNINIT BIT(6) #define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4) -#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3) +#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3) #define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2) #define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0) -#define TCPC_REG_FAULT_STATUS 0x1f -#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7) -#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6) -#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5) -#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4) -#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3) -#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2) -#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1) -#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0) - -#define TCPC_REG_EXT_STATUS 0x20 -#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0) - -#define TCPC_REG_ALERT_EXT 0x21 -#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2) -#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1) -#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0) - -#define TCPC_REG_COMMAND 0x23 -#define TCPC_REG_COMMAND_WAKE_I2C 0x11 -#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33 -#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44 -#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55 -#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66 -#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77 -#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99 -#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD -#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE -#define TCPC_REG_COMMAND_I2CIDLE 0xFF - -#define TCPC_REG_DEV_CAP_1 0x24 -#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) -#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) -#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) -#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) -#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) -#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8)|BIT(9)) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8) -#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5) -#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) -#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) -#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) -#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1) -#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) - -#define TCPC_REG_DEV_CAP_2 0x26 -#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12) -#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9) - -#define TCPC_REG_STD_INPUT_CAP 0x28 -#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4)|BIT(3)) -#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2) -#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1) -#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0) - -#define TCPC_REG_STD_OUTPUT_CAP 0x29 -#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7) -#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6) -#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5) -#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4) -#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3) -#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2) -#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1) -#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0) - -#define TCPC_REG_CONFIG_EXT_1 0x2A -#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1) - -#define TCPC_REG_GENERIC_TIMER 0x2c - -#define TCPC_REG_MSG_HDR_INFO 0x2e +#define TCPC_REG_FAULT_STATUS 0x1f +#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7) +#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6) +#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5) +#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4) +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3) +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2) +#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1) +#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0) + +#define TCPC_REG_EXT_STATUS 0x20 +#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0) + +#define TCPC_REG_ALERT_EXT 0x21 +#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2) +#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1) +#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0) + +#define TCPC_REG_COMMAND 0x23 +#define TCPC_REG_COMMAND_WAKE_I2C 0x11 +#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33 +#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44 +#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55 +#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66 +#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77 +#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99 +#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD +#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE +#define TCPC_REG_COMMAND_I2CIDLE 0xFF + +#define TCPC_REG_DEV_CAP_1 0x24 +#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) +#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) +#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) +#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) +#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) +#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8) | BIT(9)) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8) +#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5) | BIT(6) | BIT(7)) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5) +#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) +#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) +#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) +#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1) +#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) + +#define TCPC_REG_DEV_CAP_2 0x26 +#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12) +#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9) + +#define TCPC_REG_STD_INPUT_CAP 0x28 +#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4) | BIT(3)) +#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2) +#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1) +#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0) + +#define TCPC_REG_STD_OUTPUT_CAP 0x29 +#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7) +#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6) +#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5) +#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4) +#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3) +#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2) +#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1) +#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0) + +#define TCPC_REG_CONFIG_EXT_1 0x2A +#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1) + +#define TCPC_REG_GENERIC_TIMER 0x2c + +#define TCPC_REG_MSG_HDR_INFO 0x2e #define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \ - ((drole) << 3 | (PD_REV20 << 1) | (prole)) -#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3) -#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1) - -#define TCPC_REG_RX_DETECT 0x2f -#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7) -#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6) -#define TCPC_REG_RX_DETECT_HRST BIT(5) -#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4) -#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3) -#define TCPC_REG_RX_DETECT_SOPPP BIT(2) -#define TCPC_REG_RX_DETECT_SOPP BIT(1) -#define TCPC_REG_RX_DETECT_SOP BIT(0) -#define TCPC_REG_RX_DETECT_SOP_HRST_MASK (TCPC_REG_RX_DETECT_SOP | \ - TCPC_REG_RX_DETECT_HRST) -#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \ - (TCPC_REG_RX_DETECT_SOP | \ - TCPC_REG_RX_DETECT_SOPP | \ - TCPC_REG_RX_DETECT_SOPPP | \ - TCPC_REG_RX_DETECT_HRST) + ((drole) << 3 | (PD_REV20 << 1) | (prole)) +#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg)&0x8) >> 3) +#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg)&0x1) + +#define TCPC_REG_RX_DETECT 0x2f +#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7) +#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6) +#define TCPC_REG_RX_DETECT_HRST BIT(5) +#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4) +#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3) +#define TCPC_REG_RX_DETECT_SOPPP BIT(2) +#define TCPC_REG_RX_DETECT_SOPP BIT(1) +#define TCPC_REG_RX_DETECT_SOP BIT(0) +#define TCPC_REG_RX_DETECT_SOP_HRST_MASK \ + (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST) +#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \ + (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | \ + TCPC_REG_RX_DETECT_SOPPP | TCPC_REG_RX_DETECT_HRST) /* TCPCI Rev 1.0 receive registers */ -#define TCPC_REG_RX_BYTE_CNT 0x30 +#define TCPC_REG_RX_BYTE_CNT 0x30 #define TCPC_REG_RX_BUF_FRAME_TYPE 0x31 -#define TCPC_REG_RX_HDR 0x32 -#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */ +#define TCPC_REG_RX_HDR 0x32 +#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */ /* * In TCPCI Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers: * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can * only be accessed by reading at a common register address 30h. */ -#define TCPC_REG_RX_BUFFER 0x30 +#define TCPC_REG_RX_BUFFER 0x30 -#define TCPC_REG_TRANSMIT 0x50 +#define TCPC_REG_TRANSMIT 0x50 #define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) \ - ((retries) << 4 | (type)) + ((retries) << 4 | (type)) #define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type) -#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4) -#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg) & 0x7) +#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg)&0x30) >> 4) +#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg)&0x7) /* TCPCI Rev 1.0 transmit registers */ -#define TCPC_REG_TX_BYTE_CNT 0x51 -#define TCPC_REG_TX_HDR 0x52 -#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */ +#define TCPC_REG_TX_BYTE_CNT 0x51 +#define TCPC_REG_TX_HDR 0x52 +#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */ /* * In TCPCI Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the @@ -274,12 +265,12 @@ * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x * is “hidden” and can only be accessed by writing to register address 51h */ -#define TCPC_REG_TX_BUFFER 0x51 +#define TCPC_REG_TX_BUFFER 0x51 -#define TCPC_REG_VBUS_VOLTAGE 0x70 -#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0) -#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10) -#define TCPC_REG_VBUS_VOLTAGE_LSB 25 +#define TCPC_REG_VBUS_VOLTAGE 0x70 +#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0) +#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10) +#define TCPC_REG_VBUS_VOLTAGE_LSB 25 /* * 00: the measurement is not scaled @@ -287,22 +278,21 @@ * 10: the measurement is divided by 4 * 11: reserved */ -#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \ - (1 << (((x) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9)) -#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) \ - ((x) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT) -#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \ - (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \ +#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \ + (1 << (((x)&TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9)) +#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) ((x)&TCPC_REG_VBUS_VOLTAGE_MEASUREMENT) +#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \ + (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \ TCPC_REG_VBUS_VOLTAGE_LSB) #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72 #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */ -#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74 -#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 -#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 +#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74 +#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 +#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 -#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a +#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a extern const struct tcpm_drv tcpci_tcpm_drv; extern const struct usb_mux_driver tcpci_tcpm_usb_mux_driver; @@ -315,7 +305,7 @@ enum tcpc_cc_pull tcpci_get_cached_pull(int port); void tcpci_tcpc_alert(int port); int tcpci_tcpm_init(int port); int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); bool tcpci_tcpm_check_vbus_level(int port, enum vbus_level level); int tcpci_tcpm_select_rp_value(int port, int rp); int tcpci_tcpm_set_cc(int port, int pull); @@ -325,20 +315,22 @@ int tcpci_tcpm_set_vconn(int port, int enable); int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role); int tcpci_tcpm_set_rx_enable(int port, int enable); int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head); -int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, - uint16_t header, const uint32_t *data); +int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header, + const uint32_t *data); int tcpci_tcpm_release(int port); #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp, - enum tcpc_cc_pull pull); + enum tcpc_cc_pull pull); int tcpci_tcpc_drp_toggle(int port); #endif #ifdef CONFIG_USB_PD_TCPC_LOW_POWER int tcpci_enter_low_power_mode(int port); void tcpci_wake_low_power_mode(int port); #endif -enum ec_error_list tcpci_set_bist_test_mode(const int port, - const bool enable); +int tcpci_hard_reset_reinit(int port); + +enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable); +enum ec_error_list tcpci_get_bist_test_mode(const int port, bool *enable); void tcpci_tcpc_discharge_vbus(int port, int enable); void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable); int tcpci_tcpc_debug_accessory(int port, bool enable); diff --git a/include/driver/tcpm/tcpm.h b/include/driver/tcpm/tcpm.h index ef47a3b1e2..8352423d9d 100644 --- a/include/driver/tcpm/tcpm.h +++ b/include/driver/tcpm/tcpm.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,26 +26,22 @@ #ifndef CONFIG_USB_PD_TCPC_LOW_POWER static inline int tcpc_addr_write(int port, int i2c_addr, int reg, int val) { - return i2c_write8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_write8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_write16(int port, int i2c_addr, int reg, int val) { - return i2c_write16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_write16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_read(int port, int i2c_addr, int reg, int *val) { - return i2c_read8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_read8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val) { - return i2c_read16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_read16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } /* @@ -65,8 +61,8 @@ static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val) * need an explicit by the caller. */ -static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, - int reg, int *val) +static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, + int *val) { return tcpc_addr_read16(port, i2c_addr, reg, val); } @@ -75,49 +71,47 @@ static inline int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in, int in_size) { return i2c_xfer(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - out, out_size, in, in_size); + tcpc_config[port].i2c_info.addr_flags, out, out_size, + in, in_size); } static inline int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) + uint8_t *in, int in_size, int flags) { return i2c_xfer_unlocked(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - out, out_size, in, in_size, flags); + tcpc_config[port].i2c_info.addr_flags, out, + out_size, in, in_size, flags); } static inline int tcpc_read_block(int port, int reg, uint8_t *in, int size) { return i2c_read_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, in, size); + tcpc_config[port].i2c_info.addr_flags, reg, in, + size); } -static inline int tcpc_write_block(int port, int reg, - const uint8_t *out, int size) +static inline int tcpc_write_block(int port, int reg, const uint8_t *out, + int size) { return i2c_write_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, out, size); + tcpc_config[port].i2c_info.addr_flags, reg, out, + size); } -static inline int tcpc_update8(int port, int reg, - uint8_t mask, +static inline int tcpc_update8(int port, int reg, uint8_t mask, enum mask_update_action action) { return i2c_update8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, mask, action); + tcpc_config[port].i2c_info.addr_flags, reg, mask, + action); } -static inline int tcpc_update16(int port, int reg, - uint16_t mask, +static inline int tcpc_update16(int port, int reg, uint16_t mask, enum mask_update_action action) { return i2c_update16(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, mask, action); + tcpc_config[port].i2c_info.addr_flags, reg, mask, + action); } #else /* !CONFIG_USB_PD_TCPC_LOW_POWER */ @@ -128,40 +122,40 @@ int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val); int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val); int tcpc_read_block(int port, int reg, uint8_t *in, int size); int tcpc_write_block(int port, int reg, const uint8_t *out, int size); -int tcpc_xfer(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size); -int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); +int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size); +int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags); -int tcpc_update8(int port, int reg, - uint8_t mask, enum mask_update_action action); -int tcpc_update16(int port, int reg, - uint16_t mask, enum mask_update_action action); +int tcpc_update8(int port, int reg, uint8_t mask, + enum mask_update_action action); +int tcpc_update16(int port, int reg, uint16_t mask, + enum mask_update_action action); #endif /* CONFIG_USB_PD_TCPC_LOW_POWER */ static inline int tcpc_write(int port, int reg, int val) { - return tcpc_addr_write(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_write(port, tcpc_config[port].i2c_info.addr_flags, reg, + val); } static inline int tcpc_write16(int port, int reg, int val) { - return tcpc_addr_write16(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_write16(port, tcpc_config[port].i2c_info.addr_flags, + reg, val); } static inline int tcpc_read(int port, int reg, int *val) { - return tcpc_addr_read(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_read(port, tcpc_config[port].i2c_info.addr_flags, reg, + val); } static inline int tcpc_read16(int port, int reg, int *val) { - return tcpc_addr_read16(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_read16(port, tcpc_config[port].i2c_info.addr_flags, + reg, val); } static inline void tcpc_lock(int port, int lock) @@ -191,7 +185,7 @@ static inline int tcpm_release(int port) } static inline int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { return tcpc_config[port].drv->get_cc(port, cc1, cc2); } @@ -281,7 +275,8 @@ static inline int tcpm_transmit(int port, enum tcpci_msg_type type, static inline bool tcpm_get_snk_ctrl(int port) { return tcpc_config[port].drv->get_snk_ctrl ? - tcpc_config[port].drv->get_snk_ctrl(port) : false; + tcpc_config[port].drv->get_snk_ctrl(port) : + false; } static inline int tcpm_set_snk_ctrl(int port, int enable) { @@ -293,9 +288,9 @@ static inline int tcpm_set_snk_ctrl(int port, int enable) static inline bool tcpm_get_src_ctrl(int port) { - return tcpc_config[port].drv->get_src_ctrl ? - tcpc_config[port].drv->get_src_ctrl(port) : false; + tcpc_config[port].drv->get_src_ctrl(port) : + false; } static inline int tcpm_set_src_ctrl(int port, int enable) { @@ -387,6 +382,13 @@ static inline int tcpm_get_chip_info(int port, int live, return EC_ERROR_UNIMPLEMENTED; } +static inline int tcpm_hard_reset_reinit(int port) +{ + if (tcpc_config[port].drv->hard_reset_reinit) + return tcpc_config[port].drv->hard_reset_reinit(port); + return EC_ERROR_UNIMPLEMENTED; +} + static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable) { const struct tcpm_drv *tcpc; @@ -398,6 +400,19 @@ static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable) return rv; } +static inline enum ec_error_list tcpc_get_bist_test_mode(int port, bool *enable) +{ + const struct tcpm_drv *tcpc; + + tcpc = tcpc_config[port].drv; + if (tcpc->get_bist_test_mode) + return tcpc->get_bist_test_mode(port, enable); + + *enable = false; + + return EC_ERROR_UNIMPLEMENTED; +} + /* * Returns true if the port controls FRS using the TCPC. */ @@ -444,8 +459,8 @@ static inline int tcpm_set_frs_enable(int port, int enable) static inline int tcpc_set_sbu(int port, bool enable) { return tcpc_config[port].drv->set_sbu ? - tcpc_config[port].drv->set_sbu(port, enable) : - EC_SUCCESS; + tcpc_config[port].drv->set_sbu(port, enable) : + EC_SUCCESS; } #endif /* CONFIG_USB_PD_TCPM_SBU */ @@ -470,7 +485,7 @@ int tcpm_init(int port); * @return EC_SUCCESS or error */ int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); /** * Check VBUS level diff --git a/include/driver/tcpm/tusb422_public.h b/include/driver/tcpm/tusb422_public.h index 8756d9b362..004abdd5c9 100644 --- a/include/driver/tcpm/tusb422_public.h +++ b/include/driver/tcpm/tusb422_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/temp_sensor/pct2075.h b/include/driver/temp_sensor/pct2075.h index c09d0e383c..e79ac0e97a 100644 --- a/include/driver/temp_sensor/pct2075.h +++ b/include/driver/temp_sensor/pct2075.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,10 +17,10 @@ #define PCT2075_I2C_ADDR_FLAGS6 (0x4E | I2C_FLAG_BIG_ENDIAN) #define PCT2075_I2C_ADDR_FLAGS7 (0x4F | I2C_FLAG_BIG_ENDIAN) -#define PCT2075_REG_TEMP 0x00 -#define PCT2075_REG_CONF 0x01 -#define PCT2075_REG_THYST 0x02 -#define PCT2075_REG_TOS 0x03 +#define PCT2075_REG_TEMP 0x00 +#define PCT2075_REG_CONF 0x01 +#define PCT2075_REG_THYST 0x02 +#define PCT2075_REG_TOS 0x03 /* * I2C port and address information for all the board PCT2075 sensors should be diff --git a/include/driver/temp_sensor/sb_tsi.h b/include/driver/temp_sensor/sb_tsi.h index b7113dbc70..d8b015d200 100644 --- a/include/driver/temp_sensor/sb_tsi.h +++ b/include/driver/temp_sensor/sb_tsi.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,27 +11,27 @@ #ifndef __CROS_EC_SB_TSI_H #define __CROS_EC_SB_TSI_H -#define SB_TSI_I2C_ADDR_FLAGS 0x4C +#define SB_TSI_I2C_ADDR_FLAGS 0x4C /* G781 register */ -#define SB_TSI_TEMP_H 0x01 -#define SB_TSI_STATUS 0x02 -#define SB_TSI_CONFIG_1 0x03 -#define SB_TSI_UPDATE_RATE 0x04 -#define SB_TSI_HIGH_TEMP_THRESHOLD_H 0x07 -#define SB_TSI_LOW_TEMP_THRESHOLD_H 0x08 -#define SB_TSI_CONFIG_2 0x09 -#define SB_TSI_TEMP_L 0x10 -#define SB_TSI_TEMP_OFFSET_H 0x11 -#define SB_TSI_TEMP_OFFSET_L 0x12 -#define SB_TSI_HIGH_TEMP_THRESHOLD_L 0x13 -#define SB_TSI_LOW_TEMP_THRESHOLD_L 0x14 -#define SB_TSI_TIMEOUT_CONFIG 0x22 -#define SB_TSI_PSTATE_LIMIT_CONFIG 0x2F -#define SB_TSI_ALERT_THRESHOLD 0x32 -#define SB_TSI_ALERT_CONFIG 0xBF -#define SB_TSI_MANUFACTURE_ID 0xFE -#define SB_TSI_REVISION 0xFF +#define SB_TSI_TEMP_H 0x01 +#define SB_TSI_STATUS 0x02 +#define SB_TSI_CONFIG_1 0x03 +#define SB_TSI_UPDATE_RATE 0x04 +#define SB_TSI_HIGH_TEMP_THRESHOLD_H 0x07 +#define SB_TSI_LOW_TEMP_THRESHOLD_H 0x08 +#define SB_TSI_CONFIG_2 0x09 +#define SB_TSI_TEMP_L 0x10 +#define SB_TSI_TEMP_OFFSET_H 0x11 +#define SB_TSI_TEMP_OFFSET_L 0x12 +#define SB_TSI_HIGH_TEMP_THRESHOLD_L 0x13 +#define SB_TSI_LOW_TEMP_THRESHOLD_L 0x14 +#define SB_TSI_TIMEOUT_CONFIG 0x22 +#define SB_TSI_PSTATE_LIMIT_CONFIG 0x2F +#define SB_TSI_ALERT_THRESHOLD 0x32 +#define SB_TSI_ALERT_CONFIG 0xBF +#define SB_TSI_MANUFACTURE_ID 0xFE +#define SB_TSI_REVISION 0xFF /** * Get the value of a sensor in K. @@ -43,4 +43,4 @@ */ int sb_tsi_get_val(int idx, int *temp_ptr); -#endif /* __CROS_EC_SB_TSI_H */ +#endif /* __CROS_EC_SB_TSI_H */ diff --git a/include/driver/temp_sensor/thermistor.h b/include/driver/temp_sensor/thermistor.h index adcd5c5be4..46b7763747 100644 --- a/include/driver/temp_sensor/thermistor.h +++ b/include/driver/temp_sensor/thermistor.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,13 +9,13 @@ #define __CROS_EC_TEMP_SENSOR_THERMISTOR_H struct thermistor_data_pair { - uint8_t mv; /* Scaled voltage level at ADC (in mV) */ - uint8_t temp; /* Temperature in Celsius */ + uint8_t mv; /* Scaled voltage level at ADC (in mV) */ + uint8_t temp; /* Temperature in Celsius */ }; struct thermistor_info { - uint8_t scaling_factor; /* Scaling factor for voltage in data pair. */ - uint8_t num_pairs; /* Number of data pairs. */ + uint8_t scaling_factor; /* Scaling factor for voltage in data pair. */ + uint8_t num_pairs; /* Number of data pairs. */ /* * Values between given data pairs will be calculated as points on diff --git a/include/driver/temp_sensor/tmp112.h b/include/driver/temp_sensor/tmp112.h index d1b97b138c..56d55d9133 100644 --- a/include/driver/temp_sensor/tmp112.h +++ b/include/driver/temp_sensor/tmp112.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,10 +13,10 @@ #define TMP112_I2C_ADDR_FLAGS2 (0x4A | I2C_FLAG_BIG_ENDIAN) #define TMP112_I2C_ADDR_FLAGS3 (0x4B | I2C_FLAG_BIG_ENDIAN) -#define TMP112_REG_TEMP 0x00 -#define TMP112_REG_CONF 0x01 -#define TMP112_REG_HYST 0x02 -#define TMP112_REG_MAX 0x03 +#define TMP112_REG_TEMP 0x00 +#define TMP112_REG_CONF 0x01 +#define TMP112_REG_HYST 0x02 +#define TMP112_REG_MAX 0x03 /* * I2C port and address information for all the board TMP112 sensors should be diff --git a/include/driver/usb_mux/it5205_public.h b/include/driver/usb_mux/it5205_public.h index 81dc326049..40590194c4 100644 --- a/include/driver/usb_mux/it5205_public.h +++ b/include/driver/usb_mux/it5205_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/driver/usb_mux/ps8743_public.h b/include/driver/usb_mux/ps8743_public.h index c20b948d07..64ba2d0cd7 100644 --- a/include/driver/usb_mux/ps8743_public.h +++ b/include/driver/usb_mux/ps8743_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,69 +10,69 @@ #include <inttypes.h> -#define PS8743_I2C_ADDR0_FLAG 0x10 -#define PS8743_I2C_ADDR1_FLAG 0x11 -#define PS8743_I2C_ADDR2_FLAG 0x19 -#define PS8743_I2C_ADDR3_FLAG 0x1a +#define PS8743_I2C_ADDR0_FLAG 0x10 +#define PS8743_I2C_ADDR1_FLAG 0x11 +#define PS8743_I2C_ADDR2_FLAG 0x19 +#define PS8743_I2C_ADDR3_FLAG 0x1a /* Mode register for setting mux */ #define PS8743_REG_MODE 0x00 -#define PS8743_MODE_IN_HPD_ASSERT BIT(0) -#define PS8743_MODE_IN_HPD_CONTROL BIT(1) -#define PS8743_MODE_FLIP_ENABLE BIT(2) +#define PS8743_MODE_IN_HPD_ASSERT BIT(0) +#define PS8743_MODE_IN_HPD_CONTROL BIT(1) +#define PS8743_MODE_FLIP_ENABLE BIT(2) #define PS8743_MODE_FLIP_REG_CONTROL BIT(3) -#define PS8743_MODE_USB_ENABLE BIT(4) -#define PS8743_MODE_USB_REG_CONTROL BIT(5) -#define PS8743_MODE_DP_ENABLE BIT(6) -#define PS8743_MODE_DP_REG_CONTROL BIT(7) +#define PS8743_MODE_USB_ENABLE BIT(4) +#define PS8743_MODE_USB_REG_CONTROL BIT(5) +#define PS8743_MODE_DP_ENABLE BIT(6) +#define PS8743_MODE_DP_REG_CONTROL BIT(7) /* To reset the state machine to default */ -#define PS8743_MODE_POWER_DOWN (PS8743_MODE_USB_REG_CONTROL | \ - PS8743_MODE_DP_REG_CONTROL) +#define PS8743_MODE_POWER_DOWN \ + (PS8743_MODE_USB_REG_CONTROL | PS8743_MODE_DP_REG_CONTROL) /* DP output setting */ -#define PS8743_REG_DP_SETTING 0x07 -#define PS8743_DP_SWG_ADJ_DFLT 0x00 -#define PS8743_DP_SWG_ADJ_N20P 0x40 -#define PS8743_DP_SWG_ADJ_N15P 0x80 -#define PS8743_DP_SWG_ADJ_P15P 0xc0 -#define PS8743_DP_OUT_SWG_400 0x00 -#define PS8743_DP_OUT_SWG_600 0x10 -#define PS8743_DP_OUT_SWG_800 0x20 -#define PS8743_DP_OUT_SWG_1000 0x30 -#define PS8743_DP_OUT_PRE_EM_0_DB 0x00 +#define PS8743_REG_DP_SETTING 0x07 +#define PS8743_DP_SWG_ADJ_DFLT 0x00 +#define PS8743_DP_SWG_ADJ_N20P 0x40 +#define PS8743_DP_SWG_ADJ_N15P 0x80 +#define PS8743_DP_SWG_ADJ_P15P 0xc0 +#define PS8743_DP_OUT_SWG_400 0x00 +#define PS8743_DP_OUT_SWG_600 0x10 +#define PS8743_DP_OUT_SWG_800 0x20 +#define PS8743_DP_OUT_SWG_1000 0x30 +#define PS8743_DP_OUT_PRE_EM_0_DB 0x00 #define PS8743_DP_OUT_PRE_EM_3_5_DB 0x04 #define PS8743_DP_OUT_PRE_EM_6_0_DB 0x08 #define PS8743_DP_OUT_PRE_EM_9_5_DB 0x0c -#define PS8743_DP_POST_CUR2_0_DB 0x00 +#define PS8743_DP_POST_CUR2_0_DB 0x00 #define PS8743_DP_POST_CUR2_NEG_0_9_DB 0x01 #define PS8743_DP_POST_CUR2_NEG_1_9_DB 0x02 #define PS8743_DP_POST_CUR2_NEG_3_1_DB 0x03 /* USB equalization settings for Host to Mux */ -#define PS8743_REG_USB_EQ_TX 0x32 +#define PS8743_REG_USB_EQ_TX 0x32 #define PS8743_USB_EQ_TX_12_8_DB 0x00 -#define PS8743_USB_EQ_TX_17_DB 0x20 -#define PS8743_USB_EQ_TX_7_7_DB 0x40 -#define PS8743_USB_EQ_TX_3_6_DB 0x60 -#define PS8743_USB_EQ_TX_15_DB 0x80 +#define PS8743_USB_EQ_TX_17_DB 0x20 +#define PS8743_USB_EQ_TX_7_7_DB 0x40 +#define PS8743_USB_EQ_TX_3_6_DB 0x60 +#define PS8743_USB_EQ_TX_15_DB 0x80 #define PS8743_USB_EQ_TX_10_9_DB 0xc0 -#define PS8743_USB_EQ_TX_4_5_DB 0xe0 +#define PS8743_USB_EQ_TX_4_5_DB 0xe0 /* USB swing adjust for Mux to Type-C connector */ -#define PS8743_REG_USB_SWING 0x36 -#define PS8743_OUT_SWG_DEFAULT 0x00 -#define PS8743_OUT_SWG_NEG_20 0x40 -#define PS8743_OUT_SWG_NEG_15 0x80 -#define PS8743_OUT_SWG_POS_15 0xc0 -#define PS8743_LFPS_SWG_DEFAULT 0x00 -#define PS8743_LFPS_SWG_TD 0x08 +#define PS8743_REG_USB_SWING 0x36 +#define PS8743_OUT_SWG_DEFAULT 0x00 +#define PS8743_OUT_SWG_NEG_20 0x40 +#define PS8743_OUT_SWG_NEG_15 0x80 +#define PS8743_OUT_SWG_POS_15 0xc0 +#define PS8743_LFPS_SWG_DEFAULT 0x00 +#define PS8743_LFPS_SWG_TD 0x08 /* USB equalization settings for Connector to Mux */ -#define PS8743_REG_USB_EQ_RX 0x3b -#define PS8743_USB_EQ_RX_2_4_DB 0x00 -#define PS8743_USB_EQ_RX_5_DB 0x10 -#define PS8743_USB_EQ_RX_6_5_DB 0x20 -#define PS8743_USB_EQ_RX_7_4_DB 0x30 -#define PS8743_USB_EQ_RX_8_7_DB 0x40 +#define PS8743_REG_USB_EQ_RX 0x3b +#define PS8743_USB_EQ_RX_2_4_DB 0x00 +#define PS8743_USB_EQ_RX_5_DB 0x10 +#define PS8743_USB_EQ_RX_6_5_DB 0x20 +#define PS8743_USB_EQ_RX_7_4_DB 0x30 +#define PS8743_USB_EQ_RX_8_7_DB 0x40 #define PS8743_USB_EQ_RX_10_9_DB 0x50 #define PS8743_USB_EQ_RX_12_8_DB 0x60 #define PS8743_USB_EQ_RX_13_8_DB 0x70 @@ -85,21 +85,21 @@ #define PS8743_USB_EQ_RX_22_2_DB 0xe0 /* USB High Speed Signal Detector thershold adjustment */ -#define PS8743_REG_HS_DET_THRESHOLD 0x3c +#define PS8743_REG_HS_DET_THRESHOLD 0x3c #define PS8743_USB_HS_THRESH_DEFAULT 0x00 -#define PS8743_USB_HS_THRESH_POS_10 0x20 -#define PS8743_USB_HS_THRESH_POS_33 0x40 -#define PS8743_USB_HS_THRESH_NEG_10 0x60 -#define PS8743_USB_HS_THRESH_NEG_25 0x80 -#define PS8743_USB_HS_THRESH_POS_25 0xa0 -#define PS8743_USB_HS_THRESH_NEG_45 0xc0 -#define PS8743_USB_HS_THRESH_NEG_35 0xe0 +#define PS8743_USB_HS_THRESH_POS_10 0x20 +#define PS8743_USB_HS_THRESH_POS_33 0x40 +#define PS8743_USB_HS_THRESH_NEG_10 0x60 +#define PS8743_USB_HS_THRESH_NEG_25 0x80 +#define PS8743_USB_HS_THRESH_POS_25 0xa0 +#define PS8743_USB_HS_THRESH_NEG_45 0xc0 +#define PS8743_USB_HS_THRESH_NEG_35 0xe0 /* DCI config: 0x45~0x4D */ -#define PS8743_REG_DCI_CONFIG_2 0x47 -#define PS8743_AUTO_DCI_MODE_SHIFT 6 -#define PS8743_AUTO_DCI_MODE_MASK (3 << PS8743_AUTO_DCI_MODE_SHIFT) -#define PS8743_AUTO_DCI_MODE_ENABLE (0 << PS8743_AUTO_DCI_MODE_SHIFT) +#define PS8743_REG_DCI_CONFIG_2 0x47 +#define PS8743_AUTO_DCI_MODE_SHIFT 6 +#define PS8743_AUTO_DCI_MODE_MASK (3 << PS8743_AUTO_DCI_MODE_SHIFT) +#define PS8743_AUTO_DCI_MODE_ENABLE (0 << PS8743_AUTO_DCI_MODE_SHIFT) #define PS8743_AUTO_DCI_MODE_FORCE_USB (2 << PS8743_AUTO_DCI_MODE_SHIFT) #define PS8743_AUTO_DCI_MODE_FORCE_DCI (3 << PS8743_AUTO_DCI_MODE_SHIFT) |