diff options
Diffstat (limited to 'include/power')
| -rw-r--r-- | include/power/alderlake_slg4bd44540.h | 46 | ||||
| -rw-r--r-- | include/power/apollolake.h | 52 | ||||
| -rw-r--r-- | include/power/cannonlake.h | 30 | ||||
| -rw-r--r-- | include/power/cometlake-discrete.h | 150 | ||||
| -rw-r--r-- | include/power/cometlake.h | 45 | ||||
| -rw-r--r-- | include/power/icelake.h | 82 | ||||
| -rw-r--r-- | include/power/intel_x86.h | 105 | ||||
| -rw-r--r-- | include/power/mt8192.h | 16 | ||||
| -rw-r--r-- | include/power/qcom.h | 28 | ||||
| -rw-r--r-- | include/power/skylake.h | 57 |
10 files changed, 0 insertions, 611 deletions
diff --git a/include/power/alderlake_slg4bd44540.h b/include/power/alderlake_slg4bd44540.h deleted file mode 100644 index 62c617bd98..0000000000 --- a/include/power/alderlake_slg4bd44540.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Alder Lake chipset power control module using the SLG4BD44540 power - * sequencer chip for Chrome EC - */ - -#ifndef __CROS_EC_ALDERLAKE_SLG4BD44540_H -#define __CROS_EC_ALDERLAKE_SLG4BD44540_H - -/* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) -#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) - -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) - -#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK) - -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED) - -#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED - -#define CHARGER_INITIALIZED_DELAY_MS 100 -#define CHARGER_INITIALIZED_TRIES 40 - -/* Power signals list */ -enum power_signal { - X86_SLP_S0_DEASSERTED, - X86_SLP_S3_DEASSERTED, - X86_SLP_S4_DEASSERTED, - X86_SLP_SUS_DEASSERTED, - X86_RSMRST_L_PGOOD, - X86_DSW_DPWROK, - X86_ALL_SYS_PGOOD, - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT -}; - -#endif /* __CROS_EC_ALDERLAKE_SLG4BD44540_H */ diff --git a/include/power/apollolake.h b/include/power/apollolake.h deleted file mode 100644 index cc864f26c3..0000000000 --- a/include/power/apollolake.h +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Apollolake chipset power control module for Chrome EC */ - -#ifndef __CROS_EC_APOLLOLAKE_H -#define __CROS_EC_APOLLOLAKE_H - -/* - * Input state flags. - * TODO: Normalize the power signal masks from board defines to SoC headers. - */ -#define IN_RSMRST_N POWER_SIGNAL_MASK(X86_RSMRST_N) -#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) -#define IN_SLP_S3_N POWER_SIGNAL_MASK(X86_SLP_S3_N) -#define IN_SLP_S4_N POWER_SIGNAL_MASK(X86_SLP_S4_N) -#define IN_PCH_SLP_S4_DEASSERTED IN_SLP_S4_N -#define IN_SUSPWRDNACK POWER_SIGNAL_MASK(X86_SUSPWRDNACK) -#define IN_SUS_STAT_N POWER_SIGNAL_MASK(X86_SUS_STAT_N) - -#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | \ - IN_SLP_S4_N) - -#define IN_PGOOD_ALL_CORE (IN_RSMRST_N) - -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED) - -#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PGOOD_ALL_CORE - -#define CHARGER_INITIALIZED_DELAY_MS 100 -#define CHARGER_INITIALIZED_TRIES 40 - -enum power_signal { -#ifdef CONFIG_POWER_S0IX - X86_SLP_S0_N, /* PCH -> SLP_S0_L */ -#endif - X86_SLP_S3_N, /* PCH -> SLP_S3_L */ - X86_SLP_S4_N, /* PCH -> SLP_S4_L */ - X86_SUSPWRDNACK, /* PCH -> SUSPWRDNACK */ - - X86_ALL_SYS_PG, /* PMIC -> PMIC_EC_PWROK_OD */ - X86_RSMRST_N, /* PMIC -> PMIC_EC_RSMRST_ODL */ - X86_PGOOD_PP3300, /* PMIC -> PP3300_PG_OD */ - X86_PGOOD_PP5000, /* PMIC -> PP5000_PG_OD */ - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT -}; - -#endif /* __CROS_EC_APOLLOLAKE_H */ diff --git a/include/power/cannonlake.h b/include/power/cannonlake.h deleted file mode 100644 index a056a96ec8..0000000000 --- a/include/power/cannonlake.h +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Cannonlake chipset power control module for Chrome EC */ - -#ifndef __CROS_EC_CANNONLAKE_H -#define __CROS_EC_CANNONLAKE_H - -/* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) -#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) - -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) - -#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK) - -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ - PP5000_PGOOD_POWER_SIGNAL_MASK) - -#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED - -#define CHARGER_INITIALIZED_DELAY_MS 100 -#define CHARGER_INITIALIZED_TRIES 40 - -#endif /* __CROS_EC_CANNONLAKE_H */ diff --git a/include/power/cometlake-discrete.h b/include/power/cometlake-discrete.h deleted file mode 100644 index 6f5370beee..0000000000 --- a/include/power/cometlake-discrete.h +++ /dev/null @@ -1,150 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Chrome EC chipset power control for Cometlake with platform-controlled - * discrete sequencing. - */ - -#ifndef __CROS_EC_COMETLAKE_DISCRETE_H -#define __CROS_EC_COMETLATE_DISCRETE_H - -/* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) - -#define IN_ALL_PM_SLP_DEASSERTED \ - (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED) - -/* - * Power mask used by intel_x86 to check that S5 is ready. - * - * This driver controls RSMRST in the G3->S5 transition so this check has nearly - * no use, but letting the common Intel code read RSMRST allows us to avoid - * duplicating the common code (introducing a little redundancy instead). - * - * PP3300 monitoring is analog-only: power_handle_state enforces that it's good - * before continuing to common_intel_x86_power_handle_state. This means we can't - * detect dropouts on that rail, however. - * - * Polling analog inputs as a signal for the common code would require - * modification to support non-power signals as inputs and incurs a minimum 12 - * microsecond time penalty on NPCX7 to do an ADC conversion. Running the ADC - * in repetitive scan mode and enabling threshold detection on the relevant - * channels would permit immediate readings (that might be up to 100 - * microseconds old) but is not currently supported by the ADC driver. - * TODO(b/143188569) try to implement analog watchdogs - */ -#define CHIPSET_G3S5_POWERUP_SIGNAL \ - (POWER_SIGNAL_MASK(PP5000_A_PGOOD) | \ - POWER_SIGNAL_MASK(PP1800_A_PGOOD) | \ - POWER_SIGNAL_MASK(PP1050_A_PGOOD) | \ - POWER_SIGNAL_MASK(OUT_PCH_RSMRST_DEASSERTED)) - -/* - * Power mask used by intel_x86 to check that S3 is ready. - * - * Transition S5->S3 only involves turning on the DRAM power rails which are - * controlled directly from the PCH, so this condition doesn't require any - * special code, except this collection of signals is also polled in POWER_S3 - * and POWER_S0 states. - * - * During normal shutdown the PCH will turn off the DRAM rails before the EC - * notices, so if this collection includes those rails a normal shutdown will be - * treated as a power failure so the system immediately drops to G3 rather than - * doing an orderly shutdown. This must only include those signals that are - * EC-controlled, not those controlled by the PCH. - */ -#define IN_PGOOD_ALL_CORE CHIPSET_G3S5_POWERUP_SIGNAL - -/* - * intel_x86 power mask for S0 all-OK. - * - * This is only used on power task init to check whether the system is powered - * up and already in S0, to correctly handle switching from RO to RW firmware. - */ -#define IN_ALL_S0 \ - (IN_PGOOD_ALL_CORE | POWER_SIGNAL_MASK(PP2500_DRAM_PGOOD) | \ - POWER_SIGNAL_MASK(PP1200_DRAM_PGOOD) | IN_ALL_PM_SLP_DEASSERTED) - -#define CHARGER_INITIALIZED_DELAY_MS 100 -#define CHARGER_INITIALIZED_TRIES 40 - -/* Power signals, in power-on sequence order. */ -enum power_signal { - PP5000_A_PGOOD, - /* PP3300 monitoring is analog */ - PP1800_A_PGOOD, - VPRIM_CORE_A_PGOOD, - PP1050_A_PGOOD, - OUT_PCH_RSMRST_DEASSERTED, - /* S5 ready */ - X86_SLP_S4_DEASSERTED, - PP2500_DRAM_PGOOD, - PP1200_DRAM_PGOOD, - /* S3 ready */ - X86_SLP_S3_DEASSERTED, - /* PP1050 monitoring is analog */ - PP950_VCCIO_PGOOD, - /* S0 ready */ - X86_SLP_S0_DEASSERTED, - CPU_C10_GATE_DEASSERTED, - IMVP8_READY, - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT -}; - -/* - * Board-specific enable for any additional rails in S0. - * - * Input 0 to turn off, 1 to turn on. - * - * This function may be called from interrupts so must not assume it's running - * in a task. - */ -void board_enable_s0_rails(int enable); - -/* - * Board-specific flag for whether EN_S0_RAILS can be turned off when - * CPU_C10_GATED is asserted by the PCH. - * - * Return 0 if EN_S0_RAILS must be left on when in S0, even if the PCH asserts - * the C10 gate. - * - * If this can ever return 1, the CPU_C10_GATE_L input from the PCH must also - * be configured to call c10_gate_interrupt() rather than - * power_signal_interrupt() in order to actually control the relevant core - * rails. - * - * TODO: it is safe to remove this function and assume C10 gating is enabled if - * support for rev0 puff boards is no longer required- it was added only for the - * benefit of those boards. - */ -int board_is_c10_gate_enabled(void); - -/* - * Special interrupt for CPU_C10_GATE_L handling. - * - * Response time on resume from C10 has very strict timing requirements- no more - * than 65 uS to turn on, and the load switches are specified to turn on in 65 - * uS max at 1V (30 uS typical). This means the response to changes on the C10 - * gate input must be as fast as possible to meet PCH timing requirements- much - * faster than doing this handling in the power state machine can achieve - * (hundreds of microseconds). - */ -void c10_gate_interrupt(enum gpio_signal signal); - -/* - * Special interrupt for SLP_S3_L handling. - * - * The time window in which to turn off some rails when dropping to S3 is - * ~200us, and using the regular power state machine path tends to have latency - * >1ms. This ISR short-circuits the relevant signals in a fast path before - * scheduling a state machine update to ensure sufficiently low latency. - */ -void slp_s3_interrupt(enum gpio_signal signal); - -#endif /* __CROS_EC_COMETLAKE_DISCRETE_H */ diff --git a/include/power/cometlake.h b/include/power/cometlake.h deleted file mode 100644 index 0f48346c9e..0000000000 --- a/include/power/cometlake.h +++ /dev/null @@ -1,45 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Cometlake chipset power control module for Chrome EC */ - -#ifndef __CROS_EC_COMETLAKE_H -#define __CROS_EC_COMETLAKE_H - -/* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) - -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED) - -#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) - -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ - PP5000_PGOOD_POWER_SIGNAL_MASK) - -#define CHIPSET_G3S5_POWERUP_SIGNAL (POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \ - POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD)) - -#define CHARGER_INITIALIZED_DELAY_MS 100 -#define CHARGER_INITIALIZED_TRIES 40 - -/* Power signals list */ -enum power_signal { - X86_SLP_S0_DEASSERTED, - X86_SLP_S3_DEASSERTED, - X86_SLP_S4_DEASSERTED, - X86_RSMRST_L_PGOOD, - X86_PP5000_A_PGOOD, - X86_ALL_SYS_PGOOD, - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT -}; - -void all_sys_pgood_check_reboot(void); -__override_proto void board_chipset_forced_shutdown(void); - -#endif /* __CROS_EC_COMETLAKE_H */ diff --git a/include/power/icelake.h b/include/power/icelake.h deleted file mode 100644 index 08c14718ec..0000000000 --- a/include/power/icelake.h +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Icelake chipset power control module for Chrome EC */ - -#ifndef __CROS_EC_ICELAKE_H -#define __CROS_EC_ICELAKE_H - -#include "stdbool.h" - -/* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) -#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) - -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) - -#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK) - -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED) - -#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED - -#define CHARGER_INITIALIZED_DELAY_MS 100 -#define CHARGER_INITIALIZED_TRIES 40 - -/* Power signals list */ -enum power_signal { - X86_SLP_S0_DEASSERTED, - X86_SLP_S3_DEASSERTED, - X86_SLP_S4_DEASSERTED, - X86_SLP_SUS_DEASSERTED, - X86_RSMRST_L_PGOOD, - X86_DSW_DPWROK, - X86_ALL_SYS_PGOOD, - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT -}; - -struct intel_x86_pwrok_signal { - enum gpio_signal gpio; - bool active_low; - int delay_ms; -}; - -/* - * Ice Lake/Tiger Lake/Jasper Lake PWROK Generation - * - * The following signals are controlled based on the state of the ALL_SYS_PWRGD - * signal - * - * VCCIN enable (input to the VCCIN voltage rail controller) - * VCCST_PWRGD (input to the SoC) - * PCH_PWROK (input to the SoC) - * SYS_PWROK (input to the SoC) - * - * For any the above signals that are controlled by the EC, create an entry - * in the pwrok_signal_assert_list[] and pwrok_signal_deassert_list[] arrays. - * The typical order for asserting the signals is shown above, the deassert - * order is the reverse. - * - * ALL_SYS_PWRGD indicates when all the following are asserted. - * RSMRST_PWRGD & DPWROK - * S4 voltage rails good (DDR) - * VCCST voltage rail good - * S0 voltage rails good - * - * ALL_SYS_PWRGD can be implemented as a single GPIO if the platform power logic - * combines the above power good signals. Otherwise your board can override - * intel_x86_get_pg_ec_all_sys_pwrgd() to check multiple power good signals. - */ -extern const struct intel_x86_pwrok_signal pwrok_signal_assert_list[]; -extern const int pwrok_signal_assert_count; -extern const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[]; -extern const int pwrok_signal_deassert_count; - -#endif /* __CROS_EC_ICELAKE_H */ diff --git a/include/power/intel_x86.h b/include/power/intel_x86.h deleted file mode 100644 index 303db20de7..0000000000 --- a/include/power/intel_x86.h +++ /dev/null @@ -1,105 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel X86 chipset power control module for Chrome EC */ - - -#ifndef __CROS_EC_INTEL_X86_H -#define __CROS_EC_INTEL_X86_H - -#include "espi.h" -#include "power.h" - -/* Chipset specific header files */ -#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) -#include "alderlake_slg4bd44540.h" -/* Geminilake and apollolake use same power sequencing. */ -#elif defined(CONFIG_CHIPSET_APL_GLK) -#include "apollolake.h" -#elif defined(CONFIG_CHIPSET_CANNONLAKE) -#include "cannonlake.h" -#elif defined(CONFIG_CHIPSET_COMETLAKE) -#include "cometlake.h" -#elif defined(CONFIG_CHIPSET_COMETLAKE_DISCRETE) -#include "cometlake-discrete.h" -#elif defined(CONFIG_CHIPSET_ICELAKE) -#include "icelake.h" -#elif defined(CONFIG_CHIPSET_SKYLAKE) -#include "skylake.h" -#endif - -/* GPIO for power signal */ -#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 -#define SLP_S3_SIGNAL_L VW_SLP_S3_L -#else -#define SLP_S3_SIGNAL_L GPIO_PCH_SLP_S3_L -#endif -#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#define SLP_S4_SIGNAL_L VW_SLP_S4_L -#else -#define SLP_S4_SIGNAL_L GPIO_PCH_SLP_S4_L -#endif - -/** - * Handle RSMRST signal. - * - * @param state Current chipset state. - */ -void common_intel_x86_handle_rsmrst(enum power_state state); - -/** - * Force chipset to G3 state. - * - * @return power_state New chipset state. - */ -enum power_state chipset_force_g3(void); - -/** - * Handle power states. - * - * @param state Current chipset state. - * @return power_state New chipset state. - */ -enum power_state common_intel_x86_power_handle_state(enum power_state state); - -/** - * Wait for power-up to be allowed based on available power. - * - * This delays G3->S5 until there is enough power to boot the AP, waiting - * first until the charger (if any) is ready, then for there to be sufficient - * power. - * - * In case of error, the caller should not allow power-up past G3. - * - * @return EC_SUCCESS if OK. - */ -enum ec_error_list intel_x86_wait_power_up_ok(void); - -/** - * Get the value of PG_EC_DSW_PWROK. - * - * The default implementation is just to return the GPIO. But if a - * board doesn't have that GPIO, they may override this function. - */ -__override_proto int intel_x86_get_pg_ec_dsw_pwrok(void); - -/** - * Get the value of PG_EC_ALL_SYS_PWRGD. - * - * The default implementation is just to return the GPIO. But if a - * board doesn't have that GPIO, they may override this function. - */ -__override_proto int intel_x86_get_pg_ec_all_sys_pwrgd(void); - -/** - * Introduces SYS_RESET_L Debounce time delay - * - * The default implementation is to wait for a duration of 32 ms. - * If board needs a different debounce time delay, they may override - * this function - */ -__override_proto void intel_x86_sys_reset_delay(void); - -#endif /* __CROS_EC_INTEL_X86_H */ diff --git a/include/power/mt8192.h b/include/power/mt8192.h deleted file mode 100644 index e0c65c3bcc..0000000000 --- a/include/power/mt8192.h +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_POWER_MT8192_H_ -#define __CROS_EC_POWER_MT8192_H_ - -enum power_signal { - PMIC_PWR_GOOD, - AP_IN_S3_L, - AP_WDT_ASSERTED, - POWER_SIGNAL_COUNT, -}; - -#endif /* __CROS_EC_POWER_MT8192_H_ */ diff --git a/include/power/qcom.h b/include/power/qcom.h deleted file mode 100644 index 5f5247fa87..0000000000 --- a/include/power/qcom.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_POWER_QCOM_H_ -#define __CROS_EC_POWER_QCOM_H_ - -#if defined(CONFIG_CHIPSET_SC7180) || defined(CONFIG_CHIPSET_SC7280) -enum power_signal { - SC7X80_AP_RST_ASSERTED = 0, - SC7X80_PS_HOLD, - SC7X80_POWER_GOOD, - SC7X80_AP_SUSPEND, -#ifdef CONFIG_CHIPSET_SC7180 - SC7X80_WARM_RESET, - SC7X80_DEPRECATED_AP_RST_REQ, -#endif - POWER_SIGNAL_COUNT, -}; -#endif - -/* Swithcap functions */ -void board_set_switchcap_power(int enable); -int board_is_switchcap_enabled(void); -int board_is_switchcap_power_good(void); - -#endif /* __CROS_EC_POWER_QCOM_H_ */ diff --git a/include/power/skylake.h b/include/power/skylake.h deleted file mode 100644 index c8a656c6c5..0000000000 --- a/include/power/skylake.h +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Skylake IMVP8 / ROP PMIC chipset power control module for Chrome EC */ - -#ifndef __CROS_EC_SKYLAKE_H -#define __CROS_EC_SKYLAKE_H - -/* - * Input state flags. - * TODO: Normalize the power signal masks from board defines to SoC headers. - */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) -#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) - -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) - -/* - * DPWROK is NC / stuffing option on initial boards. - * TODO(shawnn): Figure out proper control signals. - */ -#define IN_PGOOD_ALL_CORE 0 - -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED) - -#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED - -#define CHARGER_INITIALIZED_DELAY_MS 100 -#define CHARGER_INITIALIZED_TRIES 40 - -/* Power signals list */ -enum power_signal { -#ifdef CONFIG_POWER_S0IX - X86_SLP_S0_DEASSERTED, -#endif - X86_SLP_S3_DEASSERTED, - X86_SLP_S4_DEASSERTED, - X86_SLP_SUS_DEASSERTED, - X86_RSMRST_L_PWRGD, - X86_PMIC_DPWROK, - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT -}; - -/* - * Board can define this function to indicate to the skylake - * power code that it does not have working reset flags. - */ -int board_has_working_reset_flags(void); - -#endif /* __CROS_EC_SKYLAKE_H */ |