diff options
Diffstat (limited to 'include/spi_nor.h')
| -rw-r--r-- | include/spi_nor.h | 39 |
1 files changed, 19 insertions, 20 deletions
diff --git a/include/spi_nor.h b/include/spi_nor.h index f0c379cd43..9ffe3ebac9 100644 --- a/include/spi_nor.h +++ b/include/spi_nor.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -63,32 +63,32 @@ extern const unsigned int spi_nor_devices_used; /* Industry standard Serial NOR Flash opcodes. All other opcodes are part * specific and require SFDP discovery. */ -#define SPI_NOR_OPCODE_WRITE_STATUS 0x01 /* Write Status Register (1 Byte) */ -#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02 /* Page program */ -#define SPI_NOR_OPCODE_SLOW_READ 0x03 /* Read data (low frequency) */ +#define SPI_NOR_OPCODE_WRITE_STATUS 0x01 /* Write Status Register (1 Byte) */ +#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02 /* Page program */ +#define SPI_NOR_OPCODE_SLOW_READ 0x03 /* Read data (low frequency) */ #define SPI_NOR_OPCODE_WRITE_DISABLE 0x04 -#define SPI_NOR_OPCODE_READ_STATUS 0x05 /* Read Status Register */ -#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06 -#define SPI_NOR_OPCODE_FAST_READ 0x0b /* Read data (high frequency) */ -#define SPI_NOR_OPCODE_SFDP 0x5a /* Read JEDEC SFDP */ -#define SPI_NOR_OPCODE_JEDEC_ID 0x9f /* Read JEDEC ID */ -#define SPI_NOR_OPCODE_WREAR 0xc5 /* Write extended address register */ -#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define SPI_NOR_OPCODE_RDEAR 0xc8 /* Read extended address register */ +#define SPI_NOR_OPCODE_READ_STATUS 0x05 /* Read Status Register */ +#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06 +#define SPI_NOR_OPCODE_FAST_READ 0x0b /* Read data (high frequency) */ +#define SPI_NOR_OPCODE_SFDP 0x5a /* Read JEDEC SFDP */ +#define SPI_NOR_OPCODE_JEDEC_ID 0x9f /* Read JEDEC ID */ +#define SPI_NOR_OPCODE_WREAR 0xc5 /* Write extended address register */ +#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define SPI_NOR_OPCODE_RDEAR 0xc8 /* Read extended address register */ /* Flags for SPI_NOR_OPCODE_READ_STATUS */ -#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */ -#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */ +#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */ +#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */ /* If needed in the future this driver can be extended to discover SFDP * advertised erase sizes and opcodes for SFDP v1.0+. */ -#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20 +#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20 #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_64KIB_ERASE 0xd8 /* If needed in the future this driver can be extended to discover 4B entry and * exit methods for SFDP v1.5+. */ #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_ENTER_4B 0xb7 -#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9 +#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9 /* JEDEC JEP106AR specifies 9 Manufacturer ID banks, read 12 to be sure. */ #define SPI_NOR_JEDEC_ID_BANKS 12 @@ -144,8 +144,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device, * @param data Destination buffer for data. * @return ec_error_list (non-zero on error and timeout). */ -int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, - uint32_t offset, size_t size, uint8_t *data); +int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, uint32_t offset, + size_t size, uint8_t *data); /** * Erase flash on the Serial Flash Device. @@ -181,5 +181,4 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device, int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device, const uint8_t value); - -#endif /* __CROS_EC_SPI_NOR_H */ +#endif /* __CROS_EC_SPI_NOR_H */ |