1 files changed, 0 insertions, 61 deletions
diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg
deleted file mode 100644
index 0ab2b42888..0000000000
--- a/util/openocd/npcx.cfg
+++ /dev/null
@@ -1,61 +0,0 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# nuvoton-m4 devices support both JTAG and SWD transports.
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
-} else {
-   set  _CHIPNAME npcx_ec
-}
-
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
-   set  _WORKAREASIZE $WORKAREASIZE
-} else {
-   set  _WORKAREASIZE 0x8000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x4BA00477
-}
-
-#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position \
-		$_CHIPNAME.cpu -work-area-phys 0x200C0000 \
-		-work-area-size $_WORKAREASIZE
-
-# JTAG speed
-adapter_khz 100
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-# use sysresetreq to perform a system reset
-cortex_m reset_config sysresetreq
-
-#reset configuration
-reset_config trst_and_srst
-
-$_TARGETNAME configure -event reset-start {
-	echo "NPCX Reset..."
-	halt
-	adapter_khz 1000
-}